From 022d650c1c6d14272f4fc6844b7437c7ba826d61 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:47:18 +0800 Subject: [PATCH 01/21] hal_nxp: mcux-sdk-ng: Refine sync_sdk_ng.py Signed-off-by: Zhaoxiang Jin --- mcux/scripts/sync_sdk_ng.py | 43 +++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/mcux/scripts/sync_sdk_ng.py b/mcux/scripts/sync_sdk_ng.py index 6a63378fa..48c576995 100644 --- a/mcux/scripts/sync_sdk_ng.py +++ b/mcux/scripts/sync_sdk_ng.py @@ -12,11 +12,19 @@ def should_ignore(name): name_lower = name.lower() - ignored_names = {'.git', '.gitignore', 'doc', 'docs', 'doxygen', 'Doxygen'} - + # Ignore by exact name (mostly directories and control files) + ignored_names = {'.git', '.gitignore', 'doc', 'docs', 'doxygen'} + # Ignore by file extension (binary/artifact files) + ignored_exts = ('.a', '.o', '.d', '.elf', '.bin', '.hex', '.img', '.lib', + '.dll', '.exe', '.pdb', '.map') + if name_lower in ignored_names: return True - if name_lower.startswith('kconfig') or name_lower == 'kconfig': + # Ignore any Kconfig files/dirs + if name_lower.startswith('kconfig'): + return True + # Ignore known binary/artifact extensions + if name_lower.endswith(ignored_exts): return True return False @@ -125,7 +133,14 @@ def copy_components(src_sdk, dest_root): continue if os.path.isdir(src): - copy_filtered_files(src, dest, skip_empty=True) + # Exclude specific subdirectories when copying certain components + dir_ignore = None + if comp_path == 'conn_fwloader': + # Do not copy the 'script' directory directly under components/conn_fwloader + def dir_ignore(dirname, parent_path, base=src): + return dirname.lower() == 'script' and os.path.abspath(parent_path) == os.path.abspath(base) + + copy_filtered_files(src, dest, dir_ignore_func=dir_ignore, skip_empty=True) else: print(f" Warning: Component is not a directory - {src}") @@ -203,10 +218,10 @@ def main(): parser = argparse.ArgumentParser(description='MCUx SDK SYNC TOOL') parser.add_argument('--mcuxsdk_dir', required=True, help='mcux sdk source dir') parser.add_argument('--copy_module', nargs='*', choices=[ - 'arch', 'drivers', 'components', - 'middleware/usb', 'devices/arch', 'devices/i.MX', - 'devices/Kinetis', 'devices/LPC', 'devices/MCX', - 'devices/RT', 'devices/Wireless', 'cmake_extension' + 'arch', 'devices/arch', 'cmake_extension', + 'drivers', 'components', 'middleware/usb', + 'devices/i.MX', 'devices/Kinetis', 'devices/LPC', + 'devices/MCX', 'devices/RT', 'devices/Wireless', ], help='Please select the module to copy (default sync all modules)') args = parser.parse_args() @@ -216,10 +231,10 @@ def main(): os.makedirs(dest_root, exist_ok=True) all_modules = [ - 'arch', 'drivers', 'components', - 'middleware/usb', 'devices/arch', 'devices/i.MX', - 'devices/Kinetis', 'devices/LPC', 'devices/MCX', - 'devices/RT', 'devices/Wireless', 'cmake_extension' + 'arch', 'devices/arch', 'cmake_extension', + 'drivers', 'components', 'middleware/usb', + 'devices/i.MX', 'devices/Kinetis', 'devices/LPC', + 'devices/MCX', 'devices/RT', 'devices/Wireless', ] selected_modules = args.copy_module if args.copy_module else all_modules @@ -227,11 +242,11 @@ def main(): module_actions = { 'arch': copy_arch, + 'devices/arch': copy_device_arch, + 'cmake_extension': copy_cmake_extension, 'drivers': copy_drivers, 'components': copy_components, 'middleware/usb': copy_middleware_usb, - 'cmake_extension': copy_cmake_extension, - 'devices/arch': copy_device_arch, 'devices/i.MX': partial(copy_device_family, 'i.MX'), 'devices/Kinetis': partial(copy_device_family, 'Kinetis'), 'devices/LPC': partial(copy_device_family, 'LPC'), From e768429d078b5bce9d37b53ef85672a5a275ac23 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:52:58 +0800 Subject: [PATCH 02/21] hal_nxp: mcux-sdk-ng: Update sdk infrastructures to 25.09.00 Signed-off-by: Zhaoxiang Jin --- .../arch/arm/cortexm/core_cm23.cmake | 55 +++++ .../arch/arm/cortexm/core_cm55.cmake | 108 +++++++++ .../arch/arm/cortexm/core_cm85.cmake | 108 +++++++++ .../cmake/extension/basic_settings_lite.cmake | 4 +- .../cmake/extension/function.cmake | 219 ++++++++++++++++-- mcux/mcux-sdk-ng/devices/arm/shared.cmake | 2 +- 6 files changed, 469 insertions(+), 27 deletions(-) create mode 100644 mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm23.cmake create mode 100644 mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm55.cmake create mode 100644 mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm85.cmake diff --git a/mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm23.cmake b/mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm23.cmake new file mode 100644 index 000000000..26573f69c --- /dev/null +++ b/mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm23.cmake @@ -0,0 +1,55 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +# for CM23 with SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm23) + + mcux_add_iar_configuration( + AS "--cpu=cortex-m23.no_se" + CC "--cpu=cortex-m23.no_se" + CX "--cpu=cortex-m23.no_se" + LD "--cpu=cortex-m23.no_se" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m23 --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m23" + CX "-mcpu=cortex-m23" + LD "--cpu=Cortex-M33" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m23" + CC "-mcpu=cortex-m23" + CX "-mcpu=cortex-m23" + LD "-mcpu=cortex-m23" + ) + +endif() + +# for CM23 with DSP but no SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm23_nosau) + + mcux_add_iar_configuration( + AS "--cpu=cortex-m23.no_se" + CC "--cpu=cortex-m23.no_se" + CX "--cpu=cortex-m23.no_se" + LD "--cpu=cortex-m23.no_se" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m23 --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m23" + CX "-mcpu=cortex-m23" + LD "--cpu=Cortex-M33" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m23" + CC "-mcpu=cortex-m23" + CX "-mcpu=cortex-m23" + LD "-mcpu=cortex-m23" + ) + +endif() diff --git a/mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm55.cmake b/mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm55.cmake new file mode 100644 index 000000000..e6bab18ff --- /dev/null +++ b/mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm55.cmake @@ -0,0 +1,108 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +# for CM55 with DSP and SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm55) + + mcux_add_iar_configuration( + AS "--cpu=cortex-m55.no_se" + CC "--cpu=cortex-m55.no_se" + CX "--cpu=cortex-m55.no_se" + LD "--cpu=cortex-m55.no_se" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m55 --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m55" + CX "-mcpu=cortex-m55" + LD "--cpu=Cortex-m55" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m55" + CC "-mcpu=cortex-m55" + CX "-mcpu=cortex-m55" + LD "-mcpu=cortex-m55" + ) + +endif() + +# for CM55 without DSP and SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm55_nodsp_nosau) + + mcux_add_iar_configuration( + AS "--cpu=cortex-m55.no_dsp.no_se" + CC "--cpu=cortex-m55.no_dsp.no_se" + CX "--cpu=cortex-m55.no_dsp.no_se" + LD "--cpu=cortex-m55.no_dsp.no_se" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m55+nodsp --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m55+nodsp" + CX "-mcpu=cortex-m55+nodsp" + LD "--cpu=Cortex-m55.no_dsp" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m55+nodsp" + CC "-mcpu=cortex-m55+nodsp" + CX "-mcpu=cortex-m55+nodsp" + LD "-mcpu=cortex-m55+nodsp" + ) + +endif() + +# for CM55 with DSP but no SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm55_dsp_nosau) + + mcux_add_iar_configuration( + AS "--cpu=cortex-m55.no_se" + CC "--cpu=cortex-m55.no_se" + CX "--cpu=cortex-m55.no_se" + LD "--cpu=cortex-m55.no_se" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m55 --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m55" + CX "-mcpu=cortex-m55" + LD "--cpu=Cortex-m55" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m55" + CC "-mcpu=cortex-m55" + CX "-mcpu=cortex-m55" + LD "-mcpu=cortex-m55" + ) + +endif() + +# for CM55 with no DSP but with SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm55_nodsp_sau) + + mcux_add_iar_configuration( + AS "--cpu=Cortex-m55.no_dsp" + CC "--cpu=Cortex-m55.no_dsp" + CX "--cpu=Cortex-m55.no_dsp" + LD "--cpu=Cortex-m55.no_dsp" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m55+nodsp --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m55+nodsp" + CX "-mcpu=cortex-m55+nodsp" + LD "--cpu=Cortex-m55.no_dsp" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m55+nodsp" + CC "-mcpu=cortex-m55+nodsp" + CX "-mcpu=cortex-m55+nodsp" + LD "-mcpu=cortex-m55+nodsp" + ) + + +endif() diff --git a/mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm85.cmake b/mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm85.cmake new file mode 100644 index 000000000..2c00fefbe --- /dev/null +++ b/mcux/mcux-sdk-ng/arch/arm/cortexm/core_cm85.cmake @@ -0,0 +1,108 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +# for cm85 with DSP and SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm85) + + mcux_add_iar_configuration( + AS "--cpu=cortex-m85.no_se" + CC "--cpu=cortex-m85.no_se" + CX "--cpu=cortex-m85.no_se" + LD "--cpu=cortex-m85.no_se" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m85 --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m85" + CX "-mcpu=cortex-m85" + LD "--cpu=Cortex-m85" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m85" + CC "-mcpu=cortex-m85" + CX "-mcpu=cortex-m85" + LD "-mcpu=cortex-m85" + ) + +endif() + +# for cm85 without DSP and SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm85_nodsp_nosau) + + mcux_add_iar_configuration( + AS "--cpu=cortex-m85.no_dsp.no_se" + CC "--cpu=cortex-m85.no_dsp.no_se" + CX "--cpu=cortex-m85.no_dsp.no_se" + LD "--cpu=cortex-m85.no_dsp.no_se" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m85+nodsp --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m85+nodsp" + CX "-mcpu=cortex-m85+nodsp" + LD "--cpu=Cortex-m85.no_dsp" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m85+nodsp" + CC "-mcpu=cortex-m85+nodsp" + CX "-mcpu=cortex-m85+nodsp" + LD "-mcpu=cortex-m85+nodsp" + ) + +endif() + +# for cm85 with DSP but no SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm85_dsp_nosau) + + mcux_add_iar_configuration( + AS "--cpu=cortex-m85.no_se" + CC "--cpu=cortex-m85.no_se" + CX "--cpu=cortex-m85.no_se" + LD "--cpu=cortex-m85.no_se" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m85 --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m85" + CX "-mcpu=cortex-m85" + LD "--cpu=Cortex-m85" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m85" + CC "-mcpu=cortex-m85" + CX "-mcpu=cortex-m85" + LD "-mcpu=cortex-m85" + ) + +endif() + +# for cm85 with no DSP but with SAU +if (CONFIG_MCUX_PRJSEG_config.arm.core.cm85_nodsp_sau) + + mcux_add_iar_configuration( + AS "--cpu=Cortex-m85.no_dsp" + CC "--cpu=Cortex-m85.no_dsp" + CX "--cpu=Cortex-m85.no_dsp" + LD "--cpu=Cortex-m85.no_dsp" + ) + + mcux_add_mdk_configuration( + AS "-mcpu=cortex-m85+nodsp --target=arm-arm-none-eabi" + CC "-mcpu=cortex-m85+nodsp" + CX "-mcpu=cortex-m85+nodsp" + LD "--cpu=Cortex-m85.no_dsp" + ) + + mcux_add_armgcc_mcux_configuration( + AS "-mcpu=cortex-m85+nodsp" + CC "-mcpu=cortex-m85+nodsp" + CX "-mcpu=cortex-m85+nodsp" + LD "-mcpu=cortex-m85+nodsp" + ) + + +endif() diff --git a/mcux/mcux-sdk-ng/cmake/extension/basic_settings_lite.cmake b/mcux/mcux-sdk-ng/cmake/extension/basic_settings_lite.cmake index 4b0807512..5afc0919f 100644 --- a/mcux/mcux-sdk-ng/cmake/extension/basic_settings_lite.cmake +++ b/mcux/mcux-sdk-ng/cmake/extension/basic_settings_lite.cmake @@ -61,4 +61,6 @@ list( list( APPEND USED_CONFIG_SYMBOLS - CONFIG_TOOLCHAIN) + CONFIG_TOOLCHAIN + MCUXPRESSO_CONFIG_TOOL_MEX_PATH +) diff --git a/mcux/mcux-sdk-ng/cmake/extension/function.cmake b/mcux/mcux-sdk-ng/cmake/extension/function.cmake index 73d833b52..a86515c7d 100644 --- a/mcux/mcux-sdk-ng/cmake/extension/function.cmake +++ b/mcux/mcux-sdk-ng/cmake/extension/function.cmake @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause function(mcux_add_source) @@ -61,19 +61,24 @@ function(mcux_add_source) get_filename_component(directory ${source_abs_path} DIRECTORY) set(files "") - # check if the file_name follow the pattern *.* and ** - string(REGEX MATCH "\\*\\..*" match "${file}") - if (match) + + if ("${file}" MATCHES "\\*\\*\\..*") + # If the file_name follows the pattern **.*, will search the type of files + # recursively in the folder. + file(GLOB_RECURSE files "${directory}/${file}") + elseif ("${file}" MATCHES "\\*\\..*") + # If the file_name follows the pattern *.*, will search the type of files + # in the folder. file(GLOB files "${directory}/${file}") + elseif ("${file}" MATCHES "\\*\\*") + # If the file_name follows the pattern **, will search all types of files + # recursively in the folder. + file(GLOB_RECURSE files "${directory}/*") else () - string(REGEX MATCH "\\*\\*" match "${file}") - if (match) - file(GLOB_RECURSE files "${directory}/*") - else () - # add source_abs_path to list file - list(APPEND files "${source_abs_path}") - endif () + # add source_abs_path to list file + list(APPEND files "${source_abs_path}") endif () + foreach(source_abs_path ${files}) # process config files, project customized config files have higher priority # over component default config files @@ -159,21 +164,28 @@ function(mcux_add_source) if (__PREINCLUDE) set(pre_flag "") + # MCUX-81203: If the build folder's path contains space, need to wrap the include file with quotes + string(FIND "${source_abs_path}" " " space_index) + if(space_index EQUAL -1) + set(pre_include_flag ${source_abs_path}) + else() + set(pre_include_flag \"${source_abs_path}\") + endif() if(${CONFIG_TOOLCHAIN} STREQUAL "iar") - set(pre_flag "--preinclude ${source_abs_path}") - set(as_pre_flag "-P ${source_abs_path}") + set(pre_flag "--preinclude ${pre_include_flag}") + set(as_pre_flag "-P ${pre_include_flag}") elseif(${CONFIG_TOOLCHAIN} STREQUAL "armgcc") - set(pre_flag "-include ${source_abs_path}") + set(pre_flag "-include ${pre_include_flag}") elseif(${CONFIG_TOOLCHAIN} STREQUAL "zephyr") - set(pre_flag "-include ${source_abs_path}") + set(pre_flag "-include ${pre_include_flag}") elseif(${CONFIG_TOOLCHAIN} STREQUAL "mdk") - set(pre_flag "-include ${source_abs_path}") + set(pre_flag "-include ${pre_include_flag}") elseif(${CONFIG_TOOLCHAIN} STREQUAL "xtensa") - set(pre_flag "-include ${source_abs_path}") + set(pre_flag "-include ${pre_include_flag}") elseif(${CONFIG_TOOLCHAIN} STREQUAL "codewarrior") - set(pre_flag "-include ${source_abs_path}") + set(pre_flag "-include ${pre_include_flag}") elseif(${CONFIG_TOOLCHAIN} STREQUAL "riscvllvm") - set(pre_flag "-include ${source_abs_path}") + set(pre_flag "-include ${pre_include_flag}") endif() if (pre_flag) if(__PREINCLUDE_TYPE) @@ -541,7 +553,7 @@ endfunction() function(mcux_convert_binary) set(single_value BINARY TARGET) - set(multi_value TOOLCHAINS EXTRA_ARGS) + set(multi_value TOOLCHAINS EXTRA_ARGS CONVERT_CUSTOM_COMMANDS) cmake_parse_arguments(_ "${options}" "${single_value}" "${multi_value}" ${ARGN}) @@ -579,18 +591,45 @@ function(mcux_convert_binary) log_debug("Convert to binary file ${binary_name}") + if(__CONVERT_CUSTOM_COMMANDS) + add_custom_command( + TARGET ${target_name} + POST_BUILD + ${__CONVERT_CUSTOM_COMMANDS} + ) + return() + endif() + # Get file extension name and set proper OBJDUMP_BIN_CMD get_filename_component(FILE_EXT ${binary_name} EXT) if(${FILE_EXT} STREQUAL ".srec") if (${CONFIG_TOOLCHAIN} STREQUAL "armgcc") set(OBJDUMP_BIN_CMD "-Osrec") + elseif (${CONFIG_TOOLCHAIN} STREQUAL "riscvllvm") + set(OBJDUMP_BIN_CMD "-Osrec") elseif (${CONFIG_TOOLCHAIN} STREQUAL "iar") set(OBJDUMP_BIN_CMD "--srec") elseif (${CONFIG_TOOLCHAIN} STREQUAL "mdk") set(OBJDUMP_BIN_CMD "--m32combined") elseif (${CONFIG_TOOLCHAIN} STREQUAL "codewarrior") set(OBJDUMP_BIN_CMD "-srec") + elseif (${CONFIG_TOOLCHAIN} STREQUAL "xtensa") + set(OBJDUMP_BIN_CMD "-Osrec") endif () + elseif(${FILE_EXT} STREQUAL ".hex") + if (${CONFIG_TOOLCHAIN} STREQUAL "armgcc") + set(OBJDUMP_BIN_CMD "-Oihex") + elseif (${CONFIG_TOOLCHAIN} STREQUAL "riscvllvm") + set(OBJDUMP_BIN_CMD "-Oihex") + elseif (${CONFIG_TOOLCHAIN} STREQUAL "iar") + set(OBJDUMP_BIN_CMD "--ihex") + elseif (${CONFIG_TOOLCHAIN} STREQUAL "mdk") + set(OBJDUMP_BIN_CMD "--i32combined") + elseif (${CONFIG_TOOLCHAIN} STREQUAL "codewarrior") + log_debug("Codewarrior does not support hex format, use bin instead" ${CMAKE_CURRENT_LIST_FILE}) + elseif (${CONFIG_TOOLCHAIN} STREQUAL "xtensa") + set(OBJDUMP_BIN_CMD "-Oihex") + endif() endif() if (${CONFIG_TOOLCHAIN} STREQUAL "codewarrior") if(NOT __EXTRA_ARGS) @@ -1150,8 +1189,26 @@ function(mcux_add_riscvllvm_linker_script) endif() endfunction() +macro(_mcux_get_binary_path binary_path path relative_path) + # Check if path is on a different drive by looking for drive letter pattern (e.g., "D:/") + if(CMAKE_HOST_SYSTEM_NAME STREQUAL "Windows") + string(REGEX MATCH "^([A-Za-z]:)" path_drive "${path}") + string(REGEX MATCH "^([A-Za-z]:)" sdk_drive "${SdkRootDirPath}") + if(path_drive AND sdk_drive AND NOT "${path_drive}" STREQUAL "${sdk_drive}") + set(${binary_path} "${path}") + else() + get_filename_component(${binary_path} "${APPLICATION_BINARY_DIR}/${relative_path}" ABSOLUTE) + endif() + else() + # On non-Windows platforms, always use the relative path + get_filename_component(${binary_path} "${APPLICATION_BINARY_DIR}/${relative_path}" ABSOLUTE) + endif() +endmacro() + function(mcux_add_cmakelists path) set(add_cmakelist 0) + # Convert path to CMake standard path (forward slashes) + file(TO_CMAKE_PATH "${path}" path) set(cmakelist_path ${path}/CMakeLists.txt) file(RELATIVE_PATH relative_path ${SdkRootDirPath} ${path}) @@ -1162,13 +1219,13 @@ function(mcux_add_cmakelists path) if(ARGC EQUAL 1) set(add_cmakelist 1) - get_filename_component(binary_path "${APPLICATION_BINARY_DIR}/${relative_path}" ABSOLUTE) + _mcux_get_binary_path(binary_path "${path}" "${relative_path}") elseif(ARGC EQUAL 2) string(TOUPPER ${ARGV1} ARGV1) if(${ARGV1} STREQUAL OPTIONAL) if(EXISTS ${cmakelist_path}) set(add_cmakelist 1) - get_filename_component(binary_path "${APPLICATION_BINARY_DIR}/${relative_path}" ABSOLUTE) + _mcux_get_binary_path(binary_path "${path}" "${relative_path}") else() log_debug("No CMakeLists.txt in ${path}" ${CMAKE_CURRENT_LIST_FILE}) endif() @@ -1597,12 +1654,40 @@ endfunction() function(mcux_project_remove_source) set(single_value BASE_PATH) - set(multi_value SOURCES) + set(multi_value SOURCES ${MCUX_SOURCE_CONDITION}) cmake_parse_arguments(_ "${options}" "${single_value}" "${multi_value}" ${ARGN}) # remove sources foreach(item ${__SOURCES}) + foreach(cond ${MCUX_SOURCE_CONDITION}) + if(__${cond}) + + list(FIND MCUX_SOURCE_CONDITION ${cond} INDEX) + + if(${INDEX} GREATER -1) + + list(GET CMAKE_CONDITION ${INDEX} _cmake_cond) + + if(_cmake_cond IN_LIST LIST_CMAKE_CONDITION) + set(condition_meet 0) + foreach(cmake_condition_item ${${_cmake_cond}}) + if(cmake_condition_item IN_LIST __${cond}) + set(condition_meet 1) + endif() + endforeach() + if(NOT condition_meet) + return() + endif() + elseif(NOT ${${_cmake_cond}} IN_LIST __${cond}) + return() + endif() + endif() + + endif() + + endforeach() + if(__BASE_PATH) set(source_abs_path ${__BASE_PATH}/${item}) else() @@ -1638,12 +1723,39 @@ endfunction() function(mcux_project_remove_include) set(single_value BASE_PATH) - set(multi_value INCLUDES) + set(multi_value INCLUDES ${MCUX_SOURCE_CONDITION}) cmake_parse_arguments(_ "${options}" "${single_value}" "${multi_value}" ${ARGN}) # remove includes foreach(item ${__INCLUDES}) + foreach(cond ${MCUX_SOURCE_CONDITION}) + if(__${cond}) + + list(FIND MCUX_SOURCE_CONDITION ${cond} INDEX) + + if(${INDEX} GREATER -1) + + list(GET CMAKE_CONDITION ${INDEX} _cmake_cond) + + if(_cmake_cond IN_LIST LIST_CMAKE_CONDITION) + set(condition_meet 0) + foreach(cmake_condition_item ${${_cmake_cond}}) + if(cmake_condition_item IN_LIST __${cond}) + set(condition_meet 1) + endif() + endforeach() + if(NOT condition_meet) + return() + endif() + elseif(NOT ${${_cmake_cond}} IN_LIST __${cond}) + return() + endif() + endif() + + endif() + endforeach() + set(include_abs_path "") if(__BASE_PATH) @@ -1776,6 +1888,10 @@ function(mcux_load_sysbuild_config) endif() foreach(name ${sysbuild_variable_names}) + # SB_CONF_FILE is used for sysbuild only, no need to be set for sub projects + if("${name}" MATCHES "SB_CONF_FILE") + continue() + endif() # For main app, all variables are valid, for other apps, only those with # prefix is valid if(SYSBUILD_MAIN_APP) @@ -2540,4 +2656,57 @@ function(_get_subfolder_file OUTPUT_VAR CURRENT_DIR PATTERN LEVEL) endif () endforeach () -endfunction() \ No newline at end of file +endfunction() + +function(mcux_add_config_mex_path) + set(single_value BASE_PATH PATH) + set(multi_value) + cmake_parse_arguments(_ "${options}" "${single_value}" "${multi_value}" ${ARGN}) + + # Validate that PATH is provided + if(NOT __PATH) + log_error("PATH parameter is required for mcux_add_config_mex_path" ${CMAKE_CURRENT_LIST_FILE}) + return() + endif() + + # Resolve directory path + if(__BASE_PATH) + set(dir_abs_path ${__BASE_PATH}/${__PATH}) + else() + set(dir_abs_path ${CMAKE_CURRENT_LIST_DIR}/${__PATH}) + endif() + + file(TO_CMAKE_PATH ${dir_abs_path} dir_abs_path) + get_filename_component(dir_abs_path ${dir_abs_path} ABSOLUTE) + + if(NOT IS_DIRECTORY ${dir_abs_path}) + if(DEFINED MCUXPRESSO_CONFIG_TOOL_MEX_PATH) + unset(MCUXPRESSO_CONFIG_TOOL_MEX_PATH CACHE) + log_debug("Cleared MCUXPRESSO_CONFIG_TOOL_MEX_PATH (not a directory)" ${CMAKE_CURRENT_LIST_FILE}) + log_warn("Config MEX directory ${dir_abs_path} does not exist or is not a directory" ${CMAKE_CURRENT_LIST_FILE}) + endif() + return() + endif() + + # Non-recursive search for *.mex in the given directory + file(GLOB mex_files "${dir_abs_path}/*.mex") + + list(LENGTH mex_files mex_count) + if(mex_count EQUAL 0) + log_error("No .mex file found in ${dir_abs_path}" ${CMAKE_CURRENT_LIST_FILE}) + return() + endif() + + list(GET mex_files 0 mex_file) + if(mex_count GREATER 1) + log_warn("Multiple .mex files found in ${dir_abs_path}" ${CMAKE_CURRENT_LIST_FILE}) + endif() + + # Re-configure when mex changes in this directory + set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${mex_files}) + + # Set cache var to the directory that contains the .mex file + get_filename_component(mex_dir "${mex_file}" DIRECTORY) + set(MCUXPRESSO_CONFIG_TOOL_MEX_PATH "${mex_dir}" CACHE STRING "Directory containing the MEX file consumed by MCUXpresso Config Tool" FORCE) + log_debug("Set MCUXPRESSO_CONFIG_TOOL_MEX_PATH ${mex_dir}" ${CMAKE_CURRENT_LIST_FILE}) +endfunction() diff --git a/mcux/mcux-sdk-ng/devices/arm/shared.cmake b/mcux/mcux-sdk-ng/devices/arm/shared.cmake index e5101047c..08a7735c6 100644 --- a/mcux/mcux-sdk-ng/devices/arm/shared.cmake +++ b/mcux/mcux-sdk-ng/devices/arm/shared.cmake @@ -1,5 +1,5 @@ -if(CONFIG_CPU_CORTEX_M) # core related +if(CONFIG_CPU_CORTEX_M) include(${SdkRootDirPath}/arch/arm/cortexm/core_${CONFIG_MCUX_HW_CORE}.cmake) include(${SdkRootDirPath}/arch/arm/cortexm/core_${CONFIG_MCUX_HW_FPU_TYPE}.cmake) include(${SdkRootDirPath}/arch/arm/cortexm/cpu_define.cmake) From b9dafb13e74f7bc4b3490d1c2beb35d0079a0c09 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:07:44 +0800 Subject: [PATCH 03/21] hal_nxp: mcux-sdk-ng: Update drivers to SDK 25.09.00 Update drivers to SDK 25.09.00 Signed-off-by: Zhaoxiang Jin --- mcux/mcux-sdk-ng/drivers/asrc/fsl_asrc.c | 46 + .../mcux-sdk-ng/drivers/audmix/CMakeLists.txt | 12 + mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.c | 625 +++++++ mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.h | 346 ++++ .../drivers/cache/armv8-a/CMakeLists.txt | 3 +- .../drivers/cache/armv8-a/fsl_cache.c | 1 - .../drivers/cache/armv8-a/fsl_cache.h | 1 - mcux/mcux-sdk-ng/drivers/ce/CMakeLists.txt | 4 +- .../drivers/ce/firmware/ce_kw47_mcxw72.txt | 1134 ++++++++++++ mcux/mcux-sdk-ng/drivers/ce/fsl_ce.c | 25 +- mcux/mcux-sdk-ng/drivers/ce/fsl_ce.h | 30 +- mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.c | 43 +- mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.h | 37 +- mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.c | 169 +- mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.h | 121 +- mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.c | 29 +- mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.h | 23 +- mcux/mcux-sdk-ng/drivers/ce/fsl_ce_if.h | 65 +- mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.c | 358 ++-- mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.h | 323 ++-- .../mcux-sdk-ng/drivers/ce/fsl_ce_transform.c | 113 +- .../mcux-sdk-ng/drivers/ce/fsl_ce_transform.h | 90 +- .../mcux-sdk-ng/drivers/cmu_fc/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.c | 6 +- mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.h | 2 +- .../mcux-sdk-ng/drivers/cmu_fm/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.c | 2 +- mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.h | 5 +- .../mcux-sdk-ng/drivers/common/CMakeLists.txt | 1 + mcux/mcux-sdk-ng/drivers/common/fsl_common.h | 1 + mcux/mcux-sdk-ng/drivers/csi/fsl_csi.c | 6 +- mcux/mcux-sdk-ng/drivers/dac12/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.c | 10 +- mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.h | 7 +- mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.c | 4 +- mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.h | 8 +- mcux/mcux-sdk-ng/drivers/dma3/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.c | 26 +- mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.h | 2 +- mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.c | 27 +- mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.h | 2 +- mcux/mcux-sdk-ng/drivers/dmic/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.c | 5 +- mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.h | 4 +- mcux/mcux-sdk-ng/drivers/dpu_1/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.c | 71 +- mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.h | 153 +- mcux/mcux-sdk-ng/drivers/easrc/fsl_asrc.c | 1 - mcux/mcux-sdk-ng/drivers/ecat/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.c | 18 +- mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.h | 4 +- mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c | 23 + mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h | 2 +- mcux/mcux-sdk-ng/drivers/eim/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/eim/fsl_eim.c | 29 +- mcux/mcux-sdk-ng/drivers/eim/fsl_eim.h | 5 +- .../drivers/endat3/endat3_mem_defs.h | 7 +- mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.c | 285 +-- mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.h | 196 ++- mcux/mcux-sdk-ng/drivers/enet/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/enet/fsl_enet.c | 4 +- mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h | 15 +- .../drivers/enet_qos/CMakeLists.txt | 2 +- .../drivers/enet_qos/fsl_enet_qos.c | 56 +- .../drivers/enet_qos/fsl_enet_qos.h | 196 ++- mcux/mcux-sdk-ng/drivers/erm/fsl_erm.c | 13 +- mcux/mcux-sdk-ng/drivers/erm/fsl_erm.h | 9 +- mcux/mcux-sdk-ng/drivers/flash/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/flash/fsl_flash.h | 2 +- .../drivers/flash/fsl_ftfx_adapter.h | 8 +- .../drivers/flash/fsl_ftfx_cache.c | 2 +- .../drivers/flash/fsl_ftfx_cache.h | 2 +- .../drivers/flash/fsl_ftfx_controller.c | 71 +- .../drivers/flash/fsl_ftfx_controller.h | 62 +- .../drivers/flash/fsl_ftfx_features.h | 2 +- .../drivers/flash/fsl_ftfx_flash.c | 4 +- .../drivers/flash/fsl_ftfx_flash.h | 4 +- .../drivers/flash/fsl_ftfx_flexnvm.c | 16 +- .../drivers/flash/fsl_ftfx_flexnvm.h | 28 +- .../drivers/flash/fsl_ftfx_utilities.h | 2 +- .../drivers/flash_c40/fsl_c40_flash.c | 35 +- .../drivers/flash_c40/fsl_c40_flash.h | 2 +- .../drivers/flash_k4/CMakeLists.txt | 4 +- .../drivers/flash_k4/fsl_k4_controller.c | 269 ++- .../drivers/flash_k4/fsl_k4_controller.h | 50 + .../drivers/flash_k4/fsl_k4_flash.c | 120 +- .../drivers/flash_k4/fsl_k4_flash.h | 10 +- .../drivers/flexcan/CMakeLists.txt | 4 +- .../mcux-sdk-ng/drivers/flexcan/fsl_flexcan.c | 19 +- .../mcux-sdk-ng/drivers/flexcan/fsl_flexcan.h | 2 +- .../drivers/flexcan/fsl_flexcan_edma.c | 4 +- .../drivers/flexcan/fsl_flexcan_edma.h | 2 +- .../drivers/flexcomm/spi/CMakeLists.txt | 4 +- .../drivers/flexcomm/spi/fsl_spi_dma.c | 677 ++++---- .../drivers/flexcomm/spi/fsl_spi_dma.h | 27 +- .../drivers/flexio/i2c/CMakeLists.txt | 2 +- .../flexio/i2c/fsl_flexio_i2c_master.c | 19 +- .../flexio/i2c/fsl_flexio_i2c_master.h | 6 +- .../drivers/flexio/mculcd/CMakeLists.txt | 2 +- .../drivers/flexio/mculcd/fsl_flexio_mculcd.c | 3 + .../flexio/mculcd/fsl_flexio_mculcd_edma.c | 4 + .../mculcd/fsl_flexio_mculcd_smartdma.c | 17 +- .../mculcd/fsl_flexio_mculcd_smartdma.h | 2 +- .../drivers/flexio/spi/CMakeLists.txt | 2 +- .../drivers/flexio/spi/fsl_flexio_spi.h | 6 +- .../drivers/flexio/uart/CMakeLists.txt | 2 +- .../drivers/flexio/uart/fsl_flexio_uart.c | 1 + .../drivers/flexio/uart/fsl_flexio_uart.h | 8 +- .../drivers/flexspi/CMakeLists.txt | 2 +- .../mcux-sdk-ng/drivers/flexspi/fsl_flexspi.c | 132 +- .../mcux-sdk-ng/drivers/flexspi/fsl_flexspi.h | 22 +- .../drivers/flexspi_flr/fsl_flexspi_flr.c | 153 +- .../drivers/flexspi_flr/fsl_flexspi_flr.h | 348 ++-- mcux/mcux-sdk-ng/drivers/ftm/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.c | 68 + mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.h | 21 +- mcux/mcux-sdk-ng/drivers/gpio/fsl_gpio.h | 2 +- mcux/mcux-sdk-ng/drivers/gpt/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/gpt/fsl_gpt.h | 4 +- .../drivers/hashcrypt/CMakeLists.txt | 4 +- .../drivers/hashcrypt/fsl_hashcrypt.c | 2 +- .../drivers/hashcrypt/fsl_hashcrypt.h | 8 +- mcux/mcux-sdk-ng/drivers/i3c/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.c | 17 + mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.h | 15 +- mcux/mcux-sdk-ng/drivers/imu/fsl_imu.c | 12 +- .../drivers/irqsteer/CMakeLists.txt | 2 +- .../drivers/irqsteer/fsl_irqsteer.c | 26 +- .../drivers/irqsteer/fsl_irqsteer.h | 12 +- .../drivers/irqsteer_1/CMakeLists.txt | 4 +- .../drivers/irqsteer_1/fsl_irqsteer.h | 4 +- mcux/mcux-sdk-ng/drivers/irtc/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.c | 17 +- mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.h | 4 +- mcux/mcux-sdk-ng/drivers/lcdic/fsl_lcdic.c | 5 +- .../mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.c | 112 +- .../mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.h | 17 +- mcux/mcux-sdk-ng/drivers/lin/fsl_lin.c | 5 +- mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.c | 25 +- mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.h | 2 +- .../mcux-sdk-ng/drivers/lpacmp/CMakeLists.txt | 12 + mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.c | 141 ++ mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.h | 357 ++++ mcux/mcux-sdk-ng/drivers/lpadc/fsl_lpadc.c | 5 +- mcux/mcux-sdk-ng/drivers/lpc_lcdc/fsl_lcdc.c | 2 +- .../drivers/lpflexcomm/lpspi/CMakeLists.txt | 2 +- .../drivers/lpflexcomm/lpspi/fsl_lpspi.c | 3 +- .../drivers/lpflexcomm/lpspi/fsl_lpspi.h | 2 +- .../drivers/lpflexcomm/lpuart/CMakeLists.txt | 2 +- .../drivers/lpflexcomm/lpuart/fsl_lpuart.c | 31 +- .../drivers/lpflexcomm/lpuart/fsl_lpuart.h | 2 +- mcux/mcux-sdk-ng/drivers/lpi2c/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.c | 29 +- mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.h | 6 +- mcux/mcux-sdk-ng/drivers/lpit/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.c | 8 +- mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.h | 2 +- mcux/mcux-sdk-ng/drivers/lpspi/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.c | 42 +- mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.h | 8 +- .../drivers/lpspi/fsl_lpspi_edma.c | 77 +- .../drivers/lpspi/fsl_lpspi_edma.h | 2 +- mcux/mcux-sdk-ng/drivers/lptmr/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.c | 39 +- mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.h | 9 +- .../mcux-sdk-ng/drivers/lpuart/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.c | 324 ++-- mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.h | 13 +- .../drivers/mailbox/CMakeLists.txt | 4 +- .../mcux-sdk-ng/drivers/mailbox/fsl_mailbox.h | 120 +- mcux/mcux-sdk-ng/drivers/mau/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/mau/fsl_mau.c | 12 + mcux/mcux-sdk-ng/drivers/mau/fsl_mau.h | 2 +- .../drivers/mcx_spc/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.c | 10 +- mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.h | 12 +- .../drivers/mipi_dsi/CMakeLists.txt | 4 +- .../drivers/mipi_dsi/fsl_mipi_dsi.c | 12 +- .../drivers/mipi_dsi/fsl_mipi_dsi.h | 6 +- .../drivers/mipi_dsi_imx/CMakeLists.txt | 2 +- .../drivers/mipi_dsi_imx/fsl_mipi_dsi.c | 8 +- .../drivers/mipi_dsi_imx/fsl_mipi_dsi.h | 4 +- .../drivers/mipi_dsi_split/CMakeLists.txt | 4 +- .../drivers/mipi_dsi_split/fsl_mipi_dsi.c | 55 +- .../drivers/mipi_dsi_split/fsl_mipi_dsi.h | 28 +- mcux/mcux-sdk-ng/drivers/mu/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/mu/fsl_mu.c | 278 ++- mcux/mcux-sdk-ng/drivers/mu/fsl_mu.h | 139 +- mcux/mcux-sdk-ng/drivers/mu1/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.c | 165 +- mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.h | 128 +- mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h | 24 +- .../drivers/netc/fsl_netc_endpoint.c | 13 +- mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c | 28 +- mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h | 9 + .../drivers/netc/fsl_netc_switch.c | 7 +- .../drivers/netc/fsl_netc_switch.h | 13 + .../drivers/netc/netc_hw/fsl_netc_hw.c | 4 +- .../drivers/netc/netc_hw/fsl_netc_hw_si.h | 2 +- .../drivers/ostimer/CMakeLists.txt | 2 +- .../mcux-sdk-ng/drivers/ostimer/fsl_ostimer.c | 31 +- .../mcux-sdk-ng/drivers/ostimer/fsl_ostimer.h | 57 +- mcux/mcux-sdk-ng/drivers/pdm/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.c | 59 +- mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.h | 2 +- .../drivers/pls_pmu/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/pls_pmu/fsl_pmu.h | 12 +- mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.c | 8 +- mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.h | 4 +- mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.c | 55 +- mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.h | 8 +- mcux/mcux-sdk-ng/drivers/qspi/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.c | 32 +- mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.h | 120 +- .../drivers/qspi/socs/mcxe31b/fsl_qspi_soc.c | 14 +- .../mcux-sdk-ng/drivers/qtmr_1/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.c | 44 +- mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.h | 48 +- .../drivers/rdc_sema42/CMakeLists.txt | 4 +- .../drivers/rdc_sema42/fsl_rdc_sema42.c | 5 +- .../drivers/rdc_sema42/fsl_rdc_sema42.h | 4 +- mcux/mcux-sdk-ng/drivers/rtc/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.c | 46 +- mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.h | 63 +- .../drivers/rtc_analog/CMakeLists.txt | 12 + mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.c | 1534 +++++++++++++++++ mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.h | 681 ++++++++ mcux/mcux-sdk-ng/drivers/sai/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/sai/fsl_sai.c | 152 +- mcux/mcux-sdk-ng/drivers/sai/fsl_sai.h | 26 +- .../mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c | 30 +- mcux/mcux-sdk-ng/drivers/sema4/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.c | 2 +- mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.h | 6 +- .../mcux-sdk-ng/drivers/sema42/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.c | 10 +- mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.h | 2 +- mcux/mcux-sdk-ng/drivers/sfa/fsl_sfa.c | 6 +- mcux/mcux-sdk-ng/drivers/slcd/fsl_slcd.c | 2 +- .../mcux-sdk-ng/drivers/slcd_split/fsl_slcd.c | 4 +- .../drivers/smartdma/CMakeLists.txt | 4 +- .../drivers/smartdma/fsl_smartdma.h | 19 +- .../drivers/smartdma/fsl_smartdma_mcxa.c | 11 +- .../drivers/smartdma/fsl_smartdma_mcxn.c | 16 +- .../drivers/smartdma/fsl_smartdma_rt500.c | 5 + mcux/mcux-sdk-ng/drivers/smm/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/smm/fsl_smm.c | 2 +- mcux/mcux-sdk-ng/drivers/smm/fsl_smm.h | 264 ++- mcux/mcux-sdk-ng/drivers/spc/CMakeLists.txt | 6 +- mcux/mcux-sdk-ng/drivers/spc/fsl_spc.c | 148 +- mcux/mcux-sdk-ng/drivers/spc/fsl_spc.h | 246 ++- mcux/mcux-sdk-ng/drivers/sramc/CMakeLists.txt | 12 + mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.c | 184 ++ mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.h | 194 +++ mcux/mcux-sdk-ng/drivers/stm/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/stm/fsl_stm.c | 2 +- mcux/mcux-sdk-ng/drivers/stm/fsl_stm.h | 2 +- mcux/mcux-sdk-ng/drivers/tpm/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.c | 167 +- mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.h | 103 +- mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.c | 21 +- mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.h | 10 +- mcux/mcux-sdk-ng/drivers/trng/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/trng/fsl_trng.c | 45 +- mcux/mcux-sdk-ng/drivers/trng/fsl_trng.h | 6 +- .../drivers/tsi/tsi_v5/CMakeLists.txt | 4 +- .../drivers/tsi/tsi_v5/fsl_tsi_v5.c | 4 +- .../drivers/tsi/tsi_v6/CMakeLists.txt | 4 +- .../drivers/tsi/tsi_v6/fsl_tsi_v6.h | 28 +- mcux/mcux-sdk-ng/drivers/tspc/fsl_tspc.h | 2 +- mcux/mcux-sdk-ng/drivers/tstmr/CMakeLists.txt | 5 +- mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.c | 137 ++ mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.h | 48 +- mcux/mcux-sdk-ng/drivers/usdhc/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.c | 9 + .../mcux-sdk-ng/drivers/wdog32/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.c | 10 +- mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.h | 6 +- mcux/mcux-sdk-ng/drivers/wwdt/CMakeLists.txt | 4 +- mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.c | 6 +- mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.h | 4 +- 283 files changed, 11684 insertions(+), 2812 deletions(-) create mode 100644 mcux/mcux-sdk-ng/drivers/audmix/CMakeLists.txt create mode 100644 mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.c create mode 100644 mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.h create mode 100644 mcux/mcux-sdk-ng/drivers/ce/firmware/ce_kw47_mcxw72.txt create mode 100644 mcux/mcux-sdk-ng/drivers/lpacmp/CMakeLists.txt create mode 100644 mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.c create mode 100644 mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.h create mode 100644 mcux/mcux-sdk-ng/drivers/rtc_analog/CMakeLists.txt create mode 100644 mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.c create mode 100644 mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.h create mode 100644 mcux/mcux-sdk-ng/drivers/sramc/CMakeLists.txt create mode 100644 mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.c create mode 100644 mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.h create mode 100644 mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.c diff --git a/mcux/mcux-sdk-ng/drivers/asrc/fsl_asrc.c b/mcux/mcux-sdk-ng/drivers/asrc/fsl_asrc.c index adf3afa3f..34972325f 100644 --- a/mcux/mcux-sdk-ng/drivers/asrc/fsl_asrc.c +++ b/mcux/mcux-sdk-ng/drivers/asrc/fsl_asrc.c @@ -1077,3 +1077,49 @@ void ASRC_DriverIRQHandler(void) SDK_ISR_EXIT_BARRIER; } #endif /* ASRC */ + +#if defined ASRC1 +void ASRC1_DriverIRQHandler(void); +void ASRC1_DriverIRQHandler(void) +{ + /* channel PAIR A interrupt handling*/ + if ((ASRC1->ASRSTR & (uint32_t)kASRC_StatusPairAInterrupt) != 0U) + { + s_asrcIsr(ASRC1, s_asrcHandle[0][0U]); + } + /* channel PAIR B interrupt handling*/ + if ((ASRC1->ASRSTR & (uint32_t)kASRC_StatusPairBInterrupt) != 0U) + { + s_asrcIsr(ASRC1, s_asrcHandle[0][1U]); + } + /* channel PAIR C interrupt handling*/ + if ((ASRC1->ASRSTR & (uint32_t)kASRC_StatusPairCInterrupt) != 0U) + { + s_asrcIsr(ASRC1, s_asrcHandle[0][2U]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ASRC1 */ + +#if defined ASRC2 +void ASRC2_DriverIRQHandler(void); +void ASRC2_DriverIRQHandler(void) +{ + /* channel PAIR A interrupt handling*/ + if ((ASRC2->ASRSTR & (uint32_t)kASRC_StatusPairAInterrupt) != 0U) + { + s_asrcIsr(ASRC2, s_asrcHandle[1][0U]); + } + /* channel PAIR B interrupt handling*/ + if ((ASRC2->ASRSTR & (uint32_t)kASRC_StatusPairBInterrupt) != 0U) + { + s_asrcIsr(ASRC2, s_asrcHandle[1][1U]); + } + /* channel PAIR C interrupt handling*/ + if ((ASRC2->ASRSTR & (uint32_t)kASRC_StatusPairCInterrupt) != 0U) + { + s_asrcIsr(ASRC2, s_asrcHandle[1][2U]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ASRC2 */ diff --git a/mcux/mcux-sdk-ng/drivers/audmix/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/audmix/CMakeLists.txt new file mode 100644 index 000000000..99518606b --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/audmix/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +if(CONFIG_MCUX_COMPONENT_driver.audmix) + mcux_component_version(1.0.0) + + mcux_add_source(SOURCES fsl_audmix.h fsl_audmix.c) + + mcux_add_include(INCLUDES .) + +endif() diff --git a/mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.c b/mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.c new file mode 100644 index 000000000..17d503158 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.c @@ -0,0 +1,625 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_audmix.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.audmix" +#endif + +/* Maximum values for AUDMIX parameters to prevent overflow */ +#define AUDMIX_MAX_STEP_DIVIDER 0xFFFU +#define AUDMIX_MAX_INITIAL_VALUE 0x3FFFFU +#define AUDMIX_MAX_STEP_FACTOR 0x3FFFFU +#define AUDMIX_MAX_STEP_TARGET 0x3FFFFU + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Initializes the AUDMIX peripheral. + * + * This API gates the AUDMIX clock. The AUDMIX module can't operate unless AUDMIX_Init is called to enable the clock. + * + * @param base AUDMIX base pointer. + */ +void AUDMIX_Init(WAKEUP_AUDMIX_Type *base) +{ + /* Prevent compiler warning about unused parameter */ + (void)base; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Audmix); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief De-initializes the AUDMIX peripheral. + * + * This API gates the AUDMIX clock. The AUDMIX module can't operate unless AUDMIX_Init + * is called to enable the clock. + * + * @param base AUDMIX base pointer. + */ +void AUDMIX_Deinit(WAKEUP_AUDMIX_Type *base) +{ + /* Prevent compiler warning about unused parameter */ + (void)base; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Audmix); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the AUDMIX configuration structure to default values. + * + * @param config Pointer to the configuration structure. + * @return Status of the operation + */ +status_t AUDMIX_GetDefaultConfig(audmix_config_t *config) +{ + if (config == NULL) + { + return kStatus_AUDMIX_Error; + } + + /* Initialize the config structure with default values */ + config->outputSource = kAUDMIX_OutputDisabled; + config->mixClockSource = kAUDMIX_MixClockFromTDM1; + config->outputWidth = kAUDMIX_OutputWidth16Bit; + config->outputClockPolarity = kAUDMIX_OutputClockPolarityPositiveEdge; + config->maskFrameRateDiffError = false; + config->maskClockFrequencyDiffError = false; + config->syncModeEnable = false; + config->syncModeClockSource = kAUDMIX_MixClockFromTDM1; + + return kStatus_Success; +} + +/*! + * @brief Sets the AUDMIX configuration. + * + * @param base AUDMIX base pointer. + * @param config Pointer to the configuration structure. + * @return Status of the operation + */ +status_t AUDMIX_SetConfig(WAKEUP_AUDMIX_Type *base, const audmix_config_t *config) +{ + if (base == NULL || config == NULL) + { + return kStatus_AUDMIX_Error; + } + + uint32_t reg = 0U; + uint32_t mixClockSource = (uint32_t)config->mixClockSource & 0x1U; + uint32_t outputSource = (uint32_t)config->outputSource & 0x3U; + uint32_t outputWidth = (uint32_t)config->outputWidth & 0x7U; + uint32_t outputClockPolarity = (uint32_t)config->outputClockPolarity & 0x1U; + uint32_t syncModeClockSource = (uint32_t)config->syncModeClockSource & 0x1U; + + /* Configure CTR register */ + reg = WAKEUP_AUDMIX_CTR_MIXCLK(mixClockSource) | + WAKEUP_AUDMIX_CTR_OUTSRC(outputSource) | + WAKEUP_AUDMIX_CTR_OUTWIDTH(outputWidth) | + WAKEUP_AUDMIX_CTR_OUTCKPOL(outputClockPolarity); + + if (config->maskFrameRateDiffError) + { + reg |= WAKEUP_AUDMIX_CTR_MASKRTDF_MASK; + } + + if (config->maskClockFrequencyDiffError) + { + reg |= WAKEUP_AUDMIX_CTR_MASKCKDF_MASK; + } + + if (config->syncModeEnable) + { + reg |= WAKEUP_AUDMIX_CTR_SYNCMODE_MASK; + } + + reg |= WAKEUP_AUDMIX_CTR_SYNCSRC(syncModeClockSource); + + base->CTR = reg; + + return kStatus_Success; +} + +/*! + * @brief Gets the default attenuation configuration structure. + * + * This function initializes the AUDMIX attenuation configuration structure to default values. + * + * @param config Pointer to the attenuation configuration structure. + * @return Status of the operation + */ +status_t AUDMIX_GetDefaultAttenuationConfig(audmix_attenuation_config_t *config) +{ + if (config == NULL) + { + return kStatus_AUDMIX_Error; + } + + /* Initialize the attenuation config structure with default values */ + config->attenuationEnable = false; + config->attenuationDirection = kAUDMIX_AttenuationDirectionDown; + config->stepDivider = 0U; + config->initialValue = 0x3FFFFU; /* Default initial value (0.999996185) */ + config->stepUpFactor = 0x2AAAAU; /* Default step up factor (0.666664124) */ + config->stepDownFactor = 0x30000U; /* Default step down factor (0.75) */ + config->stepTarget = 16U; /* Default step target */ + + return kStatus_Success; +} + +/*! + * @brief Sets the attenuation configuration for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param config Pointer to the attenuation configuration structure. + * @return Status of the operation + */ +/* Improve integer handling in AUDMIX_SetAttenuationConfig */ +status_t AUDMIX_SetAttenuationConfig(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, const audmix_attenuation_config_t *config) +{ + if (base == NULL || config == NULL) + { + return kStatus_AUDMIX_Error; + } + + /* More explicit bounds checking */ + if (tdmChannel != 0U && tdmChannel != 1U) + { + return kStatus_AUDMIX_Error; + } + + uint32_t atcr = 0U; + /* Safe type conversion with explicit masking */ + uint32_t attenuationDirection = ((uint32_t)config->attenuationDirection) & 0x1U; + + /* Safe integer handling with explicit bounds checking */ + uint32_t stepDivider = (config->stepDivider <= AUDMIX_MAX_STEP_DIVIDER) ? + (uint32_t)config->stepDivider : AUDMIX_MAX_STEP_DIVIDER; + + uint32_t initialValue = (config->initialValue <= AUDMIX_MAX_INITIAL_VALUE) ? + config->initialValue : AUDMIX_MAX_INITIAL_VALUE; + + uint32_t stepUpFactor = (config->stepUpFactor <= AUDMIX_MAX_STEP_FACTOR) ? + config->stepUpFactor : AUDMIX_MAX_STEP_FACTOR; + + uint32_t stepDownFactor = (config->stepDownFactor <= AUDMIX_MAX_STEP_FACTOR) ? + config->stepDownFactor : AUDMIX_MAX_STEP_FACTOR; + + uint32_t stepTarget = (config->stepTarget <= AUDMIX_MAX_STEP_TARGET) ? + config->stepTarget : AUDMIX_MAX_STEP_TARGET; + + /* Configure attenuation control register with safe operations */ + atcr = WAKEUP_AUDMIX_ATCR0_AT_EN(config->attenuationEnable ? 1U : 0U) | + WAKEUP_AUDMIX_ATCR0_AT_UPDN(attenuationDirection) | + WAKEUP_AUDMIX_ATCR0_ATSTPDIV(stepDivider); + + /* Set the attenuation registers based on the TDM channel */ + if (tdmChannel == 0U) + { + base->ATCR0 = atcr; + base->ATIVAL0 = initialValue & WAKEUP_AUDMIX_ATIVAL0_ATINTVAL_MASK; + base->ATSTPUP0 = stepUpFactor & WAKEUP_AUDMIX_ATSTPUP0_ATSTEPUP_MASK; + base->ATSTPDN0 = stepDownFactor & WAKEUP_AUDMIX_ATSTPDN0_ATSTEPDN_MASK; + base->ATSTPTGT0 = stepTarget & WAKEUP_AUDMIX_ATSTPTGT0_ATSTPTG_MASK; + } + else /* tdmChannel == 1U (already validated) */ + { + base->ATCR1 = atcr; + base->ATIVAL1 = initialValue & WAKEUP_AUDMIX_ATIVAL1_ATINTVAL_MASK; + base->ATSTPUP1 = stepUpFactor & WAKEUP_AUDMIX_ATSTPUP1_ATSTEPUP_MASK; + base->ATSTPDN1 = stepDownFactor & WAKEUP_AUDMIX_ATSTPDN1_ATSTEPDN_MASK; + base->ATSTPTGT1 = stepTarget & WAKEUP_AUDMIX_ATSTPTGT1_ATSTPTG_MASK; + } + + return kStatus_Success; +} + + +/*! + * @brief Enables or disables attenuation for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param enable true to enable, false to disable. + * @return Status of the operation + */ +status_t AUDMIX_EnableAttenuation(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, bool enable) +{ + if (base == NULL || tdmChannel > 1U) + { + return kStatus_AUDMIX_Error; + } + + if (tdmChannel == 0U) + { + if (enable) + { + base->ATCR0 |= WAKEUP_AUDMIX_ATCR0_AT_EN_MASK; + } + else + { + base->ATCR0 &= ~WAKEUP_AUDMIX_ATCR0_AT_EN_MASK; + } + } + else + { + if (enable) + { + base->ATCR1 |= WAKEUP_AUDMIX_ATCR1_AT_EN_MASK; + } + else + { + base->ATCR1 &= ~WAKEUP_AUDMIX_ATCR1_AT_EN_MASK; + } + } + + return kStatus_Success; +} + +/*! + * @brief Sets the attenuation direction for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param direction Attenuation direction (up or down). + * @return Status of the operation + */ +status_t AUDMIX_SetAttenuationDirection(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, audmix_attenuation_direction_t direction) +{ + if (base == NULL || tdmChannel > 1U) + { + return kStatus_AUDMIX_Error; + } + + uint32_t directionValue = (uint32_t)direction & 0x1U; + + if (tdmChannel == 0U) + { + uint32_t reg = base->ATCR0; + reg &= ~WAKEUP_AUDMIX_ATCR0_AT_UPDN_MASK; + reg |= WAKEUP_AUDMIX_ATCR0_AT_UPDN(directionValue); + base->ATCR0 = reg; + } + else + { + uint32_t reg = base->ATCR1; + reg &= ~WAKEUP_AUDMIX_ATCR1_AT_UPDN_MASK; + reg |= WAKEUP_AUDMIX_ATCR1_AT_UPDN(directionValue); + base->ATCR1 = reg; + } + + return kStatus_Success; +} + +/*! + * @brief Checks if the frame rates of TDM1 and TDM2 are matched. + * + * @param base AUDMIX base pointer. + * @return true if frame rates match, false if they don't match. + */ +bool AUDMIX_IsFrameRateMatched(WAKEUP_AUDMIX_Type *base) +{ + if (base == NULL) + { + return false; + } + + return ((base->STR & WAKEUP_AUDMIX_STR_RATEDIFF_MASK) == 0U); +} + +/*! + * @brief Checks if the clock frequencies of TDM1 and TDM2 are matched. + * + * @param base AUDMIX base pointer. + * @return true if clock frequencies match, false if they don't match. + */ +bool AUDMIX_IsClockFrequencyMatched(WAKEUP_AUDMIX_Type *base) +{ + if (base == NULL) + { + return false; + } + + return ((base->STR & WAKEUP_AUDMIX_STR_CLKDIFF_MASK) == 0U); +} + +/*! + * @brief Gets the current mixer state. + * + * @param base AUDMIX base pointer. + * @return Current mixer state (disabled, TDM1, TDM2, or mixed). + */ +audmix_output_source_t AUDMIX_GetMixerState(WAKEUP_AUDMIX_Type *base) +{ + if (base == NULL) + { + return kAUDMIX_OutputDisabled; + } + + uint32_t status = (base->STR & WAKEUP_AUDMIX_STR_MIXSTAT_MASK) >> WAKEUP_AUDMIX_STR_MIXSTAT_SHIFT; + return (audmix_output_source_t)status; +} + +/*! + * @brief Sets the output source for the AUDMIX. + * + * @param base AUDMIX base pointer. + * @param source Output source (disabled, TDM1, TDM2, or mixed). + * @return Status of the operation + */ +status_t AUDMIX_SetOutputSource(WAKEUP_AUDMIX_Type *base, audmix_output_source_t source) +{ + if (base == NULL) + { + return kStatus_AUDMIX_Error; + } + + uint32_t reg = base->CTR; + reg &= ~WAKEUP_AUDMIX_CTR_OUTSRC_MASK; + reg |= WAKEUP_AUDMIX_CTR_OUTSRC((uint32_t)source & 0x3U); + base->CTR = reg; + + return kStatus_Success; +} + +/*! + * @brief Sets the mixing clock source for the AUDMIX. + * + * @param base AUDMIX base pointer. + * @param source Mixing clock source (TDM1 or TDM2). + * @return Status of the operation + */ +status_t AUDMIX_SetMixClockSource(WAKEUP_AUDMIX_Type *base, audmix_mix_clock_source_t source) +{ + if (base == NULL) + { + return kStatus_AUDMIX_Error; + } + + uint32_t reg = base->CTR; + reg &= ~WAKEUP_AUDMIX_CTR_MIXCLK_MASK; + reg |= WAKEUP_AUDMIX_CTR_MIXCLK((uint32_t)source & 0x1U); + base->CTR = reg; + + return kStatus_Success; +} + +/*! + * @brief Gets the current attenuation value for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param value Pointer to store the attenuation value. + * @return Status of the operation + */ +status_t AUDMIX_GetAttenuationValue(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, uint32_t *value) +{ + if (base == NULL || value == NULL || tdmChannel > 1U) + { + return kStatus_AUDMIX_Error; + } + + if (tdmChannel == 0U) + { + *value = (base->ATTNVAL0 & WAKEUP_AUDMIX_ATTNVAL0_ATCURVAL_MASK) >> WAKEUP_AUDMIX_ATTNVAL0_ATCURVAL_SHIFT; + } + else + { + *value = (base->ATTNVAL1 & WAKEUP_AUDMIX_ATTNVAL1_ATCURVAL_MASK) >> WAKEUP_AUDMIX_ATTNVAL1_ATCURVAL_SHIFT; + } + + return kStatus_Success; +} + +/*! + * @brief Gets the current attenuation step counter for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param counter Pointer to store the step counter value. + * @return Status of the operation + */ +status_t AUDMIX_GetAttenuationStepCounter(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, uint32_t *counter) +{ + if (base == NULL || counter == NULL || tdmChannel > 1U) + { + return kStatus_AUDMIX_Error; + } + + if (tdmChannel == 0U) + { + *counter = (base->ATSTP0 & WAKEUP_AUDMIX_ATSTP0_STPCTR_MASK) >> WAKEUP_AUDMIX_ATSTP0_STPCTR_SHIFT; + } + else + { + *counter = (base->ATSTP1 & WAKEUP_AUDMIX_ATSTP1_STPCTR_MASK) >> WAKEUP_AUDMIX_ATSTP1_STPCTR_SHIFT; + } + + return kStatus_Success; +} + +/*! + * @brief Sets the output width for the AUDMIX. + * + * @param base AUDMIX base pointer. + * @param width Output width (16-bit, 18-bit, 20-bit, or 24-bit). + * @return Status of the operation + */ +status_t AUDMIX_SetOutputWidth(WAKEUP_AUDMIX_Type *base, audmix_output_width_t width) +{ + if (base == NULL) + { + return kStatus_AUDMIX_Error; + } + + uint32_t reg = base->CTR; + reg &= ~WAKEUP_AUDMIX_CTR_OUTWIDTH_MASK; + reg |= WAKEUP_AUDMIX_CTR_OUTWIDTH((uint32_t)width & 0x7U); + base->CTR = reg; + + return kStatus_Success; +} + +/*! + * @brief Sets the output clock polarity for the AUDMIX. + * + * @param base AUDMIX base pointer. + * @param polarity Output clock polarity (positive or negative edge). + * @return Status of the operation + */ +status_t AUDMIX_SetOutputClockPolarity(WAKEUP_AUDMIX_Type *base, audmix_output_clock_polarity_t polarity) +{ + if (base == NULL) + { + return kStatus_AUDMIX_Error; + } + + uint32_t reg = base->CTR; + reg &= ~WAKEUP_AUDMIX_CTR_OUTCKPOL_MASK; + reg |= WAKEUP_AUDMIX_CTR_OUTCKPOL((uint32_t)polarity & 0x1U); + base->CTR = reg; + + return kStatus_Success; +} + +/*! + * @brief Enables or disables the frame rate difference error masking. + * + * @param base AUDMIX base pointer. + * @param enable true to enable masking, false to disable masking. + * @return Status of the operation + */ +status_t AUDMIX_EnableFrameRateDiffErrorMasking(WAKEUP_AUDMIX_Type *base, bool enable) +{ + if (base == NULL) + { + return kStatus_AUDMIX_Error; + } + + uint32_t reg = base->CTR; + + if (enable) + { + reg |= WAKEUP_AUDMIX_CTR_MASKRTDF_MASK; + } + else + { + reg &= ~WAKEUP_AUDMIX_CTR_MASKRTDF_MASK; + } + + base->CTR = reg; + + return kStatus_Success; +} + +/*! + * @brief Enables or disables the clock frequency difference error masking. + * + * @param base AUDMIX base pointer. + * @param enable true to enable masking, false to disable masking. + * @return Status of the operation + */ +status_t AUDMIX_EnableClockFrequencyDiffErrorMasking(WAKEUP_AUDMIX_Type *base, bool enable) +{ + if (base == NULL) + { + return kStatus_AUDMIX_Error; + } + + uint32_t reg = base->CTR; + + if (enable) + { + reg |= WAKEUP_AUDMIX_CTR_MASKCKDF_MASK; + } + else + { + reg &= ~WAKEUP_AUDMIX_CTR_MASKCKDF_MASK; + } + + base->CTR = reg; + + return kStatus_Success; +} + +/*! + * @brief Enables or disables the sync mode. + * + * @param base AUDMIX base pointer. + * @param enable true to enable sync mode, false to disable sync mode. + * @return Status of the operation + */ +status_t AUDMIX_EnableSyncMode(WAKEUP_AUDMIX_Type *base, bool enable) +{ + if (base == NULL) + { + return kStatus_AUDMIX_Error; + } + + uint32_t reg = base->CTR; + + if (enable) + { + reg |= WAKEUP_AUDMIX_CTR_SYNCMODE_MASK; + } + else + { + reg &= ~WAKEUP_AUDMIX_CTR_SYNCMODE_MASK; + } + + base->CTR = reg; + + return kStatus_Success; +} + +/*! + * @brief Sets the sync mode clock source. + * + * @param base AUDMIX base pointer. + * @param source Sync mode clock source (TDM1 or TDM2). + * @return Status of the operation + */ +status_t AUDMIX_SetSyncModeClockSource(WAKEUP_AUDMIX_Type *base, audmix_mix_clock_source_t source) +{ + if (base == NULL) + { + return kStatus_AUDMIX_Error; + } + + uint32_t reg = base->CTR; + reg &= ~WAKEUP_AUDMIX_CTR_SYNCSRC_MASK; + reg |= WAKEUP_AUDMIX_CTR_SYNCSRC((uint32_t)source & 0x1U); + base->CTR = reg; + + return kStatus_Success; +} + diff --git a/mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.h b/mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.h new file mode 100644 index 000000000..e2fe9d487 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/audmix/fsl_audmix.h @@ -0,0 +1,346 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_AUDMIX_H_ +#define FSL_AUDMIX_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup audmix_driver AUDMIX Driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +#define FSL_AUDMIX_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) /*!< Version 1.0.0 */ +/*! @} */ + +/*! @brief _audmix_status_t, AUDMIX return status.*/ +enum +{ + kStatus_AUDMIX_Busy = MAKE_STATUS(kStatusGroup_AUDMIX, 0), /*!< AUDMIX is busy */ + kStatus_AUDMIX_Error = MAKE_STATUS(kStatusGroup_AUDMIX, 1), /*!< AUDMIX error occurred */ +}; + +/*! @brief AUDMIX output source selection */ +typedef enum _audmix_output_source +{ + kAUDMIX_OutputDisabled = 0U, /*!< Output is disabled */ + kAUDMIX_OutputFromTDM1 = 1U, /*!< Output from TDM1 */ + kAUDMIX_OutputFromTDM2 = 2U, /*!< Output from TDM2 */ + kAUDMIX_OutputMixed = 3U, /*!< Output is mixed from TDM1 and TDM2 */ +} audmix_output_source_t; + +/*! @brief AUDMIX mixing clock source selection */ +typedef enum _audmix_mix_clock_source +{ + kAUDMIX_MixClockFromTDM1 = 0U, /*!< Mix clock from TDM1 interface */ + kAUDMIX_MixClockFromTDM2 = 1U, /*!< Mix clock from TDM2 interface */ +} audmix_mix_clock_source_t; + +/*! @brief AUDMIX output audio sample width */ +typedef enum _audmix_output_width +{ + kAUDMIX_OutputWidth16Bit = 0U, /*!< 16-bit output width */ + kAUDMIX_OutputWidth18Bit = 1U, /*!< 18-bit output width */ + kAUDMIX_OutputWidth20Bit = 2U, /*!< 20-bit output width */ + kAUDMIX_OutputWidth24Bit = 3U, /*!< 24-bit output width */ +} audmix_output_width_t; + +/*! @brief AUDMIX output bit clock polarity */ +typedef enum _audmix_output_clock_polarity +{ + kAUDMIX_OutputClockPolarityPositiveEdge = 0U, /*!< Output data driven on positive edge */ + kAUDMIX_OutputClockPolarityNegativeEdge = 1U, /*!< Output data driven on negative edge */ +} audmix_output_clock_polarity_t; + +/*! @brief AUDMIX attenuation direction */ +typedef enum _audmix_attenuation_direction +{ + kAUDMIX_AttenuationDirectionDown = 0U, /*!< Downward attenuation (increasing attenuation) */ + kAUDMIX_AttenuationDirectionUp = 1U, /*!< Upward attenuation (decreasing attenuation) */ +} audmix_attenuation_direction_t; + +/*! @brief AUDMIX configuration structure */ +typedef struct _audmix_config +{ + audmix_output_source_t outputSource; /*!< Output source selection */ + audmix_mix_clock_source_t mixClockSource; /*!< Mix clock source selection */ + audmix_output_width_t outputWidth; /*!< Output audio sample width */ + audmix_output_clock_polarity_t outputClockPolarity; /*!< Output bit clock polarity */ + bool maskFrameRateDiffError; /*!< Mask frame rate difference error */ + bool maskClockFrequencyDiffError; /*!< Mask clock frequency difference error */ + bool syncModeEnable; /*!< Enable sync mode */ + audmix_mix_clock_source_t syncModeClockSource; /*!< Sync mode clock source */ +} audmix_config_t; + +/*! @brief AUDMIX attenuation configuration structure */ +typedef struct _audmix_attenuation_config +{ + bool attenuationEnable; /*!< Enable attenuation */ + audmix_attenuation_direction_t attenuationDirection; /*!< Attenuation direction */ + uint16_t stepDivider; /*!< Step divider value (0-4095) */ + uint32_t initialValue; /*!< Initial attenuation value (18-bit) */ + uint32_t stepUpFactor; /*!< Step up factor (18-bit) */ + uint32_t stepDownFactor; /*!< Step down factor (18-bit) */ + uint32_t stepTarget; /*!< Step target value (18-bit) */ +} audmix_attenuation_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the AUDMIX peripheral. + * + * This API gates the AUDMIX clock. The AUDMIX module can't operate unless AUDMIX_Init is called to enable the clock. + * + * @param base AUDMIX base pointer. + */ +void AUDMIX_Init(WAKEUP_AUDMIX_Type *base); + +/*! + * @brief De-initializes the AUDMIX peripheral. + * + * This API gates the AUDMIX clock. The AUDMIX module can't operate unless AUDMIX_Init + * is called to enable the clock. + * + * @param base AUDMIX base pointer. + */ +void AUDMIX_Deinit(WAKEUP_AUDMIX_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the AUDMIX configuration structure to default values. + * + * @param config Pointer to the configuration structure. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_GetDefaultConfig(audmix_config_t *config); + +/*! + * @brief Sets the AUDMIX configuration. + * + * @param base AUDMIX base pointer. + * @param config Pointer to the configuration structure. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_SetConfig(WAKEUP_AUDMIX_Type *base, const audmix_config_t *config); + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the AUDMIX status flags. + * + * @param base AUDMIX base pointer. + * @return Status flags. Use the defined AUDMIX_STR_* masks to get the status value. + * Returns 0 if base is NULL. + */ +uint32_t AUDMIX_GetStatusFlags(WAKEUP_AUDMIX_Type *base); + +/*! + * @brief Checks if frame rates between TDM1 and TDM2 are matched. + * + * @param base AUDMIX base pointer. + * @return true if frame rates match, false if mismatch or if base is NULL. + */ +bool AUDMIX_IsFrameRateMatched(WAKEUP_AUDMIX_Type *base); + +/*! + * @brief Checks if bit clock frequencies between TDM1 and TDM2 are matched. + * + * @param base AUDMIX base pointer. + * @return true if bit clock frequencies match, false if mismatch or if base is NULL. + */ +bool AUDMIX_IsClockFrequencyMatched(WAKEUP_AUDMIX_Type *base); + +/*! + * @brief Gets the current mixer state. + * + * @param base AUDMIX base pointer. + * @return Current mixer state (disabled, TDM1, TDM2, or mixed). + * Returns kAUDMIX_OutputDisabled if base is NULL. + */ +audmix_output_source_t AUDMIX_GetMixerState(WAKEUP_AUDMIX_Type *base); + +/*! @} */ + +/*! + * @name Attenuation Control + * @{ + */ + +/*! + * @brief Gets the default attenuation configuration structure. + * + * This function initializes the AUDMIX attenuation configuration structure to default values. + * + * @param config Pointer to the attenuation configuration structure. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_GetDefaultAttenuationConfig(audmix_attenuation_config_t *config); + +/*! + * @brief Sets the attenuation configuration for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param config Pointer to the attenuation configuration structure. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + * Failure occurs if base or config is NULL, or if tdmChannel is not 0 or 1. + */ +status_t AUDMIX_SetAttenuationConfig(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, const audmix_attenuation_config_t *config); + +/*! + * @brief Enables or disables attenuation for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param enable true to enable, false to disable. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_EnableAttenuation(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, bool enable); + +/*! + * @brief Sets the attenuation direction for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param direction Attenuation direction (up or down). + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_SetAttenuationDirection(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, audmix_attenuation_direction_t direction); + +/*! + * @brief Gets the current attenuation value for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param value Pointer to store the attenuation value. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_GetAttenuationValue(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, uint32_t *value); + +/*! + * @brief Gets the current attenuation step counter for a specific TDM channel. + * + * @param base AUDMIX base pointer. + * @param tdmChannel TDM channel (0 for TDM1, 1 for TDM2). + * @param counter Pointer to store the step counter value. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_GetAttenuationStepCounter(WAKEUP_AUDMIX_Type *base, uint8_t tdmChannel, uint32_t *counter); + +/*! @} */ + +/*! + * @name Output Control + * @{ + */ + +/*! + * @brief Sets the output source. + * + * @param base AUDMIX base pointer. + * @param source Output source selection. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_SetOutputSource(WAKEUP_AUDMIX_Type *base, audmix_output_source_t source); + +/*! + * @brief Sets the mixing clock source. + * + * @param base AUDMIX base pointer. + * @param source Mix clock source selection. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_SetMixClockSource(WAKEUP_AUDMIX_Type *base, audmix_mix_clock_source_t source); + +/*! + * @brief Sets the output audio sample width. + * + * @param base AUDMIX base pointer. + * @param width Output audio sample width. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_SetOutputWidth(WAKEUP_AUDMIX_Type *base, audmix_output_width_t width); + +/*! + * @brief Sets the output bit clock polarity. + * + * @param base AUDMIX base pointer. + * @param polarity Output bit clock polarity. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_SetOutputClockPolarity(WAKEUP_AUDMIX_Type *base, audmix_output_clock_polarity_t polarity); + +/*! + * @brief Enables or disables the frame rate difference error masking. + * + * @param base AUDMIX base pointer. + * @param enable true to enable masking, false to disable masking. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_EnableFrameRateDiffErrorMasking(WAKEUP_AUDMIX_Type *base, bool enable); + +/*! + * @brief Enables or disables the clock frequency difference error masking. + * + * @param base AUDMIX base pointer. + * @param enable true to enable masking, false to disable masking. + * + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_EnableClockFrequencyDiffErrorMasking(WAKEUP_AUDMIX_Type *base, bool enable); + +/*! + * @brief Enables or disables the sync mode. + * + * @param base AUDMIX base pointer. + * @param enable true to enable sync mode, false to disable sync mode. + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_EnableSyncMode(WAKEUP_AUDMIX_Type *base, bool enable); + +/*! + * @brief Sets the sync mode clock source. + * + * @param base AUDMIX base pointer. + * @param source Sync mode clock source (TDM1 or TDM2). + * @return Returns status code. kStatus_Success on success, kStatus_AUDMIX_Error on failure. + */ +status_t AUDMIX_SetSyncModeClockSource(WAKEUP_AUDMIX_Type *base, audmix_mix_clock_source_t source); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* FSL_AUDMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/drivers/cache/armv8-a/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/cache/armv8-a/CMakeLists.txt index ba85cc1ad..e159acaa8 100644 --- a/mcux/mcux-sdk-ng/drivers/cache/armv8-a/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/cache/armv8-a/CMakeLists.txt @@ -1,8 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.cache_armv8_a) + mcux_component_version(2.0.0) mcux_add_source(SOURCES fsl_cache.c fsl_cache.h) diff --git a/mcux/mcux-sdk-ng/drivers/cache/armv8-a/fsl_cache.c b/mcux/mcux-sdk-ng/drivers/cache/armv8-a/fsl_cache.c index 3bb038eeb..c13b606c3 100644 --- a/mcux/mcux-sdk-ng/drivers/cache/armv8-a/fsl_cache.c +++ b/mcux/mcux-sdk-ng/drivers/cache/armv8-a/fsl_cache.c @@ -1,6 +1,5 @@ /* * Copyright 2022 NXP - * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/mcux/mcux-sdk-ng/drivers/cache/armv8-a/fsl_cache.h b/mcux/mcux-sdk-ng/drivers/cache/armv8-a/fsl_cache.h index 0ecab0ba6..bfafc2a09 100644 --- a/mcux/mcux-sdk-ng/drivers/cache/armv8-a/fsl_cache.h +++ b/mcux/mcux-sdk-ng/drivers/cache/armv8-a/fsl_cache.h @@ -1,6 +1,5 @@ /* * Copyright 2022 NXP - * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/mcux/mcux-sdk-ng/drivers/ce/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/ce/CMakeLists.txt index db92f43d1..f304caa20 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/ce/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.ce) - mcux_component_version(2.1.1) + mcux_component_version(2.3.3) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/drivers/ce/firmware/ce_kw47_mcxw72.txt b/mcux/mcux-sdk-ng/drivers/ce/firmware/ce_kw47_mcxw72.txt new file mode 100644 index 000000000..83062a076 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/ce/firmware/ce_kw47_mcxw72.txt @@ -0,0 +1,1134 @@ +0xEF, 0x00, 0x00, 0x08, 0xEF, 0x00, 0x80, 0x12, 0xEF, 0x00, 0x40, 0x12, 0xEF, 0x00, 0x00, 0x0F, +0xEF, 0x00, 0xC0, 0x11, 0xEF, 0x00, 0x80, 0x11, 0xEF, 0x00, 0x40, 0x11, 0xEF, 0x00, 0xC0, 0x0E, +0xEF, 0x00, 0xC0, 0x10, 0xEF, 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Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -18,6 +18,11 @@ Implementation file for CE wrapper/driver functions on ARM #define FSL_COMPONENT_ID "platform.drivers.ce" #endif +/*! + * brief Initializes the CE. + * + * param [in] ceCopyImage The information about the CE image to copy. + */ void CE_Init(ce_copy_image_t *ceCopyImage) { #if (defined(KW47_core0_SERIES) || defined(MCXW72_core0_SERIES)) @@ -30,6 +35,11 @@ void CE_Init(ce_copy_image_t *ceCopyImage) CE_InitWithoutFirmware(); #if (defined(KW47_core0_SERIES) || defined(MCXW72_core0_SERIES)) + /* + * $Branch Coverage Justification$ + * The CE images released in the SDK use the STCM6 as the stack and the STCM7 as the data RAM. + * In this case, the CE core cannot boot from the STCM6 and STCM7. + */ switch (ceCopyImage->destAddr) { case CE_STCM5_BASE: @@ -48,6 +58,11 @@ void CE_Init(ce_copy_image_t *ceCopyImage) #endif } +/*! + * brief Installs CE firmware by given image info + * + * param [in] ceCopyImage The information about the CE image to copy. + */ void CE_InstallFirmware(ce_copy_image_t *ceCopyImage) { #if (defined(KW47_core0_SERIES) || defined(MCXW72_core0_SERIES)) @@ -64,10 +79,16 @@ void CE_InstallFirmware(ce_copy_image_t *ceCopyImage) srcAddr = ceCopyImage->srcAddr; size = ceCopyImage->size; - memcpy((void *)(uint32_t *)dstAddr, (const void *)(uint32_t *)srcAddr, size); + (void)memcpy((void *)(uint32_t *)dstAddr, (const void *)(uint32_t *)srcAddr, size); #endif } +/*! + * brief Initializes the CE. + * + * details This function is similar to CE_Init, but it does not install + * the firmware, the firmware can be installed using CE_InstallFirmware. + */ void CE_InitWithoutFirmware(void) { CLOCK_EnableClock(kCLOCK_DSP0); diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce.h b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce.h index 341aad80c..b11d104fc 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce.h +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce.h @@ -18,13 +18,16 @@ Functional API definitions for ARM drivers for CE #include "fsl_ce_transform.h" /*! - * @defgroup ce Computer Engine (CE) Driver + * @ingroup ce + * @defgroup ce_init CE Initialization Functions + * @brief Functional API definitions for CE initialization functions. + * @{ */ /*! @name Driver version */ /*! @{ */ /*! @brief CE driver version. */ -#define FSL_CE_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +#define FSL_CE_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) /*! @} */ /*! @@ -47,30 +50,33 @@ extern "C" { #endif /*! - * @brief Initialize the CE. + * @brief Initializes the CE. * - * @param ceCopyImage The information about the CE image to copy. + * @param [in] ceCopyImage The information about the CE image to copy. */ void CE_Init(ce_copy_image_t *ceCopyImage); /*! - * @brief Initialize the CE. + * @brief Installs CE firmware by given image info * - * This function is similar with CE_Init, the difference is this function - * does not install the firmware, the firmware could be installed using - * CE_InstallFirmware. + * @param [in] ceCopyImage The information about the CE image to copy. */ -void CE_InitWithoutFirmware(void); +void CE_InstallFirmware(ce_copy_image_t *ceCopyImage); /*! - * @brief install CE firmware by given image info + * @brief Initializes the CE. * - * @param ceCopyImage The information about the CE image to copy. + * @details This function is similar to CE_Init, but it does not install + * the firmware, the firmware can be installed using CE_InstallFirmware. */ -void CE_InstallFirmware(ce_copy_image_t *ceCopyImage); +void CE_InitWithoutFirmware(void); #if defined(__cplusplus) } #endif +/*! + * @} + */ + #endif /*FSL_CE_H*/ diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.c b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.c index bcafb9d07..2ef38f805 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.c +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.c @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -12,15 +12,31 @@ Implementation file for CE wrapper/driver functions on ARM #include "fsl_ce_basic.h" #include "fsl_ce_cmd.h" -int CE_ExecCmd() +/*! + * brief Executes commands in the command queue. + * + * return Command execution status. + */ +int32_t CE_ExecCmd(void) { - int status = CE_CmdLaunch(1); + int32_t status = CE_CmdLaunch(1); + return status; } -int CE_NullCmd() +/*! + * brief Sends a basic command to verify that ZV2117 is operational + * and that the command interface is functioning properly. + * + * details This function passes through the command processing interface + * and returns a success status. + * + * return Command execution status. + */ +int32_t CE_NullCmd(void) { - int status; + int32_t status; + ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 0; cmdstruct.n_param_args = 0; @@ -35,9 +51,22 @@ int CE_NullCmd() return status; } -int CE_Copy(int *pDst, int *pSrc, const int N) +/*! + * brief Copies data between buffers in the ZV2117 memory section. + * + * details Copies a specified number of 32-bit words from the source + * to the destination buffer. Both buffers must reside in the ZV2117 + * data memory section. + * + * param [out] pDst Pointer to destination buffer + * param [in] pSrc Pointer to source buffer + * param [in] N Number of 32-bit words to copy + * + * return Command execution status. + */ +int32_t CE_Copy(int32_t *pDst, int32_t *pSrc, const int32_t N) { - int status; + int32_t status; ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 2; diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.h b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.h index 0cac2e0d2..58a6f4cb3 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.h +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_basic.h @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -34,32 +34,37 @@ extern "C" { #endif /*! - * @brief Execute command in command queue - * - * @return Return 0 if succeeded, otherwise return error code. + * @brief Executes commands in the command queue. + * + * @return Command execution status. */ -int CE_ExecCmd(); +int32_t CE_ExecCmd(void); /*! - * @brief Simple echo test cmd + * @brief Sends a basic command to verify that ZV2117 is operational + * and that the command interface is functioning properly. * - * @return Return 0 if succeeded, otherwise return error code. + * @details This function passes through the command processing interface + * and returns a success status. + * + * @return Command execution status. */ -int CE_NullCmd(); +int32_t CE_NullCmd(void); /*! - * @brief Copies one memory buffer to another + * @brief Copies data between buffers in the ZV2117 memory section. * - * Copies one memory buffer to another. Copy is in units of words. Any data type - * can be used. + * @details Copies a specified number of 32-bit words from the source + * to the destination buffer. Both buffers must reside in the ZV2117 + * data memory section. * - * @param pDst Pointer to destination buffer - * @param pSrc Pointer to source buffer - * @param N Number of words to copy + * @param [out] pDst Pointer to destination buffer + * @param [in] pSrc Pointer to source buffer + * @param [in] N Number of 32-bit words to copy * - * @return Return 0 if succeeded, otherwise return error code. + * @return Command execution status. */ -int CE_Copy(int *pDst, int *pSrc, const int N); +int32_t CE_Copy(int32_t *pDst, int32_t *pSrc, const int32_t N); #ifdef __cplusplus } diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.c b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.c index b8fcb33df..d20677a75 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.c +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.c @@ -23,29 +23,58 @@ static ce_cmdbuffer_t *s_ce_cmdbuffer; #define NOP16 NOP4 NOP4 NOP4 NOP4 #define NOP32 NOP16 NOP16 +/*! + * brief Inserts a small delay using a NOP instruction. + */ static inline void CE_CmdDelay(void) { NOP32 } -int CE_CmdInitBuffer(ce_cmdbuffer_t *psCmdBuffer, +/*! + * brief Initializes the CM33-ZV2117 command buffer. + * details This function must to be called once after power-up or reset, + * or when the command queue mode needs to be changed. Once configured, + * the command mode remains unchanged till reset or re-initialization. + * + * param [out] psCmdBuffer Pointer to the command buffer structure. + * Must be allocated in ARM memory (not ZV2117). + * param [in] cmdbuffer Command buffer. Must be 256 words in ZV2117 data memory. + * param [in] statusbuffer Status buffer. Must be 134 words in ZV2117 data memory. + * param [in] cmdmode Command mode. One of: + * - ref kCE_CmdModeOneNonBlocking + * - ref kCE_CmdModeMultipleNonBlocking + * - ref kCE_CmdModeOneBlocking + * - ref kCE_CmdModeMultipleBlocking + * + * retval 0 Initialization is successful. + */ +int32_t CE_CmdInitBuffer(ce_cmdbuffer_t *psCmdBuffer, volatile uint32_t cmdbuffer[], - volatile uint32_t statusbuffer[], + volatile int32_t statusbuffer[], ce_cmd_mode_t cmdmode) { s_ce_cmdbuffer = psCmdBuffer; s_ce_cmdbuffer->cmdmode = cmdmode; - s_ce_cmdbuffer->buffer_base_ptr = (unsigned int *)cmdbuffer; - s_ce_cmdbuffer->status_buffer_ptr = (int *)statusbuffer; - CE_CmdReset(); + s_ce_cmdbuffer->buffer_base_ptr = cmdbuffer; + s_ce_cmdbuffer->status_buffer_ptr = statusbuffer; + (void)CE_CmdReset(); return 0; } -int CE_CmdReset() +/*! + * brief Resets the CM33-ZV2117 command queue. + * + * details Any pending commands in the queue will be flushed. + * + * retval 0 Reset is successful. + */ +int32_t CE_CmdReset(void) { - unsigned int *cmd_base = s_ce_cmdbuffer->buffer_base_ptr; + volatile uint32_t *cmd_base = s_ce_cmdbuffer->buffer_base_ptr; + *cmd_base = 0xCCCC; s_ce_cmdbuffer->next_buffer_ptr = cmd_base + 1; s_ce_cmdbuffer->n_cmd = 0; @@ -53,22 +82,36 @@ int CE_CmdReset() return 0; } -int CE_CmdAdd(ce_cmd_t cmd, ce_cmdstruct_t *cmdargs) +/*! + * brief Adds a command to the command queue. + * + * param [in] cmd Command name. Choose from the enum description + * in ref fsl_ce_if.h. Not all of the cmd are implemented + * in the current release. + * param [in] cmdargs Arguments structure detailing the arguments + * for the function/command. + * + * retval 0 Command added successfully. + * retval -1 Command not added (queue is full). + */ +int32_t CE_CmdAdd(ce_cmd_t cmd, ce_cmdstruct_t *cmdargs) { - int i, size, addstatus; - unsigned short *nargsbase; - unsigned int *cmdbase; + int32_t addstatus; + volatile uint16_t *nargsbase; + uint16_t i; + uint32_t size; + volatile uint32_t *cmdbase; void **ptrargbase; - int *ptrparambase; + int32_t *ptrparambase; if (s_ce_cmdbuffer->n_cmd < CE_CMD_MAX_CMDS_ZVQ) { - size = sizeof(void *) * cmdargs->n_ptr_args + sizeof(int) * (cmdargs->n_param_args + 1) + sizeof(short) * 2; + size = sizeof(void *) * cmdargs->n_ptr_args + sizeof(int32_t) * ((uint32_t)cmdargs->n_param_args + 1U) + sizeof(int16_t) * 2U; cmdbase = s_ce_cmdbuffer->next_buffer_ptr; - *cmdbase = (unsigned int)cmd; + *cmdbase = (uint32_t)cmd; - nargsbase = (unsigned short *)(cmdbase + 1); + nargsbase = (volatile uint16_t *)(cmdbase + 1U); *nargsbase = cmdargs->n_ptr_args; nargsbase += 1; *nargsbase = cmdargs->n_param_args; @@ -81,7 +124,7 @@ int CE_CmdAdd(ce_cmd_t cmd, ce_cmdstruct_t *cmdargs) ptrargbase += 1; } - ptrparambase = (int *)ptrargbase; + ptrparambase = (int32_t *)ptrargbase; for (i = 0; i < cmdargs->n_param_args; i++) { *ptrparambase = cmdargs->arg_param_array[i]; @@ -90,7 +133,7 @@ int CE_CmdAdd(ce_cmd_t cmd, ce_cmdstruct_t *cmdargs) s_ce_cmdbuffer->n_cmd++; - cmdbase += (size / sizeof(int)); + cmdbase += (size / sizeof(int32_t)); s_ce_cmdbuffer->next_buffer_ptr = cmdbase; addstatus = 0; @@ -103,7 +146,16 @@ int CE_CmdAdd(ce_cmd_t cmd, ce_cmdstruct_t *cmdargs) return addstatus; } -int CE_CmdLaunch(int force_launch) +/*! + * brief Launches the ZV2117 with the current command queue. + * + * param [in] force_launch + * - 1: Launches the queue regardless of the command mode. + * - 0: Launches only if in single-command mode. Otherwise, does nothing. + * + * retval 0 Launch is successful. + */ +int32_t CE_CmdLaunch(int32_t force_launch) { if (force_launch == 1) { @@ -130,21 +182,35 @@ int CE_CmdLaunch(int force_launch) return 0; } -int CE_CmdLaunchBlocking() +/*! + * brief Launches the current command queue and waits for completion. + * + * retval 0 Launch is successful. + */ +int32_t CE_CmdLaunchBlocking(void) { - unsigned int n_cmd; + uint32_t n_cmd; + status_t status = kStatus_Fail; - if (s_ce_cmdbuffer->n_cmd == 0) +#if CE_COMPUTE_TIMEOUT + uint32_t timeout = CE_COMPUTE_TIMEOUT; +#endif + + if (s_ce_cmdbuffer->n_cmd == 0U) { return -2; /* no commands to send */ } /* write number of commands via TX2 reg */ - MU_SendMsg((MU_Type *)DSP0_MU_BASE_ADDR, 2U, s_ce_cmdbuffer->n_cmd); + status = MU_SendMsg((MU_Type *)DSP0_MU_BASE_ADDR, 2U, s_ce_cmdbuffer->n_cmd); + if (kStatus_Success != status) + { + assert(false); + } + CE_CmdDelay(); /* launch CE by sending MU interrupt */ - status_t status = MU_TriggerInterrupts((MU_Type *)DSP0_MU_BASE_ADDR, kMU_GenInt0InterruptTrigger); - + status = MU_TriggerInterrupts((MU_Type *)DSP0_MU_BASE_ADDR, (uint32_t)kMU_GenInt0InterruptTrigger); if (kStatus_Success != status) { assert(false); @@ -153,32 +219,59 @@ int CE_CmdLaunchBlocking() /* blocking: so poll till completion */ /* completion is signaled when ZV2117 writes "D09E"to top of cmd buffer */ n_cmd = *(s_ce_cmdbuffer->buffer_base_ptr); + while (n_cmd != CE_COMPUTE_DONE) { +#if CE_COMPUTE_TIMEOUT + if (--timeout == 0U) + { + return kStatus_Timeout; + } +#endif CE_CmdDelay(); n_cmd = *(s_ce_cmdbuffer->buffer_base_ptr); } - CE_CmdReset(); + (void)CE_CmdReset(); /* read the status register */ - return *(s_ce_cmdbuffer->status_buffer_ptr + 1); + return *(s_ce_cmdbuffer->status_buffer_ptr + 1U); } -int CE_CmdLaunchNonBlocking() +/*! + * brief Launches the current command queue and returns immediately. + * + * details ZV2117 will send an interrupt via MUA->GCR to ARM upon task completion. + * Alternatively, the user can poll for completion. + * + * If using interrupt, the user must call CE_CmdReset() in the IRQ handler. + * IRQ::DSP_IRQn must be enabled. + * + * The user can optionally also poll to figure out the command queue execution status. + * + * retval 0 Launch is successful. + */ +int32_t CE_CmdLaunchNonBlocking(void) { + status_t status = kStatus_Fail; + /* Launches non-blocking */ - if (s_ce_cmdbuffer->n_cmd == 0) + if (s_ce_cmdbuffer->n_cmd == 0U) { return -2; /* no commands to send */ } /* Write number of commands via TX2 reg, * set MSb to indicate non-blocking mode to ZENV: ZENV will send interrupt back in this case. */ - MU_SendMsg((MU_Type *)DSP0_MU_BASE_ADDR, 2U, 0x80000000 | s_ce_cmdbuffer->n_cmd); + status = MU_SendMsg((MU_Type *)DSP0_MU_BASE_ADDR, 2U, 0x80000000U | s_ce_cmdbuffer->n_cmd); + if (kStatus_Success != status) + { + assert(false); + } + CE_CmdDelay(); /* launch CE by sending MU interrupt */ - status_t status = MU_TriggerInterrupts((MU_Type *)DSP0_MU_BASE_ADDR, kMU_GenInt0InterruptTrigger); + status = MU_TriggerInterrupts((MU_Type *)DSP0_MU_BASE_ADDR, (uint32_t)kMU_GenInt0InterruptTrigger); if (kStatus_Success != status) { assert(false); @@ -188,10 +281,18 @@ int CE_CmdLaunchNonBlocking() return 0; } -int CE_CmdCheckStatus() +/*! + * brief Checks the execution status of the current command queue. + * Only applicable in non-blocking mode. + * + * return + * - ref CE_STATUS_BUSY ZV2117 is still executing. + * - ref CE_STATUS_IDLE Execution completed; ZV2117 is ready for new commands. + */ +int32_t CE_CmdCheckStatus(void) { - int status = -1; - unsigned int n_cmd = *(s_ce_cmdbuffer->buffer_base_ptr); + int32_t status = -1; + uint32_t n_cmd = *(s_ce_cmdbuffer->buffer_base_ptr); if (n_cmd != CE_COMPUTE_DONE) { @@ -200,7 +301,7 @@ int CE_CmdCheckStatus() else { status = CE_STATUS_IDLE; /* completed */ - CE_CmdReset(); + (void)CE_CmdReset(); } return status; diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.h b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.h index 9e5dc9804..bf808a3c4 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.h +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmd.h @@ -22,6 +22,20 @@ /******************************************************************************* * Definitions ******************************************************************************/ +/*! + * @brief Maximum loop wait time for CE computation. + * + * When CE is computing, driver will wait for the computation to complete. + * This parameter defines how many loops to check completion before return timeout. + * If defined as 0, driver will wait forever until completion. + */ +#ifndef CE_COMPUTE_TIMEOUT + #ifdef CONFIG_CE_COMPUTE_TIMEOUT + #define CE_COMPUTE_TIMEOUT CONFIG_CE_COMPUTE_TIMEOUT + #else + #define CE_COMPUTE_TIMEOUT 0U + #endif +#endif /******************************************************************************* * Variables @@ -36,78 +50,93 @@ extern "C" { #endif /*! - * @brief Initalizes the ARM-CE command buffer - * - * Initalizes the ARM-CE command buffer. Needs to called on power-up or reset - * or if the command mode needs to be changed. - * @param[in] psCmdBuffer Pointer to the command buffer structure, application shall - * allocate it, and it shall be in CE memory. - * @param[in] cmdbuffer The command buffer memory. Size of the buffer should be 256. - * @param[in] statusbuffer The status buffer memory. Size of the buffer should be 134. - * @param[in] cmdmode Whether one command or multi command queue, and, blocking or non-blocking - * call + * @brief Initializes the CM33-ZV2117 command buffer. + * @details This function must to be called once after power-up or reset, + * or when the command queue mode needs to be changed. Once configured, + * the command mode remains unchanged till reset or re-initialization. + * + * @param [out] psCmdBuffer Pointer to the command buffer structure. + * Must be allocated in ARM memory (not ZV2117). + * @param [in] cmdbuffer Command buffer. Must be 256 words in ZV2117 data memory. + * @param [in] statusbuffer Status buffer. Must be 134 words in ZV2117 data memory. + * @param [in] cmdmode Command mode. One of: + * - @ref kCE_CmdModeOneNonBlocking + * - @ref kCE_CmdModeMultipleNonBlocking + * - @ref kCE_CmdModeOneBlocking + * - @ref kCE_CmdModeMultipleBlocking * - * @return Currently only return 0. + * @retval 0 Initialization is successful. */ -int CE_CmdInitBuffer(ce_cmdbuffer_t *psCmdBuffer, +int32_t CE_CmdInitBuffer(ce_cmdbuffer_t *psCmdBuffer, volatile uint32_t cmdbuffer[], - volatile uint32_t statusbuffer[], + volatile int32_t statusbuffer[], ce_cmd_mode_t cmdmode); /*! - * @brief Resets the command queue + * @brief Resets the CM33-ZV2117 command queue. * - * Any pending commands in the queue will be flushed. - * - * @return Currently only return 0. + * @details Any pending commands in the queue will be flushed. + * + * @retval 0 Reset is successful. */ -int CE_CmdReset(); +int32_t CE_CmdReset(void); /*! - * @brief Adds a command to the command queue + * @brief Adds a command to the command queue. * - * @param cmd Specifies the command name - * @param cmdargs Defines all arguments for the command - * @retval 0 Command added successfully - * @retval -1 Command not added since command queue is at maximum limit + * @param [in] cmd Command name. Choose from the enum description + * in @ref fsl_ce_if.h. Not all of the cmd are implemented + * in the current release. + * @param [in] cmdargs Arguments structure detailing the arguments + * for the function/command. + * + * @retval 0 Command added successfully. + * @retval -1 Command not added (queue is full). */ -int CE_CmdAdd(ce_cmd_t cmd, ce_cmdstruct_t *cmdargs); +int32_t CE_CmdAdd(ce_cmd_t cmd, ce_cmdstruct_t *cmdargs); /*! - * @brief Launches the command queue for execution on CE + * @brief Launches the ZV2117 with the current command queue. * - * @param force_launch Specifies the mode - * - 1: executes the queue regardless of the command mode - * - 0: executes the queue only if in ONE cmd mode. Otherwise, does nothing + * @param [in] force_launch + * - 1: Launches the queue regardless of the command mode. + * - 0: Launches only if in single-command mode. Otherwise, does nothing. * - * @return Return 0 if succeeded, otherwise return error code. + * @retval 0 Launch is successful. */ -int CE_CmdLaunch(int force_launch); +int32_t CE_CmdLaunch(int32_t force_launch); /*! - * @brief Launches the current command queue and returns upon completion of the queue on CE - * - * @return Return 0 if succeeded, otherwise return error code. + * @brief Launches the current command queue and waits for completion. + * + * @retval 0 Launch is successful. */ -int CE_CmdLaunchBlocking(); +int32_t CE_CmdLaunchBlocking(void); /*! - * @brief Launches the current command queue and returns without waiting for completion on CE - * - * CE Will send an interrupt via MUA->GCR to ARM upon completion of task. User can also poll to check for completion. - * User has to call CE_CmdReset() in the IRQ handler. IRQ::DSP_IRQn needs to be enabled. - * - * @return Currently only return 0. + * @brief Launches the current command queue and returns immediately. + * + * @details ZV2117 will send an interrupt via MUA->GCR to ARM upon task completion. + * Alternatively, the user can poll for completion. + * + * If using interrupt, the user must call CE_CmdReset() in the IRQ handler. + * IRQ::DSP_IRQn must be enabled. + * + * The user can optionally also poll to figure out the command queue execution status. + * + * @retval 0 Launch is successful. */ -int CE_CmdLaunchNonBlocking(); +int32_t CE_CmdLaunchNonBlocking(void); /*! - * @brief Checks the command queue execution status on CE - * - * @retval 0 Task completed and CE is ready for next command(s) - * @retval 1 Task still running; CE is busy + * @brief Checks the execution status of the current command queue. + * Only applicable in non-blocking mode. + * + * @return + * - @ref CE_STATUS_BUSY ZV2117 is still executing. + * - @ref CE_STATUS_IDLE Execution completed; ZV2117 is ready for new commands. */ -int CE_CmdCheckStatus(); +int32_t CE_CmdCheckStatus(void); #ifdef __cplusplus } diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.c b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.c index 71f51f522..022c0b6b2 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.c +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.c @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -13,25 +13,38 @@ Implementation file for ARM API compatible FFT functions on CE #include "fsl_ce_cmd.h" #include "fsl_ce_transform.h" +/*! + * brief CMSIS-compatible FFT implementation using ZV2117 backend. + * + * details This API is designed to be compatible with the ARM CM33 FFT interface. + * It delegates the FFT computation to the ZV2117 CE module. + * Please refer to CM33 documentation for details. + * + * return Command execution status. + * + * note This API only support float32 FFTs. + */ void ce_arm_cfft_f32( const arm_cfft_instance_f32 *S, float *p1, uint8_t ifftFlag, uint8_t bitReverseFlag, float *pOut, float *pScratch) { - int l2N = 0, temp = S->fftLen; - if (temp > 0) + int32_t l2N = 0; + uint16_t temp = S->fftLen; + + if (temp > 0U) { - while ((temp & 0x1) != 1) + while ((temp & 0x1U) != 1U) { - temp = temp >> 1; + temp = temp >> 1U; l2N++; } } - if (ifftFlag == 0) + if (ifftFlag == 0U) { - CE_TransformCFFT_F32(pOut, p1, pScratch, l2N); + (void)CE_TransformCFFT_F32(pOut, p1, pScratch, l2N); } else { - CE_TransformIFFT_F32(pOut, p1, pScratch, l2N); + (void)CE_TransformIFFT_F32(pOut, p1, pScratch, l2N); } } diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.h b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.h index 699178880..b12ab7c82 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.h +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_cmsis.h @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -13,7 +13,7 @@ /*! * @ingroup ce * @defgroup ce_cmsis CE CMSIS Functions - * @brief Functional API definitions CMSIS compatible functions + * @brief Functional API definitions for CMSIS compatible functions * @{ */ @@ -23,10 +23,10 @@ /*! @brief FFT/IFFT float32 */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const float *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ + uint16_t fftLen; /*!< Length of the FFT. */ + const float *pTwiddle; /*!< Points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /*!< Points to the bit reversal table. */ + uint16_t bitRevLength; /*!< Length of the bit reversal table. */ } arm_cfft_instance_f32; /******************************************************************************* @@ -41,6 +41,17 @@ typedef struct extern "C" { #endif +/*! + * @brief CMSIS-compatible FFT implementation using ZV2117 backend. + * + * @details This API is designed to be compatible with the ARM CM33 FFT interface. + * It delegates the FFT computation to the ZV2117 CE module. + * Please refer to CM33 documentation for details. + * + * @return Command execution status. + * + * @note This API only support float32 FFTs. + */ void ce_arm_cfft_f32(const arm_cfft_instance_f32 *S, float *p1, /* input pointer */ uint8_t ifftFlag, diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_if.h b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_if.h index b8ea2790f..b4f82eaf2 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_if.h +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_if.h @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -11,25 +11,30 @@ Interface Definitions for CM33-CE Driver #ifndef FSL_CE_IF_H #define FSL_CE_IF_H -#define CE_CMD_MAX_ARGS 6 -#define CE_CMD_MAX_CMDS_ZVQ 18 +#define CE_CMD_MAX_ARGS 6U +#define CE_CMD_MAX_CMDS_ZVQ 18U -#define CE_STATUS_BUSY 0xB054U -#define CE_STATUS_IDLE 0xFF00U +/*! @brief ZV2117 is busy executing current command queue. */ +#define CE_STATUS_BUSY 0xB054 +/*! + * @brief Command queue execution completed on ZV2117. + * ZV2117 is ready to process next set of commands. + */ +#define CE_STATUS_IDLE 0xFF00 -/* CMD name definitions */ +/*! @brief CMD mode name definitions */ typedef enum { - kCE_CmdModeOneNonBlocking = 0, /* one command non-blocking */ - kCE_CmdModeMultipleNonBlocking = 1, /* multi-command non-blocking */ - kCE_CmdModeOneBlocking = 2, /* one command blocking */ - kCE_CmdModeMultipleBlocking = 3 /* multi-command blocking */ + kCE_CmdModeOneNonBlocking = 0, /*!< one command non-blocking */ + kCE_CmdModeMultipleNonBlocking = 1, /*!< multi-command non-blocking */ + kCE_CmdModeOneBlocking = 2, /*!< one command blocking */ + kCE_CmdModeMultipleBlocking = 3 /*!< multi-command blocking */ } ce_cmd_mode_t; -/* CMD name definitions */ +/*! @brief CMD name definitions */ typedef enum { - /* Legacy PQ Matrix functions */ + /*!< Legacy PQ Matrix functions */ kCE_Cmd_MAT_ADD_Q15, kCE_Cmd_MAT_ADD_Q31, kCE_Cmd_MAT_ADD_F32, @@ -48,7 +53,7 @@ typedef enum kCE_Cmd_MAT_SCALE_Q31, kCE_Cmd_MAT_SCALE_F32, - /* Legacy PQ Math functions */ + /*!< Legacy PQ Math functions */ kCE_Cmd_SQRT_Q15, kCE_Cmd_SQRT_Q31, kCE_Cmd_SIN_Q15, @@ -58,7 +63,7 @@ typedef enum kCE_Cmd_COS_Q31, kCE_Cmd_COS_F32, - /* Legacy PQ Filter functions */ + /*!< Legacy PQ Filter functions */ kCE_Cmd_FIR_Q15, kCE_Cmd_FIR_Q31, kCE_Cmd_FIR_F32, @@ -69,7 +74,7 @@ typedef enum kCE_Cmd_CORR_Q31, kCE_Cmd_CORR_F32, - /* Legacy PQ Transform functions */ + /*!< Legacy PQ Transform functions */ kCE_Cmd_RFFT_Q15, kCE_Cmd_RFFT_Q31, kCE_Cmd_CFFT_Q15, @@ -79,7 +84,7 @@ typedef enum kCE_Cmd_DCT4_Q15, kCE_Cmd_DCT4_Q31, - /* New Transform functions */ + /*!< New Transform functions */ kCE_Cmd_RFFT_F16, kCE_Cmd_RFFT_F32, kCE_Cmd_CFFT_F16, @@ -87,7 +92,7 @@ typedef enum kCE_Cmd_IFFT_F16, kCE_Cmd_IFFT_F32, - /* Advanced Linear Algebra */ + /*!< Advanced Linear Algebra */ kCE_Cmd_MAT_INV_HERM_CF32, kCE_Cmd_MAT_INV_CF32, kCE_Cmd_MAT_INV_SYMM_F32, @@ -97,28 +102,28 @@ typedef enum kCE_Cmd_MAT_EVD_F32, kCE_Cmd_MAT_CHOL_CF32, - /* Misc CMD */ - kCE_Cmd_NULLCMD = 0xAA, /* NULL command */ - kCE_Cmd_ZVCOPY = 0xAB /* COPY */ + /*!< Misc CMD */ + kCE_Cmd_NULLCMD = 0xAA, /*!< NULL command */ + kCE_Cmd_ZVCOPY = 0xAB /*!< COPY */ } ce_cmd_t; -/* structure defining the ce command buffer configuration */ +/*! @brief structure defining the ce command buffer configuration */ typedef struct { - unsigned int *buffer_base_ptr; - unsigned int *next_buffer_ptr; - int *status_buffer_ptr; - unsigned int n_cmd; + volatile uint32_t *buffer_base_ptr; + volatile uint32_t *next_buffer_ptr; + volatile int32_t *status_buffer_ptr; + uint32_t n_cmd; ce_cmd_mode_t cmdmode; } ce_cmdbuffer_t; -/* structure for a single zv/ce command */ +/*! @brief structure for a single zv/ce command */ typedef struct { - unsigned short n_ptr_args; /* number of pointer arguments */ - unsigned short n_param_args; /* number of integer arguments */ - void *arg_ptr_array[CE_CMD_MAX_ARGS]; /* array of pointer arguments */ - int arg_param_array[CE_CMD_MAX_ARGS]; /* array of integer arguments */ + uint16_t n_ptr_args; /*!< number of pointer arguments */ + uint16_t n_param_args; /*!< number of integer arguments */ + void *arg_ptr_array[CE_CMD_MAX_ARGS]; /*!< array of pointer arguments */ + int32_t arg_param_array[CE_CMD_MAX_ARGS]; /*!< array of integer arguments */ } ce_cmdstruct_t; #endif /*FSL_CE_IF_H*/ diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.c b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.c index ab73c9f58..00ab56526 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.c +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.c @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -12,9 +12,23 @@ Implementation file for CE wrapper/driver functions on ARM #include "fsl_ce_matrix.h" #include "fsl_ce_cmd.h" -int CE_MatrixAdd_Q15(int16_t *pDst, int16_t *pA, int16_t *pB, int M, int N) +/*! + * brief Calculates the sum of two real 16-bit integer (Q15) matrices. + * + * details Computes C = A + B, where A, B, and C are an M × N real int16_t matrices. + * All matrices are assumed to have the same format and dimensions. + * + * param [out] pDst Pointer to the output matrix C (size M × N). + * param [in] pA Pointer to the input matrix A (size M × N). + * param [in] pB Pointer to the input matrix B (size M × N). + * param [in] M Number of rows of matrices A, B, and C. + * param [in] N Number of columns of matrices A, B, and C. + * + * return Command execution status. + */ +int32_t CE_MatrixAdd_Q15(int16_t *pDst, int16_t *pA, int16_t *pB, int32_t M, int32_t N) { - int status; + int32_t status; ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -35,9 +49,23 @@ int CE_MatrixAdd_Q15(int16_t *pDst, int16_t *pA, int16_t *pB, int M, int N) return status; } -int CE_MatrixAdd_Q31(int32_t *pDst, int32_t *pA, int32_t *pB, int M, int N) +/*! + * brief Calculates the sum of two real 32-bit integer (Q31) matrices. + * + * details Computes C = A + B, where A, B, and C are an M × N real int32_t matrices. + * All matrices are assumed to have the same format and dimensions. + * + * param [out] pDst Pointer to the output matrix C (size M × N). + * param [in] pA Pointer to the input matrix A (size M × N). + * param [in] pB Pointer to the input matrix B (size M × N). + * param [in] M Number of rows of matrices A, B, and C. + * param [in] N Number of columns of matrices A, B, and C. + * + * return Command execution status. + */ +int32_t CE_MatrixAdd_Q31(int32_t *pDst, int32_t *pA, int32_t *pB, int32_t M, int32_t N) { - int status; + int32_t status; ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -58,9 +86,23 @@ int CE_MatrixAdd_Q31(int32_t *pDst, int32_t *pA, int32_t *pB, int M, int N) return status; } -int CE_MatrixAdd_F32(float *pDst, float *pA, float *pB, int M, int N) +/*! + * brief Calculates the sum of two real 32-bit floating-point matrices. + * + * details Computes C = A + B, where A, B, and C are an M × N real float32 matrices. + * All matrices are assumed to have the same format and dimensions. + * + * param [out] pDst Pointer to the output matrix C (size M × N). + * param [in] pA Pointer to the input matrix A (size M × N). + * param [in] pB Pointer to the input matrix B (size M × N). + * param [in] M Number of rows of matrices A, B, and C. + * param [in] N Number of columns of matrices A, B, and C. + * + * return Command execution status. + */ +int32_t CE_MatrixAdd_F32(float *pDst, float *pA, float *pB, int32_t M, int32_t N) { - int status; + int32_t status; ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -81,9 +123,23 @@ int CE_MatrixAdd_F32(float *pDst, float *pA, float *pB, int M, int N) return status; } -int CE_MatrixElemMul_F32(float *pDst, float *pA, float *pB, int M, int N) +/*! + * brief Calculates the element-wise product of two real 32-bit floating-point matrices. + * + * details Computes C = A .× B, where A, B, and C are an M × N real float32 matrices. + * All matrices are assumed to have the same format and dimensions. + * + * param [out] pDst Pointer to the output matrix C (size M × N). + * param [in] pA Pointer to the input matrix A (size M × N). + * param [in] pB Pointer to the input matrix B (size M × N). + * param [in] M Number of rows of matrices A, B, and C. + * param [in] N Number of columns of matrices A, B, and C. + * + * return Command execution status. + */ +int32_t CE_MatrixElemMul_F32(float *pDst, float *pA, float *pB, int32_t M, int32_t N) { - int status; + int32_t status; ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -104,9 +160,33 @@ int CE_MatrixElemMul_F32(float *pDst, float *pA, float *pB, int M, int N) return status; } -int CE_MatrixMul_F32(float *pDst, float *pA, float *pB, int M, int N, int P) +/*! + * brief Calculates the matrix product of two real 32-bit floating-point matrices. + * + * details Computes C = A × B, where: + * - A is an M × N real float32 matrix, + * - B is an N × P real float32 matrix, + * - C is the resulting M × P real float32 matrix. + * + * All matrices are assumed to be in row-major format. + * + * param [out] pDst Pointer to the output matrix C (size M × P) + * param [in] pA Pointer to the input matrix A (size M × N). + * param [in] pB Pointer to the input matrix B (size N × P). + * param [in] M Number of rows of matrix A. + * param [in] N Number of columns in matrix A (and rows in matrix B). + * param [in] P Number of columns of matrix B. + * + * return Command execution status. + * + * note Data precision and format is as defined by the argument type. + * Limits on max value of N: + * - For F32: N < 128; + * - For CF32: N < 64. + */ +int32_t CE_MatrixMul_F32(float *pDst, float *pA, float *pB, int32_t M, int32_t N, int32_t P) { - int status; + int32_t status; ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -128,9 +208,28 @@ int CE_MatrixMul_F32(float *pDst, float *pA, float *pB, int M, int N, int P) return status; } -int CE_MatrixMul_CF32(float *pDst, float *pA, float *pB, int M, int N, int P) +/*! + * brief Calculates the matrix product of two complex 32-bit floating point matrices. + * + * details Computes C = A × B, where: + * - A is an M × N complex float32 matrix, + * - B is an N × P complex float32 matrix, + * - C is the resulting M × P complex float32 matrix. + * + * All matrices are assumed to be in row-major format. + * + * param [out] pDst Pointer to the output matrix C (size M × P). + * param [in] pA Pointer to the input matrix A (size M × N). + * param [in] pB Pointer to the input matrix B (size N × P). + * param [in] M Number of rows of matrix A. + * param [in] N Number of columns in matrix A (and rows in matrix B). + * param [in] P Number of columns of matrix B. + * + * return Command execution status. + */ +int32_t CE_MatrixMul_CF32(float *pDst, float *pA, float *pB, int32_t M, int32_t N, int32_t P) { - int status; + int32_t status; ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -152,73 +251,44 @@ int CE_MatrixMul_CF32(float *pDst, float *pA, float *pB, int M, int N, int P) return status; } -int CE_MatrixInv_F32(float *pAinv, float *pA, int M) -{ - int status; - - ce_cmdstruct_t cmdstruct; - cmdstruct.n_ptr_args = 2; - cmdstruct.n_param_args = 1; - cmdstruct.arg_ptr_array[0] = (void *)pAinv; - cmdstruct.arg_ptr_array[1] = (void *)pA; - cmdstruct.arg_param_array[0] = M; - - status = CE_CmdAdd(kCE_Cmd_MAT_INV_F32, &cmdstruct); - - if (status == 0) - { - status = CE_CmdLaunch(0); - } - - return status; -} - -int CE_MatrixInvSymm_F32(float *pAinv, float *pA, int M) -{ - int status; - - ce_cmdstruct_t cmdstruct; - cmdstruct.n_ptr_args = 2; - cmdstruct.n_param_args = 1; - cmdstruct.arg_ptr_array[0] = (void *)pAinv; - cmdstruct.arg_ptr_array[1] = (void *)pA; - cmdstruct.arg_param_array[0] = M; - - status = CE_CmdAdd(kCE_Cmd_MAT_INV_SYMM_F32, &cmdstruct); - - if (status == 0) - { - status = CE_CmdLaunch(0); - } - - return status; -} - -int CE_MatrixInv_CF32(float *pAinv, float *pA, int M) -{ - int status; - - ce_cmdstruct_t cmdstruct; - cmdstruct.n_ptr_args = 2; - cmdstruct.n_param_args = 1; - cmdstruct.arg_ptr_array[0] = (void *)pAinv; - cmdstruct.arg_ptr_array[1] = (void *)pA; - cmdstruct.arg_param_array[0] = M; - - status = CE_CmdAdd(kCE_Cmd_MAT_INV_CF32, &cmdstruct); - - if (status == 0) - { - status = CE_CmdLaunch(0); - } - - return status; -} - -int CE_MatrixInvHerm_CF32( - float *pAinv, float *pA, float *pScratch, int M, uint8_t flag_packedInput, uint8_t flag_cholInv) +/*! + * brief Calculates the inverse or Cholesky inverse of a complex Hermitian matrix + * (in float32 precision). + * + * details Computes one of the following: + * - Ainv = inv(A) + * - Ainv = inv(chol(A)) + * + * where chol(A) is the lower triangular Cholesky decomposition of matrix A. + * + * The input matrix must be in row-major format and can be either: + * - A full M × M matrix, or + * - A packed upper triangular matrix (containing only the upper triangle). + * + * The output matrix is written in row-major format, and only + * the lower triangle is stored. The total number of output elements is: + * - Mc = (M + 1) × M / 2 + * + * param[out] pAinv Pointer to the output matrix inverse. + * Mc elements are written (complex float32). + * param[in] pA Pointer to the input matrix A (complex float32, size M × M). + * param[in] pScratch Pointer to scratch buffer (minimum size Mc × 3 × 8 bytes). + * param[in] M Number of rows/columns in matrix A. + * param[in] flag_packedInput Format of input matrix: + * - 0: full matrix + * - 1: packed upper triangular matrix + * param[in] flag_cholInv Type of inverse to compute: + * - 0: inv(A) + * - 1: inv(chol(A)) + * + * return Command execution status. + * + * note The input, output and scratch buffers must be separately allocated and non-overlapping. + */ +int32_t CE_MatrixInvHerm_CF32( + float *pAinv, float *pA, float *pScratch, int32_t M, uint8_t flag_packedInput, uint8_t flag_cholInv) { - int status; + int32_t status; ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -227,8 +297,8 @@ int CE_MatrixInvHerm_CF32( cmdstruct.arg_ptr_array[1] = (void *)pA; cmdstruct.arg_ptr_array[2] = (void *)pScratch; cmdstruct.arg_param_array[0] = M; - cmdstruct.arg_param_array[1] = flag_packedInput; - cmdstruct.arg_param_array[2] = flag_cholInv; + cmdstruct.arg_param_array[1] = (int32_t)flag_packedInput; + cmdstruct.arg_param_array[2] = (int32_t)flag_cholInv; status = CE_CmdAdd(kCE_Cmd_MAT_INV_HERM_CF32, &cmdstruct); @@ -240,18 +310,71 @@ int CE_MatrixInvHerm_CF32( return status; } -int CE_MatrixChol_CF32(float *pL, float *pA, int M) +/*! + * brief Calculates the Eigenvalue Decomposition (EVD) of a complex Hermitian matrix + * (float32 precision). + * + * details Performs EVD on an M×M complex Hermitian matrix A: + * - [U, T] = eig(A) + * + * The input matrix must be in column-major format and can be either: + * - A full M × M matrix, or + * - A packed upper triangular matrix. + * + * The decomposition uses an iterative QR algorithm to compute: + * - U: matrix of eigenvectors (M × M, column-major) + * - T: vector of eigenvalues (M × 1) + * + * Maximum supported matrix size: M ≤ 40. + * + * param [out] pLambdaOut Pointer to the output vector of eigenvalues + * (size M × 1, complex float32). + * param [out] pUout Pointer to the output matrix of eigenvectors + * (size M × M, column-major, complex float32). + * param [in] pUin Pointer to the input matrix A + * (size M × M, column-major, complex float32). + * param [in] pScratch Pointer to scratch buffer + * (minimum size: (M × M × 4 + 360) × 4 bytes). + * param [in] M Number of rows/columns in matrix A. + * param [in] tol Tolerance value for QR convergence. + * Smaller values yield better accuracy but require more iterations. + * param [in] max_iter Maximum number of QR iterations. + * If exceeded, the function terminates regardless of convergence. + * param [in] flag_packedInput Format of input matrix: + * - 0: full matrix + * - 1: packed upper triangular part only + * + * return Command execution status. + * The number of QR iterations is returned in status[3] register. + * + * note If input and output buffers overlap, + * the output U matrix will overwrite the input matrix A. + */ +int32_t CE_MatrixEvdHerm_CF32(float *pLambdaOut, + float *pUout, + float *pUin, + float *pScratch, + int32_t M, + float tol, + int32_t max_iter, + uint8_t flag_packedInput) { - int status; + int32_t status; + int32_t *ptemp = (int32_t *)&tol; ce_cmdstruct_t cmdstruct; - cmdstruct.n_ptr_args = 2; - cmdstruct.n_param_args = 1; - cmdstruct.arg_ptr_array[0] = (void *)pL; - cmdstruct.arg_ptr_array[1] = (void *)pA; + cmdstruct.n_ptr_args = 4; + cmdstruct.n_param_args = 4; + cmdstruct.arg_ptr_array[0] = (void *)pLambdaOut; + cmdstruct.arg_ptr_array[1] = (void *)pUout; + cmdstruct.arg_ptr_array[2] = (void *)pScratch; + cmdstruct.arg_ptr_array[3] = (void *)pUin; cmdstruct.arg_param_array[0] = M; + cmdstruct.arg_param_array[1] = *ptemp; + cmdstruct.arg_param_array[2] = max_iter; + cmdstruct.arg_param_array[3] = (int32_t)flag_packedInput; - status = CE_CmdAdd(kCE_Cmd_MAT_CHOL_CF32, &cmdstruct); + status = CE_CmdAdd(kCE_Cmd_MAT_EVD_HERM_CF32, &cmdstruct); if (status == 0) { @@ -261,31 +384,50 @@ int CE_MatrixChol_CF32(float *pL, float *pA, int M) return status; } -int CE_MatrixEvdHerm_CF32(float *pLambdaOut, - float *pUout, - float *pUin, - float *pScratch, - int M, - float tol, - int max_iter, - uint8_t flag_packedInput) +/*! + * brief Calculates the Cholesky Decomposition of a complex Hermitian matrix + * (float32 precision). + * + * details Calculates L = chol(A), where A is a complex Hermitian M × M matrix and + * L is a lower triangular matrix such that A = L × L ^ H. + * + * The input matrix must be in row-major format and can be either: + * - A full M × M matrix, or + * - A packed format containing only the upper triangular elements. + * + * The output matrix is also in row-major format, + * and only the lower triangular part is written. + * The total number of output elements is Mc, where: + * - Mc = (M + 1) × M / 2 + * + * param [out] pL Pointer to the output lower triangular matrix L. + * Only Mc elements are written (complex-valued float32 data in row-major format). + * param [in] pA Pointer to the input matrix A (full or packed format). + * Must be complex-valued float32 data in row-major format. + * param [in] pScratch Pointer to a scratch buffer (at least Mc × 8 bytes). + * param [in] M Number of rows/columns of matrix A. + * param [in] flag_packedInput Format flag for input matrix: + * - 0: full matrix + * - 1: packed upper triangular matrix + * + * return Command execution status. + * + * note The input, output and scratch buffers must be separately allocated and non-overlapping. + */ +int32_t CE_MatrixChol_CF32(float *pL, float *pA, float *pScratch, int32_t M, uint8_t flag_packedInput) { - int status; - int *ptemp = (int *)&tol; + int32_t status; ce_cmdstruct_t cmdstruct; - cmdstruct.n_ptr_args = 4; - cmdstruct.n_param_args = 4; - cmdstruct.arg_ptr_array[0] = (void *)pLambdaOut; - cmdstruct.arg_ptr_array[1] = (void *)pUout; + cmdstruct.n_ptr_args = 3; + cmdstruct.n_param_args = 2; + cmdstruct.arg_ptr_array[0] = (void *)pL; + cmdstruct.arg_ptr_array[1] = (void *)pA; cmdstruct.arg_ptr_array[2] = (void *)pScratch; - cmdstruct.arg_ptr_array[3] = (void *)pUin; cmdstruct.arg_param_array[0] = M; - cmdstruct.arg_param_array[1] = *ptemp; - cmdstruct.arg_param_array[2] = max_iter; - cmdstruct.arg_param_array[3] = flag_packedInput; + cmdstruct.arg_param_array[1] = (int32_t)flag_packedInput; - status = CE_CmdAdd(kCE_Cmd_MAT_EVD_HERM_CF32, &cmdstruct); + status = CE_CmdAdd(kCE_Cmd_MAT_CHOL_CF32, &cmdstruct); if (status == 0) { @@ -293,4 +435,4 @@ int CE_MatrixEvdHerm_CF32(float *pLambdaOut, } return status; -} +} \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.h b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.h index cdbba3236..c49e71cbe 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.h +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_matrix.h @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -30,190 +30,233 @@ extern "C" { #endif /*! - * @brief Adds two MxN matrices with data in specified format + * @brief Calculates the sum of two real 16-bit integer (Q15) matrices. * - * Adds two MxN matrices; matrices can be in either of row or columns major - * formats. - * Data precision and format is as defined by the argument type + * @details Computes C = A + B, where A, B, and C are an M × N real int16_t matrices. + * All matrices are assumed to have the same format and dimensions. * - * @param pDst Pointer to buffer for output matrix - * @param pA Pointer to buffer for input matrix A - * @param pB Pointer to buffer for input matrix B - * @param M Number of rows for each input matrix - * @param N Number of columns for each input matrix + * @param [out] pDst Pointer to the output matrix C (size M × N). + * @param [in] pA Pointer to the input matrix A (size M × N). + * @param [in] pB Pointer to the input matrix B (size M × N). + * @param [in] M Number of rows of matrices A, B, and C. + * @param [in] N Number of columns of matrices A, B, and C. * - * @return Return 0 if succeeded, otherwise return error code. + * @return Command execution status. */ -int CE_MatrixAdd_Q15(int16_t *pDst, int16_t *pA, int16_t *pB, int M, int N); +int32_t CE_MatrixAdd_Q15(int16_t *pDst, int16_t *pA, int16_t *pB, int32_t M, int32_t N); /*! - * @copydoc CE_MatrixAdd_Q15 + * @brief Calculates the sum of two real 32-bit integer (Q31) matrices. + * + * @details Computes C = A + B, where A, B, and C are an M × N real int32_t matrices. + * All matrices are assumed to have the same format and dimensions. + * + * @param [out] pDst Pointer to the output matrix C (size M × N). + * @param [in] pA Pointer to the input matrix A (size M × N). + * @param [in] pB Pointer to the input matrix B (size M × N). + * @param [in] M Number of rows of matrices A, B, and C. + * @param [in] N Number of columns of matrices A, B, and C. + * + * @return Command execution status. */ -int CE_MatrixAdd_Q31(int32_t *pDst, int32_t *pA, int32_t *pB, int M, int N); +int32_t CE_MatrixAdd_Q31(int32_t *pDst, int32_t *pA, int32_t *pB, int32_t M, int32_t N); /*! - * @copydoc CE_MatrixAdd_Q15 + * @brief Calculates the sum of two real 32-bit floating-point matrices. + * + * @details Computes C = A + B, where A, B, and C are an M × N real float32 matrices. + * All matrices are assumed to have the same format and dimensions. + * + * @param [out] pDst Pointer to the output matrix C (size M × N). + * @param [in] pA Pointer to the input matrix A (size M × N). + * @param [in] pB Pointer to the input matrix B (size M × N). + * @param [in] M Number of rows of matrices A, B, and C. + * @param [in] N Number of columns of matrices A, B, and C. + * + * @return Command execution status. */ -int CE_MatrixAdd_F32(float *pDst, float *pA, float *pB, int M, int N); +int32_t CE_MatrixAdd_F32(float *pDst, float *pA, float *pB, int32_t M, int32_t N); /*! - * @brief Element wise multiply between two MxN matrices + * @brief Calculates the element-wise product of two real 32-bit floating-point matrices. * - * Elementwise multiplies two MxN matrices; matrices can be in either of row or - * columns major formats. + * @details Computes C = A .× B, where A, B, and C are an M × N real float32 matrices. + * All matrices are assumed to have the same format and dimensions. * - * Data precision and format is as defined by the argument type + * @param [out] pDst Pointer to the output matrix C (size M × N). + * @param [in] pA Pointer to the input matrix A (size M × N). + * @param [in] pB Pointer to the input matrix B (size M × N). + * @param [in] M Number of rows of matrices A, B, and C. + * @param [in] N Number of columns of matrices A, B, and C. * - * @param pDst Pointer to buffer for output matrix - * @param pA Pointer to buffer for input matrix A - * @param pB Pointer to buffer for input matrix B - * @param M Number of rows for each input matrix - * @param N Number of columns for each input matrix - * - * @return Return 0 if succeeded, otherwise return error code. + * @return Command execution status. */ -int CE_MatrixElemMul_F32(float *pDst, float *pA, float *pB, int M, int N); +int32_t CE_MatrixElemMul_F32(float *pDst, float *pA, float *pB, int32_t M, int32_t N); /*! - * @brief Matrix multiply between two MxN matrices + * @brief Calculates the matrix product of two real 32-bit floating-point matrices. + * + * @details Computes C = A × B, where: + * - A is an M × N real float32 matrix, + * - B is an N × P real float32 matrix, + * - C is the resulting M × P real float32 matrix. * - * Matrix multiply C[MxP] = A[MxN] x B[NxP] matrices with data in specified - * format. - * Multiply between MxN and NxP matrices; matrices must be in row major format + * All matrices are assumed to be in row-major format. * - * @param pDst Pointer to buffer for output matrix [MxP] - * @param pA Pointer to buffer for input matrix A [MxN] - * @param pB Pointer to buffer for input matrix B [NxP] - * @param M Number of rows for input matrix A - * @param N Number of columns for input matrix A, or, Number of rows for input matrix B - * @param P Number of columns for input matrix B + * @param [out] pDst Pointer to the output matrix C (size M × P) + * @param [in] pA Pointer to the input matrix A (size M × N). + * @param [in] pB Pointer to the input matrix B (size N × P). + * @param [in] M Number of rows of matrix A. + * @param [in] N Number of columns in matrix A (and rows in matrix B). + * @param [in] P Number of columns of matrix B. * - * Data precision and format is as defined by the argument type - * @note Limits on max value of N: For F32: N < 128; For CF32: N < 64 + * @return Command execution status. + * + * @note Data precision and format is as defined by the argument type. + * Limits on max value of N: + * - For F32: N < 128; + * - For CF32: N < 64. */ -int CE_MatrixMul_F32(float *pDst, float *pA, float *pB, int M, int N, int P); +int32_t CE_MatrixMul_F32(float *pDst, float *pA, float *pB, int32_t M, int32_t N, int32_t P); /*! - * @copydoc CE_MatrixMul_F32 - */ -int CE_MatrixMul_CF32(float *pDst, float *pA, float *pB, int M, int N, int P); - -/* - * @brief Matrix Inversion + * @brief Calculates the matrix product of two complex 32-bit floating point matrices. * - * Calculates inv(A) where A is a MxM real matrix + * @details Computes C = A × B, where: + * - A is an M × N complex float32 matrix, + * - B is an N × P complex float32 matrix, + * - C is the resulting M × P complex float32 matrix. * - * @param pAinv Pointer to buffer for output inverse matrix - * @param pA Pointer to buffer for input matrix A - * @param M Number of rows or columns of A + * All matrices are assumed to be in row-major format. * - * @return Return 0 if succeeded, otherwise return error code. + * @param [out] pDst Pointer to the output matrix C (size M × P). + * @param [in] pA Pointer to the input matrix A (size M × N). + * @param [in] pB Pointer to the input matrix B (size N × P). + * @param [in] M Number of rows of matrix A. + * @param [in] N Number of columns in matrix A (and rows in matrix B). + * @param [in] P Number of columns of matrix B. + * + * @return Command execution status. */ -int CE_MatrixInv_F32(float *pAinv, float *pA, int M); +int32_t CE_MatrixMul_CF32(float *pDst, float *pA, float *pB, int32_t M, int32_t N, int32_t P); -/* - * @brief Matrix Inversion +/*! + * @brief Calculates the inverse or Cholesky inverse of a complex Hermitian matrix + * (in float32 precision). * - * Calculates inv(A) where A is a MxM symmetric real matrix + * @details Computes one of the following: + * - Ainv = inv(A) + * - Ainv = inv(chol(A)) * - * @param pAinv Pointer to buffer for output inverse matrix - * @param pA Pointer to buffer for input matrix A - * @param M Number of rows or columns of A + * where chol(A) is the lower triangular Cholesky decomposition of matrix A. * - * @return Return 0 if succeeded, otherwise return error code. - */ -int CE_MatrixInvSymm_F32(float *pAinv, float *pA, int M); - -/* - * @brief Matrix Inversion + * The input matrix must be in row-major format and can be either: + * - A full M × M matrix, or + * - A packed upper triangular matrix (containing only the upper triangle). * - * Calculates inv(A) where A is a MxM complex matrix + * The output matrix is written in row-major format, and only + * the lower triangle is stored. The total number of output elements is: + * - Mc = (M + 1) × M / 2 * - * @param pAinv Pointer to buffer for output inverse matrix - * @param pA Pointer to buffer for input matrix A - * @param M Number of rows or columns of A + * @param[out] pAinv Pointer to the output matrix inverse. + * Mc elements are written (complex float32). + * @param[in] pA Pointer to the input matrix A (complex float32, size M × M). + * @param[in] pScratch Pointer to scratch buffer (minimum size Mc × 3 × 8 bytes). + * @param[in] M Number of rows/columns in matrix A. + * @param[in] flag_packedInput Format of input matrix: + * - 0: full matrix + * - 1: packed upper triangular matrix + * @param[in] flag_cholInv Type of inverse to compute: + * - 0: inv(A) + * - 1: inv(chol(A)) * - * @return Return 0 if succeeded, otherwise return error code. - */ -int CE_MatrixInv_CF32(float *pAinv, float *pA, int M); - -/*! - * @brief Matrix Inversion - * - * Based on an user specified flag, calculates either - * \li Ainv = inv(A), or, - * \li Linv = inv(chol(A)), - * - * where chol() is the lower triangular Cholesky Decomposition of A. - * A is a MxM complex Hermitian matrix. - * A is expected to be in row major format and can either be packed (only - * upper traingular elements) or full - * - * @param[out] pAinv Pointer to buffer for output inverse matrix. - * Only the upper triangular elements of the output matrix are written out. The - * output is written in row major order. Output size is Mc*8 bytes. - * Mc = *((1+M)*M)/2. - * @param[in] pA Pointer to buffer for input matrix A. If flag_packedInput=0, - * MxM matrix expected in row major format. If flag_packedInput=1, Only - * upper triangular part of A is expected in row major format (Mc CF32 elements). - * @param[in] pScratch Scratch memory of size (Mc*3)*8 bytes. - * @param M Number of rows or columns of A - * @param flag_packedInput Flag indicating input matrix format. - * - 0: full matrix - * - 1: upper triangular part only - * @param flag_cholInv Flag indicating inverse type. - * - 0: Out = inv(A) - * - 1: Out = inv(chol(A)) - * - * @return Return 0 if succeeded, otherwise return error code. + * @return Command execution status. + * + * @note The input, output and scratch buffers must be separately allocated and non-overlapping. */ -int CE_MatrixInvHerm_CF32( - float *pAinv, float *pA, float *pScratch, int M, uint8_t flag_packedInput, uint8_t flag_cholInv); +int32_t CE_MatrixInvHerm_CF32( + float *pAinv, float *pA, float *pScratch, int32_t M, uint8_t flag_packedInput, uint8_t flag_cholInv); /*! - * @brief Eigen Value Decompositions - * - * Calculates Eigen Value Decompositions of a MxM matrix. - * Calculates [U, T] = evd(A) where A is a MxM complex Hermitian matrix, U is - * the output matrix of eigen vectors, and T is the diagonal matrix of eigen - * values. - * - * @param pLambdaOut Pointer to buffer for output Eigen Vectors (MxM) - * @param pUout Pointer to buffer with output Eigen Values (Mx1) - * @param pUin Pointer to buffer for input matrix A - * @param M Number of rows or columns of A - * @param pScratch Scratch memory, the minimum scratch size required is (40 x 40 x 4 + 360) x 4 bytes. - * @param tol Tolerance specifying exit condition for the iterative computation - * @param max_iter Upper bound on number of iterations for convergence of each Eigen value - * @param flag_packedInput Flag indicating input matrix format. - * - 0: full matrix - * - 1: upper triangular part only - * - * @return Return 0 if succeeded, otherwise return error code. + * @brief Calculates the Eigenvalue Decomposition (EVD) of a complex Hermitian matrix + * (float32 precision). + * + * @details Performs EVD on an M×M complex Hermitian matrix A: + * - [U, T] = eig(A) + * + * The input matrix must be in column-major format and can be either: + * - A full M × M matrix, or + * - A packed upper triangular matrix. + * + * The decomposition uses an iterative QR algorithm to compute: + * - U: matrix of eigenvectors (M × M, column-major) + * - T: vector of eigenvalues (M × 1) + * + * Maximum supported matrix size: M ≤ 40. + * + * @param [out] pLambdaOut Pointer to the output vector of eigenvalues + * (size M × 1, complex float32). + * @param [out] pUout Pointer to the output matrix of eigenvectors + * (size M × M, column-major, complex float32). + * @param [in] pUin Pointer to the input matrix A + * (size M × M, column-major, complex float32). + * @param [in] pScratch Pointer to scratch buffer + * (minimum size: (M × M × 4 + 360) × 4 bytes). + * @param [in] M Number of rows/columns in matrix A. + * @param [in] tol Tolerance value for QR convergence. + * Smaller values yield better accuracy but require more iterations. + * @param [in] max_iter Maximum number of QR iterations. + * If exceeded, the function terminates regardless of convergence. + * @param [in] flag_packedInput Format of input matrix: + * - 0: full matrix + * - 1: packed upper triangular part only + * + * @return Command execution status. + * The number of QR iterations is returned in status[3] register. + * + * @note If input and output buffers overlap, + * the output U matrix will overwrite the input matrix A. */ -int CE_MatrixEvdHerm_CF32(float *pLambdaOut, - float *pUout, - float *pUin, - float *pScratch, - int M, - float tol, - int max_iter, - uint8_t flag_packedInput); +int32_t CE_MatrixEvdHerm_CF32(float *pLambdaOut, + float *pUout, + float *pUin, + float *pScratch, + int32_t M, + float tol, + int32_t max_iter, + uint8_t flag_packedInput); /*! - * @brief Cholesky Decomposition + * @brief Calculates the Cholesky Decomposition of a complex Hermitian matrix + * (float32 precision). + * + * @details Calculates L = chol(A), where A is a complex Hermitian M × M matrix and + * L is a lower triangular matrix such that A = L × L ^ H. + * + * The input matrix must be in row-major format and can be either: + * - A full M × M matrix, or + * - A packed format containing only the upper triangular elements. + * + * The output matrix is also in row-major format, + * and only the lower triangular part is written. + * The total number of output elements is Mc, where: + * - Mc = (M + 1) × M / 2 * - * Calculates L = chol(A) where A is a MxM complex Hermitian matrix - * This Cholesky Decomposition returns a lower triangular matrix L, - * such that A = L*L^H, A and L are expected to be in column major format + * @param [out] pL Pointer to the output lower triangular matrix L. + * Only Mc elements are written (complex-valued float32 data in row-major format). + * @param [in] pA Pointer to the input matrix A (full or packed format). + * Must be complex-valued float32 data in row-major format. + * @param [in] pScratch Pointer to a scratch buffer (at least Mc × 8 bytes). + * @param [in] M Number of rows/columns of matrix A. + * @param [in] flag_packedInput Format flag for input matrix: + * - 0: full matrix + * - 1: packed upper triangular matrix * - * @param pL Pointer to buffer for output triangular matrix L - * @param pA Pointer to buffer for input matrix A - * @param M Number of rows or columns of A + * @return Command execution status. * - * @return Return 0 if succeeded, otherwise return error code. + * @note The input, output and scratch buffers must be separately allocated and non-overlapping. */ -int CE_MatrixChol_CF32(float *pL, float *pA, int M); +int32_t CE_MatrixChol_CF32(float *pL, float *pA, float *pScratch, int32_t M, uint8_t flag_packedInput); #ifdef __cplusplus } diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_transform.c b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_transform.c index 0f7ac759d..983d60869 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_transform.c +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_transform.c @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -12,9 +12,34 @@ Implementation file for CE wrapper/driver FFT functions on ARM #include "fsl_ce_transform.h" #include "fsl_ce_cmd.h" -int CE_TransformCFFT_F16(float *pY, float *pX, float *pScratch, int log2N) +/*! + * brief Computes the FFT of complex-valued 16-bit floating point data. + * + * details Performs an N-point Fast Fourier Transform (FFT) on + * a complex-valued float16 input stream. The FFT size N must be a power of 2, + * with valid range: 16 ≤ N ≤ 16384. + * + * param [out] pY Pointer to the FFT output buffer (complex-valued float16 data). + * param [in] pX Pointer to the FFT input buffer (complex-valued float16 data). + * param [in] pScratch Pointer to a scratch buffer (at least N × 4 bytes). + * param [in] log2N Base-2 logarithm of the FFT size N. + * + * return Command execution status. + * + * note + * - Data precision and format follow the argument types. + * - `float*` is used to represent float16 pointers. + * - The input, output and scratch buffers must be separately allocated and non-overlapping. + */ +int32_t CE_TransformCFFT_F16(float *pY, float *pX, float *pScratch, int32_t log2N) { - int status; + int32_t status; + + if (log2N < 5 || log2N > 15) + { + status = FFT_ERROR_SZOUTSIDERANGE; + return status; + } ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -34,9 +59,31 @@ int CE_TransformCFFT_F16(float *pY, float *pX, float *pScratch, int log2N) return status; } -int CE_TransformCFFT_F32(float *pY, float *pX, float *pScratch, int log2N) +/*! + * brief Computes the FFT of complex-valued 32-bit floating point data. + * + * details Performs an N-point Fast Fourier Transform (FFT) on + * a complex-valued float32 input stream. The FFT size N must be a power of 2, + * with valid range: 32 ≤ N ≤ 16384. + * + * param [out] pY Pointer to the FFT output buffer (complex-valued float32). + * param [in] pX Pointer to the FFT input buffer (complex-valued float32). + * param [in] pScratch Pointer to a scratch buffer (at least N × 8 bytes). + * param [in] log2N Base-2 logarithm of the FFT size N. + * + * return Command execution status. + * + * note The input, output and scratch buffers must be separately allocated and non-overlapping. + */ +int32_t CE_TransformCFFT_F32(float *pY, float *pX, float *pScratch, int32_t log2N) { - int status; + int32_t status; + + if (log2N < 4 || log2N > 15) + { + status = FFT_ERROR_SZOUTSIDERANGE; + return status; + } ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -56,9 +103,34 @@ int CE_TransformCFFT_F32(float *pY, float *pX, float *pScratch, int log2N) return status; } -int CE_TransformIFFT_F16(float *pY, float *pX, float *pScratch, int log2N) +/*! + * brief Computes the IFFT of complex-valued 16-bit floating point data. + * + * details Performs an N-point Inverse Fast Fourier Transform (IFFT) on + * a complex-valued float16 input stream. The IFFT size N must be a power of 2, + * with valid range: 16 ≤ N ≤ 16384. + * + * param [out] pY Pointer to the IFFT output buffer (complex-valued float16). + * param [in] pX Pointer to the IFFT input buffer (complex-valued float16). + * param [in] pScratch Pointer to a scratch buffer (at least N × 4 bytes). + * param [in] log2N Base-2 logarithm of the IFFT size N. + * + * return Command execution status. + * + * note + * - Data precision and format follow the argument types. + * - `float*` is used to represent float16 pointers. + * - The input, output and scratch buffers must be separately allocated and non-overlapping. + */ +int32_t CE_TransformIFFT_F16(float *pY, float *pX, float *pScratch, int32_t log2N) { - int status; + int32_t status; + + if (log2N < 5 || log2N > 15) + { + status = FFT_ERROR_SZOUTSIDERANGE; + return status; + } ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; @@ -78,9 +150,32 @@ int CE_TransformIFFT_F16(float *pY, float *pX, float *pScratch, int log2N) return status; } -int CE_TransformIFFT_F32(float *pY, float *pX, float *pScratch, int log2N) +/*! + * brief Computes the IFFT of complex-valued 32-bit floating point data. + * + * + * details Performs an N-point Inverse Fast Fourier Transform (IFFT) on + * a complex-valued float32 input stream. The IFFT size N must be a power of 2, + * with valid range: 32 ≤ N ≤ 16384. + * + * param [out] pY Pointer to the IFFT output buffer (complex-valued float32). + * param [in] pX Pointer to the IFFT input buffer (complex-valued float32). + * param [in] pScratch Pointer to a scratch buffer (at least N × 8 bytes). + * param [in] log2N Base-2 logarithm of the IFFT size N. + * + * return Command execution status. + * + * note The input, output and scratch buffers must be separately allocated and non-overlapping. + */ +int32_t CE_TransformIFFT_F32(float *pY, float *pX, float *pScratch, int32_t log2N) { - int status; + int32_t status; + + if (log2N < 4 || log2N > 15) + { + status = FFT_ERROR_SZOUTSIDERANGE; + return status; + } ce_cmdstruct_t cmdstruct; cmdstruct.n_ptr_args = 3; diff --git a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_transform.h b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_transform.h index 661f896e8..a99d54700 100644 --- a/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_transform.h +++ b/mcux/mcux-sdk-ng/drivers/ce/fsl_ce_transform.h @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -10,6 +10,9 @@ #include +// define FFT Error Codes +#define FFT_ERROR_SZOUTSIDERANGE 0xE00B + /*! * @ingroup ce * @defgroup ce_transform CE Transform Functions @@ -30,48 +33,83 @@ extern "C" { #endif /*! - * @brief Calculates N point FFT of a Nx1 vector + * @brief Computes the FFT of complex-valued 16-bit floating point data. * - * Calculates Y = fft(X) where X is a Nx1 complex vector + * @details Performs an N-point Fast Fourier Transform (FFT) on + * a complex-valued float16 input stream. The FFT size N must be a power of 2, + * with valid range: 16 ≤ N ≤ 16384. * - * Data precision and format is as defined by the argument type (except - * *float* is used for float16 data type as well to denote the pointer value) + * @param [out] pY Pointer to the FFT output buffer (complex-valued float16 data). + * @param [in] pX Pointer to the FFT input buffer (complex-valued float16 data). + * @param [in] pScratch Pointer to a scratch buffer (at least N × 4 bytes). + * @param [in] log2N Base-2 logarithm of the FFT size N. * - * @param pY Pointer to buffer for FFT output - * @param pX Pointer to buffer for FFT input - * @param pScratch Pointer to scratch buffer. Must be equal to or greater than size of the output buffer - * @param log2N log2(N), where N is the FFT size + * @return Command execution status. * - * @return Return 0 if succeeded, otherwise return error code. + * @note + * - Data precision and format follow the argument types. + * - `float*` is used to represent float16 pointers. + * - The input, output and scratch buffers must be separately allocated and non-overlapping. */ -int CE_TransformCFFT_F16(float *pY, float *pX, float *pScratch, int log2N); +int32_t CE_TransformCFFT_F16(float *pY, float *pX, float *pScratch, int32_t log2N); /*! - * @copydoc CE_TransformCFFT_F16 + * @brief Computes the FFT of complex-valued 32-bit floating point data. + * + * @details Performs an N-point Fast Fourier Transform (FFT) on + * a complex-valued float32 input stream. The FFT size N must be a power of 2, + * with valid range: 32 ≤ N ≤ 16384. + * + * @param [out] pY Pointer to the FFT output buffer (complex-valued float32). + * @param [in] pX Pointer to the FFT input buffer (complex-valued float32). + * @param [in] pScratch Pointer to a scratch buffer (at least N × 8 bytes). + * @param [in] log2N Base-2 logarithm of the FFT size N. + * + * @return Command execution status. + * + * @note The input, output and scratch buffers must be separately allocated and non-overlapping. */ -int CE_TransformCFFT_F32(float *pY, float *pX, float *pScratch, int log2N); +int32_t CE_TransformCFFT_F32(float *pY, float *pX, float *pScratch, int32_t log2N); /*! - * @brief Calculates N point IFFT of a Nx1 vector + * @brief Computes the IFFT of complex-valued 16-bit floating point data. * - * Calculates Y = ifft(X) where X is a Nx1 complex vector + * @details Performs an N-point Inverse Fast Fourier Transform (IFFT) on + * a complex-valued float16 input stream. The IFFT size N must be a power of 2, + * with valid range: 16 ≤ N ≤ 16384. + * + * @param [out] pY Pointer to the IFFT output buffer (complex-valued float16). + * @param [in] pX Pointer to the IFFT input buffer (complex-valued float16). + * @param [in] pScratch Pointer to a scratch buffer (at least N × 4 bytes). + * @param [in] log2N Base-2 logarithm of the IFFT size N. * - * Data precision and format is as defined by the argument type (except - * *float* is used for float16 data type as well to denote the pointer value) + * @return Command execution status. * - * @param pY Pointer to buffer for IFFT output - * @param pX Pointer to buffer for IFFT input - * @param pScratch Pointer to scratch buffer. Must be equal to or greater than size of the output buffer - * @param log2N log2(N), where N is the IFFT size - * - * @return Return 0 if succeeded, otherwise return error code. + * @note + * - Data precision and format follow the argument types. + * - `float*` is used to represent float16 pointers. + * - The input, output and scratch buffers must be separately allocated and non-overlapping. */ -int CE_TransformIFFT_F16(float *pY, float *pX, float *pScratch, int log2N); +int32_t CE_TransformIFFT_F16(float *pY, float *pX, float *pScratch, int32_t log2N); /*! - * @copydoc CE_TransformIFFT_F16 + * @brief Computes the IFFT of complex-valued 32-bit floating point data. + * + * + * @details Performs an N-point Inverse Fast Fourier Transform (IFFT) on + * a complex-valued float32 input stream. The IFFT size N must be a power of 2, + * with valid range: 32 ≤ N ≤ 16384. + * + * @param [out] pY Pointer to the IFFT output buffer (complex-valued float32). + * @param [in] pX Pointer to the IFFT input buffer (complex-valued float32). + * @param [in] pScratch Pointer to a scratch buffer (at least N × 8 bytes). + * @param [in] log2N Base-2 logarithm of the IFFT size N. + * + * @return Command execution status. + * + * @note The input, output and scratch buffers must be separately allocated and non-overlapping. */ -int CE_TransformIFFT_F32(float *pY, float *pX, float *pScratch, int log2N); +int32_t CE_TransformIFFT_F32(float *pY, float *pX, float *pScratch, int32_t log2N); #ifdef __cplusplus } diff --git a/mcux/mcux-sdk-ng/drivers/cmu_fc/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/cmu_fc/CMakeLists.txt index 2ca1603d6..3d4955d92 100644 --- a/mcux/mcux-sdk-ng/drivers/cmu_fc/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/cmu_fc/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.cmu_fc) - mcux_component_version(2.0.0) + mcux_component_version(2.0.1) mcux_add_source( SOURCES fsl_cmu_fc.c fsl_cmu_fc.h ) mcux_add_include( INCLUDES . ) endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.c b/mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.c index 1aab6f389..13d3ddb8e 100644 --- a/mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.c +++ b/mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.c @@ -189,9 +189,9 @@ void CMU_FC_CalcOptimumThreshold(cmu_fc_config_t *config, float f_ref_clk_min = (float)ref_clk * (1.0f - ref_clk_deviation); config->highThresholdCnt = - (uint32_t)(ceil((double)((f_m_clk_max / f_ref_clk_min) * (float)config->refClockCount + 3.0f))); + (uint32_t)ceilf((f_m_clk_max / f_ref_clk_min) * (float)config->refClockCount + 3.0f); config->lowThresholdCnt = - (uint32_t)(ceil((double)((f_m_clk_min / f_ref_clk_max) * (float)config->refClockCount - 3.0f))); + (uint32_t)ceilf((f_m_clk_min / f_ref_clk_max) * (float)config->refClockCount - 3.0f); } /*! @@ -209,7 +209,7 @@ void CMU_FC_RegisterCallBack(CMU_FC_Type *base, cmu_fc_callback_t cb_func) /* IRQ handler functions overloading weak symbols in the startup */ void CMU_FC_DriverIRQHandler(uint32_t idx) { - if (idx > ARRAY_SIZE(s_cmufcBases)) + if (idx >= ARRAY_SIZE(s_cmufcBases)) { return; } diff --git a/mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.h b/mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.h index 4e8649edc..9b8c79b41 100644 --- a/mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.h +++ b/mcux/mcux-sdk-ng/drivers/cmu_fc/fsl_cmu_fc.h @@ -20,7 +20,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief Defines CMU_FC driver version. */ -#define FSL_CMU_FC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_CMU_FC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*! @} */ /*! @brief List of CMU_FC status */ diff --git a/mcux/mcux-sdk-ng/drivers/cmu_fm/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/cmu_fm/CMakeLists.txt index e7b6bdb98..10268eafc 100644 --- a/mcux/mcux-sdk-ng/drivers/cmu_fm/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/cmu_fm/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.cmu_fm) - mcux_component_version(2.0.0) + mcux_component_version(2.0.1) mcux_add_source( SOURCES fsl_cmu_fm.c fsl_cmu_fm.h ) mcux_add_include( INCLUDES . ) endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.c b/mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.c index 4f53b990b..1470f83c9 100644 --- a/mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.c +++ b/mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.c @@ -174,7 +174,7 @@ void CMU_FM_RegisterCallBack(CMU_FM_Type *base, cmu_fm_callback_t cb_func) /* IRQ handler functions overloading weak symbols in the startup */ void CMU_FM_DriverIRQHandler(uint32_t idx) { - if (idx > ARRAY_SIZE(s_cmufmBases)) + if (idx >= ARRAY_SIZE(s_cmufmBases)) { return; } diff --git a/mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.h b/mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.h index 0776b45eb..b1ff32832 100644 --- a/mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.h +++ b/mcux/mcux-sdk-ng/drivers/cmu_fm/fsl_cmu_fm.h @@ -20,7 +20,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief Defines CMU_FM driver version. */ -#define FSL_CMU_FM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_CMU_FM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*! @} */ /*! @brief List of CMU_FM status */ @@ -214,7 +214,8 @@ static inline void CMU_FM_StopFreqMetering(CMU_FM_Type *base) */ static inline uint32_t CMU_FM_CalcMeteredClkFreq(uint32_t meteredClkCnt, uint32_t refClKCnt, uint32_t refClkFreq) { - return (uint32_t)(((float)meteredClkCnt * (float)refClkFreq) / (float)refClKCnt); + float result = ((float)meteredClkCnt * (float)refClkFreq) / (float)refClKCnt; + return (uint32_t)result; } /*! diff --git a/mcux/mcux-sdk-ng/drivers/common/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/common/CMakeLists.txt index 22ad397d0..e4c134a2a 100644 --- a/mcux/mcux-sdk-ng/drivers/common/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/common/CMakeLists.txt @@ -16,6 +16,7 @@ if(CONFIG_MCUX_COMPONENT_driver.common) cm7f cm33 cm0p + cm85 SOURCES fsl_common_arm.c fsl_common_arm.h diff --git a/mcux/mcux-sdk-ng/drivers/common/fsl_common.h b/mcux/mcux-sdk-ng/drivers/common/fsl_common.h index 49775055f..76b90be6a 100644 --- a/mcux/mcux-sdk-ng/drivers/common/fsl_common.h +++ b/mcux/mcux-sdk-ng/drivers/common/fsl_common.h @@ -161,6 +161,7 @@ enum _status_groups kStatusGroup_XSPI = 108, /*!< Group number for XSPI status codes */ kStatusGroup_PNGDEC = 109, /*!< Group number for PNGDEC status codes */ kStatusGroup_JPEGDEC = 110, /*!< Group number for JPEGDEC status codes */ + kStatusGroup_AUDMIX = 111, /*!< Group number for AUDMIX status codes */ kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ diff --git a/mcux/mcux-sdk-ng/drivers/csi/fsl_csi.c b/mcux/mcux-sdk-ng/drivers/csi/fsl_csi.c index 34a1dbd89..f034909d2 100644 --- a/mcux/mcux-sdk-ng/drivers/csi/fsl_csi.c +++ b/mcux/mcux-sdk-ng/drivers/csi/fsl_csi.c @@ -142,12 +142,12 @@ static void CSI_InitBufferQueue(buf_queue_t *bq) static bool CSI_IsBufferQueueEmpty(buf_queue_t *bq) { - return bq->head == -1; + return (bq->head == -1) && (bq->tail == -1); } static bool CSI_IsBufferQueueFull(buf_queue_t *bq) { - return bq->tail == (CSI_DRIVER_QUEUE_SIZE - 1); + return bq->tail == ((int)CSI_DRIVER_QUEUE_SIZE - 1); } static uint32_t CSI_BufferQueueCount(buf_queue_t *bq) @@ -156,7 +156,7 @@ static uint32_t CSI_BufferQueueCount(buf_queue_t *bq) { return 0; } - return bq->tail - bq->head + 1; + return (uint32_t)(bq->tail - bq->head) + 1U; } static status_t CSI_EnqueueBuffer(buf_queue_t *bq, uint32_t addr) diff --git a/mcux/mcux-sdk-ng/drivers/dac12/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/dac12/CMakeLists.txt index 6c2757caa..ce99d3f28 100644 --- a/mcux/mcux-sdk-ng/drivers/dac12/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/dac12/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.dac12) - mcux_component_version(2.1.1) + mcux_component_version(2.1.2) mcux_add_source(SOURCES fsl_dac12.c fsl_dac12.h) diff --git a/mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.c b/mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.c index abb6b8b1a..0aabdb588 100644 --- a/mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.c +++ b/mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. + * Copyright 2016-2020, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -76,8 +75,11 @@ void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info) { assert(NULL != info); - info->fifoSizeInfo = - (dac12_fifo_size_info_t)(uint32_t)((DAC_PARAM_FIFOSZ_MASK & base->PARAM) >> DAC_PARAM_FIFOSZ_SHIFT); + uint32_t tmp = ((DAC_PARAM_FIFOSZ_MASK & base->PARAM) >> DAC_PARAM_FIFOSZ_SHIFT); + + assert(tmp <= kDAC12_FIFOSize256); + + info->fifoSizeInfo = (dac12_fifo_size_info_t)tmp; } /*! diff --git a/mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.h b/mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.h index 2825c89a3..ca7a594a2 100644 --- a/mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.h +++ b/mcux/mcux-sdk-ng/drivers/dac12/fsl_dac12.h @@ -1,7 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. + * Copyright 2016-2021, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,8 +23,8 @@ /*! @name Driver version */ /*! @{ */ -/*! @brief DAC12 driver version 2.1.1. */ -#define FSL_DAC12_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*! @brief DAC12 driver version 2.1.2. */ +#define FSL_DAC12_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*! @} */ /*! @brief Define "write 1 to clear" flags. */ diff --git a/mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.c b/mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.c index bd112b7c1..89a6270a1 100644 --- a/mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.c +++ b/mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.c @@ -109,7 +109,7 @@ void DCIF_Init(DCIF_Type *base) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && (0 != FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) uint32_t instance = DCIF_GetInstance(base); /* Enable the clock. */ - CLOCK_EnableClock(s_dcifClocks[instance]); + (void)CLOCK_EnableClock(s_dcifClocks[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ DCIF_ResetRegister(base); @@ -130,7 +130,7 @@ void DCIF_Deinit(DCIF_Type *base) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && (0 != FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) uint32_t instance = DCIF_GetInstance(base); /* Disable the clock. */ - CLOCK_DisableClock(s_dcifClocks[instance]); + (void)CLOCK_DisableClock(s_dcifClocks[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } diff --git a/mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.h b/mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.h index 7fc6e9f9d..7484dc6f5 100644 --- a/mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.h +++ b/mcux/mcux-sdk-ng/drivers/dcif/fsl_dcif.h @@ -331,7 +331,7 @@ static inline void DCIF_ClearInterruptStatus(DCIF_Type *base, uint32_t mask) */ static inline void DCIF_SetLayerPosition(DCIF_Type *base, uint8_t layerIndex, uint16_t posy, uint16_t posx) { - if (layerIndex == 0) + if (layerIndex == 0U) { base->CTRLDESC1_L0 = ((uint32_t)posx << DCIF_CTRLDESC1_L0_POSX_SHIFT) | ((uint32_t)posy << DCIF_CTRLDESC1_L0_POSY_SHIFT); @@ -354,7 +354,7 @@ static inline void DCIF_SetLayerPosition(DCIF_Type *base, uint8_t layerIndex, ui */ static inline void DCIF_SetLayerSize(DCIF_Type *base, uint8_t layerIndex, uint16_t width, uint16_t height) { - if (layerIndex == 0) + if (layerIndex == 0U) { base->CTRLDESC2_L0 = ((uint32_t)height << DCIF_CTRLDESC2_L0_HEIGHT_SHIFT) | ((uint32_t)width << DCIF_CTRLDESC2_L0_WIDTH_SHIFT); @@ -386,7 +386,7 @@ void DCIF_SetLayerBufferConfig(DCIF_Type *base, uint8_t layerIndex, const dcif_b */ static inline void DCIF_SetLayerBufferAddr(DCIF_Type *base, uint8_t layerIndex, uint32_t addr) { - if (layerIndex == 0) + if (layerIndex == 0U) { base->CTRLDESC4_L0 = DCIF_CTRLDESC4_L0_ADDR(addr); } @@ -430,7 +430,7 @@ static inline void DCIF_EnableLayer(DCIF_Type *base, uint8_t layerIndex, bool en */ static inline void DCIF_TriggerLayerShadowLoad(DCIF_Type *base, uint8_t layerIndex) { - if (layerIndex == 0) + if (layerIndex == 0U) { base->CTRLDESC0_L0 |= DCIF_CTRLDESC0_L0_SHADOW_LOAD_EN_MASK; } diff --git a/mcux/mcux-sdk-ng/drivers/dma3/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/dma3/CMakeLists.txt index 1cf784f4d..5bfc97222 100644 --- a/mcux/mcux-sdk-ng/drivers/dma3/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/dma3/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.ad_dma3) - mcux_component_version(2.3.0) + mcux_component_version(2.3.1) mcux_add_source(SOURCES fsl_ad_edma.h fsl_ad_edma.c) @@ -12,7 +12,7 @@ if(CONFIG_MCUX_COMPONENT_driver.ad_dma3) endif() if(CONFIG_MCUX_COMPONENT_driver.dma3) - mcux_component_version(2.5.0) + mcux_component_version(2.5.1) mcux_add_source(SOURCES fsl_edma.h fsl_edma.c) diff --git a/mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.c b/mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.c index fc5cf77e4..8c1a539fc 100644 --- a/mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.c +++ b/mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.c @@ -238,17 +238,7 @@ void EDMA_AD_ResetChannel(DMA_AD_Type *base, uint32_t channel) base->CH[channel].CH_CSR |= DMA_CH_CSR_DONE_MASK; /* Reset channel TCD */ - base->CH[channel].TCD_SADDR = 0U; - base->CH[channel].TCD_SOFF = 0U; - base->CH[channel].TCD_ATTR = 0U; - base->CH[channel].TCD_NBYTES_MLOFFNO = 0U; - base->CH[channel].TCD_SLAST_SDA = 0U; - base->CH[channel].TCD_DADDR = 0U; - base->CH[channel].TCD_DOFF = 0U; - base->CH[channel].TCD_CITER_ELINKNO = 0U; - base->CH[channel].TCD_DLAST_SGA = 0U; - base->CH[channel].TCD_CSR = 0U; - base->CH[channel].TCD_BITER_ELINKNO = 0U; + EDMA_AD_TcdReset((edma_tcd_t *)((uint32_t)&base->CH[channel] + 0x00000020)); } /*! @@ -830,6 +820,7 @@ void EDMA_AD_CreateHandle(edma_handle_t *handle, DMA_AD_Type *base, uint32_t cha uint32_t edmaInstance; uint32_t channelIndex; + edma_tcd_t *tcdRegs; handle->base = base; handle->channel = (uint8_t)channel; @@ -847,7 +838,18 @@ void EDMA_AD_CreateHandle(edma_handle_t *handle, DMA_AD_Type *base, uint32_t cha CSR will be 0. Because in order to suit EDMA busy check mechanism in EDMA_AD_SubmitTransfer, CSR must be set 0. */ - EDMA_AD_ResetChannel(base, channel); + tcdRegs = (edma_tcd_t *)((uint32_t)&handle->base->CH[handle->channel] + 0x00000020); + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; + tcdRegs->DLAST_SGA = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; } /*! diff --git a/mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.h b/mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.h index a6b6535c7..75206f0fd 100644 --- a/mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.h +++ b/mcux/mcux-sdk-ng/drivers/dma3/fsl_ad_edma.h @@ -23,7 +23,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1. */ /*! @} */ /*! @brief eDMA transfer configuration */ diff --git a/mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.c b/mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.c index 76e62f5e9..449f80fdd 100644 --- a/mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.c +++ b/mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.c @@ -270,18 +270,7 @@ void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) base->CH[channel].CH_ES |= DMA_CH_ES_ERR_MASK; base->CH[channel].CH_CSR |= DMA_CH_CSR_DONE_MASK; - /* Reset channel TCD */ - base->CH[channel].TCD_SADDR = 0U; - base->CH[channel].TCD_SOFF = 0U; - base->CH[channel].TCD_ATTR = 0U; - base->CH[channel].TCD_NBYTES_MLOFFNO = 0U; - base->CH[channel].TCD_SLAST_SDA = 0U; - base->CH[channel].TCD_DADDR = 0U; - base->CH[channel].TCD_DOFF = 0U; - base->CH[channel].TCD_CITER_ELINKNO = 0U; - base->CH[channel].TCD_DLAST_SGA = 0U; - base->CH[channel].TCD_CSR = 0U; - base->CH[channel].TCD_BITER_ELINKNO = 0U; + EDMA_TcdReset((edma_tcd_t *)((uint32_t)&base->CH[channel] + 0x00000020)); } /*! @@ -860,6 +849,7 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) uint32_t edmaInstance; uint32_t channelIndex; + edma_tcd_t *tcdRegs; handle->base = base; handle->channel = (uint8_t)channel; @@ -879,7 +869,18 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) CSR will be 0. Because in order to suit EDMA busy check mechanism in EDMA_SubmitTransfer, CSR must be set 0. */ - EDMA_ResetChannel(base, channel); + tcdRegs = (edma_tcd_t *)((uint32_t)&handle->base->CH[handle->channel] + 0x00000020); + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; + tcdRegs->DLAST_SGA = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; } /*! diff --git a/mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.h b/mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.h index 537c211a0..0c3c029d9 100644 --- a/mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.h +++ b/mcux/mcux-sdk-ng/drivers/dma3/fsl_edma.h @@ -23,7 +23,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) /*!< Version 2.5.0. */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) /*!< Version 2.5.1. */ /*! @} */ /*! @brief eDMA transfer configuration */ diff --git a/mcux/mcux-sdk-ng/drivers/dmic/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/dmic/CMakeLists.txt index 6575c35ef..46a953a79 100644 --- a/mcux/mcux-sdk-ng/drivers/dmic/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/dmic/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.dmic_dma) - mcux_component_version(2.4.0) + mcux_component_version(2.4.2) mcux_add_source(SOURCES fsl_dmic_dma.c fsl_dmic_dma.h) diff --git a/mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.c b/mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.c index 7fa44c5ff..bf122de55 100644 --- a/mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.c +++ b/mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.c @@ -239,7 +239,10 @@ void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle) { assert(NULL != handle); assert(NULL != handle->rxDmaHandle); - assert(handle->channel >= (uint32_t)kDMIC_ChannelMAX); + if (handle->channel >= (uint32_t)kDMIC_ChannelMAX) + { + handle->channel = kDMIC_Channel0; // Reset channel to a safe default value + } /* Stop transfer. */ DMA_AbortTransfer(handle->rxDmaHandle); diff --git a/mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.h b/mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.h index 13258e0d9..db544dc71 100644 --- a/mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.h +++ b/mcux/mcux-sdk-ng/drivers/dmic/fsl_dmic_dma.h @@ -27,8 +27,8 @@ * @{ */ -/*! @brief DMIC DMA driver version 2.4.1 */ -#define FSL_DMIC_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*! @brief DMIC DMA driver version 2.4.2 */ +#define FSL_DMIC_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) /*! @} */ /*! @brief DMIC transfer structure. */ diff --git a/mcux/mcux-sdk-ng/drivers/dpu_1/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/dpu_1/CMakeLists.txt index aeb7ee4da..4515ffed4 100644 --- a/mcux/mcux-sdk-ng/drivers/dpu_1/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/dpu_1/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.dpu_1) - mcux_component_version(2.2.0) + mcux_component_version(2.3.1) mcux_add_source(SOURCES fsl_dpu.c fsl_dpu.h) diff --git a/mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.c b/mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.c index 9354f8b8e..f75cdd3d0 100644 --- a/mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.c +++ b/mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2023-2024 NXP + * Copyright 2023-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -580,6 +580,11 @@ typedef struct #define DPU_FRAMEGEN_VTCFG2_Vsbp(x) (((uint32_t)(x)&0x3FFFU) << 16U) #define DPU_FRAMEGEN_VTCFG2_VsEn_MASK (1UL << 31U) +/* Bit in MDR7 only */ +#if defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7 +#define DPU_FRAMEGEN_VTCFG2_VsAlign_MASK (1UL << 30U) +#endif + #define DPU_FRAMEGEN_PKICKCONFIG_PKickRow(x) (((uint32_t)(x)&0x3FFFU) << 16U) #define DPU_FRAMEGEN_PKICKCONFIG_PKickCol(x) (((uint32_t)(x)&0x3FFFU) << 0U) #define DPU_FRAMEGEN_PKICKCONFIG_PKickEn_MASK (1UL << 31U) @@ -644,7 +649,6 @@ typedef union _u32_f32 #define DPU_FETCHDECODE9_DYNAMIC_OFFSET 0x91008U #define DPU_FETCHROT9_DYNAMIC_OFFSET 0x86008U #define DPU_ROP9_DYNAMIC_OFFSET 0x41008U -#define DPU_FETCHYUV0_DYNAMIC_OFFSET 0x201008U #define DPU_BLITBLEND9_DYNAMIC_OFFSET 0x71008U #define DPU_H_SCALER9_DYNAMIC_OFFSET 0xB1008U #define DPU_V_SCALER9_DYNAMIC_OFFSET 0xC1008U @@ -652,8 +656,15 @@ typedef union _u32_f32 #define DPU_EXTDST4_DYNAMIC_OFFSET 0x12100CU #define DPU_EXTDST1_DYNAMIC_OFFSET 0x15100CU #define DPU_EXTDST5_DYNAMIC_OFFSET 0x16100CU +#if defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7 +#define DPU_FETCHYUV0_DYNAMIC_OFFSET 0x1F1008U +#define DPU_H_SCALER4_DYNAMIC_OFFSET 0x241008U +#define DPU_V_SCALER4_DYNAMIC_OFFSET 0x251008U +#else +#define DPU_FETCHYUV0_DYNAMIC_OFFSET 0x201008U #define DPU_H_SCALER4_DYNAMIC_OFFSET 0x271008U #define DPU_V_SCALER4_DYNAMIC_OFFSET 0x281008U +#endif #define DPU_LAYERBLEND1_DYNAMIC_OFFSET 0x171008U #define DPU_LAYERBLEND2_DYNAMIC_OFFSET 0x181008U #define DPU_LAYERBLEND3_DYNAMIC_OFFSET 0x191008U @@ -937,10 +948,12 @@ static const dpu_unit_dynamic_reg_offset_t s_dpuUnitDynamicRegOffsetTable[] = { .unit = kDPU_LayerBlend5, .offset = DPU_LAYERBLEND5_DYNAMIC_OFFSET, }, +#if !(defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7) { .unit = kDPU_LayerBlend6, .offset = DPU_LAYERBLEND6_DYNAMIC_OFFSET, }, +#endif }; /*! @@ -1019,7 +1032,7 @@ static DPU_SUBLAYER_CONTROL_Type *DPU_GetSubLayer(DISPLAY_SEERIS_Type *base, dpu static uint32_t DPU_ConvertFloat(float floatValue, uint8_t intBits, uint8_t fracBits) { /* One bit reserved for sign bit. */ - assert(intBits + fracBits < 32U); + assert(intBits + fracBits + 1U < 32U); u32_f32_t u32_f32; uint32_t ret; @@ -1051,7 +1064,7 @@ static uint32_t DPU_ConvertFloat(float floatValue, uint8_t intBits, uint8_t frac /* Set the sign bit. */ if (0U != (floatBits & 0x80000000UL)) { - ret = ((~ret) + 1U) & ~(((uint32_t)-1) << (intBits + fracBits + 1U)); + ret = ((~(uint32_t)ret) + 1U) & ~(0xFFFFFFFFU << (intBits + fracBits + 1U)); } return ret; @@ -1059,13 +1072,25 @@ static uint32_t DPU_ConvertFloat(float floatValue, uint8_t intBits, uint8_t frac void DPU_Init(DISPLAY_SEERIS_Type *base) { - /* No dpu dedicate clock, related root clocks were enabled in dpu_board.c */ - /* Enable domainmask for store9 and extdst0, 1, 4, 5 */ + /* + * No dpu dedicate clock, related root clocks were enabled in dpu_board.c. + * Enable domainmask for store9 and extdst0, 1, 4, 5. + */ +#if defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7 + /* MDR7 version. */ + DISPLAY__SEERIS__DOMAINMA->STOR9DM |= DOMAINMASK_ENABLE; + DISPLAY__SEERIS__DOMAINMA->EXTD0DK0 |= DOMAINMASK_ENABLE; + DISPLAY__SEERIS__DOMAINMA->EXTD4DK0 |= DOMAINMASK_ENABLE; + DISPLAY__SEERIS__DOMAINMA->EXTD1DK0 |= DOMAINMASK_ENABLE; + DISPLAY__SEERIS__DOMAINMA->EXTD5DK0 |= DOMAINMASK_ENABLE; +#else + /* MDR5 version */ base->DOMAINMASK_STORE9_DOMAIN_MASK0 |= DOMAINMASK_ENABLE; base->DOMAINMASK_EXTDST0_DOMAIN_MASK0 |= DOMAINMASK_ENABLE; base->DOMAINMASK_EXTDST4_DOMAIN_MASK0 |= DOMAINMASK_ENABLE; base->DOMAINMASK_EXTDST1_DOMAIN_MASK0 |= DOMAINMASK_ENABLE; base->DOMAINMASK_EXTDST5_DOMAIN_MASK0 |= DOMAINMASK_ENABLE; +#endif } /*! @@ -1131,17 +1156,25 @@ void DPU_PreparePathConfig(DISPLAY_SEERIS_Type *base) kDPU_FetchDecode9, kDPU_Hscaler9, kDPU_Vscaler9, kDPU_Rop9, kDPU_BlitBlend9, kDPU_Store9, kDPU_ExtDst0, kDPU_ExtDst4, kDPU_ExtDst1, kDPU_ExtDst5, kDPU_Hscaler4, kDPU_Vscaler4, kDPU_FetchRot9, kDPU_FetchYuv0, kDPU_FetchYuv1, - kDPU_LayerBlend1, kDPU_LayerBlend2, kDPU_LayerBlend3, kDPU_LayerBlend4, kDPU_FetchYuv2, - kDPU_LayerBlend5, kDPU_LayerBlend6, kDPU_FetchYuv3 + kDPU_LayerBlend1, kDPU_LayerBlend2, kDPU_LayerBlend3, kDPU_LayerBlend4, kDPU_FetchYuv3, + kDPU_LayerBlend5, +#if !(defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7) + kDPU_LayerBlend6, kDPU_FetchYuv2 +#endif }; for (uint32_t i = 0; i < ARRAY_SIZE(dpuUnits); i++) { DPU_SetUnitSrc(base, dpuUnits[i], 0U); } - /* Enable fetchlayer shdldreq Sticky */ +/* Enable fetchlayer shdldreq Sticky */ +#if defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7 + DISPLAY__SEERIS__FETCHLAY->SHDLRCON |= SHDLDREQSTICKY_ENABLE; + DISPLAY__SEERIS__FETCHL13->SHDLRCON |= SHDLDREQSTICKY_ENABLE; +#else base->PIXENG_FETCHLAYER0_SHDLDREQCONTROL |= SHDLDREQSTICKY_ENABLE; base->PIXENG_FETCHLAYER1_SHDLDREQCONTROL |= SHDLDREQSTICKY_ENABLE; +#endif } /*! @@ -1570,7 +1603,7 @@ void DPU_SetLayerBlendConfig(DISPLAY_SEERIS_Type *base, dpu_unit_t unit, const d /* Set alpha mask config. */ layerBlend->CONTROL = ((layerBlend->CONTROL & ~(DPU_LAYERBLEND_CONTROL_AlphaMaskEnable_MASK | DPU_LAYERBLEND_CONTROL_AlphaMaskMode_MASK)) | - DPU_LAYERBLEND_CONTROL_AlphaMaskEnable(config->enableAlphaMask) | + DPU_LAYERBLEND_CONTROL_AlphaMaskEnable(config->enableAlphaMask ? 1U : 0U) | DPU_LAYERBLEND_CONTROL_AlphaMaskMode(config->alphaMaskMode)); } @@ -2300,15 +2333,18 @@ void DPU_InitDisplayTiming(DISPLAY_SEERIS_Type *base, uint8_t displayIndex, cons display->VTCFG2 = DPU_FRAMEGEN_VTCFG2_Vsync(config->vsw - 1UL) | DPU_FRAMEGEN_VTCFG2_Vsbp((uint32_t)config->vbp + config->vsw - 1UL) | +#if defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7 + DPU_FRAMEGEN_VTCFG2_VsEn_MASK | DPU_FRAMEGEN_VTCFG2_VsAlign_MASK; +#else DPU_FRAMEGEN_VTCFG2_VsEn_MASK; +#endif - /* KICK signal set to start of last vertical blanking line. */ - display->PKICKCONFIG = DPU_FRAMEGEN_PKICKCONFIG_PKickRow(config->height) | - DPU_FRAMEGEN_PKICKCONFIG_PKickCol(config->width + 1UL) | + /* Kick signal set to start of last vertical blanking line. */ + display->PKICKCONFIG = DPU_FRAMEGEN_PKICKCONFIG_PKickRow(vtotal + 1UL) | + DPU_FRAMEGEN_PKICKCONFIG_PKickCol((uint32_t)config->width + config->hfp + config->hbp + config->hsw) | DPU_FRAMEGEN_PKICKCONFIG_PKickEn_MASK; - - display->SKICKCONFIG = DPU_FRAMEGEN_SKICKCONFIG_SKickRow(config->height) | - DPU_FRAMEGEN_SKICKCONFIG_SKickCol(config->width + 1UL) | + display->SKICKCONFIG = DPU_FRAMEGEN_SKICKCONFIG_SKickRow(vtotal + 1UL) | + DPU_FRAMEGEN_SKICKCONFIG_SKickCol((uint32_t)config->width + config->hfp + config->hbp + config->hsw) | DPU_FRAMEGEN_SKICKCONFIG_SKickEn_MASK; } @@ -2719,7 +2755,7 @@ status_t DPU_InitFetchUnitWarp(DISPLAY_SEERIS_Type *base, dpu_unit_t unit, const /* Setup warping. */ fetchWarp->WARPCONTROL = DPU_FETCHWARP_WARPCONTROL_WarpBitsPerPixel(config->warpBitsPerPixel) | DPU_FETCHWARP_WARPCONTROL_WarpCoordinateMode(config->coordMode) | - DPU_FETCHWARP_WARPCONTROL_WarpSymmetricOffset(config->enableSymmetricOffset); + DPU_FETCHWARP_WARPCONTROL_WarpSymmetricOffset(config->enableSymmetricOffset ? 1UL : 0UL); fetchWarp->ARBSTARTX = config->arbStartX; fetchWarp->ARBSTARTY = config->arbStartY; @@ -2820,3 +2856,4 @@ status_t DPU_InitWarpCoordinates(DISPLAY_SEERIS_Type *base, dpu_unit_t unit, con return kStatus_Success; } + diff --git a/mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.h b/mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.h index b02ac23ce..0291756f9 100644 --- a/mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.h +++ b/mcux/mcux-sdk-ng/drivers/dpu_1/fsl_dpu.h @@ -1,5 +1,5 @@ /* - * Copyright 2023-2024 NXP + * Copyright 2023-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,7 +21,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief Driver version. */ -#define FSL_DPU_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +#define FSL_DPU_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*@}*/ /*! @brief DPU palette entery number. */ @@ -154,6 +154,36 @@ #define DPU_EXT_DST1_OFFSET 0x150000U #define DPU_CONST_FRAME5_OFFSET 0x140000U #define DPU_EXT_DST5_OFFSET 0x160000U +#define DPU_LAYER_BLEND1_OFFSET 0x170000U +#define DPU_LAYER_BLEND2_OFFSET 0x180000U +#define DPU_LAYER_BLEND3_OFFSET 0x190000U +#define DPU_LAYER_BLEND4_OFFSET 0x1A0000U +#define DPU_LAYER_BLEND5_OFFSET 0x1B0000U +#define DPU_DOMAIN_BLEND0_OFFSET 0x2A0000U +#define DPU_FRAME_GEN0_OFFSET 0x2B0000U +#define DPU_PIPELINE_EXTDST0_OFFSET 0x111000U +#define DPU_PIPELINE_EXTDST1_OFFSET 0x151000U +#define DPU_PIPELINE_EXTDST4_OFFSET 0x121000U +#define DPU_PIPELINE_EXTDST5_OFFSET 0x161000U +#define DPU_PIPELINE_STORE9_OFFSET 0xE1000U +#if defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7 +#define DPU_FETCH_ECO0_OFFSET 0x200000U +#define DPU_FETCH_ECO1_OFFSET 0x220000U +#define DPU_FETCH_LAYER0_OFFSET 0x1c0000U +#define DPU_FETCH_LAYER1_OFFSET 0x1d0000U +#define DPU_H_SCALER4_OFFSET 0x240000U +#define DPU_V_SCALER4_OFFSET 0x250000U +#define DPU_FETCH_YUV0_OFFSET 0x1F0000U +#define DPU_FETCH_YUV1_OFFSET 0x210000U +#define DPU_FETCH_YUV3_OFFSET 0x1E0000U +#define DPU_DOMAIN_BLEND1_OFFSET 0x330000U +#define DPU_FRAME_GEN1_OFFSET 0x340000U +#define DPU_ID_HASH0_OFFSET 0x300000U +#define DPU_SIG0_OFFSET 0x310000U +#define DPU_SIG1_OFFSET 0x3A0000U +#define DPU_DITHER0_CONFIG_OFFSET 0x2F0000U /* Dither 0 config offset */ +#define DPU_DITHER1_CONFIG_OFFSET 0x380000U /* Dither 1 config offset */ +#else #define DPU_FETCH_ECO0_OFFSET 0x210000U #define DPU_FETCH_ECO1_OFFSET 0x230000U #define DPU_FETCH_ECO2_OFFSET 0x250000U @@ -161,19 +191,12 @@ #define DPU_FETCH_LAYER1_OFFSET 0x1e0000U #define DPU_H_SCALER4_OFFSET 0x270000U #define DPU_V_SCALER4_OFFSET 0x280000U -#define DPU_LAYER_BLEND1_OFFSET 0x170000U -#define DPU_LAYER_BLEND2_OFFSET 0x180000U -#define DPU_LAYER_BLEND3_OFFSET 0x190000U -#define DPU_LAYER_BLEND4_OFFSET 0x1A0000U -#define DPU_LAYER_BLEND5_OFFSET 0x1B0000U #define DPU_LAYER_BLEND6_OFFSET 0x1C0000U #define DPU_FETCH_YUV0_OFFSET 0x200000U #define DPU_FETCH_YUV1_OFFSET 0x220000U #define DPU_FETCH_YUV2_OFFSET 0x240000U #define DPU_FETCH_YUV3_OFFSET 0x1F0000U -#define DPU_DOMAIN_BLEND0_OFFSET 0x2a0000U #define DPU_DOMAIN_BLEND1_OFFSET 0x320000U -#define DPU_FRAME_GEN0_OFFSET 0x2B0000U #define DPU_FRAME_GEN1_OFFSET 0x330000U #define DPU_ID_HASH0_OFFSET 0x2C0000U #define DPU_SIG0_OFFSET 0x2d0000U @@ -181,11 +204,7 @@ #define DPU_SIG2_OFFSET 0x2E0000U #define DPU_DITHER0_CONFIG_OFFSET 0x311000U /* Dither 0 config offset */ #define DPU_DITHER1_CONFIG_OFFSET 0x371020U /* Dither 1 config offset */ -#define DPU_PIPELINE_EXTDST0_OFFSET 0x111000U -#define DPU_PIPELINE_EXTDST1_OFFSET 0x151000U -#define DPU_PIPELINE_EXTDST4_OFFSET 0x121000U -#define DPU_PIPELINE_EXTDST5_OFFSET 0x161000U -#define DPU_PIPELINE_STORE9_OFFSET 0xE1000U +#endif #define DPU_ROP_CONTROL_Mode_MASK (1U << 0U) #define DPU_ROP_CONTROL_RedMode_MASK (1U << 7U) @@ -274,16 +293,14 @@ typedef enum _dpu_unit kDPU_ExtDst1 = DPU_MAKE_UNIT(kDPU_ExtDst, kDPU_UnitAttrHasSrc, DPU_EXT_DST1_OFFSET), kDPU_ConstFrame5 = DPU_MAKE_UNIT(kDPU_ConstFrame, 0U, DPU_CONST_FRAME5_OFFSET), kDPU_ExtDst5 = DPU_MAKE_UNIT(kDPU_ExtDst, kDPU_UnitAttrHasSrc, DPU_EXT_DST5_OFFSET), - kDPU_FetchEco2 = DPU_MAKE_UNIT(kDPU_FetchEco, kDPU_UnitAttrIsFetch, DPU_FETCH_ECO2_OFFSET), kDPU_FetchEco0 = DPU_MAKE_UNIT(kDPU_FetchEco, kDPU_UnitAttrIsFetch, DPU_FETCH_ECO0_OFFSET), kDPU_FetchEco1 = DPU_MAKE_UNIT(kDPU_FetchEco, kDPU_UnitAttrIsFetch, DPU_FETCH_ECO1_OFFSET), - kDPU_FetchLayer0 = + kDPU_FetchLayer0 = DPU_MAKE_UNIT(kDPU_FetchLayer, kDPU_UnitAttrIsFetch | kDPU_UnitAttrSubLayer, DPU_FETCH_LAYER0_OFFSET), - kDPU_FetchLayer1 = + kDPU_FetchLayer1 = DPU_MAKE_UNIT(kDPU_FetchLayer, kDPU_UnitAttrIsFetch | kDPU_UnitAttrSubLayer, DPU_FETCH_LAYER1_OFFSET), kDPU_FetchYuv0 = DPU_MAKE_UNIT(KDPU_FetchYuv, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc, DPU_FETCH_YUV0_OFFSET), kDPU_FetchYuv1 = DPU_MAKE_UNIT(KDPU_FetchYuv, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc, DPU_FETCH_YUV1_OFFSET), - kDPU_FetchYuv2 = DPU_MAKE_UNIT(KDPU_FetchYuv, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc, DPU_FETCH_YUV2_OFFSET), kDPU_FetchYuv3 = DPU_MAKE_UNIT(KDPU_FetchYuv, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc, DPU_FETCH_YUV3_OFFSET), kDPU_Hscaler4 = DPU_MAKE_UNIT(kDPU_HScaler, kDPU_UnitAttrHasSrc, DPU_H_SCALER4_OFFSET), kDPU_Vscaler4 = DPU_MAKE_UNIT(kDPU_VScaler, kDPU_UnitAttrHasSrc, DPU_V_SCALER4_OFFSET), @@ -292,7 +309,11 @@ typedef enum _dpu_unit kDPU_LayerBlend3 = DPU_MAKE_UNIT(kDPU_LayerBlend, kDPU_UnitAttrHasSrc, DPU_LAYER_BLEND3_OFFSET), kDPU_LayerBlend4 = DPU_MAKE_UNIT(kDPU_LayerBlend, kDPU_UnitAttrHasSrc, DPU_LAYER_BLEND4_OFFSET), kDPU_LayerBlend5 = DPU_MAKE_UNIT(kDPU_LayerBlend, kDPU_UnitAttrHasSrc, DPU_LAYER_BLEND5_OFFSET), +#if !(defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7) kDPU_LayerBlend6 = DPU_MAKE_UNIT(kDPU_LayerBlend, kDPU_UnitAttrHasSrc, DPU_LAYER_BLEND6_OFFSET), + kDPU_FetchYuv2 = DPU_MAKE_UNIT(KDPU_FetchYuv, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc, DPU_FETCH_YUV2_OFFSET), + kDPU_FetchEco2 = DPU_MAKE_UNIT(kDPU_FetchEco, kDPU_UnitAttrIsFetch, DPU_FETCH_ECO2_OFFSET), +#endif kDPU_DomainBlend0 = DPU_MAKE_UNIT(kDPU_DomainBlend, kDPU_UnitAttrHasSrc, DPU_DOMAIN_BLEND0_OFFSET), kDPU_DomainBlend1 = DPU_MAKE_UNIT(kDPU_DomainBlend, kDPU_UnitAttrHasSrc, DPU_DOMAIN_BLEND1_OFFSET), @@ -318,6 +339,76 @@ enum _dpu_interrupt kDPU_Group0ExtDst5SeqCompleteInterrupt = (1U << 14U), /*!< ExtDst5 sequence complete interrupt. */ kDPU_Group0DomainBlend0ShadowLoadInterrupt = (1U << 15U), /*!< DomainBlend0 shadow load interrupt. */ kDPU_Group0DomainBlend0FrameCompleteInterrupt = (1U << 16U), /*!< DomainBlend0 frame complete interrupt. */ +#if defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7 + kDPU_Group0DiSengcfgShadowLoad0Interrupt = (1U << 17U), /*!< DiSengcfg shadow load0 interrupt */ + kDPU_Group0DiSengcfgFrameComplete0Interrupt = (1U << 18U), /*!< DiSengcfg frame complete0 interrupt. */ + kDPU_Group0DiSengcfgSeqComplete0Interrupt = (1U << 19U), /*!< DiSengcfg sequence complete0 interrupt. */ + kDPU_Group0FrameGen0Int0Interrupt = (1U << 20U), /*!< FrameGen 0 interrupt 0. */ + kDPU_Group0FrameGen0Int1Interrupt = (1U << 21U), /*!< FrameGen 0 interrupt 1. */ + kDPU_Group0FrameGen0Int2Interrupt = (1U << 22U), /*!< FrameGen 0 interrupt 2. */ + kDPU_Group0FrameGen0Int3Interrupt = (1U << 23U), /*!< FrameGen 0 interrupt 3. */ + kDPU_Group0Sig0ShadowLoadInterrupt = (1U << 24U), /*!< Sig0 shadow load interrupt. */ + kDPU_Group0Sig0ValidInterrupt = (1U << 25U), /*!< Sig0 measurement valid interrupt. */ + kDPU_Group0Sig0ErrorInterrupt = (1U << 26U), /*!< Sig0 error interrupt. */ + kDPU_Group0Sig0ClusterErrorInterrupt = (1U << 27U), /*!< Sig0 cluster error interrupt. */ + kDPU_Group0Sig0ClusterMatchInterrupt = (1U << 28U), /*!< Sig0 cluster match interrupt. */ + kDPU_Group0Sig0Idash0ShadowLoadInterrupt = (1U << 29U), /*!< Sig0 IDash0 shadow load interrupt. */ + kDPU_Group0Sig0Idash0ValidInterrupt = (1U << 30U), /*!< Sig0 IDash0 valid interrupt. */ + kDPU_Group0Sig0Idash0WindowErrorInterrupt = (1U << 31U), /*!< Sig0 IDash0 window error interrupt. */ + kDPU_Group1LocalDimming0Irq0Interrupt = (1U << 0U), /*!< Local dimming 0 interrupt 0. */ + kDPU_Group1LocalDimming0Irq1Interrupt = (1U << 1U), /*!< Local dimming 0 interrupt 1. */ + kDPU_Group1LocalDimming0Irq2Interrupt = (1U << 2U), /*!< Local dimming 0 interrupt 2. */ + kDPU_Group1DomainBlend1ShadowLoadInterrupt = (1U << 3U), /*!< DomainBlend1 shadow load interrupt. */ + kDPU_Group1DomainBlend1FrameCompleteInterrupt = (1U << 4U), /*!< DomainBlend1 frame complete interrupt. */ + kDPU_Group1DiSengcfgShadowLoad1Interrupt = (1U << 5U), /*!< DiSengcfg shadow load1 interrupt */ + kDPU_Group1DiSengcfgFrameComplete1Interrupt = (1U << 6U), /*!< DiSengcfg frame complete1 interrupt. */ + kDPU_Group1DiSengcfgSeqComplete1Interrupt = (1U << 7U), /*!< DiSengcfg sequence complete1 interrupt. */ + kDPU_Group1FrameGen1Int0Interrupt = (1U << 8U), /*!< FrameGen 1 interrupt 0. */ + kDPU_Group1FrameGen1Int1Interrupt = (1U << 9U), /*!< FrameGen 1 interrupt 1. */ + kDPU_Group1FrameGen1Int2Interrupt = (1U << 10U), /*!< FrameGen 1 interrupt 2. */ + kDPU_Group1FrameGen1Int3Interrupt = (1U << 11U), /*!< FrameGen 1 interrupt 3. */ + kDPU_Group1Sig1ShadowLoadInterrupt = (1U << 12U), /*!< Sig1 shadow load interrupt. */ + kDPU_Group1Sig1ValidInterrupt = (1U << 13U), /*!< Sig1 measurement valid interrupt. */ + kDPU_Group1Sig1ErrorInterrupt = (1U << 14U), /*!< Sig1 error interrupt. */ + kDPU_Group1Sig1ClusterErrorInterrupt = (1U << 15U), /*!< Sig1 cluster error interrupt. */ + kDPU_Group1Sig1ClusterMatchInterrupt = (1U << 16U), /*!< Sig1 cluster match interrupt. */ + kDPU_Group1Sig1Idash1ShadowLoadInterrupt = (1U << 17U), /*!< Sig1 IDash1 shadow load interrupt. */ + kDPU_Group1Sig1Idash1ValidInterrupt = (1U << 18U), /*!< Sig1 IDash1 valid interrupt. */ + kDPU_Group1Sig1Idash1WindowErrorInterrupt = (1U << 19U), /*!< Sig1 IDash1 window error interrupt. */ + kDPU_Group1CmdSeqErrorInterrupt = (1U << 20U), /*!< CmdSeq Error interrupt. */ + kDPU_Group1ComCtrlSw0Interrupt = (1U << 21U), /*!< ComCtrlSw0 interrupt. */ + kDPU_Group1ComCtrlSw1Interrupt = (1U << 22U), /*!< ComCtrlSw1 interrupt. */ + kDPU_Group1ComCtrlSw2Interrupt = (1U << 23U), /*!< ComCtrlSw1 interrupt. */ + kDPU_Group1ComCtrlSw3Interrupt = (1U << 24U), /*!< ComCtrlSw1 interrupt. */ + kDPU_Group1FrameGen0PrimSyncOnInterrupt = (1U << 25U), /*!< FrameGen 0 primary sync on interrupt. */ + kDPU_Group1FrameGen0PrimSyncOffInterrupt = (1U << 26U), /*!< FrameGen 0 primary sync off interrupt. */ + kDPU_Group1FrameGen0OverFlow0OnInterrupt = (1U << 27U), /*!< FrameGen 0 over flow0 on interrupt. */ + kDPU_Group1FrameGen0OverFlow0OffInterrupt = (1U << 28U), /*!< FrameGen 0 over flow0 off interrupt. */ + kDPU_Group1FrameGen0UnderRun0OnInterrupt = (1U << 29U), /*!< FrameGen 0 under run0 on interrupt. */ + kDPU_Group1FrameGen0UnderRun0OffInterrupt = (1U << 30U), /*!< FrameGen 0 under run0 off interrupt. */ + kDPU_Group1FrameGen0Threshold0RiseInterrupt = (1U << 31U), /*!< FrameGen 0 Threshold0 rise interrupt. */ + kDPU_Group2FrameGen0Threshold0FailInterrupt = (1U << 0U), /*!< FrameGen 0 Threshold0 fail interrupt. */ + kDPU_Group2FrameGen0OverFlow1OnInterrupt = (1U << 1U), /*!< FrameGen 0 over flow1 on interrupt. */ + kDPU_Group2FrameGen0OverFlow1OffInterrupt = (1U << 2U), /*!< FrameGen 0 over flow1 off interrupt. */ + kDPU_Group2FrameGen0UnderRun1OnInterrupt = (1U << 3U), /*!< FrameGen 0 under run1 on interrupt. */ + kDPU_Group2FrameGen0UnderRun1OffInterrupt = (1U << 4U), /*!< FrameGen 0 under run1 off interrupt. */ + kDPU_Group2FrameGen0Threshold1RiseInterrupt = (1U << 5U), /*!< FrameGen 0 Threshold1 rise interrupt. */ + kDPU_Group2FrameGen0Threshold1FailInterrupt = (1U << 6U), /*!< FrameGen 0 Threshold1 fail interrupt. */ + kDPU_Group2FrameGen1PrimSyncOnInterrupt = (1U << 7U), /*!< FrameGen 1 primary sync on interrupt. */ + kDPU_Group2FrameGen1PrimSyncOffInterrupt = (1U << 8U), /*!< FrameGen 1 primary sync off interrupt. */ + kDPU_Group2FrameGen1OverFlow0OnInterrupt = (1U << 9U), /*!< FrameGen 1 over flow0 on interrupt. */ + kDPU_Group2FrameGen1OverFlow0OffInterrupt = (1U << 10U), /*!< FrameGen 1 over flow0 off interrupt. */ + kDPU_Group2FrameGen1UnderRun0OnInterrupt = (1U << 11U), /*!< FrameGen 1 under run0 on interrupt. */ + kDPU_Group2FrameGen1UnderRun0OffInterrupt = (1U << 12U), /*!< FrameGen 1 under run0 off interrupt. */ + kDPU_Group2FrameGen1Threshold0RiseInterrupt = (1U << 13U), /*!< FrameGen 1 Threshold0 rise interrupt. */ + kDPU_Group2FrameGen1Threshold0FailInterrupt = (1U << 14U), /*!< FrameGen 1 Threshold0 fail interrupt. */ + kDPU_Group2FrameGen1OverFlow1OnInterrupt = (1U << 15U), /*!< FrameGen 1 over flow1 on interrupt. */ + kDPU_Group2FrameGen1OverFlow1OffInterrupt = (1U << 16U), /*!< FrameGen 1 over flow1 off interrupt. */ + kDPU_Group2FrameGen1UnderRun1OnInterrupt = (1U << 17U), /*!< FrameGen 1 under run1 on interrupt. */ + kDPU_Group2FrameGen1UnderRun1OffInterrupt = (1U << 18U), /*!< FrameGen 1 under run1 off interrupt. */ + kDPU_Group2FrameGen1Threshold1RiseInterrupt = (1U << 19U), /*!< FrameGen 1 Threshold1 rise interrupt. */ + kDPU_Group2FrameGen1Threshold1FailInterrupt = (1U << 20U), /*!< FrameGen 1 Threshold1 fail interrupt. */ +#else kDPU_Group0DomainBlend0SeqCompleteInterrupt = (1U << 17U), /*!< DomainBlend0 sequence complete interrupt. */ kDPU_Group0DiSengcfgShadowLoad0Interrupt = (1U << 18U), /*!< DiSengcfg shadow load0 interrupt */ kDPU_Group0DiSengcfgFrameComplete0Interrupt = (1U << 19U), /*!< DiSengcfg frame complete0 interrupt. */ @@ -387,6 +478,7 @@ enum _dpu_interrupt kDPU_Group2FrameGen1UnderRun1OffInterrupt = (1U << 19U), /*!< FrameGen 1 under run1 off interrupt. */ kDPU_Group2FrameGen1Threshold1RiseInterrupt = (1U << 20U), /*!< FrameGen 1 Threshold1 rise interrupt. */ kDPU_Group2FrameGen1Threshold1FailInterrupt = (1U << 21U), /*!< FrameGen 1 Threshold1 fail interrupt. */ +#endif }; enum _dpu_unit_source @@ -399,8 +491,9 @@ enum _dpu_unit_source kDPU_UnitSrcFetchRot9 = 5U, /*!< The input source is Rot 9. */ kDPU_UnitSrcFetchDecode9 = 6U, /*!< The input source is fetch decode 9. */ kDPU_UnitSrcFetchEco9 = 7U, /*!< input source is fetch eco 9. */ - kDPU_UnitSrcVScaler9 = 8U, /*!< The input source is VScaler 9. */ - kDPU_UnitSrcFilter9 = 9U, /*!< The input source is Filter 9. */ + kDPU_UnitSrcHscaler9 = 8U, /*!< The input source is HScaler 9. */ + kDPU_UnitSrcVScaler9 = 9U, /*!< The input source is VScaler 9. */ + kDPU_UnitSrcFilter9 = 10U, /*!< The input source is Filter 9. */ kDPU_UnitSrcConstFrame0 = 12U, /*!< The input source is ConstFrame 0. */ kDPU_UnitSrcConstFrame4 = 13U, /*!< The input source is ConstFrame 4. */ kDPU_UnitSrcConstFrame1 = 16U, /*!< The input source is ConstFrame 1. */ @@ -410,20 +503,32 @@ enum _dpu_unit_source kDPU_UnitSrcLayerBlend3 = 22U, /*!< The input source is LayerBlend 3. */ kDPU_UnitSrcLayerBlend4 = 23U, /*!< The input source is LayerBlend 4. */ kDPU_UnitSrcLayerBlend5 = 24U, /*!< The input source is LayerBlend 5. */ +#if defined(FSL_FEATURE_DISPLAY_SEERIS_MDR7) && FSL_FEATURE_DISPLAY_SEERIS_MDR7 + kDPU_UnitSrcFetchLayer0 = 25U, /*!< The input source is FetchLayer 0. */ + kDPU_UnitSrcFetchLayer1 = 26U, /*!< The input source is FetchLayer 1. */ + kDPU_UnitSrcFetchYUV3 = 27U, /*!< The input source is Fetchyuv 3. */ + kDPU_UnitSrcFetchYUV0 = 28U, /*!< The input source is Fetchyuv 0. */ + kDPU_UnitSrcFetchEco0 = 29U, /*!< The input source is FetchEco 0. */ + kDPU_UnitSrcFetchYUV1 = 30U, /*!< The input source is Fetchyuv 1. */ + kDPU_UnitSrcFetchEco1 = 31U, /*!< The input source is FetchEco 1. */ + kDPU_UnitSrcMatrix4 = 32U, /*!< The input source is Matrix 4. */ + kDPU_UnitSrcHScaler4 = 33U, /*!< The input source is HScaler 4. */ + kDPU_UnitSrcVScaler4 = 34U, /*!< The input source is VScaler 4. */ +#else kDPU_UnitSrcLayerBlend6 = 25U, /*!< The input source is LayerBlend 6. */ kDPU_UnitSrcFetchLayer0 = 26U, /*!< The input source is FetchLayer 0. */ kDPU_UnitSrcFetchLayer1 = 27U, /*!< The input source is FetchLayer 1. */ kDPU_UnitSrcFetchYUV3 = 28U, /*!< The input source is Fetchyuv 3. */ kDPU_UnitSrcFetchYUV0 = 29U, /*!< The input source is Fetchyuv 0. */ - kDPU_UnitSrcFetchEco0 = 30U, /*!< The input source is FetchEco 0. */ kDPU_UnitSrcFetchYUV1 = 31U, /*!< The input source is Fetchyuv 1. */ - kDPU_UnitSrcFetchEco1 = 32U, /*!< The input source is FetchEco 1. */ kDPU_UnitSrcFetchYUV2 = 33U, /*!< The input source is Fetchyuv 2. */ - kDPU_UnitSrcFetchEco2 = 34U, /*!< The input source is FetchEco 2. */ kDPU_UnitSrcMatrix4 = 35U, /*!< The input source is Matrix 4. */ kDPU_UnitSrcHScaler4 = 36U, /*!< The input source is HScaler 4. */ kDPU_UnitSrcVScaler4 = 37U, /*!< The input source is VScaler 4. */ - KDPU_UnitSrcExtDst1 = 38U, /*!< The input source is ExtDst 1. */ + kDPU_UnitSrcFetchEco0 = 30U, /*!< The input source is FetchEco 0. */ + kDPU_UnitSrcFetchEco1 = 32U, /*!< The input source is FetchEco 1. */ + kDPU_UnitSrcFetchEco2 = 34U, /*!< The input source is FetchEco 2. */ +#endif }; /*! @brief LayerBlend unit shadow token generate mode. */ diff --git a/mcux/mcux-sdk-ng/drivers/easrc/fsl_asrc.c b/mcux/mcux-sdk-ng/drivers/easrc/fsl_asrc.c index c07f6a8f4..fdd7de665 100644 --- a/mcux/mcux-sdk-ng/drivers/easrc/fsl_asrc.c +++ b/mcux/mcux-sdk-ng/drivers/easrc/fsl_asrc.c @@ -324,7 +324,6 @@ static status_t ASRC_SetSampleRateRatioConfig(ASRC_Type *base, ratio = ((uint64_t)inRate << fracBits) / outRate; - base->RS_RATIO_LOW[context].RS_RATIO_LOW = (uint32_t)(ratio & 0xFFFFFFFFUL); base->RS_RATIO_LOW[context].RS_RATIO_HIGH = ((uint32_t)((ratio >> 32U)) & 0xFFFFFFFFUL); diff --git a/mcux/mcux-sdk-ng/drivers/ecat/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/ecat/CMakeLists.txt index fdb295a38..c2cf45bbe 100644 --- a/mcux/mcux-sdk-ng/drivers/ecat/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/ecat/CMakeLists.txt @@ -1,5 +1,5 @@ if(CONFIG_MCUX_COMPONENT_driver.ecat) - mcux_component_version(2.0.0) + mcux_component_version(2.0.1) mcux_add_source(SOURCES fsl_ecat.c fsl_ecat.h) diff --git a/mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.c b/mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.c index f62a34e34..429f455ba 100644 --- a/mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.c +++ b/mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.c @@ -1,5 +1,5 @@ /* - * Copyright 2022-2024 NXP + * Copyright 2022-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,9 @@ status_t ECAT_EscMdioRead(ECAT_Type *ecat, uint8_t phy_addr, uint8_t reg_addr, u ecat->MII_MANAGEMENT_PDI_ACCESS_STATE = ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF0_MASK; if ((ecat->MII_MANAGEMENT_CONTROL_OR_STATUS & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF15_MASK) != 0U) + { return kStatus_Busy; + } /*Clear the error bits*/ ecat->MII_MANAGEMENT_CONTROL_OR_STATUS = ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF8(0x00); @@ -31,12 +33,18 @@ status_t ECAT_EscMdioRead(ECAT_Type *ecat, uint8_t phy_addr, uint8_t reg_addr, u /*wait command done*/ while ((ecat->MII_MANAGEMENT_CONTROL_OR_STATUS & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF15_MASK) != 0U) + { ; + } if ((ecat->MII_MANAGEMENT_CONTROL_OR_STATUS & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF13_MASK) != 0U) + { return kStatus_Fail; + } if ((ecat->MII_MANAGEMENT_CONTROL_OR_STATUS & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF14_MASK) != 0U) + { return kStatus_Fail; + } *data = ecat->PHY_DATA; @@ -49,7 +57,9 @@ status_t ECAT_EscMdioWrite(ECAT_Type *ecat, uint8_t phy_addr, uint8_t reg_addr, ecat->MII_MANAGEMENT_PDI_ACCESS_STATE = ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF0_MASK; if ((ecat->MII_MANAGEMENT_CONTROL_OR_STATUS & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF15_MASK) != 0U) + { return kStatus_Busy; + } /*Clear the error bits*/ ecat->MII_MANAGEMENT_CONTROL_OR_STATUS = ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF8(0x00); @@ -65,12 +75,18 @@ status_t ECAT_EscMdioWrite(ECAT_Type *ecat, uint8_t phy_addr, uint8_t reg_addr, /*wait command done*/ while ((ecat->MII_MANAGEMENT_CONTROL_OR_STATUS & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF15_MASK) != 0U) + { ; + } if ((ecat->MII_MANAGEMENT_CONTROL_OR_STATUS & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF13_MASK) != 0U) + { return kStatus_Fail; + } if ((ecat->MII_MANAGEMENT_CONTROL_OR_STATUS & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF14_MASK) != 0U) + { return kStatus_Fail; + } return kStatus_Success; } \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.h b/mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.h index 59c719646..e6bc856cd 100644 --- a/mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.h +++ b/mcux/mcux-sdk-ng/drivers/ecat/fsl_ecat.h @@ -1,5 +1,5 @@ /* - * Copyright 2022-2024 NXP + * Copyright 2022-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief eCAT driver version */ -#define FSL_ECAT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +#define FSL_ECAT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ /*! @} */ /*! @brief Returns the first 16Bit of the AL Event register (0x220).*/ diff --git a/mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt index 73c9b7bad..5db123f0e 100644 --- a/mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.edma4) - mcux_component_version(2.10.5) + mcux_component_version(2.10.6) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c b/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c index a3a51896a..6e32fac22 100644 --- a/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c +++ b/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c @@ -56,6 +56,13 @@ static EDMA_Type *const s_edmaBases[] = EDMA_BASE_PTRS; static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE) && FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE +/*! @brief Array to map EDMA instance number to clock name. */ +static const clock_ip_name_t s_edmaTcdClockName[] = EDMA_TCD_CLOCKS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + #if defined(EDMA_RESETS_ARRAY) /* Reset array */ static const reset_ip_name_t s_edmaResets[] = EDMA_RESETS_ARRAY; @@ -203,6 +210,12 @@ void EDMA_Init(EDMA_Type *base, const edma_config_t *config) /* channel transfer configuration */ for (i = 0U; i < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base); i++) { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE) && FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE + /* Ungate EDMA TCD peripheral clock */ + CLOCK_EnableClock(s_edmaTcdClockName[i]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ if (config->channelConfig[i] != NULL) { EDMA_InitChannel(base, i, config->channelConfig[i]); @@ -225,6 +238,16 @@ void EDMA_Deinit(EDMA_Type *base) /* Gate EDMA peripheral clock */ CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE) && FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE + for (uint32_t i = 0U; i < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base); i++) + { + /* Gate EDMA TCD peripheral clock */ + CLOCK_DisableClock(s_edmaTcdClockName[i]); + } +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } #if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG diff --git a/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h b/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h index 19d734111..c53710e5b 100644 --- a/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h +++ b/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 10, 5)) /*!< Version 2.10.5. */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 10, 6)) /*!< Version 2.10.6. */ /*! @} */ /*! @brief eDMA driver name */ diff --git a/mcux/mcux-sdk-ng/drivers/eim/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/eim/CMakeLists.txt index 73f8ad0c7..64f549e9b 100644 --- a/mcux/mcux-sdk-ng/drivers/eim/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/eim/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.eim) - mcux_component_version(2.0.1) + mcux_component_version(2.0.2) mcux_add_source(SOURCES fsl_eim.c fsl_eim.h) diff --git a/mcux/mcux-sdk-ng/drivers/eim/fsl_eim.c b/mcux/mcux-sdk-ng/drivers/eim/fsl_eim.c index 7dc976e7e..561fbe758 100644 --- a/mcux/mcux-sdk-ng/drivers/eim/fsl_eim.c +++ b/mcux/mcux-sdk-ng/drivers/eim/fsl_eim.c @@ -1,8 +1,7 @@ /* - * Copyright 2022 NXP + * Copyright 2022, 2025 NXP * All rights reserved. * - * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,6 +30,11 @@ static EIM_Type *const s_eimBases[] = EIM_BASE_PTRS; /*! @brief Pointers to EIM clocks for each instance. */ static const clock_ip_name_t s_eimClocks[] = EIM_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(EIM_RSTS_N) +/*! @brief Pointers to EIM clocks for each instance. */ +static const clock_ip_name_t s_eimResets[] = EIM_RSTS_N; +#endif /******************************************************************************* * Code ******************************************************************************/ @@ -63,7 +67,10 @@ void EIM_Init(EIM_Type *base) /* Ungate EIM clock. */ CLOCK_EnableClock(s_eimClocks[EIM_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - +#if defined(EIM_RSTS_N) + /* Reset the EIM module */ + RESET_PeripheralReset(s_eimResets[EIM_GetInstance(base)]); +#endif base->EIMCR = 0x00U; base->EICHEN = 0x00U; } @@ -260,42 +267,42 @@ uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel) switch ((uint8_t)channel) { case 0U: - mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT; + mask = (base->EICHD0_WORD1 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT; break; #ifdef EIM_EICHEN_EICH1EN_MASK case 1U: - mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT; + mask = (base->EICHD1_WORD1 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT; break; #endif #ifdef EIM_EICHEN_EICH2EN_MASK case 2U: - mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT; + mask = (base->EICHD2_WORD1 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT; break; #endif #ifdef EIM_EICHEN_EICH3EN_MASK case 3U: - mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT; + mask = (base->EICHD3_WORD1 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT; break; #endif #ifdef EIM_EICHEN_EICH4EN_MASK case 4U: - mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT; + mask = (base->EICHD4_WORD1 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT; break; #endif #ifdef EIM_EICHEN_EICH5EN_MASK case 5U: - mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT; + mask = (base->EICHD5_WORD1 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT; break; #endif #ifdef EIM_EICHEN_EICH6EN_MASK case 6U: - mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT; + mask = (base->EICHD6_WORD1 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT; break; #endif #ifdef EIM_EICHEN_EICH7EN_MASK case 7U: - mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT; + mask = (base->EICHD7_WORD1 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT; break; #endif #ifdef EIM_EICHEN_EICH8EN_MASK diff --git a/mcux/mcux-sdk-ng/drivers/eim/fsl_eim.h b/mcux/mcux-sdk-ng/drivers/eim/fsl_eim.h index 799ff3f20..cf754056d 100644 --- a/mcux/mcux-sdk-ng/drivers/eim/fsl_eim.h +++ b/mcux/mcux-sdk-ng/drivers/eim/fsl_eim.h @@ -1,8 +1,7 @@ /* - * Copyright 2022 NXP + * Copyright 2022, 2025 NXP * All rights reserved. * - * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief Driver version. */ -#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U)) /*! @} */ /******************************************************************************* diff --git a/mcux/mcux-sdk-ng/drivers/endat3/endat3_mem_defs.h b/mcux/mcux-sdk-ng/drivers/endat3/endat3_mem_defs.h index 423e85801..f16464560 100644 --- a/mcux/mcux-sdk-ng/drivers/endat3/endat3_mem_defs.h +++ b/mcux/mcux-sdk-ng/drivers/endat3/endat3_mem_defs.h @@ -316,7 +316,7 @@ #define ENDAT3_MEM_XEL_DEVICEFEATURE_TYPE uint64_t #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_1VPP_TYPE uint16_t #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_TTL_TYPE uint16_t -#define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_TYPEPOS_TYPE uint16_t +#define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_OFFSETPOS_TYPE uint16_t #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_TEMPWARN_TYPE uint16_t #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_BBMT_TYPE uint16_t #define ENDAT3_MEM_XEL_FORMATPOS1ABS_TYPE uint32_t @@ -555,7 +555,7 @@ #define ENDAT3_MEM_XEL_DEVICEFEATURE_SHIFT 0 #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_1VPP_SHIFT 0 #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_TTL_SHIFT 1 -#define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_SHIFTPOS_SHIFT 2 +#define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_OFFSETPOS_SHIFT 2 #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_TEMPWARN_SHIFT 3 #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_BBMT_SHIFT 4 #define ENDAT3_MEM_XEL_FORMATPOS1ABS_SHIFT 0 @@ -793,7 +793,7 @@ #define ENDAT3_MEM_XEL_DEVICEFEATURE_MASK 0xFFFFFFFFFFFF #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_1VPP_MASK 1 #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_TTL_MASK 1 -#define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_MASKPOS_MASK 1 +#define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_OFFSETPOS_MASK 1 #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_TEMPWARN_MASK 1 #define ENDAT3_MEM_XEL_DEVICEFEATURE_SUPP_BBMT_MASK 1 #define ENDAT3_MEM_XEL_FORMATPOS1ABS_MASK 0xFFFFFFFF @@ -1557,6 +1557,7 @@ ~(ENDAT3_MEM_SET_BUSADDRESS_MASK); \ *(ENDAT3_MEM_SET_BUSADDRESS_TYPE *)(((cache)->cacheMem) + (ENDAT3_MEM_SET_BUSADDRESS_OFFSET)) |= \ ((val) & ENDAT3_MEM_SET_BUSADDRESS_MASK) << ENDAT3_MEM_SET_BUSADDRESS_SHIFT; \ + ENDAT3_memCacheSetDirty(cache, ENDAT3_MEM_SET_BUSADDRESS_OFFSET, 1); \ } while(0) #define ENDAT3_MEM_CACHE_WRITE_SET_AXISADDRESS(cache, val) do { \ *(ENDAT3_MEM_SET_AXISADDRESS_TYPE *)(((cache)->cacheMem) + (ENDAT3_MEM_SET_AXISADDRESS_OFFSET)) &= \ diff --git a/mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.c b/mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.c index a975d7a9d..1b771dc31 100644 --- a/mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.c +++ b/mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.c @@ -29,9 +29,10 @@ /******************************************************************************* * Code ******************************************************************************/ +uint32_t timerstamp = 0; __WEAK uint32_t getTimestampMS() { - return 0; + return timerstamp++; } status_t ENDAT3_RxTxClkConfig(ENDAT3_Type *base, uint32_t clk_sys, uint8_t rate, uint16_t watchdag_us) @@ -66,6 +67,7 @@ status_t ENDAT3_RxTxClkConfig(ENDAT3_Type *base, uint32_t clk_sys, uint8_t rate, base->CONFIG_1 = ENDAT3_CONFIG_1_CFG_CLKDIV(clkdiv); base->CONFIG_2 = ENDAT3_CONFIG_2_CFG_DEC_1(dec[1]) | ENDAT3_CONFIG_2_CFG_DEC_0(dec[0]); base->CONFIG_3 = ENDAT3_CONFIG_3_CFG_DEC_3(dec[3]) | ENDAT3_CONFIG_3_CFG_DEC_2(dec[2]); + if (watchDogVal == 0 || watchDogVal > 0xFFFF) { base->CONFIG_4 = ENDAT3_CONFIG_4_CFG_WATCHDOG(0xffff); } else { @@ -83,15 +85,20 @@ status_t ENDAT3_FG_WaitingMasterReady(ENDAT3_Type *base) fg_status = base->FG_STATUS & 0xFF; } - if (fg_status & (ENDAT3_FG_STATUS_STROBE_ERROR_MASK | ENDAT3_FG_STATUS_WD_ERROR_MASK | ENDAT3_FG_STATUS_PHY_ERROR_MASK | ENDAT3_FG_STATUS_CS_ERROR_MASK)) { - if (fg_status & ENDAT3_FG_STATUS_STROBE_ERROR_MASK) - return kStatus_Endat3_FG_Strobe_Error; - else if (fg_status & ENDAT3_FG_STATUS_WD_ERROR_MASK) + if (fg_status & (ENDAT3_FG_STATUS_STROBE_ERROR_MASK | ENDAT3_FG_STATUS_WD_ERROR_MASK | + ENDAT3_FG_STATUS_PHY_ERROR_MASK | ENDAT3_FG_STATUS_CS_ERROR_MASK)) { + if (fg_status & ENDAT3_FG_STATUS_STROBE_ERROR_MASK) { + return kStatus_Endat3_FG_Strobe_Error; + } + else if (fg_status & ENDAT3_FG_STATUS_WD_ERROR_MASK) { return kStatus_Endat3_FG_Watchdog_Error; - else if (fg_status & ENDAT3_FG_STATUS_PHY_ERROR_MASK) + } + else if (fg_status & ENDAT3_FG_STATUS_PHY_ERROR_MASK) { return kStatus_Endat3_FG_PHY_Error; - else if (fg_status & ENDAT3_FG_STATUS_CS_ERROR_MASK) + } + else if (fg_status & ENDAT3_FG_STATUS_CS_ERROR_MASK) { return kStatus_Endat3_FG_CRC_Error; + } } return kStatus_Success; @@ -99,7 +106,8 @@ status_t ENDAT3_FG_WaitingMasterReady(ENDAT3_Type *base) bool ENDAT3_FG_CheckStatus(ENDAT3_Type *base) { - if (base->FG_STATUS & (ENDAT3_FG_STATUS_STROBE_ERROR_MASK | ENDAT3_FG_STATUS_WD_ERROR_MASK | ENDAT3_FG_STATUS_PHY_ERROR_MASK | ENDAT3_FG_STATUS_CS_ERROR_MASK)) + if (base->FG_STATUS & (ENDAT3_FG_STATUS_STROBE_ERROR_MASK | ENDAT3_FG_STATUS_WD_ERROR_MASK | + ENDAT3_FG_STATUS_PHY_ERROR_MASK | ENDAT3_FG_STATUS_CS_ERROR_MASK)) return false; else return true; @@ -156,6 +164,7 @@ status_t ENDAT3_FG_Hello(ENDAT3_Type *base) return kStatus_Endat3_FG_Hello_Failed; } + /*FG Request: Echo */ status_t ENDAT3_FG_Echo(ENDAT3_Type *base, uint16_t arbitrary_data) { @@ -183,7 +192,8 @@ status_t ENDAT3_FG_Echo(ENDAT3_Type *base, uint16_t arbitrary_data) /* FG requests for BUS mode */ -status_t ENDAT3_FG_Bus_Req_Rsp(ENDAT3_Type *base, uint8_t bus_addr, uint8_t req, uint16_t data, uint8_t busCode, uint16_t busData, endat3_rsp_t *rsp) +status_t ENDAT3_FG_Bus_Req_Rsp(ENDAT3_Type *base, uint8_t bus_addr, uint8_t req, uint16_t data, uint8_t busCode, + uint16_t busData, endat3_rsp_t *rsp) { status_t status; ENDAT3_FG_Bus_Req(base, req, data, busCode, busData); @@ -202,7 +212,7 @@ status_t ENDAT3_FG_Bus_Req_Rsp(ENDAT3_Type *base, uint8_t bus_addr, uint8_t req, status_t ENDAT3_FG_Bus_P2P_Hello(ENDAT3_Type *base, uint8_t addr) { status_t status; - uint32_t timeOutMS = getTimestampMS() + ENDAT3_HELLO_TIMEOUT; + uint32_t timeOutMS = getTimestampMS() + 200; do { status = ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_HELLO, ENDAT3_FG_DATA_HELLO, NULL); @@ -215,6 +225,29 @@ status_t ENDAT3_FG_Bus_P2P_Hello(ENDAT3_Type *base, uint8_t addr) return kStatus_Endat3_FG_Hello_Failed; } +/* FG Request: RATE */ +status_t ENDAT3_FG_Bus_Rate_Switch(ENDAT3_Type *base, uint8_t nodes_num, uint8_t rate) +{ + status_t status = kStatus_Success; + uint8_t addr = 1; + + while (addr <= nodes_num ) { + if (ENDAT3_FG_Bus_P2P_Rate(base, addr, rate) != kStatus_Success) { + status = kStatus_Endat3_FG_RATE_Failed; + } + addr++; + } + + addr = 1; + while (addr <= nodes_num) { + if (ENDAT3_FG_Bus_P2P_Hello(base, addr) != kStatus_Success) { + status = kStatus_Endat3_FG_Hello_Failed; + } + addr++; + } + return status; +} + /*FG Request: Echo */ status_t ENDAT3_FG_Bus_P2P_Echo(ENDAT3_Type *base, uint8_t addr, uint16_t arbitrary_data) { @@ -248,32 +281,21 @@ void ENDAT3_BG_Req(ENDAT3_Type *base, uint8_t bus_addr, struct BGREQ *req, uint8 uint64_t req64 = ((uint64_t)req_h32 << 32) | req_l32; base->BG_REQ_0 = ENDAT3_BG_REQ_0_BG_ADDR(bus_addr); base->BG_REQ_1 = ENDAT3_BG_REQ_1_BG_REQ_LO(req64 & 0xFFFFFFFF); - base->BG_REQ_2 = ENDAT3_BG_REQ_2_BG_REQ_HI(req64 >> 32) | ENDAT3_BG_REQ_2_BG_STROBE(1) | ENDAT3_BG_REQ_2_WAIT_RSP(wait_rsp); -} - -void ENDAT3_BG_WaitReqEmpty(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes) -{ - while (!(base->BG_RSP_1 & ENDAT3_BG_RSP_1_BG_REQ_EMPTY_MASK)) { - if (fg_strobes) { -#if (ENDAT3_PARTICIPANTS_NUM > 1) - ENDAT3_FG_Bus_P2P_Data(base, bus_addr, ENDAT3_FG_REQ_DATA0, NULL); -#else - ENDAT3_FG_Data(base, ENDAT3_FG_REQ_DATA0, NULL); -#endif - } - } + base->BG_REQ_2 = ENDAT3_BG_REQ_2_BG_REQ_HI(req64 >> 32) | ENDAT3_BG_REQ_2_BG_STROBE(1) | + ENDAT3_BG_REQ_2_WAIT_RSP(wait_rsp); } -status_t ENDAT3_BG_WaitReqFinished(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes, uint32_t timeout_ms) +status_t ENDAT3_BG_WaitReqFinished(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes, uint32_t timeout_ms, + enum op_mode op) { uint32_t timeout = getTimestampMS() + timeout_ms; while (!(base->BG_RSP_1 & (ENDAT3_BG_RSP_1_BG_HANDLER_IDLE_MASK | ENDAT3_BG_RSP_1_BG_HANDLER_ERROR_MASK))) { if (fg_strobes) { -#if (ENDAT3_PARTICIPANTS_NUM > 1) - ENDAT3_FG_Bus_P2P_Data(base, bus_addr, ENDAT3_FG_REQ_DATA0, NULL); -#else - ENDAT3_FG_Data(base, ENDAT3_FG_REQ_DATA0, NULL); -#endif + if (op == Point2Point) { + ENDAT3_FG_Data(base, ENDAT3_FG_REQ_DATA0, NULL); + } else if (op == Peer2Peer) { + ENDAT3_FG_Bus_P2P_Data(base, bus_addr, ENDAT3_FG_REQ_DATA0, NULL); + } } if (base->BG_RSP_1 & ENDAT3_BG_RSP_1_BG_HANDLER_ERROR_MASK) { @@ -281,36 +303,53 @@ status_t ENDAT3_BG_WaitReqFinished(ENDAT3_Type *base, uint8_t bus_addr, uint8_t } if (timeout_ms && getTimestampMS() > timeout) { + base->BG_REQ_2 |= ENDAT3_BG_REQ_2_BG_ABORT_MASK; return kStatus_Timeout; } } return kStatus_Success; } -uint64_t ENDAT3_BG_GetRsp(ENDAT3_Type *base) +status_t ENDAT3_BG_GetRsp(ENDAT3_Type *base, uint64_t *rsp, uint32_t timeout_ms) { - uint64_t temp = ((base->BG_RSP_1 & ENDAT3_BG_RSP_1_BG_RSP_HI_MASK)); - return ((temp <<32) | base->BG_RSP_0); + uint32_t timeout = getTimestampMS() + timeout_ms; + uint64_t temp; + while (!(base->BG_RSP_1 & (ENDAT3_BG_RSP_1_BG_RSP_DATA_UPDATED_MASK))) { + if (timeout_ms && getTimestampMS() > timeout) { + return kStatus_Timeout; + } + } + temp = ((base->BG_RSP_1 & ENDAT3_BG_RSP_1_BG_RSP_HI_MASK)); + *rsp = (((temp)) <<32) | base->BG_RSP_0; + return kStatus_Success; } -status_t ENDAT3_BG_Req_Rsp(ENDAT3_Type *base, uint8_t bus_addr, struct BGREQ *req, uint64_t *rsp, uint8_t fg_strobes, uint32_t timeout_ms) +status_t ENDAT3_BG_Req_Rsp(ENDAT3_Type *base, uint8_t bus_addr, struct BGREQ *req, uint64_t *rsp, uint8_t fg_strobes, + uint32_t timeout_ms, enum op_mode op) { - ENDAT3_BG_WaitReqEmpty(base, bus_addr, fg_strobes); - ENDAT3_BG_Req(base, bus_addr, req, 1); - ENDAT3_BG_WaitReqFinished(base, bus_addr, fg_strobes, timeout_ms); + uint8_t wait_rsp; + status_t status; + if (rsp != NULL) + wait_rsp = 1; + else + wait_rsp = 0; - if (base->BG_RSP_1 & ENDAT3_BG_RSP_1_BG_HANDLER_ERROR_MASK) { - return kStatus_Endat3_BG_Handler_Error; + ENDAT3_BG_Req(base, bus_addr, req, wait_rsp); + if ((status = ENDAT3_BG_WaitReqFinished(base, bus_addr, fg_strobes, timeout_ms, op)) != kStatus_Success) { + return status; } - *rsp = ENDAT3_BG_GetRsp(base); - if (base->BG_RSP_1 & ENDAT3_BG_RSP_1_BG_ERR_EXEC_MASK) { - return kStatus_Endat3_BG_Excute_Error; + if (rsp != NULL) { + if ((status = ENDAT3_BG_GetRsp(base, rsp, timeout_ms) != kStatus_Success)) { + return status; + } } + return kStatus_Success; } -status_t ENDAT3_BG_Nop(ENDAT3_Type *base, uint8_t bus_addr, uint64_t arbitrary, uint64_t *bg_rsp, uint8_t fg_strobes) +status_t ENDAT3_BG_Nop_OP(ENDAT3_Type *base, uint8_t bus_addr, uint64_t arbitrary, uint64_t *bg_rsp, uint8_t fg_strobes, + enum op_mode op) { struct BGREQ req = {0}; @@ -321,10 +360,10 @@ status_t ENDAT3_BG_Nop(ENDAT3_Type *base, uint8_t bus_addr, uint64_t arbitrary, req.NOP.arbitrary[3] = (arbitrary >> 8) & 0xFF; req.NOP.arbitrary[4] = arbitrary & 0xFF; - return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, bg_rsp, fg_strobes, 2); + return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, bg_rsp, fg_strobes, ENDAT3_BG_REQ_TIMEOUT, op); } -status_t ENDAT3_BG_Reconfigure(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes) +status_t ENDAT3_BG_Reconfigure_OP(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes, enum op_mode op) { struct BGREQ req = {0}; uint64_t bg_rsp; @@ -335,10 +374,11 @@ status_t ENDAT3_BG_Reconfigure(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_s req.RECONFIGURE.res1[2] = 0; req.RECONFIGURE.res1[3] = 0; req.RECONFIGURE.res1[4] = 0; - return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, 100); + return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, ENDAT3_BG_REQ_TIMEOUT, op); } -status_t ENDAT3_BG_Read(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint8_t num_words, uint16_t *words, uint8_t fg_strobes) +status_t ENDAT3_BG_Read_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint8_t num_words, uint16_t *words, + uint8_t fg_strobes, enum op_mode op) { struct BGREQ req = {0}; uint64_t bg_rsp; @@ -349,8 +389,9 @@ status_t ENDAT3_BG_Read(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint req.READ.addr[2] = (addr) & 0xFF; req.READ.num_words = num_words; - status = ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, 6); - + status = ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, ENDAT3_BG_REQ_TIMEOUT, op); + if (status != kStatus_Success) + return status; if (num_words > 0) { words[0] = bg_rsp & 0xFFFF; } @@ -366,7 +407,8 @@ status_t ENDAT3_BG_Read(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint return status; } -status_t ENDAT3_BG_Write(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, const uint16_t word, uint8_t fg_strobes) +status_t ENDAT3_BG_Write_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, const uint16_t word, + uint8_t fg_strobes, enum op_mode op) { struct BGREQ req = {0}; uint64_t bg_rsp; @@ -377,31 +419,33 @@ status_t ENDAT3_BG_Write(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, con req.WRITE.addr[2] = (addr) & 0xFF; req.WRITE.data[0] = (word >> 8) & 0xFF; req.WRITE.data[1] = (word) & 0xFF; - - return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, 10); + return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, ENDAT3_BG_REQ_TIMEOUT, op); } -status_t ENDAT3_BG_Auth(ENDAT3_Type *base, uint8_t bus_addr, uint8_t usrlevel, uint32_t pass, uint8_t fg_strobes) +status_t ENDAT3_BG_Auth_OP(ENDAT3_Type *base, uint8_t bus_addr, uint8_t usrlevel, uint32_t pass, uint8_t fg_strobes, + enum op_mode op) { struct BGREQ req = {0}; uint64_t bg_rsp; req.AUTH.code = ENDAT3_BG_OPCODE_AUTH; req.AUTH.usrlevel = usrlevel; req.AUTH.pass = BSWAP32(pass); - return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, 20); + return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, ENDAT3_BG_REQ_TIMEOUT, op); } -status_t ENDAT3_BG_Setpass(ENDAT3_Type *base, uint8_t bus_addr, uint8_t usrlevel, uint32_t pass, uint8_t fg_strobes) +status_t ENDAT3_BG_Setpass_OP(ENDAT3_Type *base, uint8_t bus_addr, uint8_t usrlevel, uint32_t pass, uint8_t fg_strobes, + enum op_mode op) { struct BGREQ req = {0}; uint64_t bg_rsp; req.SETPASS.code = ENDAT3_BG_OPCODE_SETPASS; req.SETPASS.usrlevel = usrlevel; req.SETPASS.pass = BSWAP32(pass); - return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, 20); + return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, ENDAT3_BG_REQ_TIMEOUT, op); } -status_t ENDAT3_BG_Protect(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint8_t mode, const uint8_t acclevel, uint8_t *al_write, uint8_t *al_read, uint8_t fg_strobes) +status_t ENDAT3_BG_Protect_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint8_t mode, const uint8_t acclevel, + uint8_t *al_write, uint8_t *al_read, uint8_t fg_strobes, enum op_mode op) { struct BGREQ req = {0}; uint64_t bg_rsp; @@ -413,7 +457,7 @@ status_t ENDAT3_BG_Protect(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, u req.PROTECT.mode = mode; req.PROTECT.acclevel = acclevel; - status = ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, 20); + status = ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, ENDAT3_BG_REQ_TIMEOUT, op); *al_write = (bg_rsp >> 8) & 0xFF; *al_read = bg_rsp & 0xFF; @@ -421,16 +465,17 @@ status_t ENDAT3_BG_Protect(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, u return status; } -status_t ENDAT3_BG_Locate(ENDAT3_Type *base, uint8_t bus_addr, uint8_t ctrl, uint8_t fg_strobes) +status_t ENDAT3_BG_Locate_OP(ENDAT3_Type *base, uint8_t bus_addr, uint8_t ctrl, uint8_t fg_strobes, enum op_mode op) { struct BGREQ req = {0}; uint64_t bg_rsp; req.LOCATE.code = ENDAT3_BG_OPCODE_LOCATE; req.LOCATE.ctrl = ctrl; - return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, 20); + return ENDAT3_BG_Req_Rsp(base, bus_addr, &req, &bg_rsp, fg_strobes, ENDAT3_BG_REQ_TIMEOUT, op); } -status_t ENDAT3_memRead(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint16_t n_words, uint16_t *pbuf, uint8_t fg_strobes) +status_t ENDAT3_memRead_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint16_t n_words, uint16_t *pbuf, + uint8_t fg_strobes, enum op_mode op) { int n; uint16_t words[3]; @@ -447,7 +492,7 @@ status_t ENDAT3_memRead(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uin n_words = 0; } - if ((status = ENDAT3_BG_Read(base, bus_addr, addr, n, words, fg_strobes)) != kStatus_Success) { + if ((status = ENDAT3_BG_Read_OP(base, bus_addr, addr, n, words, fg_strobes, op)) != kStatus_Success) { return status; } @@ -458,11 +503,12 @@ status_t ENDAT3_memRead(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uin return kStatus_Success; } -status_t ENDAT3_memWrite(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint16_t n_words, uint16_t *pbuf, uint8_t fg_strobes) +status_t ENDAT3_memWrite_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint16_t n_words, uint16_t *pbuf, + uint8_t fg_strobes, enum op_mode op) { status_t status; while (n_words > 0) { - if ((status = ENDAT3_BG_Write(base, bus_addr, addr, *pbuf, fg_strobes)) != kStatus_Success) { + if ((status = ENDAT3_BG_Write_OP(base, bus_addr, addr, *pbuf, fg_strobes, op)) != kStatus_Success) { return status; } addr++; @@ -473,12 +519,13 @@ status_t ENDAT3_memWrite(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, ui return kStatus_Success; } -status_t ENDAT3_memCacheInit(ENDAT3_Type *base, uint8_t bus_addr, uint32_t mem_base, endat3_mem_cache_t *cache, uint16_t *pbuf, uint32_t pbufSize, uint8_t fg_strobes) +status_t ENDAT3_memCacheInit_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t mem_base, endat3_mem_cache_t *cache, + uint16_t *pbuf, uint32_t pbufSize, uint8_t fg_strobes, enum op_mode op) { cache->memBase = mem_base; cache->cacheMem = pbuf; cache->cacheMemSize = pbufSize; - cache->memSize = ENDAT3_memGetRangeSize(base, bus_addr, mem_base, fg_strobes); + cache->memSize = ENDAT3_memGetRangeSize_OP(base, bus_addr, mem_base, fg_strobes, op); if (cache->memSize == 0) { return kStatus_Endat3_MEM_Cache_Not_Initialized; } @@ -510,13 +557,14 @@ int ENDAT3_memCacheDirty(endat3_mem_cache_t *cache, int word_index) return cache->dirtyWordMap[mod_index] & (1 << mod_bit); } -status_t ENDAT3_memCacheFlush(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes) +status_t ENDAT3_memCacheFlush_OP(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes, + enum op_mode op) { int i; status_t status; for (i = 0; i < cache->memSize; i++) { if (ENDAT3_memCacheDirty(cache, i)) { - status = ENDAT3_BG_Write(base, bus_addr, cache->memBase + i, cache->cacheMem[i], fg_strobes); + status = ENDAT3_BG_Write_OP(base, bus_addr, cache->memBase + i, cache->cacheMem[i], fg_strobes, op); if (status != kStatus_Success) { return status; } @@ -526,17 +574,19 @@ status_t ENDAT3_memCacheFlush(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_ca return kStatus_Success; } -status_t ENDAT3_memCacheFetch(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes) +status_t ENDAT3_memCacheFetch_OP(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes, + enum op_mode op) { status_t status; - if ((status = ENDAT3_memRead(base, bus_addr, cache->memBase, cache->memSize, cache->cacheMem, fg_strobes)) != kStatus_Success) { + if ((status = ENDAT3_memRead_OP(base, bus_addr, cache->memBase, cache->memSize, cache->cacheMem, fg_strobes, op)) + != kStatus_Success) { return status; } memset(cache->dirtyWordMap, 0, sizeof(uint32_t) * MAX_MEMORY_AREA_SIZE/32); return status; } -uint16_t ENDAT3_memGetRangeSize(ENDAT3_Type *base, uint8_t bus_addr, uint32_t mem_base, uint8_t fg_strobes) +uint16_t ENDAT3_memGetRangeSize_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t mem_base, uint8_t fg_strobes, enum op_mode op) { uint32_t addr; uint16_t size; @@ -570,10 +620,9 @@ uint16_t ENDAT3_memGetRangeSize(ENDAT3_Type *base, uint8_t bus_addr, uint32_t me case ENDAT3_MEM_BASE_FEATURE2: addr = ENDAT3_MEM_FEATURE2_SIZE_OFFSET; break; default: return 0; - } - if (ENDAT3_memRead(base, bus_addr, addr, 1, &size, fg_strobes) != kStatus_Success) { + if (ENDAT3_memRead_OP(base, bus_addr, addr, 1, &size, fg_strobes, op) != kStatus_Success) { return 0; } @@ -679,11 +728,12 @@ void ENDAT3_lpfCacheSetPointer(uint8_t z, endat3_mem_cache_t *lpf_cache, uint16_ void ENDAT3_lpfCacheSetXdimYdim(uint8_t z, endat3_mem_cache_t *lpf_cache, uint8_t xdim, uint8_t y_dim) { uint8_t z_list, xy_dim, *addr; + z_list = z - 1; if (y_dim == 0) { - return; + xy_dim = (xdim << 4) | ((y_dim) & 0xF); + } else { + xy_dim = (xdim << 4) | ((y_dim - 1) & 0xF); } - z_list = z - 1; - xy_dim = (xdim << 4) | ((y_dim - 1) & 0xF); addr = (uint8_t *)(lpf_cache->cacheMem + ENDAT3_MEM_LPFSET_LPFLIVE_HEAD_YDIM_1_OFFSET + z_list / 2); ENDAT3_memCacheSetDirty(lpf_cache, ENDAT3_MEM_LPFSET_LPFLIVE_HEAD_YDIM_1_OFFSET + z_list / 2, 1); addr += z_list % 2; @@ -698,12 +748,13 @@ void ENDAT3_lpfCacheListSetFid(endat3_mem_cache_t *lpf_cache, uint8_t xdim, uint *addr = fid; } -void ENDAT3_lpfCacheListSetSendlist(endat3_mem_cache_t *lpf_cache, uint8_t z, uint8_t xdim, uint8_t ydim, uint16_t pointer, uint8_t *fids) +void ENDAT3_lpfCacheListSetSendlist(endat3_mem_cache_t *lpf_cache, uint8_t z, uint8_t xdim, uint8_t ydim, uint16_t pointer, + uint8_t *fids) { uint8_t x, y; ENDAT3_lpfCacheSetPointer(z, lpf_cache, pointer); ENDAT3_lpfCacheSetXdimYdim(z, lpf_cache, xdim, ydim); - for(y = 0;y < ydim; y++) { + for(y = 0; y < ydim; y++) { for (x = 0; x < xdim; x++) { ENDAT3_lpfCacheListSetFid(lpf_cache, xdim, x, y, pointer, fids[y * xdim + x]); } @@ -717,15 +768,16 @@ uint8_t ENDAT3_lpfCacheListGetFid(endat3_mem_cache_t *lpf_cache, uint8_t xdim, u return *addr; } -status_t ENDAT3_lpfCacheUpdateFromEnconder(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *lpf_cache, uint16_t *pdat, uint32_t pdat_size, uint8_t from_set, uint8_t fg_strobes) +status_t ENDAT3_lpfCacheUpdateFromEnconder_OP(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *lpf_cache, uint16_t *pdat, + uint32_t pdat_size, uint8_t from_set, uint8_t fg_strobes, enum op_mode op) { uint32_t mem_actual_size; status_t status; if (from_set) { - mem_actual_size = ENDAT3_memGetRangeSize(base, bus_addr, ENDAT3_MEM_BASE_LPFSET, fg_strobes); + mem_actual_size = ENDAT3_memGetRangeSize_OP(base, bus_addr, ENDAT3_MEM_BASE_LPFSET, fg_strobes, op); lpf_cache->memBase = ENDAT3_MEM_BASE_LPFSET; } else { - mem_actual_size = ENDAT3_memGetRangeSize(base, bus_addr, ENDAT3_MEM_BASE_LPFLIVE, fg_strobes); + mem_actual_size = ENDAT3_memGetRangeSize_OP(base, bus_addr, ENDAT3_MEM_BASE_LPFLIVE, fg_strobes, op); lpf_cache->memBase = ENDAT3_MEM_BASE_LPFLIVE; } @@ -736,7 +788,7 @@ status_t ENDAT3_lpfCacheUpdateFromEnconder(ENDAT3_Type *base, uint8_t bus_addr, lpf_cache->memSize = mem_actual_size; lpf_cache->cacheMem = pdat; - if ((status = ENDAT3_memCacheFetch(base, bus_addr, lpf_cache, fg_strobes)) != kStatus_Success) { + if ((status = ENDAT3_memCacheFetch_OP(base, bus_addr, lpf_cache, fg_strobes, op)) != kStatus_Success) { return status; } @@ -744,13 +796,15 @@ status_t ENDAT3_lpfCacheUpdateFromEnconder(ENDAT3_Type *base, uint8_t bus_addr, return status; } -status_t ENDAT3_lpfCacheFlushToEncoder(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *lpf_cache, uint8_t fg_strobes) +status_t ENDAT3_lpfCacheFlushToEncoder_OP(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *lpf_cache, + uint8_t fg_strobes, enum op_mode op) { ENDAT3_memCacheUpdataCS(lpf_cache); - return ENDAT3_memCacheFlush(base, bus_addr, lpf_cache, fg_strobes); + return ENDAT3_memCacheFlush_OP(base, bus_addr, lpf_cache, fg_strobes, op); } -void ENDAT3_lpfCacheListUpdate(endat3_mem_cache_t *global_cache, endat3_mem_cache_t *lpf_cache, uint8_t z, uint8_t xdim, uint8_t ydim, uint16_t pointer, uint8_t *fid) +void ENDAT3_lpfCacheListUpdate(endat3_mem_cache_t *global_cache, endat3_mem_cache_t *lpf_cache, uint8_t z, + uint8_t xdim, uint8_t ydim, uint16_t pointer, uint8_t *fid) { int32_t i,j; ENDAT3_lpfCacheSetPointer(z, global_cache, pointer); @@ -777,7 +831,6 @@ uint8_t ENDAT3_FIDMEM_getTimestamp(ENDAT3_Type *base, uint8_t bus_addr, uint8_t return temp->fid.timeStamp; } - uint8_t ENDAT3_lpfGetLPFVByFID(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fid) { @@ -793,32 +846,58 @@ uint64_t ENDAT3_FIDMEM_getData(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fid) } /* Assign bus address for all encoders */ -status_t ENDAT3_Bus_Assign_Address(ENDAT3_Type *base, uint8_t encoderNum) +status_t ENDAT3_Bus_Assign_Address(ENDAT3_Type *base, uint8_t address) { - int i; status_t status; - uint16_t cache_buf[0x100]; + uint16_t cache_buf[0x100] = {0}; endat3_mem_cache_t mem_cache; - for (i = encoderNum; i > 0; i--) { - if ((status = ENDAT3_memCacheInit(base, 0, ENDAT3_MEM_BASE_SET, &mem_cache, cache_buf, 0x100, 1)) != kStatus_Success) - return status; - if ((status = ENDAT3_memCacheFetch(base, 0, &mem_cache, 1)) != kStatus_Success) - return status; - if ((status = ENDAT3_memCacheCheckCS(&mem_cache)) != kStatus_Success) - return status; + if ((status = ENDAT3_memCacheInit_OP(base, 0, ENDAT3_MEM_BASE_SET, &mem_cache, cache_buf, 0x100, 1, Peer2Peer)) != kStatus_Success) { + return status; + } + if ((status = ENDAT3_memCacheFetch_OP(base, 0, &mem_cache, 1, Peer2Peer)) != kStatus_Success) { + return status; + } - ENDAT3_MEM_CACHE_WRITE_SET_BUSADDRESS(&mem_cache, i); - if ((status = ENDAT3_lpfCacheFlushToEncoder(base, 0, &mem_cache, 1)) != kStatus_Success) - return status; - if ((status = ENDAT3_FG_Bus_P2P_Reset(base, 0)) != kStatus_Success) - return status; - if ((status = ENDAT3_FG_Bus_P2P_Hello(base, i)) != kStatus_Success) - return status; + ENDAT3_MEM_CACHE_WRITE_SET_BUSADDRESS(&mem_cache, address); + ENDAT3_memCacheUpdataCS(&mem_cache); + if ((status = ENDAT3_Bus_P2P_memCacheFlush(base, 0, &mem_cache, 1)) != kStatus_Success) { + return status; } + + ENDAT3_FG_Bus_P2P_Reset(base, 0); + return kStatus_Success; } +status_t ENDAT3_Bus_Hello_ForAllParticipants(ENDAT3_Type *base, int nodes_num) +{ + status_t status = kStatus_Success; + for (int i = nodes_num; i > 0; i--) { + ENDAT3_FG_Hello(base); + if (ENDAT3_FG_Bus_P2P_Hello(base, i) != kStatus_Success) { + status = kStatus_Endat3_FG_ECHO_Failed; + } + } + return status; +} + +void ENDAT3_Bus_Init_ForAllParticipants(ENDAT3_Type *base, int nodes_num) +{ + uint32_t address[8] = {0}; + uint32_t index = 0; + for (int i = nodes_num; i >= 0; i--) { + ENDAT3_FG_Hello(base); + if (ENDAT3_FG_Bus_P2P_Hello(base, i) == kStatus_Success) { + address[index++] = i; + } + } + + for (int i = 0; i < index; i++) { + ENDAT3_FG_Bus_P2P_BUSINIT(base, address[i]); + } +} + char* ENDAT3_FID2str(const uint8_t fid) { switch (fid) { diff --git a/mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.h b/mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.h index 047b16c8f..30cbed23b 100644 --- a/mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.h +++ b/mcux/mcux-sdk-ng/drivers/endat3/fsl_endat3.h @@ -31,6 +31,7 @@ typedef struct _endat3_dev enum { kStatus_Endat3_FG_Hello_Failed = MAKE_STATUS(kStatusGroup_ENDAT3, 0), kStatus_Endat3_FG_ECHO_Failed = MAKE_STATUS(kStatusGroup_ENDAT3, 0), + kStatus_Endat3_FG_RATE_Failed = MAKE_STATUS(kStatusGroup_ENDAT3, 0), kStatus_Endat3_FG_Strobe_Error = MAKE_STATUS(kStatusGroup_ENDAT3, 1), kStatus_Endat3_FG_Watchdog_Error = MAKE_STATUS(kStatusGroup_ENDAT3, 2), kStatus_Endat3_FG_PHY_Error = MAKE_STATUS(kStatusGroup_ENDAT3, 3), @@ -85,8 +86,14 @@ enum { }; enum { - ENDAT3_RXTX_RATE_25MBPS = 0x0, - ENDAT3_RXTX_RATE_12_5MBPS, + ENDAT3_RXTX_RATE_12_5MBPS = 0x0, + ENDAT3_RXTX_RATE_25MBPS = 0x01 +}; + +enum op_mode { + Point2Point, + Peer2Peer, + Broadcast }; __PACKED_STRUCT HPF { @@ -202,6 +209,15 @@ typedef struct _Endat3_res struct LPF lpf[15]; } endat3_rsp_t; +typedef struct _Endat3_bg_req +{ + ENDAT3_Type *base; + uint8_t bus_addr; + uint8_t fg_strobes; + enum op_mode op; + uint32_t timeout_ms; +} endat3_bg_req_t; + #define MAX_MEMORY_AREA_SIZE 0x100 typedef struct { @@ -236,7 +252,7 @@ typedef struct { #define ENDAT3_FG_DATA_HELLO 0x2222 #define ENDAT3_FG_DATA_RESET 0xBBBB #define ENDAT3_FG_DATA_RATE_12_5MBPS 0x0001 -#define ENDAT3_FG_DATA_RATE_25MBPS 0x0000 +#define ENDAT3_FG_DATA_RATE_25_MBPS 0x0000 #define ENDAT3_FG_DATA_ClearF 0x0000 #define ENDAT3_FG_DATA_ClearW 0x0001 #define ENDAT3_FG_DATA_ClearREF 0x0002 @@ -272,7 +288,7 @@ typedef struct { #define ENDAT3_BG_OPCODE_AUTH 0x80 #define ENDAT3_BG_OPCODE_PROTECT 0x81 #define ENDAT3_BG_OPCODE_SETPASS 0x83 -#define ENDAT3_BG_OPCODE_LOCATE 0x83 +#define ENDAT3_BG_OPCODE_LOCATE 0x84 // EnDat 3 Background Request Data #define ENDAT3_BG_PROTECT_MODE_QUERY 0x01 @@ -284,42 +300,6 @@ typedef struct { #define ENDAT3_BG_ACCLEVEL_OEM1 2 #define ENDAT3_BG_ACCLEVEL_MANUFACTURER 3 -// Timing -#define ENDAT3_HELLO_TIMEOUT 302 - -///////////// -#define CYCLE_BASED_MEM_HPF_LPF 0x1000 -#define CYCLE_BASED_MEM_LPH 0x2000 -#define FID_BASED_MEM 0x8000 -#define SAFETY_COLLECTOR_MEM 0x3000 - -#define ENDAT3_GET_HPF_ADDR(base, bus_addr) (struct HPF *)(((uint8_t *) (base)) + CYCLE_BASED_MEM_HPF_LPF + ((bus_addr) << 7)) -#define ENDAT3_GET_LPF_ADDR(base, bus_addr, index) (struct LPF *)(((uint8_t *) (base)) + CYCLE_BASED_MEM_HPF_LPF + ((bus_addr) << 7) + (((index) + 1) << 3)) -#define ENDAT3_GET_LPH_ADDR(base, bus_addr) (struct LPH *)(((uint8_t *) (base)) + CYCLE_BASED_MEM_LPH + ((bus_addr) << 3)) -#define ENDAT3_GET_FID_ADDR(base, bus_addr, fid) (struct FID *)(((uint8_t *) (base)) + FID_BASED_MEM + ((bus_addr) << 10) + ((fid) << 3)) -#define ENDAT3_GET_SAFETY_FID_SD1_HPF(base, bus_addr, packet) (struct HPF *)(((uint8_t *) (base)) + SAFETY_COLLECTOR_MEM + ((bus_addr) << 6) + ((packet) << 5)) -#define ENDAT3_GET_SAFETY_FID_SD1_LPF(base, bus_addr, packet) (struct LPF *)(((uint8_t *) (base)) + SAFETY_COLLECTOR_MEM + ((bus_addr) << 6) + ((packet) << 5)) -#define ENDAT3_GET_SAFETY_FID_SD2_LPF(base, bus_addr, packet) (struct LPF *)(((uint8_t *) (base)) + SAFETY_COLLECTOR_MEM + ((bus_addr) << 6) + ((packet) << 5) + 0x8) -#define ENDAT3_GET_SAFETY_FID_SF_LPF(base, bus_addr, packet) (struct LPF *)(((uint8_t *) (base)) + SAFETY_COLLECTOR_MEM + ((bus_addr) << 6) + ((packet) << 5) + 0x10) - -#define ENDAT3_FG_Bus_P2P_Req_Rsp(base, bus_addr, code, data, rsp) ENDAT3_FG_Bus_Req_Rsp(base, bus_addr, code, data, ENDAT3_FG_REQ_BUSP2P, (uint16_t)bus_addr, rsp) -#define ENDAT3_FG_Bus_BC_with_individual_FG_Req(base, bus_addr, code, data) ENDAT3_FG_Bus_Req(base, code, data, ENDAT3_FG_REQ_BUSBC, (uint16_t)bus_addr) -#define ENDAT3_FG_Bus_BC_without_individual_FG_Req(base, code, data) ENDAT3_FG_Bus_Req(base, code, data, ENDAT3_FG_REQ_BUSBC, 0) -#define ENDAT3_FG_Bus_BC_without_individual_FG_Req_and_strobe(base, code, data) ENDAT3_FG_Bus_Req_without_strobe(base, code, data, ENDAT3_FG_REQ_BUSBC, 0) - -#define ENDAT3_FG_Reset(base) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_RESET, ENDAT3_FG_DATA_RESET, NULL) -#define ENDAT3_FG_Rate(base, rate) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_RATE, rate, NULL) -#define ENDAT3_FG_Clear(base, flag) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_RATE, flag, NULL) -#define ENDAT3_FG_Force(base) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_FORCE, 0x0, NULL) -#define ENDAT3_FG_BusInit(base) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_BUSINIT, ENDAT3_FG_DATA_BUSINIT, NULL) -#define ENDAT3_FG_Data(base, DATAx, rsp) ENDAT3_FG_Req_Rsp(base, DATAx, 0, rsp) - -#define ENDAT3_FG_Bus_P2P_Reset(base, addr) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_RESET, ENDAT3_FG_DATA_RESET, NULL) -#define ENDAT3_FG_Bus_P2P_Rate(base, addr, rate) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_RATE, rate, NULL) -#define ENDAT3_FG_Bus_P2P_Clear(base, addr, flag) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_RATE, flag, NULL) -#define ENDAT3_FG_Bus_P2P_Force(base, addr) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_FORCE, 0x0, NULL) -#define ENDAT3_FG_Bus_P2P_BUSINIT(base, addr) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_BUSINIT, ENDAT3_FG_DATA_BUSINIT, NULL) -#define ENDAT3_FG_Bus_P2P_Data(base, addr, DATAx, rsp) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, DATAx, 0, rsp) #define ENDAT3_LPF_HEAD_SIZE_WORDS 0x0E @@ -584,6 +564,93 @@ typedef struct { /******************************************************************************* * Definitions ******************************************************************************/ +// Timing +#define ENDAT3_HELLO_TIMEOUT 3020 +#define ENDAT3_RATE_TIMEOUT 2 +#define ENDAT3_BG_REQ_TIMEOUT 1000 //ms + +///////////// +#define CYCLE_BASED_MEM_HPF_LPF 0x1000 +#define CYCLE_BASED_MEM_LPH 0x2000 +#define FID_BASED_MEM 0x8000 +#define SAFETY_COLLECTOR_MEM 0x3000 + +#define ENDAT3_GET_HPF_ADDR(base, bus_addr) (struct HPF *)(((uint8_t *) (base)) + CYCLE_BASED_MEM_HPF_LPF + ((bus_addr) << 7)) +#define ENDAT3_GET_LPF_ADDR(base, bus_addr, index) (struct LPF *)(((uint8_t *) (base)) + CYCLE_BASED_MEM_HPF_LPF + ((bus_addr) << 7) + (((index) + 1) << 3)) +#define ENDAT3_GET_LPH_ADDR(base, bus_addr) (struct LPH *)(((uint8_t *) (base)) + CYCLE_BASED_MEM_LPH + ((bus_addr) << 2)) +#define ENDAT3_GET_FID_ADDR(base, bus_addr, fid) (struct FID *)(((uint8_t *) (base)) + FID_BASED_MEM + ((bus_addr) << 10) + ((fid) << 3)) +#define ENDAT3_GET_SAFETY_FID_SD1_HPF(base, bus_addr, packet) (struct HPF *)(((uint8_t *) (base)) + SAFETY_COLLECTOR_MEM + ((bus_addr) << 6) + ((packet) << 5)) +#define ENDAT3_GET_SAFETY_FID_SD1_LPF(base, bus_addr, packet) (struct LPF *)(((uint8_t *) (base)) + SAFETY_COLLECTOR_MEM + ((bus_addr) << 6) + ((packet) << 5)) +#define ENDAT3_GET_SAFETY_FID_SD2_LPF(base, bus_addr, packet) (struct LPF *)(((uint8_t *) (base)) + SAFETY_COLLECTOR_MEM + ((bus_addr) << 6) + ((packet) << 5) + 0x8) +#define ENDAT3_GET_SAFETY_FID_SF_LPF(base, bus_addr, packet) (struct LPF *)(((uint8_t *) (base)) + SAFETY_COLLECTOR_MEM + ((bus_addr) << 6) + ((packet) << 5) + 0x10) + +#define ENDAT3_FG_Bus_BC_Req(base) ENDAT3_FG_Bus_Req(base, 0, 0, ENDAT3_FG_REQ_BUSBC, 0) +#define ENDAT3_FG_Bus_BC_with_FG_Req(base, fg_addr, fg_code, fg_data) ENDAT3_FG_Bus_Req(base, fg_code, fg_data, ENDAT3_FG_REQ_BUSBC, (uint16_t)(fg_addr)) +#define ENDAT3_FG_Bus_BC_with_BG_Req(base, bg_addr) ENDAT3_FG_Bus_Req(base, 0, 0, ENDAT3_FG_REQ_BUSBC, (uint16_t)(bg_addr << 8)) +#define ENDAT3_FG_Bus_BC_with_FG_BG_Req(base, fg_addr, fg_code, fg_data, bg_addr) ENDAT3_FG_Bus_Req(base, fg_code, fg_data, ENDAT3_FG_REQ_BUSBC, (uint16_t)((bg_addr << 8) | fg_addr)) + +#define ENDAT3_FG_Bus_BC_Req_Rsp(base) ENDAT3_FG_Bus_Req_Rsp(base, 0, 0, 0, ENDAT3_FG_REQ_BUSBC, 0, NULL) +#define ENDAT3_FG_Bus_BC_with_FG_Req_Rsp(base, fg_addr, fg_code, fg_data) ENDAT3_FG_Bus_Req_Rsp(base, 0, fg_code, fg_data, ENDAT3_FG_REQ_BUSBC, (uint16_t)(fg_addr), NULL) +#define ENDAT3_FG_Bus_BC_with_BG_Req_Rsp(base, bg_addr) ENDAT3_FG_Bus_Req_Rsp(base, 0, 0, 0, ENDAT3_FG_REQ_BUSBC, (uint16_t)(bg_addr << 8), NULL) +#define ENDAT3_FG_Bus_BC_with_FG_BG_Req_Rsp(base, fg_addr, fg_code, fg_data, bg_addr) ENDAT3_FG_Bus_Req_Rsp(base, 0, fg_code, fg_data, ENDAT3_FG_REQ_BUSBC, (uint16_t)((bg_addr << 8) | fg_addr), NULL) + +#define ENDAT3_FG_Reset(base) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_RESET, ENDAT3_FG_DATA_RESET, NULL) +#define ENDAT3_FG_Rate(base, rate) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_RATE, rate, NULL) +#define ENDAT3_FG_Clear(base, flag) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_CLEAR, flag, NULL) +#define ENDAT3_FG_Force(base) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_FORCE, 0x0, NULL) +#define ENDAT3_FG_BusInit(base) ENDAT3_FG_Req_Rsp(base, ENDAT3_FG_REQ_BUSINIT, ENDAT3_FG_DATA_BUSINIT, NULL) +#define ENDAT3_FG_Data(base, DATAx, rsp) ENDAT3_FG_Req_Rsp(base, DATAx, 0, rsp) + +#define ENDAT3_FG_Bus_P2P_Req_Rsp(base, bus_addr, code, data, rsp) ENDAT3_FG_Bus_Req_Rsp(base, bus_addr, code, data, ENDAT3_FG_REQ_BUSP2P, (uint16_t)(bus_addr), rsp) +#define ENDAT3_FG_Bus_P2P_Reset(base, addr) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_RESET, ENDAT3_FG_DATA_RESET, NULL) +#define ENDAT3_FG_Bus_P2P_Rate(base, addr, rate) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_RATE, rate, NULL) +#define ENDAT3_FG_Bus_P2P_Clear(base, addr, flag) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_RATE, flag, NULL) +#define ENDAT3_FG_Bus_P2P_Force(base, addr) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_FORCE, 0x0, NULL) +#define ENDAT3_FG_Bus_P2P_BUSINIT(base, addr) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, ENDAT3_FG_REQ_BUSINIT, ENDAT3_FG_DATA_BUSINIT, NULL) +#define ENDAT3_FG_Bus_P2P_Data(base, addr, DATAx, rsp) ENDAT3_FG_Bus_P2P_Req_Rsp(base, addr, DATAx, 0, rsp) + +#define ENDAT3_BG_Nop(base, arbitrary, bg_rsp, fg_strobes) ENDAT3_BG_Nop_OP(base, 0, arbitrary, bg_rsp, fg_strobes, Point2Point) +#define ENDAT3_BG_Reconfigure(base, fg_strobes) ENDAT3_BG_Reconfigure_OP(base, 0, fg_strobes, Point2Point) +#define ENDAT3_BG_Read(base, addr, num_words, words, fg_strobes) ENDAT3_BG_Read_OP(base, 0, addr, num_words, words, fg_strobes, Point2Point) +#define ENDAT3_BG_Write(base, addr, word, fg_strobes) ENDAT3_BG_Write_OP(base, 0, addr, word, fg_strobes, Point2Point) +#define ENDAT3_BG_Auth(base, usrlevel, pass, fg_strobes) ENDAT3_BG_Auth_OP(base, 0, usrlevel, pass, fg_strobes, Point2Point) +#define ENDAT3_BG_Setpass(base, usrlevel, pass, fg_strobes) ENDAT3_BG_Setpass_OP(base, 0, usrlevel, pass, fg_strobes, Point2Point) +#define ENDAT3_BG_Protect(base, addr, mode, acclevel, al_write, al_read, fg_strobes) \ + ENDAT3_BG_Protect_OP(base, 0, addr, mode, acclevel, al_write, al_read, fg_strobes, Point2Point) +#define ENDAT3_BG_Locate(base, ctrl, fg_strobes) ENDAT3_BG_Locate_OP(base, 0, ctrl, fg_strobes, Point2Point) + +#define ENDAT3_BG_Bus_P2P_Nop(base, bus_addr, arbitrary, bg_rsp, fg_strobes) ENDAT3_BG_Nop_OP(base, bus_addr, arbitrary, bg_rsp, fg_strobes, Peer2Peer) +#define ENDAT3_BG_Bus_P2P_Reconfigure(base, bus_addr, fg_strobes) ENDAT3_BG_Reconfigure_OP(base, bus_addr, fg_strobes, Peer2Peer) +#define ENDAT3_BG_Bus_P2P_Read(base, bus_addr, addr, num_words, words, fg_strobes) ENDAT3_BG_Read_OP(base, bus_addr, addr, num_words, words, fg_strobes, Peer2Peer) +#define ENDAT3_BG_Bus_P2P_Write(base, bus_addr, addr, word, fg_strobes) ENDAT3_BG_Write_OP(base, bus_addr, addr, word, fg_strobes, Peer2Peer) +#define ENDAT3_BG_Bus_P2P_Auth(base, bus_addr, usrlevel, pass, fg_strobes) ENDAT3_BG_Auth_OP(base, bus_addr, usrlevel, pass, fg_strobes, Peer2Peer) +#define ENDAT3_BG_Bus_P2P_Setpass(base, bus_addr, usrlevel, pass, fg_strobes) ENDAT3_BG_Setpass_OP(base, bus_addr, usrlevel, pass, fg_strobes, Peer2Peer) +#define ENDAT3_BG_Bus_P2P_Protect(base, bus_addr, addr, mode, acclevel, al_write, al_read, fg_strobes) \ + ENDAT3_BG_Protect_OP(base, bus_addr, addr, mode, acclevel, al_write, al_read, fg_strobes, Peer2Peer) +#define ENDAT3_BG_Bus_P2P_Locate(base, bus_addr, ctrl, fg_strobes) ENDAT3_BG_Locate_OP(base, bus_addr, ctrl, fg_strobes, Peer2Peer) + +#define ENDAT3_memCacheInit(base, mem_base, cache, pbuf, pbufSize, fg_strobes) ENDAT3_memCacheInit_OP(base, 0, mem_base, cache, pbuf, pbufSize, fg_strobes, Point2Point) +#define ENDAT3_memRead(base, addr, n_words, pbuf, fg_strobes) ENDAT3_memRead_OP(base, 0, addr, n_words, pbuf, fg_strobes, Point2Point) +#define ENDAT3_memWrite(base, addr, n_words, pbuf, fg_strobes) ENDAT3_memWrite_OP(base, 0, addr, n_words, pbuf, fg_strobes, Point2Point) +#define ENDAT3_memCacheFlush(base, cache, fg_strobes) ENDAT3_memCacheFlush_OP(base, 0, cache, fg_strobes, Point2Point) +#define ENDAT3_memCacheFetch(base, cache, fg_strobes) ENDAT3_memCacheFetch_OP(base, 0, cache, fg_strobes, Point2Point) +#define ENDAT3_memGetRangeSize(base, mem_base, fg_strobes) ENDAT3_memGetRangeSize_OP(base, 0, mem_base, fg_strobes, Point2Point) + +#define ENDAT3_Bus_P2P_memCacheInit(base, bus_addr, mem_base, cache, pbuf, pbufSize, fg_strobes) ENDAT3_memCacheInit_OP(base, bus_addr, mem_base, cache, pbuf, pbufSize, fg_strobes, Peer2Peer) +#define ENDAT3_Bus_P2P_memRead(base, bus_addr, addr, n_words, pbuf, fg_strobes) ENDAT3_memRead_OP(base, bus_addr, addr, n_words, pbuf, fg_strobes, Peer2Peer) +#define ENDAT3_Bus_P2P_memWrite(base, bus_addr, addr, n_words, pbuf, fg_strobes) ENDAT3_memWrite_OP(base, bus_addr, addr, n_words, pbuf, fg_strobes, Peer2Peer) +#define ENDAT3_Bus_P2P_memCacheFlush(base, bus_addr, cache, fg_strobes) ENDAT3_memCacheFlush_OP(base, bus_addr, cache, fg_strobes, Peer2Peer) +#define ENDAT3_Bus_P2P_memCacheFetch(base, bus_addr, cache, fg_strobes) ENDAT3_memCacheFetch_OP(base, bus_addr, cache, fg_strobes, Peer2Peer) +#define ENDAT3_Bus_P2P_memGetRangeSize(base, bus_addr, mem_base, fg_strobes) ENDAT3_memGetRangeSize_OP(base, bus_addr, mem_base, fg_strobes, Peer2Peer) + + +#define ENDAT3_lpfCacheUpdateFromEnconder(base, lpf_cache, pdat, pdat_size, from_set, fg_strobes) \ + ENDAT3_lpfCacheUpdateFromEnconder_OP(base, 0, lpf_cache, pdat, pdat_size, from_set, fg_strobes, Point2Point) +#define ENDAT3_lpfCacheFlushToEncoder(base, lpf_cache, fg_strobes) ENDAT3_lpfCacheFlushToEncoder_OP(base, 0, lpf_cache, fg_strobes, Point2Point) + +#define ENDAT3_Bus_P2P_lpfCacheUpdateFromEnconder(base, bus_addr, lpf_cache, pdat, pdat_size, from_set, fg_strobes) \ + ENDAT3_lpfCacheUpdateFromEnconder_OP(base, bus_addr, lpf_cache, pdat, pdat_size, from_set, fg_strobes, Peer2Peer) +#define ENDAT3_Bus_P2P_lpfCacheFlushToEncoder(base, bus_addr, lpf_cache, fg_strobes) ENDAT3_lpfCacheFlushToEncoder_OP(base, bus_addr, lpf_cache, fg_strobes, Peer2Peer) /******************************************************************************* @@ -625,7 +692,6 @@ static inline void ENDAT3_Set_Bus_Participants_Num(ENDAT3_Type *base, uint8_t nu } /* API interface for FG commnunication*/ - static inline void ENDAT3_FG_IRQ_Enable_With_FIxM_Frame_Count(ENDAT3_Type *base, uint32_t irq_index, uint8_t counter) { base->FG_IRQ_MASK[irq_index] &= ~ENDAT3_FG_IRQ_MASK_FIxM_FRAME_CNT_MASK; @@ -711,6 +777,7 @@ static inline uint32_t ENDAT3_Safety_Packet_status(ENDAT3_Type *base, uint8_t pa static inline void ENDAT3_FG_Req(ENDAT3_Type *base, uint8_t code, uint16_t dat) { + base->FG_REQ_0 = 0; base->FG_REQ_1 = ENDAT3_FG_REQ_1_REQ_CODE(code) | ENDAT3_FG_REQ_1_REQ_DATA(dat) | ENDAT3_FG_REQ_1_FG_STROBE(1); } @@ -743,30 +810,30 @@ status_t ENDAT3_FG_Echo(ENDAT3_Type *base, uint16_t arbitrary_data); status_t ENDAT3_FG_Bus_Req_Rsp(ENDAT3_Type *base, uint8_t bus_addr, uint8_t req, uint16_t data, uint8_t busCode, uint16_t busData, endat3_rsp_t *rsp); status_t ENDAT3_FG_Bus_P2P_Hello(ENDAT3_Type *base, uint8_t addr); status_t ENDAT3_FG_Bus_P2P_Echo(ENDAT3_Type *base, uint8_t addr, uint16_t arbitrary_data); - +status_t ENDAT3_FG_Bus_Rate_Switch(ENDAT3_Type *base, uint8_t nodes_num, uint8_t rate); /* API interface for BG commnunication*/ void ENDAT3_BG_Req(ENDAT3_Type *base, uint8_t bus_addr, struct BGREQ *req, uint8_t wait_rsp); -void ENDAT3_BG_WaitReqEmpty(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes); -status_t ENDAT3_BG_WaitReqFinished(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes, uint32_t timeout_ms); -uint64_t ENDAT3_BG_GetRsp(ENDAT3_Type *base); -status_t ENDAT3_BG_Req_Rsp(ENDAT3_Type *base, uint8_t bus_addr, struct BGREQ *req, uint64_t *rsp, uint8_t fg_strobes, uint32_t timeout_ms); -status_t ENDAT3_BG_Nop(ENDAT3_Type *base, uint8_t bus_addr, uint64_t arbitrary, uint64_t *bg_rsp, uint8_t fg_strobes); -status_t ENDAT3_BG_Reconfigure(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes); -status_t ENDAT3_BG_Read(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint8_t num_words, uint16_t *words, uint8_t fg_strobes); -status_t ENDAT3_BG_Write(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, const uint16_t word, uint8_t fg_strobes); -status_t ENDAT3_BG_Auth(ENDAT3_Type *base, uint8_t bus_addr, uint8_t usrlevel, uint32_t pass, uint8_t fg_strobes); -status_t ENDAT3_BG_Setpass(ENDAT3_Type *base, uint8_t bus_addr, uint8_t usrlevel, uint32_t pass, uint8_t fg_strobes); -status_t ENDAT3_BG_Protect(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint8_t mode, const uint8_t acclevel, uint8_t *al_write, uint8_t *al_read, uint8_t fg_strobes); -status_t ENDAT3_BG_Locate(ENDAT3_Type *base, uint8_t bus_addr, uint8_t ctrl, uint8_t fg_strobes); +status_t ENDAT3_BG_WaitReqFinished_OP(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes, uint32_t timeout_ms, enum op_mode op); +status_t ENDAT3_BG_GetRsp(ENDAT3_Type *base, uint64_t *rsp, uint32_t timeout_ms); +status_t ENDAT3_BG_Req_Rsp_OP(ENDAT3_Type *base, uint8_t bus_addr, struct BGREQ *req, uint64_t *rsp, uint8_t fg_strobes, uint32_t timeout_ms, enum op_mode op); +status_t ENDAT3_BG_Nop_OP(ENDAT3_Type *base, uint8_t bus_addr, uint64_t arbitrary, uint64_t *bg_rsp, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_BG_Reconfigure_OP(ENDAT3_Type *base, uint8_t bus_addr, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_BG_Read_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint8_t num_words, uint16_t *words, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_BG_Write_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, const uint16_t word, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_BG_Auth_OP(ENDAT3_Type *base, uint8_t bus_addr, uint8_t usrlevel, uint32_t pass, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_BG_Setpass_OP(ENDAT3_Type *base, uint8_t bus_addr, uint8_t usrlevel, uint32_t pass, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_BG_Protect_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint8_t mode, const uint8_t acclevel, uint8_t *al_write, uint8_t *al_read, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_BG_Locate_OP(ENDAT3_Type *base, uint8_t bus_addr, uint8_t ctrl, uint8_t fg_strobes, enum op_mode op); status_t ENDAT3_RxTxClkConfig(ENDAT3_Type *base, uint32_t clk_sys, uint8_t rate, uint16_t watchdag_us); -status_t ENDAT3_memRead(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint16_t n_words, uint16_t *pbuf, uint8_t fg_strobes); -status_t ENDAT3_memWrite(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint16_t n_words, uint16_t *pbuf, uint8_t fg_strobes); -status_t ENDAT3_memCacheInit(ENDAT3_Type *base, uint8_t bus_addr, uint32_t mem_base, endat3_mem_cache_t *cache, uint16_t *pbuf, uint32_t pbufSize, uint8_t fg_strobes); -status_t ENDAT3_memCacheFlush(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes); -status_t ENDAT3_memCacheFetch(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes); -uint16_t ENDAT3_memGetRangeSize(ENDAT3_Type *base, uint8_t bus_addr, uint32_t mem_base, uint8_t fg_strobes); +status_t ENDAT3_memRead_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint16_t n_words, uint16_t *pbuf, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_memWrite_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t addr, uint16_t n_words, uint16_t *pbuf, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_memCacheInit_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t mem_base, endat3_mem_cache_t *cache, uint16_t *pbuf, uint32_t pbufSize, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_memCacheFlush_OP(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_memCacheFetch_OP(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes, enum op_mode op); +uint16_t ENDAT3_memGetRangeSize_OP(ENDAT3_Type *base, uint8_t bus_addr, uint32_t mem_base, uint8_t fg_strobes, enum op_mode op); status_t ENDAT3_memCacheCheckCS(endat3_mem_cache_t *cache); status_t ENDAT3_memCacheUpdataCS(endat3_mem_cache_t *cache); +void ENDAT3_memCacheSetDirty(endat3_mem_cache_t *cache, int word_index, int isDirty); uint16_t ENDAT3_lpfCacheGetPointer(uint8_t z, endat3_mem_cache_t *lpf_cache); void ENDAT3_lpfCacheGetXdimYdim(uint8_t z, endat3_mem_cache_t *lpf_cache, uint8_t *xdim, uint8_t *y_dim); void ENDAT3_lpfCacheSetXdimYdim(uint8_t z, endat3_mem_cache_t *lpf_cache, uint8_t xdim, uint8_t y_dim); @@ -774,11 +841,14 @@ void ENDAT3_lpfCacheSetPointer(uint8_t z, endat3_mem_cache_t *lpf_cache, uint16_ void ENDAT3_lpfCacheListSetFid(endat3_mem_cache_t *cache, uint8_t xdim, uint8_t x, uint8_t y, uint16_t pointer, uint8_t fid); void ENDAT3_lpfCacheListSetSendlist(endat3_mem_cache_t *cache, uint8_t z, uint8_t xdim, uint8_t ydim, uint16_t pointer, uint8_t *fids); uint8_t ENDAT3_lpfCacheListGetFid(endat3_mem_cache_t *cache, uint8_t xdim, uint8_t x, uint8_t y, uint16_t pointer); -status_t ENDAT3_lpfCacheUpdateFromEnconder(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint16_t *pdat, uint32_t pdat_size, uint8_t from_set, uint8_t fg_strobes); -status_t ENDAT3_lpfCacheFlushToEncoder(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes); +status_t ENDAT3_lpfCacheUpdateFromEnconder_OP(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint16_t *pdat, uint32_t pdat_size, uint8_t from_set, uint8_t fg_strobes, enum op_mode op); +status_t ENDAT3_lpfCacheFlushToEncoder_OP(ENDAT3_Type *base, uint8_t bus_addr, endat3_mem_cache_t *cache, uint8_t fg_strobes, enum op_mode op); void ENDAT3_lpfCacheListUpdate(endat3_mem_cache_t *global_cache, endat3_mem_cache_t *cache, uint8_t z, uint8_t xdim, uint8_t ydim, uint16_t pointer, uint8_t *fid); -status_t ENDAT3_Bus_Assign_Address(ENDAT3_Type *base, uint8_t encoderNum); +status_t ENDAT3_Bus_Assign_Address(ENDAT3_Type *base, uint8_t encoderNum); +void ENDAT3_Bus_Init_ForAllParticipants(ENDAT3_Type *base, int nodes_num); +status_t ENDAT3_Bus_Hello_ForAllParticipants(ENDAT3_Type *base, int nodes_num); +status_t ENDAT3_FG_Bus_BC_Rate_Switch(ENDAT3_Type *base, uint8_t nodes_num, uint8_t rate); char* ENDAT3_FID2str(const uint8_t fid); char *ENDAT3_Err2str(uint16_t errCode); diff --git a/mcux/mcux-sdk-ng/drivers/enet/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/enet/CMakeLists.txt index 74035c1fb..09c3c42e3 100644 --- a/mcux/mcux-sdk-ng/drivers/enet/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/enet/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.enet) - mcux_component_version(2.9.2) + mcux_component_version(2.9.3) mcux_add_source(SOURCES fsl_enet.h fsl_enet.c) diff --git a/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.c b/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.c index 1ae45d4df..57cc37e4d 100644 --- a/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.c +++ b/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -2995,7 +2995,7 @@ void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_ ENET_Ptp1588GetTimerNoIrqDisable(base, handle, ptpTime); /* Get PTP timer wrap event. */ - if (0U != (base->EIR & (uint32_t)kENET_TsTimerInterrupt)) + if ((0U != (base->EIR & (uint32_t)kENET_TsTimerInterrupt)) && (ptpTime->nanosecond < (ENET_NANOSECOND_ONE_SECOND / 2))) { ptpTime->second++; } diff --git a/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h b/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h index 2bec20097..fc3506d64 100644 --- a/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h +++ b/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,7 +23,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief Defines the driver version. */ -#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 9, 2)) +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 9, 3)) /*! @} */ /*! @name ENET DESCRIPTOR QUEUE */ @@ -1953,17 +1953,6 @@ void ENET_Ptp1588GetTimerNoIrqDisable(ENET_Type *base, enet_handle_t *handle, en */ void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); -/*! - * @brief Gets the last captured ENET time from the PTP 1588 timer. - * - * @param base ENET peripheral base address. - * @param channel The ENET PTP timer channel number. - */ -static inline uint32_t ENET_Ptp1588GetChannelCaptureValue(ENET_Type *base, enet_ptp_timer_channel_t channel) -{ - return base->CHANNEL[channel].TCCR; -} - /*! * @brief Sets the ENET PTP 1588 timer to the assigned time. * diff --git a/mcux/mcux-sdk-ng/drivers/enet_qos/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/enet_qos/CMakeLists.txt index 9770d4535..77a8049c6 100644 --- a/mcux/mcux-sdk-ng/drivers/enet_qos/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/enet_qos/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.enet_qos) - mcux_component_version(2.6.5) + mcux_component_version(2.7.0) mcux_add_source(SOURCES fsl_enet_qos.h fsl_enet_qos.c) diff --git a/mcux/mcux-sdk-ng/drivers/enet_qos/fsl_enet_qos.c b/mcux/mcux-sdk-ng/drivers/enet_qos/fsl_enet_qos.c index 1aff7daa7..cf9beae8e 100644 --- a/mcux/mcux-sdk-ng/drivers/enet_qos/fsl_enet_qos.c +++ b/mcux/mcux-sdk-ng/drivers/enet_qos/fsl_enet_qos.c @@ -19,8 +19,10 @@ /*! @brief Defines 10^6 microsecond.*/ #define ENET_QOS_MICRSECS_ONESECOND (1000000U) +#ifndef ENET_QOS_RXBUFF_IGNORELSB_BITS /*! @brief Rx buffer LSB ignore bits. */ #define ENET_QOS_RXBUFF_IGNORELSB_BITS (3U) +#endif /* ENET_QOS_RXBUFF_IGNORELSB_BITS */ /*! @brief ENET FIFO size unit. */ #define ENET_QOS_FIFOSIZE_UNIT (256U) /*! @brief ENET half-dulpex default IPG. */ @@ -284,6 +286,7 @@ static status_t ENET_QOS_SetDMAControl(ENET_QOS_Type *base, const enet_qos_confi return kStatus_InvalidArgument; } +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS if (kENET_QOS_RmiiMode == config->miiMode) { /* Disable enet qos clock first. */ @@ -294,6 +297,10 @@ static status_t ENET_QOS_SetDMAControl(ENET_QOS_Type *base, const enet_qos_confi /* Enable enet qos clock. */ ENET_QOS_EnableClock(true); } +#else + /* Enable enet qos clock. */ + ENET_QOS_EnableClock(true); +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ /* Set MII mode*/ ENET_QOS_SetSYSControl(config->miiMode); @@ -316,8 +323,10 @@ static status_t ENET_QOS_SetDMAControl(ENET_QOS_Type *base, const enet_qos_confi reg |= ENET_QOS_MAC_CONFIGURATION_IPG(ENET_QOS_HALFDUPLEX_DEFAULTIPG); } base->MAC_CONFIGURATION = reg; +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS /* Enable enet qos clock. */ ENET_QOS_EnableClock(true); +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ for (uint32_t i = 0U; i < 100UL; i++) { __NOP(); @@ -407,7 +416,11 @@ static void ENET_QOS_SetMTL(ENET_QOS_Type *base, const enet_qos_config_t *config rxqOpReg |= ENET_QOS_MTL_RXQX_OP_MODE_RQS( ((uint32_t)ENET_QOS_MTL_RXFIFOSIZE / ((uint32_t)multiqCfg->rxQueueUse * ENET_QOS_FIFOSIZE_UNIT)) - 1U); base->MTL_QUEUE[index].MTL_RXQX_OP_MODE = rxqOpReg; +#if ENET_QOS_MAC_RXQ_CTRL_COUNT > 3 mtlrxQuemapReg = (index < 4U) ? &base->MTL_RXQ_DMA_MAP0 : &base->MTL_RXQ_DMA_MAP1; +#else + mtlrxQuemapReg = &base->MTL_RXQ_DMA_MAP0; +#endif /* ENET_QOS_MAC_RXQ_CTRL_COUNT > 3 */ configIndex = (index & 0x3U); *mtlrxQuemapReg &= ~((uint32_t)ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK << (8U * configIndex)); *mtlrxQuemapReg |= (uint32_t)ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(multiqCfg->rxQueueConfig[index].mapChannel) @@ -459,9 +472,11 @@ static status_t ENET_QOS_SetMacControl(ENET_QOS_Type *base, base->MAC_TX_FLOW_CTRL_Q[0] = ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration); } +#ifdef ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR /* Set the 1us ticket. */ reg = config->csrClock_Hz / ENET_QOS_MICRSECS_ONESECOND - 1U; base->MAC_ONEUS_TIC_COUNTER = ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(reg); +#endif /* ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR */ /* Set the speed and duplex. */ reg = ENET_QOS_MAC_CONFIGURATION_DM(config->miiDuplex) | (uint32_t)config->miiSpeed | @@ -480,12 +495,17 @@ static status_t ENET_QOS_SetMacControl(ENET_QOS_Type *base, reg = 0U; uint8_t configIndex; enet_qos_multiqueue_config_t *multiqCfg = config->multiqueueCfg; +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS uint32_t txQueuePrioMap0 = base->MAC_TXQ_PRTY_MAP0; uint32_t txQueuePrioMap1 = base->MAC_TXQ_PRTY_MAP1; +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ uint32_t rxQueuePrioMap0 = base->MAC_RXQ_CTRL[2]; +#if ENET_QOS_MAC_RXQ_CTRL_COUNT > 3 uint32_t rxQueuePrioMap1 = base->MAC_RXQ_CTRL[3]; +#endif /* ENET_QOS_MAC_RXQ_CTRL_COUNT > 3 */ uint32_t rxCtrlReg1 = base->MAC_RXQ_CTRL[1]; +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS for (uint8_t index = 0U; index < multiqCfg->txQueueUse; index++) { configIndex = index & 0x3U; @@ -504,6 +524,7 @@ static status_t ENET_QOS_SetMacControl(ENET_QOS_Type *base, << (8U * configIndex); } } +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ for (uint8_t index = 0U; index < multiqCfg->rxQueueUse; index++) { @@ -516,12 +537,14 @@ static status_t ENET_QOS_SetMacControl(ENET_QOS_Type *base, rxQueuePrioMap0 |= (uint32_t)ENET_QOS_MAC_RXQ_CTRL_PSRQ0(multiqCfg->rxQueueConfig[index].priority) << (8U * configIndex); } +#if ENET_QOS_MAC_RXQ_CTRL_COUNT > 3 else - { + { rxQueuePrioMap1 &= ~((uint32_t)ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK << (8U * configIndex)); rxQueuePrioMap1 |= (uint32_t)ENET_QOS_MAC_RXQ_CTRL_PSRQ0(multiqCfg->rxQueueConfig[index].priority) << (8U * configIndex); } +#endif /* ENET_QOS_MAC_RXQ_CTRL_COUNT > 3 */ /* Configure queue enable mode. */ reg |= ENET_QOS_MAC_RXQ_CTRL_RXQ0EN((uint32_t)multiqCfg->rxQueueConfig[index].mode) << (2U * index); @@ -539,11 +562,13 @@ static status_t ENET_QOS_SetMacControl(ENET_QOS_Type *base, rxCtrlReg1 |= ENET_QOS_MAC_RXQ_CTRL_PTPQ(index); } +#if defined(ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK) && defined(ENET_QOS_MAC_RXQ_CTRL_DCBCPQ) if (((uint8_t)multiqCfg->rxQueueConfig[index].packetRoute & (uint8_t)kENET_QOS_PacketDCBCPQ) != 0U) { rxCtrlReg1 &= ~ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK; rxCtrlReg1 |= ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(index); } +#endif /* ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK && ENET_QOS_MAC_RXQ_CTRL_DCBCPQ */ if (((uint8_t)multiqCfg->rxQueueConfig[index].packetRoute & (uint8_t)kENET_QOS_PacketUPQ) != 0U) { @@ -558,10 +583,14 @@ static status_t ENET_QOS_SetMacControl(ENET_QOS_Type *base, } } +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS base->MAC_TXQ_PRTY_MAP0 = txQueuePrioMap0; base->MAC_TXQ_PRTY_MAP1 = txQueuePrioMap1; +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ base->MAC_RXQ_CTRL[2] = rxQueuePrioMap0; +#if ENET_QOS_MAC_RXQ_CTRL_COUNT > 3 base->MAC_RXQ_CTRL[3] = rxQueuePrioMap1; +#endif /* ENET_QOS_MAC_RXQ_CTRL_COUNT > 3 */ base->MAC_RXQ_CTRL[1] = rxCtrlReg1; } else @@ -578,7 +607,9 @@ static status_t ENET_QOS_SetMacControl(ENET_QOS_Type *base, */ base->MAC_MMC_RX_INTERRUPT_MASK = 0xFFFFFFFFU; base->MAC_MMC_TX_INTERRUPT_MASK = 0xFFFFFFFFU; +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS base->MAC_MMC_IPC_RX_INTERRUPT_MASK = 0xFFFFFFFFU; +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ base->MAC_MMC_FPE_RX_INTERRUPT_MASK = 0xFFFFFFFFU; base->MAC_MMC_FPE_TX_INTERRUPT_MASK = 0xFFFFFFFFU; @@ -1418,10 +1449,12 @@ void ENET_QOS_ClearMacInterruptStatus(ENET_QOS_Type *base, uint32_t mask) { dummy = base->MAC_TIMESTAMP_STATUS; } +#ifdef ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK else if ((mask & (uint32_t)kENET_QOS_MacPmt) != 0U) { dummy = base->MAC_PMT_CONTROL_STATUS; } +#endif /* ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK */ else { /* Add for avoid the misra 2004 rule 14.10 */ @@ -2021,6 +2054,7 @@ status_t ENET_QOS_MDIOC45Read(ENET_QOS_Type *base, uint8_t portAddr, uint8_t dev return result; } +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS /*! * brief Set the MAC to enter into power down mode. * the remote power wake up frame and magic frame can wake up @@ -2059,6 +2093,7 @@ void ENET_QOS_EnterPowerDown(ENET_QOS_Type *base, uint32_t *wakeFilter) /* Enable the MAC rx. */ base->MAC_CONFIGURATION |= ENET_QOS_MAC_CONFIGURATION_RE_MASK; } +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ /*! * brief Enable/Disable Rx parser, please notice that for enable/disable Rx Parser, @@ -3792,6 +3827,7 @@ status_t ENET_QOS_ReadRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpCo return result; } +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS /*! * brief Configure flexible rx parser. * @@ -3895,6 +3931,7 @@ status_t ENET_QOS_ConfigureRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t * return result; } +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ /*! * brief Gets statistical data in transfer. @@ -3925,6 +3962,8 @@ void ENET_QOS_GetStatistics(ENET_QOS_Type *base, enet_qos_transfer_stats_t *stat void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle) { /* Check for the interrupt source type. */ + +#ifdef ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK /* DMA CHANNEL 0. */ if ((base->DMA_INTERRUPT_STATUS & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK) != 0U) { @@ -3943,7 +3982,9 @@ void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle) ENET_QOS_ReclaimTxDescriptor(base, handle, 0); } } +#endif /* ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK */ +#ifdef ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK /* DMA CHANNEL 1. */ if ((base->DMA_INTERRUPT_STATUS & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK) != 0U) { @@ -3962,7 +4003,9 @@ void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle) ENET_QOS_ReclaimTxDescriptor(base, handle, 1); } } +#endif /* ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK */ +#ifdef ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK /* DMA CHANNEL 2. */ if ((base->DMA_INTERRUPT_STATUS & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK) != 0U) { @@ -3981,7 +4024,9 @@ void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle) ENET_QOS_ReclaimTxDescriptor(base, handle, 2); } } +#endif /* ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK */ +#ifdef ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK /* DMA CHANNEL 3. */ if ((base->DMA_INTERRUPT_STATUS & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK) != 0U) { @@ -4000,6 +4045,7 @@ void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle) ENET_QOS_ReclaimTxDescriptor(base, handle, 3); } } +#endif /* ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK */ /* MAC TIMESTAMP. */ if ((base->DMA_INTERRUPT_STATUS & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK) != 0U) @@ -4030,3 +4076,11 @@ void CONNECTIVITY_EQOS_INT_DriverIRQHandler(void) s_enetqosIsr(CONNECTIVITY__ENET_QOS, s_ENETHandle[0]); } #endif + +#if defined(ENET_QOS_EMAC_USED_AS_ENET_QOS) +void EMAC_0_DriverIRQHandler(void); +void EMAC_0_DriverIRQHandler(void) +{ + s_enetqosIsr(EMAC, s_ENETHandle[0]); +} +#endif diff --git a/mcux/mcux-sdk-ng/drivers/enet_qos/fsl_enet_qos.h b/mcux/mcux-sdk-ng/drivers/enet_qos/fsl_enet_qos.h index 7dc4aaca8..e8de02992 100644 --- a/mcux/mcux-sdk-ng/drivers/enet_qos/fsl_enet_qos.h +++ b/mcux/mcux-sdk-ng/drivers/enet_qos/fsl_enet_qos.h @@ -15,9 +15,193 @@ #endif #if !defined(ENET_QOS) -/* Keep reusing ENET_QOS for platforms which renames it to Ethernet Controller with TSN (EQoS-TSN) */ #if defined(ENET_QOS_TSN) + +/* Keep reusing ENET_QOS for platforms which renames it to Ethernet Controller with TSN (EQoS-TSN) */ #define ENET_QOS ENET_QOS_TSN + +#elif defined(EMAC) + +/* Reuse ENET_QOS driver for EMAC, which is similar */ +#define ENET_QOS EMAC + +#define ENET_QOS_EMAC_USED_AS_ENET_QOS + +#define ENET_QOS_Type EMAC_Type +#define ENET_QOS_BASE_PTRS EMAC_BASE_PTRS +#define ENET_QOS_IRQS EMAC_IRQS +#define ENETQOS_CLOCKS EMAC_CLOCKS + +#ifdef FSL_FEATURE_EMAC_TX_OFFLOAD_QUEUE_SUPPORT_BITMAP +#define FSL_FEATURE_ENET_QOS_TX_OFFLOAD_QUEUE_SUPPORT_BITMAP FSL_FEATURE_EMAC_TX_OFFLOAD_QUEUE_SUPPORT_BITMAP +#else +#define FSL_FEATURE_ENET_QOS_TX_OFFLOAD_QUEUE_SUPPORT_BITMAP 0xFFFFFFFF +#endif /* FSL_FEATURE_EMAC_TX_OFFLOAD_QUEUE_SUPPORT_BITMAP */ + +#ifndef ENET_QOS_RXBUFF_IGNORELSB_BITS +#define ENET_QOS_RXBUFF_IGNORELSB_BITS (2U) +#endif /* ENET_QOS_RXBUFF_IGNORELSB_BITS */ + +#define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK EMAC_DMA_CHX_INT_EN_TXSE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK EMAC_DMA_CHX_INT_EN_RBUE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK EMAC_DMA_CHX_INT_EN_RSE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK EMAC_DMA_CHX_INT_EN_RWTE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK EMAC_DMA_CHX_INT_EN_FBEE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK EMAC_DMA_CHX_INT_EN_ETIE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK EMAC_DMA_CHX_INT_EN_TIE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK EMAC_DMA_CHX_INT_EN_TBUE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK EMAC_DMA_CHX_INT_EN_RIE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK EMAC_DMA_CHX_INT_EN_ERIE_MASK +#define ENET_QOS_MAC_CONFIGURATION_PS EMAC_MAC_CONFIGURATION_PS +#define ENET_QOS_MAC_CONFIGURATION_FES EMAC_MAC_CONFIGURATION_FES +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1 EMAC_MAC_MDIO_ADDRESS_GOC_1 +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0 EMAC_MAC_MDIO_ADDRESS_GOC_0 +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK EMAC_MAC_INTERRUPT_ENABLE_TSIE_MASK +#define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK EMAC_MAC_MDIO_ADDRESS_GB_MASK +#define ENET_QOS_MAC_MDIO_DATA_GD_MASK EMAC_MAC_MDIO_DATA_GD_MASK +#define ENET_QOS_HIGH_AE_MASK EMAC_HIGH_AE_MASK +#define ENET_QOS_MAC_PACKET_FILTER_PM_MASK EMAC_MAC_PACKET_FILTER_PM_MASK +#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK EMAC_MAC_FPE_CTRL_STS_EFPE_MASK +#define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK EMAC_MTL_FPE_CTRL_STS_PEC_MASK +#define ENET_QOS_MTL_FPE_CTRL_STS_PEC EMAC_MTL_FPE_CTRL_STS_PEC +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0 EMAC_MAC_PPS_CONTROL_TRGTMODSEL0 +#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD +#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0 EMAC_MAC_PPS_CONTROL_PPSEN0 +#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0 EMAC_MAC_PPS0_WIDTH_PPSWIDTH0 +#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0 EMAC_MAC_PPS0_INTERVAL_PPSINT0 +#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK EMAC_MTL_TXQX_ETS_CTRL_AVALG_MASK +#define ENET_QOS_DMA_MODE_SWR_MASK EMAC_DMA_MODE_SWR_MASK +#define ENET_QOS_MAC_CONFIGURATION_DM EMAC_MAC_CONFIGURATION_DM +#define ENET_QOS_MAC_CONFIGURATION_S2KP EMAC_MAC_CONFIGURATION_S2KP +#define ENET_QOS_MAC_CONFIGURATION_IPG EMAC_MAC_CONFIGURATION_IPG +#define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK EMAC_DMA_CHX_CTRL_PBLx8_MASK +#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK EMAC_DMA_CHX_TX_CTRL_TxPBL_MASK +#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL EMAC_DMA_CHX_TX_CTRL_TxPBL +#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK EMAC_DMA_CHX_RX_CTRL_RxPBL_MASK +#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL EMAC_DMA_CHX_RX_CTRL_RxPBL +#define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK EMAC_MTL_TXQX_OP_MODE_TSF_MASK +#define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK EMAC_MTL_RXQX_OP_MODE_RSF_MASK +#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK EMAC_MTL_TXQX_OP_MODE_FTQ_MASK +#define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK EMAC_MTL_RXQX_OP_MODE_FUP_MASK +#define ENET_QOS_MTL_RXQX_OP_MODE_RFD EMAC_MTL_RXQX_OP_MODE_RFD +#define ENET_QOS_MTL_RXQX_OP_MODE_RFA EMAC_MTL_RXQX_OP_MODE_RFA +#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK EMAC_MTL_RXQX_OP_MODE_EHFC_MASK +#define ENET_QOS_MTL_TXQX_OP_MODE_TQS EMAC_MTL_TXQX_OP_MODE_TQS +#define ENET_QOS_MTL_RXQX_OP_MODE_RQS EMAC_MTL_RXQX_OP_MODE_RQS +#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN EMAC_MTL_TXQX_OP_MODE_TXQEN +#define ENET_QOS_MTL_OPERATION_MODE_SCHALG EMAC_MTL_OPERATION_MODE_SCHALG +#define ENET_QOS_MTL_OPERATION_MODE_RAA EMAC_MTL_OPERATION_MODE_RAA +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH +#define ENET_QOS_MAC_PACKET_FILTER_PR EMAC_MAC_PACKET_FILTER_PR +#define ENET_QOS_MAC_PACKET_FILTER_DBF EMAC_MAC_PACKET_FILTER_DBF +#define ENET_QOS_MAC_PACKET_FILTER_PM EMAC_MAC_PACKET_FILTER_PM +#define ENET_QOS_MAC_PACKET_FILTER_HMC EMAC_MAC_PACKET_FILTER_HMC +#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK EMAC_MAC_RX_FLOW_CTRL_RFE_MASK +#define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK EMAC_MAC_RX_FLOW_CTRL_UP_MASK +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT EMAC_MAC_TX_FLOW_CTRL_Q_PT +#define ENET_QOS_MAC_CONFIGURATION_IPC EMAC_MAC_CONFIGURATION_IPC +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK EMAC_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0 EMAC_MAC_TXQ_PRTY_MAP0_PSTQ0 +#define ENET_QOS_MAC_RXQ_CTRL_COUNT EMAC_MAC_RXQ_CTRL_COUNT +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK EMAC_MAC_RXQ_CTRL_PSRQ0_MASK +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0 EMAC_MAC_RXQ_CTRL_PSRQ0 +#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN EMAC_MAC_RXQ_CTRL_RXQ0EN +#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK EMAC_MAC_RXQ_CTRL_AVCPQ_MASK +#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ EMAC_MAC_RXQ_CTRL_AVCPQ +#define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK EMAC_MAC_RXQ_CTRL_TACPQE_MASK +#define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK EMAC_MAC_RXQ_CTRL_PTPQ_MASK +#define ENET_QOS_MAC_RXQ_CTRL_PTPQ EMAC_MAC_RXQ_CTRL_PTPQ +#define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK EMAC_MAC_RXQ_CTRL_UPQ_MASK +#define ENET_QOS_MAC_RXQ_CTRL_UPQ EMAC_MAC_RXQ_CTRL_UPQ +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK EMAC_MAC_RXQ_CTRL_MCBCQ_MASK +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ EMAC_MAC_RXQ_CTRL_MCBCQ +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK EMAC_MAC_RXQ_CTRL_MCBCQEN_MASK +#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK EMAC_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK +#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK EMAC_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK +#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK EMAC_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK +#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK EMAC_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK +#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK EMAC_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK +#define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK EMAC_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK EMAC_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y EMAC_DMA_CHX_RX_CTRL_RBSZ_13_y +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC EMAC_MAC_SUB_SECOND_INCREMENT_SSINC +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK +#define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK EMAC_DMA_CHX_TX_CTRL_ST_MASK +#define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK EMAC_MTL_TXQX_DBG_TXQSTS_MASK +#define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK EMAC_MTL_TXQX_DBG_PTXQ_MASK +#define ENET_QOS_MAC_CONFIGURATION_TE_MASK EMAC_MAC_CONFIGURATION_TE_MASK +#define ENET_QOS_MAC_CONFIGURATION_RE_MASK EMAC_MAC_CONFIGURATION_RE_MASK +#define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK EMAC_DMA_CHX_RX_CTRL_SR_MASK +#define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK EMAC_DMA_CHX_INT_EN_AIE_MASK +#define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK EMAC_DMA_CHX_INT_EN_NIE_MASK +#define ENET_QOS_MAC_CONFIGURATION_DM_MASK EMAC_MAC_CONFIGURATION_DM_MASK +#define ENET_QOS_MAC_CONFIGURATION_PS_MASK EMAC_MAC_CONFIGURATION_PS_MASK +#define ENET_QOS_MAC_CONFIGURATION_FES_MASK EMAC_MAC_CONFIGURATION_FES_MASK +#define ENET_QOS_MAC_MDIO_ADDRESS_CR EMAC_MAC_MDIO_ADDRESS_CR +#define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK EMAC_MAC_MDIO_ADDRESS_CR_MASK +#define ENET_QOS_MAC_MDIO_ADDRESS_PA EMAC_MAC_MDIO_ADDRESS_PA +#define ENET_QOS_MAC_MDIO_ADDRESS_RDA EMAC_MAC_MDIO_ADDRESS_RDA +#define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK EMAC_MAC_MDIO_ADDRESS_C45E_MASK +#define ENET_QOS_MAC_MDIO_DATA_RA EMAC_MAC_MDIO_DATA_RA +#define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK EMAC_MTL_OPERATION_MODE_FRPE_MASK +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK EMAC_MTL_RXP_CONTROL_STATUS_RXPI_MASK +#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0 EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0 +#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0 EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0 +#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR EMAC_MTL_EST_GCL_CONTROL_ADDR +#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO EMAC_MTL_EST_GCL_CONTROL_SRWO +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM EMAC_MTL_EST_GCL_CONTROL_DBGM +#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR EMAC_MTL_EST_GCL_CONTROL_GCRR +#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0 EMAC_MTL_EST_GCL_CONTROL_R1W0 +#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK EMAC_MTL_EST_GCL_CONTROL_SRWO_MASK +#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK EMAC_MTL_EST_GCL_CONTROL_ERR0_MASK +#define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK EMAC_MTL_EST_CONTROL_SSWL_MASK +#define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK EMAC_MTL_EST_CONTROL_PTOV_MASK +#define ENET_QOS_MTL_EST_CONTROL_EEST_MASK EMAC_MTL_EST_CONTROL_EEST_MASK +#define ENET_QOS_MTL_EST_CONTROL_PTOV EMAC_MTL_EST_CONTROL_PTOV +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK EMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK +#define ENET_QOS_DMA_CHX_STAT_RI_MASK EMAC_DMA_CHX_STAT_RI_MASK +#define ENET_QOS_DMA_CHX_STAT_NIS_MASK EMAC_DMA_CHX_STAT_NIS_MASK +#define ENET_QOS_DMA_CHX_STAT_TI_MASK EMAC_DMA_CHX_STAT_TI_MASK +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK EMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK +#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK EMAC_DMA_INTERRUPT_STATUS_MACIS_MASK +#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK EMAC_MAC_INTERRUPT_STATUS_TSIS_MASK +#define MAC_MMC_RX_INTERRUPT_MASK MMC_RX_INTERRUPT_MASK +#define MAC_MMC_TX_INTERRUPT_MASK MMC_TX_INTERRUPT_MASK +#define MAC_MMC_FPE_RX_INTERRUPT_MASK MMC_FPE_RX_INTERRUPT_MASK +#define MAC_MMC_FPE_TX_INTERRUPT_MASK MMC_FPE_TX_INTERRUPT_MASK +#define MAC_RX_PACKETS_COUNT_GOOD_BAD RX_PACKETS_COUNT_GOOD_BAD +#define MAC_RX_CRC_ERROR_PACKETS RX_CRC_ERROR_PACKETS +#define MAC_RX_ALIGNMENT_ERROR_PACKETS RX_ALIGNMENT_ERROR_PACKETS +#define MAC_RX_LENGTH_ERROR_PACKETS RX_LENGTH_ERROR_PACKETS +#define MAC_RX_FIFO_OVERFLOW_PACKETS RX_FIFO_OVERFLOW_PACKETS +#define MAC_TX_PACKET_COUNT_GOOD_BAD TX_PACKET_COUNT_GOOD_BAD +#define MAC_TX_UNDERFLOW_ERROR_PACKETS TX_UNDERFLOW_ERROR_PACKETS + #endif #endif /*! @@ -32,7 +216,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief Defines the driver version. */ -#define FSL_ENET_QOS_DRIVER_VERSION (MAKE_VERSION(2, 6, 5)) +#define FSL_ENET_QOS_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) /*! @} */ /*! @name Control and status region bit masks of the receive buffer descriptor. */ @@ -276,7 +460,9 @@ typedef enum _enet_qos_dma_interrupt_enable */ typedef enum _enet_qos_mac_interrupt_enable { +#ifdef ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK kENET_QOS_MacPmt = (ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET), +#endif /* ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK */ kENET_QOS_MacTimestamp = (ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET), } enet_qos_mac_interrupt_enable_t; @@ -327,7 +513,9 @@ typedef enum _enet_qos_rx_queue_route kENET_QOS_PacketNoQ = 0x0, /* Not specific queue */ kENET_QOS_PacketAVCPQ = (1U << 0U), /* AV Untagged Control Packets Queue */ kENET_QOS_PacketPTPQ = (1U << 1U), /* PTP Packets Queue */ +#if defined(ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK) && defined(ENET_QOS_MAC_RXQ_CTRL_DCBCPQ) kENET_QOS_PacketDCBCPQ = (1U << 2U), /* DCB Control Packets Queue */ +#endif /* ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK && ENET_QOS_MAC_RXQ_CTRL_DCBCPQ */ kENET_QOS_PacketUPQ = (1U << 3U), /* Untagged Packets Queue */ kENET_QOS_PacketMCBCQ = (1U << 4U), /* Multicast & Broadcast Packets Queue */ } enet_qos_rx_queue_route_t; @@ -1144,6 +1332,7 @@ static inline void ENET_QOS_RejectAllMulticast(ENET_QOS_Type *base) base->MAC_PACKET_FILTER = reg & ~ENET_QOS_MAC_PACKET_FILTER_PM_MASK; } +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS /*! * @brief Set the MAC to enter into power down mode. * the remote power wake up frame and magic frame can wake up @@ -1173,6 +1362,7 @@ static inline void ENET_QOS_ExitPowerDown(ENET_QOS_Type *base) base->DMA_CH[1].DMA_CHX_TX_CTRL |= ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK; base->MAC_CONFIGURATION |= ENET_QOS_MAC_CONFIGURATION_TE_MASK; } +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ /*! * @brief Enable/Disable Rx parser,please notice that for enable/disable Rx Parser, @@ -1401,6 +1591,7 @@ static inline uint32_t ENET_QOS_GetRxDescriptor(enet_qos_rx_bd_struct_t *rxDesc) void ENET_QOS_UpdateRxDescriptor( enet_qos_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable); +#ifndef ENET_QOS_EMAC_USED_AS_ENET_QOS /*! * @brief Configure flexible rx parser. * @@ -1413,6 +1604,7 @@ void ENET_QOS_UpdateRxDescriptor( * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout. */ status_t ENET_QOS_ConfigureRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryCount); +#endif /* ENET_QOS_EMAC_USED_AS_ENET_QOS */ /*! * @brief Read flexible rx parser configuration at specified index. diff --git a/mcux/mcux-sdk-ng/drivers/erm/fsl_erm.c b/mcux/mcux-sdk-ng/drivers/erm/fsl_erm.c index c07147633..a8e5999e7 100644 --- a/mcux/mcux-sdk-ng/drivers/erm/fsl_erm.c +++ b/mcux/mcux-sdk-ng/drivers/erm/fsl_erm.c @@ -1,8 +1,7 @@ /* - * Copyright 2022 NXP + * Copyright 2022, 2025 NXP * All rights reserved. * - * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,6 +30,11 @@ static ERM_Type *const s_ermBases[] = ERM_BASE_PTRS; /*! @brief Pointers to ERM clocks for each instance. */ static const clock_ip_name_t s_ermClocks[] = ERM_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(ERM_RSTS_N) +/*! @brief Pointers to ERM clocks for each instance. */ +static const clock_ip_name_t s_ermResets[] = ERM_RSTS_N; +#endif /******************************************************************************* * Code ******************************************************************************/ @@ -64,6 +68,11 @@ void ERM_Init(ERM_Type *base) CLOCK_EnableClock(s_ermClocks[ERM_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(ERM_RSTS_N) + /* Reset the ERM module */ + RESET_PeripheralReset(s_ermResets[ERM_GetInstance(base)]); +#endif + base->CR0 = 0x00U; #ifdef ERM_CR1_ENCIE8_MASK base->CR1 = 0x00U; diff --git a/mcux/mcux-sdk-ng/drivers/erm/fsl_erm.h b/mcux/mcux-sdk-ng/drivers/erm/fsl_erm.h index 45303523e..b772fb537 100644 --- a/mcux/mcux-sdk-ng/drivers/erm/fsl_erm.h +++ b/mcux/mcux-sdk-ng/drivers/erm/fsl_erm.h @@ -1,8 +1,7 @@ /* - * Copyright 2022 NXP + * Copyright 2022, 2025 NXP * All rights reserved. * - * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief Driver version. */ -#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U)) /*! @} */ /*! @@ -143,12 +142,12 @@ static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel { if ((uint32_t)channel <= 0x07U) { - return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U); + return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U) & 0xFU; } #ifdef ERM_SR1_SBC8_MASK else { - return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U)) & 0xFU; } #else { diff --git a/mcux/mcux-sdk-ng/drivers/flash/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/flash/CMakeLists.txt index 9ed999598..6ea14d45e 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/flash/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.flash) - mcux_component_version(3.1.3) + mcux_component_version(3.3.0) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_flash.h b/mcux/mcux-sdk-ng/drivers/flash/fsl_flash.h index 429d33b8a..5b18ee781 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_flash.h +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_flash.h @@ -1,6 +1,6 @@ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_adapter.h b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_adapter.h index c21ab3aff..36230b526 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_adapter.h +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_adapter.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -115,6 +115,10 @@ #define FTFx_FCCOB5_REG (FTFx->FCCOB5) #define FTFx_FCCOB6_REG (FTFx->FCCOB6) #define FTFx_FCCOB7_REG (FTFx->FCCOB7) +#if defined(FTFC) +#define FTFx_FCCOB8_REG (FTFx->FCCOB8) +#define FTFx_FCCOB9_REG (FTFx->FCCOB9) +#endif #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) #if defined(FTFA_FPROTSL_PROTS_MASK) || defined(FTFE_FPROTSL_PROTS_MASK) || defined(FTFL_FPROTSL_PROTS_MASK) @@ -190,7 +194,7 @@ #define MCM0_CACHE_REG MCM0->PLACR #elif defined(MCM) && (!defined(MCM1)) #define MCM0_CACHE_REG MCM->PLACR -#else +#else #define MCM0_CACHE_REG (INVALID_REG_ADDRESS) #endif diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_cache.c b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_cache.c index 6bcab766e..e8e02a820 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_cache.c +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_cache.c @@ -1,6 +1,6 @@ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_cache.h b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_cache.h index 0bba177d4..f678ce55e 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_cache.h +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_cache.h @@ -1,6 +1,6 @@ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_controller.c b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_controller.c index ce5812c31..342f4740c 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_controller.c +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_controller.c @@ -1,6 +1,6 @@ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -239,10 +239,10 @@ status_t FTFx_API_UpdateFlexnvmPartitionStatus(ftfx_config_t *config) { uint32_t flexnvmInfoIfrAddr; status_t returnCode; - + flexnvmInfoIfrAddr = config->ifrDesc.resRange.dflashIfrStart + config->ifrDesc.resRange.ifrMemSize - sizeof(dataIFRReadOut); - + returnCode = FTFx_CMD_ReadResource(config, flexnvmInfoIfrAddr, (uint8_t *)&dataIFRReadOut, sizeof(dataIFRReadOut), kFTFx_ResourceOptionFlashIfr); if (returnCode != kStatus_FTFx_Success) @@ -250,16 +250,16 @@ status_t FTFx_API_UpdateFlexnvmPartitionStatus(ftfx_config_t *config) return kStatus_FTFx_PartitionStatusUpdateFailure; } } - + #elif defined(SIM_FCFG1_DEPART_MASK) { uint32_t dflashSize; uint32_t dflashTotalSize; - + dataIFRReadOut.FlexNVMPartitionCode = (uint8_t)((SIM->FCFG1 & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT); dflashSize = kDflashDensities[dataIFRReadOut.FlexNVMPartitionCode & 0x0FU]; dflashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; - + if (dflashSize < dflashTotalSize) { dataIFRReadOut.EEPROMDataSetSize = (uint8_t)((SIM->FCFG1 & SIM_FCFG1_EEERAMSIZE_MASK) >> SIM_FCFG1_EEERAMSIZE_SHIFT); @@ -272,7 +272,7 @@ status_t FTFx_API_UpdateFlexnvmPartitionStatus(ftfx_config_t *config) } #else - + #error "Cannot get FlexNVM memory partition info" #endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ @@ -1140,12 +1140,15 @@ status_t FTFx_REG_GetSecurityState(ftfx_config_t *config, ftfx_security_state_t } #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /*! * @brief Sets the FlexRAM function command. */ + status_t FTFx_CMD_SetFlexramFunction(ftfx_config_t *config, ftfx_flexram_func_opt_t option) { status_t status; + if (config == NULL) { return kStatus_FTFx_InvalidArgument; @@ -1157,12 +1160,54 @@ status_t FTFx_CMD_SetFlexramFunction(ftfx_config_t *config, ftfx_flexram_func_op return status; } - /* preparing passing parameter to verify all block command */ kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); - /* calling flash command sequence function to execute the command */ return ftfx_command_sequence(config); } + +#ifdef FSL_FEATURE_FLASH_IS_FTFC + +/*! + * @brief Sets the FlexRAM function command with EEPROM Quick Write support + */ + +status_t FTFx_CMD_SetFlexramFunction_QuickWrite(ftfx_config_t *config, ftfx_flexram_func_opt_t option, uint16_t qwSize, ftfx_flexram_eeprom_qw_status *returnInfo) +{ + status_t status; + status_t returnCode; + + if (config == NULL) + { + return kStatus_FTFx_InvalidArgument; + } + + status = ftfx_check_flexram_function_option(option); + if (kStatus_FTFx_Success != status) + { + return status; + } + + kFCCOBx[0] = BYTE2WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); + + if (option == kFTFx_FlexramFuncOptAvailableForEepromQuickWrite) + { + kFCCOBx[1] = BYTE2WORD_2_2(qwSize, 0xFFFFU); + } + + returnCode = ftfx_command_sequence(config); + + if (returnInfo != NULL) + { + returnInfo->brownoutStatus = (ftfx_eeprom_qw_bo_code)FTFx_FCCOB5_REG; + returnInfo->recordsRequireMaintenanceCount = (FTFx_FCCOB6_REG << 8) | FTFx_FCCOB7_REG; + returnInfo->sectorEraseCount = (FTFx_FCCOB8_REG << 8) | FTFx_FCCOB9_REG; + } + + return returnCode; +} + +#endif /* FSL_FEATURE_FLASH_IS_FTFC */ + #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ #if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD @@ -1525,7 +1570,13 @@ static status_t ftfx_check_resource_range(ftfx_config_t *config, /*! @brief Validates the given flexram function option.*/ static inline status_t ftfx_check_flexram_function_option(ftfx_flexram_func_opt_t option) { - if ((option != kFTFx_FlexramFuncOptAvailableAsRam) && (option != kFTFx_FlexramFuncOptAvailableForEeprom)) + if ((option != kFTFx_FlexramFuncOptAvailableAsRam) && (option != kFTFx_FlexramFuncOptAvailableForEeprom) +#ifdef FSL_FEATURE_FLASH_IS_FTFC + && (option != kFTFx_FlexramFuncOptEepromQuickWriteRecovery) + && (option != kFTFx_FlexramFuncOptEepromQuickWriteStatus) + && (option != kFTFx_FlexramFuncOptAvailableForEepromQuickWrite) +#endif + ) { return kStatus_FTFx_InvalidArgument; } diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_controller.h b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_controller.h index ed248e19a..aa7085064 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_controller.h +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_controller.h @@ -1,6 +1,6 @@ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -149,10 +149,14 @@ typedef enum _ftfx_security_state */ typedef enum _ftfx_flexram_function_option { - kFTFx_FlexramFuncOptAvailableAsRam = 0xFFU, /*!< An option used to make FlexRAM available as RAM */ - kFTFx_FlexramFuncOptAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */ + kFTFx_FlexramFuncOptAvailableAsRam = 0xFFU, /*!< An option used to make FlexRAM available as RAM */ + kFTFx_FlexramFuncOptEepromQuickWriteRecovery = 0xAAU, /*!< An option used to complete interrupted EEPROM quick write process */ + kFTFx_FlexramFuncOptEepromQuickWriteStatus = 0x77U, /*!< An option used to make EEPROM quick write status query */ + kFTFx_FlexramFuncOptAvailableForEepromQuickWrite = 0x55U, /*!< An option used to make FlexRAM available for EEPROM in Quick Write mode */ + kFTFx_FlexramFuncOptAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */ } ftfx_flexram_func_opt_t; + /*! * @brief Enumeration for acceleration ram property. */ @@ -211,6 +215,33 @@ typedef struct _ftfx_swap_state_config } ftfx_swap_state_config_t; #endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#ifdef FSL_FEATURE_FLASH_IS_FTFC + +/*! + * @brief Enumeration for EEPROM Quick Write Brown-out detection codes + */ +typedef enum _ftfx_eeprom_qw_bo_code +{ + kFTFx_EepromQW_BO_NoIssue = 0x00U, /*!< No EEPROM issues detected. */ + kFTFx_EepromQW_BO_BeforeQWMaintenance = 0x01U, /*!< BO detected before completing EEPROM quick write maintenance.*/ + kFTFx_EepromQW_BO_BeforeQW = 0x02U, /*!< BO detected before completing EEPROM quick writes.*/ + kFTFx_EepromQW_BO_DuringNormalWrite = 0x04U, /*!< BO detected during normal EEPROM write activity.*/ +} ftfx_eeprom_qw_bo_code; + +/*! + * @brief EEPROM Quick Write Status + */ + +typedef struct _ftfx_flexram_eeprom_qw_status +{ + ftfx_eeprom_qw_bo_code brownoutStatus; + uint16_t recordsRequireMaintenanceCount; + uint16_t sectorEraseCount; +} ftfx_flexram_eeprom_qw_status; + +#endif /* FSL_FEATURE_FLASH_IS_FTFC */ + /*! * @brief Enumeration for FTFx memory type. */ @@ -793,6 +824,7 @@ status_t FTFx_CMD_SecurityBypass(ftfx_config_t *config, const uint8_t *backdoorK */ #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /*! * @brief Sets the FlexRAM function command. * @@ -806,7 +838,31 @@ status_t FTFx_CMD_SecurityBypass(ftfx_config_t *config, const uint8_t *backdoorK * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. */ + status_t FTFx_CMD_SetFlexramFunction(ftfx_config_t *config, ftfx_flexram_func_opt_t option); + +#ifdef FSL_FEATURE_FLASH_IS_FTFC + +/*! + * @brief Sets the FlexRAM function command with EEPROM Quick Write feature + * + * @param config A pointer to the storage for the driver runtime state. + * @param option The option used to set the work mode of FlexRAM. + * @param qwSize Number of FlexRAM bytes allocated for EEPROM quick writes + * @param returnInfo Pointer to Quick Write Status info, can be NULL when not used. + * + * @retval #kStatus_FTFx_Success API was executed successfully. + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ + +status_t FTFx_CMD_SetFlexramFunction_QuickWrite(ftfx_config_t *config, ftfx_flexram_func_opt_t option, uint16_t qwSize, ftfx_flexram_eeprom_qw_status *returnInfo); + +#endif /* #ifdef FSL_FEATURE_FLASH_IS_FTFC */ + #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ /*! @} */ diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_features.h b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_features.h index f42bf8d0a..89128a333 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_features.h +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_features.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2019 NXP + * Copyright 2017-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flash.c b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flash.c index c0c9e99e0..b7939bf5f 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flash.c +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flash.c @@ -1,6 +1,6 @@ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020, 2023 NXP + * Copyright 2016-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -176,7 +176,7 @@ status_t FLASH_Init(flash_config_t *config) for (uint8_t flashIndex = 0U; flashIndex < FTFx_FLASH_COUNT; flashIndex++) { - /* init flash type, kinetis has Pflash and flxnvm, pflash is often used to store executable code + /* init flash type, for chips which have Pflash and flxnvm, pflash is often used to store executable code * and flexnvm can be used as date flash to store user data, and can also be configured as eeprom backup space * with flexram. */ diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flash.h b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flash.h index 5204300f5..af1c616ca 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flash.h +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flash.h @@ -1,6 +1,6 @@ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -27,7 +27,7 @@ * @{ */ /*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(3U, 2U, 0U)) /*!< Version 3.1.3. */ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(3U, 3U, 0U)) /*!< Version 3.3.0. */ /*! @brief Flash driver version for ROM*/ #define FSL_FLASH_DRIVER_VERSION_ROM (MAKE_VERSION(3U, 0U, 0U)) /*!< Version 3.0.0. */ diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flexnvm.c b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flexnvm.c index 75fd10583..315407d5a 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flexnvm.c +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flexnvm.c @@ -1,6 +1,6 @@ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -242,6 +242,7 @@ status_t FLEXNVM_SecurityBypass(flexnvm_config_t *config, const uint8_t *backdoo } #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /*! * @brief Sets the FlexRAM function command. */ @@ -249,6 +250,19 @@ status_t FLEXNVM_SetFlexramFunction(flexnvm_config_t *config, ftfx_flexram_func_ { return FTFx_CMD_SetFlexramFunction(&config->ftfxConfig, option); } + +#ifdef FSL_FEATURE_FLASH_IS_FTFC + +/*! + * @brief Sets the FlexRAM function command with EEPROM Quick Write support + */ +status_t FLEXNVM_SetFlexramFunction_QuickWrite(flexnvm_config_t *config, ftfx_flexram_func_opt_t option, uint16_t qwSize, ftfx_flexram_eeprom_qw_status *returnInfo) +{ + return FTFx_CMD_SetFlexramFunction_QuickWrite(&config->ftfxConfig, option, qwSize, returnInfo); +} + +#endif /* FSL_FEATURE_FLASH_IS_FTFC */ + #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ /*! diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flexnvm.h b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flexnvm.h index 241b04fdb..880c315ba 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flexnvm.h +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_flexnvm.h @@ -1,6 +1,6 @@ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -438,6 +438,7 @@ status_t FLEXNVM_SecurityBypass(flexnvm_config_t *config, const uint8_t *backdoo */ #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /*! * @brief Sets the FlexRAM function command. * @@ -454,6 +455,31 @@ status_t FLEXNVM_SecurityBypass(flexnvm_config_t *config, const uint8_t *backdoo * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. */ status_t FLEXNVM_SetFlexramFunction(flexnvm_config_t *config, ftfx_flexram_func_opt_t option); + + +#ifdef FSL_FEATURE_FLASH_IS_FTFC + +/*! + * @brief Sets the FlexRAM function command with EEPROM Quick Write support + * + * @param config A pointer to the storage for the driver runtime state. + * @param option The option used to set the work mode of FlexRAM. + * @param qwSize Number of FlexRAM bytes allocated for EEPROM quick writes + * @param returnInfo Pointer to Quick Write Status info, can be NULL when not used. + * + * @retval #kStatus_FTFx_Success API was executed successfully; + * the FlexRAM has been successfully configured as RAM or EEPROM + * + * @retval #kStatus_FTFx_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available. + * @retval #kStatus_FTFx_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FTFx_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FTFx_CommandFailure Run-time error during the command execution. + */ +status_t FLEXNVM_SetFlexramFunction_QuickWrite(flexnvm_config_t *config, ftfx_flexram_func_opt_t option, uint16_t qwSize, ftfx_flexram_eeprom_qw_status *returnInfo); + +#endif /* FSL_FEATURE_FLASH_IS_FTFC */ + #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ /*! @} */ diff --git a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_utilities.h b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_utilities.h index a3f9a84f6..443d18cdb 100644 --- a/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_utilities.h +++ b/mcux/mcux-sdk-ng/drivers/flash/fsl_ftfx_utilities.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/drivers/flash_c40/fsl_c40_flash.c b/mcux/mcux-sdk-ng/drivers/flash_c40/fsl_c40_flash.c index b543bd6b7..31395a57c 100644 --- a/mcux/mcux-sdk-ng/drivers/flash_c40/fsl_c40_flash.c +++ b/mcux/mcux-sdk-ng/drivers/flash_c40/fsl_c40_flash.c @@ -7,6 +7,9 @@ */ /* + Version 1.2.0: + - UTEST write support + Version 1.1.0: - Generic setup for entire family @@ -36,7 +39,7 @@ #if defined(__IAR_SYSTEMS_ICC__) #define RAMFUNC __ramfunc #elif defined(__GNUC__) -#define RAMFUNC __attribute__((section(".ramfunc"))) __attribute__((__noinline__)) +#define RAMFUNC __attribute__((section("CodeQuickAccess"), __noinline__)) #else #error "Unsupported toolchain" #endif @@ -59,6 +62,9 @@ #define C40_BASE_ADDR_DATA (0x10000000) #define C40_END_ADDR_DATA (C40_BASE_ADDR_DATA + (C40_BLOCK_SIZE_DATA * C40_BLOCK_COUNT_DATA) - 1) +#define C40_BASE_ADDR_UTEST (0x1B000000) +#define C40_END_ADDR_UTEST (0x1B001FFF) + #define C40_SECTOR_SIZE ( 8 * 1024) #define C40_SUPER_SECTOR_SIZE (64 * 1024) @@ -100,8 +106,9 @@ #define C40_WRITE_SIZE_MAX C40_QUAD_PAGE_SIZE -#define LOGADDR_IN_CODE_REGION(a) ((a) >= C40_BASE_ADDR_CODE && (a) <= C40_END_ADDR_CODE) -#define LOGADDR_IN_DATA_REGION(a) ((a) >= C40_BASE_ADDR_DATA && (a) <= C40_END_ADDR_DATA) +#define LOGADDR_IN_CODE_REGION(a) ((a) >= C40_BASE_ADDR_CODE && (a) <= C40_END_ADDR_CODE) +#define LOGADDR_IN_DATA_REGION(a) ((a) >= C40_BASE_ADDR_DATA && (a) <= C40_END_ADDR_DATA) +#define LOGADDR_IN_UTEST_REGION(a) ((a) >= C40_BASE_ADDR_UTEST && (a) <= C40_END_ADDR_UTEST) /* The driver partly works with Core Domain ID support. @@ -247,6 +254,12 @@ static status_t C40_AddrToSectorNum(uint32_t address, uint32_t *sectorNum) sector = (address - C40_BASE_ADDR_DATA) / C40_SECTOR_SIZE; sector += C40_SECTOR_COUNT_CODE; } + else if (LOGADDR_IN_UTEST_REGION(address)) + { + /* UTEST flash */ + /* Writing to UTEST is considered as a special case */ + sector = C40_SECTOR_COUNT_TOTAL; + } else { return kStatus_FLASH_AddressError; @@ -277,13 +290,21 @@ static status_t C40_LockSectorIndex(uint32_t sectorNum, uint32_t *lockSectorInde uint32_t index; volatile uint32_t *reg; - if (sectorNum >= C40_SECTOR_COUNT_TOTAL) + if (sectorNum > C40_SECTOR_COUNT_TOTAL) { return kStatus_FLASH_AddressError; } - if (sectorNum >= C40_SECTOR_COUNT_CODE) + if (sectorNum == C40_SECTOR_COUNT_TOTAL) + { + /* UTEST flash */ + + index = 0; + reg = &(PFLASH->PFCBLKU_SPELOCK[0]); + + } + else if (sectorNum >= C40_SECTOR_COUNT_CODE) { /* DATA Flash */ @@ -560,7 +581,7 @@ static status_t C40_SectorErase(uint32_t sectorNum, uint8_t callerDomainId) static void C40_FillDataBuff(uint32_t dataRegIndex, const uint8_t *src, uint32_t length) { assert(dataRegIndex < FLASH_DATA_COUNT); - assert(dataRegIndex + (length/4) < FLASH_DATA_COUNT); + assert(dataRegIndex + (length/4) <= FLASH_DATA_COUNT); const uint32_t *src32 = (const uint32_t *) src; const uint8_t *src8 = src; @@ -878,4 +899,4 @@ status_t FLASH_GetSectorProtection(flash_config_t *config, uint32_t address) } return C40_SectorLockStatus(sectorNum); -} \ No newline at end of file +} diff --git a/mcux/mcux-sdk-ng/drivers/flash_c40/fsl_c40_flash.h b/mcux/mcux-sdk-ng/drivers/flash_c40/fsl_c40_flash.h index 69b98a9d6..d3a134b31 100644 --- a/mcux/mcux-sdk-ng/drivers/flash_c40/fsl_c40_flash.h +++ b/mcux/mcux-sdk-ng/drivers/flash_c40/fsl_c40_flash.h @@ -18,7 +18,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief eDMA driver version */ -#define FSL_FLASH_C40_DRIVER_VERSION (MAKE_VERSION(1, 1, 0)) +#define FSL_FLASH_C40_DRIVER_VERSION (MAKE_VERSION(1, 2, 0)) /*! @} */ diff --git a/mcux/mcux-sdk-ng/drivers/flash_k4/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/flash_k4/CMakeLists.txt index 104c8e8c2..4fff31eb1 100644 --- a/mcux/mcux-sdk-ng/drivers/flash_k4/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/flash_k4/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.flash_k4) - mcux_component_version(2.2.1) + mcux_component_version(2.3.3) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_controller.c b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_controller.c index bf2729025..c077464e4 100644 --- a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_controller.c +++ b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_controller.c @@ -36,13 +36,13 @@ * Prototypes ******************************************************************************/ -static void flash_command_pre_sequence(FMU_Type *base); +static status_t flash_command_pre_sequence(FMU_Type *base); -static void flash_command_sequence(FMU_Type *base); +static status_t flash_command_sequence(FMU_Type *base); -static void flash_erase_sequence(FMU_Type *base, uint32_t start); +static status_t flash_erase_sequence(FMU_Type *base, uint32_t start); -static void flash_pgm_sequence(FMU_Type *base, uint32_t start, uint32_t *src, uint8_t isPage); +static status_t flash_pgm_sequence(FMU_Type *base, uint32_t start, uint32_t *src, uint8_t isPage); /*! @brief Internal function Flash command*/ static status_t flash_command_complete(FMU_Type *base); @@ -63,11 +63,19 @@ status_t FLASH_CMD_EraseSector(FMU_Type *base, uint32_t start) /* Clear flash cache before every erase to prevent the possibility of returning stale data */ MCM->CPCR2 |= MCM_CPCR2_CCBC_MASK; #endif - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* preparing passing parameter to erase a sector flash */ base->FCCOB[0] = FLASH_ERASE_SECTOR; /* Erase Command sequence */ - flash_erase_sequence(base, start); + returnCode = flash_erase_sequence(base, start); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* check command completion and error handling */ returnCode = flash_command_complete(base); @@ -82,10 +90,20 @@ status_t FLASH_CMD_EraseAll(FMU_Type *base) /* Clear flash cache before every erase to prevent the possibility of returning stale data */ MCM->CPCR2 |= MCM_CPCR2_CCBC_MASK; #endif - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } + /* preparing passing parameter to erase all flash blocks */ base->FCCOB[0] = FLASH_ERASE_ALL; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } + /* calling flash command sequence function to execute the command */ returnCode = flash_command_complete(base); @@ -101,11 +119,20 @@ status_t FLASH_CMD_ProgramPhrase(FMU_Type *base, uint32_t start, uint32_t *src) /* Clear flash cache before every erase to prevent the possibility of returning stale data */ MCM->CPCR2 |= MCM_CPCR2_CCBC_MASK; #endif - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* preparing passing parameter to program the flash block */ base->FCCOB[0] = FLASH_PROGRAM_PHRASE; /* Program Command sequence */ - flash_pgm_sequence(base, start, src, isPage); + returnCode = flash_pgm_sequence(base, start, src, isPage); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } + returnCode = flash_command_complete(base); return returnCode; @@ -120,11 +147,20 @@ status_t FLASH_CMD_ProgramPage(FMU_Type *base, uint32_t start, uint32_t *src) /* Clear flash cache before every erase to prevent the possibility of returning stale data */ MCM->CPCR2 |= MCM_CPCR2_CCBC_MASK; #endif - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* preparing passing parameter to program the flash block */ base->FCCOB[0] = FLASH_PROGRAM_PAGE; /* Program Command sequence */ - flash_pgm_sequence(base, start, src, isPage); + returnCode = flash_pgm_sequence(base, start, src, isPage); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } + returnCode = flash_command_complete(base); return returnCode; @@ -134,11 +170,19 @@ status_t FLASH_CMD_VerifyErasePhrase(FMU_Type *base, uint32_t start) { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* Fill in verify erase phrase command parameters. */ base->FCCOB[0] = FLASH_VERIFY_ERASE_PHRASE; base->FCCOB[2] = start; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command sequence function to execute the command */ returnCode = flash_command_complete(base); @@ -149,11 +193,19 @@ status_t FLASH_CMD_VerifyErasePage(FMU_Type *base, uint32_t start) { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* Fill in verify erase page command parameters. */ base->FCCOB[0] = FLASH_VERIFY_ERASE_PAGE; base->FCCOB[2] = start; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command sequence function to execute the command */ returnCode = flash_command_complete(base); @@ -164,11 +216,19 @@ status_t FLASH_CMD_VerifyEraseSector(FMU_Type *base, uint32_t start) { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* Fill in verify erase sector command parameters. */ base->FCCOB[0] = FLASH_VERIFY_ERASE_SECTOR; base->FCCOB[2] = start; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command sequence function to execute the command */ returnCode = flash_command_complete(base); @@ -179,11 +239,19 @@ status_t FLASH_CMD_VerifyEraseIFRPhrase(FMU_Type *base, uint32_t start) { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* Fill in verify erase ifr phrase command parameters. */ base->FCCOB[0] = FLASH_VERIFY_ERASE_IFR_PHRASE; base->FCCOB[2] = start; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command function to execute the command */ returnCode = flash_command_complete(base); @@ -194,11 +262,19 @@ status_t FLASH_CMD_VerifyEraseIFRPage(FMU_Type *base, uint32_t start) { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* Fill in verify erase ifr page command parameters. */ base->FCCOB[0] = FLASH_VERIFY_ERASE_IFR_PAGE; base->FCCOB[2] = start; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command function to execute the command */ returnCode = flash_command_complete(base); @@ -209,11 +285,19 @@ status_t FLASH_CMD_VerifyEraseIFRSector(FMU_Type *base, uint32_t start) { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* Fill in verify erase ifr sector command parameters. */ base->FCCOB[0] = FLASH_VERIFY_ERASE_IFR_SECTOR; base->FCCOB[2] = start; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command function to execute the command */ returnCode = flash_command_complete(base); @@ -224,11 +308,19 @@ status_t FLASH_CMD_VerifyEraseBlock(FMU_Type *base, uint32_t blockaddr) { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* preparing passing parameter to verify erase block command */ base->FCCOB[0] = FLASH_VERIFY_ERASE_BLOCK; base->FCCOB[2] = blockaddr; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command sequence function to execute the command */ returnCode = flash_command_complete(base); @@ -239,10 +331,18 @@ status_t FLASH_CMD_VerifyEraseAll(FMU_Type *base) { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* preparing passing parameter to verify erase all command */ base->FCCOB[0] = FLASH_VERIFY_ERASE_ALL; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command sequence function to execute the command */ returnCode = flash_command_complete(base); return returnCode; @@ -252,7 +352,11 @@ status_t FLASH_CMD_ReadIntoMISR(FMU_Type *base, uint32_t start, uint32_t ending, { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* preparing passing parameter to read into misr command */ base->FCCOB[0] = FLASH_READ_INTO_MISR; base->FCCOB[2] = start; @@ -261,7 +365,11 @@ status_t FLASH_CMD_ReadIntoMISR(FMU_Type *base, uint32_t start, uint32_t ending, base->FCCOB[5] = seed[1]; base->FCCOB[6] = seed[2]; base->FCCOB[7] = seed[3]; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command sequence function to execute the command */ returnCode = flash_command_complete(base); @@ -280,7 +388,11 @@ status_t FLASH_CMD_ReadIFRIntoMISR(FMU_Type *base, uint32_t start, uint32_t endi { status_t returnCode = kStatus_Fail; - flash_command_pre_sequence(base); + returnCode = flash_command_pre_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* preparing passing parameter to read into misr command */ base->FCCOB[0] = FLASH_READ_IFR_INTO_MISR; base->FCCOB[2] = start; @@ -289,7 +401,11 @@ status_t FLASH_CMD_ReadIFRIntoMISR(FMU_Type *base, uint32_t start, uint32_t endi base->FCCOB[5] = seed[1]; base->FCCOB[6] = seed[2]; base->FCCOB[7] = seed[3]; - flash_command_sequence(base); + returnCode = flash_command_sequence(base); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } /* calling flash command sequence function to execute the command */ returnCode = flash_command_complete(base); @@ -319,8 +435,12 @@ __ramfunc __attribute__((section(".ramfunc"))) __attribute__((__noinline__)) #endif #endif -static void flash_command_pre_sequence(FMU_Type *base) +static status_t flash_command_pre_sequence(FMU_Type *base) { +#if FLASH_COMMAND_COMPLETE_TIMEOUT + uint32_t cmdCompleteTimeout = FLASH_COMMAND_COMPLETE_TIMEOUT; +#endif + if ((base->FSTAT & FLASH_FSTAT_DFDIF_MASK) != 0U) { /* Acknowledge previous ECC fault. The fault occured during a previous read or verify erase but too late to */ @@ -329,10 +449,18 @@ static void flash_command_pre_sequence(FMU_Type *base) // Check if previous command complete, CCIF==1, wait for CCIF set while (((base->FSTAT) & FLASH_FSTAT_CCIF_MASK) == 0U) { +#if FLASH_COMMAND_COMPLETE_TIMEOUT + if (--cmdCompleteTimeout == 0U) + { + return kStatus_FLASH_CommandCompleteTimeout; + } +#endif } /* clear CMDABT & ACCERR & PVIOL flag in flash status register */ base->FSTAT = (FLASH_FSTAT_CMDABT_MASK | FLASH_FSTAT_ACCERR_MASK | FLASH_FSTAT_PVIOL_MASK); + + return kStatus_FLASH_Success; } /*! @@ -350,15 +478,26 @@ __ramfunc __attribute__((section(".ramfunc"))) __attribute__((__noinline__)) #endif #endif -static void flash_command_sequence(FMU_Type *base) +static status_t flash_command_sequence(FMU_Type *base) { + #if FLASH_COMMAND_COMPLETE_TIMEOUT + uint32_t cmdCompleteTimeout = FLASH_COMMAND_COMPLETE_TIMEOUT; +#endif /* clear CCIF bit to launch the command */ base->FSTAT = FLASH_FSTAT_CCIF_MASK; /* Check CCIF bit of the flash status register, wait till it is set */ while ((base->FSTAT & FLASH_FSTAT_CCIF_MASK) == 0U) { +#if FLASH_COMMAND_COMPLETE_TIMEOUT + if (--cmdCompleteTimeout == 0U) + { + return kStatus_FLASH_CommandCompleteTimeout; + } +#endif } + + return kStatus_FLASH_Success; } /*! @@ -376,13 +515,28 @@ __ramfunc __attribute__((section(".ramfunc"))) __attribute__((__noinline__)) #endif #endif -static void flash_erase_sequence(FMU_Type *base, uint32_t start) +static status_t flash_erase_sequence(FMU_Type *base, uint32_t start) { +#if FLASH_COMMAND_COMPLETE_TIMEOUT + uint32_t cmdCompleteTimeout = FLASH_COMMAND_COMPLETE_TIMEOUT; +#endif +#if FLASH_WRITE_ENABLE_TIMEOUT + uint32_t writeEnableTimeout = FLASH_WRITE_ENABLE_TIMEOUT; +#endif +#if FLASH_PROGRAM_ERASE_READY_TIMEOUT + uint32_t programEraseReadyTimeout = FLASH_PROGRAM_ERASE_READY_TIMEOUT; +#endif /* clear CCIF bit to launch the command */ base->FSTAT = FLASH_FSTAT_CCIF_MASK; while ((base->FSTAT & FLASH_FSTAT_PEWEN_MASK) == 0U) { +#if FLASH_WRITE_ENABLE_TIMEOUT + if (--writeEnableTimeout == 0U) + { + return kStatus_FLASH_WriteEnableTimeout; + } +#endif } for (uint32_t i = 0u; i < 4u; i++) @@ -392,6 +546,12 @@ static void flash_erase_sequence(FMU_Type *base, uint32_t start) while ((base->FSTAT & FLASH_FSTAT_PERDY_MASK) == 0U) { +#if FLASH_PROGRAM_ERASE_READY_TIMEOUT + if (--programEraseReadyTimeout == 0U) + { + return kStatus_FLASH_ProgramEraseReadyTimeout; + } +#endif } base->FSTAT = FLASH_FSTAT_PERDY_MASK; @@ -399,7 +559,15 @@ static void flash_erase_sequence(FMU_Type *base, uint32_t start) /* Check CCIF bit of the flash status register, wait till it is set */ while ((base->FSTAT & FLASH_FSTAT_CCIF_MASK) == 0U) { +#if FLASH_COMMAND_COMPLETE_TIMEOUT + if (--cmdCompleteTimeout == 0U) + { + return kStatus_FLASH_CommandCompleteTimeout; + } +#endif } + + return kStatus_FLASH_Success; } /*! @@ -417,13 +585,28 @@ __ramfunc __attribute__((section(".ramfunc"))) __attribute__((__noinline__)) #endif #endif -static void flash_pgm_sequence(FMU_Type *base, uint32_t start, uint32_t *src, uint8_t isPage) +static status_t flash_pgm_sequence(FMU_Type *base, uint32_t start, uint32_t *src, uint8_t isPage) { +#if FLASH_COMMAND_COMPLETE_TIMEOUT + uint32_t cmdCompleteTimeout = FLASH_COMMAND_COMPLETE_TIMEOUT; +#endif +#if FLASH_WRITE_ENABLE_TIMEOUT + uint32_t writeEnableTimeout = FLASH_WRITE_ENABLE_TIMEOUT; +#endif +#if FLASH_PROGRAM_ERASE_READY_TIMEOUT + uint32_t programEraseReadyTimeout = FLASH_PROGRAM_ERASE_READY_TIMEOUT; +#endif /* clear CCIF bit to launch the command */ base->FSTAT = FLASH_FSTAT_CCIF_MASK; while ((base->FSTAT & FLASH_FSTAT_PEWEN_MASK) == 0U) { +#if FLASH_WRITE_ENABLE_TIMEOUT + if (--writeEnableTimeout == 0U) + { + return kStatus_FLASH_WriteEnableTimeout; + } +#endif } uint8_t lengthInWord; @@ -444,6 +627,12 @@ static void flash_pgm_sequence(FMU_Type *base, uint32_t start, uint32_t *src, ui while ((base->FSTAT & FLASH_FSTAT_PERDY_MASK) == 0U) { +#if FLASH_PROGRAM_ERASE_READY_TIMEOUT + if (--programEraseReadyTimeout == 0U) + { + return kStatus_FLASH_ProgramEraseReadyTimeout; + } +#endif } base->FSTAT = FLASH_FSTAT_PERDY_MASK; @@ -451,7 +640,15 @@ static void flash_pgm_sequence(FMU_Type *base, uint32_t start, uint32_t *src, ui /* Check CCIF bit of the flash status register, wait till it is set */ while ((base->FSTAT & FLASH_FSTAT_CCIF_MASK) == 0U) { +#if FLASH_COMMAND_COMPLETE_TIMEOUT + if (--cmdCompleteTimeout == 0U) + { + return kStatus_FLASH_CommandCompleteTimeout; + } +#endif } + + return kStatus_FLASH_Success; } /*! diff --git a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_controller.h b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_controller.h index 7c200be67..426c6ea39 100644 --- a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_controller.h +++ b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_controller.h @@ -76,7 +76,57 @@ enum kStatus_FLASH_CommandAborOption = MAKE_STATUS(kStatusGroupFlashDriver, 21), /*!< The option of flash prefetch speculation is invalid.*/ kStatus_FLASH_EccFaultDetected = MAKE_STATUS(kStatusGroupFlashDriver, 22), /*!< An ECC double fault occurred.*/ + kStatus_FLASH_CommandCompleteTimeout = MAKE_STATUS(kStatusGroupFlashDriver, 23), /*!< Flash command complete timeout occurred.*/ + kStatus_FLASH_WriteEnableTimeout = MAKE_STATUS(kStatusGroupFlashDriver, 24), /*!< Flash writes are enabled timeout occurred.*/ + kStatus_FLASH_ProgramEraseReadyTimeout = MAKE_STATUS(kStatusGroupFlashDriver, 25), /*!< Flash program-erase ready timeout occurred.*/ }; + +/*! + * @brief Maximum loop wait time for flash command operations. + * + * When flash is processing the command, driver will wait for the command to complete. + * This parameter defines how many loops to check completion before return timeout. + * If defined as 0, driver will wait forever until completion. + */ +#ifndef FLASH_COMMAND_COMPLETE_TIMEOUT + #ifdef CONFIG_FLASH_COMMAND_COMPLETE_TIMEOUT + #define FLASH_COMMAND_COMPLETE_TIMEOUT CONFIG_FLASH_COMMAND_COMPLETE_TIMEOUT + #else + #define FLASH_COMMAND_COMPLETE_TIMEOUT 0U + #endif +#endif + +/*! + * @brief Maximum loop wait time for flash program-erase write enable. + * + * During program or sector erase command operations, driver will wait for the operations to complete. + * This parameter defines how many loops to check completion before return timeout. + * If defined as 0, driver will wait forever until completion. + */ +#ifndef FLASH_WRITE_ENABLE_TIMEOUT + #ifdef CONFIG_FLASH_WRITE_ENABLE_TIMEOUT + #define FLASH_WRITE_ENABLE_TIMEOUT CONFIG_FLASH_WRITE_ENABLE_TIMEOUT + #else + #define FLASH_WRITE_ENABLE_TIMEOUT 0U + #endif +#endif + +/*! + * @brief Maximum loop wait time for flash program-erase ready. + * + * The program-erase ready flag is set by the command controller when a program or sector erase command + * operation has successfully completed the write phase. This parameter defines how many loops to check + * completion before return timeout. + * If defined as 0, driver will wait forever until completion. + */ +#ifndef FLASH_PROGRAM_ERASE_READY_TIMEOUT + #ifdef CONFIG_FLASH_PROGRAM_ERASE_READY_TIMEOUT + #define FLASH_PROGRAM_ERASE_READY_TIMEOUT CONFIG_FLASH_PROGRAM_ERASE_READY_TIMEOUT + #else + #define FLASH_PROGRAM_ERASE_READY_TIMEOUT 0U + #endif +#endif + /*! @} */ /******************************************************************************* * API diff --git a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.c b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.c index 7a590bcdd..6de74b98d 100644 --- a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.c +++ b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.c @@ -17,6 +17,18 @@ #define FSL_COMPONENT_ID "platform.drivers.flash_k4" #endif +#if defined(__IAR_SYSTEMS_ICC__) +#define __RAMFUNC __ramfunc +#elif defined(__GNUC__) +#define __RAMFUNC __attribute__((section(".ramfunc"))) __attribute__((__noinline__)) +#endif + +#if defined(FLASH_DRIVER_IS_FLASH_RESIDENT) && (FLASH_DRIVER_IS_FLASH_RESIDENT == 1) +#define FCT_PLACEMENT __RAMFUNC +#else +#define FCT_PLACEMENT +#endif + #if defined(FLASH_DRIVER_IS_FLASH_RESIDENT) && FLASH_DRIVER_IS_FLASH_RESIDENT /*! * @brief Constants for execute-in-RAM flash function. @@ -204,6 +216,11 @@ status_t FLASH_Erase(flash_config_t *config, FMU_Type *base, uint32_t start, uin start += FLASH_FEATURE_SECTOR_SIZE; } } + /* + * Data cache may contain stale values following a flash programming or erasing operation. + * Data cache invalidation is only on KW43. + */ + flash_cache_invalidate(); } else { @@ -234,6 +251,11 @@ status_t FLASH_EraseAll(FMU_Type *base, uint32_t key) if (kStatus_FLASH_Success == status) { status = FLASH_CMD_EraseAll(base); + /* + * Data cache may contain stale values following a flash programming or erasing operation. + * Data cache invalidation is only on KW43. + */ + flash_cache_invalidate(); } else { @@ -315,6 +337,11 @@ status_t FLASH_Program(flash_config_t *config, FMU_Type *base, uint32_t start, u status = FLASH_CMD_ProgramPhrase(base, start, extraData); } + /* + * Data cache may contain stale values following a flash programming or erasing operation. + * Data cache invalidation is only on KW43. + */ + flash_cache_invalidate(); } else { @@ -400,6 +427,11 @@ status_t FLASH_ProgramPage(flash_config_t *config, FMU_Type *base, uint32_t star status = FLASH_CMD_ProgramPage(base, start, extraData); } + /* + * Data cache may contain stale values following a flash programming or erasing operation. + * Data cache invalidation is only on KW43. + */ + flash_cache_invalidate(); } else { @@ -766,6 +798,7 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro *value = config->msf1Config[0].flashDesc.blockBase; break; case kFLASH_PropertyPflash0SectorSize: + case kFLASH_PropertyPflash1SectorSize: *value = FLASH_FEATURE_SECTOR_SIZE; break; case kFLASH_PropertyPflash1TotalSize: @@ -789,15 +822,7 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro } #if defined(SMSCM) -#if defined(FLASH_DRIVER_IS_FLASH_RESIDENT) && (FLASH_DRIVER_IS_FLASH_RESIDENT == 1) -#if defined(__IAR_SYSTEMS_ICC__) -__ramfunc -#elif defined(__GNUC__) -__attribute__ ((section (".ramfunc"))) -#endif -#endif - void - flash_cache_disable(void) +FCT_PLACEMENT void flash_cache_disable(void) { SMSCM->OCMDR0 = (SMSCM->OCMDR0 & (~SMSCM_FLASH_CACHE_CTRL_MASK)) | SMSCM_FLASH_CACHE_CTRL(0x1); SMSCM->OCMDR0 = (SMSCM->OCMDR0 & (~SMSCM_FLASH_CACHE_CTRL_MASK)) | SMSCM_FLASH_CACHE_CTRL(0x8); @@ -807,15 +832,7 @@ __attribute__ ((section (".ramfunc"))) } -#if defined(FLASH_DRIVER_IS_FLASH_RESIDENT) && (FLASH_DRIVER_IS_FLASH_RESIDENT == 1) -#if defined(__IAR_SYSTEMS_ICC__) -__ramfunc -#elif defined(__GNUC__) -__attribute__ ((section (".ramfunc"))) -#endif -#endif - void - flash_cache_speculation_control(bool isPreProcess, FMU_Type *base) +FCT_PLACEMENT void flash_cache_speculation_control(bool isPreProcess, FMU_Type *base) { if (base == FLASH) { @@ -855,6 +872,73 @@ __attribute__ ((section (".ramfunc"))) __DSB(); } +void flash_cache_invalidate(void) +{ +} + +#else + +#if defined SYSCON_FMC0_CTRL_DFC_MASK + +FCT_PLACEMENT void flash_cache_invalidate(void) +{ + SYSCON->AUTHENTICATE = 0xaaaaaaaa; + __ISB(); + __DSB(); + SYSCON->FMC0_CTRL |= SYSCON_FMC0_CTRL_ECFC_MASK; /* Execute clear cache */ + __ISB(); + __DSB(); + SYSCON->FMC0_CTRL |= (SYSCON_FMC0_CTRL_DFDC_MASK|SYSCON_FMC0_CTRL_DFS_MASK|SYSCON_FMC0_CTRL_DDP_MASK); /* Disable Data Cache - Disable Data Prefetch - Disable Flash Speculation */ + __ISB(); + __DSB(); + SYSCON->FMC0_CTRL &= ~(SYSCON_FMC0_CTRL_DFDC_MASK|SYSCON_FMC0_CTRL_ECFC_MASK|SYSCON_FMC0_CTRL_DFS_MASK|SYSCON_FMC0_CTRL_DDP_MASK); /* re-enable all the disabled bits */ + __ISB(); + __DSB(); +} + +FCT_PLACEMENT void flash_cache_disable(void) +{ + SYSCON->AUTHENTICATE = 0xaaaaaaaa; + SYSCON->FMC0_CTRL |= (SYSCON_FMC0_CTRL_DFDC_MASK | SYSCON_FMC0_CTRL_DFC_MASK | SYSCON_FMC0_CTRL_DFIC_MASK); + SYSCON->FMC0_CTRL |= SYSCON_FMC0_CTRL_ECFC_MASK; + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +} +FCT_PLACEMENT void flash_cache_enable(void) +{ + SYSCON->AUTHENTICATE = 0xaaaaaaaa; + SYSCON->FMC0_CTRL &= ~(SYSCON_FMC0_CTRL_DFDC_MASK | SYSCON_FMC0_CTRL_DFC_MASK | SYSCON_FMC0_CTRL_DFIC_MASK); + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +} + +#endif + +#if defined SYSCON_FMC0_CTRL_DFS_MASK + +FCT_PLACEMENT void flash_cache_speculation_control(bool isPreProcess, FMU_Type *base) +{ + (void)base; + SYSCON->AUTHENTICATE = 0xaaaaaaaa; + + if (isPreProcess == false) + { + SYSCON->FMC0_CTRL |= SYSCON_FMC0_CTRL_DFS_MASK; + } + else + { + SYSCON->FMC0_CTRL &= ~SYSCON_FMC0_CTRL_DFS_MASK; + } + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +} +#endif #endif static status_t flash_check_param( diff --git a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.h b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.h index 98b5b23ef..eb5601c0f 100644 --- a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.h +++ b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.h @@ -24,7 +24,7 @@ * @{ */ /*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1. */ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) /*!< Version 2.3.3. */ /*! @brief Flash driver version for ROM*/ enum _flash_driver_version_constants @@ -32,7 +32,7 @@ enum _flash_driver_version_constants kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ kFLASH_DriverVersionMinor = 3, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ + kFLASH_DriverVersionBugfix = 3 /*!< Bugfix for flash driver version.*/ }; /*! @@ -261,9 +261,13 @@ status_t Read_IFR_Into_MISR( /*! @} */ -#if defined(SMSCM) +#if defined(SMSCM) || defined (SYSCON_FMC0_CTRL_DFC_MASK) void flash_cache_disable(void); +void flash_cache_enable(void); +void flash_cache_invalidate(void); +#endif +#if defined(SMSCM) || defined (SYSCON_FMC0_CTRL_DFS_MASK) void flash_cache_speculation_control(bool isPreProcess, FMU_Type *base); #endif diff --git a/mcux/mcux-sdk-ng/drivers/flexcan/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/flexcan/CMakeLists.txt index 8bbc8d0ec..ac2f4fdcd 100644 --- a/mcux/mcux-sdk-ng/drivers/flexcan/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/flexcan/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.flexcan_edma) - mcux_component_version(2.12.0) + mcux_component_version(2.12.1) mcux_add_source(SOURCES fsl_flexcan_edma.h fsl_flexcan_edma.c) @@ -12,7 +12,7 @@ if(CONFIG_MCUX_COMPONENT_driver.flexcan_edma) endif() if(CONFIG_MCUX_COMPONENT_driver.flexcan) - mcux_component_version(2.14.3) + mcux_component_version(2.14.4) mcux_add_source(SOURCES fsl_flexcan.h fsl_flexcan.c) diff --git a/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan.c b/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan.c index c958fced9..40f9ac1fd 100644 --- a/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan.c +++ b/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan.c @@ -1145,8 +1145,8 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sour /* Selects the byte order for the payload of transmit and receive frames. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION) && FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION) - ctrl2Temp = (pConfig->payloadEndianness) ? ctrl2Temp | CAN_CTRL2_PES_MASK : - ctrl2Temp & ~CAN_CTRL2_PES_MASK; + ctrl2Temp = (pConfig->payloadEndianness == kFLEXCAN_littleEndian) ? ctrl2Temp | CAN_CTRL2_PES_MASK : + ctrl2Temp & ~CAN_CTRL2_PES_MASK; #endif #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK) && FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK) @@ -3543,8 +3543,8 @@ status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame * message which is being read. */ (void)memcpy((void *)pRxFrame, (void *)(uint32_t *)E_RX_FIFO(base), sizeof(uint32_t) * idHitOff); #if (defined(FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP) && FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP) - /* If idHitOff is 20 or DLC is 15, no need to get idhit and hrtimestamp individually. */ - if (idHitOff < 20U) + /* If idHitOff is 16 or DLC is 14, need to get idhit and hrtimestamp individually. */ + if (idHitOff <= 16U) { pRxFrame->idhit = pRxFrame->dataWord[idHitOff - 4U]; pRxFrame->hrtimestamp = pRxFrame->dataWord[idHitOff - 3U]; @@ -3555,8 +3555,8 @@ status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame } } #else - /* If idHitOff is 19 or DLC is 15, no need to get idhit individually. */ - if (idHitOff < 19U) + /* If idHitOff is 15 or DLC is 14, need to get idhit individually. */ + if (idHitOff <= 15U) { pRxFrame->idhit = pRxFrame->dataWord[idHitOff - 3U]; /* Clear the unused frame data. */ @@ -4964,8 +4964,8 @@ static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, { if (intflag[i] != 0U) { - bitStart = (i == startIdx) ? (startMbIdx % 32) : 0; - bitEnd = (i == endIdx) ? (endMbIdx % 32) : 31; + bitStart = (i == startIdx) ? (startMbIdx % 32U) : 0U; + bitEnd = (i == endIdx) ? (endMbIdx % 32U) : 31U; for (uint32_t j = bitStart; j <= bitEnd; j++) { if (0UL != (intflag[i] & ((uint32_t)1UL << j))) @@ -5391,6 +5391,7 @@ void FLEXCAN_MemoryErrorHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) #endif #endif +void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t startMbIdx, uint32_t endMbIdx); void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t startMbIdx, uint32_t endMbIdx) { assert(NULL != s_flexcanHandle[instance]); @@ -5408,6 +5409,7 @@ void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t startMbIdx, uint32 SDK_ISR_EXIT_BARRIER; } +void FLEXCAN_DriverEventIRQHandler(uint32_t instance); void FLEXCAN_DriverEventIRQHandler(uint32_t instance) { assert(NULL != s_flexcanHandle[instance]); @@ -5431,6 +5433,7 @@ void FLEXCAN_DriverEventIRQHandler(uint32_t instance) SDK_ISR_EXIT_BARRIER; } +void FLEXCAN_DriverIRQHandler(uint32_t instance); void FLEXCAN_DriverIRQHandler(uint32_t instance) { assert(NULL != s_flexcanHandle[instance]); diff --git a/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan.h b/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan.h index 12efa0ea4..258fc6267 100644 --- a/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan.h +++ b/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan.h @@ -21,7 +21,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief FlexCAN driver version. */ -#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 14, 3)) +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 14, 4)) /*! @} */ #if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT) diff --git a/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan_edma.c b/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan_edma.c index 041b89a11..b1fdfc7f7 100644 --- a/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan_edma.c +++ b/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan_edma.c @@ -82,8 +82,8 @@ static void FLEXCAN_ReceiveFifoEDMACallback(edma_handle_t *handle, void *param, { /* Enhanced Rx FIFO ID HIT offset is changed dynamically according to data length code (DLC) . */ idHitIndex = (DLC_LENGTH_DECODE(framefd->length) + 3U) / 4U; - /* If idHitIndex is 16 or DLC is 15, no need to get idhit or hrtimestamp individually. */ - if (idHitIndex < 16U) + /* If idHitIndex is 12 or DLC is 14, need to get idhit or hrtimestamp individually. */ + if (idHitIndex <= 12U) { framefd->idhit = framefd->dataWord[idHitIndex]; #if (defined(FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP) && FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP) diff --git a/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan_edma.h b/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan_edma.h index d0800cd22..d07b30116 100644 --- a/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan_edma.h +++ b/mcux/mcux-sdk-ng/drivers/flexcan/fsl_flexcan_edma.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief FlexCAN EDMA driver version. */ -#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 12, 0)) +#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 12, 1)) /*! @} */ /* Forward declaration of the handle typedef. */ diff --git a/mcux/mcux-sdk-ng/drivers/flexcomm/spi/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/flexcomm/spi/CMakeLists.txt index faf6d7cdc..e4a5a76b4 100644 --- a/mcux/mcux-sdk-ng/drivers/flexcomm/spi/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/flexcomm/spi/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.flexcomm_spi_dma) - mcux_component_version(2.2.1) + mcux_component_version(2.2.2) mcux_add_source(SOURCES fsl_spi_dma.c fsl_spi_dma.h) diff --git a/mcux/mcux-sdk-ng/drivers/flexcomm/spi/fsl_spi_dma.c b/mcux/mcux-sdk-ng/drivers/flexcomm/spi/fsl_spi_dma.c index 9b67c98ab..e1e6bae93 100644 --- a/mcux/mcux-sdk-ng/drivers/flexcomm/spi/fsl_spi_dma.c +++ b/mcux/mcux-sdk-ng/drivers/flexcomm/spi/fsl_spi_dma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -17,13 +17,6 @@ #define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" #endif -/*configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; - *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; + *fifowr |= (xfer->configFlags & ((uint32_t)kSPI_FrameDelay | (uint32_t)kSPI_FrameAssert)); } -static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) +static void SpiConfigToFifoWR(const spi_config_t *config, uint32_t *fifowr) { *fifowr |= ((uint32_t)SPI_DEASSERT_ALL & (~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)config->sselNum))); /* set width of data - range asserted at entry */ *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); } -static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) +static void PrepareTxLastWord(spi_dma_handle_t *handle, spi_transfer_t *xfer, const spi_config_t *config) { - if (config->dataWidth > kSPI_Data8Bits) + uint32_t txLastWord; + + if (NULL != xfer->txData) { - *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); + if (config->dataWidth > kSPI_Data8Bits) + { + txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); + } + else + { + txLastWord = xfer->txData[xfer->dataSize - 1U]; + } } else { - *txLastWord = xfer->txData[xfer->dataSize - 1U]; + txLastWord = s_dummyData[handle->instance]; + txLastWord |= (txLastWord << 8U); } - XferToFifoWR(xfer, txLastWord); - SpiConfigToFifoWR(config, txLastWord); -} -static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) -{ - uint32_t instance = SPI_GetInstance(base); - uint32_t dummydata = (uint32_t)s_dummyData[instance]; - dummydata |= (uint32_t)s_dummyData[instance] << 8U; - - dummy->word = dummydata; - dummy->lastWord = dummydata; - - XferToFifoWR(xfer, &dummy->word); - XferToFifoWR(xfer, &dummy->lastWord); - SpiConfigToFifoWR(spi_config_p, &dummy->word); - SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); - /* Clear the end of transfer bit for continue word transfer. */ - dummy->word &= (~(uint32_t)kSPI_FrameAssert); + XferToFifoWR(xfer, &txLastWord); + SpiConfigToFifoWR(config, &txLastWord); + + handle->lastword = txLastWord; } /*! @@ -178,27 +131,195 @@ status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, (void)memset(handle, 0, sizeof(*handle)); /* Set spi base to handle */ + handle->base = base; handle->txHandle = txHandle; handle->rxHandle = rxHandle; handle->callback = callback; handle->userData = userData; handle->instance = instance; - handle->dataBytesEveryTime = DMA_MAX_TRANSFER_COUNT; /* Set SPI state to idle */ handle->state = (uint8_t)kSPI_Idle; - /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - /* Install callback for Tx dma channel */ - DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); - DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); + DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, handle); + DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, handle); return kStatus_Success; } +/*! + * @brief Setup the context for RX + * + * This function should be called once before starting the RX DMA transfer. + * + * @param handle SPI handle pointer. + * @param xfer SPI transfer structure. + */ +static void SPI_TransferSetupRxContextDMA(spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + handle->rxNextData = xfer->rxData; + handle->rxRemainingBytes = xfer->dataSize; +} + +/*! + * @brief Submit the next RX chunk. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + */ +static void SPI_TransferSubmitNextRxDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + size_t nextRxSize; + dma_transfer_config_t dmaXferConfig; + dma_transfer_type_t dmaXferType; + uint8_t *nextRxData; + + uint8_t *address = (uint8_t *)(uintptr_t)&base->FIFORD; + + nextRxSize = MIN(DMA_MAX_TRANSFER_COUNT, handle->rxRemainingBytes); + + if (handle->rxNextData != NULL) + { + dmaXferType = kDMA_PeripheralToMemory; + nextRxData = handle->rxNextData; + handle->rxNextData += nextRxSize; + } + else + { + dmaXferType = kDMA_StaticToStatic; + nextRxData = (uint8_t*)&s_rxDummy; + } + + DMA_PrepareTransfer(&dmaXferConfig, address, nextRxData, handle->bytesPerFrame, nextRxSize, dmaXferType, NULL); + (void)DMA_SubmitTransfer(handle->rxHandle, &dmaXferConfig); + + handle->rxRemainingBytes -= nextRxSize; +} + +/*! + * @brief Prepare for TX + * + * This function should be called once before starting the TX DMA transfer. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param xfer SPI transfer structure. + * @param spi_config_p SPI configuration structure. + */ +static void SPI_TransferSetupTxContextDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer, const spi_config_t *spi_config_p) +{ + uint8_t *address; + + handle->txNextData = xfer->txData; + handle->txRemainingBytes = xfer->dataSize; + + /* + * If SSEL need be deasserted at last, then the EOT of the last data frame will + * be different from previous data frame. Use a seperate DMA descriptor for it. + */ + if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) + { + handle->lastwordBytes = handle->bytesPerFrame; + handle->txRemainingBytes -= handle->bytesPerFrame; + } + else + { + handle->lastwordBytes = 0U; + } + + /* + * Set up the DMA descriptor for the last data frame. + */ + if (0u != handle->lastwordBytes) + { + /* Create chained descriptor to transmit last word */ + dma_xfercfg_t tmp_xfercfg; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = 4U; + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1U; + tmp_xfercfg.reload = false; + tmp_xfercfg.clrtrig = false; + tmp_xfercfg.intB = false; + + address = (uint8_t*)(uintptr_t)(&base->FIFOWR); + + DMA_CreateDescriptor(&s_spi_descriptor_table[handle->instance], &tmp_xfercfg, &handle->lastword, address, NULL); + } + + /* Create 16-bit dummy data, used for 16-bit data width. */ + if (handle->txNextData == NULL) + { + handle->txDummy = s_dummyData[handle->instance]; + handle->txDummy |= (handle->txDummy << 8); + } + + /* Setup the control info. + * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. + * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR + * will push the data and the current control bits into the FIFO. + * Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. + */ + uint32_t writeAddress = ((uintptr_t) & (base->FIFOWR)) + 2UL; + *(volatile uint16_t *)writeAddress = (uint16_t)((handle->lastword & (~(uint32_t)kSPI_FrameAssert)) >> 16u); +} + +/*! + * @brief Submit the next TX chunk. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + */ +static status_t SPI_TransferSubmitNextTxDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + uint8_t * address; + void *nextDesc; + bool txIntFlag; + dma_transfer_config_t xferConfig; + dma_transfer_type_t dmaXferType; + const uint8_t *txNextData; + + size_t nextTxSize = MIN(DMA_MAX_TRANSFER_COUNT, handle->txRemainingBytes); + handle->txRemainingBytes -= nextTxSize; + + /* + * If this is the last part, check whether the last word is needed. + * if yes, connect the DMA descriptor. + */ + if ((0u == handle->txRemainingBytes) && (0u != handle->lastwordBytes)) + { + txIntFlag = false; + nextDesc = &s_spi_descriptor_table[handle->instance]; + } + else + { + txIntFlag = true; + nextDesc = NULL; + } + + if (handle->txNextData != NULL) + { + dmaXferType = kDMA_MemoryToPeripheral; + txNextData = handle->txNextData; + handle->txNextData += nextTxSize; + } + else + { + dmaXferType = kDMA_StaticToStatic; + txNextData = (uint8_t*)&handle->txDummy; + } + + address = (uint8_t*)(uintptr_t)&base->FIFOWR; + DMA_PrepareTransfer(&xferConfig, (uint8_t *)(uintptr_t)txNextData, address, handle->bytesPerFrame, nextTxSize, dmaXferType, nextDesc); + + xferConfig.xfercfg.intA = txIntFlag; + return DMA_SubmitTransfer(handle->txHandle, &xferConfig); +} + /*! * brief Perform a non-blocking SPI transfer using DMA. * @@ -216,214 +337,64 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra { assert(!((NULL == handle) || (NULL == xfer))); - uint32_t instance; - status_t result = kStatus_Success; - uint32_t address; - void *nextDesc = NULL; - uint32_t firstTimeSize = 0; - uint32_t rxDataSize = xfer->dataSize; - dma_transfer_config_t xferConfig = {0}; - spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(base); - bool txIntFlag = true; - uint8_t bytesPerFrame = - (uint8_t)((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))); - handle->bytesPerFrame = bytesPerFrame; - uint8_t lastwordBytes = 0U; - bool sselDeasert = false; - - if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) - { - handle->lastwordBytes = bytesPerFrame; - lastwordBytes = bytesPerFrame; - sselDeasert = true; - } - else - { - handle->lastwordBytes = 0U; - lastwordBytes = 0U; - } + status_t result = kStatus_Success; + spi_config_t *spi_config_p; if ((NULL == handle) || (NULL == xfer)) { return kStatus_InvalidArgument; } - /* Byte size is zero. */ - if (xfer->dataSize == 0U) + if (xfer->dataSize < handle->bytesPerFrame) { return kStatus_InvalidArgument; } - /* Get instance from base address */ - instance = SPI_GetInstance(base); - /* Check if the device is busy */ if (handle->state == (uint8_t)kSPI_Busy) { return kStatus_SPI_Busy; } - else - { - /* Set the dma unit by dataSize */ - if (xfer->dataSize <= bytesPerFrame) - { - firstTimeSize = xfer->dataSize; - } - else if (xfer->dataSize - lastwordBytes <= handle->dataBytesEveryTime) - { - firstTimeSize = xfer->dataSize - lastwordBytes; - if (lastwordBytes != 0U) - { - nextDesc = &s_spi_descriptor_table[instance]; - txIntFlag = false; - } - else - { - } - } - else - { - firstTimeSize = handle->dataBytesEveryTime; - rxDataSize = handle->dataBytesEveryTime; - } - /* Clear FIFOs before transfer. */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* Clear FIFOs before transfer. */ + base->FIFOCFG |= (SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK); + base->FIFOSTAT |= (SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK); - handle->state = (uint8_t)kSPI_Busy; - handle->transferSize = xfer->dataSize; + handle->state = (uint8_t)kSPI_Busy; + spi_config_p = (spi_config_t *)SPI_GetConfig(base); + handle->bytesPerFrame = + (uint8_t)((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))); - /* receive */ - SPI_EnableRxDMA(base, true); - address = (uint32_t)&base->FIFORD; - if (xfer->rxData != NULL) - { - handle->rxEndData = xfer->rxData + xfer->dataSize; - handle->rxNextData = xfer->rxData + rxDataSize; - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->rxData, bytesPerFrame, rxDataSize, kDMA_PeripheralToMemory, - NULL); - } - else - { - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, &s_rxDummy, bytesPerFrame, xfer->dataSize, kDMA_StaticToStatic, - NULL); - } - (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - DMA_StartTransfer(handle->rxHandle); - - /* transmit */ - SPI_EnableTxDMA(base, true); - address = (uint32_t)&base->FIFOWR; - if (xfer->txData != NULL) - { - handle->txEndData = xfer->txData + xfer->dataSize; - handle->txNextData = xfer->txData + firstTimeSize; - - /* If end of tranfer function is enabled and data transfer frame is bigger than bytesPerFrame, use dma - * descriptor to send the last data. - */ - if ((sselDeasert == true) && (xfer->dataSize > bytesPerFrame)) - { - PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); - - /* Create chained descriptor to transmit last word */ - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = 4U; - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1U; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], (uint32_t *)address, - NULL); - } - - DMA_PrepareTransfer(&xferConfig, (void *)xfer->txData, (uint32_t *)address, bytesPerFrame, firstTimeSize, - kDMA_MemoryToPeripheral, nextDesc); - xferConfig.xfercfg.intA = txIntFlag; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - /* Setup tx dummy data. */ - SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); - if ((sselDeasert == true) && (xfer->dataSize > bytesPerFrame)) - { - /* Create chained descriptor to transmit last word */ - dma_xfercfg_t tmp_xfercfg; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = (uint8_t)sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - tmp_xfercfg.reload = false; - tmp_xfercfg.clrtrig = false; - tmp_xfercfg.intB = false; - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (uint32_t *)address, NULL); - - /* Use common API to setup first descriptor */ - DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (uint32_t *)address, bytesPerFrame, - (xfer->dataSize - bytesPerFrame), kDMA_StaticToStatic, - &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (uint32_t *)address, bytesPerFrame, xfer->dataSize, - kDMA_StaticToStatic, NULL); - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - } + /* receive */ + SPI_TransferSetupRxContextDMA(handle, xfer); + SPI_EnableRxDMA(base, true); + SPI_TransferSubmitNextRxDMA(base, handle); + handle->rxInProgress = true; + DMA_StartTransfer(handle->rxHandle); - handle->txInProgress = true; - uint32_t tmpData = 0U; - uint32_t writeAddress = (uint32_t) & (base->FIFOWR) + 2UL; - XferToFifoWR(xfer, &tmpData); - SpiConfigToFifoWR(spi_config_p, &tmpData); - - /* Setup the control info. - * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. - * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR - * will push the data and the current control bits into the FIFO. - */ - if ((sselDeasert == true) && (xfer->dataSize == bytesPerFrame)) - { - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } - else - { - /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ - tmpData &= (~(uint32_t)kSPI_FrameAssert); - *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); - } + /* transmit */ + PrepareTxLastWord(handle, xfer, spi_config_p); + + if (xfer->dataSize == handle->bytesPerFrame) + { + /* Only one time send, write the TX register directly. */ + base->FIFOWR = handle->lastword; + handle->txInProgress = false; + return kStatus_Success; + } + + SPI_TransferSetupTxContextDMA(base, handle, xfer, spi_config_p); + SPI_EnableTxDMA(base, true); - DMA_StartTransfer(handle->txHandle); + result = SPI_TransferSubmitNextTxDMA(base, handle); + if (result != kStatus_Success) + { + return result; } + handle->txInProgress = true; + DMA_StartTransfer(handle->txHandle); + return result; } @@ -493,125 +464,99 @@ status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handl return status; } -static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +/*! + * @brief Handle the RX DMA IRQ. + */ +static void SPI_TransferRxHandlerDMA(SPI_Type *base, spi_dma_handle_t *spiHandle) { - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - uint8_t bytesPerFrame = spiHandle->bytesPerFrame; - uint32_t nextDataSize = 0; - uint32_t address = (uint32_t)&base->FIFORD; - - spiHandle->rxInProgress = false; - - if (spiHandle->rxNextData >= spiHandle->rxEndData) + if (spiHandle->rxRemainingBytes <= 0u) { - /* All finished, call the callback */ - if (spiHandle->txInProgress == false) - { - SPI_EnableTxDMA(base, false); - SPI_EnableRxDMA(base, false); - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } + spiHandle->rxInProgress = false; } else { - /* Need transmit by DMA again */ - if (spiHandle->rxEndData <= (spiHandle->dataBytesEveryTime + spiHandle->rxNextData)) - { - nextDataSize = (uint32_t)((uint32_t)spiHandle->rxEndData - (uint32_t)spiHandle->rxNextData); - } - else - { - nextDataSize = spiHandle->dataBytesEveryTime; - } - - dma_transfer_config_t xferConfig; - DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, spiHandle->rxNextData, bytesPerFrame, nextDataSize, - kDMA_PeripheralToMemory, NULL); - spiHandle->rxNextData = (uint8_t *)(spiHandle->rxNextData + nextDataSize); - (void)DMA_SubmitTransfer(spiHandle->rxHandle, &xferConfig); - - if (spiHandle->txInProgress == false) - { - spiHandle->rxInProgress = true; - DMA_StartTransfer(spiHandle->rxHandle); - - spiHandle->txInProgress = true; - DMA_StartTransfer(spiHandle->txHandle); - } + SPI_TransferSubmitNextRxDMA(base, spiHandle); + DMA_StartTransfer(spiHandle->rxHandle); } } -static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +/*! + * @brief Handle the TX DMA IRQ. + */ +static void SPI_TransferTxHandlerDMA(SPI_Type *base, spi_dma_handle_t *spiHandle) { - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - uint32_t instance = spiHandle->instance; - bool txIntFlag = true; - uint8_t bytesPerFrame = spiHandle->bytesPerFrame; - void *nextDesc = NULL; - uint32_t nextDataSize = 0U; - uint8_t lastwordBytes = spiHandle->lastwordBytes; - uint32_t writeAddress = (uint32_t)&base->FIFOWR; - - spiHandle->txInProgress = false; - - if (spiHandle->txNextData + lastwordBytes >= spiHandle->txEndData) + if (spiHandle->txRemainingBytes <= 0u) { spiHandle->txInProgress = false; - - if (spiHandle->rxInProgress == false) - { - SPI_EnableTxDMA(base, false); - SPI_EnableRxDMA(base, false); - spiHandle->state = (uint8_t)kSPI_Idle; - if (spiHandle->callback != NULL) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } } else { - if (((uint32_t)spiHandle->txEndData) <= - (spiHandle->dataBytesEveryTime + lastwordBytes + (uint32_t)spiHandle->txNextData)) - { - if (lastwordBytes != 0U) - { - nextDesc = &s_spi_descriptor_table[instance]; - txIntFlag = false; - } - else - { - } - nextDataSize = (uint32_t)((uint32_t)spiHandle->txEndData - (uint32_t)spiHandle->txNextData - lastwordBytes); - } - else + (void)SPI_TransferSubmitNextTxDMA(base, spiHandle); + DMA_StartTransfer(spiHandle->txHandle); + } +} + +/*! + * @brief Check if the transfer is done, if so, disable DMA and call the callback function. + */ +static void SPI_TransferCheckTransferDoneDMA(SPI_Type *base, spi_dma_handle_t *spiHandle) +{ + if ((spiHandle->rxInProgress == false) && (spiHandle->txInProgress == false)) + { + SPI_EnableTxDMA(base, false); + SPI_EnableRxDMA(base, false); + spiHandle->state = (uint8_t)kSPI_Idle; + if (spiHandle->callback != NULL) { - nextDataSize = spiHandle->dataBytesEveryTime; + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); } + } +} + +/*! + * @brief RX DMA callback. + */ +static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_handle_t *spiHandle = (spi_dma_handle_t *)userData; + SPI_Type *base = spiHandle->base; + + SPI_TransferRxHandlerDMA(base, spiHandle); + + /* + * The TX is handled differently for master and slave. + * + * According to the SPI protocol, the data flow between master and slave is as follows: + * 1. Before master sending the data frame, slave should fill (prepare) a data frame (or dummy) to SPI TX register. + * 2. Master writes data frame to SPI TX register. + * 3. Master written data frame is sent to the SPI bus with clock by SPI IP. + * 4. Based on SPI clock, slave will receive the data frame, and save it to SPI RX register. + * At the same time, the data frame in SPI slave TX register will be sent to SPI bus, and received by master. + * 5. Master saves the received data frame to SPI RX register. + * + * From the above, if master TX is setup before master RX DMA ready, then master RX will overflow. + * So, for master, the driver doesn't submit the TX DMA until RX DMA is ready. + */ + if (!spiHandle->isSlave) + { + SPI_TransferTxHandlerDMA(base, spiHandle); + } - dma_transfer_config_t xferConfig; - DMA_PrepareTransfer(&xferConfig, (void *)spiHandle->txNextData, (uint32_t *)writeAddress, bytesPerFrame, nextDataSize, - kDMA_MemoryToPeripheral, nextDesc); - spiHandle->txNextData = (spiHandle->txNextData + nextDataSize); - xferConfig.xfercfg.intA = txIntFlag; - (void)DMA_SubmitTransfer(spiHandle->txHandle, &xferConfig); + SPI_TransferCheckTransferDoneDMA(base, spiHandle); +} - if (spiHandle->rxInProgress == false) - { - spiHandle->rxInProgress = true; - DMA_StartTransfer(spiHandle->rxHandle); +/*! + * @brief TX DMA callback. + */ +static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_handle_t *spiHandle = (spi_dma_handle_t *)userData; + SPI_Type *base = spiHandle->base; - spiHandle->txInProgress = true; - DMA_StartTransfer(spiHandle->txHandle); - } + if (spiHandle->isSlave) + { + SPI_TransferTxHandlerDMA(base, spiHandle); + SPI_TransferCheckTransferDoneDMA(base, spiHandle); } } @@ -637,9 +582,9 @@ void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) } /*! - * brief Gets the master DMA transfer remaining bytes. + * brief Gets the master DMA transfered bytes. * - * This function gets the master DMA transfer remaining bytes. + * This function gets the master DMA transfered bytes. * * param base SPI peripheral base address. * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. @@ -666,7 +611,7 @@ status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); - *count = handle->transferSize - bytes; + *count = handle->transferSize - handle->rxRemainingBytes - bytes; return kStatus_Success; } diff --git a/mcux/mcux-sdk-ng/drivers/flexcomm/spi/fsl_spi_dma.h b/mcux/mcux-sdk-ng/drivers/flexcomm/spi/fsl_spi_dma.h index 5559c707e..c2c702b3e 100644 --- a/mcux/mcux-sdk-ng/drivers/flexcomm/spi/fsl_spi_dma.h +++ b/mcux/mcux-sdk-ng/drivers/flexcomm/spi/fsl_spi_dma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,8 +24,8 @@ /*! @name Driver version */ /*! @{ */ -/*! @brief SPI DMA driver version 2.1.1. */ -#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*! @brief SPI DMA driver version. */ +#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*! @} */ typedef struct _spi_dma_handle spi_dma_handle_t; @@ -36,10 +36,13 @@ typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, sta /*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ struct _spi_dma_handle { + SPI_Type *base; /*!< SPI base address */ volatile bool txInProgress; /*!< Send transfer finished */ volatile bool rxInProgress; /*!< Receive transfer finished */ uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI transfer */ uint8_t lastwordBytes; /*!< The Bytes of lastword for master*/ + uint16_t txDummy; /*!< The dummy data for TX. */ + uint32_t lastword; /*!< The last word for master TX. */ dma_handle_t *txHandle; /*!< DMA handler for SPI send */ dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ @@ -48,10 +51,10 @@ struct _spi_dma_handle size_t transferSize; /*!< Bytes need to be transfer */ uint32_t instance; /*!< Index of SPI instance*/ const uint8_t *txNextData; /*!< The pointer of next time tx data*/ - const uint8_t *txEndData; /*!< The pointer of end of data*/ + size_t txRemainingBytes; /*!< lastwordBytes + txRemainingBytes is number of data to be send [in bytes] */ uint8_t *rxNextData; /*!< The pointer of next time rx data*/ - uint8_t *rxEndData; /*!< The pointer of end of rx data*/ - uint32_t dataBytesEveryTime; /*!< Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT */ + size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ + bool isSlave; /*!< SPI work in slave mode. */ }; /******************************************************************************* @@ -137,7 +140,9 @@ static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, dma_handle_t *txHandle, dma_handle_t *rxHandle) { - return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); + status_t status = SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); + handle->isSlave = true; + return status; } /*! @@ -167,9 +172,9 @@ static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *ha void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); /*! - * @brief Gets the master DMA transfer remaining bytes. + * @brief Gets the master DMA transfered bytes. * - * This function gets the master DMA transfer remaining bytes. + * This function gets the master DMA transfered bytes. * * @param base SPI peripheral base address. * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. @@ -190,9 +195,9 @@ static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *h } /*! - * @brief Gets the slave DMA transfer remaining bytes. + * @brief Gets the slave DMA transfered bytes. * - * This function gets the slave DMA transfer remaining bytes. + * This function gets the slave DMA transfered bytes. * * @param base SPI peripheral base address. * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. diff --git a/mcux/mcux-sdk-ng/drivers/flexio/i2c/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/flexio/i2c/CMakeLists.txt index 02455085b..43118329e 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/i2c/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/flexio/i2c/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.flexio_i2c_master) - mcux_component_version(2.6.1) + mcux_component_version(2.6.2) mcux_add_source(SOURCES fsl_flexio_i2c_master.c fsl_flexio_i2c_master.h) diff --git a/mcux/mcux-sdk-ng/drivers/flexio/i2c/fsl_flexio_i2c_master.c b/mcux/mcux-sdk-ng/drivers/flexio/i2c/fsl_flexio_i2c_master.c index c7d687ba6..9ad1fc9f8 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/i2c/fsl_flexio_i2c_master.c +++ b/mcux/mcux-sdk-ng/drivers/flexio/i2c/fsl_flexio_i2c_master.c @@ -253,6 +253,9 @@ static bool FLEXIO_I2C_MasterTransferStateMachineSendCommand(FLEXIO_I2C_Type *ba flexio_i2c_master_handle_t *handle, uint32_t statusFlags) { +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) { if (handle->transfer.subaddressSize > 0U) @@ -302,6 +305,7 @@ static bool FLEXIO_I2C_MasterTransferStateMachineSendCommand(FLEXIO_I2C_Type *ba FLEXIO_I2C_MasterStop(base); #if I2C_RETRY_TIMES + waitTimes = I2C_RETRY_TIMES; while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && (0U != --waitTimes)) { @@ -354,6 +358,7 @@ static bool FLEXIO_I2C_MasterTransferStateMachineSendData(FLEXIO_I2C_Type *base, FLEXIO_I2C_MasterStop(base); #if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && (0U != --waitTimes)) { @@ -387,6 +392,7 @@ static bool FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(FLEXIO_I2C_Typ { FLEXIO_I2C_MasterEnableAck(base, false); #if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && (0U != --waitTimes)) { @@ -446,6 +452,7 @@ static status_t FLEXIO_I2C_MasterTransferStateMachineReceiveData(FLEXIO_I2C_Type { FLEXIO_I2C_MasterEnableAck(base, false); #if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && (0U != --waitTimes)) { @@ -482,9 +489,6 @@ static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, uint32_t statusFlags) { status_t status; -#if I2C_RETRY_TIMES - uint32_t waitTimes = I2C_RETRY_TIMES; -#endif if ((statusFlags & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U) { @@ -1220,10 +1224,19 @@ status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_mas } while ((tmpHandle.state != (uint8_t)kFLEXIO_I2C_Idle) && (result == kStatus_Success)); +#if I2C_RETRY_TIMES + waitTimes = I2C_RETRY_TIMES; +#endif /* Timer disable on timer compare, wait until bit clock TSF set, which means timer disable and stop has been sent. */ while (0U == (FLEXIO_GetTimerStatusFlags(base->flexioBase) & (1UL << base->timerIndex[1]))) { +#if I2C_RETRY_TIMES + if (--waitTimes == 0U) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#endif } return result; diff --git a/mcux/mcux-sdk-ng/drivers/flexio/i2c/fsl_flexio_i2c_master.h b/mcux/mcux-sdk-ng/drivers/flexio/i2c/fsl_flexio_i2c_master.h index fa9dadf3d..1fb810f42 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/i2c/fsl_flexio_i2c_master.h +++ b/mcux/mcux-sdk-ng/drivers/flexio/i2c/fsl_flexio_i2c_master.h @@ -22,13 +22,17 @@ /*! @name Driver version */ /*! @{ */ -#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 6, 1)) +#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 6, 2)) /*! @} */ /*! @brief Retry times for waiting flag. */ #ifndef I2C_RETRY_TIMES +#ifdef CONFIG_I2C_RETRY_TIMES +#define I2C_RETRY_TIMES CONFIG_I2C_RETRY_TIMES +#else #define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ #endif +#endif /*! @brief FlexIO I2C transfer status*/ enum diff --git a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/CMakeLists.txt index 44f36d917..be03a3234 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/CMakeLists.txt @@ -21,7 +21,7 @@ if(CONFIG_MCUX_COMPONENT_driver.flexio_mculcd_edma) endif() if(CONFIG_MCUX_COMPONENT_driver.flexio_mculcd_smartdma) - mcux_component_version(2.0.5) + mcux_component_version(2.0.6) mcux_add_source(SOURCES fsl_flexio_mculcd_smartdma.c fsl_flexio_mculcd_smartdma.h) diff --git a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd.c b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd.c index 17e9199cd..7fabe86dd 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd.c +++ b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd.c @@ -511,6 +511,7 @@ void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) */ void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) { + assert(base->txShifterEndIndex > base->txShifterStartIndex); /* * This function will be called at the beginning of every data writing. For * performance consideration, it access the FlexIO registers directly, but not @@ -627,6 +628,8 @@ void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) */ void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base) { + assert(base->rxShifterEndIndex > base->rxShifterStartIndex); + /* * This function will be called at the beginning of every data reading. For * performance consideration, it access the FlexIO registers directly, but not diff --git a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.c b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.c index 942375557..dbe5ad782 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.c +++ b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.c @@ -203,6 +203,8 @@ static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle) { + assert(handle->remainingCount / handle->minorLoopBytes != 0U); + edma_transfer_config_t xferConfig = {0}; edma_transfer_size_t transferSize = kEDMA_TransferSize1Bytes; int16_t offset; @@ -326,6 +328,8 @@ status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base, edma_handle_t *rxDmaHandle) { assert(NULL != handle); + assert(base->txShifterEndIndex > base->txShifterStartIndex); + assert(base->rxShifterEndIndex > base->rxShifterStartIndex); /* Zero the handle. */ (void)memset(handle, 0, sizeof(*handle)); diff --git a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.c b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.c index 737e89c91..ef7217f8e 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.c +++ b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.c @@ -17,11 +17,12 @@ #endif #define FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER 0U -#if defined(MCXA276_SERIES) || defined(MCXA275_SERIES) || defined(MCXA176_SERIES) || defined(MCXA175_SERIES)|| \ - defined(MCXA166_SERIES) || defined(MCXA165_SERIES) -#define FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER 3U +#if defined(MCXA175_SERIES) || defined(MCXA176_SERIES) || defined(MCXA185_SERIES) || defined(MCXA186_SERIES) || \ + defined(MCXA255_SERIES) || defined(MCXA256_SERIES) || defined(MCXA265_SERIES) || defined(MCXA266_SERIES) || \ + defined(MCXA365_SERIES) || defined(MCXA366_SERIES) +#define FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER 3U #else -#define FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER 7U +#define FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER 7U #endif #define FLEXIO_MCULCD_SMARTDMA_TX_SHIFTER_NUM \ (FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER - FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER + 1) @@ -111,8 +112,9 @@ static void FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen( static void FLEXIO_MCULCD_RGB656ToRGB888(const uint16_t *rgb565, uint32_t pixelCount, uint8_t *rgb888) { - while ((pixelCount--) != 0U) + while (pixelCount != 0U) { + pixelCount--; *rgb888 = (uint8_t)(((*rgb565) & 0x001FU) << 3U); rgb888++; *rgb888 = (uint8_t)(((*rgb565) & 0x07E0U) >> 3U); @@ -171,8 +173,9 @@ status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base, { handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA; } -#if !(defined(MCXA276_SERIES) || defined(MCXA275_SERIES) || defined(MCXA176_SERIES) || defined(MCXA175_SERIES)|| \ - defined(MCXA166_SERIES) || defined(MCXA165_SERIES)) +#if !(defined(MCXA175_SERIES) || defined(MCXA176_SERIES) || defined(MCXA185_SERIES) || defined(MCXA186_SERIES) || \ + defined(MCXA255_SERIES) || defined(MCXA256_SERIES) || defined(MCXA265_SERIES) || defined(MCXA266_SERIES) || \ + defined(MCXA365_SERIES) || defined(MCXA366_SERIES)) else if (((config->inputPixelFormat == kFLEXIO_MCULCD_RGB565) && (config->outputPixelFormat == kFLEXIO_MCULCD_RGB888)) || ((config->inputPixelFormat == kFLEXIO_MCULCD_BGR565) && diff --git a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.h b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.h index 88a2a068a..225b49868 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.h +++ b/mcux/mcux-sdk-ng/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.h @@ -22,7 +22,7 @@ /*@{*/ /*! @brief FlexIO MCULCD SMARTDMA driver version. */ -#define FSL_FLEXIO_MCULCD_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +#define FSL_FLEXIO_MCULCD_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 6)) /*@}*/ /*! @brief SMARTDMA transfer size should be multiple of 64 bytes. */ diff --git a/mcux/mcux-sdk-ng/drivers/flexio/spi/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/flexio/spi/CMakeLists.txt index f0df7456a..f457d55c1 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/spi/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/flexio/spi/CMakeLists.txt @@ -21,7 +21,7 @@ if(CONFIG_MCUX_COMPONENT_driver.flexio_spi_edma) endif() if(CONFIG_MCUX_COMPONENT_driver.flexio_spi) - mcux_component_version(2.4.2) + mcux_component_version(2.4.3) mcux_add_source(SOURCES fsl_flexio_spi.c fsl_flexio_spi.h) diff --git a/mcux/mcux-sdk-ng/drivers/flexio/spi/fsl_flexio_spi.h b/mcux/mcux-sdk-ng/drivers/flexio/spi/fsl_flexio_spi.h index 8c52a76b8..d86000dcb 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/spi/fsl_flexio_spi.h +++ b/mcux/mcux-sdk-ng/drivers/flexio/spi/fsl_flexio_spi.h @@ -24,7 +24,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief FlexIO SPI driver version. */ -#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) /*! @} */ #ifndef FLEXIO_SPI_DUMMYDATA @@ -34,8 +34,12 @@ /*! @brief Retry times for waiting flag. */ #ifndef SPI_RETRY_TIMES +#ifdef CONFIG_SPI_RETRY_TIMES +#define SPI_RETRY_TIMES CONFIG_SPI_RETRY_TIMES +#else #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ #endif +#endif /*! @brief Get the transfer data format of width and bit order. */ #define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U)) diff --git a/mcux/mcux-sdk-ng/drivers/flexio/uart/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/flexio/uart/CMakeLists.txt index a9b65e8d4..d5592749d 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/uart/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/flexio/uart/CMakeLists.txt @@ -21,7 +21,7 @@ if(CONFIG_MCUX_COMPONENT_driver.flexio_uart_edma) endif() if(CONFIG_MCUX_COMPONENT_driver.flexio_uart) - mcux_component_version(2.6.2) + mcux_component_version(2.6.4) mcux_add_source(SOURCES fsl_flexio_uart.c fsl_flexio_uart.h) diff --git a/mcux/mcux-sdk-ng/drivers/flexio/uart/fsl_flexio_uart.c b/mcux/mcux-sdk-ng/drivers/flexio/uart/fsl_flexio_uart.c index 6244749d3..f00009726 100644 --- a/mcux/mcux-sdk-ng/drivers/flexio/uart/fsl_flexio_uart.c +++ b/mcux/mcux-sdk-ng/drivers/flexio/uart/fsl_flexio_uart.c @@ -129,6 +129,7 @@ static status_t FLEXIO_UART_CalculateBaudRate(uint32_t baudRate_Bps, uint32_t sr for (i=0; iAHBCR; configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK | +#if (defined(FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT) && FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT) + FLEXSPI_AHBCR_RESUMEDISABLE_MASK | +#endif FLEXSPI_AHBCR_CACHABLEEN_MASK); configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) | FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) | FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) | +#if (defined(FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT) && FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT) + FLEXSPI_AHBCR_RESUMEDISABLE(config->ahbConfig.disableAhbReadResume) | +#endif FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable); base->AHBCR = configValue; @@ -457,6 +463,15 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) config->ahbConfig.enableAHBPrefetch = false; config->ahbConfig.enableAHBBufferable = false; config->ahbConfig.enableAHBCachable = false; +#if (defined(FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT) && FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT) +#if FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 + /* ERR052733: When IPED is enabled, the RESUME should be disabled. Flexspi does not support RESUME when IPED is enabled. + Workaround: Software should configure this AHBCR_RESUMEDISABLE bit to 1'b1 which uses the IPED enable.*/ + config->ahbConfig.disableAhbReadResume = true; +#else + config->ahbConfig.disableAhbReadResume = false; +#endif /* FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 */ +#endif /* FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT */ } /*! @@ -667,6 +682,44 @@ void FLEXSPI_SetAddressMapping(FLEXSPI_Type *base, const flexspi_addr_map_config } #endif +/*! + * brief Update all AHB buffers' settings, including buffer size, master ID. + * + * param base FLEXSPI peripheral base address. + * param ptrAhbBufferCtrl Pointer to structure flexspi_ahbBuffers_ctrl_t which store all AHB buffers' settings. + */ +void FLEXSPI_UpdateAhbBuffersSettings(FLEXSPI_Type *base, flexspi_ahbBuffers_ctrl_t *ptrAhbBufferCtrl) +{ + assert(ptrAhbBufferCtrl != NULL); + + uint32_t configValue = 0UL; + uint32_t totalAhbBufferSize = 0UL; + + /* Wait for bus to be idle before changing flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + for (uint32_t i = 0; i < (uint32_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) + { + totalAhbBufferSize += (ptrAhbBufferCtrl->buffer[i].bufferSize); + /* Check if input configuration not overallocate AHB RX buffer. */ + assert(totalAhbBufferSize <= (uint32_t)FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(base)); + + configValue = base->AHBRXBUFCR0[i]; + + configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK | + FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK); + configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(ptrAhbBufferCtrl->buffer[i].enablePrefetch) | + FLEXSPI_AHBRXBUFCR0_PRIORITY(ptrAhbBufferCtrl->buffer[i].priority) | + FLEXSPI_AHBRXBUFCR0_MSTRID(ptrAhbBufferCtrl->buffer[i].masterIndex) | + FLEXSPI_AHBRXBUFCR0_BUFSZ((uint32_t)ptrAhbBufferCtrl->buffer[i].bufferSize / 8U); + base->AHBRXBUFCR0[i] = configValue; + } + + (void)totalAhbBufferSize; +} + /*! brief Updates the LUT table. * * param base FLEXSPI peripheral base address. @@ -1247,18 +1300,6 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; } - if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag)) - { - base->INTR = (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag; - - FLEXSPI_TransferAbort(base, handle); - - if (NULL != handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_Success, handle->userData); - } - } - /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */ if ((0U != (status & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) && (handle->state == (uint32_t)kFLEXSPI_BusyWrite)) @@ -1313,6 +1354,73 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) { /* Empty else */ } + + if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag)) + { + base->INTR = (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag; + if (handle->dataSize > 0UL) /* In case of some data not read/write. */ + { + if (handle->state == kFLEXSPI_BusyRead) + { + /* Read word aligned data from rx fifo. */ + for (i = 0U; i < (handle->dataSize / 4U); i++) + { + *(uint32_t *)(void *)handle->data = base->RFDR[i]; + handle->data += 4U; + } + + /* Adjust size by the amount processed. */ + handle->dataSize -= (size_t)4U * i; + + /* Read word un-aligned data from rx fifo. */ + if (0x00U != handle->dataSize) + { + uint32_t tempVal = base->RFDR[i]; + + for (i = 0U; i < handle->dataSize; i++) + { + *handle->data++ = ((uint8_t)(tempVal >> (8U * i)) & 0xFFU); + } + } + + } + else if (handle->state == kFLEXSPI_BusyWrite) + { + /* Write word aligned data into tx fifo. */ + for (i = 0U; i < (handle->dataSize / 4U); i++) + { + base->TFDR[i] = *(uint32_t *)(void *)handle->data; + handle->data += 4U; + } + + /* Adjust size by the amount processed. */ + handle->dataSize -= (size_t)4U * i; + + /* Write word un-aligned data into tx fifo. */ + if (0x00U != handle->dataSize) + { + uint32_t tempVal = 0x00U; + + for (uint32_t j = 0U; j < handle->dataSize; j++) + { + tempVal |= ((uint32_t)*handle->data++ << (8U * j)); + } + + base->TFDR[i] = tempVal; + } + } + handle->dataSize = 0; + } + + /* Until now, all data should be read/write. */ + /* Abort transfer, reset state as Idle. */ + FLEXSPI_TransferAbort(base, handle); + + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_Success, handle->userData); + } + } } } else diff --git a/mcux/mcux-sdk-ng/drivers/flexspi/fsl_flexspi.h b/mcux/mcux-sdk-ng/drivers/flexspi/fsl_flexspi.h index 1c1468f25..698bb2ea0 100644 --- a/mcux/mcux-sdk-ng/drivers/flexspi/fsl_flexspi.h +++ b/mcux/mcux-sdk-ng/drivers/flexspi/fsl_flexspi.h @@ -25,7 +25,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief FLEXSPI driver version. */ -#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) +#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 8, 0)) /*! @} */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) @@ -224,6 +224,14 @@ typedef struct _flexspi_ahbBuffer_config prefetch disable/enable separately for each master. */ } flexspi_ahbBuffer_config_t; +/*! + * @brief Structure to control all AHB buffers. + */ +typedef struct _flexspi_ahbBuffers_ctrl +{ + flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< Configurations of all AHB buffers. */ +} flexspi_ahbBuffers_ctrl_t; + /*! @brief FLEXSPI configuration structure. */ typedef struct _flexspi_config { @@ -268,6 +276,10 @@ typedef struct _flexspi_config timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */ uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */ +#if (defined(FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT) && FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT) + bool disableAhbReadResume; /*!< \b True: Suspended AHB read prefetch does not resume once aborted; + \b False: Suspended AHB read prefetch resumes when AHB is IDLE. */ +#endif flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */ bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer when FLEXSPI returns STOP mode ACK. */ @@ -490,6 +502,14 @@ static inline void FLEXSPI_EnableRemap(FLEXSPI_Type *base, bool enable) } #endif +/*! + * @brief Update all AHB buffers' settings, including buffer size, master ID. + * + * @param base FLEXSPI peripheral base address. + * @param ptrAhbBufferCtrl Pointer to structure @ref flexspi_ahbBuffers_ctrl_t which store all AHB buffers' settings. + */ +void FLEXSPI_UpdateAhbBuffersSettings(FLEXSPI_Type *base, flexspi_ahbBuffers_ctrl_t *ptrAhbBufferCtrl); + /*! @} */ /*! diff --git a/mcux/mcux-sdk-ng/drivers/flexspi_flr/fsl_flexspi_flr.c b/mcux/mcux-sdk-ng/drivers/flexspi_flr/fsl_flexspi_flr.c index 64a52bc2e..4919ccb96 100644 --- a/mcux/mcux-sdk-ng/drivers/flexspi_flr/fsl_flexspi_flr.c +++ b/mcux/mcux-sdk-ng/drivers/flexspi_flr/fsl_flexspi_flr.c @@ -36,15 +36,12 @@ static const IRQn_Type s_flexspiSlvIrqs[] = {FLEXSPI_SLV_IRQn}; static const clock_ip_name_t s_flexspiSlvClock[] = FLEXSPI_SLV_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if defined(FSL_DRIVER_FOLLOWER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_FOLLOWER_DOUBLE_WEAK_IRQ /*! @brief Pointers to Flexspi Follower handles for each instance. */ static flexspi_slv_handle_t *s_flexspiSlvHandle[ARRAY_SIZE(s_flexspiSlvBases)]; -#endif -#if defined(FSL_DRIVER_FOLLOWER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_FOLLOWER_DOUBLE_WEAK_IRQ /*! @brief Pointer to Flexspi Follower IRQ handler. */ static flexspi_slv_isr_t s_flexspiSlvIsr; -#endif + /******************************************************************************* * Code ******************************************************************************/ @@ -52,6 +49,7 @@ static flexspi_slv_isr_t s_flexspiSlvIsr; #if defined(__ICCARM__) #pragma optimize = none #endif /* defined(__ICCARM__) */ + static void FLEXSPI_SLV_Memset(void *src, uint8_t value, size_t length) { assert(src != NULL); @@ -87,59 +85,6 @@ uint32_t FLEXSPI_SLV_GetInstance(FLEXSPI_SLV_Type *base) return instance; } -/*! - * brief Returns the interrupt status and clear the interrupt flag. - * - * param base FLEXSPI FOLLOWER peripheral base address. - */ -uint32_t FLEXSPI_SLV_CheckAndClearInterrupt(FLEXSPI_SLV_Type *base) -{ - uint32_t status = FLEXSPI_SLV_GetInterruptStatusFlags(base); - uint32_t intEnableStatus = FLEXSPI_SLV_GetEnabledInterrupts(base); - - /* Check for interrupt. */ - status &= intEnableStatus; - if (0U != status) - { - /* Clear the flags. */ - FLEXSPI_SLV_ClearInterruptStatusFlags(base, status); - - /* Select the correct interrupt flag. */ - if (0U != (status & (uint32_t)FLEXSPI_SLV_MODULE_INT_WOF_MASK)) - { - status = kFLEXSPI_SLV_WriteOverflowFlag; - } - else if (0U != (status & (uint32_t)FLEXSPI_SLV_MODULE_INT_RUF_MASK)) - { - status = kFLEXSPI_SLV_ReadUnderflowFlag; - } - else if (0U != (status & (uint32_t)FLEXSPI_SLV_MODULE_INT_ERRCMD_MASK)) - { - status = kFLEXSPI_SLV_ErrorCommandFlag; - } - else - { - status = kFLEXSPI_SLV_InvalidInterruptFlag; - } - } - else if (FLEXSPI_SLV_GetEnabledMailInterrupt(base)) - { - status = FLEXSPI_SLV_GetMailInterruptIndex(base); - if (status >= FLEXSPI_SLV_SPIMAIL_COUNT) - { - status = kFLEXSPI_SLV_InvalidInterruptFlag; - } - /* Clear the flag. */ - FLEXSPI_SLV_ClearMailInterruptFlag(base); - } - else - { - status = kFLEXSPI_SLV_InvalidInterruptFlag; - } - - return status; -} - /*! * brief Initializes the FLEXSPI FOLLOWER module and internal state. * @@ -158,32 +103,36 @@ void FLEXSPI_SLV_Init(FLEXSPI_SLV_Type *base, const flexspi_slv_config_t *config #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Reset peripheral before configuring it. */ - FLEXSPI_SLV_SoftwareReset_SetVal(base, 1); - FLEXSPI_SLV_SoftwareReset_SetVal(base, 0); + FLEXSPI_SLV_SoftwareReset(base); /* Set IO mode. */ - FLEXSPI_SLV_IOMode_SetVal(base, config->io_mode); + FLEXSPI_SLV_SetIOMode(base, config->ioMode); /* Set RW base address and range */ - FLEXSPI_SLV_RW_CMD_BaseAddr1_SetVal(base, (config->baseAddr1) >> 16); - FLEXSPI_SLV_RW_CMD_BaseAddr2_SetVal(base, (config->baseAddr2) >> 16); - FLEXSPI_SLV_Update_RWCMD_Base_Range(base); + FLEXSPI_SLV_SetRWCmdBaseAddr(base, (config->baseAddr1 >> 16U), (config->baseAddr2 >> 16U)); + FLEXSPI_SLV_UpdateRWCmdBaseRange(base); - FLEXSPI_SLV_AddrRange_SetVal(base, 0x0, config->addrRange1); - FLEXSPI_SLV_AddrRange_SetVal(base, 0x1, config->addrRange2); - FLEXSPI_SLV_Update_RWCMD_Base_Range(base); + FLEXSPI_SLV_SetAddrRange(base, 0x0, config->addrRange1); + FLEXSPI_SLV_SetAddrRange(base, 0x1, config->addrRange2); + FLEXSPI_SLV_UpdateRWCmdBaseRange(base); /* Set read water mark level */ - FLEXSPI_SLV_Read_WMEN_SetVal(base, 1); - FLEXSPI_SLV_Read_RDWM_SetVal(base, config->rxWatermark); - - FLEXSPI_SLV_Read_FetchSizeSet(base, config->rxFetch_size); + FLEXSPI_SLV_SetReadWatermark(base, config->rxWatermark, true); + FLEXSPI_SLV_SetReadFetchSize(base, config->rxFetchSize); /* Set write water mark level */ - FLEXSPI_SLV_Write_WRWM_SetVal(base, config->txWatermark); - - /* Clear CS mask*/ - FLEXSPI_SLV_CSMASK_SetVal(base, 0); + FLEXSPI_SLV_SetWriteWatermark(base, config->txWatermark); + + /* Clear CS mask. */ + FLEXSPI_SLV_MaskChipSelect(base, 0); + + /* Set the commands. */ + FLEXSPI_SLV_SetReadRegCommand(base, config->readRegCmd, config->readRegDummyCycle); + FLEXSPI_SLV_SetWriteRegCommand(base, config->writeRegCmd); + FLEXSPI_SLV_SetReadMemCommand(base, 0, config->readMemCmd1, config->readMemDummyCycle1); + FLEXSPI_SLV_SetReadMemCommand(base, 1, config->readMemCmd2, config->readMemDummyCycle2); + FLEXSPI_SLV_SetWriteMemCommand(base, 0, config->writeMemCmd1); + FLEXSPI_SLV_SetWriteMemCommand(base, 1, config->writeMemCmd2); } /*! @@ -196,14 +145,14 @@ void FLEXSPI_SLV_GetDefaultConfig(flexspi_slv_config_t *config) /* Initializes the configure structure to zero. */ FLEXSPI_SLV_Memset(config, 0, sizeof(*config)); - config->baseAddr1 = 0; - config->baseAddr2 = 0x1000; - config->addrRange1 = 0; - config->addrRange2 = 0; - config->io_mode = kFLEXSPI_SLV_IOMODE_SDRx4; - config->rxFetch_size = Read_Fetch_256Bytes; - config->rxWatermark = 0; - config->txWatermark = Write_Watermark_128Bytes; + config->baseAddr1 = 0; + config->baseAddr2 = 0x1000; + config->addrRange1 = 0; + config->addrRange2 = 0; + config->ioMode = kFLEXSPI_SLV_IOMODE_SDRx4; + config->rxFetchSize = kFLEXSPI_SLV_Read_Fetch_256Bytes; + config->rxWatermark = 0; + config->txWatermark = kFLEXSPI_SLV_Write_Watermark_128Bytes; } /*! @@ -216,10 +165,7 @@ void FLEXSPI_SLV_GetDefaultConfig(flexspi_slv_config_t *config) void FLEXSPI_SLV_Deinit(FLEXSPI_SLV_Type *base) { /* Reset peripheral. */ - while (FLEXSPI_SLV_GetModuleBusyStatus(base)) - { - } - FLEXSPI_SLV_SoftwareReset_SetVal(base, 1); + FLEXSPI_SLV_SoftwareReset(base); } /*! @@ -232,32 +178,27 @@ void FLEXSPI_SLV_Deinit(FLEXSPI_SLV_Type *base) */ void FLEXSPI_SLV_InterruptCreateHandle(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle, - flexspi_slv_interrupt_callback_t callback, + flexspi_slv_callback_t callback, uint32_t interruptMask) { assert(NULL != handle); uint32_t instance = FLEXSPI_SLV_GetInstance(base); - /* Zero handle. */ (void)memset(handle, 0, sizeof(*handle)); - /* Set callback and userData. */ + /* Set callback. */ handle->callback = callback; -#if defined(FSL_DRIVER_FOLLOWER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_FOLLOWER_DOUBLE_WEAK_IRQ /* Save the context in global variables to support the double weak mechanism. */ s_flexspiSlvHandle[instance] = handle; s_flexspiSlvIsr = FLEXSPI_SLV_HandleIRQ; -#endif /* Enable NVIC interrupt. */ (void)EnableIRQ(s_flexspiSlvIrqs[instance]); FLEXSPI_SLV_EnableInterrupts(base, interruptMask); -#if defined(FSL_DRIVER_FOLLOWER_MAILBOX_IRQ) && FSL_DRIVER_FOLLOWER_MAILBOX_IRQ FLEXSPI_SLV_EnableMailInterrupt(base, true); -#endif } /*! @@ -268,22 +209,36 @@ void FLEXSPI_SLV_InterruptCreateHandle(FLEXSPI_SLV_Type *base, */ void FLEXSPI_SLV_HandleIRQ(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle) { - handle->state = FLEXSPI_SLV_CheckAndClearInterrupt(base); + uint32_t status = FLEXSPI_SLV_GetInterruptStatusFlags(base); + uint32_t intEnableStatus = FLEXSPI_SLV_GetEnabledInterrupts(base); + + status &= intEnableStatus; + if (0U != status) + { + FLEXSPI_SLV_ClearInterruptStatusFlags(base, status); + } + else if (FLEXSPI_SLV_GetEnabledMailInterrupt(base)) + { + status |= (uint32_t)kFLEXSPI_SLV_MailInterruptFlag; + FLEXSPI_SLV_ClearMailInterruptFlag(base); + } + else + { + /* Intentional empty. */ + } + + handle->intrMask = status; /* Check if interrupt is enabled and status is alerted. */ - if ((handle->state != kFLEXSPI_SLV_InvalidInterruptFlag) && (handle->callback != NULL)) + if (handle->callback != NULL) { handle->callback(base, handle); } } -#if defined(FSL_DRIVER_FOLLOWER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_FOLLOWER_DOUBLE_WEAK_IRQ -#if defined(FLEXSPI_SLV) void FLEXSPI_SLV_DriverIRQHandler(void); void FLEXSPI_SLV_DriverIRQHandler(void) { s_flexspiSlvIsr(FLEXSPI_SLV, s_flexspiSlvHandle[0]); SDK_ISR_EXIT_BARRIER; } -#endif -#endif diff --git a/mcux/mcux-sdk-ng/drivers/flexspi_flr/fsl_flexspi_flr.h b/mcux/mcux-sdk-ng/drivers/flexspi_flr/fsl_flexspi_flr.h index b20c23fda..5772b514b 100644 --- a/mcux/mcux-sdk-ng/drivers/flexspi_flr/fsl_flexspi_flr.h +++ b/mcux/mcux-sdk-ng/drivers/flexspi_flr/fsl_flexspi_flr.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __FSL_FLEXSPI_FOLLOWER_H_ -#define __FSL_FLEXSPI_FOLLOWER_H_ +#ifndef FSL_FLEXSPI_FLR_H_ +#define FSL_FLEXSPI_FLR_H_ #include #include "fsl_device_registers.h" @@ -26,13 +26,7 @@ #define FSL_FLEXSPI_SLV_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*@}*/ -#define FSL_FEATURE_FLEXSPI_SLV_AXI_RX_BUFFER_SIZE (2 * 1024) -#define FSL_FEATURE_FLEXSPI_SLV_AXI_TX_BUFFER_SIZE (1024) - -#define FLEXSPI_SLV_MAILBOX_CMD(x) ((x) & 0xFFFFFFFE) -#define FLEXSPI_SLV_MAILBOX_CMD_INT(x) ((x) | 0x1) - -#define FLEXSPI_SLV_CMD_DDR(x) (((x) << 8) | (x)) +#define FLEXSPI_SLV_CMD_DDR(x) (((uint16_t)(x) << 8U) | (uint16_t)(x)) /*! @brief IO mode enumeration of FLEXSPI FOLLOWER.*/ enum @@ -46,67 +40,69 @@ enum /*! @brief The read fetch size enumeration of FLEXSPI FOLLOWER.*/ enum { - Read_Fetch_256Bytes = 0, - Read_Fetch_512Bytes = 1, - Read_Fetch_1KBytes = 2, - Read_Fetch_2KBytes = 3 + kFLEXSPI_SLV_Read_Fetch_256Bytes = 0, + kFLEXSPI_SLV_Read_Fetch_512Bytes = 1, + kFLEXSPI_SLV_Read_Fetch_1KBytes = 2, + kFLEXSPI_SLV_Read_Fetch_2KBytes = 3 }; -/*! @brief Clock frequency enumeration of FLEXSPI FOLLOWER.*/ +/*! @brief The write watermark enumeration of FLEXSPI FOLLOWER.*/ enum { - Write_Watermark_32Bytes = 0, - Write_Watermark_64Bytes = 1, - Write_Watermark_128Bytes = 2, - Write_Watermark_256Bytes = 3 + kFLEXSPI_SLV_Write_Watermark_32Bytes = 0, + kFLEXSPI_SLV_Write_Watermark_64Bytes = 1, + kFLEXSPI_SLV_Write_Watermark_128Bytes = 2, + kFLEXSPI_SLV_Write_Watermark_256Bytes = 3 }; /*! @brief Interrupt status flags of FLEXSPI FOLLOWER.*/ enum { - kFLEXSPI_SLV_Mail0InterruptFlag = 0, /*!< Mailbox0 interrupt */ - kFLEXSPI_SLV_Mail1InterruptFlag = 1, /*!< Mailbox1 interrupt */ - kFLEXSPI_SLV_Mail2InterruptFlag = 2, /*!< Mailbox2 interrupt */ - kFLEXSPI_SLV_Mail3InterruptFlag = 3, /*!< Mailbox3 interrupt */ - kFLEXSPI_SLV_Mail4InterruptFlag = 4, /*!< Mailbox4 interrupt */ - kFLEXSPI_SLV_Mail5InterruptFlag = 5, /*!< Mailbox5 interrupt */ - kFLEXSPI_SLV_Mail6InterruptFlag = 6, /*!< Mailbox6 interrupt */ - kFLEXSPI_SLV_Mail7InterruptFlag = 7, /*!< Mailbox7 interrupt */ - kFLEXSPI_SLV_Mail8InterruptFlag = 8, /*!< Mailbox8 interrupt */ - kFLEXSPI_SLV_WriteOverflowFlag = 9, /*!< An IO RX FIFO overflow occurred during - command/address/write data phase */ - kFLEXSPI_SLV_ReadUnderflowFlag = 10, /*!< IO TX FIFO underflow has occurred - during a read command */ - kFLEXSPI_SLV_ErrorCommandFlag = 11, /*!< An unknown command has been received - from the SPI bus */ - kFLEXSPI_SLV_InvalidInterruptFlag = 12, + kFLEXSPI_SLV_WriteOverflowFlag = FLEXSPI_SLV_MODULE_INTEN_WOFEN_MASK, /*!< An IO RX FIFO overflow occurred during + command/address/write data phase. */ + kFLEXSPI_SLV_ReadUnderflowFlag = FLEXSPI_SLV_MODULE_INTEN_RUFEN_MASK, /*!< IO TX FIFO underflow has occurred + during a read command. */ + kFLEXSPI_SLV_ErrorCommandFlag = FLEXSPI_SLV_MODULE_INTEN_ERRCMDEN_MASK, /*!< An unknown command has been received + from the SPI bus. */ + kFLEXSPI_SLV_MailInterruptFlag = 0x8U, /*!< Mailbox interrupt. */ + kFLEXSPI_SLV_AllInterruptFlags = kFLEXSPI_SLV_WriteOverflowFlag | kFLEXSPI_SLV_ReadUnderflowFlag | + kFLEXSPI_SLV_ErrorCommandFlag | kFLEXSPI_SLV_MailInterruptFlag, /*!< All flags. */ }; /*! @brief FLEXSPI FOLLOWER configuration structure. */ typedef struct _flexspi_slv_config { - uint32_t baseAddr1; /*!< Read/Write CMD1 Base Address. */ - uint32_t baseAddr2; /*!< Read/Write CMD2 Base Address. */ - uint32_t addrRange1; /*!< Read/Write CMD1 Addr Range. */ - uint32_t addrRange2; /*!< Read/Write CMD2 Addr Range. */ - uint8_t io_mode; /*!< IO mode control - SDRx4, SDRx8, DDRx4, DDRx8*/ - uint8_t rxFetch_size; /*!< Specifies the maximum read size triggered by a single read command. */ - uint8_t rxWatermark; /*!< Triggers a new AXI read to fetch more data through the IP AXI header. */ - uint8_t txWatermark; /*!< Specifies the watermark value. During the write command, if pending - write data equals or exceeds the watermark level, it triggers a new AXI write. */ + uint32_t baseAddr1; /*!< Read/Write CMD1 Base Address. */ + uint32_t baseAddr2; /*!< Read/Write CMD2 Base Address. */ + uint32_t addrRange1; /*!< Read/Write CMD1 Addr Range. */ + uint32_t addrRange2; /*!< Read/Write CMD2 Addr Range. */ + uint8_t ioMode; /*!< IO mode control - SDRx4, SDRx8, DDRx4, DDRx8. */ + uint8_t rxFetchSize; /*!< Specifies the maximum read size triggered by a single read command. */ + uint8_t rxWatermark; /*!< Triggers a new AXI read to fetch more data through the IP AXI header. */ + uint8_t txWatermark; /*!< Specifies the watermark value. During the write command, if pending + write data equals or exceeds the watermark level, it triggers a new AXI write. */ + uint16_t readRegCmd; /*!< Read register command. */ + uint16_t readRegDummyCycle; /*!< Read register dymmy cycle. */ + uint16_t writeRegCmd; /*!< Write register command. */ + uint16_t readMemCmd1; /*!< Read memory command1. */ + uint16_t readMemDummyCycle1; /*!< Read memory dymmy cycle1. */ + uint16_t readMemCmd2; /*!< Read memory command2. */ + uint16_t readMemDummyCycle2; /*!< Read memory dymmy cycle2. */ + uint16_t writeMemCmd1; /*!< Write memory command1. */ + uint16_t writeMemCmd2; /*!< Write memory command2. */ } flexspi_slv_config_t; /* Forward declaration of the handle typedef. */ typedef struct _flexspi_slv_handle flexspi_slv_handle_t; /*! @brief FLEXSPI FOLLOWER interrupt callback function. */ -typedef void (*flexspi_slv_interrupt_callback_t)(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle); +typedef void (*flexspi_slv_callback_t)(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle); /*! @brief Interrupt handle structure for FLEXSPI FOLLOWER. */ struct _flexspi_slv_handle { - uint32_t state; /*!< Interrupt state for FLEXSPI FOLLOWER */ - flexspi_slv_interrupt_callback_t callback; /*!< Callback for users while mailbox received or error occurred */ + uint32_t intrMask; /*!< Interrupt state for FLEXSPI FOLLOWER. */ + flexspi_slv_callback_t callback; /*!< Callback for users while mailbox received or error occurred. */ }; /******************************************************************************* @@ -129,14 +125,6 @@ extern "C" { */ uint32_t FLEXSPI_SLV_GetInstance(FLEXSPI_SLV_Type *base); -/*! - * @brief Check and clear interrupt flags. - * - * @param base FLEXSPI FOLLOWER base pointer. - * @return Interrupt flag. - */ -uint32_t FLEXSPI_SLV_CheckAndClearInterrupt(FLEXSPI_SLV_Type *base); - /*! * @brief Initializes the FLEXSPI FOLLOWER module and internal state. * @@ -167,15 +155,21 @@ void FLEXSPI_SLV_Deinit(FLEXSPI_SLV_Type *base); /*! * @brief Software reset for the FLEXSPI FOLLOWER logic. * - * This function sets the software reset flags for the FLEXSPI FOLLOWER. + * This function does software reset for the FLEXSPI FOLLOWER. * * @param base FLEXSPI FOLLOWER peripheral base address. - * @param val 0(Finished) or 1(Initiate) */ -static inline void FLEXSPI_SLV_SoftwareReset_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) +static inline void FLEXSPI_SLV_SoftwareReset(FLEXSPI_SLV_Type *base) { +#if (defined(FSL_FEATURE_NETC_HAS_ERRATA_052145) && FSL_FEATURE_NETC_HAS_ERRATA_052145) + /* Errata 052145: AWhen setting the block operations (Block Read, Block Write, Block Next Read and Block Next Write) + in MODULE_CONTROL register and implementing the software reset, the block behavior will mismatch the bit + definition in the register after the reset. */ + base->MODULE_CONTROL = 0; +#endif + + base->MODULE_CONTROL |= FLEXSPI_SLV_MODULE_CONTROL_SWRESET_MASK; base->MODULE_CONTROL &= ~FLEXSPI_SLV_MODULE_CONTROL_SWRESET_MASK; - base->MODULE_CONTROL |= FLEXSPI_SLV_MODULE_CONTROL_SWRESET(val); } /*! @@ -184,12 +178,12 @@ static inline void FLEXSPI_SLV_SoftwareReset_SetVal(FLEXSPI_SLV_Type *base, uint * This function sets the IO mode flags for the FLEXSPI FOLLOWER. * * @param base FLEXSPI FOLLOWER peripheral base address. - * @param val Set IO Mode for FLEXSPI FOLLOWER + * @param ioMode Set IO Mode for FLEXSPI FOLLOWER */ -static inline void FLEXSPI_SLV_IOMode_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) +static inline void FLEXSPI_SLV_SetIOMode(FLEXSPI_SLV_Type *base, uint32_t ioMode) { - base->MODULE_CONTROL &= ~FLEXSPI_SLV_MODULE_CONTROL_IOMODE_MASK; - base->MODULE_CONTROL |= FLEXSPI_SLV_MODULE_CONTROL_IOMODE(val); + base->MODULE_CONTROL = + (base->MODULE_CONTROL & ~FLEXSPI_SLV_MODULE_CONTROL_IOMODE_MASK) | FLEXSPI_SLV_MODULE_CONTROL_IOMODE(ioMode); } /*! @@ -199,7 +193,7 @@ static inline void FLEXSPI_SLV_IOMode_SetVal(FLEXSPI_SLV_Type *base, uint32_t va * * @param base FLEXSPI FOLLOWER peripheral base address. */ -static inline void FLEXSPI_SLV_Update_RWCMD_Base_Range(FLEXSPI_SLV_Type *base) +static inline void FLEXSPI_SLV_UpdateRWCmdBaseRange(FLEXSPI_SLV_Type *base) { base->MODULE_CONTROL |= FLEXSPI_SLV_MODULE_CONTROL_CMDRANGEBASEUPDATE_MASK; } @@ -210,26 +204,12 @@ static inline void FLEXSPI_SLV_Update_RWCMD_Base_Range(FLEXSPI_SLV_Type *base) * This function sets the RW command base address1 for the FLEXSPI FOLLOWER. * * @param base FLEXSPI FOLLOWER peripheral base address. - * @param val The high 16-bit base address of the RW command - */ -static inline void FLEXSPI_SLV_RW_CMD_BaseAddr1_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) -{ - base->RW_COMMAND_BASE &= ~FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE1_MASK; - base->RW_COMMAND_BASE |= FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE1(val); -} - -/*! - * @brief Set RW command base address2 for the FLEXSPI FOLLOWER module. - * - * This function sets the RW command base address2 for the FLEXSPI FOLLOWER. - * - * @param base FLEXSPI FOLLOWER peripheral base address. - * @param val The high 16-bit base address of the RW command + * @param addr1 The high 16-bit base address of the RW command0. + * @param addr2 The high 16-bit base address of the RW command1. */ -static inline void FLEXSPI_SLV_RW_CMD_BaseAddr2_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) +static inline void FLEXSPI_SLV_SetRWCmdBaseAddr(FLEXSPI_SLV_Type *base, uint32_t addr1, uint32_t addr2) { - base->RW_COMMAND_BASE &= ~FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE2_MASK; - base->RW_COMMAND_BASE |= FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE2(val); + base->RW_COMMAND_BASE = FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE1(addr1) | FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE2(addr2); } /*! @@ -238,26 +218,13 @@ static inline void FLEXSPI_SLV_RW_CMD_BaseAddr2_SetVal(FLEXSPI_SLV_Type *base, u * This function sets the address1/2 range for the FLEXSPI FOLLOWER. * * @param base FLEXSPI FOLLOWER peripheral base address. - * @param i The index of RW command, 0 or 1. + * @param index The index of RW command, 0 or 1. * @param val The size of the memory range in 1KB units. */ -static inline void FLEXSPI_SLV_AddrRange_SetVal(FLEXSPI_SLV_Type *base, uint32_t i, uint32_t val) -{ - base->CMD_RANGE[i] = FLEXSPI_SLV_CMD_RANGE_RANGE(val); -} - -/*! - * @brief Enable or disable read water mark for the FLEXSPI FOLLOWER module. - * - * This function enables or disables read water mark for the FLEXSPI FOLLOWER. - * - * @param base FLEXSPI FOLLOWER peripheral base address. - * @param val 0(Disable) or 1(Enable) - */ -static inline void FLEXSPI_SLV_Read_WMEN_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) +static inline void FLEXSPI_SLV_SetAddrRange(FLEXSPI_SLV_Type *base, uint32_t index, uint32_t val) { - base->READ_COMMAND_CONTROL &= ~FLEXSPI_SLV_READ_COMMAND_CONTROL_WMEN_MASK; - base->READ_COMMAND_CONTROL |= FLEXSPI_SLV_READ_COMMAND_CONTROL_WMEN(val); + assert(index < FLEXSPI_SLV_CMD_RANGE_COUNT); + base->CMD_RANGE[index] = FLEXSPI_SLV_CMD_RANGE_RANGE(val); } /*! @@ -268,10 +235,12 @@ static inline void FLEXSPI_SLV_Read_WMEN_SetVal(FLEXSPI_SLV_Type *base, uint32_t * @param base FLEXSPI FOLLOWER peripheral base address. * @param val Read watermark level in bytes */ -static inline void FLEXSPI_SLV_Read_RDWM_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) +static inline void FLEXSPI_SLV_SetReadWatermark(FLEXSPI_SLV_Type *base, uint32_t rxWatermark, bool enable) { - base->READ_COMMAND_CONTROL &= ~FLEXSPI_SLV_READ_COMMAND_CONTROL_RDWM_MASK; - base->READ_COMMAND_CONTROL |= FLEXSPI_SLV_READ_COMMAND_CONTROL_RDWM(val); + base->READ_COMMAND_CONTROL = + (base->READ_COMMAND_CONTROL & + ~(FLEXSPI_SLV_READ_COMMAND_CONTROL_WMEN_MASK | FLEXSPI_SLV_READ_COMMAND_CONTROL_RDWM_MASK)) | + (enable ? FLEXSPI_SLV_READ_COMMAND_CONTROL_WMEN_MASK : 0U) | FLEXSPI_SLV_READ_COMMAND_CONTROL_RDWM(rxWatermark); } /*! @@ -279,28 +248,13 @@ static inline void FLEXSPI_SLV_Read_RDWM_SetVal(FLEXSPI_SLV_Type *base, uint32_t * * This function sets the maximum read size for the FLEXSPI FOLLOWER. * - * @param base FLEXSPI FOLLOWER peripheral base address. - * @param val The maximum read size - */ -static inline void FLEXSPI_SLV_Read_FetchSizeSet(FLEXSPI_SLV_Type *base, uint32_t val) -{ - base->READ_COMMAND_CONTROL &= ~FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE_MASK; - base->READ_COMMAND_CONTROL |= FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE(val); -} - -/*! - * @brief Gets the maximum read size triggered by a single read command. - * - * This function gets the maximum read size for the FLEXSPI FOLLOWER. - * - * @param base FLEXSPI FOLLOWER peripheral base address. - * @return The maximum read size + * @param base FLEXSPI FOLLOWER peripheral base address. + * @param rxFetchSize The maximum read size triggered by a single read command. */ -static inline uint32_t FLEXSPI_SLV_Read_FetchSizeGet(FLEXSPI_SLV_Type *base) +static inline void FLEXSPI_SLV_SetReadFetchSize(FLEXSPI_SLV_Type *base, uint32_t rxFetchSize) { - uint32_t regBitVal = base->READ_COMMAND_CONTROL & FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE_MASK; - - return (regBitVal >> FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE_SHIFT); + base->READ_COMMAND_CONTROL = (base->WRITE_COMMAND_CONTROL & ~FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE_MASK) | + FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE(rxFetchSize); } /*! @@ -309,12 +263,12 @@ static inline uint32_t FLEXSPI_SLV_Read_FetchSizeGet(FLEXSPI_SLV_Type *base) * This function sets write water mark level for the FLEXSPI FOLLOWER. * * @param base FLEXSPI FOLLOWER peripheral base address. - * @param val Write watermark level + * @param txWatermark Write watermark level */ -static inline void FLEXSPI_SLV_Write_WRWM_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) +static inline void FLEXSPI_SLV_SetWriteWatermark(FLEXSPI_SLV_Type *base, uint32_t txWatermark) { - base->WRITE_COMMAND_CONTROL &= ~FLEXSPI_SLV_WRITE_COMMAND_CONTROL_WRWM_MASK; - base->WRITE_COMMAND_CONTROL |= FLEXSPI_SLV_WRITE_COMMAND_CONTROL_WRWM(val); + base->WRITE_COMMAND_CONTROL = (base->WRITE_COMMAND_CONTROL & ~FLEXSPI_SLV_WRITE_COMMAND_CONTROL_WRWM_MASK) | + FLEXSPI_SLV_WRITE_COMMAND_CONTROL_WRWM(txWatermark); } /*! @@ -322,13 +276,13 @@ static inline void FLEXSPI_SLV_Write_WRWM_SetVal(FLEXSPI_SLV_Type *base, uint32_ * * This function sets CS mask value for the FLEXSPI FOLLOWER. * - * @param base FLEXSPI FOLLOWER peripheral base address. - * @param val 0(Not masked) or 1(Masked) + * @param base FLEXSPI FOLLOWER peripheral base address. + * @param mask 0 - Not masked, 1 - Masked. */ -static inline void FLEXSPI_SLV_CSMASK_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) +static inline void FLEXSPI_SLV_MaskChipSelect(FLEXSPI_SLV_Type *base, uint32_t mask) { - base->MODULE_CONTROL &= ~FLEXSPI_SLV_MODULE_CONTROL_CSMASK_MASK; - base->MODULE_CONTROL |= FLEXSPI_SLV_MODULE_CONTROL_CSMASK(val); + base->MODULE_CONTROL = + (base->MODULE_CONTROL & ~FLEXSPI_SLV_MODULE_CONTROL_CSMASK_MASK) | FLEXSPI_SLV_MODULE_CONTROL_CSMASK(mask); } /* @} */ @@ -365,7 +319,7 @@ static inline void FLEXSPI_SLV_DisableInterrupts(FLEXSPI_SLV_Type *base, uint32_ */ static inline uint32_t FLEXSPI_SLV_GetEnabledInterrupts(FLEXSPI_SLV_Type *base) { - return (base->MODULE_INTEN); + return base->MODULE_INTEN; } /*! @@ -386,7 +340,7 @@ static inline void FLEXSPI_SLV_EnableMailInterrupt(FLEXSPI_SLV_Type *base, bool */ static inline bool FLEXSPI_SLV_GetEnabledMailInterrupt(FLEXSPI_SLV_Type *base) { - return ((base->SPI_MAIL_CTRL & FLEXSPI_SLV_SPI_MAIL_CTRL_SPIINTEN_MASK) ? true : false); + return (0U != (base->SPI_MAIL_CTRL & FLEXSPI_SLV_SPI_MAIL_CTRL_SPIINTEN_MASK)); } /* @} */ @@ -428,26 +382,6 @@ static inline uint32_t FLEXSPI_SLV_GetInterruptStatusFlags(FLEXSPI_SLV_Type *bas return (base->MODULE_INT); } -/*! - * @brief Get the FLEXSPI FOLLOWER mailbox interrupt register. - * - * @param base FLEXSPI FOLLOWER peripheral base address. - * @return Return the index of the FLEXSPI FOLLOWER mail interrupt register - */ -static inline uint32_t FLEXSPI_SLV_GetMailInterruptIndex(FLEXSPI_SLV_Type *base) -{ - uint32_t index; - - for (index = 0; index < FLEXSPI_SLV_SPIMAIL_COUNT; index++) - { - if (base->SPIMAIL[index] & 0x1U) - { - break; - } - } - return index; -} - /*! * @brief Get the FLEXSPI FOLLOWER mailbox data. * @@ -489,7 +423,7 @@ static inline void FLEXSPI_SLV_ClearMailInterruptFlag(FLEXSPI_SLV_Type *base) */ static inline bool FLEXSPI_SLV_GetAXIWriteBusyStatus(FLEXSPI_SLV_Type *base) { - return ((base->MODULE_STATUS & FLEXSPI_SLV_MODULE_STATUS_WIP_MASK) ? true : false); + return (0U != (base->MODULE_STATUS & FLEXSPI_SLV_MODULE_STATUS_WIP_MASK)); } /*! @brief Returns whether the AXI read leader is busy with a read request or else idle with no pending @@ -501,7 +435,7 @@ static inline bool FLEXSPI_SLV_GetAXIWriteBusyStatus(FLEXSPI_SLV_Type *base) */ static inline bool FLEXSPI_SLV_GetAXIReadIdleStatus(FLEXSPI_SLV_Type *base) { - return ((base->MODULE_STATUS & FLEXSPI_SLV_MODULE_STATUS_AXIREADIDLE_MASK) ? true : false); + return (0U != (base->MODULE_STATUS & FLEXSPI_SLV_MODULE_STATUS_AXIREADIDLE_MASK)); } /*! @brief Returns whether the SPI to read/write register queue is idle. @@ -512,7 +446,7 @@ static inline bool FLEXSPI_SLV_GetAXIReadIdleStatus(FLEXSPI_SLV_Type *base) */ static inline bool FLEXSPI_SLV_GetRegReadWriteIdleStatus(FLEXSPI_SLV_Type *base) { - return ((base->MODULE_STATUS & FLEXSPI_SLV_MODULE_STATUS_REGRWIDLE_MASK) ? true : false); + return (0U != (base->MODULE_STATUS & FLEXSPI_SLV_MODULE_STATUS_REGRWIDLE_MASK)); } /*! @brief Returns whether the SEQ control logic is idle or else busy with an ongoing SPI request. @@ -523,7 +457,7 @@ static inline bool FLEXSPI_SLV_GetRegReadWriteIdleStatus(FLEXSPI_SLV_Type *base) */ static inline bool FLEXSPI_SLV_GetSEQIdleStatus(FLEXSPI_SLV_Type *base) { - return ((base->MODULE_STATUS & FLEXSPI_SLV_MODULE_STATUS_SEQIDLE_MASK) ? true : false); + return (0U != (base->MODULE_STATUS & FLEXSPI_SLV_MODULE_STATUS_SEQIDLE_MASK)); } /*! @brief Returns whether the FLEXSPI FOLLOWER module is busy. @@ -554,102 +488,56 @@ static inline bool FLEXSPI_SLV_GetModuleBusyStatus(FLEXSPI_SLV_Type *base) /*! * @brief Sets the read memory command. * - * @param base FLEXSPI FOLLOWER peripheral base address - * @param i The read command setting register index - * @param val The read command value. - */ -static inline void FLEXSPI_SLV_Read_CommandSet(FLEXSPI_SLV_Type *base, uint32_t i, uint32_t val) -{ - base->READ_COMMAND[i] &= ~FLEXSPI_SLV_READ_COMMAND_COMMANDSET_MASK; - base->READ_COMMAND[i] |= FLEXSPI_SLV_READ_COMMAND_COMMANDSET(val); -} - -/*! - * @brief Gets the read memory command. - * - * @param base FLEXSPI FOLLOWER peripheral base address - * @param i The read command setting register index - */ -static inline uint32_t FLEXSPI_SLV_Read_CommandGet(FLEXSPI_SLV_Type *base, uint32_t i) -{ - uint32_t regBitVal = base->READ_COMMAND[i] & FLEXSPI_SLV_READ_COMMAND_COMMANDSET_MASK; - - return (regBitVal >> FLEXSPI_SLV_READ_COMMAND_COMMANDSET_SHIFT); -} - -/*! - * @brief Sets the dummy cycle for the read memory command. - * - * @param base FLEXSPI FOLLOWER peripheral base address - * @param i The read command dummy cycle setting register index - * @param val The dummy cycle value of the read command. - */ -static inline void FLEXSPI_SLV_Read_Command_DummyCyclesSet(FLEXSPI_SLV_Type *base, uint32_t i, uint32_t val) -{ - base->READ_COMMAND[i] &= ~FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES_MASK; - base->READ_COMMAND[i] |= FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES(val); -} - -/*! - * @brief Gets the dummy cycle for the read memory command. - * - * @param base FLEXSPI FOLLOWER peripheral base address - * @param i The read command dummy cycle setting register index + * @param base FLEXSPI FOLLOWER peripheral base address. + * @param index The read command setting register index. + * @param command The read command value. + * @param dummyCycle The dummy cycle value of the read command. */ -static inline uint32_t FLEXSPI_SLV_Read_Command_DummyCyclesGet(FLEXSPI_SLV_Type *base, uint32_t i) +static inline void FLEXSPI_SLV_SetReadMemCommand(FLEXSPI_SLV_Type *base, + uint32_t index, + uint16_t command, + uint16_t dummyCycle) { - uint32_t regBitVal = base->READ_COMMAND[i] & FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES_MASK; - - return (regBitVal >> FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES_SHIFT); + assert(index < FLEXSPI_SLV_READ_COMMAND_COUNT); + base->READ_COMMAND[index] = + FLEXSPI_SLV_READ_COMMAND_COMMANDSET(command) | FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES(dummyCycle); } /*! * @brief Sets the write memory command. * - * @param base FLEXSPI FOLLOWER peripheral base address - * @param i The write command setting register index - * @param val The write command value. + * @param base FLEXSPI FOLLOWER peripheral base address. + * @param index The write command setting register index. + * @param command The write command value. */ -static inline void FLEXSPI_SLV_Write_CommandSet(FLEXSPI_SLV_Type *base, uint32_t i, uint32_t val) +static inline void FLEXSPI_SLV_SetWriteMemCommand(FLEXSPI_SLV_Type *base, uint32_t index, uint32_t command) { - base->WRITE_COMMAND[i] &= ~FLEXSPI_SLV_WRITE_COMMAND_COMMANDSET_MASK; - base->WRITE_COMMAND[i] |= FLEXSPI_SLV_WRITE_COMMAND_COMMANDSET(val); + assert(index < FLEXSPI_SLV_WRITE_COMMAND_COUNT); + base->WRITE_COMMAND[index] = FLEXSPI_SLV_WRITE_COMMAND_COMMANDSET(command); } /*! * @brief Sets the read register command. * * @param base FLEXSPI FOLLOWER peripheral base address - * @param val The read register command value. - */ -static inline void FLEXSPI_SLV_Read_Register_CommandSet(FLEXSPI_SLV_Type *base, uint32_t val) -{ - base->READ_REGISTER_COMMAND0 &= ~FLEXSPI_SLV_READ_REGISTER_COMMAND0_COMMANDSET_MASK; - base->READ_REGISTER_COMMAND0 |= FLEXSPI_SLV_READ_REGISTER_COMMAND0_COMMANDSET(val); -} - -/*! - * @brief Sets the dummy cycle for the read register command. - * - * @param base FLEXSPI FOLLOWER peripheral base address - * @param val The dummy cycle value of the read register command. + * @param command The read command value. + * @param dummyCycle The dummy cycle value of the read command. */ -static inline void FLEXSPI_SLV_Read_Register_Command_DummyCyclesSet(FLEXSPI_SLV_Type *base, uint32_t val) +static inline void FLEXSPI_SLV_SetReadRegCommand(FLEXSPI_SLV_Type *base, uint16_t command, uint16_t dummyCycle) { - base->READ_REGISTER_COMMAND0 &= ~FLEXSPI_SLV_READ_REGISTER_COMMAND0_DUMMYCYCLES_MASK; - base->READ_REGISTER_COMMAND0 |= FLEXSPI_SLV_READ_REGISTER_COMMAND0_DUMMYCYCLES(val); + base->READ_REGISTER_COMMAND0 = FLEXSPI_SLV_READ_REGISTER_COMMAND0_COMMANDSET(command) | + FLEXSPI_SLV_READ_REGISTER_COMMAND0_DUMMYCYCLES(dummyCycle); } /*! * @brief Sets the write register command. * - * @param base FLEXSPI FOLLOWER peripheral base address - * @param val The write register command value. + * @param base FLEXSPI FOLLOWER peripheral base address. + * @param command The write register command value. */ -static inline void FLEXSPI_SLV_Write_Register_CommandSet(FLEXSPI_SLV_Type *base, uint32_t val) +static inline void FLEXSPI_SLV_SetWriteRegCommand(FLEXSPI_SLV_Type *base, uint32_t command) { - base->WRITE_REGISTER_COMMAND0 &= ~FLEXSPI_SLV_WRITE_REGISTER_COMMAND0_COMMANDSET_MASK; - base->WRITE_REGISTER_COMMAND0 |= FLEXSPI_SLV_WRITE_REGISTER_COMMAND0_COMMANDSET(val); + base->WRITE_REGISTER_COMMAND0 = FLEXSPI_SLV_WRITE_REGISTER_COMMAND0_COMMANDSET(command); } /*! @} */ @@ -669,7 +557,7 @@ static inline void FLEXSPI_SLV_Write_Register_CommandSet(FLEXSPI_SLV_Type *base, */ void FLEXSPI_SLV_InterruptCreateHandle(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle, - flexspi_slv_interrupt_callback_t callback, + flexspi_slv_callback_t callback, uint32_t interruptMask); /*! @@ -686,4 +574,4 @@ void FLEXSPI_SLV_HandleIRQ(FLEXSPI_SLV_Type *base, flexspi_slv_handle_t *handle) #endif /*_cplusplus. */ /*@}*/ -#endif /* __FSL_FLEXSPI_FOLLOWER_H_ */ +#endif /* FSL_FLEXSPI_FLR_H_ */ diff --git a/mcux/mcux-sdk-ng/drivers/ftm/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/ftm/CMakeLists.txt index 751a400ef..70013f879 100644 --- a/mcux/mcux-sdk-ng/drivers/ftm/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/ftm/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.ftm) - mcux_component_version(2.7.1) + mcux_component_version(2.7.2) mcux_add_source(SOURCES fsl_ftm.c fsl_ftm.h) diff --git a/mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.c b/mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.c index b79d5ab13..da1cfabdb 100644 --- a/mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.c +++ b/mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.c @@ -1542,3 +1542,71 @@ void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask) /* Clear the channel status flags by writing a 0 to the bit */ base->STATUS &= ~(mask & 0xFFU); } + +#if (defined(FSL_FEATURE_FTM_HAS_ERRATA_010856) && FSL_FEATURE_FTM_HAS_ERRATA_010856) +/*! + * brief Workaround for ERR010856. + * + * This API should be invoked in TOF interrupt handler when a fault is detected to ensure that the outputs + * return to the value configured by SWOCTRL, then FTM should be configured as follows: + * - MODE[FAULTM] configured for manual fault clearing. (MODE[FAULTM] = 0b10) + * - For devices that include the CONF[NUMTOF] field, it must be cleared to 0b00000. + * - SYNC[SYNCHOM] and SYNCONF[SWOC] configured for update OUTMASK and SWOCTRL register at each rising + * edge of system clock. (SYNC[SYNCHOM] = 0, SYNCONF[SWOC] = 0) + * + * param base FTM peripheral base address + * param faultFlag Pointer to variable to indicate that a fault was detected + * param channel Channels controlled by Software output, logical OR of enumeration ::ftm_channel_index_t + * param channelValue Channels value controlled by Software output, logical OR of enumeration ::ftm_channel_index_t + */ +void FTM_ERRATA_010856(FTM_Type *base, uint8_t *faultFlag, uint32_t channel, uint32_t channelValue) +{ + /* + * Step1: Check the value of FMS[FAULTF]. + * - If FMS[FAULTF] = 1 (fault occurred or is occurring), then set a variable to indicate + * that a fault was detected and continue to step 2. + * - If FMS[FAULTF] = 0 but the fault variable is set (fault is not active, but was previously + * detected), continue to step 6. + */ + if ((base->FMS & FTM_FMS_FAULTF_MASK) != 0U) + { + *faultFlag = 1U; + + /* + * Step2: Write OUTMASK register to set bits corresponding to any channels that are + * controlled by SWOCTRL to temporarily inactivate the channel output. + */ + base->OUTMASK |= channel; + + /* Step3: Clear fault conditions by reading FMS register and writing FMS with all zeroes. */ + base->FMS &= 0U; + + /* Step4: Clear the SC[TOF] bit by reading the SC register, then writing a 0 to SC[TOF]. */ + base->SC &= ~FTM_SC_TOF_MASK; + + /* Step5: Exit the interrupt handler. */ + } + else if (((base->FMS & FTM_FMS_FAULTF_MASK) == 0U) && (*faultFlag == 1U)) + { + /* Step6: Clear SWOCTRL by writing all zeroes to it. */ + base->SWOCTRL = 0U; + + /* Step7: Write FTM_SWOCTRL with the desired value again. */ + base->SWOCTRL = (channel | (channelValue << FTM_SWOCTRL_CH0OCV_SHIFT)); + + /* Step8: Clear the FTM_OUTMASK bits that were set in Step2. */ + base->OUTMASK &= ~channel; + + /* Step9: Clear fault variable that was set in Step1 when fault condition was originally detected. */ + *faultFlag = 0U; + + /* Step10: Clear the SC[TOF] bit by reading the SC register, then writing a 0 to SC[TOF]. */ + base->SC &= ~FTM_SC_TOF_MASK; + } + else + { + /* If fault is not active and previously not detected, Clear the SC[TOF] bit. */ + base->SC &= ~FTM_SC_TOF_MASK; + } +} +#endif diff --git a/mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.h b/mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.h index 4ff4200e5..72c660493 100644 --- a/mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.h +++ b/mcux/mcux-sdk-ng/drivers/ftm/fsl_ftm.h @@ -21,7 +21,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief FTM driver version 2.7.1. */ -#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 7, 1)) +#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 7, 2)) /*! @} */ /*! @@ -746,6 +746,25 @@ void FTM_SetupDualEdgeCapture(FTM_Type *base, */ void FTM_SetupFaultInput(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams); +#if (defined(FSL_FEATURE_FTM_HAS_ERRATA_010856) && FSL_FEATURE_FTM_HAS_ERRATA_010856) +/*! + * @brief Workaround for ERR010856. + * + * This API should be invoked in TOF interrupt handler when a fault is detected to ensure that the outputs + * return to the value configured by SWOCTRL, then FTM should be configured as follows: + * - MODE[FAULTM] configured for manual fault clearing. (MODE[FAULTM] = 0b10) + * - For devices that include the CONF[NUMTOF] field, it must be cleared to 0b00000. + * - SYNC[SYNCHOM] and SYNCONF[SWOC] configured for update OUTMASK and SWOCTRL register at each rising + * edge of system clock. (SYNC[SYNCHOM] = 0, SYNCONF[SWOC] = 0) + * + * @param base FTM peripheral base address + * @param faultFlag Pointer to variable to indicate that a fault was detected + * @param channel Channels controlled by Software output, logical OR of enumeration ::ftm_channel_index_t + * @param channelValue Channels value controlled by Software output, logical OR of enumeration ::ftm_channel_index_t + */ +void FTM_ERRATA_010856(FTM_Type *base, uint8_t *faultFlag, uint32_t channel, uint32_t channelValue); +#endif + /*! * @name Interrupt Interface * @{ diff --git a/mcux/mcux-sdk-ng/drivers/gpio/fsl_gpio.h b/mcux/mcux-sdk-ng/drivers/gpio/fsl_gpio.h index 3010db8d5..424c57c8c 100644 --- a/mcux/mcux-sdk-ng/drivers/gpio/fsl_gpio.h +++ b/mcux/mcux-sdk-ng/drivers/gpio/fsl_gpio.h @@ -633,7 +633,7 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut /* * Introduces the FGPIO feature. * - * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT + * The FGPIO registers are aliased to the IOPORT * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. */ diff --git a/mcux/mcux-sdk-ng/drivers/gpt/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/gpt/CMakeLists.txt index ffc29ea83..1ab1b4a35 100644 --- a/mcux/mcux-sdk-ng/drivers/gpt/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/gpt/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.gpt) - mcux_component_version(2.0.5) + mcux_component_version(2.0.6) mcux_add_source(SOURCES fsl_gpt.c fsl_gpt.h) diff --git a/mcux/mcux-sdk-ng/drivers/gpt/fsl_gpt.h b/mcux/mcux-sdk-ng/drivers/gpt/fsl_gpt.h index bd22faecd..03650a8e6 100644 --- a/mcux/mcux-sdk-ng/drivers/gpt/fsl_gpt.h +++ b/mcux/mcux-sdk-ng/drivers/gpt/fsl_gpt.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ -#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 6)) /*! @} */ /*! @@ -250,6 +250,7 @@ static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base) */ static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider) { + assert(divider > 0U); assert(divider - 1U <= GPT_PR_PRESCALER_MASK); base->PR = (base->PR & ~GPT_PR_PRESCALER_MASK) | GPT_PR_PRESCALER(divider - 1U); @@ -274,6 +275,7 @@ static inline uint32_t GPT_GetClockDivider(GPT_Type *base) */ static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider) { + assert(divider > 0U); assert(divider - 1U <= (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT)); base->PR = (base->PR & ~GPT_PR_PRESCALER24M_MASK) | GPT_PR_PRESCALER24M(divider - 1U); diff --git a/mcux/mcux-sdk-ng/drivers/hashcrypt/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/hashcrypt/CMakeLists.txt index 58d5cb8d8..200cc98c5 100644 --- a/mcux/mcux-sdk-ng/drivers/hashcrypt/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/hashcrypt/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.hashcrypt) - mcux_component_version(2.2.16) + mcux_component_version(2.2.17) mcux_add_source(SOURCES fsl_hashcrypt.h fsl_hashcrypt.c) diff --git a/mcux/mcux-sdk-ng/drivers/hashcrypt/fsl_hashcrypt.c b/mcux/mcux-sdk-ng/drivers/hashcrypt/fsl_hashcrypt.c index 3b0d602f9..01c099344 100644 --- a/mcux/mcux-sdk-ng/drivers/hashcrypt/fsl_hashcrypt.c +++ b/mcux/mcux-sdk-ng/drivers/hashcrypt/fsl_hashcrypt.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2024 NXP + * Copyright 2017-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/drivers/hashcrypt/fsl_hashcrypt.h b/mcux/mcux-sdk-ng/drivers/hashcrypt/fsl_hashcrypt.h index cff121ec5..233e9d27e 100644 --- a/mcux/mcux-sdk-ng/drivers/hashcrypt/fsl_hashcrypt.h +++ b/mcux/mcux-sdk-ng/drivers/hashcrypt/fsl_hashcrypt.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2024 NXP + * Copyright 2017-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -96,8 +96,10 @@ enum _hashcrypt_status * - Add wait on DIGEST BIT inside hashcrypt_sha_one_block() to fix issues with some optimization flags * - Version 2.2.16 * - Add DSB instruction inside hashcrypt_sha_ldm_stm_16_words() to fix issues with some optimization flags + * - Version 2.2.17 + * - Fix context size when hashcrypt built with reload feature */ -#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 16)) +#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 17)) /*! @} */ /*! @brief Algorithm definitions correspond with the values for Mode field in Control register !*/ @@ -179,7 +181,7 @@ typedef struct _hashcrypt_handle hashcrypt_handle_t; /*! @brief HASHCRYPT HASH Context size. */ #if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) -#define HASHCRYPT_HASH_CTX_SIZE 30 +#define HASHCRYPT_HASH_CTX_SIZE 31 #else #define HASHCRYPT_HASH_CTX_SIZE 22 #endif diff --git a/mcux/mcux-sdk-ng/drivers/i3c/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/i3c/CMakeLists.txt index 14b003697..f0b8f3126 100644 --- a/mcux/mcux-sdk-ng/drivers/i3c/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/i3c/CMakeLists.txt @@ -21,7 +21,7 @@ if(CONFIG_MCUX_COMPONENT_driver.i3c_edma) endif() if(CONFIG_MCUX_COMPONENT_driver.i3c) - mcux_component_version(2.14.1) + mcux_component_version(2.14.2) mcux_add_source(SOURCES fsl_i3c.h fsl_i3c.c) diff --git a/mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.c b/mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.c index 6e8712ee4..2746424f2 100644 --- a/mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.c +++ b/mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.c @@ -1604,6 +1604,9 @@ status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, uint32_t devCount = 0; uint8_t rxSize = 0; bool mctrlDone = false; +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif i3c_baudrate_hz_t baudRate_Hz; uint32_t errStatus; uint32_t status; @@ -1663,6 +1666,9 @@ status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, { I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); mctrlDone = true; +#if I3C_RETRY_TIMES + waitTimes = I3C_RETRY_TIMES; +#endif } } else if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) && @@ -1693,11 +1699,22 @@ status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, /* Ready to handle next device. */ mctrlDone = false; rxSize = 0; +#if I3C_RETRY_TIMES + waitTimes = I3C_RETRY_TIMES; +#endif } else { /* Intentional empty */ } + +#if I3C_RETRY_TIMES + if (--waitTimes == 0U) + { + result = kStatus_I3C_Timeout; + break; + } +#endif } while ((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag); /* Master stops DAA if slave device number exceeds the prepared address number. */ diff --git a/mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.h b/mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.h index fc3de4ea7..b0e8de873 100644 --- a/mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.h +++ b/mcux/mcux-sdk-ng/drivers/i3c/fsl_i3c.h @@ -20,13 +20,22 @@ /*! @name Driver version */ /*! @{ */ /*! @brief I3C driver version */ -#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 14, 1)) +#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 14, 2)) /*! @} */ -/*! @brief Timeout times for waiting flag. */ +/*! + * @brief Max loops to wait for I3C operation status complete. + * + * This is the maximum number of loops to wait for I3C operation status complete. + * If set to 0, it will wait indefinitely. + */ #ifndef I3C_RETRY_TIMES -#define I3C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#ifdef CONFIG_I3C_RETRY_TIMES +#define I3C_RETRY_TIMES CONFIG_I3C_RETRY_TIMES +#else +#define I3C_RETRY_TIMES 0U #endif +#endif /* I3C_RETRY_TIMES */ #ifndef I3C_MAX_DEVCNT #define I3C_MAX_DEVCNT 10U diff --git a/mcux/mcux-sdk-ng/drivers/imu/fsl_imu.c b/mcux/mcux-sdk-ng/drivers/imu/fsl_imu.c index a4045c0a5..01f4b83ee 100644 --- a/mcux/mcux-sdk-ng/drivers/imu/fsl_imu.c +++ b/mcux/mcux-sdk-ng/drivers/imu/fsl_imu.c @@ -62,10 +62,16 @@ status_t IMU_Init(imu_link_t link) while (!IMU_RX_FIFO_EMPTY(link)) { #if IMU_BUSY_POLL_COUNT - if ((--poll_count) == 0u) + if ((--poll_count) == 0u) /* GCOVR_EXCL_BR_LINE */ { - status = kStatus_Timeout; - break; + /* + * $Branch Coverage Justification$ + * ((--poll_count) == 0u) not covered as it is almost + * impossible to reach the timeout here (newly received messages can be + * processed by IMU_RD_MSG fast enough, sooner than the fifo is full). + */ + status = kStatus_Timeout; /* GCOVR_EXCL_LINE */ + break; /* GCOVR_EXCL_LINE */ } #endif (void)IMU_RD_MSG(link); diff --git a/mcux/mcux-sdk-ng/drivers/irqsteer/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/irqsteer/CMakeLists.txt index 8f35afced..2404d73b0 100644 --- a/mcux/mcux-sdk-ng/drivers/irqsteer/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/irqsteer/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.irqsteer) - mcux_component_version(2.1.4) + mcux_component_version(2.1.5) mcux_add_source(SOURCES fsl_irqsteer.h fsl_irqsteer.c) diff --git a/mcux/mcux-sdk-ng/drivers/irqsteer/fsl_irqsteer.c b/mcux/mcux-sdk-ng/drivers/irqsteer/fsl_irqsteer.c index c745c21bf..9b0efc710 100644 --- a/mcux/mcux-sdk-ng/drivers/irqsteer/fsl_irqsteer.c +++ b/mcux/mcux-sdk-ng/drivers/irqsteer/fsl_irqsteer.c @@ -151,21 +151,18 @@ uint32_t IRQSTEER_GetMasterIrqCount(IRQSTEER_Type *base, irqsteer_int_master_t i * So each master 0 has 32 interrupt sources connected, and for other masters, * every master has 64 interrupt sources connected. */ - if (((uint32_t)FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT % 2U) == 0U) +#if ((FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT % 2U) == 0U) + count = IRQSTEER_INT_MASTER_AGGREGATED_INT_NUM; +#else + if (intMasterIndex == kIRQSTEER_InterruptMaster0) { - count = IRQSTEER_INT_MASTER_AGGREGATED_INT_NUM; + count = IRQSTEER_INT_SRC_REG_WIDTH; } else { - if (intMasterIndex == kIRQSTEER_InterruptMaster0) - { - count = IRQSTEER_INT_SRC_REG_WIDTH; - } - else - { - count = IRQSTEER_INT_MASTER_AGGREGATED_INT_NUM; - } + count = IRQSTEER_INT_MASTER_AGGREGATED_INT_NUM; } +#endif return count; } @@ -175,10 +172,9 @@ static uint32_t IRQSTEER_GetRegIndex(irqsteer_int_master_t intMasterIndex, { uint32_t base = (uint32_t)FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT - 1u - ((uint32_t)intMasterIndex * 2u); - if (0u != ((uint32_t)FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT % 2u)) - { - base += sliceNum - 1; - } +#if (0u != (FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT % 2u)) + base += sliceNum - 1u; +#endif return base - slice; } @@ -259,7 +255,7 @@ uint64_t IRQSTEER_GetMasterInterruptsStatus(IRQSTEER_Type *base, irqsteer_int_ma sliceNum = IRQSTEER_GetMasterIrqCount(base, intMasterIndex) / 32u - 1u; for (i = 0; i <= sliceNum; i++) { - regIndex = IRQSTEER_GetRegIndex(intMasterIndex, i, sliceNum + 1); + regIndex = IRQSTEER_GetRegIndex(intMasterIndex, i, sliceNum + 1u); chanStatus = base->CHn_STATUS[regIndex]; diff --git a/mcux/mcux-sdk-ng/drivers/irqsteer/fsl_irqsteer.h b/mcux/mcux-sdk-ng/drivers/irqsteer/fsl_irqsteer.h index a3340c6db..5c208ae7e 100644 --- a/mcux/mcux-sdk-ng/drivers/irqsteer/fsl_irqsteer.h +++ b/mcux/mcux-sdk-ng/drivers/irqsteer/fsl_irqsteer.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! Driver version. */ -#define FSL_IRQSTEER_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +#define FSL_IRQSTEER_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*! @} */ /*! @@ -146,7 +146,7 @@ void IRQSTEER_Deinit(IRQSTEER_Type *base); */ static inline void IRQSTEER_EnableInterrupt(IRQSTEER_Type *base, IRQn_Type irq) { - assert((uint32_t)irq >= (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX); + assert(((int)irq >= 0) && ((uint32_t)irq >= (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX)); base->CHn_MASK[((uint32_t)IRQSTEER_INT_SRC_REG_INDEX(((uint32_t)irq)))] |= (1UL << ((uint32_t)IRQSTEER_INT_SRC_BIT_OFFSET(((uint32_t)irq)))); @@ -160,7 +160,7 @@ static inline void IRQSTEER_EnableInterrupt(IRQSTEER_Type *base, IRQn_Type irq) */ static inline void IRQSTEER_DisableInterrupt(IRQSTEER_Type *base, IRQn_Type irq) { - assert(((uint32_t)irq) >= ((uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX)); + assert(((int)irq >= 0) && ((uint32_t)irq >= (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX)); base->CHn_MASK[(IRQSTEER_INT_SRC_REG_INDEX(((uint32_t)irq)))] &= ~(1UL << ((uint32_t)IRQSTEER_INT_SRC_BIT_OFFSET(((uint32_t)irq)))); @@ -175,7 +175,7 @@ static inline void IRQSTEER_DisableInterrupt(IRQSTEER_Type *base, IRQn_Type irq) */ static inline bool IRQSTEER_InterruptIsEnabled(IRQSTEER_Type *base, IRQn_Type irq) { - assert((uint32_t)irq >= (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX); + assert(((int)irq >= 0) && ((uint32_t)irq >= (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX)); return (0U != (base->CHn_MASK[((uint32_t)IRQSTEER_INT_SRC_REG_INDEX(((uint32_t)irq)))] & (1UL << ((uint32_t)IRQSTEER_INT_SRC_BIT_OFFSET(((uint32_t)irq)))))); @@ -192,7 +192,7 @@ static inline bool IRQSTEER_InterruptIsEnabled(IRQSTEER_Type *base, IRQn_Type ir */ static inline void IRQSTEER_SetInterrupt(IRQSTEER_Type *base, IRQn_Type irq, bool set) { - assert(((uint32_t)irq) >= ((uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX)); + assert(((int)irq >= 0) && ((uint32_t)irq >= (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX)); if (set) { @@ -262,7 +262,7 @@ static inline void IRQSTEER_DisableMasterInterrupt(IRQSTEER_Type *base, irqsteer */ static inline bool IRQSTEER_IsInterruptSet(IRQSTEER_Type *base, IRQn_Type irq) { - assert(((uint32_t)irq) >= ((uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX)); + assert(((int)irq >= 0) && ((uint32_t)irq >= (uint32_t)FSL_FEATURE_IRQSTEER_IRQ_START_INDEX)); return (0U != ((base->CHn_STATUS[((uint32_t)(IRQSTEER_INT_SRC_REG_INDEX(((uint32_t)irq))))] & (1UL << ((uint32_t)(IRQSTEER_INT_SRC_BIT_OFFSET(((uint32_t)irq)))))))); diff --git a/mcux/mcux-sdk-ng/drivers/irqsteer_1/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/irqsteer_1/CMakeLists.txt index b9f156a31..efc0ebcc2 100644 --- a/mcux/mcux-sdk-ng/drivers/irqsteer_1/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/irqsteer_1/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024-2025 NXP +# Copyright 2024 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.irqsteer_1) - mcux_component_version(2.0.2) + mcux_component_version(2.0.1) mcux_add_source(SOURCES fsl_irqsteer.h fsl_irqsteer.c) diff --git a/mcux/mcux-sdk-ng/drivers/irqsteer_1/fsl_irqsteer.h b/mcux/mcux-sdk-ng/drivers/irqsteer_1/fsl_irqsteer.h index 0391328c3..e57898cf0 100644 --- a/mcux/mcux-sdk-ng/drivers/irqsteer_1/fsl_irqsteer.h +++ b/mcux/mcux-sdk-ng/drivers/irqsteer_1/fsl_irqsteer.h @@ -21,8 +21,8 @@ /*! @name Driver version */ /*! @{ */ -/*! Version 2.0.2. */ -#define FSL_IRQSTEER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! Version 2.0.1. */ +#define FSL_IRQSTEER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*! @} */ /* diff --git a/mcux/mcux-sdk-ng/drivers/irtc/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/irtc/CMakeLists.txt index 1d990557a..2681bb65c 100644 --- a/mcux/mcux-sdk-ng/drivers/irtc/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/irtc/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.irtc) - mcux_component_version(2.3.2) + mcux_component_version(2.3.3) mcux_add_source(SOURCES fsl_irtc.c fsl_irtc.h) diff --git a/mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.c b/mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.c index 647a780b1..8d374c7ef 100644 --- a/mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.c +++ b/mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2023, 2024 NXP + * Copyright 2016-2019, 2023-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -189,13 +189,14 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config) (uint16_t)RTC_CTRL_ALM_MATCH_MASK); reg |= ( #if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) - RTC_CTRL_TIMER_STB_MASK(config->timerStdMask) | + RTC_CTRL_TIMER_STB_MASK(config->timerStdMask ? 1U : 0U) | + #endif #if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT RTC_CTRL_CLK_SEL(config->clockSelect) | #endif #if defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE - RTC_CTRL_CLKO_DIS(config->disableClockOutput) | + RTC_CTRL_CLKO_DIS(config->disableClockOutput ? 1U : 0U) | #endif RTC_CTRL_ALM_MATCH(config->alrmMatch)); base->CTRL = reg; @@ -653,7 +654,7 @@ void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const reg = base->FILTER01_CFG; reg &= ~((uint16_t)RTC_FILTER01_CFG_POL0_MASK | (uint16_t)RTC_FILTER01_CFG_FIL_DUR0_MASK | (uint16_t)RTC_FILTER01_CFG_CLK_SEL0_MASK); - reg |= (RTC_FILTER01_CFG_POL0(tamperConfig->pinPolarity) | + reg |= (RTC_FILTER01_CFG_POL0(tamperConfig->pinPolarity ? 1U : 0U) | RTC_FILTER01_CFG_FIL_DUR0(tamperConfig->filterDuration) | RTC_FILTER01_CFG_CLK_SEL0(tamperConfig->filterClk)); base->FILTER01_CFG = reg; @@ -662,7 +663,7 @@ void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const reg = base->FILTER01_CFG; reg &= ~((uint16_t)RTC_FILTER01_CFG_POL1_MASK | (uint16_t)RTC_FILTER01_CFG_FIL_DUR1_MASK | (uint16_t)RTC_FILTER01_CFG_CLK_SEL1_MASK); - reg |= (RTC_FILTER01_CFG_POL1(tamperConfig->pinPolarity) | + reg |= (RTC_FILTER01_CFG_POL1(tamperConfig->pinPolarity ? 1U : 0U) | RTC_FILTER01_CFG_FIL_DUR1(tamperConfig->filterDuration) | RTC_FILTER01_CFG_CLK_SEL1(tamperConfig->filterClk)); base->FILTER01_CFG = reg; @@ -672,7 +673,7 @@ void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const reg = base->FILTER23_CFG; reg &= ~((uint16_t)RTC_FILTER23_CFG_POL2_MASK | (uint16_t)RTC_FILTER23_CFG_FIL_DUR2_MASK | (uint16_t)RTC_FILTER23_CFG_CLK_SEL2_MASK); - reg |= (RTC_FILTER23_CFG_POL2(tamperConfig->pinPolarity) | + reg |= (RTC_FILTER23_CFG_POL2(tamperConfig->pinPolarity ? 1U : 0U) | RTC_FILTER23_CFG_FIL_DUR2(tamperConfig->filterDuration) | RTC_FILTER23_CFG_CLK_SEL2(tamperConfig->filterClk)); base->FILTER23_CFG = reg; @@ -681,7 +682,7 @@ void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const reg = base->FILTER23_CFG; reg &= ~((uint16_t)RTC_FILTER23_CFG_POL3_MASK | (uint16_t)RTC_FILTER23_CFG_FIL_DUR3_MASK | (uint16_t)RTC_FILTER23_CFG_CLK_SEL3_MASK); - reg |= (RTC_FILTER23_CFG_POL3(tamperConfig->pinPolarity) | + reg |= (RTC_FILTER23_CFG_POL3(tamperConfig->pinPolarity ? 1U : 0U) | RTC_FILTER23_CFG_FIL_DUR3(tamperConfig->filterDuration) | RTC_FILTER23_CFG_CLK_SEL3(tamperConfig->filterClk)); base->FILTER23_CFG = reg; @@ -691,7 +692,7 @@ void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const reg = base->FILTER2_CFG; reg &= ~((uint16_t)RTC_FILTER2_CFG_POL2_MASK | (uint16_t)RTC_FILTER2_CFG_FIL_DUR2_MASK | (uint16_t)RTC_FILTER2_CFG_CLK_SEL2_MASK); - reg |= (RTC_FILTER2_CFG_POL2(tamperConfig->pinPolarity) | + reg |= (RTC_FILTER2_CFG_POL2(tamperConfig->pinPolarity ? 1U : 0U) | RTC_FILTER2_CFG_FIL_DUR2(tamperConfig->filterDuration) | RTC_FILTER2_CFG_CLK_SEL2(tamperConfig->filterClk)); base->FILTER2_CFG = reg; diff --git a/mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.h b/mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.h index d452e264c..e3533a326 100644 --- a/mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.h +++ b/mcux/mcux-sdk-ng/drivers/irtc/fsl_irtc.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2022-2023, 2024 NXP + * Copyright 2016-2019, 2022-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,7 @@ /*! @name Driver version */ /*! @{ */ -#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) +#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) /*! @} */ #if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) diff --git a/mcux/mcux-sdk-ng/drivers/lcdic/fsl_lcdic.c b/mcux/mcux-sdk-ng/drivers/lcdic/fsl_lcdic.c index da9e43cca..fc5d2d6fa 100644 --- a/mcux/mcux-sdk-ng/drivers/lcdic/fsl_lcdic.c +++ b/mcux/mcux-sdk-ng/drivers/lcdic/fsl_lcdic.c @@ -407,8 +407,9 @@ uint32_t LCDIC_FillByteToWord(const uint8_t *bytes, uint8_t len) { uint32_t word = 0U; - while ((len--) > 0u) + while (len != 0U) { + len--; word <<= 8U; word |= bytes[len]; } @@ -429,6 +430,8 @@ uint32_t LCDIC_FillByteToWord(const uint8_t *bytes, uint8_t len) */ void LCDIC_ExtractByteFromWord(uint32_t word, uint8_t *bytes, uint8_t len) { + assert(len <= 4U); + for (uint8_t i = 0; i < len; i++) { bytes[i] = (uint8_t)word; diff --git a/mcux/mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.c b/mcux/mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.c index cc811fd1a..ecf0b2245 100644 --- a/mcux/mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.c +++ b/mcux/mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.c @@ -79,18 +79,18 @@ static void LCDIFV3_ResetRegister(LCDIF_Type *base) base->INT_STATUS_D0 = 0xFFFFFFFFU; base->INT_STATUS_D1 = 0xFFFFFFFFU; - base->CTRLDESCL_1 = 0U; - base->CTRLDESCL_3 = 0U; - base->CTRLDESCL_LOW_4 = 0U; - base->CTRLDESCL_HIGH_4 = 0U; - base->CTRLDESCL_5 = 0U; - - base->CSC_COEF0 = 0x0U; - base->CSC_COEF1 = 0x0U; - base->CSC_COEF2 = 0x0U; - base->CSC_COEF3 = 0x0U; - base->CSC_COEF4 = 0x0U; - base->CSC_COEF5 = 0x0U; + base->CTRLDESCL_1[0] = 0U; + base->CTRLDESCL_3[0] = 0U; + base->CTRLDESCL_LOW_4[0] = 0U; + base->CTRLDESCL_HIGH_4[0] = 0U; + base->CTRLDESCL_5[0] = 0U; + + base->CSC_COEF0[0] = 0x0U; + base->CSC_COEF1[0] = 0x0U; + base->CSC_COEF2[0] = 0x0U; + base->CSC_COEF3[0] = 0x0U; + base->CSC_COEF4[0] = 0x0U; + base->CSC_COEF5[0] = 0x0U; } /*! @@ -185,10 +185,10 @@ void LCDIFV3_SetDisplayConfig(LCDIF_Type *base, const lcdifv3_display_config_t * base->VSYN_PARA = ((uint32_t)config->vbp << LCDIF_VSYN_PARA_BP_V_SHIFT) | ((uint32_t)config->vfp << LCDIF_VSYN_PARA_FP_V_SHIFT); - + base->VSYN_HSYN_WIDTH = ((uint32_t)config->hsw << LCDIF_VSYN_HSYN_WIDTH_PW_H_SHIFT) | ((uint32_t)config->vsw << LCDIF_VSYN_HSYN_WIDTH_PW_V_SHIFT); - + base->DISP_PARA = LCDIF_DISP_PARA_LINE_PATTERN((uint32_t)config->lineOrder); base->CTRL.RW = (uint32_t)(config->polarityFlags); @@ -219,50 +219,50 @@ void LCDIFV3_SetCscMode(LCDIF_Type *base, lcdifv3_csc_mode_t mode) * V = C1*R + C2*G + C3*B + D3 */ - base->CSC_CTRL &= ~(LCDIF_CSC_CTRL_CSC_MODE_MASK | LCDIF_CSC_CTRL_BYPASS_MASK); + base->CSC_CTRL[0] &= ~(LCDIF_CSC_CTRL_CSC_MODE_MASK | LCDIF_CSC_CTRL_BYPASS_MASK); if (kLCDIFV3_CscYUV2RGB == mode || kLCDIFV3_CscYCbCr2RGB == mode) { - base->CSC_COEF0 = LCDIF_CSC_COEF0_A1(0x0U) + base->CSC_COEF0[0] = LCDIF_CSC_COEF0_A1(0x0U) | LCDIF_CSC_COEF0_A2(0x0U); - base->CSC_COEF1 = LCDIF_CSC_COEF1_A3(0x0U) + base->CSC_COEF1[0] = LCDIF_CSC_COEF1_A3(0x0U) | LCDIF_CSC_COEF1_B1(0x0U); - base->CSC_COEF2 = LCDIF_CSC_COEF2_B2(0x0U) + base->CSC_COEF2[0] = LCDIF_CSC_COEF2_B2(0x0U) | LCDIF_CSC_COEF2_B3(0x0U); - base->CSC_COEF3 = LCDIF_CSC_COEF3_C1(0x0U) + base->CSC_COEF3[0] = LCDIF_CSC_COEF3_C1(0x0U) | LCDIF_CSC_COEF3_C2(0x0U); - base->CSC_COEF4 = LCDIF_CSC_COEF4_C3(0x0U) + base->CSC_COEF4[0] = LCDIF_CSC_COEF4_C3(0x0U) | LCDIF_CSC_COEF4_D1(0x0U); - base->CSC_COEF5 = LCDIF_CSC_COEF5_D2(0x0U) + base->CSC_COEF5[0] = LCDIF_CSC_COEF5_D2(0x0U) | LCDIF_CSC_COEF5_D3(0x0U); } else if (kLCDIFV3_CscRGB2YUV == mode || kLCDIFV3_CscRGB2YCbCr == mode) { - base->CSC_COEF0 = LCDIF_CSC_COEF0_A1(0x0U) + base->CSC_COEF0[0] = LCDIF_CSC_COEF0_A1(0x0U) | LCDIF_CSC_COEF0_A2(0x0U); - base->CSC_COEF1 = LCDIF_CSC_COEF1_A3(0x0U) + base->CSC_COEF1[0] = LCDIF_CSC_COEF1_A3(0x0U) | LCDIF_CSC_COEF1_B1(0x0U); - base->CSC_COEF2 = LCDIF_CSC_COEF2_B2(0x0U) + base->CSC_COEF2[0] = LCDIF_CSC_COEF2_B2(0x0U) | LCDIF_CSC_COEF2_B3(0x0U); - base->CSC_COEF3 = LCDIF_CSC_COEF3_C1(0x0U) + base->CSC_COEF3[0] = LCDIF_CSC_COEF3_C1(0x0U) | LCDIF_CSC_COEF3_C2(0x0U); - base->CSC_COEF4 = LCDIF_CSC_COEF4_C3(0x0U) + base->CSC_COEF4[0] = LCDIF_CSC_COEF4_C3(0x0U) | LCDIF_CSC_COEF4_D1(0x0U); - base->CSC_COEF5 = LCDIF_CSC_COEF5_D2(0x0U) + base->CSC_COEF5[0] = LCDIF_CSC_COEF5_D2(0x0U) | LCDIF_CSC_COEF5_D3(0x0U); } else { - base->CSC_COEF0 = 0x0U; - base->CSC_COEF1 = 0x0U; - base->CSC_COEF2 = 0x0U; - base->CSC_COEF3 = 0x0U; - base->CSC_COEF4 = 0x0U; - base->CSC_COEF5 = 0x0U; - base->CSC_CTRL |= LCDIF_CSC_CTRL_BYPASS(1); + base->CSC_COEF0[0] = 0x0U; + base->CSC_COEF1[0] = 0x0U; + base->CSC_COEF2[0] = 0x0U; + base->CSC_COEF3[0] = 0x0U; + base->CSC_COEF4[0] = 0x0U; + base->CSC_COEF5[0] = 0x0U; + base->CSC_CTRL[0] |= LCDIF_CSC_CTRL_BYPASS(1); } - base->CSC_CTRL |= LCDIF_CSC_CTRL_CSC_MODE(mode); + base->CSC_CTRL[0] |= LCDIF_CSC_CTRL_CSC_MODE(mode); } /*! @@ -275,9 +275,45 @@ void LCDIFV3_SetLayerBufferConfig(LCDIF_Type *base, uint8_t layerIndex, const lc { assert(NULL != config); uint32_t reg; - base->CTRLDESCL_3 = config->strideBytes; - reg = base->CTRLDESCL_5; + base->CTRLDESCL_3[0] = config->strideBytes; + reg = base->CTRLDESCL_5[0]; reg = (reg & ~(LCDIF_CTRLDESCL_5_BPP_MASK | LCDIF_CTRLDESCL_5_YUV_FORMAT_MASK)) | (uint32_t)config->pixelFormat; - base->CTRLDESCL_5 = reg; + base->CTRLDESCL_5[0] = reg; +} + +/*! + * @brief Enable plane panic to avoid underrun. + * + * @param base LCDIFv3 peripheral base address. + */ +void LCDIFV3_EnablePlanePanic(LCDIF_Type *base) +{ + uint32_t panic_thres, thres_low, thres_high; + + /* apb clock has been enabled */ + + /* As suggestion, the thres_low should be 1/3 FIFO, + * and thres_high should be 2/3 FIFO (The FIFO size + * is 8KB = 512 * 128bit). + * threshold = n * 128bit (n: 0 ~ 511) + */ + thres_low = 511 * 1 / 3; + + thres_high = 511 * 2 / 3; + + panic_thres = thres_low << LCDIF_PANIC_THRES_PANIC_THRES_LOW_SHIFT | + thres_high << LCDIF_PANIC_THRES_PANIC_THRES_HIGH_SHIFT; + + base->PANIC_THRES[0] = panic_thres; + + /* Enable Panic: + * + * As designed, the panic won't trigger an irq, + * so it is unnecessary to handle this as an irq + * and NoC + QoS modules will handle panic + * automatically. + */ + base->INT_ENABLE_D1 = LCDIF_INT_STATUS_D1_PLANE_PANIC_MASK; + } diff --git a/mcux/mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.h b/mcux/mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.h index 76e706096..f4cc25f72 100644 --- a/mcux/mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.h +++ b/mcux/mcux-sdk-ng/drivers/lcdifv3/fsl_lcdifv3.h @@ -353,7 +353,7 @@ static inline void LCDIFV3_ClearInterruptStatus(LCDIF_Type *base, uint32_t mask) */ static inline void LCDIFV3_SetLayerSize(LCDIF_Type *base, uint8_t layerIndex, uint16_t width, uint16_t height) { - base->CTRLDESCL_1 = + base->CTRLDESCL_1[0] = ((uint32_t)height << LCDIF_CTRLDESCL_1_HEIGHT_SHIFT) | ((uint32_t)width << LCDIF_CTRLDESCL_1_WIDTH_SHIFT); } @@ -377,7 +377,7 @@ void LCDIFV3_SetLayerBufferConfig(LCDIF_Type *base, uint8_t layerIndex, const lc */ static inline void LCDIFV3_SetLayerBufferAddr(LCDIF_Type *base, uint8_t layerIndex, uint32_t addr) { - base->CTRLDESCL_LOW_4 = LCDIFV3_ADDR_CPU_2_IP(addr); + base->CTRLDESCL_LOW_4[0] = LCDIFV3_ADDR_CPU_2_IP(addr); } /*! @@ -392,11 +392,11 @@ static inline void LCDIFV3_EnableLayer(LCDIF_Type *base, uint8_t layerIndex, boo { if (enable) { - base->CTRLDESCL_5 |= LCDIF_CTRLDESCL_5_EN_MASK; + base->CTRLDESCL_5[0] |= LCDIF_CTRLDESCL_5_EN_MASK; } else { - base->CTRLDESCL_5 &= ~LCDIF_CTRLDESCL_5_EN_MASK; + base->CTRLDESCL_5[0] &= ~LCDIF_CTRLDESCL_5_EN_MASK; } } @@ -414,7 +414,7 @@ static inline void LCDIFV3_EnableLayer(LCDIF_Type *base, uint8_t layerIndex, boo */ static inline void LCDIFV3_TriggerLayerShadowLoad(LCDIF_Type *base, uint8_t layerIndex) { - base->CTRLDESCL_5 |= LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_MASK; + base->CTRLDESCL_5[0] |= LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_MASK; } /*! @@ -428,6 +428,13 @@ static inline void LCDIFV3_TriggerLayerShadowLoad(LCDIF_Type *base, uint8_t laye */ void LCDIFV3_SetCscMode(LCDIF_Type *base, lcdifv3_csc_mode_t mode); +/*! + * @brief Enable plane panic to avoid underrun. + * + * @param base LCDIFv3 peripheral base address. + */ +void LCDIFV3_EnablePlanePanic(LCDIF_Type *base); + /*! @} */ #if defined(__cplusplus) diff --git a/mcux/mcux-sdk-ng/drivers/lin/fsl_lin.c b/mcux/mcux-sdk-ng/drivers/lin/fsl_lin.c index 4254060dd..b5665a9e7 100644 --- a/mcux/mcux-sdk-ng/drivers/lin/fsl_lin.c +++ b/mcux/mcux-sdk-ng/drivers/lin/fsl_lin.c @@ -53,9 +53,10 @@ lin_user_config_t *g_linUserconfigPtr[FSL_FEATURE_SOC_LPUART_COUNT]; static inline uint8_t BIT(const uint8_t A, uint8_t B) { + assert(B < 8U); uint8_t tmp = A; - tmp = (uint8_t)(((uint8_t)((uint8_t)(tmp) >> (uint8_t)(B))) & 0x01U); + tmp = ((tmp >> B) & 0x01U); return tmp; } @@ -71,6 +72,7 @@ static inline uint8_t BIT(const uint8_t A, uint8_t B) */ uint32_t LIN_CalcMaxHeaderTimeoutCnt(uint32_t baudRate) { + assert(baudRate <= (0xFFFFFFFFUL / LIN_TIME_OUT_UNIT_US)); return (uint32_t)((14U * 2U * 1000000U / (LIN_TIME_OUT_UNIT_US * baudRate)) + 1U); } @@ -85,6 +87,7 @@ uint32_t LIN_CalcMaxHeaderTimeoutCnt(uint32_t baudRate) */ uint32_t LIN_CalcMaxResTimeoutCnt(uint32_t baudRate, uint8_t size) { + assert(baudRate <= (0xFFFFFFFFUL / LIN_TIME_OUT_UNIT_US)); return (uint32_t)((14U * (1U + (uint32_t)size) * 1000000U / (LIN_TIME_OUT_UNIT_US * baudRate)) + 1U); } diff --git a/mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.c b/mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.c index b98fbbee4..31e8f8b3e 100644 --- a/mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.c +++ b/mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.c @@ -70,6 +70,16 @@ * $Justification lin_lpuart_c_ref_13$ * The LIN driver test cases are run in bare metal environment and can only be usd * in non-blocking interrupt way. + * + * $Justification lin_lpuart_c_ref_14$ + * Normally no other interrupt status can be detected, the false branch can only be + * covered when the interrupt enablement is corrupted in user application such as + * other unrelated interrupt is enabled by mistake. + * + * $Justification lin_lpuart_c_ref_15$ + * The measurement overflow can only happen when the registered function uses a timer + * whose counter's clock source is not set properly, and the autobaud sequence the LIN + * master send uses an invalid baudrate. */ /******************************************************************************* @@ -150,6 +160,8 @@ status_t LIN_LPUART_CalculateBaudRate( LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *osr, uint16_t *sbr) { assert(0U != baudRate_Bps); + assert((srcClock_Hz / baudRate_Bps / 4U) <= 0xFFFFU); + status_t status = kStatus_Success; uint16_t sbrTemp; @@ -589,9 +601,9 @@ static void LIN_LPUART_EvalTwoBitTimeLength(uint32_t instance, uint32_t twoBitTi { /* $Branch Coverage Justification$ $ref lin_lpuart_c_ref_7 $ */ if ((twoBitTimeLength < - ((100U - BIT_RATE_TOLERANCE_UNSYNC) * s_previousTwoBitTimeLength[instance] / 100U)) || + ((100U - BIT_RATE_TOLERANCE_UNSYNC) * (s_previousTwoBitTimeLength[instance] / 100U))) || (twoBitTimeLength > - ((100U + BIT_RATE_TOLERANCE_UNSYNC) * s_previousTwoBitTimeLength[instance] / 100U))) + ((100U + BIT_RATE_TOLERANCE_UNSYNC) * (s_previousTwoBitTimeLength[instance] / 100U)))) { /* cancel capturing */ (void)LIN_LPUART_GotoIdleState(base); @@ -1864,10 +1876,16 @@ lin_status_t LIN_LPUART_AutoBaudCapture(uint32_t instance) /* Calculate time between two bit (for service autobaud) */ (void)linUserConfig->timerGetTimeIntervalCallback(&tmpTime); + /* $Branch Coverage Justification$ $ref lin_lpuart_c_ref_15$ */ + if (s_timeMeasure[instance] > (0xFFFFFFFFUL - tmpTime)) + { + return LIN_ERROR; + } + /* Get two bits time length */ s_timeMeasure[instance] += tmpTime; s_countMeasure[instance]++; - if ((s_countMeasure[instance] > 1U)) + if (s_countMeasure[instance] > 1U) { switch (linCurrentState->currentNodeState) { @@ -2053,6 +2071,7 @@ void LIN_LPUART_IRQHandler(LPUART_Type *base) } else { + /* $Branch Coverage Justification$ $ref lin_lpuart_c_ref_14$ */ if (0U != (LIN_LPUART_GetStatusFlags(base) & (uint32_t)kLPUART_RxDataRegFullFlag)) { (void)LIN_LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxDataRegFullFlag); diff --git a/mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.h b/mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.h index d227c99a4..977ca3a4a 100644 --- a/mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.h +++ b/mcux/mcux-sdk-ng/drivers/lin/fsl_lin_lpuart.h @@ -73,7 +73,7 @@ enum _lin_lpuart_flags (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakFlag = (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */ #endif kLPUART_RxActiveEdgeFlag = diff --git a/mcux/mcux-sdk-ng/drivers/lpacmp/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/lpacmp/CMakeLists.txt new file mode 100644 index 000000000..2eba97a1a --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/lpacmp/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +if(CONFIG_MCUX_COMPONENT_driver.lpacmp) + mcux_component_version(2.0.1) + + mcux_add_source(SOURCES fsl_lpacmp.c fsl_lpacmp.h) + + mcux_add_include(INCLUDES .) + +endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.c b/mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.c new file mode 100644 index 000000000..c45352013 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.c @@ -0,0 +1,141 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpacmp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpacmp" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPACMP bases for each instance. */ +static LPACMP_Type *const s_LpacmpBases[] = LPACMP_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPACMP clocks for each instance. */ +static const clock_ip_name_t s_LpacmpClocks[] = LPACMP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPACMP_RSTS) +static const SYSCON_RSTn_t s_lpacmpResets[] = LPACMP_RSTS; +#endif /* LPACMP_RSTS */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPACMP_GetInstance(LPACMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_LpacmpBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ + for (instance = 0; instance < ARRAY_SIZE(s_LpacmpBases); instance++) + { + /* + * $Branch Coverage Justification$ + * (s_LpacmpBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ + if (MSDK_REG_SECURE_ADDR(s_LpacmpBases[instance]) == MSDK_REG_SECURE_ADDR(base)) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_LpacmpBases)); + + return instance; +} + +/*! + * brief Gets an available pre-defined settings for LPACMP configuration. + * + * param config Pointer to the LPACMP configuration structure, please refer to @ref lpacmp_config_t for details. + */ +void LPACMP_GetDefaultConfig(lpacmp_config_t *config) +{ + assert(config != NULL); + + (void)memset(config, 0U, sizeof(*config)); + + config->mode = kLPACMP_Continuous_Mode; + config->channelConfig = NULL; + config->channelCount = 0U; + config->intervalTime = 0U; +} + +/*! + * brief Initialize the LPACMP module + * + * param base LPACMP peripheral base address + * param config Pointer to the LPACMP configuration structure, please refer to @ref lpacmp_config_t for details. + */ +void LPACMP_Init(LPACMP_Type *base, const lpacmp_config_t *config) +{ + assert(config != NULL); + assert(config->channelConfig->channelIndex < LPACMP_EXT_TRIG_COUNT); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + (void)CLOCK_EnableClock(s_LpacmpClocks[LPACMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPACMP_RSTS) + RESET_ReleasePeripheralReset(s_lpacmpResets[LPACMP_GetInstance(base)]); +#endif /* LPACMP_RSTS */ + + /* Disable block before configuration */ + LPACMP_EnableComparator(base, false); + + /* Set operation mode and delay */ + LPACMP_SetComparatorMode(base, config->mode); + LPACMP_SetIntervalTime(base, config->intervalTime); + + /* Channels configuration. */ + lpacmp_channel_config_t *chanConf = config->channelConfig; + + for (uint8_t index = 0U; index < config->channelCount; ++index) + { + LPACMP_EnableWakeupToSmm(base, chanConf->channelIndex, chanConf->enableWakeupToSmm); + LPACMP_EnableTriggerOutput(base, chanConf->channelIndex, chanConf->enableTriggerOutput); + LPACMP_EnableInterrupt(base, chanConf->channelIndex, chanConf->enableInterrupt); + LPACMP_EnableChannel(base, chanConf->channelIndex, true); + LPACMP_SetTriggerOutputWidth(base, chanConf->channelIndex, chanConf->triggerOutputWidth); + LPACMP_SetDelayValue(base, chanConf->channelIndex, chanConf->delay); + + LPACMP_SetComparePolarity(base, chanConf->channelIndex, chanConf->comparePolarityHigher); + LPACMP_ChannelInputSelection(base, chanConf->channelIndex, chanConf->positiveInput, chanConf->negativeInput); + + chanConf += 1U; + } +} + +/*! + * brief De-initializes the LPACMP module + * + * param base LPACMP peripheral base address + */ +void LPACMP_Deinit(LPACMP_Type *base) +{ + LPACMP_EnableComparator(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + (void)CLOCK_DisableClock(s_LpacmpClocks[LPACMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPACMP_RSTS) + RESET_SetPeripheralReset(s_lpacmpResets[LPACMP_GetInstance(base)]); +#endif /* LPACMP_RSTS */ +} diff --git a/mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.h b/mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.h new file mode 100644 index 000000000..1e15e1d63 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/lpacmp/fsl_lpacmp.h @@ -0,0 +1,357 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPACMP_H +#define FSL_LPACMP_H + +#include "fsl_common.h" + +/*! + * @addtogroup lpacmp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPACMP driver version */ +#define FSL_LPACMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @} */ + +/*! @brief Comparator negative input source */ +typedef enum _lpacmp_negative_input { + kLPACMP_Negative_Input_Avdd_Divide_15 = 0U, /*!< Comparator negative input source 1 x AVDD / 15 */ + kLPACMP_Negative_Input_2Avdd_Divide_15 = 1U, /*!< Comparator negative input source 2 x AVDD / 15 */ + kLPACMP_Negative_Input_3Avdd_Divide_15 = 2U, /*!< Comparator negative input source 3 x AVDD / 15 */ + kLPACMP_Negative_Input_4Avdd_Divide_15 = 3U, /*!< Comparator negative input source 4 x AVDD / 15 */ + kLPACMP_Negative_Input_5Avdd_Divide_15 = 4U, /*!< Comparator negative input source 5 x AVDD / 15 */ + kLPACMP_Negative_Input_6Avdd_Divide_15 = 5U, /*!< Comparator negative input source 6 x AVDD / 15 */ + kLPACMP_Negative_Input_7Avdd_Divide_15 = 6U, /*!< Comparator negative input source 7 x AVDD / 15 */ + kLPACMP_Negative_Input_8Avdd_Divide_15 = 7U, /*!< Comparator negative input source 8 x AVDD / 15 */ + kLPACMP_Negative_Input_9Avdd_Divide_15 = 8U, /*!< Comparator negative input source 9 x AVDD / 15 */ + kLPACMP_Negative_Input_10Avdd_Divide_15 = 9U, /*!< Comparator negative input source 10 x AVDD / 15 */ + kLPACMP_Negative_Input_11Avdd_Divide_15 = 10U, /*!< Comparator negative input source 11 x AVDD / 15 */ + kLPACMP_Negative_Input_12Avdd_Divide_15 = 11U, /*!< Comparator negative input source 12 x AVDD / 15 */ + kLPACMP_Negative_Input_13Avdd_Divide_15 = 12U, /*!< Comparator negative input source 13 x AVDD / 15 */ + kLPACMP_Negative_Input_14Avdd_Divide_15 = 13U, /*!< Comparator negative input source 14 x AVDD / 15 */ + kLPACMP_Negative_Input_In4 = 14U, /*!< Comparator negative input source 4 */ + kLPACMP_Negative_Input_In5 = 15U, /*!< Comparator negative input source 5 */ +} lpacmp_negative_input_t; + +/*! @brief Comparator positive input source */ +typedef enum _lpacmp_positive_input { + kLPACMP_Positive_Input_In4 = 0U, /*!< Comparator positive input source 4 */ + kLPACMP_Positive_Input_In5 = 1U, /*!< Comparator positive input source 5 */ + kLPACMP_Positive_Input_In0 = 2U, /*!< Comparator positive input source 0 */ + kLPACMP_Positive_Input_In1 = 3U, /*!< Comparator positive input source 1 */ + kLPACMP_Positive_Input_In2 = 4U, /*!< Comparator positive input source 2 */ + kLPACMP_Positive_Input_In3 = 5U, /*!< Comparator positive input source 3 */ +} lpacmp_positive_input_t; + +/*! @brief Comparator operation modes */ +typedef enum _lpacmp_mode { + kLPACMP_Continuous_Mode = 0U, /*!< Always-on comparison */ + kLPACMP_Interval_Mode = 1U, /*!< Periodic sampling with internal timer */ + kLPACMP_Trigger_Mode = 2U, /*!< External trigger activation */ +} lpacmp_mode_t; + +/*! @brief Channel configuration structure */ +typedef struct _lpacmp_channel_config { + bool enableWakeupToSmm; /*!< Decides whether to enable wakeup to SMM */ + bool enableTriggerOutput; /*!< Decides whether to enable trigger output */ + bool enableInterrupt; /*!< Decides whether to enable match interrupt */ + bool comparePolarityHigher; /*!< Decides comparison polarity */ + uint8_t channelIndex; /*!< Indicates the channel being configured */ + uint8_t triggerOutputWidth; /*!< Sets trigger output width */ + uint16_t delay; /*!< Sets the delay value for which a compare event is sampled */ + lpacmp_positive_input_t positiveInput; /*!< Positive input selection (see RM SELn.INP_SEL) */ + lpacmp_negative_input_t negativeInput; /*!< Negative input selection (see RM SELn.INN_SEL) */ +} lpacmp_channel_config_t; + +/*! @brief Comparator configuration structure */ +typedef struct _lpacmp_config { + uint8_t channelCount; /*!< Indicates the channel counts */ + uint16_t intervalTime; /*!< Indicates the interval time */ + lpacmp_mode_t mode; /*!< Operating mode */ + lpacmp_channel_config_t *channelConfig; /*!< Channel configuration */ +} lpacmp_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPACMP initialization, de-initialization, and configuration + * @{ + */ +/*! + * @brief Initialize the LPACMP module + * + * @param base LPACMP peripheral base address + * @param config Pointer to the LPACMP configuration structure, please refer to @ref lpacmp_config_t for details. + */ +void LPACMP_Init(LPACMP_Type *base, const lpacmp_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for LPACMP configuration. + * + * @param config Pointer to the LPACMP configuration structure, please refer to @ref lpacmp_config_t for details. + */ +void LPACMP_GetDefaultConfig(lpacmp_config_t *config); + +/*! + * @brief De-initializes the LPACMP module + * + * @param base LPACMP peripheral base address + */ +void LPACMP_Deinit(LPACMP_Type *base); + +/*! + * @brief Enable/Disable comparator module + * + * @param base LPACMP peripheral base address + * @param enable Indicates whether to enable the comparator module + * @b true Enable the comparator module + * @b false Disable the comparator module + */ +static inline void LPACMP_EnableComparator(LPACMP_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPACMP_CTRL_BLOCK_EN_MASK; + } + else + { + base->CTRL &= ~LPACMP_CTRL_BLOCK_EN_MASK; + } +} + +/*! + * @brief Set comparator mode + * + * @param base LPACMP peripheral base address + * @param mode comparator mode + */ +static inline void LPACMP_SetComparatorMode(LPACMP_Type *base, lpacmp_mode_t mode) +{ + base->CTRL = ((base->CTRL & ~(LPACMP_CTRL_MODE_MASK)) | LPACMP_CTRL_MODE(mode)); +} + +/*! + * @brief Compare event trigger interval time + * + * @param base LPACMP peripheral base address + * @param time Compare event trigger interval time + */ +static inline void LPACMP_SetIntervalTime(LPACMP_Type *base, uint16_t time) +{ + base->INTERVAL = ((base->INTERVAL & ~(LPACMP_INTERVAL_INVL_MASK)) | LPACMP_INTERVAL_INVL(time)); +} +/*! @} */ + +/*! + * @name LPACMP channel configuration + * @{ + */ +/*! + * @brief Channel positive and negative input selection + * + * @param base LPACMP peripheral base address + * @param channel Trigger channel index (0-3) + * @param positive Positive input channel selection + * @param negative Negative input channel selection + */ +static inline void LPACMP_ChannelInputSelection(LPACMP_Type *base, + uint8_t channel, + lpacmp_positive_input_t positive, + lpacmp_negative_input_t negative) +{ + assert(channel < LPACMP_EXT_TRIG_COUNT); + + base->EXT_TRIG[channel].SEL = ((base->EXT_TRIG[channel].SEL & ~(LPACMP_SEL_INN_SEL_MASK | LPACMP_SEL_INP_SEL_MASK)) | + (LPACMP_SEL_INP_SEL(positive) | LPACMP_SEL_INN_SEL(negative))); +} + +/*! + * @brief Comparison polarity configuration + * + * @param base LPACMP peripheral base address + * @param channel Trigger channel index (0-3) + * @param polarity Comparison polarity + * - @b true When the value we are checking is higher than the reference value. + * input parameter 'result'. + * - @b false When the value we are checking is lower than the reference value. + */ +static inline void LPACMP_SetComparePolarity(LPACMP_Type *base, + uint8_t channel, + bool polarity) +{ + assert(channel < LPACMP_EXT_TRIG_COUNT); + + base->EXT_TRIG[channel].SEL = ((base->EXT_TRIG[channel].SEL & ~(LPACMP_SEL_HIGHER_MASK)) | + LPACMP_SEL_HIGHER(polarity ? 1U : 0U)); +} + +/*! + * @brief Compare event sample delay value + * + * @param base LPACMP peripheral base address + * @param channel Trigger channel index (0-3) + * @param delay Compare event sample delay value + */ +static inline void LPACMP_SetDelayValue(LPACMP_Type *base, uint8_t channel, uint16_t delay) +{ + assert(channel < LPACMP_EXT_TRIG_COUNT); + + base->EXT_TRIG[channel].DELAY = ((base->EXT_TRIG[channel].DELAY & ~(LPACMP_DELAY_DEL_MASK)) | LPACMP_DELAY_DEL(delay)); +} + +/*! + * @brief Set the trigger output width in clock units + * + * @param base LPACMP peripheral base address + * @param channel Trigger channel index (0-3) + * @param width trigger output width + */ +static inline void LPACMP_SetTriggerOutputWidth(LPACMP_Type *base, uint8_t channel, uint8_t width) +{ + assert(channel < LPACMP_EXT_TRIG_COUNT); + + base->EXT_TRIG[channel].STATUS |= ((base->EXT_TRIG[channel].STATUS & ~(LPACMP_STATUS_TRGOPWDH_MASK)) | LPACMP_STATUS_TRGOPWDH(width)); +} + +/*! + * @brief Enable/Disable wakeup to SMM + * + * @param base LPACMP peripheral base address + * @param channel Trigger channel index (0-3) + * @param enable Indicates whether to enable the comparator module + * - @b true Enable the comparator module + * - @b false Disable the comparator module + */ +static inline void LPACMP_EnableWakeupToSmm(LPACMP_Type *base, uint8_t channel, bool enable) +{ + assert(channel < LPACMP_EXT_TRIG_COUNT); + + if (enable) + { + base->EXT_TRIG[channel].STATUS |= LPACMP_STATUS_WAKEUPEN_MASK; + } + else + { + base->EXT_TRIG[channel].STATUS &= ~LPACMP_STATUS_WAKEUPEN_MASK; + } +} + +/*! + * @brief Enable/Disable trigger output + * + * @param base LPACMP peripheral base address + * @param channel Channel index (0-3) + * @param enable Indicates whether to enable the trigger output + * - @b true Enable the trigger output + * - @b false Disable the trigger output + */ +static inline void LPACMP_EnableTriggerOutput(LPACMP_Type *base, uint8_t channel, bool enable) +{ + assert(channel < LPACMP_EXT_TRIG_COUNT); + + if (enable) + { + base->EXT_TRIG[channel].STATUS |= LPACMP_STATUS_TRGOP_EN_MASK; + } + else + { + base->EXT_TRIG[channel].STATUS &= ~LPACMP_STATUS_TRGOP_EN_MASK; + } +} + +/*! + * @brief Enable/Disable channel + * + * @param base LPACMP peripheral base address + * @param channel Channel index (0-3) + * @param enable Indicates whether to enable the trigger output + * @b true Enable the trigger output + * @b false Disable the trigger output + */ +static inline void LPACMP_EnableChannel(LPACMP_Type *base, uint8_t channel, bool enable) +{ + assert(channel < LPACMP_EXT_TRIG_COUNT); + + if (enable) + { + base->EXT_TRIG[channel].STATUS |= LPACMP_STATUS_CHNL_EN_MASK; + } + else + { + base->EXT_TRIG[channel].STATUS &= ~LPACMP_STATUS_CHNL_EN_MASK; + } +} +/*! @} */ + +/*! + * @name LPACMP interrupts control + * @{ + */ +/*! + * @brief Enable/Disable match interrupt for specific channel + * + * @param base LPACMP peripheral base address + * @param channel Trigger channel index (0-3) + * @param enable Indicates whether to enable or disable the match interrupt + * @b true Enable the match interrupt + * @b false Disable the match interrupt + */ +static inline void LPACMP_EnableInterrupt(LPACMP_Type *base, uint8_t channel, bool enable) +{ + assert(channel < LPACMP_EXT_TRIG_COUNT); + + if (enable) + { + base->EXT_TRIG[channel].STATUS |= LPACMP_STATUS_MATCH_IE_MASK; + } + else + { + base->EXT_TRIG[channel].STATUS &= ~LPACMP_STATUS_MATCH_IE_MASK; + } +} + +/*! + * @brief Clear comparison interrupt status flags + * + * @param base LPACMP peripheral base address + * @param channel Trigger channel index (0-3) + * @remark Uses Write-1-to-Clear (W1C) mechanism + */ +static inline void LPACMP_ClearInterruptStatusFlags(LPACMP_Type *base, uint8_t channel) +{ + base->COMP_IF = 1U; +} + +/*! + * @brief Get the comparison interrupt status flag + * + * @param base LPACMP peripheral base address + * @return Comparison interrupt status flags + */ +static inline uint32_t LPACMP_GetInterruptStatusFlags(LPACMP_Type *base) +{ + return base->COMP_IF; +} +/*! @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif /* FSL_LPACMP_H */ diff --git a/mcux/mcux-sdk-ng/drivers/lpadc/fsl_lpadc.c b/mcux/mcux-sdk-ng/drivers/lpadc/fsl_lpadc.c index 10ad026ff..4be0ebef2 100644 --- a/mcux/mcux-sdk-ng/drivers/lpadc/fsl_lpadc.c +++ b/mcux/mcux-sdk-ng/drivers/lpadc/fsl_lpadc.c @@ -586,7 +586,10 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ * Command Buffers that have a corresponding Compare Value register. Therefore, assertion judgment needs to be * made before setting the CV register. */ - + /* + * $Branch Coverage Justification$ + * For some chips, the LPADC command compare function is always supported. + */ if ((kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) && (commandId < ADC_CV_COUNT)) { /* Set CV register. */ diff --git a/mcux/mcux-sdk-ng/drivers/lpc_lcdc/fsl_lcdc.c b/mcux/mcux-sdk-ng/drivers/lpc_lcdc/fsl_lcdc.c index 3f84ca16f..d2a4f025a 100644 --- a/mcux/mcux-sdk-ng/drivers/lpc_lcdc/fsl_lcdc.c +++ b/mcux/mcux-sdk-ng/drivers/lpc_lcdc/fsl_lcdc.c @@ -108,7 +108,7 @@ static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_ *divider = 0U; /* Find the PCD. */ - pcd = (srcClock_Hz + (config->panelClock_Hz / 2U)) / config->panelClock_Hz; + pcd = (srcClock_Hz + (config->panelClock_Hz / 2UL)) / config->panelClock_Hz; if (pcd <= 1U) { diff --git a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/CMakeLists.txt index ca04e7b05..8a8ddb82c 100644 --- a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.lpflexcomm_lpspi) - mcux_component_version(2.2.8) + mcux_component_version(2.2.9) mcux_add_source(SOURCES fsl_lpspi.h fsl_lpspi.c) diff --git a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/fsl_lpspi.c b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/fsl_lpspi.c index e9d4d87b0..ecec23022 100644 --- a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/fsl_lpspi.c +++ b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/fsl_lpspi.c @@ -239,7 +239,7 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK | LPSPI_CFGR1_SAMPLE_MASK | LPSPI_CFGR1_PCSCFG_MASK )) | LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) | - LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay )| + LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE(masterConfig->enableInputDelay ? 1U : 0U) | LPSPI_CFGR1_PCSCFG(masterConfig->pcsFunc); /* Set baudrate and delay times*/ @@ -764,6 +764,7 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, /* write the best scaler value for the delay */ LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay); + assert(bestDelay <= UINT32_MAX); /* return the actual calculated delay value (in ns) */ return (uint32_t)bestDelay; } diff --git a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/fsl_lpspi.h b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/fsl_lpspi.h index 9a29bf29d..60eef0de5 100644 --- a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/fsl_lpspi.h +++ b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpspi/fsl_lpspi.h @@ -23,7 +23,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief LPSPI driver version. */ -#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 8)) +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 9)) /*! @} */ #ifndef LPSPI_DUMMY_DATA diff --git a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/CMakeLists.txt index ff9399c04..147785d92 100644 --- a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.lpflexcomm_lpuart) - mcux_component_version(2.3.3) + mcux_component_version(2.3.4) mcux_add_source(SOURCES fsl_lpuart.h fsl_lpuart.c) diff --git a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/fsl_lpuart.c b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/fsl_lpuart.c index 397be584d..09380c2ab 100644 --- a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/fsl_lpuart.c +++ b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/fsl_lpuart.c @@ -281,9 +281,10 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t status_t status = kStatus_Success; uint32_t temp; - uint16_t sbr, sbrTemp; + uint16_t sbr; uint8_t osr, osrTemp; uint32_t tempDiff, calculatedBaud, baudDiff; + uint64_t sbrTemp; /* This LPUART instantiation uses a slightly different baud rate calculation * The idea is to use the best OSR (over-sampling rate) possible @@ -296,9 +297,10 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t sbr = 0U; for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) { - /* calculate the temporary sbr value */ - sbrTemp = (uint16_t)((srcClock_Hz * 2U / (config->baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + /* Calculate the temporary sbr value */ + sbrTemp = ((((uint64_t)srcClock_Hz * 2U) / ((uint64_t)config->baudRate_Bps * (uint64_t)osrTemp)) + 1U) / 2U; + + /* Set sbrTemp to 1 if the srcClock_Hz can not satisfy the desired baud rate */ if (sbrTemp == 0U) { sbrTemp = 1U; @@ -311,6 +313,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t { /* For MISRA 15.7 */ } + /* Calculate the baud rate based on the temporary OSR and SBR values */ calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp)); tempDiff = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) : @@ -320,7 +323,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t { baudDiff = tempDiff; osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ + sbr = (uint16_t)sbrTemp; /* update store the best SBR value calculated */ } } @@ -619,9 +622,10 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s status_t status = kStatus_Success; uint32_t temp, oldCtrl; - uint16_t sbr, sbrTemp; + uint16_t sbr; uint8_t osr, osrTemp; uint32_t tempDiff, calculatedBaud, baudDiff; + uint64_t sbrTemp; /* This LPUART instantiation uses a slightly different baud rate calculation * The idea is to use the best OSR (over-sampling rate) possible @@ -634,9 +638,10 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s sbr = 0U; for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) { - /* calculate the temporary sbr value */ - sbrTemp = (uint16_t)((srcClock_Hz * 2U / (baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + /* Calculate the temporary sbr value */ + sbrTemp = ((((uint64_t)srcClock_Hz * 2U) / ((uint64_t)baudRate_Bps * (uint64_t)osrTemp)) + 1U) / 2U; + + /* Set sbrTemp to 1 if the srcClock_Hz can not satisfy the desired baud rate */ if (sbrTemp == 0U) { sbrTemp = 1U; @@ -659,7 +664,7 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s { baudDiff = tempDiff; osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ + sbr = (uint16_t)sbrTemp; /* update store the best SBR value calculated */ } } @@ -1183,8 +1188,9 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) uint32_t waitTimes; #endif - while (0U != (length--)) + while (0U != length) { + length--; #if UART_RETRY_TIMES waitTimes = UART_RETRY_TIMES; #endif @@ -1293,8 +1299,9 @@ status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t leng uint32_t waitTimes; #endif - while (0U != (length--)) + while (0U != length) { + length--; #if UART_RETRY_TIMES waitTimes = UART_RETRY_TIMES; #endif diff --git a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/fsl_lpuart.h b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/fsl_lpuart.h index 90f541fa6..06e7bb73f 100644 --- a/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/fsl_lpuart.h +++ b/mcux/mcux-sdk-ng/drivers/lpflexcomm/lpuart/fsl_lpuart.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief LPUART driver version. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 3, 4)) /*! @} */ /*! @brief Retry times for waiting flag. */ diff --git a/mcux/mcux-sdk-ng/drivers/lpi2c/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/lpi2c/CMakeLists.txt index 8aafbbfe4..fe911fa66 100644 --- a/mcux/mcux-sdk-ng/drivers/lpi2c/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/lpi2c/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause @@ -12,7 +12,7 @@ if(CONFIG_MCUX_COMPONENT_driver.lpi2c_edma) endif() if(CONFIG_MCUX_COMPONENT_driver.lpi2c) - mcux_component_version(2.6.1) + mcux_component_version(2.6.2) mcux_add_source(SOURCES fsl_lpi2c.c fsl_lpi2c.h) diff --git a/mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.c b/mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.c index a3c805577..5c5592f86 100644 --- a/mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.c +++ b/mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.c @@ -112,8 +112,10 @@ static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance); * @param base The I2C peripheral base address. * @param handle Master nonblocking driver handle. * @param variable_set Pass the address of the parent function variable. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_Timeout */ -static void LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, +static status_t LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_state_machine_param_t *stateParams); @@ -1210,7 +1212,7 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, #endif } -static void LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, +static status_t LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_state_machine_param_t *stateParams) { @@ -1222,7 +1224,7 @@ static void LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, if (0U == (stateParams->txCount)--) { stateParams->state_complete = true; - return; + return kStatus_Success; } /* Issue command. buf is a uint8_t* pointing at the uint16 command array. */ @@ -1253,6 +1255,10 @@ static void LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, while (tmpRxSize != 0U) { LPI2C_MasterGetFifoCounts(base, NULL, &stateParams->txCount); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif /* * $Branch Coverage Justification$ * The transmission commands will not exceed FIFO SIZE.(will improve) @@ -1260,6 +1266,13 @@ static void LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, while ((size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base) == stateParams->txCount) { LPI2C_MasterGetFifoCounts(base, NULL, &stateParams->txCount); + +#if I2C_RETRY_TIMES != 0U + if (--waitTimes == 0U) + { + return kStatus_LPI2C_Timeout; + } +#endif } if (tmpRxSize > 256U) @@ -1281,6 +1294,8 @@ static void LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, handle->state = (uint8_t)kStopState; } } + + return kStatus_Success; } static void LPI2C_TransferStateMachineReadCommand(LPI2C_Type *base, @@ -1419,6 +1434,7 @@ static void LPI2C_TransferStateMachineWaitState(LPI2C_Type *base, * @retval #kStatus_LPI2C_ArbitrationLost * @retval #kStatus_LPI2C_Nak * @retval #kStatus_LPI2C_FifoError + * @retval #kStatus_LPI2C_Timeout */ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone) { @@ -1472,7 +1488,7 @@ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_han switch (handle->state) { case (uint8_t)kSendCommandState: - LPI2C_TransferStateMachineSendCommand(base, handle, &stateParams); + result = LPI2C_TransferStateMachineSendCommand(base, handle, &stateParams); break; case (uint8_t)kIssueReadCommandState: @@ -1494,6 +1510,11 @@ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_han assert(false); break; } + + if (result != kStatus_Success) + { + break; + } } } return result; diff --git a/mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.h b/mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.h index 6eeaba5d0..aff24a8c2 100644 --- a/mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.h +++ b/mcux/mcux-sdk-ng/drivers/lpi2c/fsl_lpi2c.h @@ -26,13 +26,17 @@ * @{ */ /*! @brief LPI2C driver version. */ -#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 6, 1)) +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 6, 2)) /*! @} */ /*! @brief Retry times for waiting flag. */ #ifndef I2C_RETRY_TIMES +#ifdef CONFIG_I2C_RETRY_TIMES +#define I2C_RETRY_TIMES CONFIG_I2C_RETRY_TIMES +#else #define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ #endif +#endif /*! @brief LPI2C status return codes. */ enum diff --git a/mcux/mcux-sdk-ng/drivers/lpit/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/lpit/CMakeLists.txt index e812b25ea..a3fd423bb 100644 --- a/mcux/mcux-sdk-ng/drivers/lpit/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/lpit/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.lpit) - mcux_component_version(2.1.1) + mcux_component_version(2.1.2) mcux_add_source(SOURCES fsl_lpit.c fsl_lpit.h) diff --git a/mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.c b/mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.c index f5e29dc33..85982a1d9 100644 --- a/mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.c +++ b/mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.c @@ -122,7 +122,7 @@ void LPIT_Init(LPIT_Type *base, const lpit_config_t *config) /* Setup timer operation in debug and doze modes and enable the module */ base->MCR = - (LPIT_MCR_DBG_EN(config->enableRunInDebug) | LPIT_MCR_DOZE_EN(config->enableRunInDoze) | LPIT_MCR_M_CEN_MASK); + (LPIT_MCR_DBG_EN(config->enableRunInDebug ? 1U : 0U) | LPIT_MCR_DOZE_EN(config->enableRunInDoze ? 1U : 0U) | LPIT_MCR_M_CEN_MASK); } /*! @@ -199,9 +199,9 @@ status_t LPIT_SetupChannel(LPIT_Type *base, lpit_chnl_t channel, const lpit_chnl /* Setup the channel counters operation mode, trigger operation, chain mode */ reg = (LPIT_TCTRL_MODE(chnlSetup->timerMode) | LPIT_TCTRL_TRG_SRC(chnlSetup->triggerSource) | - LPIT_TCTRL_TRG_SEL(chnlSetup->triggerSelect) | LPIT_TCTRL_TROT(chnlSetup->enableReloadOnTrigger) | - LPIT_TCTRL_TSOI(chnlSetup->enableStopOnTimeout) | LPIT_TCTRL_TSOT(chnlSetup->enableStartOnTrigger) | - LPIT_TCTRL_CHAIN(chnlSetup->chainChannel)); + LPIT_TCTRL_TRG_SEL(chnlSetup->triggerSelect) | LPIT_TCTRL_TROT(chnlSetup->enableReloadOnTrigger ? 1U : 0U) | + LPIT_TCTRL_TSOI(chnlSetup->enableStopOnTimeout ? 1U : 0U) | LPIT_TCTRL_TSOT(chnlSetup->enableStartOnTrigger ? 1U : 0U) | + LPIT_TCTRL_CHAIN(chnlSetup->chainChannel ? 1U : 0U)); base->CHANNEL[channel].TCTRL = reg; } diff --git a/mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.h b/mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.h index 4cfe2c0ea..9006c1703 100644 --- a/mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.h +++ b/mcux/mcux-sdk-ng/drivers/lpit/fsl_lpit.h @@ -21,7 +21,7 @@ /*! @name Driver version */ /*! @{ */ -#define FSL_LPIT_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ +#define FSL_LPIT_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */ /*! @{ */ /*! @brief Delay used in LPIT_Reset * diff --git a/mcux/mcux-sdk-ng/drivers/lpspi/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/lpspi/CMakeLists.txt index 58811358b..a6ad3f5b7 100644 --- a/mcux/mcux-sdk-ng/drivers/lpspi/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/lpspi/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.lpspi_edma) - mcux_component_version(2.4.6) + mcux_component_version(2.4.9) mcux_add_source(SOURCES fsl_lpspi_edma.h fsl_lpspi_edma.c) @@ -12,7 +12,7 @@ if(CONFIG_MCUX_COMPONENT_driver.lpspi_edma) endif() if(CONFIG_MCUX_COMPONENT_driver.lpspi) - mcux_component_version(2.7.1) + mcux_component_version(2.7.3) mcux_add_source(SOURCES fsl_lpspi.c fsl_lpspi.h) diff --git a/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.c b/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.c index 9bdeecc83..c968ef6d0 100644 --- a/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.c +++ b/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.c @@ -242,6 +242,11 @@ uint32_t LPSPI_GetInstance(LPSPI_Type *base) uint8_t instance = 0; /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_lpspiBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ for (instance = 0; instance < ARRAY_SIZE(s_lpspiBases); instance++) { if (MSDK_REG_SECURE_ADDR(s_lpspiBases[instance]) == MSDK_REG_SECURE_ADDR(base)) @@ -320,7 +325,7 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi #if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) LPSPI_CFGR1_PCSCFG(masterConfig->pcsFunc) | #endif - LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay); + LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE(masterConfig->enableInputDelay ? 1U : 0U); if ((masterConfig->pinCfg == kLPSPI_SdiInSdiOut) || (masterConfig->pinCfg == kLPSPI_SdoInSdoOut)) { @@ -836,6 +841,7 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, /* write the best scaler value for the delay */ LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay); + assert(bestDelay <= UINT32_MAX); /* return the actual calculated delay value (in ns) */ return (uint32_t)bestDelay; } @@ -1003,6 +1009,10 @@ static bool LPSPI_MasterTransferWriteAllTxData(LPSPI_Type *base, } else { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ if (!LPSPI_WaitTxFifoEmpty(base)) { return false; @@ -1039,13 +1049,23 @@ static bool LPSPI_MasterTransferWriteAllTxData(LPSPI_Type *base, */ if (((stateParams->rxData) != NULL) && ((stateParams->rxRemainingByteCount) != 0U)) { +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; +#endif /* To ensure parallel execution in 3-wire mode, after writting 1 to TXMSK to generate clock of bytesPerFrame's data wait until bytesPerFrame's data is received. */ while ((stateParams->isTxMask) && (LPSPI_GetRxFifoCount(base) == 0U)) { +#if SPI_RETRY_TIMES + if (--waitTimes == 0U) + { + return false; + } +#endif } + #if SPI_RETRY_TIMES - uint32_t waitTimes = SPI_RETRY_TIMES; + waitTimes = SPI_RETRY_TIMES; while ((LPSPI_GetRxFifoCount(base) != 0U) && (--waitTimes != 0U)) #else while (LPSPI_GetRxFifoCount(base) != 0U) @@ -1177,16 +1197,16 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf assert(transfer != NULL); /* Check that LPSPI is not busy.*/ - /* - * $Branch Coverage Justification$ - * MBF state setting and clearing is done by hardware, the state is too fast to be overwritten.(will improve) - */ if ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ModuleBusyFlag) != 0U) { return kStatus_LPSPI_Busy; } /* Check the SR[MBF] again - workaround for ERR010655 */ + /* + * $Branch Coverage Justification$ + * Depends on errata. + */ if ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ModuleBusyFlag) != 0U) { return kStatus_LPSPI_Busy; @@ -1516,6 +1536,10 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t */ base->TCR = LPSPI_GetTcr(base) | LPSPI_TCR_TXMSK_MASK; handle->txRemainingByteCount -= (uint32_t)handle->bytesPerFrame; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ if (!LPSPI_WaitTxFifoEmpty(base)) { return kStatus_LPSPI_Timeout; @@ -1806,6 +1830,10 @@ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *hand } else { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ if (!LPSPI_WaitTxFifoEmpty(base)) { return; @@ -2012,7 +2040,7 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * /*TCR is also shared the FIFO, so wait for TCR written.*/ /* * $Branch Coverage Justification$ - * $ref fsl_lpspi_c_ref_3$ + * $ref fsl_lpspi_c_ref_2$ */ if (!LPSPI_WaitTxFifoEmpty(base)) { diff --git a/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.h b/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.h index 8d7369f70..4026e6242 100644 --- a/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.h +++ b/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief LPSPI driver version. */ -#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 7, 1)) +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 7, 3)) /*! @} */ #ifndef LPSPI_DUMMY_DATA @@ -32,8 +32,12 @@ /*! @brief Retry times for waiting flag. */ #ifndef SPI_RETRY_TIMES +#ifdef CONFIG_SPI_RETRY_TIMES +#define SPI_RETRY_TIMES CONFIG_SPI_RETRY_TIMES +#else #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ #endif +#endif /*! @brief Global variable for dummy data value setting. */ extern volatile uint8_t g_lpspiDummyData[]; @@ -884,7 +888,7 @@ static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flus LPSPI_Enable(base, enabled); #else - base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT); + base->CR |= ((flushTxFifo ? 1U : 0U) << LPSPI_CR_RTF_SHIFT) | ((flushRxFifo ? 1U : 0U) << LPSPI_CR_RRF_SHIFT); #endif } diff --git a/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi_edma.c b/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi_edma.c index 7e235e3b1..57fe0c8f2 100644 --- a/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi_edma.c +++ b/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi_edma.c @@ -14,6 +14,12 @@ * $Justification fsl_lpspi_edma_c_ref_1$ * The default branch cannot be executed in any circumstances, it is only added to avoid MISRA violation. * + * $Justification fsl_lpspi_edma_c_ref_2$ + * Depends on configuration of macro SPI_RETRY_TIMES. + * + * $Justification fsl_lpspi_edma_c_ref_3$ + * The fifosize is determined by the hardware. + * */ /*********************************************************************************************************************** * Definitions @@ -24,8 +30,11 @@ #define FSL_COMPONENT_ID "platform.drivers.lpspi_edma" #endif +/* @brief Mask to align an address to edma_tcd_t size. */ +#define LPSPI_ALIGN_TCD_SIZE_MASK (sizeof(edma_tcd_t) - 1U) + /*! - * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. + * @brief Structure definition for lpspi_master_edma_private_handle_t. The structure is private. */ typedef struct _lpspi_master_edma_private_handle { @@ -34,7 +43,7 @@ typedef struct _lpspi_master_edma_private_handle } lpspi_master_edma_private_handle_t; /*! - * @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. + * @brief Structure definition for lpspi_slave_edma_private_handle_t. The structure is private. */ typedef struct _lpspi_slave_edma_private_handle { @@ -119,19 +128,6 @@ static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint3 } break; - case 4: - - *rxData = (uint8_t)readData; - ++rxData; - *rxData = (uint8_t)(readData >> 8); - ++rxData; - *rxData = (uint8_t)(readData >> 16); - ++rxData; - *rxData = (uint8_t)(readData >> 24); - ++rxData; - - break; - default: assert(false); break; @@ -236,6 +232,10 @@ status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma handle->isByteSwap = isByteSwap; handle->isThereExtraRxBytes = false; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_3$ + */ if (handle->fifoSize >= 1U) { LPSPI_SetFifoWatermarks(base, handle->fifoSize - 1U, 0U); @@ -323,8 +323,8 @@ status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle uint32_t bytesPerFrame = ((LPSPI_GetTcr(base) & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; edma_transfer_config_t transferConfigRx = {0}; edma_transfer_config_t transferConfigTx = {0}; - edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); - edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~LPSPI_ALIGN_TCD_SIZE_MASK)); + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~LPSPI_ALIGN_TCD_SIZE_MASK)); if (transfer->dataSize <= bytesPerFrame) { @@ -630,9 +630,13 @@ status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle if (handle->isMultiDMATransmit) { transferConfigTx.majorLoopCounts = handle->dataBytesEveryTime; + /* + * $Branch Coverage Justification$ + * Pcs-continuous mode is not supported in Multi DMA transfer. + */ if (handle->isPcsContinuous) { - /* Pcs-continue mode is not supported in Multi DMA. + /* Pcs-continuous mode is not supported in Multi DMA. Please use no-continue mode and use GPIO control CS pin*/ LPSPI_SetPCSContinous(base, false); assert(false); @@ -774,8 +778,18 @@ static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, /* Once DMA transfer */ if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) { +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; +#endif while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U) { +#if SPI_RETRY_TIMES + if (--waitTimes == 0U) + { + callbackStatus = kStatus_LPSPI_Timeout; + break; + } +#endif } readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); if (lpspiEdmaPrivateHandle->handle->rxData != NULL) @@ -954,7 +968,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha uint32_t bytesPerFrame = ((LPSPI_GetTcr(base) & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; edma_transfer_config_t transferConfigRx = {0}; edma_transfer_config_t transferConfigTx = {0}; - edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~LPSPI_ALIGN_TCD_SIZE_MASK)); /* Assign the original value for members of transfer handle. */ handle->state = (uint8_t)kLPSPI_Busy; @@ -972,6 +986,10 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha handle->isByteSwap = isByteSwap; handle->isThereExtraRxBytes = false; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_3$ + */ if (handle->fifoSize >= 1U) { LPSPI_SetFifoWatermarks(base, handle->fifoSize - 1U, 0U); @@ -995,6 +1013,10 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha if (transfer->txData == NULL) { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_2$ + */ if (!LPSPI_WaitTxFifoEmpty(base)) { return kStatus_LPSPI_Error; @@ -1095,7 +1117,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; - /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ + /* Store the initially configured eDMA minor byte transfer count into the LPSPI handle */ handle->nbytes = (uint8_t)transferConfigRx.minorLoopBytes; EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, @@ -1250,15 +1272,20 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, callbackStatus = kStatus_LPSPI_Error; } - /* - * $Branch Coverage Justification$ - * When there are extra bytes, the slave will not receive the extra bytes,The while here will not stop.(will - * improve) - */ if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) { +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; +#endif while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U) { +#if SPI_RETRY_TIMES + if (--waitTimes == 0U) + { + callbackStatus = kStatus_LPSPI_Timeout; + break; + } +#endif } readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); diff --git a/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi_edma.h b/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi_edma.h index a8481db61..5d2acb64b 100644 --- a/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi_edma.h +++ b/mcux/mcux-sdk-ng/drivers/lpspi/fsl_lpspi_edma.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief LPSPI EDMA driver version. */ -#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 6)) +#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 9)) /*! @brief DMA max transfer size */ #define DMA_MAX_TRANSFER_COUNT 0x7FFFU diff --git a/mcux/mcux-sdk-ng/drivers/lptmr/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/lptmr/CMakeLists.txt index 6403512bd..dd9f63eb3 100644 --- a/mcux/mcux-sdk-ng/drivers/lptmr/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/lptmr/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.lptmr) - mcux_component_version(2.2.0) + mcux_component_version(2.2.1) mcux_add_source(SOURCES fsl_lptmr.c fsl_lptmr.h) diff --git a/mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.c b/mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.c index 06abcbe20..01ed7ecc6 100644 --- a/mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.c +++ b/mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -13,10 +13,14 @@ #define FSL_COMPONENT_ID "platform.drivers.lptmr" #endif +#if (defined(LPTMR_CLOCKS) && !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define LPTMR_DRIVER_CLK_CTRL 1 +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ -#if defined(LPTMR_CLOCKS) +#if defined(LPTMR_DRIVER_CLK_CTRL) /*! * @brief Gets the instance from the base address to be used to gate or ungate the module clock * @@ -25,16 +29,16 @@ * @return The LPTMR instance */ static uint32_t LPTMR_GetInstance(LPTMR_Type *base); -#endif /* LPTMR_CLOCKS */ +#endif /* LPTMR_DRIVER_CLK_CTRL */ /******************************************************************************* * Variables ******************************************************************************/ -#if defined(LPTMR_CLOCKS) +#if defined(LPTMR_DRIVER_CLK_CTRL) + /*! @brief Pointers to LPTMR bases for each instance. */ static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /*! @brief Pointers to LPTMR clocks for each instance. */ static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS; @@ -43,13 +47,12 @@ static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS; static const clock_ip_name_t s_lptmrPeriphClocks[] = LPTMR_PERIPH_CLOCKS; #endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* LPTMR_CLOCKS */ +#endif /* LPTMR_DRIVER_CLK_CTRL */ /******************************************************************************* * Code ******************************************************************************/ -#if defined(LPTMR_CLOCKS) +#if defined(LPTMR_DRIVER_CLK_CTRL) static uint32_t LPTMR_GetInstance(LPTMR_Type *base) { uint32_t instance; @@ -67,7 +70,7 @@ static uint32_t LPTMR_GetInstance(LPTMR_Type *base) return instance; } -#endif /* LPTMR_CLOCKS */ +#endif /* LPTMR_DRIVER_CLK_CTRL */ /*! * brief Ungates the LPTMR clock and configures the peripheral for a basic operation. @@ -81,9 +84,7 @@ void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) { assert(NULL != config); -#if defined(LPTMR_CLOCKS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - +#if defined(LPTMR_DRIVER_CLK_CTRL) uint32_t instance = LPTMR_GetInstance(base); /* Ungate the LPTMR clock*/ @@ -91,16 +92,14 @@ void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) #if defined(LPTMR_PERIPH_CLOCKS) CLOCK_EnableClock(s_lptmrPeriphClocks[instance]); #endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* LPTMR_CLOCKS */ +#endif /* LPTMR_DRIVER_CLK_CTRL */ /* Configure the timers operation mode and input pin setup */ - base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | + base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning ? 1U : 0U) | LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); /* Configure the prescale value and clock source */ - base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | + base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler ? 1U : 0U) | LPTMR_PSR_PCS(config->prescalerClockSource)); } @@ -114,8 +113,7 @@ void LPTMR_Deinit(LPTMR_Type *base) /* Disable the LPTMR and reset the internal logic */ base->CSR &= ~LPTMR_CSR_TEN_MASK; -#if defined(LPTMR_CLOCKS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(LPTMR_DRIVER_CLK_CTRL) uint32_t instance = LPTMR_GetInstance(base); @@ -125,8 +123,7 @@ void LPTMR_Deinit(LPTMR_Type *base) CLOCK_DisableClock(s_lptmrPeriphClocks[instance]); #endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* LPTMR_CLOCKS */ +#endif /* LPTMR_DRIVER_CLK_CTRL */ } /*! diff --git a/mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.h b/mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.h index b8e473120..1fbe29d53 100644 --- a/mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.h +++ b/mcux/mcux-sdk-ng/drivers/lptmr/fsl_lptmr.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2023 NXP + * Copyright 2016-2017, 2023, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! Driver Version */ -#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*! @} */ /*! @brief LPTMR pin selection used in pulse counter mode.*/ @@ -300,12 +300,11 @@ static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) * 2. Call the utility macros provided in the fsl_common.h to convert to ticks. * * @param base LPTMR peripheral base address - * @param ticks A timer period in units of ticks, which should be equal or greater than 1. + * @param ticks A timer period in units of ticks */ static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks) { - assert(ticks > 0U); - base->CMR = LPTMR_CMR_COMPARE(ticks - 1U); + base->CMR = LPTMR_CMR_COMPARE((ticks - 1U) & LPTMR_CMR_COMPARE_MASK); } /*! diff --git a/mcux/mcux-sdk-ng/drivers/lpuart/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/lpuart/CMakeLists.txt index 925470704..e2c7a4a90 100644 --- a/mcux/mcux-sdk-ng/drivers/lpuart/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/lpuart/CMakeLists.txt @@ -21,7 +21,7 @@ if(CONFIG_MCUX_COMPONENT_driver.lpuart_edma) endif() if(CONFIG_MCUX_COMPONENT_driver.lpuart) - mcux_component_version(2.9.1) + mcux_component_version(2.10.0) mcux_add_source(SOURCES fsl_lpuart.h fsl_lpuart.c) diff --git a/mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.c b/mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.c index a888f8023..0ddd75b03 100644 --- a/mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.c +++ b/mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.c @@ -139,6 +139,24 @@ static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_ */ static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle); +/*! + * @brief Wait for read data availability and check for errors. + * + * This function polls the receiver register/FIFO and waits for data to be available. + * It monitors and handles RX error conditions including overrun, parity, framing, + * and noise errors during the wait period. + * + * @param base LPUART peripheral base address. + * @retval kStatus_Success Data available, no errors. + * @retval kStatus_LPUART_Timeout Timeout waiting for data. + * @retval kStatus_LPUART_RxHardwareOverrun RX overrun error. + * @retval kStatus_LPUART_ParityError Parity error. + * @retval kStatus_LPUART_FramingError Framing error. + * @retval kStatus_LPUART_NoiseError Noise error. + * @retval kStatus_LPUART_FlagCannotClearManually Error flag cannot be cleared. + */ +static status_t LPUART_WaitForReadData(LPUART_Type *base); + /******************************************************************************* * Variables ******************************************************************************/ @@ -197,11 +215,16 @@ uint32_t LPUART_GetInstance(LPUART_Type *base) uint32_t instance; /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_lpuartBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ for (instance = 0U; instance < ARRAY_SIZE(s_lpuartBases); instance++) { if (MSDK_REG_SECURE_ADDR(s_lpuartBases[instance]) == MSDK_REG_SECURE_ADDR(base)) { - return instance; + break; } } @@ -267,6 +290,7 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size base->DATA = data[i]; } } + static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) { assert(NULL != data); @@ -360,9 +384,10 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t status_t status = kStatus_Success; uint32_t temp; - uint16_t sbr, sbrTemp; + uint16_t sbr; uint8_t osr, osrTemp; uint32_t tempDiff, calculatedBaud, baudDiff; + uint64_t sbrTemp; /* This LPUART instantiation uses a slightly different baud rate calculation * The idea is to use the best OSR (over-sampling rate) possible @@ -375,9 +400,10 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t sbr = 0U; for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) { - /* calculate the temporary sbr value */ - sbrTemp = (uint16_t)((srcClock_Hz * 2U / (config->baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + /* Calculate the temporary sbr value */ + sbrTemp = ((((uint64_t)srcClock_Hz * 2U) / ((uint64_t)config->baudRate_Bps * (uint64_t)osrTemp)) + 1U) / 2U; + + /* Set sbrTemp to 1 if the srcClock_Hz can not satisfy the desired baud rate */ if (sbrTemp == 0U) { sbrTemp = 1U; @@ -390,6 +416,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t { /* Avoid MISRA 15.7 */ } + /* Calculate the baud rate based on the temporary OSR and SBR values */ calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp)); tempDiff = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) : @@ -399,7 +426,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t { baudDiff = tempDiff; osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ + sbr = (uint16_t)sbrTemp; /* update store the best SBR value calculated */ } } @@ -550,6 +577,10 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t /* Enable the CTS(clear-to-send) function. */ base->MODIR |= LPUART_MODIR_TXCTSE_MASK; } +#if defined(FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER) && FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER + base->MODIR &= ~LPUART_MODIR_RTSWATER_MASK; + base->MODIR |= LPUART_MODIR_RTSWATER(config->rtsWatermark); +#endif #endif /* Set data bits order. */ @@ -587,20 +618,41 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. * * param base LPUART peripheral base address. + * retval kStatus_Success Deinit is success. + * retval kStatus_LPUART_Timeout Timeout during deinit. */ -void LPUART_Deinit(LPUART_Type *base) +status_t LPUART_Deinit(LPUART_Type *base) { uint32_t temp; +#if UART_RETRY_TIMES + uint32_t waitTimes = UART_RETRY_TIMES; +#endif #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Wait tx FIFO send out*/ + /* Wait tx FIFO send out */ while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) { +#if UART_RETRY_TIMES + if (--waitTimes == 0U) + { + return kStatus_LPUART_Timeout; + } +#endif } #endif + +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif /* Wait last char shift out */ while (0U == (base->STAT & LPUART_STAT_TC_MASK)) { +#if UART_RETRY_TIMES + if (--waitTimes == 0U) + { + return kStatus_LPUART_Timeout; + } +#endif } /* Clear all status flags */ @@ -631,6 +683,8 @@ void LPUART_Deinit(LPUART_Type *base) #endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + return kStatus_Success; } /*! @@ -675,6 +729,9 @@ void LPUART_GetDefaultConfig(lpuart_config_t *config) config->enableTxCTS = false; config->txCtsConfig = kLPUART_CtsSampleAtStart; config->txCtsSource = kLPUART_CtsSourcePin; +#if defined(FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER) && FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER + config->rtsWatermark = 0U; +#endif #endif config->rxIdleType = kLPUART_IdleTypeStartBit; config->rxIdleConfig = kLPUART_IdleCharacter1; @@ -706,9 +763,10 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s status_t status = kStatus_Success; uint32_t temp, oldCtrl; - uint16_t sbr, sbrTemp; + uint16_t sbr; uint8_t osr, osrTemp; uint32_t tempDiff, calculatedBaud, baudDiff; + uint64_t sbrTemp; /* This LPUART instantiation uses a slightly different baud rate calculation * The idea is to use the best OSR (over-sampling rate) possible @@ -721,9 +779,10 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s sbr = 0U; for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) { - /* calculate the temporary sbr value */ - sbrTemp = (uint16_t)((srcClock_Hz * 2U / (baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + /* Calculate the temporary sbr value */ + sbrTemp = ((((uint64_t)srcClock_Hz * 2U) / ((uint64_t)baudRate_Bps * (uint64_t)osrTemp)) + 1U) / 2U; + + /* Set sbrTemp to 1 if the srcClock_Hz can not satisfy the desired baud rate */ if (sbrTemp == 0U) { sbrTemp = 1U; @@ -736,6 +795,7 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s { /* Avoid MISRA 15.7 */ } + /* Calculate the baud rate based on the temporary OSR and SBR values */ calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp); @@ -745,7 +805,7 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s { baudDiff = tempDiff; osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ + sbr = (uint16_t)sbrTemp; /* update store the best SBR value calculated */ } } @@ -1135,6 +1195,7 @@ status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t len #endif return kStatus_Success; } + /*! * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. * @@ -1196,6 +1257,87 @@ status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size return kStatus_Success; } +static status_t LPUART_WaitForReadData(LPUART_Type *base) +{ + status_t status = kStatus_Success; + uint32_t statusFlag; + +#if UART_RETRY_TIMES + uint32_t waitTimes = UART_RETRY_TIMES; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { + +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (kStatus_Success != status) + { + break; + } + } + + return status; +} + /*! * brief Reads the receiver data register using a blocking method. * @@ -1217,7 +1359,6 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) assert(NULL != data); status_t status = kStatus_Success; - uint32_t statusFlag; uint8_t *dataAddress = data; #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT @@ -1226,82 +1367,11 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); #endif -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - - while (0U != (length--)) + while (0U != length) { -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) -#else - while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) -#endif - { -#if UART_RETRY_TIMES - if (0U == --waitTimes) - { - status = kStatus_LPUART_Timeout; - break; - } -#endif - statusFlag = LPUART_GetStatusFlags(base); - - if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) - { - /* - * $Branch Coverage Justification$ - * $ref fsl_lpuart_c_ref_2$. - */ - status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? - (kStatus_LPUART_RxHardwareOverrun) : - (kStatus_LPUART_FlagCannotClearManually)); - /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other - * error flags*/ - break; - } - - if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) - { - /* - * $Branch Coverage Justification$ - * $ref fsl_lpuart_c_ref_2$. - */ - status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? - (kStatus_LPUART_ParityError) : - (kStatus_LPUART_FlagCannotClearManually)); - } - - if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) - { - /* - * $Branch Coverage Justification$ - * $ref fsl_lpuart_c_ref_2$. - */ - status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? - (kStatus_LPUART_FramingError) : - (kStatus_LPUART_FlagCannotClearManually)); - } - - if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) - { - /* - * $Branch Coverage Justification$ - * $ref fsl_lpuart_c_ref_2$. - */ - status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? - (kStatus_LPUART_NoiseError) : - (kStatus_LPUART_FlagCannotClearManually)); - } - if (kStatus_Success != status) - { - break; - } - } + length--; + status = LPUART_WaitForReadData(base); if (kStatus_Success == status) { #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT @@ -1328,6 +1398,7 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) return status; } + /*! * brief Reads the receiver data register in 9bit or 10bit mode. * @@ -1348,84 +1419,13 @@ status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t leng assert(NULL != data); status_t status = kStatus_Success; - uint32_t statusFlag; uint16_t *dataAddress = data; -#if UART_RETRY_TIMES - uint32_t waitTimes; -#endif - - while (0U != (length--)) + while (0U != length) { -#if UART_RETRY_TIMES - waitTimes = UART_RETRY_TIMES; -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) -#else - while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) -#endif - { -#if UART_RETRY_TIMES - if (0U == --waitTimes) - { - status = kStatus_LPUART_Timeout; - break; - } -#endif - statusFlag = LPUART_GetStatusFlags(base); - - if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) - { - /* - * $Branch Coverage Justification$ - * $ref fsl_lpuart_c_ref_2$. - */ - status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? - (kStatus_LPUART_RxHardwareOverrun) : - (kStatus_LPUART_FlagCannotClearManually)); - /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other - * error flags*/ - break; - } - - if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) - { - /* - * $Branch Coverage Justification$ - * $ref fsl_lpuart_c_ref_2$. - */ - status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? - (kStatus_LPUART_ParityError) : - (kStatus_LPUART_FlagCannotClearManually)); - } + length--; - if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) - { - /* - * $Branch Coverage Justification$ - * $ref fsl_lpuart_c_ref_2$. - */ - status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? - (kStatus_LPUART_FramingError) : - (kStatus_LPUART_FlagCannotClearManually)); - } - - if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) - { - /* - * $Branch Coverage Justification$ - * $ref fsl_lpuart_c_ref_2$. - */ - status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? - (kStatus_LPUART_NoiseError) : - (kStatus_LPUART_FlagCannotClearManually)); - } - if (kStatus_Success != status) - { - break; - } - } + status = LPUART_WaitForReadData(base); if (kStatus_Success == status) { *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU); diff --git a/mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.h b/mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.h index 3cd3943d6..0171e2b43 100644 --- a/mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.h +++ b/mcux/mcux-sdk-ng/drivers/lpuart/fsl_lpuart.h @@ -21,13 +21,17 @@ /*! @name Driver version */ /*! @{ */ /*! @brief LPUART driver version. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 9, 1)) +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 10, 0)) /*! @} */ /*! @brief Retry times for waiting flag. */ #ifndef UART_RETRY_TIMES +#ifdef CONFIG_UART_RETRY_TIMES +#define UART_RETRY_TIMES CONFIG_UART_RETRY_TIMES +#else #define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ #endif +#endif /*! @brief Error codes for the LPUART driver. */ enum @@ -254,6 +258,9 @@ typedef struct _lpuart_config bool enableTxCTS; /*!< TX CTS enable */ lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#if defined(FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER) && FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER + uint8_t rtsWatermark; /*!< RTS watermark */ +#endif #endif lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ @@ -414,8 +421,10 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. * * @param base LPUART peripheral base address. + * @retval kStatus_Success Deinit is success. + * @retval kStatus_LPUART_Timeout Timeout during deinit. */ -void LPUART_Deinit(LPUART_Type *base); +status_t LPUART_Deinit(LPUART_Type *base); /*! * @brief Gets the default configuration structure. diff --git a/mcux/mcux-sdk-ng/drivers/mailbox/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/mailbox/CMakeLists.txt index 844502bcb..d9569e3ae 100644 --- a/mcux/mcux-sdk-ng/drivers/mailbox/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/mailbox/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.mailbox) - mcux_component_version(2.3.2) + mcux_component_version(2.3.4) mcux_add_source(SOURCES fsl_mailbox.h) diff --git a/mcux/mcux-sdk-ng/drivers/mailbox/fsl_mailbox.h b/mcux/mcux-sdk-ng/drivers/mailbox/fsl_mailbox.h index 7253914ab..de2131c3c 100644 --- a/mcux/mcux-sdk-ng/drivers/mailbox/fsl_mailbox.h +++ b/mcux/mcux-sdk-ng/drivers/mailbox/fsl_mailbox.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP + * Copyright 2016-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,7 +29,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief MAILBOX driver version */ -#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) +#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 3, 4)) /*! @} */ /*! @@ -51,7 +51,12 @@ typedef enum _mailbox_cpu_id #elif (defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \ defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \ - defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES)) + defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ + defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) || \ + defined(MCXN537_cm33_core0_SERIES) || defined(MCXN537_cm33_core1_SERIES) || \ + defined(MCXN536_cm33_core0_SERIES) || defined(MCXN536_cm33_core1_SERIES) || \ + defined(MCXN527_cm33_core0_SERIES) || defined(MCXN527_cm33_core1_SERIES) || \ + defined(MCXN526_cm33_core0_SERIES) || defined(MCXN526_cm33_core1_SERIES)) typedef enum _mailbox_cpu_id { kMAILBOX_CM33_Core0 = 0, @@ -59,17 +64,6 @@ typedef enum _mailbox_cpu_id } mailbox_cpu_id_t; #endif -#if (defined(CPU_NXH2004J640UK48)) -typedef enum _mailbox_id -{ - kMAILBOX_CM0Plus_Core0 = 0, - kMAILBOX_CM0Plus_Core1, - kMAILBOX_CM0Plus_Sw_Irq0, - kMAILBOX_CM0Plus_Sw_Irq1, - kMAILBOX_CM0Plus_Sw_Irq2, - kMAILBOX_CM0Plus_Sw_Irq3 -} mailbox_id_t; -#endif /******************************************************************************* * API ******************************************************************************/ @@ -123,6 +117,11 @@ static inline void MAILBOX_Deinit(MAILBOX_Type *base) defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \ defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ + defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) || \ + defined(MCXN537_cm33_core0_SERIES) || defined(MCXN537_cm33_core1_SERIES) || \ + defined(MCXN536_cm33_core0_SERIES) || defined(MCXN536_cm33_core1_SERIES) || \ + defined(MCXN527_cm33_core0_SERIES) || defined(MCXN527_cm33_core1_SERIES) || \ + defined(MCXN526_cm33_core0_SERIES) || defined(MCXN526_cm33_core1_SERIES) || \ defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)) /*! * @brief Set data value in the mailbox based on the CPU ID. @@ -141,7 +140,12 @@ static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \ defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \ - defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES)) + defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ + defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) || \ + defined(MCXN537_cm33_core0_SERIES) || defined(MCXN537_cm33_core1_SERIES) || \ + defined(MCXN536_cm33_core0_SERIES) || defined(MCXN536_cm33_core1_SERIES) || \ + defined(MCXN527_cm33_core0_SERIES) || defined(MCXN527_cm33_core1_SERIES) || \ + defined(MCXN526_cm33_core0_SERIES) || defined(MCXN526_cm33_core1_SERIES)) assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); #elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); @@ -165,7 +169,12 @@ static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \ defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \ - defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES)) + defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ + defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) || \ + defined(MCXN537_cm33_core0_SERIES) || defined(MCXN537_cm33_core1_SERIES) || \ + defined(MCXN536_cm33_core0_SERIES) || defined(MCXN536_cm33_core1_SERIES) || \ + defined(MCXN527_cm33_core0_SERIES) || defined(MCXN527_cm33_core1_SERIES) || \ + defined(MCXN526_cm33_core0_SERIES) || defined(MCXN526_cm33_core1_SERIES)) assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); #elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); @@ -191,7 +200,12 @@ static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \ defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \ - defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES)) + defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ + defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) || \ + defined(MCXN537_cm33_core0_SERIES) || defined(MCXN537_cm33_core1_SERIES) || \ + defined(MCXN536_cm33_core0_SERIES) || defined(MCXN536_cm33_core1_SERIES) || \ + defined(MCXN527_cm33_core0_SERIES) || defined(MCXN527_cm33_core1_SERIES) || \ + defined(MCXN526_cm33_core0_SERIES) || defined(MCXN526_cm33_core1_SERIES)) assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); #elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); @@ -217,7 +231,12 @@ static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t c defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \ defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \ - defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES)) + defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ + defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) || \ + defined(MCXN537_cm33_core0_SERIES) || defined(MCXN537_cm33_core1_SERIES) || \ + defined(MCXN536_cm33_core0_SERIES) || defined(MCXN536_cm33_core1_SERIES) || \ + defined(MCXN527_cm33_core0_SERIES) || defined(MCXN527_cm33_core1_SERIES) || \ + defined(MCXN526_cm33_core0_SERIES) || defined(MCXN526_cm33_core1_SERIES)) assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); #elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); @@ -225,69 +244,7 @@ static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t c base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits; } -#elif (defined(CPU_NXH2004J640UK48)) - -/*! - * @brief Set data value in the mailbox based on the Mailbox ID. - * - * @param base MAILBOX peripheral base address. - * @param id Mailbox Index for NXH2004 devices - * @param mboxData Data to send in the mailbox. - * - */ -static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxData) -{ - assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); - base->MBOXIRQ[id].IRQ = mboxData; -} - -/*! - * @brief Get data in the mailbox based on the Mailbox ID. - * - * @param base MAILBOX peripheral base address. - * @param id, Mailbox index for NXH2004 devies. - * - * @return Current mailbox data. - */ -static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_id_t id) -{ - assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); - return base->MBOXIRQ[id].IRQ; -} - -/*! - * @brief Set data bits in the mailbox based on the Mailbox Index. - * - * @param base MAILBOX peripheral base address. - * @param id Mailbox Index for NXH2004 devices - * @param mboxSetBits Data bits to set in the mailbox. - * - * @note Sets data bits to send via the MAILBOX. A value of 0 will - * do nothing. Only sets bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxSetBits) -{ - assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); - base->MBOXIRQ[id].IRQSET = mboxSetBits; -} - -/*! - * @brief Clear data bits in the mailbox based on the Mailbox ID. - * - * @param base MAILBOX peripheral base address. - * @param id, Index to Mailbox for NXH2004 devices. - * @param mboxClrBits Data bits to clear in the mailbox. - * - * @note Clear data bits to send via the MAILBOX. A value of 0 will do - * nothing. Only clears bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxClrBits) -{ - assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); - base->MBOXIRQ[id].IRQCLR = mboxClrBits; -} - -#endif /*CPU_NXH2004J640UK48*/ +#endif /*! * @brief Get MUTEX state and lock mutex @@ -316,7 +273,6 @@ static inline void MAILBOX_SetMutex(MAILBOX_Type *base) { base->MUTEX = MAILBOX_MUTEX_EX_MASK; } - #if defined(__cplusplus) } #endif /*_cplusplus*/ diff --git a/mcux/mcux-sdk-ng/drivers/mau/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/mau/CMakeLists.txt index 4233c7432..e8e8e8c72 100644 --- a/mcux/mcux-sdk-ng/drivers/mau/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/mau/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.mau) - mcux_component_version(2.2.0) + mcux_component_version(2.2.2) mcux_add_source(SOURCES fsl_mau.c fsl_mau.h) diff --git a/mcux/mcux-sdk-ng/drivers/mau/fsl_mau.c b/mcux/mcux-sdk-ng/drivers/mau/fsl_mau.c index 37c425f76..c36c1f413 100644 --- a/mcux/mcux-sdk-ng/drivers/mau/fsl_mau.c +++ b/mcux/mcux-sdk-ng/drivers/mau/fsl_mau.c @@ -172,6 +172,8 @@ float arm_sin_f32(float input) */ mau_q31_t arm_sin_q31(mau_q31_t input) { + assert((input <= (mau_q31_t)INT32_MAX / 2) && (input >= (mau_q31_t)INT32_MIN / 2)); + return MAU_SinPIXQ31(MAU0, (input * 2), kMAU_RES0); } @@ -183,6 +185,8 @@ mau_q31_t arm_sin_q31(mau_q31_t input) */ mau_q15_t arm_sin_q15(mau_q15_t input) { + assert((input <= INT16_MAX / 2) && (input >= INT16_MIN / 2)); + return MAU_SinPIXQ15(MAU0, (input * 2), kMAU_RES0); } @@ -205,6 +209,8 @@ float arm_cos_f32(float input) */ mau_q31_t arm_cos_q31(mau_q31_t input) { + assert((input <= (mau_q31_t)INT32_MAX / 2) && (input >= (mau_q31_t)INT32_MIN / 2)); + return MAU_CosPIXQ31(MAU0, (input * 2), kMAU_RES0); } @@ -216,6 +222,8 @@ mau_q31_t arm_cos_q31(mau_q31_t input) */ mau_q15_t arm_cos_q15(mau_q15_t input) { + assert((input <= INT16_MAX / 2) && (input >= INT16_MIN / 2)); + return MAU_CosPIXQ15(MAU0, (input * 2), kMAU_RES0); } @@ -240,6 +248,8 @@ void arm_sin_cos_f32(float input, float *sin_val, float *cos_val) */ void arm_sin_cos_q31(mau_q31_t input, mau_q31_t *sin_val, mau_q31_t *cos_val) { + assert((input <= (mau_q31_t)INT32_MAX / 2) && (input >= (mau_q31_t)INT32_MIN / 2)); + MAU_SinCosPIXQ31(MAU0, (input * 2), sin_val, cos_val, kMAU_RES0, kMAU_RES1); } @@ -252,6 +262,8 @@ void arm_sin_cos_q31(mau_q31_t input, mau_q31_t *sin_val, mau_q31_t *cos_val) */ void arm_sin_cos_q15(mau_q15_t input, mau_q15_t *sin_val, mau_q15_t *cos_val) { + assert((input <= INT16_MAX / 2) && (input >= INT16_MIN / 2)); + MAU_SinCosPIXQ15(MAU0, (input * 2), sin_val, cos_val, kMAU_RES0, kMAU_RES1); } #endif diff --git a/mcux/mcux-sdk-ng/drivers/mau/fsl_mau.h b/mcux/mcux-sdk-ng/drivers/mau/fsl_mau.h index 443e93806..970384f49 100644 --- a/mcux/mcux-sdk-ng/drivers/mau/fsl_mau.h +++ b/mcux/mcux-sdk-ng/drivers/mau/fsl_mau.h @@ -21,7 +21,7 @@ /*! @{ */ /*! @brief MAU driver version. */ -#define FSL_MAU_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +#define FSL_MAU_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*! @} */ /*! @brief MAU Q15 type. */ diff --git a/mcux/mcux-sdk-ng/drivers/mcx_spc/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/mcx_spc/CMakeLists.txt index 41768082a..d985c31f5 100644 --- a/mcux/mcux-sdk-ng/drivers/mcx_spc/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/mcx_spc/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.mcx_spc) - mcux_component_version(2.8.0) + mcux_component_version(2.8.1) mcux_add_source(SOURCES fsl_spc.h fsl_spc.c) diff --git a/mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.c b/mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.c index 852660aaa..af257abe7 100644 --- a/mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.c +++ b/mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.c @@ -1471,7 +1471,15 @@ void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config) /* Clear DCDC burst acknowledge flag. */ base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; } - base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN(config->externalBurstRequest); + + if (config->externalBurstRequest) + { + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK; + } + else + { + base->DCDC_BURST_CFG &= ~SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK; + } if (config->sofwareBurstRequest) { diff --git a/mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.h b/mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.h index 236b247b0..c2fa73d13 100644 --- a/mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.h +++ b/mcux/mcux-sdk-ng/drivers/mcx_spc/fsl_spc.h @@ -19,8 +19,8 @@ /*! @name Driver version */ /*! @{ */ -/*! @brief SPC driver version 2.8.0. */ -#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 8, 0)) +/*! @brief SPC driver version 2.8.1. */ +#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 8, 1)) /*! @} */ #define SPC_EVD_CFG_REG_EVDISO_SHIFT 0UL @@ -1439,9 +1439,9 @@ static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base) * @param base SPC peripheral base address. * @return Voltage Detect Status Flags. See @ref _spc_voltage_detect_flags for details. */ -static inline uint8_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base) +static inline uint32_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base) { - return (uint8_t)(base->VD_STAT); + return (uint32_t)(base->VD_STAT); } /*! @@ -1836,7 +1836,9 @@ void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask */ static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base) { - return (uint8_t)(base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT); + uint32_t tmp32 = (base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT); + assert(tmp32 <= UINT8_MAX); + return (uint8_t)(tmp32); } /*! @} */ diff --git a/mcux/mcux-sdk-ng/drivers/mipi_dsi/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/mipi_dsi/CMakeLists.txt index a6f5b4aca..74d297d64 100644 --- a/mcux/mcux-sdk-ng/drivers/mipi_dsi/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/mipi_dsi/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause @@ -12,7 +12,7 @@ if(CONFIG_MCUX_COMPONENT_driver.mipi_dsi_smartdma) endif() if(CONFIG_MCUX_COMPONENT_driver.mipi_dsi) - mcux_component_version(2.2.2) + mcux_component_version(2.3.0) mcux_add_source(SOURCES fsl_mipi_dsi.c fsl_mipi_dsi.h) diff --git a/mcux/mcux-sdk-ng/drivers/mipi_dsi/fsl_mipi_dsi.c b/mcux/mcux-sdk-ng/drivers/mipi_dsi/fsl_mipi_dsi.c index a08153d50..f19bd7840 100644 --- a/mcux/mcux-sdk-ng/drivers/mipi_dsi/fsl_mipi_dsi.c +++ b/mcux/mcux-sdk-ng/drivers/mipi_dsi/fsl_mipi_dsi.c @@ -971,10 +971,10 @@ static status_t DSI_PrepareApbTransfer(MIPI_DSI_HOST_Type *base, dsi_transfer_t } /* ========================== Prepare TX. ========================== */ - /* If xfer->sendDscCmd is true, then the DCS command is not included in the - xfer->txData, but specified by xfer->dscCmd. + /* If xfer->sendDcsCmd is true, then the DCS command is not included in the + xfer->txData, but specified by xfer->dcsCmd. */ - if (xfer->sendDscCmd) + if (xfer->sendDcsCmd) { txDataSize = (uint32_t)xfer->txDataSize + 1U; } @@ -994,9 +994,9 @@ static status_t DSI_PrepareApbTransfer(MIPI_DSI_HOST_Type *base, dsi_transfer_t { txDataIndex = 0; - if (xfer->sendDscCmd) + if (xfer->sendDcsCmd) { - wordCount = xfer->dscCmd; + wordCount = xfer->dcsCmd; } else { @@ -1013,7 +1013,7 @@ static status_t DSI_PrepareApbTransfer(MIPI_DSI_HOST_Type *base, dsi_transfer_t else { wordCount = (uint16_t)txDataSize; - DSI_WriteApbTxPayloadExt(base, xfer->txData, xfer->txDataSize, xfer->sendDscCmd, xfer->dscCmd); + DSI_WriteApbTxPayloadExt(base, xfer->txData, xfer->txDataSize, xfer->sendDcsCmd, xfer->dcsCmd); } DSI_SetApbPacketControl(base, wordCount, xfer->virtualChannel, xfer->txDataType, xfer->flags); diff --git a/mcux/mcux-sdk-ng/drivers/mipi_dsi/fsl_mipi_dsi.h b/mcux/mcux-sdk-ng/drivers/mipi_dsi/fsl_mipi_dsi.h index 91015d2eb..d1d2c724d 100644 --- a/mcux/mcux-sdk-ng/drivers/mipi_dsi/fsl_mipi_dsi.h +++ b/mcux/mcux-sdk-ng/drivers/mipi_dsi/fsl_mipi_dsi.h @@ -1,5 +1,5 @@ /* - * Copyright 2017,2019-2023 NXP + * Copyright 2017,2019-2023,2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -350,9 +350,9 @@ typedef struct _dsi_transfer uint8_t *rxData; /*!< The RX data buffer. */ uint16_t txDataSize; /*!< Size of the TX data. */ uint16_t rxDataSize; /*!< Size of the RX data. */ - bool sendDscCmd; /*!< If set to true, the DCS command is specified by @ref dscCmd, otherwise + bool sendDcsCmd; /*!< If set to true, the DCS command is specified by @ref dcsCmd, otherwise the DCS command is included in the @ref txData. */ - uint8_t dscCmd; /*!< The DCS command to send, only valid when @ref sendDscCmd is true. */ + uint8_t dcsCmd; /*!< The DCS command to send, only valid when @ref sendDcsCmd is true. */ } dsi_transfer_t; /*! @brief MIPI DSI transfer handle. */ diff --git a/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/CMakeLists.txt index bd63b0b4b..e5023b33b 100644 --- a/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.mipi_dsi_imx) - mcux_component_version(2.0.3) + mcux_component_version(2.1.0) mcux_add_source(SOURCES fsl_mipi_dsi.c fsl_mipi_dsi.h) diff --git a/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/fsl_mipi_dsi.c b/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/fsl_mipi_dsi.c index 02bb8bd02..52c71f933 100644 --- a/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/fsl_mipi_dsi.c +++ b/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/fsl_mipi_dsi.c @@ -811,7 +811,7 @@ static status_t DSI_PrepareApbTransfer(MIPI_DSI_Type *base, dsi_transfer_t *xfer /* ========================== Prepare TX. ========================== */ /* If xfer->sendDcsCmd is true, then the DCS command is not included in the xfer->txData, but specified by xfer->dcsCmd. */ - txDataSize = xfer->sendDscCmd ? (uint32_t)xfer->txDataSize + 1U : (uint32_t)xfer->txDataSize; + txDataSize = xfer->sendDcsCmd ? (uint32_t)xfer->txDataSize + 1U : (uint32_t)xfer->txDataSize; /* Short packet. */ if (txDataSize <= 2U) @@ -824,10 +824,10 @@ static status_t DSI_PrepareApbTransfer(MIPI_DSI_Type *base, dsi_transfer_t *xfer { txDataIndex = 0; - if (xfer->sendDscCmd) + if (xfer->sendDcsCmd) { /* DCS command byte. */ - wordCount = xfer->dscCmd; + wordCount = xfer->dcsCmd; } else { @@ -846,7 +846,7 @@ static status_t DSI_PrepareApbTransfer(MIPI_DSI_Type *base, dsi_transfer_t *xfer else { wordCount = (uint16_t)txDataSize; - DSI_WriteTxPayloadExt(base, xfer->txData, xfer->txDataSize, xfer->sendDscCmd, xfer->dscCmd); + DSI_WriteTxPayloadExt(base, xfer->txData, xfer->txDataSize, xfer->sendDcsCmd, xfer->dcsCmd); } /* Clear the interrupt flags set by previous transfer. */ diff --git a/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/fsl_mipi_dsi.h b/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/fsl_mipi_dsi.h index d7a95a965..c1b5940d2 100644 --- a/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/fsl_mipi_dsi.h +++ b/mcux/mcux-sdk-ng/drivers/mipi_dsi_imx/fsl_mipi_dsi.h @@ -375,9 +375,9 @@ typedef struct _dsi_transfer uint8_t *rxData; /*!< The TX data buffer. */ uint16_t txDataSize; /*!< Size of the TX data. */ uint16_t rxDataSize; /*!< Size of the RX data. */ - bool sendDscCmd; /*!< If set to true, the DCS command is specified by @ref dscCmd, otherwise + bool sendDcsCmd; /*!< If set to true, the DCS command is specified by @ref dcsCmd, otherwise the DCS command is included in the @ref txData. */ - uint8_t dscCmd; /*!< The DCS command to send, only valid when @ref sendDscCmd is true. */ + uint8_t dcsCmd; /*!< The DCS command to send, only valid when @ref sendDcsCmd is true. */ } dsi_transfer_t; /******************************************************************************* diff --git a/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/CMakeLists.txt index 58293c8eb..1cc7070d1 100644 --- a/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.mipi_dsi_split) - mcux_component_version(2.2.5) + mcux_component_version(2.3.0) mcux_add_source(SOURCES fsl_mipi_dsi.c fsl_mipi_dsi.h) diff --git a/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/fsl_mipi_dsi.c b/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/fsl_mipi_dsi.c index 14f8997a5..1d88b73c3 100644 --- a/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/fsl_mipi_dsi.c +++ b/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/fsl_mipi_dsi.c @@ -1,5 +1,5 @@ /* - * Copyright 2020-2022,2024 NXP + * Copyright 2020-2022,2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -151,7 +151,7 @@ static uint8_t DSI_EncodeDphyPllCm(uint8_t cm); * find suitable dividers, return 0. */ static uint32_t DSI_DphyGetPllDivider( - uint32_t *cn, uint32_t *cm, uint32_t *co, uint32_t refClkFreq_Hz, uint32_t desiredOutFreq_Hz); + uint8_t *cn, uint8_t *cm, uint8_t *co, uint32_t refClkFreq_Hz, uint32_t desiredOutFreq_Hz); #endif /*! @@ -288,11 +288,11 @@ static uint8_t DSI_EncodeDphyPllCm(uint8_t cm) } static uint32_t DSI_DphyGetPllDivider( - uint32_t *cn, uint32_t *cm, uint32_t *co, uint32_t refClkFreq_Hz, uint32_t desiredOutFreq_Hz) + uint8_t *cn, uint8_t *cm, uint8_t *co, uint32_t refClkFreq_Hz, uint32_t desiredOutFreq_Hz) { - uint32_t cnCur; - uint32_t cmCur; - uint32_t coShiftCur; + uint8_t cnCur; + uint8_t cmCur; + uint8_t coShiftCur; uint32_t pllFreqCur; uint32_t diffCur; uint32_t vcoFreq; @@ -322,7 +322,7 @@ static uint32_t DSI_DphyGetPllDivider( for (cnCur = DSI_DPHY_PLL_CN_MIN; cnCur <= DSI_DPHY_PLL_CN_MAX; cnCur++) { /* REF_CLK / CN. */ - refClk_CN = refClkFreq_Hz / cnCur; + refClk_CN = refClkFreq_Hz / (uint32_t)cnCur; /* If desired REF_CLK / CN frequency is too large, try larger CN value. */ if (refClk_CN > DSI_DPHY_PLL_REFCLK_CN_MAX) @@ -337,7 +337,7 @@ static uint32_t DSI_DphyGetPllDivider( } /* Get the CM most close. */ - cmCur = (vcoFreq + (refClk_CN / 2U)) / refClk_CN; + cmCur = (uint8_t)((vcoFreq + (refClk_CN / 2U)) / refClk_CN); /* If calculated value is (DSI_DPHY_PLL_CM_MAX + 1), use DSI_DPHY_PLL_CM_MAX. */ if ((DSI_DPHY_PLL_CM_MAX + 1U) == cmCur) @@ -351,7 +351,7 @@ static uint32_t DSI_DphyGetPllDivider( } /* Output frequency using current dividers. */ - pllFreqCur = (refClk_CN * cmCur) >> coShiftCur; + pllFreqCur = (refClk_CN * (uint32_t)cmCur) >> coShiftCur; if (pllFreqCur > desiredOutFreq_Hz) { @@ -395,8 +395,9 @@ static void DSI_ApbClearRxFifo(const MIPI_DSI_Type *base) volatile uint32_t dummy = 0U; uint32_t level = base->apb->PKT_FIFO_RD_LEVEL; - while (0U != (level--)) + while (0U != level) { + level--; dummy = base->apb->PKT_RX_PAYLOAD; } @@ -620,9 +621,9 @@ uint32_t DSI_InitDphy(const MIPI_DSI_Type *base, const dsi_dphy_config_t *config DSI_HOST_Type *host = base->host; #if !((defined(FSL_FEATURE_MIPI_NO_DPHY_PLL)) && (0 != FSL_FEATURE_MIPI_DSI_HOST_NO_DPHY_PLL)) - uint32_t cn = 0x0U; - uint32_t cm = 0x0U; - uint32_t co = 0x0U; + uint8_t cn = 0x0U; + uint8_t cm = 0x0U; + uint8_t co = 0x0U; uint32_t outputPllFreq; outputPllFreq = DSI_DphyGetPllDivider(&cn, &cm, &co, refClkFreq_Hz, config->txHsBitClk_Hz); @@ -634,9 +635,9 @@ uint32_t DSI_InitDphy(const MIPI_DSI_Type *base, const dsi_dphy_config_t *config } /* Set the DPHY parameters. */ - dphy->CN = (uint32_t)DSI_EncodeDphyPllCn((uint8_t)cn); - dphy->CM = (uint32_t)DSI_EncodeDphyPllCm((uint8_t)cm); - dphy->CO = co; + dphy->CN = (uint32_t)DSI_EncodeDphyPllCn(cn); + dphy->CM = (uint32_t)DSI_EncodeDphyPllCm(cm); + dphy->CO = (uint32_t)co; #endif /* Set the timing parameters. */ @@ -855,16 +856,16 @@ void DSI_WriteApbTxPayload(const MIPI_DSI_Type *base, const uint8_t *payload, ui } void DSI_WriteApbTxPayloadExt( - const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize, bool sendDscCmd, uint8_t dscCmd) + const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize, bool sendDcsCmd, uint8_t dcsCmd) { uint32_t firstWord; uint16_t i; - uint16_t payloadSizeLocal = payloadSize; + uint32_t payloadSizeLocal = (uint32_t)payloadSize; const uint8_t *payloadLocal = payload; DSI_HOST_APB_PKT_IF_Type *apb = base->apb; - if (sendDscCmd) + if (sendDcsCmd) { payloadSizeLocal += 1U; } @@ -872,9 +873,9 @@ void DSI_WriteApbTxPayloadExt( assert(payloadSizeLocal <= FSL_DSI_TX_MAX_PAYLOAD_BYTE); /* The first 4-byte. */ - if (sendDscCmd) + if (sendDcsCmd) { - firstWord = dscCmd; + firstWord = dcsCmd; } else { @@ -952,10 +953,10 @@ static status_t DSI_PrepareApbTransfer(const MIPI_DSI_Type *base, dsi_transfer_t } /* ========================== Prepare TX. ========================== */ - /* If xfer->sendDscCmd is true, then the DSC command is not included in the - xfer->txData, but specified by xfer->dscCmd. + /* If xfer->sendDcsCmd is true, then the DCS command is not included in the + xfer->txData, but specified by xfer->dcsCmd. */ - if (xfer->sendDscCmd) + if (xfer->sendDcsCmd) { txDataSize = (uint32_t)xfer->txDataSize + 1U; } @@ -975,9 +976,9 @@ static status_t DSI_PrepareApbTransfer(const MIPI_DSI_Type *base, dsi_transfer_t { txDataIndex = 0; - if (xfer->sendDscCmd) + if (xfer->sendDcsCmd) { - wordCount = xfer->dscCmd; + wordCount = xfer->dcsCmd; } else { @@ -994,7 +995,7 @@ static status_t DSI_PrepareApbTransfer(const MIPI_DSI_Type *base, dsi_transfer_t else { wordCount = (uint16_t)txDataSize; - DSI_WriteApbTxPayloadExt(base, xfer->txData, xfer->txDataSize, xfer->sendDscCmd, xfer->dscCmd); + DSI_WriteApbTxPayloadExt(base, xfer->txData, xfer->txDataSize, xfer->sendDcsCmd, xfer->dcsCmd); } DSI_SetApbPacketControl(base, wordCount, xfer->virtualChannel, xfer->txDataType, xfer->flags); diff --git a/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/fsl_mipi_dsi.h b/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/fsl_mipi_dsi.h index 4c778687b..ab03013c9 100644 --- a/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/fsl_mipi_dsi.h +++ b/mcux/mcux-sdk-ng/drivers/mipi_dsi_split/fsl_mipi_dsi.h @@ -1,5 +1,5 @@ /* - * Copyright 2020-2022,2024 NXP + * Copyright 2020-2022,2024-2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -329,9 +329,9 @@ typedef struct _dsi_transfer uint8_t *rxData; /*!< The TX data buffer. */ uint16_t txDataSize; /*!< Size of the TX data. */ uint16_t rxDataSize; /*!< Size of the RX data. */ - bool sendDscCmd; /*!< If set to true, the DSC command is specified by @ref dscCmd, otherwise - the DSC command is included in the @ref txData. */ - uint8_t dscCmd; /*!< The DSC command to send, only valid when @ref sendDscCmd is true. */ + bool sendDcsCmd; /*!< If set to true, the DCS command is specified by @ref dcsCmd, otherwise + the DCS command is included in the @ref txData. */ + uint8_t dcsCmd; /*!< The DCS command to send, only valid when @ref sendDcsCmd is true. */ } dsi_transfer_t; /*! @brief MIPI DSI transfer handle. */ @@ -578,24 +578,24 @@ void DSI_WriteApbTxPayload(const MIPI_DSI_Type *base, const uint8_t *payload, ui * * Write the long packet payload to TX FIFO. This function could be used in two ways * - * 1. Include the DSC command in parameter @p payload. In this case, the DSC command - * is the first byte of @p payload. The parameter @p sendDscCmd is set to false, - * the @p dscCmd is not used. This function is the same as @ref DSI_WriteApbTxPayload + * 1. Include the DCS command in parameter @p payload. In this case, the DCS command + * is the first byte of @p payload. The parameter @p sendDcsCmd is set to false, + * the @p dcsCmd is not used. This function is the same as @ref DSI_WriteApbTxPayload * when used in this way. * - * 2. The DSC command in not in parameter @p payload, but specified by parameter @p dscCmd. - * In this case, the parameter @p sendDscCmd is set to true, the @p dscCmd is the DSC - * command to send. The @p payload is sent after @p dscCmd. + * 2. The DCS command in not in parameter @p payload, but specified by parameter @p dcsCmd. + * In this case, the parameter @p sendDcsCmd is set to true, the @p dcsCmd is the DCS + * command to send. The @p payload is sent after @p dcsCmd. * * @param base MIPI DSI host peripheral base address. * @param payload Pointer to the payload. * @param payloadSize Payload size in byte. - * @param sendDscCmd If set to true, the DSC command is specified by @p dscCmd, - * otherwise the DSC command is included in the @p payload. - * @param dscCmd The DSC command to send, only used when @p sendDscCmd is true. + * @param sendDcsCmd If set to true, the DCS command is specified by @p dcsCmd, + * otherwise the DCS command is included in the @p payload. + * @param dcsCmd The DCS command to send, only used when @p sendDcsCmd is true. */ void DSI_WriteApbTxPayloadExt( - const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize, bool sendDscCmd, uint8_t dscCmd); + const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize, bool sendDcsCmd, uint8_t dcsCmd); /*! * @brief Read the long APB packet payload. diff --git a/mcux/mcux-sdk-ng/drivers/mu/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/mu/CMakeLists.txt index 1b6f7159c..205e0e494 100644 --- a/mcux/mcux-sdk-ng/drivers/mu/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/mu/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.mu) - mcux_component_version(2.2.0) + mcux_component_version(2.3.0) mcux_add_source(SOURCES fsl_mu.h fsl_mu.c) diff --git a/mcux/mcux-sdk-ng/drivers/mu/fsl_mu.c b/mcux/mcux-sdk-ng/drivers/mu/fsl_mu.c index 9fa81ab5d..337d33f2e 100644 --- a/mcux/mcux-sdk-ng/drivers/mu/fsl_mu.c +++ b/mcux/mcux-sdk-ng/drivers/mu/fsl_mu.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020, 2023 NXP - * All rights reserved. + * Copyright 2016-2020, 2023-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,9 +43,16 @@ static uint32_t MU_GetInstance(MU_Type *base) uint32_t instance; /* Find the instance index from base address mappings. */ - for (instance = 0U; instance < (sizeof(s_muBases) / sizeof(s_muBases[0])); instance++) + /* + * $Branch Coverage Justification$ + * This function implements a guaranteed-success lookup because: + * 1. s_muBases[] array is populated from preprocessor defines (MU_BASE_PTRS) + * 2. Invalid base addresses would cause compilation/linking errors, not runtime errors + * 3. Function is only called with valid MU base addresses that must exist in s_muBases[] + */ + for (instance = 0U; instance < (sizeof(s_muBases) / sizeof(s_muBases[0])); instance++) /* GCOVR_EXCL_BR_LINE */ { - if (MSDK_REG_SECURE_ADDR(s_muBases[instance]) == MSDK_REG_SECURE_ADDR(base)) + if (MSDK_REG_SECURE_ADDR(s_muBases[instance]) == MSDK_REG_SECURE_ADDR(base)) /* GCOVR_EXCL_BR_LINE */ { break; } @@ -91,35 +97,114 @@ void MU_Deinit(MU_Type *base) } /*! - * brief Blocks to send a message. + * @brief Blocks to send a message. * * This function waits until the TX register is empty and sends the message. + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and returns kStatus_Timeout. * - * param base MU peripheral base address. - * param regIndex TX register index. - * param msg Message to send. + * @param base MU peripheral base address. + * @param regIndex MU message register, see @ref mu_msg_reg_index_t. + * @param msg Message to send. + * + * @return status_t + * @retval kStatus_Success Message sent successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for TX register to be empty. */ -void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg) +status_t MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg) { assert(regIndex < MU_TR_COUNT); +#if MU_BUSY_POLL_COUNT + uint32_t poll_count = MU_BUSY_POLL_COUNT; +#endif /* MU_BUSY_POLL_COUNT */ + /* Wait TX register to be empty. */ while (0U == (base->SR & (((uint32_t)kMU_Tx0EmptyFlag) >> regIndex))) { - ; /* Intentional empty while*/ +#if MU_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU_BUSY_POLL_COUNT */ } base->TR[regIndex] = msg; + + return kStatus_Success; } /*! - * brief Blocks to receive a message. + * @brief Blocks to receive a message with timeout protection. * * This function waits until the RX register is full and receives the message. + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout. * - * param base MU peripheral base address. - * param regIndex RX register index. - * return The received message. + * This function provides the same blocking behavior as MU_ReceiveMsg() but + * with additional timeout protection to prevent system hangs if the other + * core becomes unresponsive or if hardware issues occur. + * + * @note Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. + * The difference is that this function includes timeout protection while + * MU_ReceiveMsg() waits indefinitely. + * + * @param base MU peripheral base address. + * @param regIndex RX register index, see @ref mu_msg_reg_index_t. + * @param readValue Pointer to store the received message. + * + * @return status_t + * @retval kStatus_Success Message received successfully. + * @retval kStatus_InvalidArgument Invalid readValue pointer. + * @retval kStatus_Timeout Timeout occurred while waiting for RX register to be full. + */ +status_t MU_ReceiveMsgTimeout(MU_Type *base, uint32_t regIndex, uint32_t *readValue) +{ + assert(regIndex < MU_TR_COUNT); + + if (NULL == readValue) + { + return kStatus_InvalidArgument; + } + +#if MU_BUSY_POLL_COUNT + uint32_t poll_count = MU_BUSY_POLL_COUNT; +#endif /* MU_BUSY_POLL_COUNT */ + + /* Wait RX register to be full. */ + while (0U == (base->SR & (((uint32_t)kMU_Rx0FullFlag) >> regIndex))) + { +#if MU_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU_BUSY_POLL_COUNT */ + } + + *readValue = base->RR[regIndex]; + + return kStatus_Success; +} + +/*! + * @brief Blocks to receive a message (infinite wait, no timeout protection). + * + * This function waits until the RX register is full and receives the message. + * This function will wait indefinitely until a message is received. + * + * @note Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. + * The difference is that MU_ReceiveMsgTimeout() includes timeout protection + * while this function waits indefinitely. + * + * @warning This function does not include timeout protection and may cause + * system hangs if the other core becomes unresponsive. For applications + * requiring timeout protection, use MU_ReceiveMsgTimeout() instead. + * + * @param base MU peripheral base address. + * @param regIndex RX register index, see @ref mu_msg_reg_index_t. + * @return The received message. */ uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex) { @@ -144,18 +229,57 @@ uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex) * the flags cannot be changed. This function waits for the MU status flag * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags. * + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout. + * * param base MU peripheral base address. * param flags The 3-bit MU flags to set. + * + * return status_t + * retval kStatus_Success Flags were set successfully. + * retval kStatus_Timeout Timeout occurred while waiting for flags to update. */ -void MU_SetFlags(MU_Type *base, uint32_t flags) +status_t MU_SetFlags(MU_Type *base, uint32_t flags) { +#if MU_BUSY_POLL_COUNT + uint32_t poll_count = MU_BUSY_POLL_COUNT; +#endif /* MU_BUSY_POLL_COUNT */ + /* Wait for update finished. */ - while (0U != (base->SR & ((uint32_t)MU_SR_FUP_MASK))) + /* + * $Branch Coverage Justification$ + * The while loop condition cannot be reliably tested to be true because: + * 1. MU_SR_FUP_MASK (Flags Updating Pending) is cleared by hardware automatically within microseconds + * 2. Flag updates complete in a few clock cycles in normal hardware operation + * 3. Testing the true condition would require hardware fault injection or clock manipulation + * 4. The loop body execution represents a hardware timing anomaly that cannot be reliably reproduced + */ + while (0U != (base->SR & ((uint32_t)MU_SR_FUP_MASK))) /* GCOVR_EXCL_BR_LINE */ { - ; /* Intentional empty while*/ +#if MU_BUSY_POLL_COUNT + /* + * $Branch Coverage Justification$ + * The timeout branch cannot be reliably tested because: + * 1. MU_SR_FUP_MASK is cleared by hardware automatically within a few clock cycles + * 2. Timeout only occurs during catastrophic hardware failure or clock stoppage + * 3. Testing would require hardware fault injection or unrealistic clock manipulation + * 4. Normal hardware operation completes flag updates in microseconds + */ + if ((--poll_count) == 0u) /* GCOVR_EXCL_LINE */ + { + /* + * $Branch Coverage Justification$ + * Hardware timeout return path - only reachable during hardware malfunction. + * Cannot be tested without hardware fault injection capabilities. + */ + return kStatus_Timeout; /* GCOVR_EXCL_LINE */ + } +#endif /* MU_BUSY_POLL_COUNT */ } MU_SetFlagsNonBlocking(base, flags); + + return kStatus_Success; } /*! @@ -256,43 +380,53 @@ void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode) #if !(defined(FSL_FEATURE_MU_NO_HR) && FSL_FEATURE_MU_NO_HR) #if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) /*! - * brief Hardware reset the other core. + * @brief Hardware reset the other core. * * This function resets the other core, the other core could mask the - * hardware reset by calling ref MU_MaskHardwareReset. The hardware reset + * hardware reset by calling MU_MaskHardwareReset. The hardware reset * mask feature is only available for some platforms. * This function could be used together with MU_BootOtherCore to control the * other core reset workflow. * + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout + * if waiting for the other core to enter or exit reset takes too long. + * * Example 1: Reset the other core, and no hold reset - * code + * @code * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); - * endcode + * @endcode * In this example, the core at MU side B will reset with the specified boot mode. * * Example 2: Reset the other core and hold it, then boot the other core later. - * code - * Here the other core enters reset, and the reset is hold + * Here the other core enters reset, and the reset is hold + * @code * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); - * Current core boot the other core when necessary. + * @endcode + * Current core boot the other core when necessary. + * @code * MU_BootOtherCore(MU_A, bootMode); - * endcode + * @endcode * - * param base MU peripheral base address. - * param waitReset Wait the other core enters reset. + * @param base MU peripheral base address. + * @param waitReset Wait the other core enters reset. * - true: Wait until the other core enters reset, if the other * core has masked the hardware reset, then this function will * be blocked. * - false: Don't wait the reset. - * param holdReset Hold the other core reset or not. + * @param holdReset Hold the other core reset or not. * - true: Hold the other core in reset, this function returns * directly when the other core enters reset. * - false: Don't hold the other core in reset, this function * waits until the other core out of reset. - * param bootMode Boot mode of the other core, if p holdReset is true, this + * @param bootMode Boot mode of the other core, if @p holdReset is true, this * parameter is useless. + * + * @return status_t + * @retval kStatus_Success The other core was reset successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for the other core to enter or exit reset. */ -void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) +status_t MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) { #if (defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH) /* If MU does not support hold reset, then the parameter must be false. */ @@ -313,13 +447,22 @@ void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu /* Set CCR[HR] to trigger hardware reset. */ base->CCR = ccr | MU_CCR_HR_MASK; +#if MU_BUSY_POLL_COUNT + uint32_t poll_count = MU_BUSY_POLL_COUNT; +#endif /* MU_BUSY_POLL_COUNT */ + /* If wait the other core enters reset. */ if (waitReset) { /* Wait for the other core go to reset. */ while (0U == (base->SR & MU_SR_RAIP_MASK)) { - ; /* Intentional empty while*/ +#if MU_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU_BUSY_POLL_COUNT */ } if (!holdReset) @@ -327,53 +470,74 @@ void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu /* Clear CCR[HR]. */ base->CCR = ccr; +#if MU_BUSY_POLL_COUNT + poll_count = MU_BUSY_POLL_COUNT; +#endif /* MU_BUSY_POLL_COUNT */ + /* Wait for the other core out of reset. */ while (0U == (base->SR & MU_SR_RDIP_MASK)) { - ; /* Intentional empty while*/ +#if MU_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU_BUSY_POLL_COUNT */ } } } + + return kStatus_Success; } #else /* FSL_FEATURE_MU_HAS_CCR */ /*! - * brief Hardware reset the other core. + * @brief Hardware reset the other core. * * This function resets the other core, the other core could mask the - * hardware reset by calling ref MU_MaskHardwareReset. The hardware reset + * hardware reset by calling MU_MaskHardwareReset. The hardware reset * mask feature is only available for some platforms. * This function could be used together with MU_BootOtherCore to control the * other core reset workflow. * + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout + * if waiting for the other core to enter or exit reset takes too long. + * * Example 1: Reset the other core, and no hold reset - * code + * @code * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); - * endcode + * @endcode * In this example, the core at MU side B will reset with the specified boot mode. * * Example 2: Reset the other core and hold it, then boot the other core later. - * code - * Here the other core enters reset, and the reset is hold + * Here the other core enters reset, and the reset is hold + * @code * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); - * Current core boot the other core when necessary. + * @endcode + * Current core boot the other core when necessary. + * @code * MU_BootOtherCore(MU_A, bootMode); - * endcode + * @endcode * - * param base MU peripheral base address. - * param waitReset Wait the other core enters reset. + * @param base MU peripheral base address. + * @param waitReset Wait the other core enters reset. * - true: Wait until the other core enters reset, if the other * core has masked the hardware reset, then this function will * be blocked. * - false: Don't wait the reset. - * param holdReset Hold the other core reset or not. + * @param holdReset Hold the other core reset or not. * - true: Hold the other core in reset, this function returns * directly when the other core enters reset. * - false: Don't hold the other core in reset, this function * waits until the other core out of reset. - * param bootMode Boot mode of the other core, if p holdReset is true, this + * @param bootMode Boot mode of the other core, if @p holdReset is true, this * parameter is useless. + * + * @return status_t + * @retval kStatus_Success The other core was reset successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for the other core to enter or exit reset. */ -void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) +status_t MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) { #if (defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH) /* If MU does not support hold reset, then the parameter must be false. */ @@ -402,6 +566,10 @@ void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu /* Set CR[HR] to trigger hardware reset. */ base->CR = cr | MU_CR_HR_MASK; +#if MU_BUSY_POLL_COUNT + uint32_t poll_count = MU_BUSY_POLL_COUNT; +#endif /* MU_BUSY_POLL_COUNT */ + /* If wait the other core enters reset. */ if (waitReset) { @@ -409,7 +577,12 @@ void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu /* Wait for the other core go to reset. */ while (0U == (base->SR & MU_SR_RAIP_MASK)) { - ; /* Intentional empty while*/ +#if MU_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU_BUSY_POLL_COUNT */ } #endif @@ -419,14 +592,25 @@ void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu base->CR = cr; #if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) +#if MU_BUSY_POLL_COUNT + poll_count = MU_BUSY_POLL_COUNT; +#endif /* MU_BUSY_POLL_COUNT */ + /* Wait for the other core out of reset. */ while (0U == (base->SR & MU_SR_RDIP_MASK)) { - ; /* Intentional empty while*/ +#if MU_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU_BUSY_POLL_COUNT */ } #endif } } + + return kStatus_Success; } #endif /* FSL_FEATURE_MU_HAS_CCR */ #endif /* FSL_FEATURE_MU_NO_HR */ diff --git a/mcux/mcux-sdk-ng/drivers/mu/fsl_mu.h b/mcux/mcux-sdk-ng/drivers/mu/fsl_mu.h index 6059f4959..6229928ac 100644 --- a/mcux/mcux-sdk-ng/drivers/mu/fsl_mu.h +++ b/mcux/mcux-sdk-ng/drivers/mu/fsl_mu.h @@ -1,7 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2024 NXP - * All rights reserved. + * Copyright 2016-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,6 +35,29 @@ #endif /* FSL_FEATURE_MU_HAS_RESET_INT */ +/*! + * @brief Maximum polling iterations for MU waiting loops + * + * This parameter defines the maximum number of iterations for any polling loop + * in the MU code before timing out and returning an error. + * + * It applies to all waiting loops in MU driver, such as waiting for TX register + * to be empty or waiting for RX register to be full. + * + * This is a count of loop iterations, not a time-based value. + * + * If defined as 0, polling loops will continue indefinitely until their exit condition + * is met, which could potentially cause the system to hang if a core becomes + * unresponsive. + */ +#ifndef MU_BUSY_POLL_COUNT + #ifdef CONFIG_MU_BUSY_POLL_COUNT + #define MU_BUSY_POLL_COUNT CONFIG_MU_BUSY_POLL_COUNT + #else + #define MU_BUSY_POLL_COUNT 0U + #endif +#endif + /*! * @name Driver version * @{ @@ -218,12 +240,18 @@ static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint3 * @brief Blocks to send a message. * * This function waits until the TX register is empty and sends the message. + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and returns kStatus_Timeout. * * @param base MU peripheral base address. * @param regIndex MU message register, see @ref mu_msg_reg_index_t. * @param msg Message to send. + * + * @return status_t + * @retval kStatus_Success Message sent successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for TX register to be empty. */ -void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); +status_t MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); /*! * @brief Reads a message from the RX register. @@ -254,12 +282,47 @@ static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex } /*! - * @brief Blocks to receive a message. + * @brief Blocks to receive a message with timeout protection. * * This function waits until the RX register is full and receives the message. + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout. + * + * This function provides the same blocking behavior as MU_ReceiveMsg() but + * with additional timeout protection to prevent system hangs if the other + * core becomes unresponsive or if hardware issues occur. + * + * @note Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. + * The difference is that this function includes timeout protection while + * MU_ReceiveMsg() waits indefinitely. * * @param base MU peripheral base address. - * @param regIndex MU message register, see @ref mu_msg_reg_index_t + * @param regIndex RX register index, see @ref mu_msg_reg_index_t. + * @param readValue Pointer to store the received message. + * + * @return status_t + * @retval kStatus_Success Message received successfully. + * @retval kStatus_InvalidArgument Invalid readValue pointer. + * @retval kStatus_Timeout Timeout occurred while waiting for RX register to be full. + */ +status_t MU_ReceiveMsgTimeout(MU_Type *base, uint32_t regIndex, uint32_t *readValue); + +/*! + * @brief Blocks to receive a message (infinite wait, no timeout protection). + * + * This function waits until the RX register is full and receives the message. + * This function will wait indefinitely until a message is received. + * + * @note Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. + * The difference is that MU_ReceiveMsgTimeout() includes timeout protection + * while this function waits indefinitely. + * + * @warning This function does not include timeout protection and may cause + * system hangs if the other core becomes unresponsive. For applications + * requiring timeout protection, use MU_ReceiveMsgTimeout() instead. + * + * @param base MU peripheral base address. + * @param regIndex RX register index, see @ref mu_msg_reg_index_t. * @return The received message. */ uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex); @@ -309,10 +372,17 @@ static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags) * the flags cannot be changed. This function waits for the MU status flag * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags. * + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout. + * * @param base MU peripheral base address. * @param flags The 3-bit MU flags to set. + * + * @return status_t + * @retval kStatus_Success Flags were set successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for flags to update. */ -void MU_SetFlags(MU_Type *base, uint32_t flags); +status_t MU_SetFlags(MU_Type *base, uint32_t flags); /*! * @brief Gets the current value of the 3-bit MU flags set by the other side. @@ -635,22 +705,61 @@ static inline void MU_HoldOtherCoreReset(MU_Type *base) * recommended to interrupt processor B, because this function may affect the * ongoing processor B programs. * + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations if waiting for the other side + * to come out of reset takes too long. + * * @param base MU peripheral base address. + * @return status_t + * @retval kStatus_Success The MU was reset successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for the other side to come out of reset. + * * @note For some platforms, only MU side A could use this function, check * reference manual for details. */ -static inline void MU_ResetBothSides(MU_Type *base) +static inline status_t MU_ResetBothSides(MU_Type *base) { uint32_t reg = base->CR; reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_MUR_MASK; base->CR = reg; #if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) +#if MU_BUSY_POLL_COUNT + uint32_t poll_count = MU_BUSY_POLL_COUNT; +#endif /* MU_BUSY_POLL_COUNT */ + /* Wait for the other side out of reset. */ - while (0U != (base->SR & MU_SR_RS_MASK)) + /* + * $Branch Coverage Justification$ + * The while loop condition cannot be reliably tested to be true because: + * 1. MU_SR_RS_MASK is cleared by hardware immediately after MU reset + * 2. The other side comes out of reset within microseconds in normal operation + * 3. Testing the true condition would require hardware fault injection + * 4. The loop body execution represents a hardware malfunction scenario + */ + while (0U != (base->SR & MU_SR_RS_MASK)) /* GCOVR_EXCL_BR_LINE */ { +#if MU_BUSY_POLL_COUNT + /* + * $Branch Coverage Justification$ + * Timeout branch - only reachable if while condition is true, + * which cannot be reliably tested in normal hardware operation. + */ + if ((--poll_count) == 0u) /* GCOVR_EXCL_LINE */ + { + /* + * $Branch Coverage Justification$ + * MU peripheral timeout return path - only reachable during hardware malfunction + * or when other core's MU peripheral is unresponsive. Cannot be reliably tested + * without hardware fault injection capabilities. + */ + return kStatus_Timeout; /* GCOVR_EXCL_LINE */ + } +#endif /* MU_BUSY_POLL_COUNT */ } #endif /* FSL_FEATURE_MU_HAS_SR_RS */ + + return kStatus_Success; } #endif /* FSL_FEATURE_MU_NO_MUR */ @@ -698,6 +807,10 @@ static inline void MU_MaskHardwareReset(MU_Type *base, bool mask) * This function could be used together with MU_BootOtherCore to control the * other core reset workflow. * + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout + * if waiting for the other core to enter or exit reset takes too long. + * * Example 1: Reset the other core, and no hold reset * @code * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); @@ -705,10 +818,12 @@ static inline void MU_MaskHardwareReset(MU_Type *base, bool mask) * In this example, the core at MU side B will reset with the specified boot mode. * * Example 2: Reset the other core and hold it, then boot the other core later. - * @code * Here the other core enters reset, and the reset is hold + * @code * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); + * @endcode * Current core boot the other core when necessary. + * @code * MU_BootOtherCore(MU_A, bootMode); * @endcode * @@ -725,8 +840,12 @@ static inline void MU_MaskHardwareReset(MU_Type *base, bool mask) * waits until the other core out of reset. * @param bootMode Boot mode of the other core, if @p holdReset is true, this * parameter is useless. + * + * @return status_t + * @retval kStatus_Success The other core was reset successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for the other core to enter or exit reset. */ -void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode); +status_t MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode); #endif /* FSL_FEATURE_MU_NO_HR */ #if !(defined(FSL_FEATURE_MU_NO_CLKE) && FSL_FEATURE_MU_NO_CLKE) diff --git a/mcux/mcux-sdk-ng/drivers/mu1/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/mu1/CMakeLists.txt index 29bc7cbdb..ef4a6dd61 100644 --- a/mcux/mcux-sdk-ng/drivers/mu1/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/mu1/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.mu1) - mcux_component_version(2.7.0) + mcux_component_version(2.8.0) mcux_add_source(SOURCES fsl_mu.h fsl_mu.c) diff --git a/mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.c b/mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.c index 4f520dc19..ccd944c80 100644 --- a/mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.c +++ b/mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.c @@ -1,6 +1,5 @@ /* - * Copyright 2021-2024 NXP - * All rights reserved. + * Copyright 2021-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,7 +23,7 @@ ******************************************************************************/ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #if (defined(MU_CLOCKS)) -/*! @brief Pointers to mu clocks for each instance. */ +/*! brief Pointers to mu clocks for each instance. */ static const clock_ip_name_t s_muClocks[] = MU_CLOCKS; #endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ @@ -34,7 +33,7 @@ static const clock_ip_name_t s_muClocks[] = MU_CLOCKS; static const reset_ip_name_t s_muResets[] = MU_RESETS_ARRAY; #endif -/*! @brief Pointers to mu bases for each instance. */ +/*! brief Pointers to mu bases for each instance. */ static MU_Type *const s_muBases[] = MU_BASE_PTRS; /****************************************************************************** @@ -98,32 +97,111 @@ void MU_Deinit(MU_Type *base) * brief Blocks to send a message. * * This function waits until the TX register is empty and sends the message. + * If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and returns kStatus_Timeout. * * param base MU peripheral base address. - * param regIndex TX register index. + * param regIndex MU message register, see ref mu_msg_reg_index_t. * param msg Message to send. + * + * return status_t + * retval kStatus_Success Message sent successfully. + * retval kStatus_Timeout Timeout occurred while waiting for TX register to be empty. */ -void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg) +status_t MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg) { assert(regIndex < MU_TR_COUNT); +#if MU1_BUSY_POLL_COUNT + uint32_t poll_count = MU1_BUSY_POLL_COUNT; +#endif /* MU1_BUSY_POLL_COUNT */ + /* Wait TX register to be empty. */ while (0U == (base->TSR & (1UL << regIndex))) { - ; /* Intentional empty while*/ +#if MU1_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU1_BUSY_POLL_COUNT */ } base->TR[regIndex] = msg; + + return kStatus_Success; } /*! - * brief Blocks to receive a message. + * @brief Blocks to receive a message with timeout protection. * * This function waits until the RX register is full and receives the message. + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout. * - * param base MU peripheral base address. - * param regIndex RX register index. - * return The received message. + * This function provides the same blocking behavior as MU_ReceiveMsg() but + * with additional timeout protection to prevent system hangs if the other + * core becomes unresponsive or if hardware issues occur. + * + * @note Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. + * The difference is that this function includes timeout protection while + * MU_ReceiveMsg() waits indefinitely. + * + * @param base MU peripheral base address. + * @param regIndex RX register index, see @ref mu_msg_reg_index_t. + * @param readValue Pointer to store the received message. + * + * @return status_t + * @retval kStatus_Success Message received successfully. + * @retval kStatus_InvalidArgument Invalid readValue pointer. + * @retval kStatus_Timeout Timeout occurred while waiting for RX register to be full. + */ +status_t MU_ReceiveMsgTimeout(MU_Type *base, uint32_t regIndex, uint32_t *readValue) +{ + assert(regIndex < MU_RR_COUNT); + + if (NULL == readValue) + { + return kStatus_InvalidArgument; + } + +#if MU_BUSY_POLL_COUNT + uint32_t poll_count = MU_BUSY_POLL_COUNT; +#endif /* MU_BUSY_POLL_COUNT */ + + /* Wait RX register to be full. */ + while (0U == (base->RSR & (1UL << regIndex))) + { +#if MU_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU_BUSY_POLL_COUNT */ + } + + *readValue = base->RR[regIndex]; + + return kStatus_Success; +} + +/*! + * @brief Blocks to receive a message (infinite wait, no timeout protection). + * + * This function waits until the RX register is full and receives the message. + * This function will wait indefinitely until a message is received. + * + * @note Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. + * The difference is that MU_ReceiveMsgTimeout() includes timeout protection + * while this function waits indefinitely. + * + * @warning This function does not include timeout protection and may cause + * system hangs if the other core becomes unresponsive. For applications + * requiring timeout protection, use MU_ReceiveMsgTimeout() instead. + * + * @param base MU peripheral base address. + * @param regIndex RX register index, see @ref mu_msg_reg_index_t. + * @return The received message. */ uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex) { @@ -148,18 +226,36 @@ uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex) * the flags cannot be changed. This function waits for the MU status flag * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags. * + * If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout. + * * param base MU peripheral base address. * param flags The 3-bit MU flags to set. + * + * return status_t + * retval kStatus_Success Flags were set successfully. + * retval kStatus_Timeout Timeout occurred while waiting for flags to update. */ -void MU_SetFlags(MU_Type *base, uint32_t flags) +status_t MU_SetFlags(MU_Type *base, uint32_t flags) { +#if MU1_BUSY_POLL_COUNT + uint32_t poll_count = MU1_BUSY_POLL_COUNT; +#endif /* MU1_BUSY_POLL_COUNT */ + /* Wait for update finished. */ while (0U != (base->SR & ((uint32_t)MU_SR_FUP_MASK))) { - ; /* Intentional empty while*/ +#if MU1_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU1_BUSY_POLL_COUNT */ } MU_SetFlagsNonBlocking(base, flags); + + return kStatus_Success; } /* @@ -389,11 +485,15 @@ void MU_HoldOtherCoreReset(MU_Type *base) * brief Hardware reset the other core. * * This function resets the other core, the other core could mask the - * hardware reset by calling ref MU_MaskHardwareReset. The hardware reset + * hardware reset by calling MU_MaskHardwareReset. The hardware reset * mask feature is only available for some platforms. * This function could be used together with MU_BootOtherCore to control the * other core reset workflow. * + * If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout + * if waiting for the other core to enter or exit reset takes too long. + * * Example 1: Reset the other core, and no hold reset * code * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); @@ -401,28 +501,42 @@ void MU_HoldOtherCoreReset(MU_Type *base) * In this example, the core at MU side B will reset with the specified boot mode. * * Example 2: Reset the other core and hold it, then boot the other core later. + * Here the other core enters reset, and the reset is hold * code - * Here the other core enters reset, and the reset is hold * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); - * Current core boot the other core when necessary. + * endcode + * Current core boot the other core when necessary. + * code * MU_BootOtherCore(MU_A, bootMode); * endcode * + * @note The feature waitReset, holdReset, and bootMode might be not supported + * for some platforms. waitReset is only available for platforms that + * FSL_FEATURE_MU_NO_CORE_STATUS not defined as 1 and + * FSL_FEATURE_MU_HAS_RESET_ASSERT_INT not defined as 0. holdReset is only available + * for platforms that FSL_FEATURE_MU_HAS_RSTH not defined as 0. + * bootMode is only available for platforms that FSL_FEATURE_MU_HAS_BOOT not + * defined as 0. + * * param base MU peripheral base address. - * param waitReset Wait the other core enters reset. + * param waitReset Wait the other core enters reset. Only work when there is CSSR0[RAIP]. * - true: Wait until the other core enters reset, if the other * core has masked the hardware reset, then this function will * be blocked. * - false: Don't wait the reset. - * param holdReset Hold the other core reset or not. + * param holdReset Hold the other core reset or not. Only work when there is CCR0[RSTH]. * - true: Hold the other core in reset, this function returns * directly when the other core enters reset. * - false: Don't hold the other core in reset, this function * waits until the other core out of reset. * param bootMode Boot mode of the other core, if p holdReset is true, this * parameter is useless. + * + * return status_t + * retval kStatus_Success The other core was reset successfully. + * retval kStatus_Timeout Timeout occurred while waiting for the other core to enter or exit reset. */ -void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) +status_t MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) { #if defined(FSL_FEATURE_MU_HAS_HR_BY_INSTANCEn) assert(FSL_FEATURE_MU_HAS_HR_BY_INSTANCEn(base) != 0); @@ -491,10 +605,19 @@ void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu { #if !(defined(FSL_FEATURE_MU_NO_CORE_STATUS) && (0 != FSL_FEATURE_MU_NO_CORE_STATUS)) #if !(defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && (FSL_FEATURE_MU_HAS_RESET_ASSERT_INT == 0)) +#if MU1_BUSY_POLL_COUNT + uint32_t poll_count = MU1_BUSY_POLL_COUNT; +#endif /* MU1_BUSY_POLL_COUNT */ + /* Wait for the other core go to reset. */ while (0U == (base->CSSR0 & MU_CSSR0_RAIP_MASK)) { - ; /* Intentional empty while*/ +#if MU1_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU1_BUSY_POLL_COUNT */ } #endif /* FSL_FEATURE_MU_HAS_RESET_ASSERT_INT */ #endif /* FSL_FEATURE_MU_NO_CORE_STATUS */ @@ -507,5 +630,7 @@ void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu } #endif /* FSL_FEATURE_MU_HAS_RSTH */ } + + return kStatus_Success; } #endif /* FSL_FEATURE_MU_HAS_HR */ diff --git a/mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.h b/mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.h index a0623e970..55e3a49d9 100644 --- a/mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.h +++ b/mcux/mcux-sdk-ng/drivers/mu1/fsl_mu.h @@ -1,6 +1,5 @@ /* - * Copyright 2021-2024 NXP - * All rights reserved. + * Copyright 2021-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -54,6 +53,29 @@ #define FSL_FEATURE_MU_GPI_COUNT 4U #endif +/*! + * @brief Maximum polling iterations for MU waiting loops + * + * This parameter defines the maximum number of iterations for any polling loop + * in the MU code before timing out and returning an error. + * + * It applies to all waiting loops in MU driver, such as waiting for TX register + * to be empty or waiting for RX register to be full. + * + * This is a count of loop iterations, not a time-based value. + * + * If defined as 0, polling loops will continue indefinitely until their exit condition + * is met, which could potentially cause the system to hang if a core becomes + * unresponsive. + */ +#ifndef MU1_BUSY_POLL_COUNT + #ifdef CONFIG_MU1_BUSY_POLL_COUNT + #define MU1_BUSY_POLL_COUNT CONFIG_MU1_BUSY_POLL_COUNT + #else + #define MU1_BUSY_POLL_COUNT 0U + #endif +#endif + /*! * @brief MU status flags. */ @@ -416,12 +438,18 @@ static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint3 * @brief Blocks to send a message. * * This function waits until the TX register is empty and sends the message. + * If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and returns kStatus_Timeout. * * @param base MU peripheral base address. - * @param regIndex MU message register, see @ref mu_msg_reg_index_t. + * @param regIndex MU message register, see @ref mu_msg_reg_index_t. * @param msg Message to send. + * + * @return status_t + * @retval kStatus_Success Message sent successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for TX register to be empty. */ -void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); +status_t MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); /*! * @brief Reads a message from the RX register. @@ -452,12 +480,47 @@ static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex } /*! - * @brief Blocks to receive a message. + * @brief Blocks to receive a message with timeout protection. * * This function waits until the RX register is full and receives the message. + * If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout. + * + * This function provides the same blocking behavior as MU_ReceiveMsg() but + * with additional timeout protection to prevent system hangs if the other + * core becomes unresponsive or if hardware issues occur. + * + * @note Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. + * The difference is that this function includes timeout protection while + * MU_ReceiveMsg() waits indefinitely. * * @param base MU peripheral base address. - * @param regIndex MU message register, see @ref mu_msg_reg_index_t + * @param regIndex RX register index, see @ref mu_msg_reg_index_t. + * @param readValue Pointer to store the received message. + * + * @return status_t + * @retval kStatus_Success Message received successfully. + * @retval kStatus_InvalidArgument Invalid readValue pointer. + * @retval kStatus_Timeout Timeout occurred while waiting for RX register to be full. + */ +status_t MU_ReceiveMsgTimeout(MU_Type *base, uint32_t regIndex, uint32_t *readValue); + +/*! + * @brief Blocks to receive a message (infinite wait, no timeout protection). + * + * This function waits until the RX register is full and receives the message. + * This function will wait indefinitely until a message is received. + * + * @note Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. + * The difference is that MU_ReceiveMsgTimeout() includes timeout protection + * while this function waits indefinitely. + * + * @warning This function does not include timeout protection and may cause + * system hangs if the other core becomes unresponsive. For applications + * requiring timeout protection, use MU_ReceiveMsgTimeout() instead. + * + * @param base MU peripheral base address. + * @param regIndex RX register index, see @ref mu_msg_reg_index_t. * @return The received message. */ uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex); @@ -496,7 +559,7 @@ static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags) } /*! - * @brief Blocks setting the 3-bit MU flags reflect on the other MU side. + * brief Blocks setting the 3-bit MU flags reflect on the other MU side. * * This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are @@ -505,10 +568,17 @@ static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags) * the flags cannot be changed. This function waits for the MU status flag * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags. * + * If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout. + * * @param base MU peripheral base address. * @param flags The 3-bit MU flags to set. + * + * return status_t + * retval kStatus_Success Flags were set successfully. + * retval kStatus_Timeout Timeout occurred while waiting for flags to update. */ -void MU_SetFlags(MU_Type *base, uint32_t flags); +status_t MU_SetFlags(MU_Type *base, uint32_t flags); /*! * @brief Gets the current value of the 3-bit MU flags set by the other side. @@ -1033,15 +1103,37 @@ void MU_HoldOtherCoreReset(MU_Type *base); * recommended to interrupt processor B, because this function may affect the * ongoing processor B programs. * + * If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations if waiting for the other side + * to come out of reset takes too long. + * * @param base MU peripheral base address. + * @return status_t + * @retval kStatus_Success The MU was reset successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for the other side to come out of reset. + * + * @note For some platforms, only MU side A could use this function, check + * reference manual for details. */ -static inline void MU_ResetBothSides(MU_Type *base) +static inline status_t MU_ResetBothSides(MU_Type *base) { base->CR |= MU_CR_MUR_MASK; +#if MU1_BUSY_POLL_COUNT + uint32_t poll_count = MU1_BUSY_POLL_COUNT; +#endif /* MU1_BUSY_POLL_COUNT */ + while (0U != (base->SR & MU_SR_MURS_MASK)) { +#if MU1_BUSY_POLL_COUNT + if ((--poll_count) == 0u) + { + return kStatus_Timeout; + } +#endif /* MU1_BUSY_POLL_COUNT */ } + + return kStatus_Success; } #if !(defined(FSL_FEATURE_MU_NO_CLKE) && (0 != FSL_FEATURE_MU_NO_CLKE)) @@ -1080,6 +1172,10 @@ static inline void MU_SetClockOnOtherCoreEnable(MU_Type *base, bool enable) * This function could be used together with MU_BootOtherCore to control the * other core reset workflow. * + * If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout + * after the specified number of polling iterations and return kStatus_Timeout + * if waiting for the other core to enter or exit reset takes too long. + * * Example 1: Reset the other core, and no hold reset * @code * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); @@ -1087,10 +1183,12 @@ static inline void MU_SetClockOnOtherCoreEnable(MU_Type *base, bool enable) * In this example, the core at MU side B will reset with the specified boot mode. * * Example 2: Reset the other core and hold it, then boot the other core later. - * @code * Here the other core enters reset, and the reset is hold + * @code * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); + * @endcode * Current core boot the other core when necessary. + * @code * MU_BootOtherCore(MU_A, bootMode); * @endcode * @@ -1103,20 +1201,24 @@ static inline void MU_SetClockOnOtherCoreEnable(MU_Type *base, bool enable) * defined as 0. * * @param base MU peripheral base address. - * @param waitReset Wait the other core enters reset. Only work when there is CSSR0[RAIP] + * @param waitReset Wait the other core enters reset. Only work when there is CSSR0[RAIP]. * - true: Wait until the other core enters reset, if the other * core has masked the hardware reset, then this function will * be blocked. * - false: Don't wait the reset. - * @param holdReset Hold the other core reset or not. Only work when there is CCR0[RSTH] + * @param holdReset Hold the other core reset or not. Only work when there is CCR0[RSTH]. * - true: Hold the other core in reset, this function returns * directly when the other core enters reset. * - false: Don't hold the other core in reset, this function * waits until the other core out of reset. * @param bootMode Boot mode of the other core, if @p holdReset is true, this * parameter is useless. + * + * @return status_t + * @retval kStatus_Success The other core was reset successfully. + * @retval kStatus_Timeout Timeout occurred while waiting for the other core to enter or exit reset. */ -void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode); +status_t MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode); #endif /* FSL_FEATURE_MU_HAS_HR */ #if (defined(FSL_FEATURE_MU_HAS_HRM) && FSL_FEATURE_MU_HAS_HRM) diff --git a/mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt index 65194c52d..8119d1c8a 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt @@ -30,7 +30,7 @@ if(CONFIG_MCUX_COMPONENT_driver.netc_imx943) endif() if(CONFIG_MCUX_COMPONENT_driver.netc) - mcux_component_version(2.9.0) + mcux_component_version(2.10.2) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h index 1af5ac6eb..0166df6fe 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h @@ -50,7 +50,7 @@ */ /*! @brief Driver Version */ -#define FSL_NETC_DRIVER_VERSION (MAKE_VERSION(2, 9, 0)) +#define FSL_NETC_DRIVER_VERSION (MAKE_VERSION(2, 10, 1)) /*! @brief Macro to divides an address into a low 32 bits and a possible high 32 bits */ #define NETC_ADDR_LOW_32BIT(x) ((uint32_t)(x) & 0xFFFFFFFFU) @@ -1376,12 +1376,7 @@ typedef struct _netc_tb_ipf_cfge netc_host_reason_t hr : 4; /*!< Host Reason metadata when frame is redirected/copied to the switch management port */ uint32_t timecape : 1; /*!< Timestam capture enable */ -#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG - uint32_t rrt : 1; /*!< Report Receive Timestamp */ - uint32_t : 8; -#else uint32_t : 9; -#endif uint32_t fltaTgt; /*!< Target for selected switch forwarding action or filter action*/ } netc_tb_ipf_cfge_t; @@ -3646,8 +3641,23 @@ typedef union _netc_tx_bd uint32_t written : 1; /*!< Write-back flag. */ uint32_t : 5; } writeback; + + uint64_t dword[2]; } netc_tx_bd_t; + +static inline void NETC_ClearTxDescriptor(netc_tx_bd_t *txDesc) +{ + txDesc->dword[0] = 0; + txDesc->dword[1] = 0; +} + +static inline void NETC_CopyTxDescriptor(netc_tx_bd_t *txDescDst, netc_tx_bd_t *txDescSrc) +{ + txDescDst->dword[0] = txDescSrc->dword[0]; + txDescDst->dword[1] = txDescSrc->dword[1]; +} + /*! * @brief Receive Buffer Descriptor format. * @@ -3806,6 +3816,7 @@ typedef enum _netc_psi_msg_flags_t { kNETC_PsiRxMsgFromVsi1Flag = 0x2, /*!< Message receive interrupt enable, initiated by VSI1. */ kNETC_PsiRxMsgFromVsi2Flag = 0x4, /*!< Message receive interrupt enable, initiated by VSI2. */ + kNETC_PsiRxMsgFromVsi3Flag = 0x8, /*!< Message receive interrupt enable, initiated by VSI3. */ kNETC_PsiFLRFromVsi1Flag = 0x20000, /*!< Function level reset interrupt enable, initiated by VSI1. */ } netc_psi_msg_flags_t; @@ -3825,6 +3836,7 @@ typedef enum _netc_vsi_number { kNETC_Vsi1 = 0x1 << 1U, kNETC_Vsi2 = 0x1 << 2U, + kNETC_Vsi3 = 0x1 << 3U, /* Reserved for multiple VSIs. */ } netc_vsi_number_t; diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c index fb9b985c9..74b029c5b 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c @@ -819,7 +819,7 @@ status_t EP_SendFrameCommon(ep_handle_t *handle, } /* Get latest Tx BD address and clean it content. */ txDesTemp = &txBdRing->bdBase[txBdRing->producerIndex]; - (void)memset(txDesTemp, 0, sizeof(netc_tx_bd_t)); + NETC_ClearTxDescriptor(txDesTemp); #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET address = (uintptr_t)MEMORY_ConvertMemoryMapAddress((uintptr_t)(uint8_t *)txBuff->buffer, kMEMORY_Local2DMA); @@ -867,7 +867,7 @@ status_t EP_SendFrameCommon(ep_handle_t *handle, /* Increase producer index when first BD is extension BD. */ txBdRing->producerIndex = EP_IncreaseIndex(txBdRing->producerIndex, txBdRing->len); txDesTemp = &txBdRing->bdBase[txBdRing->producerIndex]; - txDesTemp->ext = txDesc[1].ext; + NETC_CopyTxDescriptor(txDesTemp, &txDesc[1]); bdIndex++; } } @@ -904,6 +904,9 @@ status_t EP_SendFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *fr netc_tx_bd_t txDesc[2] = {0}; uint8_t hwRing = ring; + NETC_ClearTxDescriptor(&txDesc[0]); + NETC_ClearTxDescriptor(&txDesc[1]); + if (ring >= handle->cfg.txRingUse) { /* Tx BD ring index is out of range */ @@ -1004,11 +1007,15 @@ netc_tx_frame_info_t *EP_ReclaimTxDescCommon(ep_handle_t *handle, if (frameInfo->isTsAvail) { frameInfo->timestamp = txDesc->writeback.timestamp; + } else { + frameInfo->timestamp = 0; } #if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) if (frameInfo->isTxTsIdAvail) { frameInfo->txtsid = (uint16_t)txDesc->writeback.txtsid; + } else { + frameInfo->txtsid = 0; } #endif frameInfo->status = (netc_ep_tx_status_t)txDesc->writeback.status; @@ -1072,7 +1079,6 @@ void EP_ReclaimTxDescriptor(ep_handle_t *handle, uint8_t ring) if (frameInfo != NULL) { (void)handle->cfg.reclaimCallback(handle, ring, frameInfo, handle->cfg.userData); - (void)memset(frameInfo, 0, sizeof(netc_tx_frame_info_t)); } } while (frameInfo != NULL); } @@ -1140,7 +1146,6 @@ status_t EP_GetRxFrameSizeCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, u else { /* Get Transmit Timestamp Reference Response messages */ - *length = rxDesc->writeback.bufLen; result = kStatus_NETC_RxTsrResp; } } diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c index 97beeb803..0ebecd524 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c @@ -238,7 +238,6 @@ static uint16_t EP_RxL2MFQueryDeleteEMTableEntry(ep_handle_t *handle, uint8_t si *(uint32_t *)(uintptr_t)&macAddr[m]; } - cmdBd.generic.addr = 0; cmdBd.generic.en = 1; cmdBd.generic.siBitMap = siBitMap; cmdBd.generic.index = result[i].index; @@ -997,6 +996,30 @@ static uint16_t EP_PsiHandleLinkSpeed(ep_handle_t *handle, uint8_t vsi, netc_psi return ret; } +static uint16_t EP_PsiHandleIpVersion(ep_handle_t *handle, uint8_t vsi, netc_psi_rx_msg_t *msgInfo) +{ + netc_msg_header_t *header = (netc_msg_header_t *)(uint32_t)(msgInfo->msgBuff); + uint16_t ret = (uint16_t)kNETC_MsgClassIpVersion << 8 | kNETC_MsgIpVersionNotAvail; + uint8_t version; + + switch (header->cmdId) + { + case (uint8_t)kNETC_MsgIpVersionMJ: + version = (handle->hw.global->IPBRR0 & ENETC_GLOBAL_IPBRR0_IP_MJ_MASK) >> ENETC_GLOBAL_IPBRR0_IP_MJ_SHIFT; + ret = (uint16_t)kNETC_MsgClassIpVersion << 8 | version; + break; + case (uint8_t)kNETC_MsgIpVersionMN: + version = (handle->hw.global->IPBRR0 & ENETC_GLOBAL_IPBRR0_IP_MN_MASK) >> ENETC_GLOBAL_IPBRR0_IP_MN_SHIFT; + ret = (uint16_t)kNETC_MsgClassIpVersion << 8 | version; + break; + default: + /* To avoid MISRA-C 2012 rule 16.4 issue. */ + break; + } + + return ret; +} + void EP_PsiNotifyLink(ep_handle_t *handle) { ENETC_SI_Type *base = handle->hw.si; @@ -1108,6 +1131,7 @@ void EP_PsiHandleRxMsg(ep_handle_t *handle, uint8_t vsi, netc_psi_rx_msg_t *msgI case (uint8_t)kNETC_MsgClassTimerSyncStatus: break; case (uint8_t)kNETC_MsgClassIpVersion: + code = EP_PsiHandleIpVersion(handle, vsi, msgInfo); break; default: /* To avoid MISRA-C 2012 rule 16.4 issue. */ @@ -1115,7 +1139,7 @@ void EP_PsiHandleRxMsg(ep_handle_t *handle, uint8_t vsi, netc_psi_rx_msg_t *msgI } out: - base->PSI_A.PSIMSGRR = ((uint32_t)vsi << 1U) | ((uint32_t)code << 16U); + base->PSI_A.PSIMSGRR = ((uint32_t)1U << vsi) | ((uint32_t)code << 16U); if (notify) { diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h index 6af7772f5..a0195bb9f 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h @@ -155,6 +155,15 @@ typedef enum _netc_msg_ip_version_cmd kNETC_MsgIpVersionCFG = 0x04U, } netc_msg_ip_version_cmd_t; +/*! + * @brief Get IP version class specific code + */ +typedef enum _netc_msg_ip_version_code +{ + kNETC_MsgIpVersionNotAvail = 0xffU, /* verion not available */ +} netc_msg_ip_version_code_t; + + /*! * @brief VSI-PSI message header format */ diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.c index 2959eeef0..e3ae3ec76 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.c @@ -765,9 +765,13 @@ status_t SWT_SendFrame(swt_handle_t *handle, void *context, swt_tx_opt *opt) { - netc_tx_bd_t txDesc[2] = {0}; + netc_tx_bd_t txDesc[2]; uint8_t hwRing; netc_tx_bdr_t *txBdRing; + + NETC_ClearTxDescriptor(&txDesc[0]); + NETC_ClearTxDescriptor(&txDesc[1]); + if (enMasquerade) { if (getSiNum(handle->epHandle->cfg.si) == 0U) @@ -858,7 +862,6 @@ void SWT_ReclaimTxDescriptor(swt_handle_t *handle, bool enMasquerade, uint8_t ri { (void)handle->cfg.reclaimCallback(handle, frameInfo, handle->cfg.userData); } - (void)memset(frameInfo, 0, sizeof(netc_tx_frame_info_t)); } } while (frameInfo != NULL); } diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.h index 52698e12a..183678ee2 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.h @@ -1590,6 +1590,19 @@ status_t SWT_FMUpdateTableEntry(swt_handle_t *handle, netc_tb_fm_config_t *confi */ status_t SWT_FMDelTableEntry(swt_handle_t *handle, uint32_t entryID); +/*! + * @brief Query table entry in Frame Modification Table + * + * The provided ID must be table index. Error return if the id is action encoded id. + * + * @param handle + * @param entryID + * @param config + * @return status_t + * @return See @ref netc_cmd_error_t + */ +status_t SWT_FMQueryTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_fm_config_t *config); + /*! * @brief Get word number (word size is 24 bytes) of Frame Modification data table * @note This is a static bounded index table, when update or query table, should satisifed: diff --git a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c index 281ca75fa..da576427e 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c +++ b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c @@ -810,7 +810,7 @@ status_t NETC_QuerySGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, n { netc_cmd_bd_t cmdBd = {0}; status_t status = kStatus_Success; - (void)memset(handle->buffer, 0, sizeof(netc_tb_sgi_rsp_data_t)); + (void)memset(handle->buffer, 0, sizeof(netc_tb_sgi_req_data_t)); handle->buffer->sgi.request.entryID = entryID; handle->buffer->sgi.request.commonHeader.updateActions = 0U; handle->buffer->sgi.request.commonHeader.queryActions = 0U; @@ -1153,7 +1153,7 @@ status_t NETC_GetTGSOperationList(netc_cbdr_handle_t *handle, netc_tb_tgs_gcl_t { return kStatus_InvalidArgument; } - (void)memset(handle->buffer, 0, sizeof(netc_tb_tgs_data_t)); + (void)memset(handle->buffer, 0, sizeof(netc_tb_tgs_req_data_t)); handle->buffer->tgs.request.entryID = gcl->entryID; handle->buffer->tgs.request.commonHeader.updateActions = 0U; handle->buffer->tgs.request.commonHeader.queryActions = 0U; diff --git a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_si.h b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_si.h index cc591c948..ea40de622 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_si.h +++ b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_si.h @@ -27,7 +27,7 @@ /*! @brief Defines for read format. */ #define NETC_SI_TXDESCRIP_RD_FL(n) (((uint32_t)(n) & 0x03U) << 27U) #define NETC_SI_TXDESCRIP_RD_TSE_MASK (1UL << 25U) -#define NETC_SI_TXDESCRIP_RD_TXSTART(n) ((uint32_t)(n) & 0x1fffffUL) +#define NETC_SI_TXDESCRIP_RD_TXSTART(n) ((uint32_t)(n) & 0x1FFFFFFUL) #if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) #define NETC_SI_TXDESCRIP_RD_DR(n) (((uint32_t)(n) & 0x3U) << 10U) #define NETC_SI_TXDESCRIP_RD_IPV(n) (((uint32_t)(n) & 0x7U) << 12U) diff --git a/mcux/mcux-sdk-ng/drivers/ostimer/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/ostimer/CMakeLists.txt index 43d311680..2f1c507f1 100644 --- a/mcux/mcux-sdk-ng/drivers/ostimer/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/ostimer/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.ostimer) - mcux_component_version(2.2.4) + mcux_component_version(2.2.5) mcux_add_source(SOURCES fsl_ostimer.h fsl_ostimer.c) diff --git a/mcux/mcux-sdk-ng/drivers/ostimer/fsl_ostimer.c b/mcux/mcux-sdk-ng/drivers/ostimer/fsl_ostimer.c index aa21eeeb9..589942fda 100644 --- a/mcux/mcux-sdk-ng/drivers/ostimer/fsl_ostimer.c +++ b/mcux/mcux-sdk-ng/drivers/ostimer/fsl_ostimer.c @@ -246,10 +246,10 @@ void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) * * This function will set a match value for OSTIMER with an optional callback. And this callback * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * Please note that, the data format may be gray-code, if so, please using OSTIMER_SetMatchValue(). * * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) + * @param count OSTIMER timer match value.(Value may be gray-code format) * * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. @@ -294,7 +294,10 @@ status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_ca * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. */ decValueTimer = OSTIMER_GetCurrentTimerValue(base); - if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && +#if !(defined(FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER) && FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER) + tmp = OSTIMER_GrayToDecimal(tmp); +#endif /* FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER */ + if ((decValueTimer >= tmp) && (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) { status = kStatus_Fail; @@ -318,26 +321,30 @@ status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_ca * * @param base OSTIMER peripheral base address. * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in - * API. ) + * API if the IP counter is gray encoded. ) * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). * @retval kStatus_Success - Set match value and enable interrupt Successfully. * @retval kStatus_Fail - Set match value fail. */ status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) { +#if (defined(FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER) && FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER) + return OSTIMER_SetMatchRawValue(base, count, cb); +#else uint64_t tmp = OSTIMER_DecimalToGray(count); return OSTIMER_SetMatchRawValue(base, tmp, cb); +#endif /* FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER */ } /*! * @brief Get current timer count value from OSTIMER. * * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * If the RAW value of timer count is gray code format, it will be translated to decimal data internally. * * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will formated to decimal value. + * @return Value of OSTIMER which will be formated to decimal value. */ uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) { @@ -345,17 +352,21 @@ uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) tmp = OSTIMER_GetCurrentTimerRawValue(base); +#if (defined(FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER) && FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER) + return tmp; +#else return OSTIMER_GrayToDecimal(tmp); +#endif /* FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER */ } /*! * @brief Get the capture value from OSTIMER. * * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * If the RAW value of timer count is gray code format, it will be translated to decimal data internally. * * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. + * @return Value of capture register, data format is decimal. */ uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) { @@ -363,7 +374,11 @@ uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) tmp = OSTIMER_GetCaptureRawValue(base); +#if (defined(FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER) && FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER) + return tmp; +#else return OSTIMER_GrayToDecimal(tmp); +#endif /* FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER */ } void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) diff --git a/mcux/mcux-sdk-ng/drivers/ostimer/fsl_ostimer.h b/mcux/mcux-sdk-ng/drivers/ostimer/fsl_ostimer.h index 41eda48c7..9fa164851 100644 --- a/mcux/mcux-sdk-ng/drivers/ostimer/fsl_ostimer.h +++ b/mcux/mcux-sdk-ng/drivers/ostimer/fsl_ostimer.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief OSTIMER driver version. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) +#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) /*! @} */ /*! @@ -112,10 +112,10 @@ void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); * * This function will set a match value for OSTIMER with an optional callback. And this callback * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * Please note that, the data format may be gray-code, if so, please using OSTIMER_SetMatchValue(). * * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) + * @param count OSTIMER timer match value.(Value may be gray-code format) * * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. @@ -131,7 +131,7 @@ status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_ca * * @param base OSTIMER peripheral base address. * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code - * internally.) + * in API if the IP counter is gray encoded.) * * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). * @retval kStatus_Success - Set match value and enable interrupt Successfully. @@ -163,6 +163,39 @@ static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) base->MATCH_H = (uint32_t)(value >> 32U); } +/*! + * @brief Get the match value from OSTIMER. + * + * This function will get the match value from OSTIMER. + * The value of timer match is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Value of match register, data format is gray code. + */ +static inline uint64_t OSTIMER_GetMatchRegister(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->MATCH_L; + tmp |= (uint64_t)(base->MATCH_H) << 32U; + + return tmp; +} + +/*! + * @brief Get the match value from OSTIMER. + * + * This function will get a match value from OSTIMER. + * + * @param base OSTIMER peripheral base address. + * @return Value of match register. + */ +static inline uint64_t OSTIMER_GetMatchValue(OSTIMER_Type *base) +{ + uint64_t value = OSTIMER_GetMatchRegister(base); + return OSTIMER_GrayToDecimal(value); +} + /*! * @brief Enable the OSTIMER counter match interrupt. * @@ -192,11 +225,11 @@ static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base) /*! * @brief Get current timer raw count value from OSTIMER. * - * This function will get a gray code type timer count value from OS timer register. - * The raw value of timer count is gray code format. + * This function will get the timer count value from OS timer register. + * The raw value of timer count may be gray code format. * * @param base OSTIMER peripheral base address. - * @return Raw value of OSTIMER, gray code format. + * @return Raw value of OSTIMER, may be gray code format. */ static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) { @@ -212,7 +245,7 @@ static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) * @brief Get current timer count value from OSTIMER. * * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * If the RAW value of timer count is gray code format, it will be translated to decimal data internally. * * @param base OSTIMER peripheral base address. * @return Value of OSTIMER which will be formated to decimal value. @@ -222,11 +255,11 @@ uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); /*! * @brief Get the capture value from OSTIMER. * - * This function will get a captured gray-code value from OSTIMER. - * The Raw value of timer capture is gray code format. + * This function will get a captured value from OSTIMER. + * The Raw value of timer capture may be gray code format. * * @param base OSTIMER peripheral base address. - * @return Raw value of capture register, data format is gray code. + * @return Raw value of capture register, data format may be gray code. */ static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) { @@ -242,7 +275,7 @@ static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) * @brief Get the capture value from OSTIMER. * * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * If the RAW value of timer count is gray code format, it will be translated to decimal data internally. * * @param base OSTIMER peripheral base address. * @return Value of capture register, data format is decimal. diff --git a/mcux/mcux-sdk-ng/drivers/pdm/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/pdm/CMakeLists.txt index 718b7fead..efc7c4d4c 100644 --- a/mcux/mcux-sdk-ng/drivers/pdm/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/pdm/CMakeLists.txt @@ -21,7 +21,7 @@ if(CONFIG_MCUX_COMPONENT_driver.pdm_sdma) endif() if(CONFIG_MCUX_COMPONENT_driver.pdm) - mcux_component_version(2.9.1) + mcux_component_version(2.9.3) mcux_add_source(SOURCES fsl_pdm.h fsl_pdm.c) diff --git a/mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.c b/mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.c index 54533c785..afb0aff7e 100644 --- a/mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.c +++ b/mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.c @@ -171,7 +171,15 @@ static status_t PDM_ValidateSrcClockRate(uint32_t channelMask, { if (((channelMask >> i) & 0x01U) != 0U) { - enabledChannel++; + // Prevent potential addition overflow by capping at maximum value + if (enabledChannel < UINT32_MAX) + { + enabledChannel++; + } + else + { + enabledChannel = UINT32_MAX; + } } } @@ -213,11 +221,52 @@ static status_t PDM_ValidateSrcClockRate(uint32_t channelMask, } /* validate the minimum clock divider */ - /* 2U is for canculating k, 100U is for determing the specific float number of clock divider */ - uint32_t leftSide = (regDiv * k) / 2U * 100U; - uint32_t rightSide = ((10U + factor * enabledChannel) * 100U / (8U * osr)) * k / 2U; + /* 2U is for calculating k, 100U is for determining the specific float number of clock divider */ + + uint32_t leftSide = 0U; // Calculation: (regDiv * k) / 2U * 100U + + // Prevent potential multiplication overflow + if (regDiv < (UINT32_MAX / k)) + { + leftSide = (regDiv * k) / 2U * 100U; + } + else + { + return kStatus_Fail; + } + + uint32_t rightSide = 0U; // Calculation: ((10U + factor * enabledChannel) * 100U / (8U * osr)) * k / 2U + + // Prevent potential multiplication overflow + if ((10U + factor) < (UINT32_MAX / enabledChannel)) + { + rightSide = 10U + factor * enabledChannel; + } + else + { + return kStatus_Fail; + } + + if (rightSide < (UINT32_MAX / 100U)) + { + rightSide *= 100U; + rightSide /= (8U * osr); + } + else + { + return kStatus_Fail; + } + + if (rightSide < (UINT32_MAX / k)) + { + rightSide *= k / 2U; + } + else + { + return kStatus_Fail; + } - if (leftSide < rightSide) + if (leftSide < rightSide) // Compare calculated values to validate clock divider { return kStatus_Fail; } diff --git a/mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.h b/mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.h index 620b2b657..f146312ca 100644 --- a/mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.h +++ b/mcux/mcux-sdk-ng/drivers/pdm/fsl_pdm.h @@ -21,7 +21,7 @@ /*! @name Driver version */ /*! @{ */ -#define FSL_PDM_DRIVER_VERSION (MAKE_VERSION(2, 9, 2)) /*!< Version 2.9.2 */ +#define FSL_PDM_DRIVER_VERSION (MAKE_VERSION(2, 9, 3)) /*!< Version 2.9.3 */ /*! @} */ /*! @brief PDM XFER QUEUE SIZE */ diff --git a/mcux/mcux-sdk-ng/drivers/pls_pmu/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/pls_pmu/CMakeLists.txt index f87fb4ff5..5eafd20d2 100644 --- a/mcux/mcux-sdk-ng/drivers/pls_pmu/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/pls_pmu/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.pls_pmu) - mcux_component_version(2.0.0) + mcux_component_version(2.0.1) mcux_add_source(SOURCES fsl_pmu.h fsl_pmu.c) diff --git a/mcux/mcux-sdk-ng/drivers/pls_pmu/fsl_pmu.h b/mcux/mcux-sdk-ng/drivers/pls_pmu/fsl_pmu.h index 9b2cdcd09..b579cdfbd 100644 --- a/mcux/mcux-sdk-ng/drivers/pls_pmu/fsl_pmu.h +++ b/mcux/mcux-sdk-ng/drivers/pls_pmu/fsl_pmu.h @@ -26,8 +26,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief pls_pmu driver version 2.0.0. */ -#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief pls_pmu driver version 2.0.1. */ +#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @@ -75,8 +75,8 @@ static inline void PMU_EnableFixedDCDC(PMU_Type *base, bool enable) */ static inline void PMU_UpdateVDDCoreInActiveMode(PMU_Type *base, uint8_t value) { - base->VDD_CORE_PCONFIG = ((base->VDD_CORE_PCONFIG) & ~(PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_ACONFIG_MASK)) | \ - PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_ACONFIG(value); + base->VDD_CORE_PCONFIG = ((base->VDD_CORE_PCONFIG) & ~(PMU_VDD_CORE_PCONFIG_VDD_ACONFIG_MASK)) | \ + PMU_VDD_CORE_PCONFIG_VDD_ACONFIG(value); } /*! @@ -87,8 +87,8 @@ static inline void PMU_UpdateVDDCoreInActiveMode(PMU_Type *base, uint8_t value) */ static inline void PMU_UpdateVDDCoreInLpMode(PMU_Type *base, uint8_t value) { - base->VDD_CORE_PCONFIG = ((base->VDD_CORE_PCONFIG) & ~(PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_VOUTSEL_LPWR_MASK)) | \ - PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_VOUTSEL_LPWR(value); + base->VDD_CORE_PCONFIG = ((base->VDD_CORE_PCONFIG) & ~(PMU_VDD_CORE_PCONFIG_VDD_DSCONFIG_MASK)) | \ + PMU_VDD_CORE_PCONFIG_VDD_DSCONFIG(value); } /*! diff --git a/mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.c b/mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.c index d22c8d728..7f3dacb56 100644 --- a/mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.c +++ b/mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2022, 2024 NXP + * Copyright 2016-2022, 2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -506,6 +506,7 @@ status_t PWM_SetupPwm(PWM_Type *base, uint32_t pwmClock; uint16_t pulseCnt = 0, pwmHighPulse = 0; uint8_t i, polarityShift = 0, outputEnableShift = 0; + uint32_t temp; for (i = 0; i < numOfChnls; i++) { @@ -518,7 +519,10 @@ status_t PWM_SetupPwm(PWM_Type *base, /* Divide the clock by the prescale value */ pwmClock = (srcClock_Hz / (1UL << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); - pulseCnt = (uint16_t)(pwmClock / pwmFreq_Hz); + + temp = pwmClock / pwmFreq_Hz; + assert(temp <= 0xFFFFU); + pulseCnt = (uint16_t)(temp); /* Update register about period */ PWM_SetPeriodRegister(base, subModule, mode, pulseCnt); diff --git a/mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.h b/mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.h index a88786ec9..671e7e66b 100644 --- a/mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.h +++ b/mcux/mcux-sdk-ng/drivers/pwm/fsl_pwm.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2022, 2024 NXP + * Copyright 2016-2022, 2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -71,7 +71,7 @@ enum _pwm_value_register_mask /*! @brief PWM clock source selection.*/ typedef enum _pwm_clock_source { - kPWM_BusClock = 0U, /*!< The IPBus clock is used as the clock */ + kPWM_BusClock = 0U, /*!< Device specific IPBus clock, refer reference manual for frequency */ kPWM_ExternalClock, /*!< EXT_CLK is used as the clock */ kPWM_Submodule0Clock /*!< Clock of the submodule 0 (AUX_CLK) is used as the source clock */ } pwm_clock_source_t; diff --git a/mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.c b/mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.c index 504bb0fea..6e7385b24 100644 --- a/mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.c +++ b/mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.c @@ -418,7 +418,7 @@ void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_ base->ALPHA_B_CTRL_1 = (base->ALPHA_B_CTRL_1 & ~(PXP_ALPHA_B_CTRL_1_ROP_MASK | PXP_ALPHA_B_CTRL_1_ROP_ENABLE_MASK)) | - PXP_ALPHA_B_CTRL_1_ROP((uint32_t)config->ropMode) | PXP_ALPHA_B_CTRL_1_ROP_ENABLE((uint32_t)config->ropEnable); + PXP_ALPHA_B_CTRL_1_ROP((uint32_t)config->ropMode) | PXP_ALPHA_B_CTRL_1_ROP_ENABLE(config->ropEnable ? 1U : 0U); if (config->invertAlpha) { @@ -516,7 +516,7 @@ void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_confi assert(NULL != config); base->PS_CTRL = ((base->PS_CTRL & ~(PXP_PS_CTRL_FORMAT_MASK | PXP_PS_CTRL_WB_SWAP_MASK)) | - PXP_PS_CTRL_FORMAT(config->pixelFormat) | PXP_PS_CTRL_WB_SWAP(config->swapByte)); + PXP_PS_CTRL_FORMAT(config->pixelFormat) | PXP_PS_CTRL_WB_SWAP(config->swapByte ? 1U : 0U)); base->PS_BUF = PXP_ADDR_CPU_2_IP(config->bufferAddr); base->PS_UBUF = PXP_ADDR_CPU_2_IP(config->bufferAddrU); @@ -710,12 +710,12 @@ void PXP_BuildRect(PXP_Type *base, PXP_SetAlphaSurfaceOverlayColorKey(base, 0U, 0xFFFFFFFFUL); PXP_EnableAlphaSurfaceOverlayColorKey(base, true); #endif - PXP_SetAlphaSurfacePosition(base, 0, 0, width, height); + PXP_SetAlphaSurfacePosition(base, 0U, 0U, width, height); } else { /* No need to configure AS for formats that do not have alpha value. */ - PXP_SetAlphaSurfacePosition(base, 0xFFFFU, 0xFFFFU, 0, 0); + PXP_SetAlphaSurfacePosition(base, 0xFFFFU, 0xFFFFU, 0U, 0U); } /* Output config. */ @@ -976,9 +976,9 @@ status_t PXP_LoadLutTable( * param data Pointer to the data to write. * param memStartAddr The start address in the internal memory to write the data. */ -void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr) +void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint16_t bytesNum, uint8_t *data, uint16_t memStartAddr) { - assert(((uint32_t)memStartAddr + bytesNum) <= (uint32_t)PXP_INTERNAL_RAM_LUT_BYTE); + assert(((uint32_t)memStartAddr + (uint32_t)bytesNum) <= (uint32_t)PXP_INTERNAL_RAM_LUT_BYTE); base->INIT_MEM_CTRL = PXP_INIT_MEM_CTRL_ADDR(memStartAddr) | PXP_INIT_MEM_CTRL_SELECT(ram) | PXP_INIT_MEM_CTRL_START_MASK; @@ -1224,6 +1224,9 @@ static void PXP_StartRectCopy(PXP_Type *base, uint16_t height, pxp_as_pixel_format_t pixelFormat) { + assert(width >= 1U); + assert(height >= 1U); + pxp_output_buffer_config_t outputBufferConfig; pxp_as_buffer_config_t asBufferConfig; uint32_t intMask; @@ -1380,6 +1383,11 @@ status_t PXP_MemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32 /* For 512 not aligned part, copy by CPU. */ unalignedSize = size % 512U; + if ((unalignedSize > (0xFFFFFFFFUL - destAddr)) || (unalignedSize > (0xFFFFFFFFUL - srcAddr))) + { + return kStatus_InvalidArgument; + } + if (0UL != unalignedSize) { (void)memcpy((uint8_t *)destAddr, (uint8_t *)srcAddr, unalignedSize); @@ -1497,16 +1505,16 @@ status_t PXP_SetFetchEngineConfig(PXP_Type *base, ((uint32_t)config->flipMode << PXP_INPUT_FETCH_CTRL_CH0_HFLIP_SHIFT) | PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE((uint32_t)config->wordOrder) | ((uint32_t)config->interface << PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT) | - PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN((uint32_t)config->fetchFormat.enableblock) | - PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16((uint32_t)config->fetchFormat.blockSize16) | - PXP_INPUT_FETCH_CTRL_CH0_CH_EN((uint32_t)config->channelEnable); + PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN(config->fetchFormat.enableblock ? 1U : 0U) | + PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16(config->fetchFormat.blockSize16 ? 1U : 0U) | + PXP_INPUT_FETCH_CTRL_CH0_CH_EN(config->channelEnable ? 1U : 0U); ulcReg = (((uint32_t)config->ulcY) << 16U) | (uint32_t)config->ulcX; lrcReg = (((uint32_t)config->lrcY) << 16U) | (uint32_t)config->lrcX; fetchSizeReg = (((uint32_t)config->totalHeight) << 16U) | ((uint32_t)config->totalWidth); shiftCtrlReg = PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP((uint32_t)config->activeBits) | PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT((uint32_t)config->pixelFormat) | PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN((uint32_t)config->expandEnable) | - PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS((uint32_t)config->shiftConfig.shiftBypass); + PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(config->shiftConfig.shiftBypass ? 1U : 0U); if (!config->shiftConfig.shiftBypass) { shiftOffsetReg = (uint32_t)config->shiftConfig.component0.offset | @@ -1677,15 +1685,15 @@ status_t PXP_SetStoreEngineConfig(PXP_Type *base, uint32_t flagShiftWidthRegAddr = 0U; ctrlReg = PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES((uint32_t)config->storeFormat.burstLength) | - PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN((uint32_t)config->useFixedData) | - PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL((uint32_t)config->packInSelect) | + PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN(config->useFixedData ? 1U : 0U) | + PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL(config->packInSelect ? 1U : 0U) | ((uint32_t)config->interface << PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT) | // PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM((uint32_t)config->arraySize) | PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(0U) | - PXP_INPUT_STORE_CTRL_CH0_BLOCK_16((uint32_t)config->storeFormat.blockSize16) | - PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN((uint32_t)config->storeFormat.enableblock) | - PXP_INPUT_STORE_CTRL_CH0_CH_EN((uint32_t)config->channelEnable); - shiftCtrlReg = PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS((uint32_t)config->shiftConfig.shiftBypass) | + PXP_INPUT_STORE_CTRL_CH0_BLOCK_16(config->storeFormat.blockSize16 ? 1U : 0U) | + PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN(config->storeFormat.enableblock ? 1U : 0U) | + PXP_INPUT_STORE_CTRL_CH0_CH_EN(config->channelEnable ? 1U : 0U); + shiftCtrlReg = PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(config->shiftConfig.shiftBypass ? 1U : 0U) | ((uint32_t)config->yuvMode << PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT) | PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP((uint32_t)config->activeBits); sizeReg = (((uint32_t)config->totalHeight) << 16U) | ((uint32_t)config->totalWidth); @@ -1846,7 +1854,7 @@ status_t PXP_SetCfaConfig(PXP_Type *base, const pxp_cfa_config_t *config) base->CFA_CTRL = PXP_CFA_CTRL_CFA_ARRAY_HSIZE((uint32_t)config->arrayWidth) | PXP_CFA_CTRL_CFA_ARRAY_VSIZE((uint32_t)config->arrayHeight) | PXP_CFA_CTRL_CFA_IN_RGB444((uint32_t)config->pixelInFormat) | - PXP_CFA_CTRL_CFA_BYPASS((uint32_t)config->bypass); + PXP_CFA_CTRL_CFA_BYPASS(config->bypass ? 1U : 0U); base->CFA_SIZE = ((uint32_t)(config->totalWidth) << 16U) | (uint32_t)(config->totalHeight); /* Calculate how many registers to configure. If the value is not divisible then add 1 no matter the remainder. */ @@ -1884,10 +1892,10 @@ status_t PXP_SetHistogramConfig(PXP_Type *base, uint8_t num, const pxp_histogram uint32_t ctrlReg = 0U; uint32_t maskReg = 0U; - ctrlReg = PXP_HIST_A_CTRL_ENABLE((uint32_t)config->enable) | + ctrlReg = PXP_HIST_A_CTRL_ENABLE(config->enable ? 1U : 0U) | PXP_HIST_A_CTRL_PIXEL_OFFSET((uint32_t)config->lutValueOffset) | PXP_HIST_A_CTRL_PIXEL_WIDTH((uint32_t)config->lutValueWidth); - maskReg = PXP_HIST_A_MASK_MASK_EN((uint32_t)config->enableMask) | + maskReg = PXP_HIST_A_MASK_MASK_EN(config->enableMask ? 1U : 0U) | PXP_HIST_A_MASK_MASK_MODE((uint32_t)config->condition) | PXP_HIST_A_MASK_MASK_OFFSET((uint32_t)config->maskOffset) | PXP_HIST_A_MASK_MASK_WIDTH((uint32_t)config->maskWidth) | @@ -1991,7 +1999,7 @@ void PXP_WfeaInit(PXP_Type *base, bool ditherHandshake) length 4, normal border pixels select(not sw reg mode), 1 line fetch, done IRQ disabled. */ base->WFA_FETCH_CTRL = PXP_WFA_FETCH_CTRL_BF1_EN(1UL) | PXP_WFA_FETCH_CTRL_BF2_EN(1UL) | PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1UL) | - PXP_WFA_FETCH_CTRL_BF1_HSK_MODE((uint32_t)ditherHandshake); + PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(ditherHandshake ? 1U : 0U); /* Select pixel from bufer 2, set the right/left bit position on the original pixel as 0/3 */ /* Other default configurations: x/y offset=0, positive offset. */ base->WFA_ARRAY_PIXEL0_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1UL) | PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(3UL); @@ -2185,6 +2193,10 @@ void PXP_WfeaInit(PXP_Type *base, bool ditherHandshake) */ void PXP_SetWfeaConfig(PXP_Type *base, const pxp_wfea_engine_config_t *config) { + assert(config->updateWidth >= 1UL); + assert(config->updateHeight >= 1UL); + assert(((uint64_t)config->wbAddr + ((uint64_t)config->ulcX + (uint64_t)config->ulcY * (uint64_t)config->resX) * 2ULL) <= 0xFFFFFFFFULL); + /* Fetch */ base->WFA_FETCH_BUF1_ADDR = config->y4Addr; base->WFA_FETCH_BUF1_PITCH = config->updatePitch; @@ -2209,8 +2221,7 @@ void PXP_SetWfeaConfig(PXP_Type *base, const pxp_wfea_engine_config_t *config) base->WFE_A_STORE_ADDR_0_CH0 = PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(config->y4cAddr); base->WFE_A_STORE_ADDR_1_CH0 = 0U; /* Channel 1: 2 bytes per pixel. */ - base->WFE_A_STORE_ADDR_0_CH1 = PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( - (uint32_t)config->wbAddr + ((uint32_t)config->ulcX + (uint32_t)config->ulcY * (uint32_t)config->resX) * 2UL); + base->WFE_A_STORE_ADDR_0_CH1 = (uint32_t)config->wbAddr + ((uint32_t)config->ulcX + (uint32_t)config->ulcY * (uint32_t)config->resX) * 2UL; base->WFE_A_STORE_ADDR_1_CH1 = 0U; /* ALU */ diff --git a/mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.h b/mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.h index 7628a4c4e..b22e3cf47 100644 --- a/mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.h +++ b/mcux/mcux-sdk-ng/drivers/pxp/fsl_pxp.h @@ -1460,7 +1460,7 @@ static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_ case 1: base->ALPHA_B_CTRL_1 = (base->ALPHA_B_CTRL_1 & ~PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK) | - PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE((uint32_t)enable); + PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(enable ? 1U : 0U); break; default: @@ -2027,7 +2027,7 @@ static inline void PXP_Select8kLutBank(PXP_Type *base, pxp_lut_8k_bank_t bank) * @param data Pointer to the data to write. * @param memStartAddr The start address in the internal memory to write the data. */ -void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr); +void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint16_t bytesNum, uint8_t *data, uint16_t memStartAddr); /*! * @brief Set the dither final LUT data. @@ -2604,12 +2604,12 @@ static inline void PXP_EnableHistogram(PXP_Type *base, uint8_t num, bool enable) { case 0: base->HIST_A_CTRL = - (base->HIST_A_CTRL & ~PXP_HIST_A_CTRL_ENABLE_MASK) | PXP_HIST_A_CTRL_ENABLE((uint32_t)enable); + (base->HIST_A_CTRL & ~PXP_HIST_A_CTRL_ENABLE_MASK) | PXP_HIST_A_CTRL_ENABLE(enable ? 1U : 0U); break; case 1: base->HIST_B_CTRL = - (base->HIST_B_CTRL & ~PXP_HIST_B_CTRL_ENABLE_MASK) | PXP_HIST_B_CTRL_ENABLE((uint32_t)enable); + (base->HIST_B_CTRL & ~PXP_HIST_B_CTRL_ENABLE_MASK) | PXP_HIST_B_CTRL_ENABLE(enable ? 1U : 0U); break; default: diff --git a/mcux/mcux-sdk-ng/drivers/qspi/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/qspi/CMakeLists.txt index 159b27991..54ab0031e 100644 --- a/mcux/mcux-sdk-ng/drivers/qspi/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/qspi/CMakeLists.txt @@ -30,7 +30,7 @@ if(CONFIG_MCUX_COMPONENT_driver.qspi_edma) endif() if(CONFIG_MCUX_COMPONENT_driver.qspi) - mcux_component_version(2.3.0) + mcux_component_version(2.3.1) mcux_add_source(SOURCES fsl_qspi.h fsl_qspi.c) diff --git a/mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.c b/mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.c index 88e8867eb..711efbce0 100644 --- a/mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.c +++ b/mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.c @@ -187,8 +187,8 @@ void QSPI_GetDefaultQspiConfig(qspi_config_t *config) #if (!defined(FSL_FEATURE_QSPI_HAS_SOC_SPECIFIC_CONFIG)) || (!FSL_FEATURE_QSPI_HAS_SOC_SPECIFIC_CONFIG) #if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) - config->clockSource = 2U; - config->baudRate = 24000000U; + config->clockSource = 2U; + config->baudRate = 24000000U; #endif #endif config->AHBbufferMaster[0] = 0xE; @@ -226,6 +226,8 @@ void QSPI_Deinit(QuadSPI_Type *base) */ void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config) { + assert(FSL_FEATURE_QSPI_AMBA_BASE + config->flashA1Size > FSL_FEATURE_QSPI_AMBA_BASE); + uint32_t address = FSL_FEATURE_QSPI_AMBA_BASE + config->flashA1Size; uint32_t val = 0; uint32_t i = 0; @@ -238,7 +240,8 @@ void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config) address += config->flashA2Size; base->SFA2AD = address; #if defined(FSL_FEATURE_QSPI_SUPPORT_SINGLE_MODE) && (FSL_FEATURE_QSPI_SUPPORT_SINGLE_MODE) - /* For single mode configuration, you must write the same value to SFB1AD and SFB2AD registers that you write to the SFA2AD register. */ + /* For single mode configuration, you must write the same value to SFB1AD and SFB2AD registers that you write to the + * SFA2AD register. */ base->SFB1AD = address; base->SFB2AD = address; #endif /* FSL_FEATURE_QSPI_SUPPORT_SINGLE_MODE */ @@ -365,12 +368,15 @@ void QSPI_SetDqsConfig(QuadSPI_Type *base, qspi_dqs_config_t *config) void QSPI_SetDelayChainConfig(QuadSPI_Type *base, qspi_delay_chain_config_t *config) { QUADSPI->DLLCRA &= ~(QuadSPI_DLLCRA_SLV_UPD_MASK | QuadSPI_DLLCRA_SLV_DLL_BYPASS_MASK | QuadSPI_DLLCRA_SLV_EN_MASK | - QuadSPI_DLLCRA_SLV_DLY_COARSE_MASK | QuadSPI_DLLCRA_SLV_DLY_OFFSET_MASK | QuadSPI_DLLCRA_SLV_FINE_OFFSET_MASK | - QuadSPI_DLLCRA_FREQEN_MASK); - - QUADSPI->DLLCRA |= QuadSPI_DLLCRA_FREQEN(config->highFreqDelay) | QuadSPI_DLLCRA_SLV_FINE_OFFSET(config->fineDelay) | QuadSPI_DLLCRA_SLV_DLY_OFFSET(config->div16Delay) | - QuadSPI_DLLCRA_SLV_DLY_COARSE(config->coarseDelay) | QuadSPI_DLLCRA_SLV_EN(config->dqsDelayEnable) | QuadSPI_DLLCRA_SLV_DLL_BYPASS(config->coarseDelayEnable) | - QuadSPI_DLLCRA_SLV_UPD_MASK; + QuadSPI_DLLCRA_SLV_DLY_COARSE_MASK | QuadSPI_DLLCRA_SLV_DLY_OFFSET_MASK | + QuadSPI_DLLCRA_SLV_FINE_OFFSET_MASK | QuadSPI_DLLCRA_FREQEN_MASK); + + QUADSPI->DLLCRA |= (config->highFreqDelay ? QuadSPI_DLLCRA_FREQEN_MASK : 0U) | + (config->dqsDelayEnable ? QuadSPI_DLLCRA_SLV_EN_MASK : 0U) | + (config->coarseDelayEnable ? QuadSPI_DLLCRA_SLV_DLL_BYPASS_MASK : 0U) | + QuadSPI_DLLCRA_SLV_FINE_OFFSET(config->fineDelay) | + QuadSPI_DLLCRA_SLV_DLY_OFFSET(config->div16Delay) | + QuadSPI_DLLCRA_SLV_DLY_COARSE(config->coarseDelay) | QuadSPI_DLLCRA_SLV_UPD_MASK; } #endif @@ -443,7 +449,8 @@ void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index) QSPI_ClearCommandSequence(base, kQSPI_IPSeq); /* Write the seqid bit */ - base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_SEQID_MASK)) | QuadSPI_IPCR_SEQID(index / FSL_FEATURE_QSPI_LUT_SEQ_UNIT)); + base->IPCR = + ((base->IPCR & (~QuadSPI_IPCR_SEQID_MASK)) | QuadSPI_IPCR_SEQID(index / FSL_FEATURE_QSPI_LUT_SEQ_UNIT)); } /*! brief Executes AHB commands located in LUT table. @@ -457,7 +464,8 @@ void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index) { } QSPI_ClearCommandSequence(base, kQSPI_BufferSeq); - base->BFGENCR = ((base->BFGENCR & (~QuadSPI_BFGENCR_SEQID_MASK)) | QuadSPI_BFGENCR_SEQID(index / FSL_FEATURE_QSPI_LUT_SEQ_UNIT)); + base->BFGENCR = ((base->BFGENCR & (~QuadSPI_BFGENCR_SEQID_MASK)) | + QuadSPI_BFGENCR_SEQID(index / FSL_FEATURE_QSPI_LUT_SEQ_UNIT)); } /*! brief Updates the LUT table. @@ -468,7 +476,7 @@ void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index) */ void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd) { - assert(index <= (FSL_FEATURE_QSPI_LUT_DEPTH - FSL_FEATURE_QSPI_LUT_SEQ_UNIT)); + assert(index <= ((uint32_t)FSL_FEATURE_QSPI_LUT_DEPTH - FSL_FEATURE_QSPI_LUT_SEQ_UNIT)); assert((index % FSL_FEATURE_QSPI_LUT_SEQ_UNIT) == 0U); uint8_t i = 0; diff --git a/mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.h b/mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.h index 6594f61e0..9bfcff0ef 100644 --- a/mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.h +++ b/mcux/mcux-sdk-ng/drivers/qspi/fsl_qspi.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief QSPI driver version. */ -#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*! @} */ /*! @brief Macro functions for LUT table */ @@ -108,33 +108,33 @@ typedef enum _qspi_endianness enum _qspi_error_flags { #if (defined(FSL_FEATURE_QSPI_HAS_DATA_LEARNING) && FSL_FEATURE_QSPI_HAS_DATA_LEARNING) - kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */ + kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */ #endif - kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */ - kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */ - kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */ - kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */ - kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */ + kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */ + kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */ + kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */ + kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */ + kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */ #if (defined(FSL_FEATURE_QSPI_HAS_AHB_SEQ_ERR) && FSL_FEATURE_QSPI_HAS_AHB_SEQ_ERR) - kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */ + kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */ #endif #if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF) - kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */ -#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */ + kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */ #if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF) - kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */ -#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */ - kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */ + kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */ + kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */ #if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */ #endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */ kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, /*!< IP command trigger during AHB access error */ kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */ #if (defined(FSL_FEATURE_QSPI_HAS_AHB_CMD_PRIORITY) && FSL_FEATURE_QSPI_HAS_AHB_CMD_PRIORITY) - kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */ + kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */ #endif - kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */ - kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */ + kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */ + kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */ }; /*! @brief QSPI state bit */ @@ -143,33 +143,33 @@ enum _qspi_flags #if (defined(FSL_FEATURE_QSPI_HAS_DATA_LEARNING) && FSL_FEATURE_QSPI_HAS_DATA_LEARNING) kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */ #endif - kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */ + kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */ #if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA) - kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */ - kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */ -#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ + kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */ + kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ #if (defined(FSL_FEATURE_QSPI_HAS_TX_BUFF_ENOUGH_DATA) && FSL_FEATURE_QSPI_HAS_TX_BUFF_ENOUGH_DATA) - kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */ + kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */ #endif - kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */ - kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */ - kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK, /*!< Rx buffer watermark exceeded */ - kQSPI_AHB3BufferFull = QuadSPI_SR_AHB3FUL_MASK, /*!< AHB buffer 3 full*/ - kQSPI_AHB2BufferFull = QuadSPI_SR_AHB2FUL_MASK, /*!< AHB buffer 2 full */ - kQSPI_AHB1BufferFull = QuadSPI_SR_AHB1FUL_MASK, /*!< AHB buffer 1 full */ - kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK, /*!< AHB buffer 0 full */ - kQSPI_AHB3BufferNotEmpty = QuadSPI_SR_AHB3NE_MASK, /*!< AHB buffer 3 not empty */ - kQSPI_AHB2BufferNotEmpty = QuadSPI_SR_AHB2NE_MASK, /*!< AHB buffer 2 not empty */ - kQSPI_AHB1BufferNotEmpty = QuadSPI_SR_AHB1NE_MASK, /*!< AHB buffer 1 not empty */ - kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK, /*!< AHB buffer 0 not empty */ - kQSPI_AHBTransactionPending = QuadSPI_SR_AHBTRN_MASK, /*!< AHB access transaction pending */ + kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */ + kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */ + kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK, /*!< Rx buffer watermark exceeded */ + kQSPI_AHB3BufferFull = QuadSPI_SR_AHB3FUL_MASK, /*!< AHB buffer 3 full*/ + kQSPI_AHB2BufferFull = QuadSPI_SR_AHB2FUL_MASK, /*!< AHB buffer 2 full */ + kQSPI_AHB1BufferFull = QuadSPI_SR_AHB1FUL_MASK, /*!< AHB buffer 1 full */ + kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK, /*!< AHB buffer 0 full */ + kQSPI_AHB3BufferNotEmpty = QuadSPI_SR_AHB3NE_MASK, /*!< AHB buffer 3 not empty */ + kQSPI_AHB2BufferNotEmpty = QuadSPI_SR_AHB2NE_MASK, /*!< AHB buffer 2 not empty */ + kQSPI_AHB1BufferNotEmpty = QuadSPI_SR_AHB1NE_MASK, /*!< AHB buffer 1 not empty */ + kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK, /*!< AHB buffer 0 not empty */ + kQSPI_AHBTransactionPending = QuadSPI_SR_AHBTRN_MASK, /*!< AHB access transaction pending */ #if (defined(FSL_FEATURE_QSPI_HAS_AHB_CMD_PRIORITY) && FSL_FEATURE_QSPI_HAS_AHB_CMD_PRIORITY) - kQSPI_AHBCommandPriorityGranted = QuadSPI_SR_AHBGNT_MASK, /*!< AHB command priority granted */ + kQSPI_AHBCommandPriorityGranted = QuadSPI_SR_AHBGNT_MASK, /*!< AHB command priority granted */ #endif - kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */ - kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */ - kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */ - kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */ + kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */ + kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */ + kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */ + kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */ }; /*! @brief QSPI interrupt enable */ @@ -179,8 +179,8 @@ enum _qspi_interrupt_enable kQSPI_DataLearningFailInterruptEnable = (int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */ #endif - kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */ - kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */ + kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */ + kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */ kQSPI_IllegalInstructionInterruptEnable = QuadSPI_RSER_ILLINIE_MASK, /*!< Illegal instruction error interrupt enable */ kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */ @@ -194,12 +194,12 @@ enum _qspi_interrupt_enable #endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */ #if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF) kQSPI_AHBIllegalBurstSizeInterruptEnable = - QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */ -#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */ - kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */ + QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */ + kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */ #if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */ -#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */ +#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */ kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable = QuadSPI_RSER_IPAEIE_MASK, /*!< IP command trigger during AHB access error */ kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable = @@ -217,14 +217,14 @@ enum _qspi_interrupt_enable enum _qspi_dma_enable { #if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA) - kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */ -#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ - kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */ + kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ + kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */ #if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA) kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */ #else kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */ -#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */ }; /*! @brief Phrase shift number for DQS mode. */ @@ -248,9 +248,9 @@ typedef enum _qspi_dqs_read_sample_clock /*! @brief DQS configure features*/ typedef struct QspiDQSConfig { - uint32_t portADelayTapNum; /*!< Delay chain tap number selection for QSPI port A DQS */ + uint32_t portADelayTapNum; /*!< Delay chain tap number selection for QSPI port A DQS */ #if defined(QuadSPI_SOCCR_DQS_IFB_DELAY_CHAIN_SEL_MASK) - uint32_t portBDelayTapNum; /*!< Delay chain tap number selection for QSPI port B DQS*/ + uint32_t portBDelayTapNum; /*!< Delay chain tap number selection for QSPI port B DQS*/ #endif qspi_dqs_phrase_shift_t shift; /*!< Phase shift for internal DQS generation */ qspi_dqs_read_sample_clock_t rxSampleClock; /*!< Read sample clock for Dqs. */ @@ -270,8 +270,8 @@ typedef struct QspiConfig { #if (!defined(FSL_FEATURE_QSPI_HAS_SOC_SPECIFIC_CONFIG)) || (!FSL_FEATURE_QSPI_HAS_SOC_SPECIFIC_CONFIG) #if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) - uint32_t clockSource; /*!< Clock source for QSPI module */ - uint32_t baudRate; /*!< Serial flash clock baud rate */ + uint32_t clockSource; /*!< Clock source for QSPI module */ + uint32_t baudRate; /*!< Serial flash clock baud rate */ #endif #endif uint8_t txWatermark; /*!< QSPI transmit watermark value */ @@ -295,16 +295,16 @@ typedef struct _qspi_flash_config #endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */ uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */ #if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH) - uint32_t dataHoldTime; /*!< Data line hold time. */ -#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */ - uint32_t CSHoldTime; /*!< CS line hold time */ - uint32_t CSSetupTime; /*!< CS line setup time*/ - uint32_t cloumnspace; /*!< Column space size */ - uint32_t dataLearnValue; /*!< Data Learn value if enable data learn */ + uint32_t dataHoldTime; /*!< Data line hold time. */ +#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */ + uint32_t CSHoldTime; /*!< CS line hold time */ + uint32_t CSSetupTime; /*!< CS line setup time*/ + uint32_t cloumnspace; /*!< Column space size */ + uint32_t dataLearnValue; /*!< Data Learn value if enable data learn */ #if !defined(FSL_FEATURE_QSPI_HAS_NO_MCR_END) || (!FSL_FEATURE_QSPI_HAS_NO_MCR_END) - qspi_endianness_t endian; /*!< Flash data endianess. */ + qspi_endianness_t endian; /*!< Flash data endianess. */ #endif - bool enableWordAddress; /*!< If enable word address.*/ + bool enableWordAddress; /*!< If enable word address.*/ } qspi_flash_config_t; /*! @brief Transfer structure for QSPI */ diff --git a/mcux/mcux-sdk-ng/drivers/qspi/socs/mcxe31b/fsl_qspi_soc.c b/mcux/mcux-sdk-ng/drivers/qspi/socs/mcxe31b/fsl_qspi_soc.c index 3f4bc2c98..fb8904ba4 100644 --- a/mcux/mcux-sdk-ng/drivers/qspi/socs/mcxe31b/fsl_qspi_soc.c +++ b/mcux/mcux-sdk-ng/drivers/qspi/socs/mcxe31b/fsl_qspi_soc.c @@ -7,13 +7,13 @@ #include "fsl_qspi_soc.h" /*! brief Defines the QuadSPI SOCCR mask field. */ -#define QuadSPI_SOCCR_OBE_PULL_TIMING_RELAX_MASK (1U << 0) -#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_INPUT_MASK (1U << 1) -#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_OUTPUT_MASK (1U << 2) -#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_DRIVE_MASK (1U << 3) -#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_PULL_ENABLE_MASK (1U << 4) -#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_PULLUP_ENABLE_MASK (1U << 5) -#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_SLEW_RATE_MASK (1U << 6) +#define QuadSPI_SOCCR_OBE_PULL_TIMING_RELAX_MASK ((uint32_t)1U << 0) +#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_INPUT_MASK ((uint32_t)1U << 1) +#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_OUTPUT_MASK ((uint32_t)1U << 2) +#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_DRIVE_MASK ((uint32_t)1U << 3) +#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_PULL_ENABLE_MASK ((uint32_t)1U << 4) +#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_PULLUP_ENABLE_MASK ((uint32_t)1U << 5) +#define QuadSPI_SOCCR_QSPIA_SCK_DUMMY_PAD_SLEW_RATE_MASK ((uint32_t)1U << 6) /*! * brief Set QuadSPI Soc specific configuration. diff --git a/mcux/mcux-sdk-ng/drivers/qtmr_1/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/qtmr_1/CMakeLists.txt index 3db5854e8..9b13ff165 100644 --- a/mcux/mcux-sdk-ng/drivers/qtmr_1/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/qtmr_1/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.qtmr_1) - mcux_component_version(2.2.2) + mcux_component_version(2.3.0) mcux_add_source(SOURCES fsl_qtmr.c fsl_qtmr.h) diff --git a/mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.c b/mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.c index 29bd45900..c3fd682c1 100644 --- a/mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.c +++ b/mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2022 NXP + * Copyright 2017-2022, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -172,7 +172,7 @@ status_t QTMR_SetupPwm(TMR_Type *base, uint32_t srcClock_Hz) { uint32_t periodCount, highCount, lowCount; - uint16_t reg; + qtmrRegType reg; status_t status; if (dutyCyclePercent <= 100U) @@ -194,6 +194,13 @@ status_t QTMR_SetupPwm(TMR_Type *base, lowCount -= 1U; } +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) + base->CHANNEL[channel].COMP1 = lowCount; + base->CHANNEL[channel].COMP2 = highCount; + + base->CHANNEL[channel].CMPLD1 = lowCount; + base->CHANNEL[channel].CMPLD2 = highCount; +#else if ((highCount > 0xFFFFU) || (lowCount > 0xFFFFU)) { /* This should not be a 16-bit overflow value. If it is, change to a larger divider for clock source. */ @@ -207,6 +214,7 @@ status_t QTMR_SetupPwm(TMR_Type *base, /* Setup the pre-load registers for PWM output */ base->CHANNEL[channel].CMPLD1 = (uint16_t)lowCount; base->CHANNEL[channel].CMPLD2 = (uint16_t)highCount; +#endif reg = base->CHANNEL[channel].CSCTRL; /* Setup the compare load control for COMP1 and COMP2. @@ -280,7 +288,7 @@ void QTMR_SetupInputCapture(TMR_Type *base, bool reloadOnCapture, qtmr_input_capture_edge_t captureMode) { - uint16_t reg; + qtmrRegType reg; /* Clear the prior value for the input source for capture */ reg = base->CHANNEL[channel].CTRL & (uint16_t)(~TMR_CTRL_SCS_MASK); @@ -317,7 +325,7 @@ void QTMR_SetupInputCapture(TMR_Type *base, */ void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { - uint16_t reg; + qtmrRegType reg; reg = base->CHANNEL[channel].SCTRL; /* Compare interrupt */ @@ -363,7 +371,7 @@ void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uin */ void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { - uint16_t reg; + qtmrRegType reg; reg = base->CHANNEL[channel].SCTRL; /* Compare interrupt */ @@ -409,7 +417,7 @@ void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, ui uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel) { uint32_t enabledInterrupts = 0; - uint16_t reg; + qtmrRegType reg; reg = base->CHANNEL[channel].SCTRL; /* Compare interrupt */ @@ -455,7 +463,7 @@ uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t chan uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel) { uint32_t statusFlags = 0; - uint16_t reg; + qtmrRegType reg; reg = base->CHANNEL[channel].SCTRL; /* Timer compare flag */ @@ -499,7 +507,7 @@ uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel) */ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { - uint16_t reg; + qtmrRegType reg; reg = base->CHANNEL[channel].SCTRL; /* Timer compare flag */ @@ -551,13 +559,21 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin * param channel Quad Timer channel number * param ticks Timer period in units of ticks */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) +void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks) +#else void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks) +#endif { /* Set the length bit to reinitialize the counters on a match */ base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK; /* Reset LOAD register to reinitialize the counters */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) + base->CHANNEL[channel].LOAD &= ~TMR_LOAD_LOAD_MASK; +#else base->CHANNEL[channel].LOAD &= (uint16_t)(~TMR_LOAD_LOAD_MASK); +#endif if ((base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) != 0U) { @@ -580,7 +596,11 @@ void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint1 * param channel Quad Timer channel number * param ticks Timer period in units of ticks. */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) +void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks) +#else void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks) +#endif { base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK; @@ -606,7 +626,7 @@ void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint */ void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { - uint16_t reg; + qtmrRegType reg; reg = base->CHANNEL[channel].DMA; /* Input Edge Flag DMA Enable */ @@ -639,7 +659,7 @@ void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t m */ void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) { - uint16_t reg; + qtmrRegType reg; reg = base->CHANNEL[channel].DMA; /* Input Edge Flag DMA Enable */ @@ -671,7 +691,7 @@ void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t */ void QTMR_SetPwmOutputToIdle(TMR_Type *base, qtmr_channel_selection_t channel, bool idleStatus) { - uint16_t reg = base->CHANNEL[channel].SCTRL; + qtmrRegType reg = base->CHANNEL[channel].SCTRL; /* Stop qtimer channel counter first */ base->CHANNEL[channel].CTRL &= (uint16_t)(~TMR_CTRL_CM_MASK); @@ -717,7 +737,7 @@ void QTMR_SetPwmClockMode(TMR_Type *base, qtmr_channel_selection_t channel, qtmr { assert((uint32_t)prescaler > 7U); - uint16_t reg = base->CHANNEL[channel].CTRL; + qtmrRegType reg = base->CHANNEL[channel].CTRL; /* Clear qtimer channel counter mode */ base->CHANNEL[channel].CTRL = reg & (uint16_t)(~TMR_CTRL_CM_MASK); diff --git a/mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.h b/mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.h index 537125a74..d141a3282 100644 --- a/mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.h +++ b/mcux/mcux-sdk-ng/drivers/qtmr_1/fsl_qtmr.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2022 NXP + * Copyright 2017-2022, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -27,9 +27,15 @@ /*! @name Driver version */ /*! @{ */ -#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version */ +#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version */ /*! @} */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) +typedef uint32_t qtmrRegType; +#else +typedef uint16_t qtmrRegType; +#endif + /*! @brief Quad Timer primary clock source selection*/ typedef enum _qtmr_primary_count_source { @@ -360,7 +366,11 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin * @param channel Quad Timer channel number * @param ticks Timer period in units of ticks */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) +void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks); +#else void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks); +#endif /*! * @brief Set compare value. @@ -371,7 +381,11 @@ void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint1 * @param channel Quad Timer channel number * @param ticks Timer period in units of ticks. */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) +void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks); +#else void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks); +#endif /*! * @brief Set load value. @@ -382,11 +396,19 @@ void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint * @param channel Quad Timer channel number * @param value Load register initialization value. */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) +static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t value) +{ + base->CHANNEL[channel].LOAD &= ~TMR_LOAD_LOAD_MASK; + base->CHANNEL[channel].LOAD = value; +} +#else static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t value) { base->CHANNEL[channel].LOAD &= (uint16_t)(~TMR_LOAD_LOAD_MASK); base->CHANNEL[channel].LOAD = value; } +#endif /*! * @brief Reads the current timer counting value. @@ -401,7 +423,11 @@ static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t ch * * @return Current counter value in ticks */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) +static inline uint32_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel) +#else static inline uint16_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel) +#endif { return base->CHANNEL[channel].CNTR; } @@ -421,6 +447,16 @@ static inline uint16_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_se * @param channel Quad Timer channel number * @param clockSource Quad Timer clock source */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) +static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource) +{ + uint32_t reg = base->CHANNEL[channel].CTRL; + + reg &= ~TMR_CTRL_CM_MASK; + reg |= TMR_CTRL_CM(clockSource); + base->CHANNEL[channel].CTRL = reg; +} +#else static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource) { uint16_t reg = base->CHANNEL[channel].CTRL; @@ -429,6 +465,7 @@ static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t chan reg |= TMR_CTRL_CM(clockSource); base->CHANNEL[channel].CTRL = reg; } +#endif /*! * @brief Stops the Quad Timer counter. @@ -436,10 +473,17 @@ static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t chan * @param base Quad Timer peripheral base address * @param channel Quad Timer channel number */ +#if (defined(FSL_FEATURE_TMR_HAS_32BIT_REGISTER) && FSL_FEATURE_TMR_HAS_32BIT_REGISTER) +static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel) +{ + base->CHANNEL[channel].CTRL &= ~TMR_CTRL_CM_MASK; +} +#else static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel) { base->CHANNEL[channel].CTRL &= (uint16_t)(~TMR_CTRL_CM_MASK); } +#endif /*! @}*/ diff --git a/mcux/mcux-sdk-ng/drivers/rdc_sema42/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/rdc_sema42/CMakeLists.txt index f10bc79ba..645b26f2b 100644 --- a/mcux/mcux-sdk-ng/drivers/rdc_sema42/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/rdc_sema42/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.rdc_sema42) - mcux_component_version(2.0.4) + mcux_component_version(2.0.5) mcux_add_source(SOURCES fsl_rdc_sema42.h fsl_rdc_sema42.c) diff --git a/mcux/mcux-sdk-ng/drivers/rdc_sema42/fsl_rdc_sema42.c b/mcux/mcux-sdk-ng/drivers/rdc_sema42/fsl_rdc_sema42.c index 2444ad513..b9b360a19 100644 --- a/mcux/mcux-sdk-ng/drivers/rdc_sema42/fsl_rdc_sema42.c +++ b/mcux/mcux-sdk-ng/drivers/rdc_sema42/fsl_rdc_sema42.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020, 2022 NXP + * Copyright 2017-2020, 2022, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -25,6 +25,8 @@ /* Compatible remap. */ #define RDC_SEMAPHORE_GATE_LDOM(x) RDC_SEMAPHORE_GATE0_LDOM(x) #define RDC_SEMAPHORE_GATE_GTFSM(x) RDC_SEMAPHORE_GATE0_GTFSM(x) +#define RDC_SEMAPHORE_GATE_GTFSM_MASK RDC_SEMAPHORE_GATE0_GTFSM_MASK +#define RDC_SEMAPHORE_GATE_GTFSM_SHIFT RDC_SEMAPHORE_GATE0_GTFSM_SHIFT #define RDC_SEMAPHORE_GATE_LDOM_MASK RDC_SEMAPHORE_GATE0_LDOM_MASK #define RDC_SEMAPHORE_GATE_LDOM_SHIFT RDC_SEMAPHORE_GATE0_LDOM_SHIFT #endif @@ -128,6 +130,7 @@ void RDC_SEMA42_Deinit(RDC_SEMAPHORE_Type *base) status_t RDC_SEMA42_TryLock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId) { assert(gateNum < RDC_SEMA42_GATE_COUNT); + assert(masterIndex < (RDC_SEMAPHORE_GATE_GTFSM_MASK >> RDC_SEMAPHORE_GATE_GTFSM_SHIFT)); status_t status = kStatus_Success; uint8_t regGate; diff --git a/mcux/mcux-sdk-ng/drivers/rdc_sema42/fsl_rdc_sema42.h b/mcux/mcux-sdk-ng/drivers/rdc_sema42/fsl_rdc_sema42.h index b7710b321..1761a16bf 100644 --- a/mcux/mcux-sdk-ng/drivers/rdc_sema42/fsl_rdc_sema42.h +++ b/mcux/mcux-sdk-ng/drivers/rdc_sema42/fsl_rdc_sema42.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020, 2022 NXP + * Copyright 2017-2020, 2022, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief RDC_SEMA42 driver version */ -#define FSL_RDC_SEMA42_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +#define FSL_RDC_SEMA42_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*! @} */ /*! @brief The number to reset all RDC_SEMA42 gates. */ diff --git a/mcux/mcux-sdk-ng/drivers/rtc/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/rtc/CMakeLists.txt index 07d85b84a..9fc928485 100644 --- a/mcux/mcux-sdk-ng/drivers/rtc/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/rtc/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.rtc) - mcux_component_version(2.3.3) + mcux_component_version(2.4.0) mcux_add_source(SOURCES fsl_rtc.c fsl_rtc.h) diff --git a/mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.c b/mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.c index 3b41b559d..a4103c7ce 100644 --- a/mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.c +++ b/mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.c @@ -118,6 +118,10 @@ static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) * represented in the hours, minutes and seconds field*/ seconds += ((uint32_t)datetime->day - 1U); /* For leap year if month less than or equal to Febraury, decrement day counter*/ + /* + * $Branch Coverage Justification$ + * ((0U == (datetime->year & 3U)) && (datetime->month <= 2U) && 0U == seconds) cannot be covered, when it is leap year(>1970), the seconds cannot be 0U + */ if ((0U == (datetime->year & 3U)) && (datetime->month <= 2U) && 0U != seconds) { seconds--; @@ -248,13 +252,19 @@ void RTC_Init(RTC_Type *base, const rtc_config_t *config) reg &= ~(RTC_CR_WPS_MASK); reg |= RTC_CR_WPS(config->wakeupSelect ? 1U : 0U); #endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */ + +#if !(defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT == 0) + reg &= ~RTC_CR_CLKO_MASK; + reg |= RTC_CR_CLKO(config->clockOutput ? 1U : 0U); +#endif /* FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT */ + base->CR = reg; /* Configure the RTC time compensation register */ base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); #if defined(FSL_FEATURE_RTC_HAS_TSIC) && FSL_FEATURE_RTC_HAS_TSIC - /* Configure RTC timer seconds interrupt to be generated once per second */ + /* Configure RTC timer seconds interrupt to be generated once per second and disable the interrupt */ base->IER &= ~(RTC_IER_TSIC_MASK | RTC_IER_TSIE_MASK); #endif } @@ -279,6 +289,10 @@ void RTC_GetDefaultConfig(rtc_config_t *config) /* Initializes the configure structure to zero. */ (void)memset(config, 0, sizeof(*config)); +#if !(defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT == 0) + /* Clock output is disabled by default */ + config->clockOutput = false; +#endif /* FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT */ /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */ config->wakeupSelect = false; /* Registers cannot be written when locked */ @@ -902,3 +916,33 @@ status_t RTC_IncrementMonotonicCounter(RTC_Type *base) } #endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ + +#if defined(FSL_FEATURE_RTC_HAS_TSIC) && FSL_FEATURE_RTC_HAS_TSIC + +/*! + * brief Sets the RTC timer seconds interrupt frequency. + * + * This function sets the RTC timer seconds interrupt frequency. + * + * param base RTC peripheral base address + * param freq The timer seconds interrupt frequency. This is a member of the + * enumeration ::rtc_timer_seconds_interrupt_frequency_t + */ +void RTC_SetTimerSecondsInterruptFrequency(RTC_Type *base, rtc_timer_seconds_interrupt_frequency_t freq) +{ + assert(freq < kRTC_TimerSecondsFrequency128Hz); + uint32_t reg = base->IER; + + reg &= ~(RTC_IER_TSIC_MASK); + reg |= RTC_IER_TSIC(freq); + + /* Enable the timer seconds interrupt if not enabled */ + if ((reg & RTC_IER_TSIE_MASK) != 0U) + { + reg |= RTC_IER_TSIE_MASK; + } + + base->IER = reg; +} + +#endif /* FSL_FEATURE_RTC_HAS_TSIC */ diff --git a/mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.h b/mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.h index b923b724b..e331deb7c 100644 --- a/mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.h +++ b/mcux/mcux-sdk-ng/drivers/rtc/fsl_rtc.h @@ -21,7 +21,7 @@ /*! @name Driver version */ /*! @{ */ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) /*!< Version 2.3.3 */ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) /*!< Version 2.4.0 */ /*! @} */ /*! @brief List of RTC interrupts */ @@ -86,9 +86,25 @@ typedef enum _rtc_osc_cap_load kRTC_Capacitor_8p = RTC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16 pF capacitor load */ } rtc_osc_cap_load_t; - #endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */ +#if defined(FSL_FEATURE_RTC_HAS_TSIC) && FSL_FEATURE_RTC_HAS_TSIC + +/*! @brief List of RTC Timer Seconds Interrupt Frequencies */ +typedef enum _rtc_timer_seconds_interrupt_frequency +{ + kRTC_TimerSecondsFrequency1Hz = 0U, /*!< Timer seconds frequency is 1Hz */ + kRTC_TimerSecondsFrequency2Hz = 1U, /*!< Timer seconds frequency is 2Hz */ + kRTC_TimerSecondsFrequency4Hz = 2U, /*!< Timer seconds frequency is 4Hz */ + kRTC_TimerSecondsFrequency8Hz = 3U, /*!< Timer seconds frequency is 8Hz */ + kRTC_TimerSecondsFrequency16Hz = 4U, /*!< Timer seconds frequency is 16Hz */ + kRTC_TimerSecondsFrequency32Hz = 5U, /*!< Timer seconds frequency is 32Hz */ + kRTC_TimerSecondsFrequency64Hz = 6U, /*!< Timer seconds frequency is 64Hz */ + kRTC_TimerSecondsFrequency128Hz = 7U /*!< Timer seconds frequency is 128Hz */ +} rtc_timer_seconds_interrupt_frequency_t; + +#endif /* FSL_FEATURE_RTC_HAS_TSIC */ + /*! @brief Structure is used to hold the date and time */ typedef struct _rtc_datetime { @@ -132,6 +148,11 @@ typedef struct _rtc_pin_config */ typedef struct _rtc_config { +#if !(defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT == 0) + bool clockOutput; /*!< true: The 32 kHz clock is not output to other + peripherals; false: The 32 kHz clock is output to other + peripherals */ +#endif /* FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT */ bool wakeupSelect; /*!< true: Wakeup pin outputs the 32 KHz clock; false:Wakeup pin used to wakeup the chip */ bool updateMode; /*!< true: Registers can be written even when locked under certain @@ -190,6 +211,7 @@ static inline void RTC_Deinit(RTC_Type *base) * * The default values are as follows. * @code + * config->clockOutput = false; * config->wakeupSelect = false; * config->updateMode = false; * config->supervisorAccess = false; @@ -541,6 +563,43 @@ static inline void RTC_EnableWakeUpPin(RTC_Type *base, bool enable) } #endif +#if !(defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT == 0) +/*! + * @brief Enables or disables the RTC 32 kHz clock output. + * + * This function enables or disables the RTC 32 kHz clock output. + * + * @param base RTC_Type base pointer. + * @param enable true to enable, false to disable. + */ +static inline void RTC_EnableClockOutput(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CR |= RTC_CR_CLKO_MASK; + } + else + { + base->CR &= ~RTC_CR_CLKO_MASK; + } +} +#endif /* FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT */ + +#if defined(FSL_FEATURE_RTC_HAS_TSIC) && FSL_FEATURE_RTC_HAS_TSIC + +/*! + * @brief Sets the RTC timer seconds interrupt frequency. + * + * This function sets the RTC timer seconds interrupt frequency. + * + * @param base RTC peripheral base address + * @param freq The timer seconds interrupt frequency. This is a member of the + * enumeration ::rtc_timer_seconds_interrupt_frequency_t + */ +void RTC_SetTimerSecondsInterruptFrequency(RTC_Type *base, rtc_timer_seconds_interrupt_frequency_t freq); + +#endif /* FSL_FEATURE_RTC_HAS_TSIC */ + #if defined(__cplusplus) } #endif diff --git a/mcux/mcux-sdk-ng/drivers/rtc_analog/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/rtc_analog/CMakeLists.txt new file mode 100644 index 000000000..799f463aa --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/rtc_analog/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +if(CONFIG_MCUX_COMPONENT_driver.rtc_analog) + mcux_component_version(2.0.0) + + mcux_add_source(SOURCES fsl_rtc.c fsl_rtc.h) + + mcux_add_include(INCLUDES .) + +endif() diff --git a/mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.c b/mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.c new file mode 100644 index 000000000..95627874c --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.c @@ -0,0 +1,1534 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rtc" +#endif + +#define YEAR_RANGE_START (2000U) +#define YEAR_RANGE_END (2099U) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Days in each month for a non-leap year */ +static const uint8_t daysInMonth[] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + +/* Days in each month for a leap year */ +static const uint8_t daysInMonthLeapYear[] = {0, 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + +/* Callback function for RTC events */ +static rtc_callback_t s_rtcCallback = NULL; + +/* Last watchdog timeout value */ +static uint32_t s_lastWdtTimeout = 0; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* Wait for RTC interface is idle. */ +static inline status_t RTC_WaitForInterfaceReady(RTC_Type *base); + +/* Check if the given year is a leap year */ +static bool RTC_IsLeapYear(uint16_t year); + +/* Check if the given date and time are valid */ +static bool RTC_ValidateDateTime(const rtc_datetime_t *datetime); + +/*! + * @brief Get the RTC operating mode. + * + * @param base RTC peripheral base address. + * @return The current RTC operating mode, kRTC_ModeTimeDate or kRTC_ModeFreeRunningCounter. + */ +static rtc_operating_mode_t RTC_GetOperatingMode(RTC_Type *base); + +/*! + * @brief Validates the BCD alarm configuration structure. + * + * This function checks if the alarm date/time fields are within valid ranges. + * Fields that are masked (set to be ignored) in the alarm configuration are not validated. + * + * @param alarmConfig Pointer to alarm configuration structure to validate + * @return true if configuration is valid, false if any enabled field is out of range + */ +static bool RTC_ValidateBCDAlarmDateTime(const rtc_bcd_alarm_config_t *alarmConfig); + +/*! + * @brief Validates the free running alarm configuration structure. + * + * This function validates: + * 1. In single shot mode, counter must not exceed 40 bits (0xFFFFFFFFFF) + * 2. In repeat mode, counter must not exceed 24 bits (0x00FFFFFF) + * + * @param alarmConfig Pointer to alarm configuration structure to validate + * @return true if configuration is valid, false if counter value exceeds limits + */ +static bool RTC_ValidateFreeRunAlarmCounter(const rtc_free_run_alarm_config_t *alarmConfig); + +/******************************************************************************* + * Code + ******************************************************************************/ +static inline status_t RTC_WaitForInterfaceReady(RTC_Type *base) +{ +#if defined(RTC_WAIT_INTERFACE_READY_TIMEOUT) && (RTC_WAIT_INTERFACE_READY_TIMEOUT > 0U) + uint32_t timeout = RTC_WAIT_INTERFACE_READY_TIMEOUT; +#endif + /* Wait until the RTC interface is ready (IF_READY bit is set) */ + while (!(base->CONFIG & RTC_CONFIG_IF_READY_MASK)) + { +#if defined(RTC_WAIT_INTERFACE_READY_TIMEOUT) && (RTC_WAIT_INTERFACE_READY_TIMEOUT > 0U) + if ((--timeout) == 0U) + { + /* Timeout occurred */ + return kStatus_Timeout; + } +#endif + } + return kStatus_Success; +} +static bool RTC_IsLeapYear(uint16_t year) +{ + if ((year % 4 == 0 && year % 100 != 0) || (year % 400 == 0)) + { + return true; + } + else + { + return false; + } +} + +static bool RTC_ValidateDateTime(const rtc_datetime_t *datetime) +{ + /* Check input parameters */ + if (datetime == NULL) + { + return false; + } + + /* Check year, month, day, hour, minute, second ranges */ + if ((datetime->year < 2000U) || (datetime->year > 2099U) || (datetime->month < 1U) || (datetime->month > 12U) || + (datetime->day < 1U) || (datetime->hour > 23U) || (datetime->minute > 59U) || (datetime->second > 59U) || + (datetime->hundredthOfSecond > 99U) || (datetime->dayOfWeek > 6U)) + { + return false; + } + + /* Check day of month validity based on month and leap year */ + const uint8_t *days = RTC_IsLeapYear(datetime->year) ? daysInMonthLeapYear : daysInMonth; + if (datetime->day > days[datetime->month]) + { + return false; + } + + return true; +} + +/*! + * @brief Validates the BCD alarm configuration structure. + * + * This function checks if the alarm date/time fields are within valid ranges. + * Fields that are masked (set to be ignored) in the alarm configuration are not validated. + * + * @param alarmConfig Pointer to alarm configuration structure to validate + * @return true if configuration is valid, false if any enabled field is out of range + */ +static bool RTC_ValidateBCDAlarmDateTime(const rtc_bcd_alarm_config_t *alarmConfig) +{ + /* Check input parameters */ + if (alarmConfig == NULL) + { + return false; + } + + /* Only validate fields that are not masked (i.e., will be used for matching) */ + + /* Check month if not masked */ + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreMonth) == 0U) + { + if (alarmConfig->month < 1U || alarmConfig->month > 12U) + { + return false; + } + } + + /* Check day if not masked */ + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreDay) == 0U) + { + if (alarmConfig->day < 1U || alarmConfig->day > 31U) + { + return false; + } + /* Note: We can't validate exact day of month since we don't have year info for leap year check */ + } + + /* Check day of week if not masked */ + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreDayOfWeek) == 0U) + { + if (alarmConfig->dayOfWeek > 6U) + { + return false; + } + } + + /* Check hour if not masked */ + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreHour) == 0U) + { + if (alarmConfig->hour > 23U) + { + return false; + } + } + + /* Check minute if not masked */ + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreMinute) == 0U) + { + if (alarmConfig->minute > 59U) + { + return false; + } + } + + /* Check second if not masked */ + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreSecond) == 0U) + { + if (alarmConfig->second > 59U) + { + return false; + } + } + + if (alarmConfig->hundredthOfSecond > 99U) + { + return false; + } + + return true; +} + +static bool RTC_ValidateFreeRunAlarmCounter(const rtc_free_run_alarm_config_t *alarmConfig) +{ + /* Check input parameters */ + if (alarmConfig == NULL) + { + return false; + } + + /* Validate counter value based on mode */ + if (alarmConfig->mode == kRTC_AlarmModeRepeat) + { + /* For repeat mode, counter must not exceed 24 bits (0x00FFFFFF) */ + if (alarmConfig->alarmCounter > 0x00FFFFFF) + { + return false; + } + } + else + { + /* For single shot mode, counter must not exceed 40 bits (0xFFFFFFFFFF) */ + if (alarmConfig->alarmCounter > 0xFFFFFFFFFF) + { + return false; + } + } + + return true; +} + +/*! + * brief Get the RTC operating mode. + * + * param base RTC peripheral base address. + * @return The current RTC operating mode. + */ +static rtc_operating_mode_t RTC_GetOperatingMode(RTC_Type *base) +{ + /* Wait until the RTC interface is ready (IF_READY bit is set) */ + while (!(base->CONFIG & RTC_CONFIG_IF_READY_MASK)) + { + } + return (base->CONFIG & RTC_CONFIG_FREE_RUNNING_MASK) ? kRTC_ModeFreeRunningCounter : kRTC_ModeTimeDate; +} + +/*! + * brief Fills the RTC configuration structure with default values. + * + * The default values are chosen for safe and common startup behavior. + * For example: + * code + * config->operatingMode = kRTC_ModeTimeDate; + * config->enableXtal32 = true; + * config->enable2kHzOutputSMM = false; + * config->alarmInitialEnable[0] = false; + * config->alarmInitialEnable[1] = false; + * config->alarmInitialEnable[2] = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->tamperConfig.enableGlobalTamper = false; + * config->tamperConfig.tamperInputConfig[0].enableTamperInput = false; + * config->tamperConfig.tamperInputConfig[0].polarity = kRTC_TamperPolarityLow; + * config->tamperConfig.tamperInputConfig[0].pullup = kRTC_TamperPullupDisabled; + * config->tamperConfig.tamperInputConfig[0].filter = kRTC_TamperFilterDisabled; + * config->tamperConfig.tamperInputConfig[1].enableTamperInput = false; + * config->tamperConfig.tamperInputConfig[1].polarity = kRTC_TamperPolarityLow; + * config->tamperConfig.tamperInputConfig[1].pullup = kRTC_TamperPullupDisabled; + * config->tamperConfig.tamperInputConfig[1].filter = kRTC_TamperFilterDisabled; + * config->aliveDetectorConfig.enableAliveDetector = false; + * config->aliveDetectorConfig.bypassAnalogAliveMechanism = false; + * config->aliveDetectorConfig.mechanismPeriod = 0U; + * endcode + * This function should be called before RTC_Init() if custom configuration is not fully provided. + * + * param config Pointer to the rtc_config_t structure to be filled. + */ +void RTC_GetDefaultConfig(rtc_config_t *config) +{ + /* Check input parameters */ + assert(config != NULL); + + /* Clear the structure */ + (void)memset(config, 0, sizeof(rtc_config_t)); + + /* Set default values */ + config->operatingMode = kRTC_ModeTimeDate; + config->enableXtal32 = true; + config->enable2kHzOutputSMM = true; + config->alarmInitialEnable[0] = false; + config->alarmInitialEnable[1] = false; + config->alarmInitialEnable[2] = false; + config->enableWatchdog = false; + config->watchdogTimeoutValue = 0U; + config->tamperConfig.enableGlobalTamper = false; + for (uint8_t i = 0U; i < RTC_MAX_TAMPER_INPUTS; ++i) + { + config->tamperConfig.tamperInputConfig[i].enableTamperInput = false; + config->tamperConfig.tamperInputConfig[i].polarity = kRTC_TamperPolarityLow; + config->tamperConfig.tamperInputConfig[i].pullup = kRTC_TamperPullupDisabled; + config->tamperConfig.tamperInputConfig[i].filter = kRTC_TamperFilterDisabled; + } + config->aliveDetectorConfig.enableAliveDetector = true; + config->aliveDetectorConfig.bypassAnalogAliveMechanism = false; + config->aliveDetectorConfig.mechanismPeriod = 0U; +} + +/*! + * brief Initializes the RTC peripheral. + * + * This function configures the RTC module according to the settings provided in the config structure. + * It setups initial operating mode, watchdog, tamper detection, and alive detector. + * + * param base RTC peripheral base address. + * param config Pointer to the user-defined rtc_config_t structure. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready, + */ +status_t RTC_Init(RTC_Type *base, const rtc_config_t *config) +{ + /* Check input parameters */ + assert(config != NULL); + uint32_t configReg = 0; + uint32_t aliveDetector = 0; + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* First perform a software reset */ + base->CONFIG |= RTC_CONFIG_SW_RST_MASK; + base->CONFIG &= ~RTC_CONFIG_SW_RST_MASK; + + /* Configure operating mode and enable the RTC */ + configReg = RTC_CONFIG_FREE_RUNNING(config->operatingMode == kRTC_ModeFreeRunningCounter ? 1U : 0U) | + RTC_CONFIG_ALARM0_DIS(config->alarmInitialEnable[0] ? 0U : 1U) | + RTC_CONFIG_ALARM1_DIS(config->alarmInitialEnable[1] ? 0U : 1U) | + RTC_CONFIG_ALARM2_DIS(config->alarmInitialEnable[2] ? 0U : 1U) | + RTC_CONFIG_K_EN(config->enable2kHzOutputSMM ? 1U : 0U) | + RTC_CONFIG_XTAL32_EN(config->enableXtal32 ? 1U : 0U); + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->CONFIG = configReg; + /* Configure watchdog timer */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->WDT_SET_VA = RTC_WDT_SET_VA_WDT_CNTR(config->watchdogTimeoutValue); + s_lastWdtTimeout = config->watchdogTimeoutValue; + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* WDOG_EN can only be enabled when WDT_SET_VA has non zero value */ + base->CONFIG |= RTC_CONFIG_WDOG_EN(config->enableWatchdog ? 1U : 0U); + + /* Configure tamper detection */ + for (uint8_t i = 0U; i < RTC_MAX_TAMPER_INPUTS; ++i) + { + RTC_ConfigureTamperInput(base, (rtc_tamper_input_id_t)i, &config->tamperConfig.tamperInputConfig[i]); + } + /* Clear tamper interrupt flags */ + RTC_ClearInterruptFlags(base, kRTC_AllStatusFlags); + + aliveDetector = RTC_RTC_ALV_DTCT_DTCT_EN(config->aliveDetectorConfig.enableAliveDetector ? 1U : 0U) | + RTC_RTC_ALV_DTCT_BYPASS(config->aliveDetectorConfig.bypassAnalogAliveMechanism ? 1U : 0U) | + RTC_RTC_ALV_DTCT_ACTV_PRD(config->aliveDetectorConfig.mechanismPeriod); + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->RTC_ALV_DTCT = aliveDetector; + + /* Enable RTC peripheral */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + + return kStatus_Success; +} + +/*! + * brief De-initializes the RTC peripheral. + * + * This function resets RTC registers to a default state and stops the RTC. + * + * param base RTC peripheral base address. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_Deinit(RTC_Type *base) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Disable the RTC */ + base->CONFIG &= ~RTC_CONFIG_EN_MASK; + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Reset the RTC */ + base->CONFIG |= RTC_CONFIG_SW_RST_MASK; + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->CONFIG &= ~RTC_CONFIG_SW_RST_MASK; + + return kStatus_Success; +} + +/*! + * brief Starts the RTC time counter. + * + * param base RTC peripheral base address + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_StartTimer(RTC_Type *base) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + + base->CONFIG |= RTC_CONFIG_EN_MASK; + + return kStatus_Success; +} + +/*! + * brief Stops the RTC time counter. + * + * param base RTC peripheral base address + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_StopTimer(RTC_Type *base) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + + base->CONFIG &= ~RTC_CONFIG_EN_MASK; + + return kStatus_Success; +} + +/*! + * brief Sets the current RTC date and time. + * + * Validates the provided date and time before setting. If the input is invalid, + * an error status is returned. + * + * param base RTC peripheral base address. + * param datetime Pointer to the rtc_datetime_t structure containing the new date and time. + * return kStatus_Success if the operation was successful, kStatus_Fail if RTC is not working in time date mode, + * kStatus_InvalidArgument if the input was invalid, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) +{ + /* Check input parameters */ + assert(datetime != NULL); + + /* Check if in time date mode */ + if (RTC_GetOperatingMode(base) != kRTC_ModeTimeDate) + { + return kStatus_Fail; + } + + if (!RTC_ValidateDateTime(datetime)) + { + return kStatus_InvalidArgument; + } + + /* Wait for RTC interface is ready */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Set year */ + base->YEAR = RTC_YEAR_YEAR(datetime->year - YEAR_RANGE_START); + + /* Wait for RTC interface is ready */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Set month and day */ + base->MONTH = + RTC_MONTH_MONTH(datetime->month - 1) | RTC_MONTH_DAY(datetime->day - 1) | RTC_MONTH_WEEK(datetime->dayOfWeek); + + /* Wait for RTC interface is ready */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Set hour and minute */ + base->HOUR_M = RTC_HOUR_M_HOUR(datetime->hour) | RTC_HOUR_M_MIN(datetime->minute); + + /* Wait for RTC interface is ready */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Set second and hundredth - this write triggers the RTC update */ + base->SEC_HUND = + RTC_SEC_HUND_SEC(datetime->second) | RTC_SEC_HUND_HUND(datetime->hundredthOfSecond); /* Set hundredths to 0 */ + + return kStatus_Success; +} + +/*! + * brief Retrieves the current RTC date and time. + * + * param base RTC peripheral base address. + * param datetime Pointer to the rtc_datetime_t structure to store the current date and time. + * return kStatus_Success if the operation was successful, kStatus_InvalidArgument if not in time/date mode, + * kStatus_Fail if a read collision occurred, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) +{ + /* Check input parameters */ + assert(datetime != NULL); + + /* Check if in time date mode */ + if (RTC_GetOperatingMode(base) != kRTC_ModeTimeDate) + { + return kStatus_InvalidArgument; + } + + /* Wait for RTC interface is ready */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + + /* Clear any previous read collision flag */ + base->CONFIG &= ~RTC_CONFIG_READ_COLL_MASK; + + /* Read year */ + datetime->year = YEAR_RANGE_START + ((base->YEAR & RTC_YEAR_YEAR_MASK) >> RTC_YEAR_YEAR_SHIFT); + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Read month and day */ + uint32_t monthReg = base->MONTH; + datetime->month = (uint8_t)((monthReg & RTC_MONTH_MONTH_MASK) >> RTC_MONTH_MONTH_SHIFT) + 1U; + datetime->day = (uint8_t)((monthReg & RTC_MONTH_DAY_MASK) >> RTC_MONTH_DAY_SHIFT) + 1U; + datetime->dayOfWeek = (uint8_t)((monthReg & RTC_MONTH_WEEK_MASK) >> RTC_MONTH_WEEK_SHIFT); + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Read hour and minute */ + uint32_t hourMinReg = base->HOUR_M; + datetime->hour = (uint8_t)((hourMinReg & RTC_HOUR_M_HOUR_MASK) >> RTC_HOUR_M_HOUR_SHIFT); + datetime->minute = (uint8_t)((hourMinReg & RTC_HOUR_M_MIN_MASK) >> RTC_HOUR_M_MIN_SHIFT); + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Read second and hundredth */ + uint32_t secondHundredth = base->SEC_HUND; + datetime->second = (uint8_t)((secondHundredth & RTC_SEC_HUND_SEC_MASK) >> RTC_SEC_HUND_SEC_SHIFT); + datetime->hundredthOfSecond = (uint8_t)((secondHundredth & RTC_SEC_HUND_HUND_MASK) >> RTC_SEC_HUND_HUND_SHIFT); + + /* Check if any read collision occurred during the whole read sequence */ + if (base->CONFIG & RTC_CONFIG_READ_COLL_MASK) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +/*! + * brief Sets the initial value of the RTC free-running counter. + * + * This function is applicable only when the RTC is in Free-Running Counter mode. + * + * param base RTC peripheral base address. + * param countValue The initial value to set for the counter. + * return kStatus_Success if the operation was successful, kStatus_InvalidArgument if the input is invalid, or + * kStatus_Timeout if the interface is not ready. + */ +status_t RTC_SetFreeRunningCounter(RTC_Type *base, uint64_t countValue) +{ + /* Check if in free-running mode */ + if (RTC_GetOperatingMode(base) != kRTC_ModeFreeRunningCounter) + { + return kStatus_InvalidArgument; + } + + /* Check if countValue exceeds 40-bit maximum (0xFFFFFFFFFF) */ + if (countValue > 0xFFFFFFFFFFULL) + { + return kStatus_InvalidArgument; + } + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Set counter values */ + base->CNT_H = RTC_CNT_H_CTRL_HIGH((countValue >> 32) & 0xFFU); + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->CNT_M = RTC_CNT_M_CTRL_MIDDLE((countValue >> 16) & 0xFFFFU); + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Writing to CNT_L triggers the update */ + base->CNT_L = RTC_CNT_L_CTRL_LOW(countValue & 0xFFFFU); + + return kStatus_Success; +} + +/*! + * brief Retrieves the current value of the RTC free-running counter. + * + * This function is applicable only when the RTC is in Free-Running Counter mode. + * + * param base RTC peripheral base address. + * param countValue Pointer to a variable to store the current counter value. + * return kStatus_Success if the operation was successful, kStatus_InvalidArgument if not in free-running mode, or + * kStatus_Fail if a read collision occurred. kStatus_Timeout if the interface is not ready. + */ +status_t RTC_GetFreeRunningCounter(RTC_Type *base, uint64_t *countValue) +{ + assert(countValue != NULL); + + /* Check if in free-running mode */ + if (RTC_GetOperatingMode(base) != kRTC_ModeFreeRunningCounter) + { + return kStatus_InvalidArgument; + } + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Clear any previous read collision flag */ + base->CONFIG &= ~RTC_CONFIG_READ_COLL_MASK; + + /* Read counter values */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + uint64_t high = (uint64_t)((base->CNT_H & RTC_CNT_H_CTRL_HIGH_MASK) >> RTC_CNT_H_CTRL_HIGH_SHIFT); + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + uint32_t middle = (base->CNT_M & RTC_CNT_M_CTRL_MIDDLE_MASK) >> RTC_CNT_M_CTRL_MIDDLE_SHIFT; + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + uint32_t low = (base->CNT_L & RTC_CNT_L_CTRL_LOW_MASK) >> RTC_CNT_L_CTRL_LOW_SHIFT; + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Check if any read collision occurred during the whole read sequence */ + if (base->CONFIG & RTC_CONFIG_READ_COLL_MASK) + { + return kStatus_Fail; + } + + /* Combine the values - cast to uint64_t first, then shift */ + *countValue = (high << 32) | ((uint64_t)middle << 16) | (uint64_t)low; + + return kStatus_Success; +} + +/*! + * brief Configures a specific RTC BCD alarm. + * + * Sets the alarm time, date, mask, mode, and initial enable state. + * The number of alarms is MCU-dependent (e.g., 3 alarms: Alarm0, Alarm1, Alarm2). + * + * param base RTC peripheral base address. + * param alarmId The ID of the alarm to configure (e.g., kRTC_Alarm_0). + * param alarmConfig Pointer to the rtc_bcd_alarm_config_t structure with alarm settings. + * return kStatus_Success if the operation was successful, kStatus_InvalidArgument if the input was invalid, or + * kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ConfigureBCDAlarm(RTC_Type *base, rtc_alarm_id_t alarmId, const rtc_bcd_alarm_config_t *alarmConfig) +{ + /* Check input parameters */ + assert(alarmConfig != NULL); + assert(alarmId <= kRTC_Alarm_2); + uint32_t bcdAlarmH = 0U; + uint32_t bcdAlarmL = 0U; + uint32_t bcdAlarmMin = 0U; + + /* Validate the alarm configuration */ + if (!RTC_ValidateBCDAlarmDateTime(alarmConfig)) + { + return kStatus_InvalidArgument; + } + + /* Disable the alarm first if it's enabled */ + RTC_DisableAlarm(base, alarmId); + + /* Set up the BCD alarm configuration */ + /* Configure high word - includes alarm number and repeat flag */ + bcdAlarmH = RTC_BCD_ALARM_H_NUM(alarmId) | RTC_BCD_ALARM_H_REP(alarmConfig->mode == kRTC_AlarmModeRepeat ? 1U : 0U); + + /* Configure mask bits */ + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreMonth) == 0U) + { + bcdAlarmH |= RTC_BCD_ALARM_H_USE_MO_MASK; + bcdAlarmH |= RTC_BCD_ALARM_H_MONTH(alarmConfig->month - 1); + } + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreDay) == 0U) + { + bcdAlarmH |= RTC_BCD_ALARM_H_USE_DAY_MO_MASK; + bcdAlarmMin = RTC_BCD_ALARM_MIN_DAY_MO(alarmConfig->day - 1); + } + + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreHour) == 0U) + { + bcdAlarmL |= RTC_BCD_ALARM_L_USE_HOUR_MASK; + bcdAlarmMin |= RTC_BCD_ALARM_MIN_HOUR(alarmConfig->hour); + } + + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreMinute) == 0U) + { + bcdAlarmL |= RTC_BCD_ALARM_L_USE_MIN_MASK; + bcdAlarmMin |= RTC_BCD_ALARM_MIN_MIN(alarmConfig->minute); + } + + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreSecond) == 0U) + { + bcdAlarmL |= RTC_BCD_ALARM_L_USE_SEC_MASK; + bcdAlarmL |= RTC_BCD_ALARM_L_SEC(alarmConfig->second); + } + + bcdAlarmL |= RTC_BCD_ALARM_L_HUND(alarmConfig->hundredthOfSecond); + + /* Day of week mask handling - set the specific days of week in the dayOfWeek field */ + /* If day of week is not ignored, set the specific day of week */ + if ((alarmConfig->mask & kRTC_AlarmMaskIgnoreDayOfWeek) == 0U) + { + bcdAlarmH |= RTC_BCD_ALARM_H_DAY_WEEK(1U << alarmConfig->dayOfWeek); + } + /* If day of week is ignored, set all days (0x7F) */ + else + { + bcdAlarmH |= RTC_BCD_ALARM_H_DAY_WEEK(0x7FU); + } + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Write the high word of the alarm */ + base->BCD_ALARM_H = bcdAlarmH; + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Write the min word of the alarm */ + base->BCD_ALARM_MIN = bcdAlarmMin; + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Write the low word of the alarm */ + base->BCD_ALARM_L = bcdAlarmL; + + /* Enable the alarm if requested */ + if (alarmConfig->enable) + { + RTC_EnableAlarm(base, alarmId); + } + + return kStatus_Success; +} + +/*! + * brief Configures a specific RTC free running mode alarm. + * + * Select the alarm id and set the alarm counter value + * + * param base RTC peripheral base address. + * param alarmId The ID of the alarm to configure (e.g., kRTC_Alarm_0). + * param alarmConfig Pointer to the rtc_free_run_alarm_config_t structure with alarm settings. + * return kStatus_Success if the operation was successful, kStatus_InvalidArgument if the input was invalid, + * or kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ConfigureFreeRunningAlarm(RTC_Type *base, + rtc_alarm_id_t alarmId, + const rtc_free_run_alarm_config_t *alarmConfig) +{ + assert(alarmConfig != NULL); + assert(alarmId <= kRTC_Alarm_2); + + /* Validate the free running alarm configuration */ + if (!RTC_ValidateFreeRunAlarmCounter(alarmConfig)) + { + return kStatus_InvalidArgument; + } + + uint32_t alarmH = 0U; + uint32_t alarmMid = 0U; + uint32_t alarmLow = 0U; + + /* Disable the alarm before configuration */ + RTC_DisableAlarm(base, alarmId); + + /* Set alarm number and repeat mode */ + alarmH = RTC_ALARM_H_ALARM_NUM(alarmId); + if (alarmConfig->mode == kRTC_AlarmModeRepeat) + { + alarmH |= RTC_ALARM_H_ALARM_REP_MASK; + + /* Only lower 24 bits are used in repeat mode (relative value) */ + uint32_t relVal = alarmConfig->alarmCounter & 0xFFFFFFU; + /* bits 23:16 */ + alarmMid = RTC_ALARM_MID_ALARM_M((relVal >> 16) & 0xFFU); + /* bits 15:0 */ + alarmLow = RTC_ALARM_LOW_ALARMN_L(relVal & 0xFFFFU); + } + /* Single shot mode */ + else + { + /* All 40 bits are used (absolute value) */ + /* bits 39:32 */ + alarmH |= RTC_ALARM_H_ALARM((uint32_t)((alarmConfig->alarmCounter >> 32) & 0xFFU)); + /* bits 31:16 */ + alarmMid = RTC_ALARM_MID_ALARM_M((uint32_t)((alarmConfig->alarmCounter >> 16) & 0xFFFFU)); + /* bits 15:0 */ + alarmLow = RTC_ALARM_LOW_ALARMN_L((uint32_t)(alarmConfig->alarmCounter & 0xFFFFU)); + } + + /* Write to hardware registers with interface ready checks */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->ALARM_H = alarmH; + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->ALARM_MID = alarmMid; + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->ALARM_LOW = alarmLow; + + /* Enable the alarm if requested */ + if (alarmConfig->enable) + { + RTC_EnableAlarm(base, alarmId); + } + + return kStatus_Success; +} + +/*! + * brief Enables a specific RTC alarm. + * + * param base RTC peripheral base address. + * param alarmId The ID of the alarm to enable. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_EnableAlarm(RTC_Type *base, rtc_alarm_id_t alarmId) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Clear the disable bit for the specified alarm */ + switch (alarmId) + { + case kRTC_Alarm_0: + base->CONFIG &= ~RTC_CONFIG_ALARM0_DIS_MASK; + break; + case kRTC_Alarm_1: + base->CONFIG &= ~RTC_CONFIG_ALARM1_DIS_MASK; + break; + case kRTC_Alarm_2: + base->CONFIG &= ~RTC_CONFIG_ALARM2_DIS_MASK; + break; + default: + /* Invalid alarm ID */ + assert(false); + break; + } + + return kStatus_Success; +} + +/*! + * brief Disables a specific RTC alarm. + * + * param base RTC peripheral base address. + * param alarmId The ID of the alarm to disable. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_DisableAlarm(RTC_Type *base, rtc_alarm_id_t alarmId) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Set the disable bit for the specified alarm */ + switch (alarmId) + { + case kRTC_Alarm_0: + base->CONFIG |= RTC_CONFIG_ALARM0_DIS_MASK; + break; + case kRTC_Alarm_1: + base->CONFIG |= RTC_CONFIG_ALARM1_DIS_MASK; + break; + case kRTC_Alarm_2: + base->CONFIG |= RTC_CONFIG_ALARM2_DIS_MASK; + break; + default: + /* Invalid alarm ID */ + assert(false); + break; + } + + return kStatus_Success; +} + +/*! + * brief Enables specified RTC interrupt sources. + * + * param base RTC peripheral base address. + * param mask Bitmask of interrupts to enable (see rtc_interrupt_enable_t). + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t enabledInterrupts; + mask &= (uint32_t)kRTC_AllInterruptsEnable; + + enabledInterrupts = base->INT & (uint32_t)kRTC_AllInterruptsEnable; + enabledInterrupts |= mask; + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->INT = enabledInterrupts; + + return kStatus_Success; +} +/*! + * brief Disables specified RTC interrupt sources. + * + * param base RTC peripheral base address. + * param mask Bitmask of interrupts to disable (see rtc_interrupt_enable_t). + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t enabledInterrupts; + mask &= (uint32_t)kRTC_AllInterruptsEnable; + + enabledInterrupts = base->INT & (uint32_t)kRTC_AllInterruptsEnable; + enabledInterrupts &= ~mask; + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->INT = enabledInterrupts; + + return kStatus_Success; +} + +/*! + * brief Clears the RTC interrupt flags. + * + * param base RTC peripheral base address + * param mask The interrupt flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ClearInterruptFlags(RTC_Type *base, uint32_t mask) +{ + uint32_t regValue; + mask &= (uint32_t)kRTC_AllStatusFlags; + + regValue = base->INT; + /* Clear all interrupt flag bits */ + regValue &= ~(uint32_t)kRTC_AllStatusFlags; + regValue |= mask; + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->INT = regValue; + + return kStatus_Success; +} + +/*! + * brief Register callback. + * + * param cb_func callback function + */ +void RTC_RegisterCallBack(rtc_callback_t cb_func) +{ + s_rtcCallback = cb_func; +} + +/*! + * brief Enables the RTC Watchdog Timer. + * Assumes timeout is already configured via RTC_Init or RTC_SetWatchdogTimeout. + * + * param base RTC peripheral base address. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_EnableWatchdog(RTC_Type *base) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->CONFIG |= RTC_CONFIG_WDOG_EN_MASK; + return kStatus_Success; +} + +/*! + * brief Disables the RTC Watchdog Timer. + * + * param base RTC peripheral base address. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_DisableWatchdog(RTC_Type *base) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->CONFIG &= ~RTC_CONFIG_WDOG_EN_MASK; + + return kStatus_Success; +} + +/*! + * brief Sets the timeout value for the RTC Watchdog Timer. + * + * param base RTC peripheral base address. + * param timeoutValue The desired timeout value. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_SetWatchdogTimeout(RTC_Type *base, uint32_t timeoutValue) +{ + s_lastWdtTimeout = timeoutValue; + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->WDT_SET_VA = RTC_WDT_SET_VA_WDT_CNTR(timeoutValue); + + return kStatus_Success; +} + +/*! + * brief Refreshes the RTC Watchdog Timer. + * + * param base RTC peripheral base address. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_RefreshWatchdog(RTC_Type *base) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->WDT_SET_VA = RTC_WDT_SET_VA_WDT_CNTR(s_lastWdtTimeout); + + return kStatus_Success; +} + +/*! + * brief Configures a specific tamper input. + * + * This function sets up the tamper input configuration, including enabling/disabling the input, + * setting polarity, pullup and filters. + * + * param base RTC peripheral base address. + * param tamperInputId The ID of the tamper input to configure (e.g., kRTC_TamperInput0). + * param config Pointer to the rtc_tamper_config_t structure containing tamper input settings. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ConfigureTamperInput(RTC_Type *base, + rtc_tamper_input_id_t tamperInputId, + const rtc_tamper_input_config_t *config) +{ + /* Check input parameters */ + assert(config != NULL); + assert(tamperInputId < RTC_MAX_TAMPER_INPUTS); + + /* First clean tamper input bits value*/ + uint32_t tamperCtrl = base->TAMP_CTRL; + + tamperCtrl &= ~(((1 << tamperInputId) << RTC_TAMP_CTRL_TAMP_EN_SHIFT) | + ((1 << tamperInputId) << RTC_TAMP_CTRL_TAMP_POL_SHIFT) | + ((1 << tamperInputId) << RTC_TAMP_CTRL_TAMP_PULL_CTRL_SHIFT) | + ((1 << tamperInputId) << RTC_TAMP_CTRL_TAMP_CTRL_SHIFT)); + + /* Configure tamper global settings */ + tamperCtrl |= RTC_TAMP_CTRL_TAMP_EN((config->enableTamperInput ? 1U : 0U) << tamperInputId) | + RTC_TAMP_CTRL_TAMP_POL(config->polarity << tamperInputId) | + RTC_TAMP_CTRL_TAMP_PULL_CTRL(config->pullup << tamperInputId) | + RTC_TAMP_CTRL_TAMP_CTRL(config->filter << tamperInputId); + + if (config->enableTamperInput) + { + /* Enable global tamper detection if not already enabled */ + tamperCtrl |= RTC_TAMP_CTRL_TAMP_LOG_EN_MASK; + } + else + { + /* If disabling, check if any other tamper input is still enabled */ + if ((tamperCtrl & RTC_TAMP_CTRL_TAMP_EN_MASK) == 0U) + { + tamperCtrl &= ~RTC_TAMP_CTRL_TAMP_LOG_EN_MASK; /* Disable global tamper detection */ + } + } + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->TAMP_CTRL = tamperCtrl; + + return kStatus_Success; +} + +/*! + * brief Enables the specific tamper detection input pin. + * + * param base RTC peripheral base address. + * param tamperInputId Bitmask of tamper inputs to enable. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_EnableTamperInputPin(RTC_Type *base, rtc_tamper_input_id_t tamperInputId) +{ + /* Ensure valid tamper pin */ + assert(tamperInputId < RTC_MAX_TAMPER_INPUTS); + + uint32_t tamperCtrl = base->TAMP_CTRL; + + /* Enable global tamper detection if requested */ + if ((tamperCtrl & RTC_TAMP_CTRL_TAMP_LOG_EN_MASK) == 0U) + { + tamperCtrl |= RTC_TAMP_CTRL_TAMP_LOG_EN_MASK; + } + + tamperCtrl |= RTC_TAMP_CTRL_TAMP_EN(tamperInputId); + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Update tamper control register */ + base->TAMP_CTRL = tamperCtrl; + + return kStatus_Success; +} + +/*! + * brief Disable the specific tamper detection input pin. + * + * param base RTC peripheral base address. + * param tamperInputId Bitmask of tamper inputs to disable. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_DisableTamperInputPin(RTC_Type *base, rtc_tamper_input_id_t tamperInputId) +{ + /* Ensure valid tamper pin */ + assert(tamperInputId < RTC_MAX_TAMPER_INPUTS); + + uint32_t tamperCtrl = base->TAMP_CTRL; + + tamperCtrl &= ~RTC_TAMP_CTRL_TAMP_EN(tamperInputId); + + /* If both pins are disabled, disable global tamper detection */ + if ((tamperCtrl & RTC_TAMP_CTRL_TAMP_EN_MASK) == 0U) + { + tamperCtrl &= ~RTC_TAMP_CTRL_TAMP_LOG_EN_MASK; + } + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Update tamper control register */ + base->TAMP_CTRL = tamperCtrl; + + return kStatus_Success; +} + +/*! + * @brief Gets the latched RTC counter value at the time of the last tamper event. + * + * @param base RTC peripheral base address. + * @param latchedCount Pointer to a variable where the latched counter value will be stored. + * @return kStatus_Success if the operation was successful, kStatus_InvalidArgument if not in tamper mode, + */ +status_t RTC_GetTamperTimestamp(RTC_Type *base, uint64_t *latchedCount) +{ + assert(latchedCount != NULL); + memset(latchedCount, 0, sizeof(uint64_t)); + + /* 1. Trigger read of latched counter from RTC to SMM */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->TAMP_CTRL |= RTC_TAMP_CTRL_READ_CNTR_STRT_MASK; + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* 2. Poll for READ_CNTR_READY */ +#if defined(RTC_WAIT_READ_COUNTER_LATCHED_READY) && (RTC_WAIT_READ_COUNTER_LATCHED_READY > 0U) + uint32_t timeout = RTC_WAIT_READ_COUNTER_LATCHED_READY; +#endif + /* Wait until the RTC interface is ready (IF_READY bit is set) */ + while (!(base->TAMP_CTRL & RTC_TAMP_CTRL_READ_CNTR_READY_MASK)) + { + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } +#if defined(RTC_WAIT_READ_COUNTER_LATCHED_READY) && (RTC_WAIT_READ_COUNTER_LATCHED_READY > 0U) + if ((--timeout) == 0U) + { + /* Timeout occurred */ + return kStatus_Timeout; + } +#endif + } + + /* Bit READ_CNTR_STRT is auto-cleared by HW when READ_CNTR_READY is set */ + /* 3. Read the latched counter value */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + uint32_t count0 = base->RTC_COUNT[0]; /* RTC_COUNT[15:0] */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + uint32_t count1 = base->RTC_COUNT[1]; /* RTC_COUNT[31:16] */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + uint32_t count2 = base->RTC_COUNT[2]; /* RTC_COUNT[39:32] - only lower 8 bits are valid */ + + *latchedCount = ((uint64_t)(count2 & 0xFFU) << 32U) | ((uint64_t)count1 << 16U) | ((uint64_t)count0); + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Clean read counter ready. */ + base->TAMP_CTRL &= ~RTC_TAMP_CTRL_READ_CNTR_READY_MASK; + + return kStatus_Success; +} + +/*! + * brief Writes a key to the RTC's non-volatile storage. + * + * param base RTC peripheral base address. + * param keyData Pointer to the key data to be written. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_WriteKey(RTC_Type *base, const uint32_t *keyData) +{ + /* Check input parameters */ + assert(keyData != NULL); + + for (uint8_t i = 0U; i < RTC_SECURE_KEY_REG_COUNT; ++i) + { + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* RM: "After each write of the 2nd 16bit the 32bits will be written to the RTC." + * This implies SMM handles sub-word writes if needed. CPU writes 32-bit words. + */ + base->SECURE_KEY[i] = keyData[i]; + } + + return kStatus_Success; +} + +/*! + * brief Reads a key from the RTC's non-volatile storage. + * + * param base RTC peripheral base address. + * param keyBuffer Pointer to a buffer where the key data will be stored. + * return kStatus_Success if the operation was successful, kStatus_Fail if SECURE_KEY_READY is not set + */ +status_t RTC_ReadKey(RTC_Type *base, uint32_t *keyBuffer) +{ + assert(keyBuffer != NULL); + + /* Trigger read of secure key from RTC to SMM */ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Set READ_SEC_KEY_START */ + base->TAMP_CTRL |= RTC_TAMP_CTRL_READ_SEC_KEY_MASK; + +#if defined(RTC_WAIT_SECURE_KEY_READY_TIMEOUT) && (RTC_WAIT_SECURE_KEY_READY_TIMEOUT > 0U) + uint32_t timeout = RTC_WAIT_SECURE_KEY_READY_TIMEOUT; +#endif + while ((base->TAMP_CTRL & RTC_TAMP_CTRL_SEC_KEY_READY_MASK) == 0U) + { +#if defined(RTC_WAIT_SECURE_KEY_READY_TIMEOUT) && (RTC_WAIT_SECURE_KEY_READY_TIMEOUT > 0U) + if ((--timeout) == 0U) + { + /* Timeout occurred */ + return kStatus_Timeout; + } +#endif + } + + /* Bit READ_SEC_KEY is auto-cleared by HW when SEC_KEY_READY is set */ + for (uint32_t i = 0U; i < RTC_SECURE_KEY_REG_COUNT; ++i) + { + keyBuffer[i] = base->SECURE_KEY[i]; + } + + return kStatus_Success; +} + +/*! + * brief Enables the RTC alive detector. + * + * param base RTC peripheral base address. + * param config Pointer to the rtc_alive_detector_config_t structure containing alive detector settings. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ConfigureAliveDetector(RTC_Type *base, const rtc_alive_detector_config_t *config) +{ + /* Check input parameters */ + assert(config != NULL); + + /* Configure alive detector settings */ + uint32_t aliveDetector = RTC_RTC_ALV_DTCT_DTCT_EN(config->enableAliveDetector ? 1U : 0U) | + RTC_RTC_ALV_DTCT_BYPASS(config->bypassAnalogAliveMechanism ? 1U : 0U) | + RTC_RTC_ALV_DTCT_ACTV_PRD(config->mechanismPeriod); + + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + base->RTC_ALV_DTCT = aliveDetector; + return kStatus_Success; +} + +/*! + * brief Alive detector enable + * + * param base RTC peripheral base address. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_EnableAliveDetector(RTC_Type *base) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Set the enable bit for the alive detector */ + base->RTC_ALV_DTCT |= RTC_RTC_ALV_DTCT_DTCT_EN_MASK; + return kStatus_Success; +} + +/*! + * brief Alive detector disable + * + * param base RTC peripheral base address. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_DisableAliveDetector(RTC_Type *base) +{ + if (kStatus_Success != RTC_WaitForInterfaceReady(base)) + { + return kStatus_Timeout; + } + /* Clear the enable bit for the alive detector */ + base->RTC_ALV_DTCT &= ~RTC_RTC_ALV_DTCT_DTCT_EN_MASK; + return kStatus_Success; +} + +/*! + * brief RTC Alarm 0 interrupt handler. + * + * This function is called when the RTC Alarm 0 interrupt occurs. + * It clears the interrupt flags and calls the registered callback function if set. + */ +void RTC_ALARM0_DriverIRQHandler(void); +void RTC_ALARM0_DriverIRQHandler(void) +{ + RTC_ClearInterruptFlags(AON__RTC_AON, kRTC_Alarm0InterruptFlag); + + if (s_rtcCallback != NULL) + { + s_rtcCallback(kRTC_Alarm0Callback); + } + + SDK_ISR_EXIT_BARRIER; +} + +/*! + * brief RTC Alarm 1 interrupt handler. + * + * This function is called when the RTC Alarm 1 interrupt occurs. + * It clears the interrupt flags and calls the registered callback function if set. + */ +void RTC_ALARM1_DriverIRQHandler(void); +void RTC_ALARM1_DriverIRQHandler(void) +{ + RTC_ClearInterruptFlags(AON__RTC_AON, kRTC_Alarm1InterruptFlag); + + if (s_rtcCallback != NULL) + { + s_rtcCallback(kRTC_Alarm1Callback); + } + + SDK_ISR_EXIT_BARRIER; +} + +/*! + * brief RTC Alarm 2 interrupt handler. + * + * This function is called when the RTC Alarm 2 interrupt occurs. + * It clears the interrupt flags and calls the registered callback function if set. + */ +void RTC_ALARM2_DriverIRQHandler(void); +void RTC_ALARM2_DriverIRQHandler(void) +{ + RTC_ClearInterruptFlags(AON__RTC_AON, kRTC_Alarm2InterruptFlag); + + if (s_rtcCallback != NULL) + { + s_rtcCallback(kRTC_Alarm2Callback); + } + + SDK_ISR_EXIT_BARRIER; +} + +/*! + * brief RTC watchdog interrupt handler. + * + * This function is called when the RTC Watchdog Timer interrupt occurs. + * It clears the interrupt flags and calls the registered callback function if set. + */ +void RTC_WDT_DriverIRQHandler(void); +void RTC_WDT_DriverIRQHandler(void) +{ + RTC_ClearInterruptFlags(AON__RTC_AON, kRTC_WatchdogInterruptFlag); + + if (s_rtcCallback != NULL) + { + s_rtcCallback(kRTC_WatchDogCallback); + } + + SDK_ISR_EXIT_BARRIER; +} + +/*! + * brief RTC xtal interrupt handler. + * This function is called when the RTC Xtal interrupt occurs. + * It clears the interrupt flags and calls the registered callback function if set. + */ +void RTC_XTAL_DriverIRQHandler(void); +void RTC_XTAL_DriverIRQHandler(void) +{ + RTC_ClearInterruptFlags(AON__RTC_AON, kRTC_XtalFailInterruptFlag); + + if (s_rtcCallback != NULL) + { + s_rtcCallback(kRTC_XtalFailCallback); + } + + SDK_ISR_EXIT_BARRIER; +} diff --git a/mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.h b/mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.h new file mode 100644 index 000000000..c607066b1 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/rtc_analog/fsl_rtc.h @@ -0,0 +1,681 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_RTC_H_ +#define FSL_RTC_H_ + +#include "fsl_common.h" + +/*! @file fsl_rtc.h */ + +/*! + * @addtogroup rtc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) /*!< Version 1.0.0 */ +/*! @} */ + +/*! @name RTC tamper */ +/*! @{ */ +/* Size of the secure key in bytes, 256bits */ +#define RTC_SECURE_KEY_SIZE_BYTES (32U) +/* Number of 32-bit registers for the secure key */ +#define RTC_SECURE_KEY_REG_COUNT (RTC_SECURE_KEY_SIZE_BYTES / 4U) +/* Number of tamper inputs supported by the rtc_tamper_config_t structure */ +#define RTC_MAX_TAMPER_INPUTS (2U) +/*! @} */ + +/*! @brief RTC wait inteface ready timeout */ +#ifndef RTC_WAIT_INTERFACE_READY_TIMEOUT +#ifdef CONFIG_RTC_WAIT_INTERFACE_READY_TIMEOUT +#define RTC_WAIT_INTERFACE_READY_TIMEOUT CONFIG_RTC_WAIT_INTERFACE_READY_TIMEOUT +#else +#define RTC_WAIT_INTERFACE_READY_TIMEOUT 0U +#endif +#endif + +/*! @brief RTC wait read counter latched timeout */ +#ifndef RTC_WAIT_READ_COUNTER_LATCHED_READY +#ifdef CONFIG_RTC_WAIT_READ_COUNTER_LATCHED_READY +#define RTC_WAIT_READ_COUNTER_LATCHED_READY CONFIG_RTC_WAIT_READ_COUNTER_LATCHED_READY +#else +#define RTC_WAIT_READ_COUNTER_LATCHED_READY 0U +#endif +#endif + +/*! @brief RTC wait secure key ready timeout */ +#ifndef RTC_WAIT_SECURE_KEY_READY_TIMEOUT +#ifdef CONFIG_RTC_WAIT_SECURE_KEY_READY_TIMEOUT +#define RTC_WAIT_SECURE_KEY_READY_TIMEOUT CONFIG_RTC_WAIT_SECURE_KEY_READY_TIMEOUT +#else +#define RTC_WAIT_SECURE_KEY_READY_TIMEOUT 0U +#endif +#endif + +/*! @brief RTC operating modes. */ +typedef enum _rtc_operating_mode +{ + kRTC_ModeTimeDate = 0U, /*!< RTC operates in Time/Date counting mode. */ + kRTC_ModeFreeRunningCounter = 1U /*!< RTC operates as a free-running counter. */ +} rtc_operating_mode_t; + +/*! @brief RTC date and time structure. */ +typedef struct _rtc_datetime +{ + uint16_t year; /*!< Year (e.g., 2023) */ + uint8_t month; /*!< Month (1-12) */ + uint8_t day; /*!< Day of the month (1-31) */ + uint8_t hour; /*!< Hour (0-23) */ + uint8_t minute; /*!< Minute (0-59) */ + uint8_t second; /*!< Second (0-59) */ + uint8_t hundredthOfSecond; /*!< Hundredth of a second (0-99) */ + uint8_t dayOfWeek; /*!< Day of the week (e.g., 0 for Sunday, 1 for Monday, etc.) */ +} rtc_datetime_t; + +/*! @brief RTC Alarm identifiers. Corresponds to Alarm 0, 1, 2. */ +typedef enum _rtc_alarm_id +{ + kRTC_Alarm_0 = 0U, /*!< Identifier for Alarm 0 */ + kRTC_Alarm_1 = 1U, /*!< Identifier for Alarm 1 */ + kRTC_Alarm_2 = 2U /*!< Identifier for Alarm 2 */ +} rtc_alarm_id_t; + +/*! @brief RTC alarm operational modes. */ +typedef enum _rtc_alarm_mode +{ + kRTC_AlarmModeSingleShot = + 0U, /*!< Alarm triggers once and then (typically) disables itself or requires re-arming. */ + kRTC_AlarmModeRepeat = 1U /*!< Alarm triggers repeatedly based on its configuration (e.g., daily, weekly). */ +} rtc_alarm_mode_t; + +/*! + * @brief RTC alarm mask fields. + * Used with rtc_bcd_alarm_config_t's mask member. Set a bit to 1 to ignore the corresponding field for alarm matching. + */ +typedef enum _rtc_alarm_mask_fields +{ + kRTC_AlarmMaskIgnoreNothing = 0U, /*!< Match all fields specified in alarm time/date. */ + kRTC_AlarmMaskIgnoreSecond = (1U << 0), /*!< Ignore seconds field for alarm match. */ + kRTC_AlarmMaskIgnoreMinute = (1U << 1), /*!< Ignore minutes field for alarm match. */ + kRTC_AlarmMaskIgnoreHour = (1U << 2), /*!< Ignore hours field for alarm match. */ + kRTC_AlarmMaskIgnoreDay = (1U << 3), /*!< Ignore day of the month field for alarm match. */ + kRTC_AlarmMaskIgnoreDayOfWeek = (1U << 4), /*!< Ignore day of the week field for alarm match. */ + kRTC_AlarmMaskIgnoreMonth = (1U << 5), /*!< Ignore month field for alarm match. */ + kRTC_AlarmMaskIgnoreAll = 0x3FU /*!< Ignore all field for alarm match. */ +} rtc_alarm_mask_fields_t; + +/*! @brief RTC bcd alarm configuration structure. */ +typedef struct _rtc_alarm_config +{ + uint8_t hour; /*!< Alarm hour (0-23). Relevant if not masked. */ + uint8_t minute; /*!< Alarm minute (0-59). Relevant if not masked. */ + uint8_t second; /*!< Alarm second (0-59). Relevant if not masked. */ + uint8_t hundredthOfSecond; /*!< Alarm hundredth of second (0-99). */ + uint8_t day; /*!< Alarm day of the month (1-31). Relevant if not masked. */ + uint8_t dayOfWeek; /*!< Alarm day of the week. Sunday is 0, Monday is 1. Relevant if not masked. */ + uint8_t month; /*!< Alarm month (1-12). Relevant if not masked. */ + uint8_t mask; /*!< Alarm mask, it a logical OR of members of the enumeration ::rtc_alarm_mask_fields_t. */ + rtc_alarm_mode_t mode; /*!< Alarm mode: kRTC_AlarmModeSingleShot or kRTC_AlarmModeRepeat. */ + bool enable; /*!< Initial enable state for this alarm when configured. True to enable, false to disable. */ +} rtc_bcd_alarm_config_t; + +/*! @brief RTC free run mode alarm */ +typedef struct _rtc_free_run_alarm_config +{ + uint64_t alarmCounter; /*!< Alarm counter value. */ + rtc_alarm_mode_t mode; /*!< Alarm mode: kRTC_AlarmModeSingleShot or kRTC_AlarmModeRepeat. */ + bool enable; /*!< Initial enable state for this alarm when configured. True to enable, false to disable. */ +} rtc_free_run_alarm_config_t; + +/*! @brief RTC Tamper input identifiers. Corresponds to Tamper 0, 1. */ +typedef enum _rtc_tamper_input_id +{ + kRTC_TamperInput0 = 0U, /*!< Enable Tamper input 0. */ + kRTC_TamperInput1 = 1U, /*!< Enable Tamper input 1. */ +} rtc_tamper_input_id_t; + +/*! @brief RTC tamper input filter configuration. */ +typedef enum _rtc_tamper_filter +{ + kRTC_TamperFilterDisabled = 0U, /*!< Digital filter disabled for this tamper input. */ + kRTC_TamperFilterEnabled = 1U, /*!< Digital filter enabled for this tamper input. */ +} rtc_tamper_filter_t; + +/*! @brief RTC tamper input trigger level. */ +typedef enum _rtc_tamper_polarity +{ + kRTC_TamperPolarityLow = 0U, /*!< Tamper event triggered on a low level or falling edge. */ + kRTC_TamperPolarityHigh = 1U /*!< Tamper event triggered on a high level or rising edge. */ +} rtc_tamper_polarity_t; + +/*! @brief RTC tamper input pull-up configuration. */ +typedef enum _rtc_tamper_pullup +{ + kRTC_TamperPullupDisabled = 0U, /*!< No pull-up resistor enabled for this tamper input. */ + kRTC_TamperPullupEnabled = 1U /*!< Pull-up resistor enabled for this tamper input. */ +} rtc_tamper_pullup_t; + +/*! @brief RTC tamper input configuration structure. */ +typedef struct _rtc_tamper_input_config +{ + bool enableTamperInput; /*!< True to enable this tamper input, false to disable. (Maps to TAMP_CTRL[TAMP_EN] bit) */ + rtc_tamper_polarity_t polarity; /*!< Trigger level for this tamper input. */ + rtc_tamper_pullup_t pullup; /*!< Pull-up configuration for this tamper input. */ + rtc_tamper_filter_t filter; /*!< Digital filter configuration for this tamper input. */ +} rtc_tamper_input_config_t; + +/*! @brief RTC global tamper detection configuration structure. */ +typedef struct _rtc_tamper_config +{ + bool enableGlobalTamper; /*!< Master enable for the tamper detection sub-module. */ + rtc_tamper_input_config_t tamperInputConfig[2]; /*!< Configuration for the tamper input pins. This structure is used + to configure each tamper input pin's behavior, such as trigger + level, pull-up, and filtering. */ +} rtc_tamper_config_t; + +/*! @brief RTC alive detector configuration structure. */ +typedef struct _rtc_alive_detector_config +{ + bool enableAliveDetector; /*!< True to enable the RTC alive detector, false to disable. */ + bool bypassAnalogAliveMechanism; /*!< Bypass the RTC analog alive mechanism, implemented at the PAC. After + de-activation of the SMM reset this value is sample back value from PAC. */ + uint8_t mechanismPeriod; /*!< Define the length of the active period of the Alive Detector Mechanism in 2KHz clock + cycles */ +} rtc_alive_detector_config_t; + +/*! @brief RTC general configuration structure. */ +typedef struct _rtc_config +{ + rtc_operating_mode_t operatingMode; /*!< RTC operating mode: Time/Date or Free-Running Counter. */ + bool enableXtal32; /*!< Enable/disable the 32kHz crystal oscillator circuitry. True to enable. */ + bool enable2kHzOutputSMM; /*!< Enable/disable 2kHz output towards SMM. True to enable. */ + bool alarmInitialEnable[3]; /*!< Initial enable state for Alarm 0, 1, 2. True to enable. */ + bool enableWatchdog; /*!< Initial enable state for the Watchdog Timer. True to enable. */ + uint32_t watchdogTimeoutValue; /*!< Watchdog Timer timeout value (units are MCU specific, e.g., seconds or RTC clock + cycles). */ + rtc_tamper_config_t tamperConfig; /*!< Tamper detection configuration. */ + rtc_alive_detector_config_t aliveDetectorConfig; /*!< RTC alive detector configuration. */ +} rtc_config_t; + +/*! @brief Callback type identifiers for RTC events. */ +typedef enum _rtc_callback_type +{ + kRTC_Alarm0Callback, /*!< Alarm 0 interrupt callback type */ + kRTC_Alarm1Callback, /*!< Alarm 1 interrupt callback type */ + kRTC_Alarm2Callback, /*!< Alarm 2 interrupt callback type */ + kRTC_XtalFailCallback, /*!< XTAL Fail interrupt callback type */ + kRTC_WatchDogCallback, /*!< WatchDog timer timeout interrupt callback type */ + kRTC_Tamper0Callback, /*!< Tamper 0 detection interrupt callback type */ + kRTC_Tamper1Callback /*!< Tamper 1 detection interrupt callback type */ +} rtc_callback_type_t; + +/*! @brief RTC interrupt enable masks. Use bitwise OR to enable multiple interrupts. */ +typedef enum _rtc_interrupt_enable +{ + kRTC_Alarm0InterruptEnable = RTC_INT_ALARM0_IE_MASK, /*!< Enable Alarm 0 interrupt. */ + kRTC_Alarm1InterruptEnable = RTC_INT_ALARM1_IE_MASK, /*!< Enable Alarm 1 interrupt. */ + kRTC_Alarm2InterruptEnable = RTC_INT_ALARM2_IE_MASK, /*!< Enable Alarm 2 interrupt. */ + kRTC_XtalFailInterruptEnable = RTC_INT_XTAL_FAIL_IE_MASK, /*!< Enable XTAL Fail interrupt. */ + kRTC_WatchdogInterruptEnable = RTC_INT_WDT_IE_MASK, /*!< Enable Watchdog timeout interrupt. */ + kRTC_Tamper0InterruptEnable = RTC_INT_TMP_DET_PIN0_IE_MASK, /*!< Enable Tamper 0 detection interrupt. */ + kRTC_Tamper1InterruptEnable = RTC_INT_TMP_DET_PIN1_IE_MASK, /*!< Enable Tamper 1 detection interrupt. */ + kRTC_AllInterruptsEnable = (RTC_INT_ALARM0_IE_MASK | RTC_INT_ALARM1_IE_MASK | RTC_INT_ALARM2_IE_MASK | + RTC_INT_XTAL_FAIL_IE_MASK | RTC_INT_WDT_IE_MASK | RTC_INT_TMP_DET_PIN0_IE_MASK | + RTC_INT_TMP_DET_PIN1_IE_MASK) /*!< Enable all RTC interrupts. */ +} rtc_interrupt_enable_t; + +/*! @brief RTC status flags. Use bitwise OR to check multiple flags. */ +typedef enum _rtc_status_flags +{ + kRTC_Alarm0InterruptFlag = RTC_INT_ALARM0_IF_MASK, /*!< Alarm 0 flag. */ + kRTC_Alarm1InterruptFlag = RTC_INT_ALARM1_IF_MASK, /*!< Alarm 1 flag. */ + kRTC_Alarm2InterruptFlag = RTC_INT_ALARM2_IF_MASK, /*!< Alarm 2 flag. */ + kRTC_XtalFailInterruptFlag = RTC_INT_XTAL_FAIL_IF_MASK, /*!< XTAL Fail flag. */ + kRTC_WatchdogInterruptFlag = RTC_INT_WDT_IF_MASK, /*!< Watchdog timeout flag. */ + kRTC_Tamper0InterruptFlag = RTC_INT_TAMP_DET_PIN0_MASK, /*!< Tamper 0 detection flag. */ + kRTC_Tamper1InterruptFlag = RTC_INT_TAMP_DET_PIN1_MASK, /*!< Tamper 1 detection flag. */ + kRTC_AllStatusFlags = (RTC_INT_ALARM0_IF_MASK | RTC_INT_ALARM1_IF_MASK | RTC_INT_ALARM2_IF_MASK | + RTC_INT_XTAL_FAIL_IF_MASK | RTC_INT_WDT_IF_MASK | RTC_INT_TAMP_DET_PIN0_MASK | + RTC_INT_TAMP_DET_PIN1_MASK) /*!< Mask for all RTC status flags. */ +} rtc_status_flags_t; + +/*! @brief RTC callback function pointer type. */ +typedef void (*rtc_callback_t)(rtc_callback_type_t type); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Fills the RTC configuration structure with default values. + * + * The default values are chosen for safe and common startup behavior. + * For example: + * @code + * config->operatingMode = kRTC_ModeTimeDate; + * config->enableXtal32 = true; + * config->enable2kHzOutputSMM = false; + * config->alarmInitialEnable[0] = false; + * config->alarmInitialEnable[1] = false; + * config->alarmInitialEnable[2] = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->tamperConfig.enableGlobalTamper = false; + * config->tamperConfig.tamperInputConfig[0].enableTamperInput = false; + * config->tamperConfig.tamperInputConfig[0].polarity = kRTC_TamperPolarityLow; + * config->tamperConfig.tamperInputConfig[0].pullup = kRTC_TamperPullupDisabled; + * config->tamperConfig.tamperInputConfig[0].filter = kRTC_TamperFilterDisabled; + * config->tamperConfig.tamperInputConfig[1].enableTamperInput = false; + * config->tamperConfig.tamperInputConfig[1].polarity = kRTC_TamperPolarityLow; + * config->tamperConfig.tamperInputConfig[1].pullup = kRTC_TamperPullupDisabled; + * config->tamperConfig.tamperInputConfig[1].filter = kRTC_TamperFilterDisabled; + * config->aliveDetectorConfig.enableAliveDetector = false; + * config->aliveDetectorConfig.bypassAnalogAliveMechanism = false; + * config->aliveDetectorConfig.mechanismPeriod = 0U; + * @endcode + * This function should be called before RTC_Init() if custom configuration is not fully provided. + * + * @param config Pointer to the rtc_config_t structure to be filled. + */ +void RTC_GetDefaultConfig(rtc_config_t *config); + +/*! + * @brief Initializes the RTC peripheral. + * + * This function configures the RTC module according to the settings provided in the config structure. + * It setups initial operating mode, watchdog, tamper detection, and alive detector. + * + * @param base RTC peripheral base address. + * @param config Pointer to the user-defined rtc_config_t structure. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready, + */ +status_t RTC_Init(RTC_Type *base, const rtc_config_t *config); + +/*! + * @brief De-initializes the RTC peripheral. + * + * This function resets RTC registers to a default state and stops the RTC. + * + * @param base RTC peripheral base address. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_Deinit(RTC_Type *base); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the RTC time counter. + * + * @param base RTC peripheral base address + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_StartTimer(RTC_Type *base); + +/*! + * @brief Stops the RTC time counter. + * + * @param base RTC peripheral base address + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_StopTimer(RTC_Type *base); + +/*! @}*/ + +/*! + * @name Time and Date Operations (Time/Date Mode) + * @{ + */ + +/*! + * @brief Sets the current RTC date and time. + * + * Validates the provided date and time before setting. If the input is invalid, + * an error status is returned. + * + * @param base RTC peripheral base address. + * @param datetime Pointer to the rtc_datetime_t structure containing the new date and time. + * @return kStatus_Success if the operation was successful, kStatus_Fail if RTC is not working in time date mode, + * kStatus_InvalidArgument if the input was invalid, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); + +/*! + * @brief Retrieves the current RTC date and time. + * + * @param base RTC peripheral base address. + * @param datetime Pointer to the rtc_datetime_t structure to store the current date and time. + * @return kStatus_Success if the operation was successful, kStatus_InvalidArgument if not in time/date mode, + * kStatus_Fail if a read collision occurred, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @name Free-Running Counter Operations (Free-Running Mode) + * @{ + */ + +/*! + * @brief Sets the initial value of the RTC free-running counter. + * + * This function is applicable only when the RTC is in Free-Running Counter mode. + * + * @param base RTC peripheral base address. + * @param countValue The initial value to set for the counter. + * @return kStatus_Success if the operation was successful, kStatus_InvalidArgument if the input was invalid, or + * kStatus_Timeout if the interface is not ready. + */ +status_t RTC_SetFreeRunningCounter(RTC_Type *base, uint64_t countValue); + +/*! + * @brief Retrieves the current value of the RTC free-running counter. + * + * This function is applicable only when the RTC is in Free-Running Counter mode. + * + * @param base RTC peripheral base address. + * @param countValue Pointer to a variable to store the current counter value. + * @return kStatus_Success if the operation was successful, kStatus_InvalidArgument if not in free-running mode, or + * kStatus_Fail if a read collision occurred, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_GetFreeRunningCounter(RTC_Type *base, uint64_t *countValue); + +/*! @}*/ + +/*! + * @name Alarm Functionality + * @{ + */ + +/*! + * @brief Configures a specific RTC BCD alarm. + * + * Sets the alarm time, date, mask, mode, and initial enable state. + * The number of alarms is MCU-dependent (e.g., 3 alarms: Alarm0, Alarm1, Alarm2). + * + * @param base RTC peripheral base address. + * @param alarmId The ID of the alarm to configure (e.g., kRTC_Alarm_0). + * @param alarmConfig Pointer to the rtc_bcd_alarm_config_t structure with alarm settings. + * @return kStatus_Success if the operation was successful, kStatus_InvalidArgument if the input was invalid, or + * kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ConfigureBCDAlarm(RTC_Type *base, rtc_alarm_id_t alarmId, const rtc_bcd_alarm_config_t *alarmConfig); + +/*! + * @brief Configures a specific RTC free running mode alarm. + * + * Select the alarm id and set the alarm counter value + * + * @param base RTC peripheral base address. + * @param alarmId The ID of the alarm to configure (e.g., kRTC_Alarm_0). + * @param alarmConfig Pointer to the rtc_free_run_alarm_config_t structure with alarm settings. + * @return kStatus_Success if the operation was successful, kStatus_InvalidArgument if the input was invalid, + * or kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ConfigureFreeRunningAlarm(RTC_Type *base, + rtc_alarm_id_t alarmId, + const rtc_free_run_alarm_config_t *alarmConfig); + +/*! + * @brief Enables a specific RTC alarm. + * + * @param base RTC peripheral base address. + * @param alarmId The ID of the alarm to enable. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_EnableAlarm(RTC_Type *base, rtc_alarm_id_t alarmId); + +/*! + * @brief Disables a specific RTC alarm. + * + * @param base RTC peripheral base address. + * @param alarmId The ID of the alarm to disable. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_DisableAlarm(RTC_Type *base, rtc_alarm_id_t alarmId); + +/*! @}*/ + +/*! + * @name Interrupt Handling + * @{ + */ + +/*! + * @brief Enables specified RTC interrupt sources. + * + * @param base RTC peripheral base address. + * @param mask Bitmask of interrupts to enable (see rtc_interrupt_enable_t). + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_EnableInterrupts(RTC_Type *base, uint32_t mask); + +/*! + * @brief Disables specified RTC interrupt sources. + * + * @param base RTC peripheral base address. + * @param mask Bitmask of interrupts to disable (see rtc_interrupt_enable_t). + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_DisableInterrupts(RTC_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled RTC interrupts. + * + * @param base RTC peripheral base address + * @return enabled interrupts bitmask. + */ +static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) +{ + return (base->INT & (uint32_t)kRTC_AllInterruptsEnable); +} + +/*! + * @brief Get the RTC interrupt flags. + * + * @param base RTC peripheral base address + * @return Occured interrupt flags bitmask. + */ +static inline uint32_t RTC_GetInterruptFlags(RTC_Type *base) +{ + return (base->INT & (uint32_t)kRTC_AllStatusFlags); +} + +/*! + * @brief Clears the RTC interrupt flags. + * + * @param base RTC peripheral base address + * @param mask The interrupt flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ClearInterruptFlags(RTC_Type *base, uint32_t mask); + +/*! + * @brief Register callback. + * + * @param cb_func callback function + */ +void RTC_RegisterCallBack(rtc_callback_t cb_func); + +/*! @}*/ + +/*! + * @name Watchdog Timer Functionality + * @{ + */ + +/*! + * @brief Enables the RTC Watchdog Timer. + * Assumes timeout is already configured via RTC_Init or RTC_SetWatchdogTimeout. + * + * @param base RTC peripheral base address. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_EnableWatchdog(RTC_Type *base); + +/*! + * @brief Disables the RTC Watchdog Timer. + * + * @param base RTC peripheral base address. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_DisableWatchdog(RTC_Type *base); + +/*! + * @brief Sets the timeout value for the RTC Watchdog Timer. + * + * @param base RTC peripheral base address. + * @param timeoutValue The desired timeout value. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_SetWatchdogTimeout(RTC_Type *base, uint32_t timeoutValue); + +/*! + * @brief Refreshes the RTC Watchdog Timer. + * + * @param base RTC peripheral base address. + * return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_RefreshWatchdog(RTC_Type *base); + +/*! @}*/ + +/*! + * @name Tamper Detection + * @{ + */ + +/*! + * @brief Configures a specific tamper detection input. + * + * This function sets up the tamper input configuration, including enabling/disabling the input, + * setting polarity, pullup and filters. + * + * @param base RTC peripheral base address. + * @param config Pointer to the rtc_tamper_config_t structure containing tamper input settings. This structure defines + * the behavior of the tamper input, such as polarity, pull-up configuration, and filtering. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ConfigureTamperInput(RTC_Type *base, + rtc_tamper_input_id_t tamperInputId, + const rtc_tamper_input_config_t *config); + +/*! + * @brief Enables the specific tamper detection input pin. + * + * @param base RTC peripheral base address. + * @param tamperInputId Bitmask of tamper inputs to enable. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_EnableTamperInputPin(RTC_Type *base, rtc_tamper_input_id_t tamperInputId); + +/*! + * @brief Disable the specific tamper detection input pin. + * + * @param base RTC peripheral base address. + * @param tamperInputId Bitmask of tamper inputs to disable. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_DisableTamperInputPin(RTC_Type *base, rtc_tamper_input_id_t tamperInputId); + +/*! + * @brief Gets the latched RTC counter value at the time of the last tamper event. + * + * @param base RTC peripheral base address. + * @param latchedCount Pointer to a variable where the latched counter value will be stored. + * @return kStatus_Success if the operation was successful, kStatus_InvalidArgument if not in tamper mode, + */ +status_t RTC_GetTamperTimestamp(RTC_Type *base, uint64_t *latchedCount); + +/*! @}*/ + +/*! + * @name Key Store Operations + * @{ + */ + +/*! + * @brief Writes a key to the RTC's non-volatile storage. + * + * @param base RTC peripheral base address. + * @param keyData Pointer to the key data to be written. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_WriteKey(RTC_Type *base, const uint32_t *keyData); + +/*! + * @brief Reads a key from the RTC's non-volatile storage. + * + * @param base RTC peripheral base address. + * @param keyBuffer Pointer to a buffer where the key data will be stored. + * @return kStatus_Success if the operation was successful, kStatus_Fail if SECURE_KEY_READY is not set. + */ +status_t RTC_ReadKey(RTC_Type *base, uint32_t *keyBuffer); + +/*! @}*/ + +/*! + * @name Alive detector configuration + * @{ + */ + +/*! + * @brief Enables the RTC alive detector. + * + * @param base RTC peripheral base address. + * @param config Pointer to the rtc_alive_detector_config_t structure containing alive detector settings. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + */ +status_t RTC_ConfigureAliveDetector(RTC_Type *base, const rtc_alive_detector_config_t *config); +/*! @}*/ + +/*! + * @brief Alive detector enable + * + * @param base RTC peripheral base address. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + * + */ +status_t RTC_EnableAliveDetector(RTC_Type *base); + +/*! + * @brief Alive detector disable + * + * @param base RTC peripheral base address. + * @return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready. + * + */ +status_t RTC_DisableAliveDetector(RTC_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_RTC_H_ */ diff --git a/mcux/mcux-sdk-ng/drivers/sai/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/sai/CMakeLists.txt index bf6b09590..6a817b7ab 100644 --- a/mcux/mcux-sdk-ng/drivers/sai/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/sai/CMakeLists.txt @@ -30,7 +30,7 @@ if(CONFIG_MCUX_COMPONENT_driver.sai_sdma) endif() if(CONFIG_MCUX_COMPONENT_driver.sai) - mcux_component_version(2.4.9) + mcux_component_version(2.4.8) mcux_add_source(SOURCES fsl_sai.h fsl_sai.c) diff --git a/mcux/mcux-sdk-ng/drivers/sai/fsl_sai.c b/mcux/mcux-sdk-ng/drivers/sai/fsl_sai.c index 5d6c26191..5a7e252ef 100644 --- a/mcux/mcux-sdk-ng/drivers/sai/fsl_sai.c +++ b/mcux/mcux-sdk-ng/drivers/sai/fsl_sai.c @@ -277,16 +277,7 @@ static uint32_t SAI_GetInstance(I2S_Type *base) } } - if (instance == ARRAY_SIZE(s_saiBases)) { - assert(false); - /* asserts may not always be enabled. As such, return NULL here to - * avoid compilation warnings complaining about a possible out-of-bounds - * access. If the user decides to disable the asserts, it is up to them - * to debug in case of out-of-bounds access as SAI_GetInstance() will - * return a valid instance. - */ - return 0; - } + assert(instance < ARRAY_SIZE(s_saiBases)); return instance; } @@ -816,6 +807,13 @@ void SAI_TxSetBitClockRate( if (bitClockDiv == 1U) { tcr2 |= I2S_TCR2_BYP_MASK; +/* ERR051421 workaround: Set BCI bit when sync mode and bypass is used */ +#if defined(FSL_FEATURE_SAI_HAS_ERRATA_051421) && (FSL_FEATURE_SAI_HAS_ERRATA_051421) + if (base->RCR2 & I2S_RCR2_SYNC_MASK) + { + base->RCR2 |= I2S_RCR2_BCI(1U); + } +#endif } else #endif @@ -884,6 +882,13 @@ void SAI_RxSetBitClockRate( if (bitClockDiv == 1U) { rcr2 |= I2S_RCR2_BYP_MASK; +/* ERR051421 workaround: Set BCI bit when sync mode and bypass is used */ +#if defined(FSL_FEATURE_SAI_HAS_ERRATA_051421) && (FSL_FEATURE_SAI_HAS_ERRATA_051421) + if (base->TCR2 & I2S_TCR2_SYNC_MASK) + { + base->TCR2 |= I2S_TCR2_BCI(1U); + } +#endif } else #endif @@ -927,6 +932,14 @@ void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai tcr2 |= I2S_TCR2_BCP(config->bclkPolarity); } +/* ERR051421 workaround: Set BCI bit when sync mode and bypass is used */ +#if defined(FSL_FEATURE_SAI_HAS_ERRATA_051421) && (FSL_FEATURE_SAI_HAS_ERRATA_051421) + if ((base->RCR2 & I2S_RCR2_BYP_MASK) && (base->TCR2 & I2S_TCR2_SYNC_MASK)) + { + tcr2 |= I2S_TCR2_BCI(1U); + } +#endif + base->TCR2 = tcr2; } @@ -963,6 +976,14 @@ void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai rcr2 |= I2S_RCR2_BCP(config->bclkPolarity); } +/* ERR051421 workaround: Set BCI bit when sync mode and bypass is used */ +#if defined(FSL_FEATURE_SAI_HAS_ERRATA_051421) && (FSL_FEATURE_SAI_HAS_ERRATA_051421) + if ((base->TCR2 & I2S_TCR2_BYP_MASK) && (base->RCR2 & I2S_RCR2_SYNC_MASK)) + { + rcr2 |= I2S_RCR2_BCI(1U); + } +#endif + base->RCR2 = rcr2; } @@ -1014,8 +1035,8 @@ void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) { assert(config != NULL); #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - if (config->fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)) || - (!MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK && config->fifoWatermark == 0U)) + if ((config->fifoWatermark == 0U) || + (config->fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) { config->fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U); } @@ -1060,8 +1081,8 @@ void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) { assert(config != NULL); #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - if (config->fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)) || - (!MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK && config->fifoWatermark == 0U)) + if ((config->fifoWatermark == 0U) || + (config->fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) { config->fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U); } @@ -1205,15 +1226,24 @@ void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config) base->RCR4 = rcr4; } -#if !MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG -static void SAI_ComputeChannelConfig(I2S_Type *base, sai_transceiver_t *config) +/*! + * brief SAI transmitter configurations. + * + * param base SAI base pointer. + * param config transmitter configurations. + */ +void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config) { assert(config != NULL); assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); uint8_t i = 0U; + uint32_t val = 0U; uint8_t channelNums = 0U; + /* reset transmitter */ + SAI_TxReset(base); + /* if channel mask is not set, then format->channel must be set, use it to get channel mask value */ if (config->channelMask == 0U) @@ -1257,35 +1287,6 @@ static void SAI_ComputeChannelConfig(I2S_Type *base, sai_transceiver_t *config) } config->channelNums = channelNums; -} -#endif /* MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG */ - -/*! - * brief SAI transmitter configurations. - * - * param base SAI base pointer. - * param config transmitter configurations. - */ -void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config) -{ - uint32_t val = 0U; - - /* reset transmitter */ - SAI_TxReset(base); - -#if !MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG - /* sometimes, the user of the SAI driver may want to - * set the channel configuration (i.e: the startChannel, - * channelMask, endChannel, and channelNums fields of - * sai_transceiver_t) before calling SAI_TxSetConfig(). - * As such, if the user wants to do this, they can define - * FSL_FEATURE_SAI_DISABLE_IMPLICIT_CHAN_CONFIG which will - * stop SAI_TxSetConfig() from implicitly computing those - * values. - */ - SAI_ComputeChannelConfig(base, config); -#endif /* MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG */ - #if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) /* make sure combine mode disabled while multipe channel is used */ if (config->channelNums > 1U) @@ -1385,24 +1386,59 @@ void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiv */ void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config) { - uint32_t val = 0U; + assert(config != NULL); + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint8_t i = 0U; + uint32_t val = 0U; + uint8_t channelNums = 0U; /* reset receiver */ SAI_RxReset(base); -#if !MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG - /* sometimes, the user of the SAI driver may want to - * set the channel configuration (i.e: the startChannel, - * channelMask, endChannel, and channelNums fields of - * sai_transceiver_t) before calling SAI_RxSetConfig(). - * As such, if the user wants to do this, they can define - * FSL_FEATURE_SAI_DISABLE_IMPLICIT_CHAN_CONFIG which will - * stop SAI_RxSetConfig() from implicitly computing those - * values. - */ - SAI_ComputeChannelConfig(base, config); -#endif /* MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG */ + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (config->channelMask == 0U) + { + if(config->startChannel < 8U) + { + config->channelMask = 1; + config->channelMask <<= config->startChannel; + } + else + { + config->channelMask = UINT8_MAX; + } + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), config->channelMask)) + { + // Prevent potential addition overflow by capping at maximum value + if (channelNums < UINT8_MAX) + { + channelNums++; + } + else + { + channelNums = UINT8_MAX; + } + + config->endChannel = i; + } + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), config->channelMask)) + { + config->startChannel = i; + break; + } + } + config->channelNums = channelNums; #if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) /* make sure combine mode disabled while multipe channel is used */ if (config->channelNums > 1U) diff --git a/mcux/mcux-sdk-ng/drivers/sai/fsl_sai.h b/mcux/mcux-sdk-ng/drivers/sai/fsl_sai.h index b798be3fa..d7b5a35a4 100644 --- a/mcux/mcux-sdk-ng/drivers/sai/fsl_sai.h +++ b/mcux/mcux-sdk-ng/drivers/sai/fsl_sai.h @@ -20,30 +20,6 @@ * Definitions ******************************************************************************/ -/*! @brief Used to control whether SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig() - * allows a NULL FIFO watermark. - * - * If this macro is set to 0 then SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig() - * will set the watermark to half of the FIFO's depth if passed a NULL - * watermark. - */ -#ifndef MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK -#define MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK 0 -#endif /* MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK */ - -/*! @brief Disable implicit channel data configuration within SAI_TxSetConfig()/SAI_RxSetConfig(). - * - * Use this macro to control whether SAI_RxSetConfig()/SAI_TxSetConfig() will - * attempt to implicitly configure the channel data. By channel data we mean - * the startChannel, channelMask, endChannel, and channelNums fields from the - * sai_transciever_t structure. By default, SAI_TxSetConfig()/SAI_RxSetConfig() - * will attempt to compute these fields, which may not be desired in cases where - * the user wants to set them before the call to said functions. - */ -#ifndef MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG -#define MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG 0 -#endif /* MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG */ - /*! @name Driver version */ /*! @{ */ #define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 4, 9)) /*!< Version 2.4.9 */ @@ -1478,4 +1454,4 @@ void SAI_DriverIRQHandler(uint32_t instance); /*! @} */ -#endif /* _FSL_SAI_H_ */ +#endif /* FSL_SAI_H_ */ diff --git a/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c b/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c index 9c9eb2c4c..2f657b454 100644 --- a/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c +++ b/mcux/mcux-sdk-ng/drivers/sar_adc/fsl_sar_adc.c @@ -187,24 +187,24 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config) /* Set GROUPn sample phase duration. */ base->CTR0 = ((base->CTR0 & (~ADC_CTR0_INPSAMP_MASK)) | ADC_CTR0_INPSAMP(config->samplePhaseDuration[0U])); base->CTR1 = ((base->CTR1 & (~ADC_CTR1_INPSAMP_MASK)) | ADC_CTR1_INPSAMP(config->samplePhaseDuration[1U])); -#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) - if(1U == FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n) + if(1U == FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n(base)) { base->CTR2 = ((base->CTR2 & (~ADC_CTR2_INPSAMP_MASK)) | ADC_CTR2_INPSAMP(config->samplePhaseDuration[2U])); } -#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n */ /* Set GROUPn pre-sample voltage sources and decide whether to convert the pre-sample value. */ base->PSCR = ((base->PSCR & (~(ADC_PSCR_PREVAL0_MASK | ADC_PSCR_PREVAL1_MASK | ADC_PSCR_PRECONV_MASK))) | (ADC_PSCR_PREVAL0(config->presampleVoltageSrc[0U]) | ADC_PSCR_PREVAL1(config->presampleVoltageSrc[1U]) | ADC_PSCR_PRECONV(config->enableConvertPresampleVal ? 1U : 0U))); -#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) - if(1U == FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n) + if(1U == FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n(base)) { base->PSCR = ((base->PSCR & (~ADC_PSCR_PREVAL2_MASK)) | ADC_PSCR_PREVAL1(config->presampleVoltageSrc[2U])); } -#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n */ } /*! @@ -265,12 +265,12 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config) for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index) { -#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) - if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n) + if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n(base)) { break; } -#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n */ /* 1. Set conversion channel's interrupt.*/ *(((volatile uint32_t *)(&(base->CIMR0))) + index) = convChannelIntMask[index]; @@ -291,12 +291,12 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config) { for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index) { -#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) - if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n) + if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n(base)) { break; } -#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n */ *(((volatile uint32_t *)(&(base->JCMR0))) + index) = convChannelMask[index]; } @@ -313,12 +313,12 @@ void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config) { for (uint8_t index = 0U; index < (uint8_t)ADC_GROUP_COUNTS; ++index) { -#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3) - if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3(base)) +#if defined (FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n) + if(1U != FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n(base)) { break; } -#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3 */ +#endif /* FSL_FEATURE_ADC_INSTANCE_SUPPORT_GROUP3n */ *(((volatile uint32_t *)(&(base->NCMR0))) + index) = convChannelMask[index]; } diff --git a/mcux/mcux-sdk-ng/drivers/sema4/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/sema4/CMakeLists.txt index 76200a250..1b6fde9c1 100644 --- a/mcux/mcux-sdk-ng/drivers/sema4/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/sema4/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.sema4) - mcux_component_version(2.2.0) + mcux_component_version(2.2.2) mcux_add_source(SOURCES fsl_sema4.h fsl_sema4.c) diff --git a/mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.c b/mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.c index 747ddeb73..67dec80a1 100644 --- a/mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.c +++ b/mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.c @@ -137,7 +137,7 @@ status_t SEMA4_TryLock(SEMA4_Type *base, uint8_t gateNum, uint8_t procNum) assert(gateNum < (uint8_t)FSL_FEATURE_SEMA4_GATE_COUNT); - if (procNum < UINT8_MAX) { + if (procNum < 0xFEU) { ++procNum; } else { /* Handle error case - procNum is at maximum value */ diff --git a/mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.h b/mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.h index 3360c0f78..6b308194f 100644 --- a/mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.h +++ b/mcux/mcux-sdk-ng/drivers/sema4/fsl_sema4.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief SEMA4 driver version */ -#define FSL_SEMA4_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +#define FSL_SEMA4_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*! @} */ /*! @brief The number to reset all SEMA4 gates. */ @@ -213,7 +213,7 @@ static inline status_t SEMA4_ResetAllGates(SEMA4_Type *base) */ static inline void SEMA4_EnableGateNotifyInterrupt(SEMA4_Type *base, uint8_t procNum, uint16_t mask) { - mask = __REV(__RBIT(mask)); + mask = (uint16_t)(__REV(__RBIT(mask)) & 0xFFFFU); base->CPINE[procNum].CPINE |= mask; } @@ -230,7 +230,7 @@ static inline void SEMA4_EnableGateNotifyInterrupt(SEMA4_Type *base, uint8_t pro */ static inline void SEMA4_DisableGateNotifyInterrupt(SEMA4_Type *base, uint8_t procNum, uint16_t mask) { - mask = __REV(__RBIT(mask)); + mask = (uint16_t)(__REV(__RBIT(mask)) & 0xFFFFU); base->CPINE[procNum].CPINE &= (~mask); } diff --git a/mcux/mcux-sdk-ng/drivers/sema42/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/sema42/CMakeLists.txt index 46b4b5398..84555ac10 100644 --- a/mcux/mcux-sdk-ng/drivers/sema42/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/sema42/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.sema42) - mcux_component_version(2.1.0) + mcux_component_version(2.1.1) mcux_add_source(SOURCES fsl_sema42.h fsl_sema42.c) diff --git a/mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.c b/mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.c index 49a265a95..e2dfccdeb 100644 --- a/mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.c +++ b/mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.c @@ -67,14 +67,14 @@ uint32_t SEMA42_GetInstance(SEMA42_Type *base) * (instance >= ARRAY_SIZE(s_sema42Bases)) not covered. The peripheral base * address is always valid and checked by assert. */ - for (instance = 0; instance < ARRAY_SIZE(s_sema42Bases); instance++) + for (instance = 0; instance < ARRAY_SIZE(s_sema42Bases); instance++) /* GCOVR_EXCL_BR_LINE */ { /* * $Branch Coverage Justification$ * (s_sema42Bases[instance] != base) not covered. The peripheral base * address is always valid and checked by assert. */ - if (MSDK_REG_SECURE_ADDR(s_sema42Bases[instance]) == MSDK_REG_SECURE_ADDR(base)) + if (MSDK_REG_SECURE_ADDR(s_sema42Bases[instance]) == MSDK_REG_SECURE_ADDR(base)) /* GCOVR_EXCL_BR_LINE */ { break; } @@ -140,7 +140,7 @@ status_t SEMA42_TryLock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum) assert(gateNum < (uint8_t)FSL_FEATURE_SEMA42_GATE_COUNT); - if (procNum < UINT8_MAX) { + if (procNum < (0xFEU)) { ++procNum; } else { /* Handle error case - procNum is at maximum value */ @@ -226,13 +226,13 @@ status_t SEMA42_ResetGate(SEMA42_Type *base, uint8_t gateNum) * (0U == (base->RSTGT_R & SEMA42_RSTGT_R_RSTGSM_MASK))) not covered. Test unfeasible, * the reset state is too short to catch. */ - if (0U != (base->RSTGT_R & SEMA42_RSTGT_R_RSTGSM_MASK)) + if (0U != (base->RSTGT_R & SEMA42_RSTGT_R_RSTGSM_MASK)) /* GCOVR_EXCL_BR_LINE */ { /* * $Line Coverage Justification$ * Block not covered. Test unfeasible, the reset state is too short to catch. */ - status = kStatus_SEMA42_Reseting; + status = kStatus_SEMA42_Reseting; /* GCOVR_EXCL_LINE */ } else { diff --git a/mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.h b/mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.h index 0bd22b330..91ec61bf1 100644 --- a/mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.h +++ b/mcux/mcux-sdk-ng/drivers/sema42/fsl_sema42.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief SEMA42 driver version */ -#define FSL_SEMA42_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +#define FSL_SEMA42_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*! @} */ /*! diff --git a/mcux/mcux-sdk-ng/drivers/sfa/fsl_sfa.c b/mcux/mcux-sdk-ng/drivers/sfa/fsl_sfa.c index fd007f797..b3f2564f5 100644 --- a/mcux/mcux-sdk-ng/drivers/sfa/fsl_sfa.c +++ b/mcux/mcux-sdk-ng/drivers/sfa/fsl_sfa.c @@ -976,9 +976,13 @@ void SFA0_DriverIRQHandler(void) #endif #if defined(RF_SFA) +/* + * $Line Coverage Justification$ + * RF_SFA is not accessable in CM33 domain. + */ void RF_SFA_DriverIRQHandler(void); void RF_SFA_DriverIRQHandler(void) { SFA_CommonIRQHandler(RF_SFA); } -#endif \ No newline at end of file +#endif diff --git a/mcux/mcux-sdk-ng/drivers/slcd/fsl_slcd.c b/mcux/mcux-sdk-ng/drivers/slcd/fsl_slcd.c index 341df825a..ba69cab83 100644 --- a/mcux/mcux-sdk-ng/drivers/slcd/fsl_slcd.c +++ b/mcux/mcux-sdk-ng/drivers/slcd/fsl_slcd.c @@ -139,7 +139,7 @@ void SLCD_Init(LCD_Type *base, slcd_config_t *configure) #endif #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT /* Configure for frame frequency interrupt. */ - gcrReg |= LCD_GCR_LCDIEN(configure->frameFreqIntEnable); + gcrReg |= LCD_GCR_LCDIEN(configure->frameFreqIntEnable ? 1U : 0U); gcrMsk |= LCD_GCR_LCDIEN_MASK; #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */ #if FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE diff --git a/mcux/mcux-sdk-ng/drivers/slcd_split/fsl_slcd.c b/mcux/mcux-sdk-ng/drivers/slcd_split/fsl_slcd.c index d4412bf7d..0ac941b74 100644 --- a/mcux/mcux-sdk-ng/drivers/slcd_split/fsl_slcd.c +++ b/mcux/mcux-sdk-ng/drivers/slcd_split/fsl_slcd.c @@ -111,9 +111,9 @@ void SLCD_Init(SLCD_Type *base, const slcd_config_t *configure) gcrReg = SGLCD_CONTROL_GCR_DUTY(configure->dutyCycle) | SGLCD_CONTROL_GCR_LCDSTP((uint32_t)configure->lowPowerBehavior & 0x1U) | SGLCD_CONTROL_GCR_LCLK(configure->clkPrescaler) | SGLCD_CONTROL_GCR_SHCYCLE(configure->sampleHold & 0x1U) | SGLCD_CONTROL_GCR_SHEN((configure->sampleHold & 0x2U) >> 1U) | SGLCD_CONTROL_GCR_VLL2TRIM(configure->voltageTrimVLL2) | - SGLCD_CONTROL_GCR_VLL1TRIM(configure->voltageTrimVLL1) | SGLCD_CONTROL_GCR_LCDLP(configure->lowPowerWaveform) | + SGLCD_CONTROL_GCR_VLL1TRIM(configure->voltageTrimVLL1) | SGLCD_CONTROL_GCR_LCDLP(configure->lowPowerWaveform ? 1U : 0U) | SGLCD_CONTROL_GCR_LCDDOZE(((uint32_t)configure->lowPowerBehavior >> 1U) & 0x1U) | - SGLCD_CONTROL_GCR_LCDIEN(configure->frameFreqIntEnable); + SGLCD_CONTROL_GCR_LCDIEN(configure->frameFreqIntEnable ? 1U : 0U); base->control->GCR = (base->control->GCR & ~gcrMsk) | gcrReg; diff --git a/mcux/mcux-sdk-ng/drivers/smartdma/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/smartdma/CMakeLists.txt index 2a5ff1152..f658c537d 100644 --- a/mcux/mcux-sdk-ng/drivers/smartdma/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/smartdma/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.smartdma) - mcux_component_version(2.13.0) + mcux_component_version(2.13.2) mcux_add_source( SOURCES @@ -43,7 +43,7 @@ if(CONFIG_MCUX_COMPONENT_driver.smartdma_mcxn) endif() if(CONFIG_MCUX_COMPONENT_driver.smartdma_mcxa) - mcux_component_version(2.13.0) + mcux_component_version(2.13.2) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma.h b/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma.h index 2383981ec..2d10172df 100644 --- a/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma.h +++ b/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma.h @@ -11,12 +11,19 @@ #if defined(MIMXRT533S_SERIES) || defined(MIMXRT555S_SERIES) || defined(MIMXRT595S_cm33_SERIES) #include "fsl_smartdma_rt500.h" -#elif defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ - defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || defined(MCXN946_cm33_core0_SERIES) || \ - defined(MCXN946_cm33_core1_SERIES) || defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \ - defined(MCXN236_SERIES) || defined(MCXN235_SERIES) +#elif defined(MCXN235_SERIES) || defined(MCXN236_SERIES) || defined(MCXN247_SERIES) || \ + defined(MCXN526_cm33_core0_SERIES) || defined(MCXN526_cm33_core1_SERIES) || defined(MCXN527_cm33_core0_SERIES) || \ + defined(MCXN527_cm33_core1_SERIES) || defined(MCXN536_cm33_core0_SERIES) || defined(MCXN536_cm33_core1_SERIES) || \ + defined(MCXN537_cm33_core0_SERIES) || defined(MCXN537_cm33_core1_SERIES) || defined(MCXN546_cm33_core0_SERIES) || \ + defined(MCXN546_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \ + defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) || \ + defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || defined(MCXN947_cm33_core0_SERIES) || \ + defined(MCXN947_cm33_core1_SERIES) #include "fsl_smartdma_mcxn.h" -#elif defined(MCXA345_SERIES) || defined(MCXA346_SERIES) || defined(MCXA276_SERIES) +#elif defined(MCXA175_SERIES) || defined(MCXA176_SERIES) || defined(MCXA185_SERIES) || defined(MCXA186_SERIES) || \ + defined(MCXA255_SERIES) || defined(MCXA256_SERIES) || defined(MCXA265_SERIES) || defined(MCXA266_SERIES) || \ + defined(MCXA345_SERIES) || defined(MCXA346_SERIES) || defined(MCXA355_SERIES) || defined(MCXA356_SERIES) || \ + defined(MCXA365_SERIES) || defined(MCXA366_SERIES) || defined(MCXA343_SERIES) || defined(MCXA344_SERIES) #include "fsl_smartdma_mcxa.h" #else #error "Device not supported" @@ -34,7 +41,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief SMARTDMA driver version */ -#define FSL_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 13, 0)) +#define FSL_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 13, 2)) /*@}*/ /*! @brief Callback function prototype for the smartdma driver. */ diff --git a/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_mcxa.c b/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_mcxa.c index 9143fd391..a2a8b6a03 100644 --- a/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_mcxa.c +++ b/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_mcxa.c @@ -6,8 +6,15 @@ #include "fsl_smartdma.h" -#if defined(MCXA276_SERIES) || defined(MCXA275_SERIES) || defined(MCXA176_SERIES) || defined(MCXA175_SERIES)|| \ - defined(MCXA166_SERIES) || defined(MCXA165_SERIES) || defined(MCXA345_SERIES) || defined(MCXA346_SERIES) +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.smartdma_mcxa" +#endif + +#if defined(MCXA175_SERIES) || defined(MCXA176_SERIES) || defined(MCXA185_SERIES) || defined(MCXA186_SERIES) || \ + defined(MCXA255_SERIES) || defined(MCXA256_SERIES) || defined(MCXA265_SERIES) || defined(MCXA266_SERIES) || \ + defined(MCXA345_SERIES) || defined(MCXA346_SERIES) || defined(MCXA355_SERIES) || defined(MCXA356_SERIES) || \ + defined(MCXA365_SERIES) || defined(MCXA366_SERIES) || defined(MCXA343_SERIES) || defined(MCXA344_SERIES) /******************************************************************************* * Definitions diff --git a/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_mcxn.c b/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_mcxn.c index 456b0e95e..ba1055ff7 100644 --- a/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_mcxn.c +++ b/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_mcxn.c @@ -7,9 +7,19 @@ #include "fsl_smartdma.h" -#if defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \ - defined(MCXN547_cm33_core1_SERIES) || defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ - defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || defined(MCXN236_SERIES) +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.smartdma_mcxn" +#endif + +#if defined(MCXN235_SERIES) || defined(MCXN236_SERIES) || defined(MCXN247_SERIES) || \ + defined(MCXN526_cm33_core0_SERIES) || defined(MCXN526_cm33_core1_SERIES) || defined(MCXN527_cm33_core0_SERIES) || \ + defined(MCXN527_cm33_core1_SERIES) || defined(MCXN536_cm33_core0_SERIES) || defined(MCXN536_cm33_core1_SERIES) || \ + defined(MCXN537_cm33_core0_SERIES) || defined(MCXN537_cm33_core1_SERIES) || defined(MCXN546_cm33_core0_SERIES) || \ + defined(MCXN546_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || \ + defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) || \ + defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || defined(MCXN947_cm33_core0_SERIES) || \ + defined(MCXN947_cm33_core1_SERIES) /******************************************************************************* * Definitions diff --git a/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_rt500.c b/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_rt500.c index 020e794a8..6f70a1091 100644 --- a/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_rt500.c +++ b/mcux/mcux-sdk-ng/drivers/smartdma/fsl_smartdma_rt500.c @@ -6,6 +6,11 @@ #include "fsl_smartdma.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.smartdma_rt500" +#endif + #if defined(MIMXRT533S_SERIES) || defined(MIMXRT555S_SERIES) || defined(MIMXRT595S_cm33_SERIES) /******************************************************************************* diff --git a/mcux/mcux-sdk-ng/drivers/smm/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/smm/CMakeLists.txt index ae1cf6b90..93906a561 100644 --- a/mcux/mcux-sdk-ng/drivers/smm/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/smm/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.smm) - mcux_component_version(2.0.0) + mcux_component_version(2.1.0) mcux_add_source(SOURCES fsl_smm.h fsl_smm.c) diff --git a/mcux/mcux-sdk-ng/drivers/smm/fsl_smm.c b/mcux/mcux-sdk-ng/drivers/smm/fsl_smm.c index 73d788222..5b8fe8e9c 100644 --- a/mcux/mcux-sdk-ng/drivers/smm/fsl_smm.c +++ b/mcux/mcux-sdk-ng/drivers/smm/fsl_smm.c @@ -16,7 +16,7 @@ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.smm +#define FSL_COMPONENT_ID "platform.drivers.smm" #endif diff --git a/mcux/mcux-sdk-ng/drivers/smm/fsl_smm.h b/mcux/mcux-sdk-ng/drivers/smm/fsl_smm.h index 9d1b7806b..02b33f677 100644 --- a/mcux/mcux-sdk-ng/drivers/smm/fsl_smm.h +++ b/mcux/mcux-sdk-ng/drivers/smm/fsl_smm.h @@ -25,10 +25,36 @@ /*! @name Driver version */ /*@{*/ -/*! @brief smm driver version 2.0.0. */ -#define FSL_SMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief smm driver version 2.1.0. */ +#define FSL_SMM_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ +/*! + * @brief The enumeration of interrupt to enable. + * @anchor smm_interrupt_enable_t. + */ +enum _smm_interrupt_enable +{ + kSMM_QChannelTimeoutInt = 1UL << 12UL, + kSMM_QChannelDenyInt = 1UL << 14UL, + kSMM_DeepSleepCounterInt = 1UL << 9UL, + kSMM_ComparatorMatchInt = 1UL << 8UL, + kSMM_AllSupportedInts = (kSMM_QChannelTimeoutInt | kSMM_QChannelDenyInt | \ + kSMM_DeepSleepCounterInt | kSMM_ComparatorMatchInt), +}; + +/*! + * @brief The enumeration of interrupt flag. + * @anchor smm_interrupt_flag_t + */ +enum _smm_interrupt_flag +{ + kSMM_QChannelTimeoutIntFlag = 1UL << 13UL, + kSMM_QChannelDenyIntFlag = 1UL << 15UL, + + kSMM_AllIntFlags = kSMM_QChannelTimeoutIntFlag | kSMM_QChannelDenyIntFlag, +}; + /*! * @brief The enumeration of external interrupt polarity. */ @@ -56,6 +82,15 @@ typedef struct _smm_backup_reg_content uint32_t word2; /* The second word of backend register 2. */ } smm_backup_reg_content_t; +/*! + * @brief Watchdog alarm use enumeration. + */ +typedef enum _smm_watchdog_alarm_use +{ + kSMM_WatchdogAlarmAsReset = 0U, /*!< Watchdog alarm as reset. */ + kSMM_WatchdogAlarmAsInterrupt = 1U /*!< Watchdog alarm as interrupt. */ +} smm_watchdog_alarm_use_t; + /******************************************************************************* * API ******************************************************************************/ @@ -99,7 +134,7 @@ static inline void SMM_DisableMainCpuIsoSingal(SMM_Type *base) */ static inline void SMM_EnableWakeupSourceToMainCpu(SMM_Type *base, uint32_t wakeupSources) { - base->WKUP_MAIN = SMM_WKUP_MAIN_WKUP_SRC_MAIN_CPU(1UL << wakeupSources); + base->WKUP_MAIN = SMM_WKUP_MAIN_WKUP_SRC_MAIN_CPU(wakeupSources); } /*! @@ -110,7 +145,7 @@ static inline void SMM_EnableWakeupSourceToMainCpu(SMM_Type *base, uint32_t wake */ static inline void SMM_DisableWakeupSourceToMainCpu(SMM_Type *base, uint32_t wakeupSources) { - base->WKUP_MAIN &= ~SMM_WKUP_MAIN_WKUP_SRC_MAIN_CPU(1UL<< wakeupSources); + base->WKUP_MAIN &= ~SMM_WKUP_MAIN_WKUP_SRC_MAIN_CPU(wakeupSources); } /*! @@ -133,7 +168,7 @@ static inline uint32_t SMM_GetEnabledWakeupSourceToMainCpu(SMM_Type *base) */ static inline void SMM_EnableWakeupSourceToAonCpu(SMM_Type *base, uint32_t wakeupSources) { - base->AON_CPU = SMM_AON_CPU_WKUP_SRC_AON_CPU(1UL << wakeupSources); + base->AON_CPU = SMM_AON_CPU_WKUP_SRC_AON_CPU(wakeupSources); } /*! @@ -144,7 +179,7 @@ static inline void SMM_EnableWakeupSourceToAonCpu(SMM_Type *base, uint32_t wakeu */ static inline void SMM_DisableWakeupSourceToAonCpu(SMM_Type *base, uint32_t wakeupSources) { - base->AON_CPU &= ~SMM_AON_CPU_WKUP_SRC_AON_CPU(1UL << wakeupSources); + base->AON_CPU &= ~SMM_AON_CPU_WKUP_SRC_AON_CPU(wakeupSources); } /*! @@ -280,7 +315,7 @@ static inline void SMM_PowerOnAonSramManually(SMM_Type *base, uint8_t sramCuts) static inline void SMM_PowerOffAonSramAutomatically(SMM_Type *base, uint8_t sramCuts) { base->PWDN_CONFIG |= SMM_PWDN_CONFIG_CTRL_SRAM_DPD2_MASK; - base->MEMORY_RTN = ((base->MEMORY_RTN & ~SMM_MEMORY_RTN_CPU_RAM_PWD_MASK) | SMM_MEMORY_RTN_CPU_RAM_PWD(sramCuts)); + base->MEMORY_RTN = ((base->MEMORY_RTN & ~SMM_MEMORY_RTN_CPU_SRAMBn_PWD_MASK) | SMM_MEMORY_RTN_CPU_SRAMBn_PWD(sramCuts)); } /*! @@ -399,7 +434,26 @@ static inline void SMM_ClearExternalIntFlag(SMM_Type *base) static inline void SMM_DisableMainCpuIso(SMM_Type *base) { base->CNFG |= (SMM_CNFG_MAIN_ISO_DSBL_MASK); + for (uint32_t i = 0UL; i < 1000UL; i++) + { + i++; + } base->CNFG &= ~(SMM_CNFG_MAIN_ISO_DSBL_MASK); + + for (uint32_t i = 0UL; i < 1000UL; i++) + { + i++; + } + base->CNFG |= (SMM_CNFG_MAIN_ISO_DSBL_MASK); + for (uint32_t i = 0UL; i < 1000UL; i++) + { + i++; + } + base->CNFG &= ~(SMM_CNFG_MAIN_ISO_DSBL_MASK); + for (uint32_t i = 0UL; i < 1000UL; i++) + { + i++; + } } /*! @@ -410,7 +464,25 @@ static inline void SMM_DisableMainCpuIso(SMM_Type *base) static inline void SMM_DisableAonCpuIso(SMM_Type *base) { base->CNFG |= (SMM_CNFG_AON_ISO_DSBL_MASK); + for (uint32_t i = 0UL; i < 1000UL; i++) + { + i++; + } + base->CNFG &= ~(SMM_CNFG_AON_ISO_DSBL_MASK); + for (uint32_t i = 0UL; i < 1000UL; i++) + { + i++; + } + base->CNFG |= (SMM_CNFG_AON_ISO_DSBL_MASK); + for (uint32_t i = 0UL; i < 1000UL; i++) + { + i++; + } base->CNFG &= ~(SMM_CNFG_AON_ISO_DSBL_MASK); + for (uint32_t i = 0UL; i < 1000UL; i++) + { + i++; + } } /*! @@ -436,13 +508,189 @@ static inline void SMM_ClearMainCpuWakeupSources(SMM_Type *base) /*! * @brief Clear all wakeup sources to AON domain. * - * @param base + * @param base SMM base address. */ static inline void SMM_ClearAonCpuWakeupSources(SMM_Type *base) { base->AON_CPU &= ~SMM_AON_CPU_WKUP_SRC_AON_CPU_MASK; } +/*! + * @brief Config the watchdog alarm use. + * + * @param base SMM base address. + * @param alarmUse The watchdog alarm use. + */ +static inline void SMM_ConfigWatchdogAlarmUse(SMM_Type *base, smm_watchdog_alarm_use_t alarmUse) +{ + base->CNFG &= ~(SMM_CNFG_WTCHDG_USE_INT_MASK); + base->CNFG |= SMM_CNFG_WTCHDG_USE_INT(alarmUse); +} + +/*! + * @brief Use the deep sleep counter for general software needs. + * + * @param base SMM base address. + */ +static inline void SMM_UseDeepSleepCounterInSoftwareMethod(SMM_Type *base) +{ + base->CNFG |= SMM_CNFG_DSLP_COUNT_USE_MASK; +} + +/*! + * @brief Use the deep sleep counter by hardware to wakeup from low power mode. + * + * @param base SMM base address. + */ +static inline void SMM_UseDeepSleepCounterInHardwareMethod(SMM_Type *base) +{ + base->CNFG &= ~SMM_CNFG_DSLP_COUNT_USE_MASK; +} + +/*! + * @brief Reset the deep sleep counter and disable count. + * + * @param base SMM base address. + */ +static inline void SMM_ResetAndDisableDeepSleepCounter(SMM_Type *base) +{ + base->CNFG |= SMM_CNFG_DSLP_COUNT_RST_MASK; + for (uint32_t i = 0UL; i < 1000UL; i++) + { + i++; + } + base->CNFG &= ~SMM_CNFG_DSLP_COUNT_RST_MASK; +} + +/*! + * @brief Enable the countdown start of the deep sleep counter when at sofware use. + * + * @param base SMM base address. + */ +static inline void SMM_StartDeepSleepCounter(SMM_Type *base) +{ + base->CNFG |= SMM_CNFG_DSLP_COUNT_STRT_MASK; +} + +/*! + * @brief Update the deep sleep counter, the counter is counting the AON clocks. + * + * @param base SMM base address. + * @param value Value to update the deep sleep counter. + */ +static inline void SMM_UpdateDeepSleepCounter(SMM_Type *base, uint16_t value) +{ + base->DPSLP_COUNT = SMM_DPSLP_COUNT_DPSLP_CNT(value); +} + +/*! + * @brief Read value of deep sleep counter. + * + * @param base SMM base address. + * + * @return Count of deep sleep counter. + */ +static inline uint16_t SMM_ReadDeepSleepCounter(SMM_Type *base) +{ + return (uint16_t)(base->DPSLP_COUNT); +} + +/*! + * @brief Enable specific interrupts. + * + * @param base SMM base address. + * @param masks The mask of interrupts to enable, should be OR'ed value of @ref smm_interrupt_enable_t. + */ +static inline void SMM_EnableInterrupts(SMM_Type *base, uint32_t masks) +{ + uint32_t tmp32 = base->STAT; + + tmp32 &= ~(kSMM_AllSupportedInts); + base->STAT = (tmp32 | (masks & kSMM_AllSupportedInts)); +} + +/*! + * @brief Disable specific interrupts. + * + * @param base SMM base address. + * @param masks The mask of interrupts to disable, should be OR'ed value of @ref smm_interrupt_enable_t. + */ +static inline void SMM_DisableInterrupts(SMM_Type *base, uint32_t masks) +{ + uint32_t tmp32 = base->STAT; + + tmp32 &= ~(kSMM_AllSupportedInts); + base->STAT = tmp32 & (~(masks & kSMM_AllSupportedInts)); +} + +/*! + * @brief Get interrupt flags. + * + * @param base SMM base address. + * + * @return The mask of all asserted interrupt flags, should be the OR'ed value of @ref smm_interrupt_flag_t. + */ +static inline uint32_t SMM_GetInterruptFlags(SMM_Type *base) +{ + return ((base->STAT) & kSMM_AllIntFlags); +} + +/*! + * @brief Clear interrupt flags. + * + * @param base SMM base address. + * @param flags The mask of interrupt flags to clear, should be the OR'ed value of @ref smm_interrupt_flag_t. + */ +static inline void SMM_ClearInterruptFlags(SMM_Type *base, uint32_t flags) +{ + base->STAT = (flags & kSMM_AllIntFlags); +} + +/*! + * @brief Check if deep sleep counter reach zero at software use. + * + * @param base SMM base address. + * + * @retval false Deep sleep counter do not reach zero. + * @retval true Deep sleep counter reach zero. + */ +static inline bool SMM_CheckDeepSleepCounterMatch(SMM_Type *base) +{ + return ((base->STAT & SMM_STAT_DPSLP_CNTR_M_MASK) != 0UL); +} + +/*! + * @brief Clear deep sleep counter match flag. + * + * @param base SMM base address. + */ +static inline void SMM_ClearDeepSleepCounterMatchFlag(SMM_Type *base) +{ + base->STAT = SMM_STAT_DPSLP_CNTR_M_MASK; +} + +/*! + * @brief Check if comparator match was active. + * + * @param base SMM base address. + * + * @retval false Comparator match is not active. + * @retval true Comparator match is active. + */ +static inline bool SMM_CheckComparatorMatch(SMM_Type *base) +{ + return ((base->STAT & SMM_STAT_COMP_MATCH_MASK) != 0UL); +} + +/*! + * @brief Clear comparator match flag. + * + * @param base SMM base address. + */ +static inline void SMM_ClearComparatorMatchFlag(SMM_Type *base) +{ + base->STAT = SMM_STAT_COMP_MATCH_MASK; +} #if defined(__cplusplus) } diff --git a/mcux/mcux-sdk-ng/drivers/spc/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/spc/CMakeLists.txt index 818d606e1..1e8787aba 100644 --- a/mcux/mcux-sdk-ng/drivers/spc/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/spc/CMakeLists.txt @@ -3,10 +3,10 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.spc) - mcux_component_version(2.6.1) + mcux_component_version(2.7.0) - mcux_add_source(SOURCES fsl_spc.c fsl_spc.h) + mcux_add_source(SOURCES fsl_spc.c fsl_spc.h) - mcux_add_include(INCLUDES .) + mcux_add_include(INCLUDES .) endif() diff --git a/mcux/mcux-sdk-ng/drivers/spc/fsl_spc.c b/mcux/mcux-sdk-ng/drivers/spc/fsl_spc.c index c9e4d214e..716fcf987 100644 --- a/mcux/mcux-sdk-ng/drivers/spc/fsl_spc.c +++ b/mcux/mcux-sdk-ng/drivers/spc/fsl_spc.c @@ -133,7 +133,7 @@ void SPC_SetActiveModeIntegratedPowerSwitchConfig(SPC_Type *base, const spc_inte /*! * brief Configs Bandgap mode in Active mode. * - * note In active mode, beacause CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to + * note In active mode, because CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to * disable Bandgap in active mode * * param base SPC peripheral base address. @@ -159,10 +159,15 @@ status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t m return kStatus_SPC_BandgapModeWrong; } + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) == SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength) || - (base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) + (base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == + SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) { return kStatus_SPC_BandgapModeWrong; } @@ -252,6 +257,10 @@ status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t return kStatus_SPC_BandgapModeWrong; } + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ if (((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) || ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == @@ -467,7 +476,7 @@ void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_d base->VD_SYS_CFG = reg; (void)(config->level); - + /* SPC_SetSystemVDDLowVoltageLevel(base, config->level); */ } @@ -817,6 +826,10 @@ status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_activ } #if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ if (option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength) { /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. @@ -840,12 +853,11 @@ status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_activ base->ACTIVE_CFG = ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(option->CoreLDOVoltage)); - /* * $Branch Coverage Justification$ * $ref spc_c_ref_1$. */ -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY while ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -891,7 +903,7 @@ status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_low uint32_t timeout = SPC_BUSY_TIMEOUT; #endif -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY if ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -920,6 +932,10 @@ status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_low } preVoltage = SPC_GetLowPowerCoreLDOVDDVoltageLevel(base); + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ /* Core LDO voltage level can only be changed when the Core LDO Drive Strength set to Normal */ if ((option->CoreLDOVoltage >= kSPC_CoreLDO_MidDriveVoltage) && (preVoltage != option->CoreLDOVoltage)) { @@ -933,7 +949,7 @@ status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_low * $Branch Coverage Justification$ * $ref spc_c_ref_1$. */ -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY while ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -984,7 +1000,7 @@ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_act uint32_t timeout = SPC_BUSY_TIMEOUT; #endif -#if (defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY) +#if (defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY) if ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -995,7 +1011,6 @@ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_act * $ref spc_c_ref_1$. */ return kStatus_SPC_Busy; - } if (option->SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) @@ -1017,6 +1032,10 @@ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_act return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; } + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ /* If select voltage level as Over Drive Voltage, Drive Strength can not be set to low. */ if (option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage) { @@ -1035,7 +1054,7 @@ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_act * $Branch Coverage Justification$ * $ref spc_c_ref_1$. */ -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY while ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1078,7 +1097,7 @@ status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_l uint32_t timeout = SPC_BUSY_TIMEOUT; #endif -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY if ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1111,7 +1130,7 @@ status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_l * $Branch Coverage Justification$ * $ref spc_c_ref_1$. */ -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY while ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1158,7 +1177,7 @@ status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_m uint32_t reg; uint32_t state; -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY if ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1191,7 +1210,7 @@ status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_m * $Branch Coverage Justification$ * $ref spc_c_ref_1$. */ -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY while ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1236,7 +1255,7 @@ status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpow uint32_t timeout = SPC_BUSY_TIMEOUT; #endif -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY if ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1253,6 +1272,10 @@ status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpow if (state != 0UL) { + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ /* If any HVD/LVDs are kept enabled write to set DCDC regulator's drive strength to low/pluse refresh will be * ignored. */ if (option->DCDCDriveStrength == kSPC_DCDC_PulseRefreshMode) @@ -1279,7 +1302,7 @@ status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpow * $Branch Coverage Justification$ * $ref spc_c_ref_1$. */ -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY while ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1398,9 +1421,13 @@ status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode if (status == kStatus_Success) { status = SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ if (status == kStatus_Success) { - while(SPC_GetBusyStatusFlag(base) == true) + while (SPC_GetBusyStatusFlag(base) == true) { #if SPC_BUSY_TIMEOUT if ((--timeout) == 0U) @@ -1510,7 +1537,7 @@ status_t SPC_SetSRAMOperateVoltage(SPC_Type *base, spc_sram_operat_voltage_t vol #if (defined(FSL_FEATURE_SPC_HAS_HP_CFG_REG) && FSL_FEATURE_SPC_HAS_HP_CFG_REG) /*! * brief Set bandgap mode in high power mode. - * + * * param base SPC peripheral base address. * param mode Specify the bandgap mode in high power mode. * @@ -1536,24 +1563,28 @@ status_t SPC_SetHighPowerModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_ /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ if (((base->HP_CFG & SPC_HP_CFG_SYSLDO_VDD_DS_MASK) == - SPC_HP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) || + SPC_HP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) || ((base->HP_CFG & SPC_HP_CFG_DCDC_VDD_DS_MASK) == SPC_HP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength))) { return kStatus_SPC_BandgapModeWrong; } + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ if ((base->HP_CFG & SPC_HP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) { return kStatus_SPC_BandgapModeWrong; } - #if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS - if ((base->HP_CFG & SPC_HP_CFG_CORELDO_VDD_DS_MASK) == - SPC_HP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) - { - return kStatus_SPC_BandgapModeWrong; - } - #endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + if ((base->HP_CFG & SPC_HP_CFG_CORELDO_VDD_DS_MASK) == + SPC_HP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ } reg &= ~SPC_HP_CFG_BGMODE_MASK; @@ -1566,7 +1597,7 @@ status_t SPC_SetHighPowerModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_ /*! * brief Configure CORE LDO regulator in high power mode. - * + * * param base SPC peripheral base address. * param option Pointer to the CORE LDO regulator configuration, please refer to @ref spc_hp_mode_core_ldo_option_t. * @@ -1577,7 +1608,7 @@ status_t SPC_SetHighPowerModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_ * retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level in high power mode is not allowed. * retval #kStatus_Timeout Timeout occurs while waiting completion. */ -status_t SPC_SetHighPowerModeCoreLDORegulatorConfig(SPC_Type *base, spc_hp_mode_core_ldo_option_t *option) +status_t SPC_SetHighPowerModeCoreLDORegulatorConfig(SPC_Type *base, spc_hp_mode_core_ldo_option_t *option) { spc_core_ldo_voltage_level_t preVoltage; uint32_t state; @@ -1586,7 +1617,7 @@ status_t SPC_SetHighPowerModeCoreLDORegulatorConfig(SPC_Type *base, spc_hp_mode uint32_t timeout = SPC_BUSY_TIMEOUT; #endif -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY if ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1602,7 +1633,12 @@ status_t SPC_SetHighPowerModeCoreLDORegulatorConfig(SPC_Type *base, spc_hp_mode #if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS if (option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength) { - /* If any voltage detect feature is enabled in High power mode, then CORE_LDO's drive strength must not set to low. + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + /* If any voltage detect feature is enabled in High power mode, then CORE_LDO's drive strength must not set to + * low. */ state = SPC_GetHighPowerModeVoltageDetectStatus(base); if (state != 0UL) @@ -1619,14 +1655,14 @@ status_t SPC_SetHighPowerModeCoreLDORegulatorConfig(SPC_Type *base, spc_hp_mode base->HP_CFG &= ~SPC_HP_CFG_CORELDO_VDD_DS_MASK; } #endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ - base->HP_CFG = ((base->HP_CFG & ~SPC_HP_CFG_CORELDO_VDD_LVL_MASK) | - SPC_HP_CFG_CORELDO_VDD_LVL(option->CoreLDOVoltage)); + base->HP_CFG = + ((base->HP_CFG & ~SPC_HP_CFG_CORELDO_VDD_LVL_MASK) | SPC_HP_CFG_CORELDO_VDD_LVL(option->CoreLDOVoltage)); /* * $Branch Coverage Justification$ * $ref spc_c_ref_1$. */ -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY while ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1645,7 +1681,7 @@ status_t SPC_SetHighPowerModeCoreLDORegulatorConfig(SPC_Type *base, spc_hp_mode /*! * brief Configure System LDO regulator in high power mode. - * + * * param base SPC peripheral base address. * param option Pointer to the SYSTEM LDO regulator configuration, please refer to @ref spc_hp_mode_sys_ldo_option_t. * @@ -1666,7 +1702,7 @@ status_t SPC_SetHighPowerModeSystemLDORegulatorConfig(SPC_Type *base, spc_hp_mod uint32_t timeout = SPC_BUSY_TIMEOUT; #endif -#if (defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY) +#if (defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY) if ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1677,11 +1713,14 @@ status_t SPC_SetHighPowerModeSystemLDORegulatorConfig(SPC_Type *base, spc_hp_mod * $ref spc_c_ref_1$. */ return kStatus_SPC_Busy; - } if (option->SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) { + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ /* When select System LDO voltage level to Over Drive voltage, The HVD of System LDO must be disabled. */ if (((base->HP_CFG & SPC_HP_CFG_SYS_HVDE_MASK) != 0UL) && (option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage)) @@ -1708,8 +1747,7 @@ status_t SPC_SetHighPowerModeSystemLDORegulatorConfig(SPC_Type *base, spc_hp_mod reg = base->HP_CFG; reg &= ~(SPC_HP_CFG_SYSLDO_VDD_DS_MASK | SPC_HP_CFG_SYSLDO_VDD_LVL_MASK); - reg |= SPC_HP_CFG_SYSLDO_VDD_DS(option->SysLDODriveStrength) | - SPC_HP_CFG_SYSLDO_VDD_LVL(option->SysLDOVoltage); + reg |= SPC_HP_CFG_SYSLDO_VDD_DS(option->SysLDODriveStrength) | SPC_HP_CFG_SYSLDO_VDD_LVL(option->SysLDOVoltage); base->HP_CFG = reg; @@ -1717,7 +1755,7 @@ status_t SPC_SetHighPowerModeSystemLDORegulatorConfig(SPC_Type *base, spc_hp_mod * $Branch Coverage Justification$ * $ref spc_c_ref_1$. */ -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY while ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1736,7 +1774,7 @@ status_t SPC_SetHighPowerModeSystemLDORegulatorConfig(SPC_Type *base, spc_hp_mod /*! * brief Configure DCDC regulator in high power mode. - * + * * param base SPC peripheral base address. * param option Pointer to the DCDC regulator configuration, please refer to @ref spc_hp_mode_dcdc_option_t. * @@ -1756,7 +1794,7 @@ status_t SPC_SetHighPowerModeDCDCRegulatorConfig(SPC_Type *base, spc_hp_mode_dcd uint32_t timeout = SPC_BUSY_TIMEOUT; #endif -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY if ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1789,7 +1827,7 @@ status_t SPC_SetHighPowerModeDCDCRegulatorConfig(SPC_Type *base, spc_hp_mode_dcd * $Branch Coverage Justification$ * $ref spc_c_ref_1$. */ -#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY +#if defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY while ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL) #else while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) @@ -1808,7 +1846,7 @@ status_t SPC_SetHighPowerModeDCDCRegulatorConfig(SPC_Type *base, spc_hp_mode_dcd /*! * brief Set configuration of regulators in high power mode. - * + * * param base SPC peripheral base address. * param config Pointer to the regulator configuration, please refer to @ref spc_hp_mode_regulators_config_t. * @@ -1847,3 +1885,27 @@ status_t SPC_SetHighPowerModeRegulatorsConfig(SPC_Type *base, spc_hp_mode_regula } #endif /* (defined(FSL_FEATURE_SPC_HAS_HP_CFG_REG) && FSL_FEATURE_SPC_HAS_HP_CFG_REG) */ + +/*! + * brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * param base SPC peripheral base address. + * param config Pointer to the structure in type of spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = (base->VDD_CORE_GLITCH_DETECT_SC) & + ~(SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK); + + reg |= SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(config->rippleCounterSelect) | + SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(config->resetTimeoutValue) | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE(config->enableReset) | + SPC_VDD_CORE_GLITCH_DETECT_SC_IE(config->enableInterrupt); + + base->VDD_CORE_GLITCH_DETECT_SC = reg; +} diff --git a/mcux/mcux-sdk-ng/drivers/spc/fsl_spc.h b/mcux/mcux-sdk-ng/drivers/spc/fsl_spc.h index 3d7d18b53..ab31e4e04 100644 --- a/mcux/mcux-sdk-ng/drivers/spc/fsl_spc.h +++ b/mcux/mcux-sdk-ng/drivers/spc/fsl_spc.h @@ -27,8 +27,8 @@ /*! @name Driver version */ /*! @{ */ -/*! @brief SPC driver version 2.6.1. */ -#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 6, 1)) +/*! @brief SPC driver version 2.7.0. */ +#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) /*! @} */ /*! @name Configuration */ @@ -43,11 +43,11 @@ * If defined as 0, the driver will wait until completion. */ #ifndef SPC_BUSY_TIMEOUT - #ifdef CONFIG_SPC_BUSY_TIMEOUT - #define SPC_BUSY_TIMEOUT CONFIG_SPC_BUSY_TIMEOUT - #else - #define SPC_BUSY_TIMEOUT 0U - #endif +#ifdef CONFIG_SPC_BUSY_TIMEOUT +#define SPC_BUSY_TIMEOUT CONFIG_SPC_BUSY_TIMEOUT +#else +#define SPC_BUSY_TIMEOUT 0U +#endif #endif /*! @@ -58,11 +58,11 @@ * If defined as 0, the driver will wait until completion. */ #ifndef SPC_SRAM_ACK_TIMEOUT - #ifdef CONFIG_SPC_SRAM_ACK_TIMEOUT - #define SPC_SRAM_ACK_TIMEOUT CONFIG_SPC_SRAM_ACK_TIMEOUT - #else - #define SPC_SRAM_ACK_TIMEOUT 0U - #endif +#ifdef CONFIG_SPC_SRAM_ACK_TIMEOUT +#define SPC_SRAM_ACK_TIMEOUT CONFIG_SPC_SRAM_ACK_TIMEOUT +#else +#define SPC_SRAM_ACK_TIMEOUT 0U +#endif #endif /*! @@ -73,13 +73,27 @@ * If defined as 0, the driver will wait until it completes. */ #ifndef SPC_DCDC_ACK_TIMEOUT - #ifdef CONFIG_SPC_DCDC_ACK_TIMEOUT - #define SPC_DCDC_ACK_TIMEOUT CONFIG_SPC_DCDC_ACK_TIMEOUT - #else - #define SPC_DCDC_ACK_TIMEOUT 0U - #endif +#ifdef CONFIG_SPC_DCDC_ACK_TIMEOUT +#define SPC_DCDC_ACK_TIMEOUT CONFIG_SPC_DCDC_ACK_TIMEOUT +#else +#define SPC_DCDC_ACK_TIMEOUT 0U +#endif #endif +#if (defined(SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK)) +#define VDD_CORE_GLITCH_DETECT_SC GLITCH_DETECT_SC +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG +#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK SPC_GLITCH_DETECT_SC_LOCK_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT SPC_GLITCH_DETECT_SC_CNT_SELECT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK SPC_GLITCH_DETECT_SC_RE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE SPC_GLITCH_DETECT_SC_RE +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK SPC_GLITCH_DETECT_SC_TIMEOUT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT SPC_GLITCH_DETECT_SC_TIMEOUT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK SPC_GLITCH_DETECT_SC_IE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE SPC_GLITCH_DETECT_SC_IE +#endif /*! * @brief SPC status enumeration. @@ -193,11 +207,11 @@ typedef enum _spc_dcdc_voltage_level kSPC_DCDC_MidVoltage = 0x2U, /*!< DCDC VDD Regulator regulate to Mid Voltage. */ kSPC_DCDC_LowUnderVoltage = 0x3U, /*!< DCDC VDD Regulator regulate to Low Under Voltage. */ #else - kSPC_DCDC_LowUnderVoltage = 0x0U, /*!< DCDC VDD Regulator regulate to Low Under Voltage. */ - kSPC_DCDC_MidVoltage = 0x1U, /*!< DCDC VDD Regulator regulate to Mid Voltage. */ - kSPC_DCDC_NormalVoltage = 0x2U, /*!< DCDC VDD Regulator regulate to Normal Voltage. */ - kSPC_DCDC_SafeModeVoltage = 0x3U, /*!< DCDC VDD Regulator regulate to Safe-Mode Voltage. */ -#endif /* FSL_FEATURE_SPC_DCDC_VOLTAGE_LEVEL_DECREASE */ + kSPC_DCDC_LowUnderVoltage = 0x0U, /*!< DCDC VDD Regulator regulate to Low Under Voltage. */ + kSPC_DCDC_MidVoltage = 0x1U, /*!< DCDC VDD Regulator regulate to Mid Voltage. */ + kSPC_DCDC_NormalVoltage = 0x2U, /*!< DCDC VDD Regulator regulate to Normal Voltage. */ + kSPC_DCDC_SafeModeVoltage = 0x3U, /*!< DCDC VDD Regulator regulate to Safe-Mode Voltage. */ +#endif /* FSL_FEATURE_SPC_DCDC_VOLTAGE_LEVEL_DECREASE */ } spc_dcdc_voltage_level_t; /*! @@ -245,7 +259,7 @@ typedef enum _spc_core_ldo_voltage_level kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */ kSPC_CoreLDO_NormalVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */ kSPC_CoreLDO_SafeModeVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to Safe-Mode Voltages. */ -#endif /* FSL_FEATURE_SPC_LDO_VOLTAGE_LEVEL_DECREASE */ +#endif /* FSL_FEATURE_SPC_LDO_VOLTAGE_LEVEL_DECREASE */ } spc_core_ldo_voltage_level_t; /*! @@ -295,7 +309,7 @@ typedef struct _spc_intergrated_power_switch_config bool wakeup; /*!< Assert an output pin to un-gate the integrated power switch. */ bool sleep; /*!< Assert an output pin to power gate the intergrated power switch. */ } spc_intergrated_power_switch_config_t; -#endif /* FSL_FEATURE_SPC_HAS_CFG_REGISTER */ +#endif /* FSL_FEATURE_SPC_HAS_CFG_REGISTER */ /*! * @brief Core LDO regulator options in Active mode. @@ -316,7 +330,7 @@ typedef struct _spc_active_mode_sys_ldo_option { spc_sys_ldo_voltage_level_t SysLDOVoltage; /*!< System LDO Regulator Voltage Level selection in Active mode. */ spc_sys_ldo_drive_strength_t - SysLDODriveStrength; /*!< System LDO Regulator Drive Strength selection in Active mode. */ + SysLDODriveStrength; /*!< System LDO Regulator Drive Strength selection in Active mode. */ } spc_active_mode_sys_ldo_option_t; /*! @@ -335,7 +349,7 @@ typedef struct _spc_lowpower_mode_core_ldo_option { spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Low Power mode. */ spc_core_ldo_drive_strength_t - CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength selection in Low Power mode */ + CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength selection in Low Power mode */ } spc_lowpower_mode_core_ldo_option_t; /*! @@ -438,20 +452,48 @@ typedef struct _spc_lowpower_mode_regulators_config typedef enum _spc_hp_request_override_option { kSPC_HpRequestOverrideDisable = 0U, /*!< Disable high power request override feature. */ - kSPC_HpRequestOverride0 = 1U, /*!< Enable high power request override feature and force value as 0. */ - kSPC_HpReqestOverride1 = 3U, /*!< Enable high power request override feature and force value as 1. */ + kSPC_HpRequestOverride0 = 1U, /*!< Enable high power request override feature and force value as 0. */ + kSPC_HpReqestOverride1 = 3U, /*!< Enable high power request override feature and force value as 1. */ } spc_hp_override_request_option_t; -#define SPC_HP_CNFG_CTRL_OVERRIDE_OPT_MASK (0x6UL) +#define SPC_HP_CNFG_CTRL_OVERRIDE_OPT_MASK (0x6UL) #define SPC_HP_CNFG_CTRL_OVERRIDE_OPT_SHIFT (1UL) -#define SPC_HP_CNFG_CTRL_OVERRIDE_OPT(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CNFG_CTRL_OVERRIDE_OPT_SHIFT)) & SPC_HP_CNFG_CTRL_OVERRIDE_OPT_MASK) +#define SPC_HP_CNFG_CTRL_OVERRIDE_OPT(x) \ + (((uint32_t)(((uint32_t)(x)) << SPC_HP_CNFG_CTRL_OVERRIDE_OPT_SHIFT)) & SPC_HP_CNFG_CTRL_OVERRIDE_OPT_MASK) -typedef spc_active_mode_dcdc_option_t spc_hp_mode_dcdc_option_t; -typedef spc_active_mode_sys_ldo_option_t spc_hp_mode_sys_ldo_option_t; -typedef spc_active_mode_core_ldo_option_t spc_hp_mode_core_ldo_option_t; +typedef spc_active_mode_dcdc_option_t spc_hp_mode_dcdc_option_t; +typedef spc_active_mode_sys_ldo_option_t spc_hp_mode_sys_ldo_option_t; +typedef spc_active_mode_core_ldo_option_t spc_hp_mode_core_ldo_option_t; typedef spc_active_mode_regulators_config_t spc_hp_mode_regulators_config_t; #endif /* (defined(FSL_FEATURE_SPC_HAS_HP_CFG_REG) && FSL_FEATURE_SPC_HAS_HP_CFG_REG) */ +/*! + * @brief Used to select output of 4-bit ripple counter is used to monitor a glitch on VDD core. + */ +typedef enum _spc_vdd_core_glitch_ripple_counter_select +{ + kSPC_selectBit0Of4bitRippleCounter = 0x0U, /*!< Select bit-0 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit1Of4bitRippleCounter = 0x1U, /*!< Select bit-1 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit2Of4bitRippleCounter = 0x2U, /*!< Select bit-2 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit3Of4bitRippleCounter = 0x3U, /*!< Select bit-3 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ +} spc_vdd_core_glitch_ripple_counter_select_t; + +/*! + * @brief The configuration of VDD Core glitch detector. + */ +typedef struct _spc_vdd_core_glitch_detector_config +{ + spc_vdd_core_glitch_ripple_counter_select_t rippleCounterSelect; /*!< Used to set ripple counter. */ + uint8_t resetTimeoutValue; /*!< The timeout value used to reset glitch detect/compare logic after an initial + glitch is detected. */ + bool enableReset; /*!< Used to enable/disable POR/LVD reset that caused by CORE VDD glitch detect error. */ + bool enableInterrupt; /*!< Used to enable/disable hardware interrupt if CORE VDD glitch detect error. */ +} spc_vdd_core_glitch_detector_config_t; + /******************************************************************************* * API ******************************************************************************/ @@ -506,14 +548,14 @@ static inline void SPC_ClearPeriphIOIsolationFlag(SPC_Type *base) */ static inline bool SPC_GetBusyStatusFlag(SPC_Type *base) { -#if (defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY ) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY) +#if (defined(FSL_FEATURE_SPC_HAS_SC_REG_BUSY) && FSL_FEATURE_SPC_HAS_SC_REG_BUSY) return ((base->SC & SPC_SC_REG_BUSY_MASK) != 0UL); #else return ((base->SC & SPC_SC_BUSY_MASK) != 0UL); #endif } -#if !(defined(FSL_FEATURE_SPC_HAS_SC_SPC_LP_REQ_BIT) && (FSL_FEATURE_SPC_HAS_SC_SPC_LP_REQ_BIT==0U)) +#if !(defined(FSL_FEATURE_SPC_HAS_SC_SPC_LP_REQ_BIT) && (FSL_FEATURE_SPC_HAS_SC_SPC_LP_REQ_BIT == 0U)) /*! * @brief Checks system low power request. * @@ -693,11 +735,11 @@ static inline uint32_t SPC_GetWakeUpValue(SPC_Type *base) /*! * @brief Check if HP_CFG selected as active configuration register. - * + * * @param base SPC peripheral base address. - * + * * @retval false ACTIVE_CFG selected as the active configuration register. - * @retval true HP_CFG selected as the active configuration register. + * @retval true HP_CFG selected as the active configuration register. */ static inline bool SPC_CheckHPCfgSelected(SPC_Type *base) { @@ -706,7 +748,7 @@ static inline bool SPC_CheckHPCfgSelected(SPC_Type *base) /*! * @brief Enable/disable high power request feature. - * + * * @param base SPC peripheral base address. * @param enable Used to specify enable/disable the high power request feature: * - \b true Enable high power request; @@ -726,29 +768,31 @@ static inline void SPC_EnableHighPowerRequest(SPC_Type *base, bool enable) /*! * @brief Override high power request manually. - * + * * @param base SPC peripheral base address. * @param opt Specify the option of high power override request, please refer to @ref spc_hp_override_request_option_t. */ static inline void SPC_OverrideHighPowerRequest(SPC_Type *base, spc_hp_override_request_option_t opt) { - base->HP_CNFG_CTRL = ((base->HP_CNFG_CTRL) & (~SPC_HP_CNFG_CTRL_OVERRIDE_OPT_MASK)) | SPC_HP_CNFG_CTRL_OVERRIDE_OPT(opt); + base->HP_CNFG_CTRL = + ((base->HP_CNFG_CTRL) & (~SPC_HP_CNFG_CTRL_OVERRIDE_OPT_MASK)) | SPC_HP_CNFG_CTRL_OVERRIDE_OPT(opt); } /*! * @brief Get voltage level of CORE LDO in high power mode. - * + * * @param base SPC peripheral base address. * @return The voltage level of CORE LDO in high power mode, please refer to @ref spc_core_ldo_voltage_level_t. */ static inline spc_core_ldo_voltage_level_t SPC_GetHighPowerModeCoreLDOVDDVoltageLevel(SPC_Type *base) { - return (spc_core_ldo_voltage_level_t)(uint32_t)((base->HP_CFG & SPC_HP_CFG_CORELDO_VDD_LVL_MASK) >> SPC_HP_CFG_CORELDO_VDD_LVL_SHIFT); + return (spc_core_ldo_voltage_level_t)(uint32_t)((base->HP_CFG & SPC_HP_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_HP_CFG_CORELDO_VDD_LVL_SHIFT); } /*! * @brief Get bandgap mode in high power mode. - * + * * @param base SPC peripheral base address. * @return The bandgap mode in high power mode, please refer to @ref spc_bandgap_mode_t. */ @@ -759,7 +803,7 @@ static inline spc_bandgap_mode_t SPC_GetHighPowerModeBandgapMode(SPC_Type *base) /*! * @brief Get enabled state of all voltage detectors. - * + * * @param base SPC peripheral base address. * @return All enabled status of all voltage detectors, 1b1 means the corrsponding voltage detector is enabled. */ @@ -768,14 +812,14 @@ static inline uint32_t SPC_GetHighPowerModeVoltageDetectStatus(SPC_Type *base) uint32_t state; state = base->HP_CFG & (SPC_HP_CFG_CORE_LVDE_MASK | SPC_HP_CFG_SYS_LVDE_MASK | SPC_HP_CFG_IO_LVDE_MASK | - SPC_HP_CFG_CORE_HVDE_MASK | SPC_HP_CFG_SYS_HVDE_MASK | SPC_HP_CFG_IO_HVDE_MASK); + SPC_HP_CFG_CORE_HVDE_MASK | SPC_HP_CFG_SYS_HVDE_MASK | SPC_HP_CFG_IO_HVDE_MASK); return state; } /*! * @brief Set bandgap mode in high power mode. - * + * * @param base SPC peripheral base address. * @param mode Specify the bandgap mode in high power mode. * @@ -786,7 +830,7 @@ status_t SPC_SetHighPowerModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_ /*! * @brief Enable/disable CMP buffer in high power mode. - * + * * @param base SPC peripheral base address. * @param enable Used to enable/disable CMP buffer: * - \b true Enable CMP buffer in high power mode; @@ -806,7 +850,7 @@ static inline void SPC_EnableHighPowerModeCMPBandgapBuffer(SPC_Type *base, bool /*! * @brief Disable/enable VDD Core Glitch detect feature in high power mode. - * + * * @param base SPC peripheral base address. * @param disable Used to disable/enable VDD Core Glitch detect feature: * - \b true Disable VDD Core Glitch detect feature; @@ -826,7 +870,7 @@ static inline void SPC_DisableHighPowerModeVddCoreGlitchDetect(SPC_Type *base, b /*! * @brief Configure CORE LDO regulator in high power mode. - * + * * @param base SPC peripheral base address. * @param option Pointer to the CORE LDO regulator configuration, please refer to @ref spc_hp_mode_core_ldo_option_t. * @@ -837,11 +881,11 @@ static inline void SPC_DisableHighPowerModeVddCoreGlitchDetect(SPC_Type *base, b * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level in high power mode is not allowed. * @retval #kStatus_Timeout Timeout occurs while waiting completion. */ -status_t SPC_SetHighPowerModeCoreLDORegulatorConfig(SPC_Type *base, spc_hp_mode_core_ldo_option_t *option); +status_t SPC_SetHighPowerModeCoreLDORegulatorConfig(SPC_Type *base, spc_hp_mode_core_ldo_option_t *option); /*! * @brief Configure System LDO regulator in high power mode. - * + * * @param base SPC peripheral base address. * @param option Pointer to the SYSTEM LDO regulator configuration, please refer to @ref spc_hp_mode_sys_ldo_option_t. * @@ -855,7 +899,7 @@ status_t SPC_SetHighPowerModeSystemLDORegulatorConfig(SPC_Type *base, spc_hp_mod /*! * @brief Configure DCDC regulator in high power mode. - * + * * @param base SPC peripheral base address. * @param option Pointer to the DCDC regulator configuration, please refer to @ref spc_hp_mode_dcdc_option_t. * @@ -868,7 +912,7 @@ status_t SPC_SetHighPowerModeDCDCRegulatorConfig(SPC_Type *base, spc_hp_mode_dcd /*! * @brief Set configuration of regulators in high power mode. - * + * * @param base SPC peripheral base address. * @param config Pointer to the regulator configuration, please refer to @ref spc_hp_mode_regulators_config_t. * @@ -884,7 +928,7 @@ status_t SPC_SetHighPowerModeRegulatorsConfig(SPC_Type *base, spc_hp_mode_regula /*! * @brief Enable/disable low voltage detect for VDD_CORE in high power mode. - * + * * @param base SPC peripheral base address. * @param enable Used to enable/disable low voltage detect feature for VDD_CORE in high power mode: * - \b true Enable low voltage detect feature for VDD_CORE in high power mode; @@ -904,7 +948,7 @@ static inline void SPC_EnableHighPowerModeCoreLowVoltageDetect(SPC_Type *base, b /*! * @brief Enable/disable high voltage detect for VDD_CORE in high power mode. - * + * * @param base SPC peripheral base address. * @param enable Used to enable/disable high voltage detect feature for VDD_CORE in high power mode: * - \b true Enable low voltage detect feature for VDD_CORE in high power mode; @@ -924,7 +968,7 @@ static inline void SPC_EnableHighPowerModeCoreHighVoltageDetect(SPC_Type *base, /*! * @brief Enable/disable low voltage detect for VDD_SYS in high power mode. - * + * * @param base SPC peripheral base address. * @param enable Used to enable/disable low voltage detect feature for VDD_SYS in high power mode: * - \b true Enable low voltage detect feature for VDD_SYS in high power mode; @@ -944,7 +988,7 @@ static inline void SPC_EnableHighPowerModeSystemLowVoltageDetect(SPC_Type *base, /*! * @brief Enable/disable high voltage detect for VDD_SYS in high power mode. - * + * * @param base SPC peripheral base address. * @param enable Used to enable/disable high voltage detect feature for VDD_SYS in high power mode: * - \b true Enable high voltage detect feature for VDD_SYS in high power mode; @@ -964,7 +1008,7 @@ static inline void SPC_EnableHighPowerModeSystemHighVoltageDetect(SPC_Type *base /*! * @brief Enable/disable low voltage detect for VDD_IO_ABC in high power mode. - * + * * @param base SPC peripheral base address. * @param enable Used to enable/disable low voltage detect feature for VDD_IO_ABC in high power mode: * - \b true Enable low voltage detect feature for VDD_IO_ABC in high power mode; @@ -984,7 +1028,7 @@ static inline void SPC_EnableHighPowerModeIOLowVoltageDetect(SPC_Type *base, boo /*! * @brief Enable/disable high voltage detect for VDD_IO_ABC in high power mode. - * + * * @param base SPC peripheral base address. * @param enable Used to enable/disable high voltage detect feature for VDD_IO_ABC in high power mode: * - \b true Enable high voltage detect feature for VDD_IO_ABC in high power mode; @@ -1066,7 +1110,7 @@ void SPC_SetActiveModeIntegratedPowerSwitchConfig(SPC_Type *base, const spc_inte /*! * @brief Configs Bandgap mode in Active mode. * - * @note In active mode, beacause CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to + * @note In active mode, because CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to * disable Bandgap in active mode * * @param base SPC peripheral base address. @@ -1536,7 +1580,7 @@ status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable) * must be done after disabling the System VDD low voltage reset and interrupt. * * @deprecated In latest RM, reserved for all devices, will removed in next release. - * + * * @param base SPC peripheral base address. * @param level System VDD Low-Voltage level selection. */ @@ -2095,6 +2139,84 @@ status_t SPC_SetSRAMOperateVoltage(SPC_Type *base, spc_sram_operat_voltage_t vol /*! @} */ +/*! + * @name VDD Core Glitch Detector Control APIs + * @{ + */ + +/*! + * @brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * @param base SPC peripheral base address. + * @param config Pointer to the structure in type of @ref spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config); + +/*! + * @brief Checks selected 4-bit glitch ripple counter's output. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + * + * @retval true The selected ripple counter output is 1, will generate interrupt or reset based on settings. + * @retval false The selected ripple counter output is 0. + */ + +static inline bool SPC_CheckGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) == + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter))); +} + +/*! + * @brief Clears output of selected glitch ripple counter. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + */ +static inline void SPC_ClearGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter)); +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are allowed. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC &= ~SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief Checks if SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * + * @param base SPC peripheral base address. + * + * @retval true SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * @retval false SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is not writable. + */ +static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) != 0UL); +} + +/*! @} */ + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/mcux/mcux-sdk-ng/drivers/sramc/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/sramc/CMakeLists.txt new file mode 100644 index 000000000..e5c922407 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/sramc/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +if(CONFIG_MCUX_COMPONENT_driver.sramc) + mcux_component_version(2.0.0) + + mcux_add_source(SOURCES fsl_sramc.c fsl_sramc.h) + + mcux_add_include(INCLUDES .) + +endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.c b/mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.c new file mode 100644 index 000000000..019057915 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.c @@ -0,0 +1,184 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sramc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sramc" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets the default configuration for the SRAMC. + * + * This function initializes the sramc_config_t structure with default values. + * The default value are: + * code + * config->turnaroundTime = 1U; + * config->addressHoldTime = 1U; + * config->addressSetupTime = 4U; + * config->ceHoldTime = 1U; + * config->ceSetupTime = 1U; + * config->advPolarity = kSRAMC_AdvActiveLow; + * config->addressMode = kSRAMC_AddressDataNonMux; + * config->portSize = kSRAMC_PortSize16Bit; + * config->busTimeoutEnable = false; + * config->busTimeoutCounter = 0U; + * config->prescaler = kSRAMC_Prescaler_4; + * config->readEnableHighTime = 9U; + * config->readEnableLowTime = 0X10U; + * config->writeEnableHighTime = 0xAU; + * config->writeEnableLowTime = 0x1FU; + * endcode + * + * param config Pointer to the sramc_config_t structure to be initialized. + */ +void SRAMC_GetDefaultConfig(sramc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + assert(config != NULL); + + config->turnaroundTime = 1U; + config->addressHoldTime = 1U; + config->addressSetupTime = 4U; + config->ceHoldTime = 1U; + config->ceSetupTime = 1U; + config->advPolarity = kSRAMC_AdvActiveLow; + config->addressMode = kSRAMC_AddressDataMux; + config->portSize = kSRAMC_PortSize16Bit; + config->busTimeoutEnable = false; + config->busTimeoutCounter = 0U; + config->prescaler = kSRAMC_Prescaler_4; + config->readEnableHighTime = 9U; + config->readEnableLowTime = 0x10U; + config->writeEnableHighTime = 0xAU; + config->writeEnableLowTime = 0X1FU; + +} + +/*! + * brief Initializes the SRAMC peripheral. + * + * This function configures the SRAMC controller based on the provided configuration. + * + * param base Pointer to the WAKEUP Domain Block Control module instance structure. + * param config Pointer to the SRAMC configuration structure (sramc_config_t). + */ +void SRAMC_Init(BLK_CTRL_WAKEUPMIX_Type *base, const sramc_config_t *config) +{ + assert(base != NULL); + assert(config != NULL); + + uint32_t sramcr0 = 0U; + uint32_t sramcr1 = 0U; + + /* Configure SRAMCR0 register */ + sramcr0 |= BLK_CTRL_WAKEUPMIX_SRAMCR0_TA(config->turnaroundTime); + sramcr0 |= BLK_CTRL_WAKEUPMIX_SRAMCR0_AH(config->addressHoldTime); + sramcr0 |= BLK_CTRL_WAKEUPMIX_SRAMCR0_AS(config->addressSetupTime); + sramcr0 |= BLK_CTRL_WAKEUPMIX_SRAMCR0_CEH(config->ceHoldTime); + sramcr0 |= BLK_CTRL_WAKEUPMIX_SRAMCR0_CES(config->ceSetupTime); + sramcr0 |= BLK_CTRL_WAKEUPMIX_SRAMCR0_ADVP(config->advPolarity); + sramcr0 |= BLK_CTRL_WAKEUPMIX_SRAMCR0_AM(config->addressMode); + sramcr0 |= BLK_CTRL_WAKEUPMIX_SRAMCR0_PS(config->portSize); + sramcr0 |= config->busTimeoutEnable ? BLK_CTRL_WAKEUPMIX_SRAMCR0_BTOEN(1U) : 0U; + sramcr0 |= BLK_CTRL_WAKEUPMIX_SRAMCR0_BTO(config->busTimeoutCounter); + + /* Configure SRAMCR1 register */ + sramcr1 |= BLK_CTRL_WAKEUPMIX_SRAMCR1_PRE(config->prescaler); + sramcr1 |= BLK_CTRL_WAKEUPMIX_SRAMCR1_REH(config->readEnableHighTime); + sramcr1 |= BLK_CTRL_WAKEUPMIX_SRAMCR1_REL(config->readEnableLowTime); + sramcr1 |= BLK_CTRL_WAKEUPMIX_SRAMCR1_WEH(config->writeEnableHighTime); + sramcr1 |= BLK_CTRL_WAKEUPMIX_SRAMCR1_WEL(config->writeEnableLowTime); + + /* Write to registers */ + base->SRAMCR0 = sramcr0; + base->SRAMCR1 = sramcr1; +} + +/*! + * brief De-initializes the SRAMC peripheral. + * + * This function resets the SRAMC configuration registers to their reset values. + * + * param base Pointer to the WAKEUP Domain Block Control module instance structure. + */ +void SRAMC_Deinit(BLK_CTRL_WAKEUPMIX_Type *base) +{ + assert(base != NULL); + + /* Reset SRAMCR0 and SRAMCR1 registers */ + base->SRAMCR0 = 0U; /* Default value after reset */ + base->SRAMCR1 = 0U; /* Default value after reset */ +} + +/*! + * brief Calculates the SRAMC register timing field value from nanoseconds. + * + * This helper function converts a time duration specified in nanoseconds (`time_ns`) into the corresponding register + * field value based on the SRAMC functional clock frequency (`hclkFreqHz`) and the selected prescaler + * (`prescalerValue`, corresponding to SRAMCR1[PRE] setting 0-3). It accounts for the '+1' logic required by some timing + * fields (e.g., REL, REH, WEL, WEH, AH, TA) as specified in the reference manual. It also checks if the calculated + * value fits within the specified bit-width of the target register field. + * + * param hclkFreqHz Frequency of the hclk clock source for SRAMC in Hz. + * param time_ns Desired time duration in nanoseconds. + * param prescalerValue The value written to the SRAMCR1[PRE] field (0=1 cycle, 1=2 cycles, 2=3 cycles, 3=4 cycles granularity). + * param addOneCycle Set to `true` if the register field represents (N+1) * granularity (e.g., for REL, REH, etc.), `false` otherwise (e.g., for CES, CEH). + * param fieldWidth The number of bits available for the target register field (e.g., 6 for WEL, 4 for CEH). + * param result Pointer to store the calculated register field. + * value. + * + * @return + * - `kStatus_Success`: Calculation successful. + * - `kStatus_InvalidArgument`: If `hclkFreqHz` is 0, or if the calculated value exceeds the capacity of the + * `fieldWidth`. + */ +status_t SRAMC_CalculateTimingValue(uint32_t hclkFreqHz, + uint32_t time_ns, + uint32_t prescalerValue, + bool addOneCycle, + uint8_t fieldWidth, + uint32_t *result) +{ + assert(result != NULL); + + if (hclkFreqHz == 0U) + { + return kStatus_InvalidArgument; + } + + uint32_t cycleTime_ns = 1000000000U / hclkFreqHz; /* Clock cycle time in nanoseconds */ + assert(cycleTime_ns > 0U); + assert(prescalerValue < UINT32_MAX -1U); + assert(prescalerValue + 1U < UINT32_MAX / cycleTime_ns); + uint32_t granularity = (prescalerValue + 1U) * cycleTime_ns; /* Time granularity in nanoseconds */ + uint32_t calculatedValue; + + /* Add one clock cycle if required */ + assert(time_ns < UINT32_MAX - granularity); + if (addOneCycle) + { + calculatedValue = (time_ns + granularity - 1U) / granularity - 1U; + } + else + { + calculatedValue = (time_ns + granularity - 1U) / granularity; + } + + /* Check if the calculated value exceeds the field width */ + if (calculatedValue >= (1UL << fieldWidth)) + { + return kStatus_InvalidArgument; + } + + *result = calculatedValue; + return kStatus_Success; +} \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.h b/mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.h new file mode 100644 index 000000000..d41990229 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/sramc/fsl_sramc.h @@ -0,0 +1,194 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_SRAMC_H_ +#define FSL_SRAMC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sramc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief Defines SRAMC driver version. */ +#define FSL_SRAMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @} */ + +/*! + * @brief SRAMC address mode. + */ +typedef enum _sramc_address_mode +{ + kSRAMC_AddressDataMux = 0U, /*!< Address/Data MUX mode (ADMUX) */ + kSRAMC_AddressDataNonMux = 1U /*!< Address/Data non-MUX mode (Non-ADMUX) */ +} sramc_address_mode_t; + +/*! + * @brief SRAMC port size. + */ +typedef enum _sramc_port_size +{ + kSRAMC_PortSize8Bit = 0U, /*!< 8-bit data port size */ + kSRAMC_PortSize16Bit = 1U /*!< 16-bit data port size */ +} sramc_port_size_t; + +/*! + * @brief SRAMC ADV# polarity. + */ +typedef enum _sramc_adv_polarity +{ + kSRAMC_AdvActiveLow = 0U, /*!< ADV# signal is active low */ + kSRAMC_AdvActiveHigh = 1U /*!< ADV# signal is active high */ +} sramc_adv_polarity_t; + +/*! + * @brief SRAMC prescaler. + */ +typedef enum _sramc_prescaler +{ + kSRAMC_Prescaler_1 = 0U, /*!< Time granularity is 1 hclk cycle */ + kSRAMC_Prescaler_2 = 1U, /*!< Time granularity is 2 hclk cycles */ + kSRAMC_Prescaler_3 = 2U, /*!< Time granularity is 3 hclk cycles */ + kSRAMC_Prescaler_4 = 3U /*!< Time granularity is 4 hclk cycles */ +} sramc_prescaler_t; + +/*! + * @brief SRAMC configuration structure. + */ +typedef struct _sramc_config +{ + /* SRAMCR0 Fields */ + uint8_t turnaroundTime; /*!< Turnaround time (TA). Actual time is (TA+1) * granularity. Range: 0-15. */ + uint8_t addressHoldTime; /*!< Address hold time (AH). Actual time is (AH+1) * granularity. Range: 0-15. */ + uint8_t addressSetupTime; /*!< Address setup time (AS). Actual time is AS * granularity (min 1 cycle in ADMUX). Range: 0-15. */ + uint8_t ceHoldTime; /*!< Chip Enable hold time (CEH). Actual time is CEH * granularity. Range: 0-15. */ + uint8_t ceSetupTime; /*!< Chip Enable setup time (CES). Actual time is CES * granularity. Range: 0-15. */ + sramc_adv_polarity_t advPolarity; /*!< ADV# polarity (ADVP). */ + sramc_address_mode_t addressMode; /*!< Address mode (AM). ADMUX or Non-ADMUX. */ + sramc_port_size_t portSize; /*!< Port Size (PS). 8-bit or 16-bit. */ + bool busTimeoutEnable; /*!< AHB Bus Timeout Enable (BTOEN). */ + uint8_t busTimeoutCounter; /*!< AHB Bus Timeout Wait Cycle (BTO). Timeout = BTO * 1024 hclk cycles. Range: 0-255. */ + + /* SRAMCR1 Fields */ + sramc_prescaler_t prescaler; /*!< Prescaler timer (PRE). Sets time granularity for timing parameters. */ + uint8_t readEnableHighTime; /*!< Read Enable high time (REH). Actual time is (REH+1) * granularity. Range: 0-15. */ + uint8_t readEnableLowTime; /*!< Read Enable low time (REL). Actual time is (REL+1) * granularity. Range: 0-63. */ + uint8_t writeEnableHighTime; /*!< Write Enable high time (WEH). Actual time is (WEH+1) * granularity. Range: 0-15. */ + uint8_t writeEnableLowTime; /*!< Write Enable low time (WEL). Actual time is (WEL+1) * granularity. Range: 0-63. */ + +} sramc_config_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Gets the default configuration for the SRAMC. + * + * This function initializes the sramc_config_t structure with default values. + * The default value are: + * @code + * config->turnaroundTime = 1U; + * config->addressHoldTime = 1U; + * config->addressSetupTime = 4U; + * config->ceHoldTime = 1U; + * config->ceSetupTime = 1U; + * config->advPolarity = kSRAMC_AdvActiveLow; + * config->addressMode = kSRAMC_AddressDataNonMux; + * config->portSize = kSRAMC_PortSize16Bit; + * config->busTimeoutEnable = false; + * config->busTimeoutCounter = 0U; + * config->prescaler = kSRAMC_Prescaler_4; + * config->readEnableHighTime = 9U; + * config->readEnableLowTime = 0X10U; + * config->writeEnableHighTime = 0xAU; + * config->writeEnableLowTime = 0x1FU; + * @endcode + * + * @param config Pointer to the sramc_config_t structure to be initialized. + */ +void SRAMC_GetDefaultConfig(sramc_config_t *config); + +/*! + * @brief Initializes the SRAMC peripheral. + * + * This function configures the SRAMC controller based on the provided configuration. + * + * @param base Pointer to the WAKEUP Domain Block Control module instance structure. + * @param config Pointer to the SRAMC configuration structure (sramc_config_t). + */ +void SRAMC_Init(BLK_CTRL_WAKEUPMIX_Type *base, const sramc_config_t *config); + +/*! + * @brief De-initializes the SRAMC peripheral. + * + * This function resets the SRAMC configuration registers to their reset values. + * + * @param base Pointer to the WAKEUP Domain Block Control module instance structure. + */ +void SRAMC_Deinit(BLK_CTRL_WAKEUPMIX_Type *base); + +/*! @}*/ + +/*! +* @name SRAMC timing paramters calculation +* @{ +*/ + +/*! + * @brief Calculates the SRAMC register timing field value from nanoseconds. + * + * This helper function converts a time duration specified in nanoseconds (`time_ns`) into the corresponding register + * field value based on the SRAMC functional clock frequency (`hclkFreqHz`) and the selected prescaler + * (`prescalerValue`, corresponding to SRAMCR1[PRE] setting 0-3). It accounts for the '+1' logic required by some timing + * fields (e.g., REL, REH, WEL, WEH, AH, TA) as specified in the reference manual. It also checks if the calculated + * value fits within the specified bit-width of the target register field. + * + * @param hclkFreqHz Frequency of the hclk clock source for SRAMC in Hz. + * @param time_ns Desired time duration in nanoseconds. + * @param prescalerValue The value written to the SRAMCR1[PRE] field (0=1 cycle, 1=2 cycles, 2=3 cycles, 3=4 cycles + * granularity). + * @param addOneCycle Set to `true` if the register field represents (N+1) * granularity (e.g., for REL, REH, etc.), + * `false` otherwise (e.g., for CES, CEH). + * @param fieldWidth The number of bits available for the target register field (e.g., 6 for WEL, 4 for CEH). + * @param result Pointer to store the calculated register field value. + * + * @return + * - `kStatus_Success`: Calculation successful. + * - `kStatus_InvalidArgument`: If `hclkFreqHz` is 0, or if the calculated value exceeds the capacity of the + * `fieldWidth`. + */ +status_t SRAMC_CalculateTimingValue(uint32_t hclkFreqHz, + uint32_t time_ns, + uint32_t prescalerValue, + bool addOneCycle, + uint8_t fieldWidth, + uint32_t *result); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_SRAMC_H_ */ \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/stm/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/stm/CMakeLists.txt index 954fa2b9d..e6c94b7d3 100644 --- a/mcux/mcux-sdk-ng/drivers/stm/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/stm/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.stm) - mcux_component_version(2.0.0) + mcux_component_version(2.0.1) mcux_add_source( SOURCES fsl_stm.c fsl_stm.h ) mcux_add_include( INCLUDES . ) endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/stm/fsl_stm.c b/mcux/mcux-sdk-ng/drivers/stm/fsl_stm.c index e3a55c104..8b0cf3d30 100644 --- a/mcux/mcux-sdk-ng/drivers/stm/fsl_stm.c +++ b/mcux/mcux-sdk-ng/drivers/stm/fsl_stm.c @@ -180,7 +180,7 @@ void STM_DriverIRQHandler(uint32_t index) uint32_t int_stat = 0U; uint32_t i; - if (index > ARRAY_SIZE(s_stmBases)) + if (index >= ARRAY_SIZE(s_stmBases)) { return; } diff --git a/mcux/mcux-sdk-ng/drivers/stm/fsl_stm.h b/mcux/mcux-sdk-ng/drivers/stm/fsl_stm.h index 8262978b5..cbaa828a9 100644 --- a/mcux/mcux-sdk-ng/drivers/stm/fsl_stm.h +++ b/mcux/mcux-sdk-ng/drivers/stm/fsl_stm.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief Defines STM driver version. */ -#define FSL_STM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_STM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*! @} */ /*! @brief List of STM channels */ diff --git a/mcux/mcux-sdk-ng/drivers/tpm/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/tpm/CMakeLists.txt index 7a614aebd..541f7be01 100644 --- a/mcux/mcux-sdk-ng/drivers/tpm/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/tpm/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.tpm) - mcux_component_version(2.3.5) + mcux_component_version(2.4.1) mcux_add_source(SOURCES fsl_tpm.c fsl_tpm.h) diff --git a/mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.c b/mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.c index 6bd91d1ab..aeb037d77 100644 --- a/mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.c +++ b/mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.c @@ -27,6 +27,10 @@ * * $Justification tpm_c_ref_5$ * Hardware limitations make this code impossible to implement. + * + * $Justification tpm_c_ref_6$ + * Following TPM IRQ handle functions are invoked in specific platform startup file or specific core. + * It is hard to update startup file for unit test, so add Justification. */ /******************************************************************************* @@ -290,8 +294,9 @@ tpm_clock_prescale_t TPM_CalculateCounterClkDiv(TPM_Type *base, uint32_t counter * param mode PWM operation mode, options available in enumeration ::tpm_pwm_mode_t * param chnlParams A structure for configuring PWM channel parameters, used to configure the channel. * - * return kStatus_Success if the PWM setup was successful, - * kStatus_Error on failure + * return kStatus_Success PWM setup successful + * kStatus_Error PWM setup failed + * kStatus_Timeout PWM setup timeout when write register CnV */ static status_t TPM_SetupSinglePwmChannel(TPM_Type *base, uint32_t mod, @@ -302,6 +307,9 @@ static status_t TPM_SetupSinglePwmChannel(TPM_Type *base, uint32_t counterMax = TPM_MAX_COUNTER_VALUE(base); uint8_t controlBits; uint8_t chnlId; +#if TPM_TIMEOUT + uint32_t timeout = TPM_TIMEOUT; +#endif /* MSnB:MSnA field value always be 10, ELSnB:ELSnA field value should config according to the channel params */ #if defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT @@ -397,13 +405,19 @@ static status_t TPM_SetupSinglePwmChannel(TPM_Type *base, base->FILTER = filterVal; /* When switching mode, disable channel n first */ - TPM_DisableChannel(base, (tpm_chnl_t)chnlId); + (void)TPM_DisableChannel(base, (tpm_chnl_t)chnlId); /* Set the requested PWM mode for channel n, under combine PWM mode, the active level is opposite of * edge-aligned mode */ - TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits ^ TPM_CnSC_ELSA_MASK); + (void)TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits ^ TPM_CnSC_ELSA_MASK); /* Set the channel n value */ do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif base->CONTROLS[chnlId].CnV = cnvFirstEdge; /* * $Branch Coverage Justification$ @@ -411,9 +425,12 @@ static status_t TPM_SetupSinglePwmChannel(TPM_Type *base, */ } while (cnvFirstEdge != base->CONTROLS[chnlId].CnV); +#if TPM_TIMEOUT + timeout = TPM_TIMEOUT; +#endif chnlId += 1U; /* When switching mode, disable channel n + 1 */ - TPM_DisableChannel(base, (tpm_chnl_t)chnlId); + (void)TPM_DisableChannel(base, (tpm_chnl_t)chnlId); #if defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT /* Select the pause level for second channel */ controlBits = (uint8_t)((uint32_t)kTPM_ChnlMSBMask | TPM_CnSC_ELSB(chnlParams.secPauseLevel) | @@ -423,17 +440,23 @@ static status_t TPM_SetupSinglePwmChannel(TPM_Type *base, if (chnlParams.enableComplementary) { /* Change the polarity on the second channel get complementary PWM signals */ - TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits); + (void)TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits); } else { /* Second channel use same control bits as first channel */ - TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits ^ TPM_CnSC_ELSA_MASK); + (void)TPM_EnableChannel(base, (tpm_chnl_t)chnlId, controlBits ^ TPM_CnSC_ELSA_MASK); } /* Set the channel n+1 value */ do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif base->CONTROLS[chnlId].CnV = cnvFirstEdge + cnv; /* * $Branch Coverage Justification$ @@ -473,6 +496,12 @@ static status_t TPM_SetupSinglePwmChannel(TPM_Type *base, */ do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif base->CONTROLS[chnlId].CnV = cnv; /* * $Branch Coverage Justification$ @@ -499,8 +528,9 @@ static status_t TPM_SetupSinglePwmChannel(TPM_Type *base, * param pwmFreq_Hz PWM signal frequency in Hz * param srcClock_Hz TPM counter clock in Hz * - * return kStatus_Success if the PWM setup was successful, - * kStatus_Error on failure + * return kStatus_Success PWM setup successful + * kStatus_Error PWM setup failed + * kStatus_Timeout PWM setup timeout when write register CnV or MOD */ status_t TPM_SetupPwm(TPM_Type *base, const tpm_chnl_pwm_signal_param_t *chnlParams, @@ -515,6 +545,9 @@ status_t TPM_SetupPwm(TPM_Type *base, uint32_t counterMax = TPM_MAX_COUNTER_VALUE(base); uint32_t tpmClock = (srcClock_Hz / (1UL << (base->SC & TPM_SC_PS_MASK))); status_t status = kStatus_Success; +#if TPM_TIMEOUT + uint32_t timeout = TPM_TIMEOUT; +#endif if ((0U == pwmFreq_Hz) || (0U == srcClock_Hz) || (0U == numOfChnls) || (tpmClock < pwmFreq_Hz)) { @@ -577,6 +610,12 @@ status_t TPM_SetupPwm(TPM_Type *base, do { base->MOD = mod; +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif /* * $Branch Coverage Justification$ * (mod != base->MOD) not covered. $ref tpm_c_ref_5$. @@ -617,8 +656,9 @@ status_t TPM_SetupPwm(TPM_Type *base, * param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 * 0=inactive signal(0% duty cycle)... * 100=active signal (100% duty cycle) - * return kStatus_Success if the PWM setup was successful, - * kStatus_Error on failure + * return kStatus_Success PWM setup successful + * kStatus_Error PWM setup failed + * kStatus_Timeout PWM setup timeout when write register CnV */ status_t TPM_UpdatePwmDutycycle(TPM_Type *base, tpm_chnl_t chnlNumber, @@ -628,6 +668,9 @@ status_t TPM_UpdatePwmDutycycle(TPM_Type *base, uint32_t cnv, mod; uint32_t counterMax = TPM_MAX_COUNTER_VALUE(base); uint8_t chnlId = (uint8_t)chnlNumber; +#if TPM_TIMEOUT + uint32_t timeout = TPM_TIMEOUT; +#endif /* Return error if requested chnlNumber is greater than the max allowed */ /* Return error if requested dutycycle/chnlNumber is greater than the max allowed */ @@ -695,14 +738,29 @@ status_t TPM_UpdatePwmDutycycle(TPM_Type *base, do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif base->CONTROLS[chnlId * 2U].CnV = cnvFirstEdge; /* * $Branch Coverage Justification$ * (cnvFirstEdge != base->CONTROLS[chnlId * 2U].CnV) not covered. $ref tpm_c_ref_1$. */ } while (cnvFirstEdge != base->CONTROLS[chnlId * 2U].CnV); +#if TPM_TIMEOUT + timeout = TPM_TIMEOUT; +#endif do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif base->CONTROLS[(chnlId * 2U) + 1U].CnV = cnvFirstEdge + cnv; } while ((cnvFirstEdge + cnv) != base->CONTROLS[(chnlId * 2U) + 1U].CnV); } @@ -725,6 +783,12 @@ status_t TPM_UpdatePwmDutycycle(TPM_Type *base, do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif base->CONTROLS[chnlId].CnV = cnv; /* * $Branch Coverage Justification$ @@ -758,14 +822,14 @@ void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_ uint8_t control = TPM_GetChannelContorlBits(base, chnlNumber); /* When switching mode, disable channel first */ - TPM_DisableChannel(base, chnlNumber); + (void)TPM_DisableChannel(base, chnlNumber); /* Clear the field and write the new level value */ control &= ~(uint8_t)(TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); control |= ((uint8_t)level << TPM_CnSC_ELSA_SHIFT) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); /* Enable channle with new level value */ - TPM_EnableChannel(base, chnlNumber, control); + (void)TPM_EnableChannel(base, chnlNumber, control); } /*! @@ -806,9 +870,9 @@ void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capt /*Clear CPWMS bit when the input capture mode is selected */ base->SC &= ~TPM_SC_CPWMS_MASK; /* When switching mode, disable channel first */ - TPM_DisableChannel(base, chnlNumber); + (void)TPM_DisableChannel(base, chnlNumber); /* Enable channel with new requested input capture mode */ - TPM_EnableChannel(base, chnlNumber, (uint8_t)captureMode); + (void)TPM_EnableChannel(base, chnlNumber, (uint8_t)captureMode); } /*! @@ -821,14 +885,19 @@ void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capt * param chnlNumber The channel number * param compareMode Action to take on the channel output when the compare condition is met * param compareValue Value to be programmed in the CnV register. + * return kStatus_Success PWM setup successful + * kStatus_Timeout PWM setup timeout when write register CnV */ -void TPM_SetupOutputCompare(TPM_Type *base, +status_t TPM_SetupOutputCompare(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_output_compare_mode_t compareMode, uint32_t compareValue) { assert(((uint8_t)chnlNumber < (uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base)) && (-1 != (int8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base))); +#if TPM_TIMEOUT + uint32_t timeout = TPM_TIMEOUT; +#endif #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL /* The TPM's QDCTRL register required to be effective */ @@ -845,19 +914,27 @@ void TPM_SetupOutputCompare(TPM_Type *base, /*Clear CPWMS bit when the output compare mode is selected */ base->SC &= ~TPM_SC_CPWMS_MASK; /* When switching mode, disable channel first */ - TPM_DisableChannel(base, chnlNumber); + (void)TPM_DisableChannel(base, chnlNumber); /* Enable channel with new requested compare mode */ - TPM_EnableChannel(base, chnlNumber, (uint8_t)compareMode); + (void)TPM_EnableChannel(base, chnlNumber, (uint8_t)compareMode); /* Setup the compare value */ do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif base->CONTROLS[chnlNumber].CnV = compareValue; /* * $Branch Coverage Justification$ * (compareValue != base->CONTROLS[chnlNumber].CnV) not covered. $ref tpm_c_ref_1$. */ } while (compareValue != base->CONTROLS[chnlNumber].CnV); + + return kStatus_Success; } #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE @@ -878,13 +955,14 @@ void TPM_SetupDualEdgeCapture(TPM_Type *base, uint32_t filterValue) { assert(NULL != edgeParam); - assert(((uint8_t)chnlPairNumber < (uint8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2U) && + assert(((int32_t)chnlPairNumber < (int32_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2) && (-1 != (int8_t)FSL_FEATURE_TPM_CHANNEL_COUNTn(base))); assert(1U == (uint8_t)FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); uint32_t reg; uint32_t u32flag; uint8_t chnlId = (uint8_t)chnlPairNumber * 2U; + uint8_t chnlIdSecond = (uint8_t)chnlPairNumber * 2U + 1U; #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL /* The TPM's QDCTRL register required to be effective */ @@ -899,10 +977,8 @@ void TPM_SetupDualEdgeCapture(TPM_Type *base, #endif /* When switching mode, disable channel first */ - TPM_DisableChannel(base, (tpm_chnl_t)chnlId); - chnlId++; - TPM_DisableChannel(base, (tpm_chnl_t)chnlId); - chnlId--; + (void)TPM_DisableChannel(base, (tpm_chnl_t)chnlId); + (void)TPM_DisableChannel(base, (tpm_chnl_t)chnlIdSecond); /* Now, the registers for input mode can be operated. */ if (true == edgeParam->enableSwap) @@ -913,8 +989,8 @@ void TPM_SetupDualEdgeCapture(TPM_Type *base, /* Input filter setup for channel n+1 input */ reg = base->FILTER; - reg &= ~((uint32_t)TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * (chnlId + 1U))); - reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * (chnlId + 1U))); + reg &= ~((uint32_t)TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * chnlIdSecond)); + reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * chnlIdSecond)); base->FILTER = reg; } else @@ -936,9 +1012,8 @@ void TPM_SetupDualEdgeCapture(TPM_Type *base, } /* Setup the edge detection from channel n and n+1*/ - TPM_EnableChannel(base, (tpm_chnl_t)chnlId, (uint8_t)edgeParam->currChanEdgeMode); - chnlId++; - TPM_EnableChannel(base, (tpm_chnl_t)chnlId, (uint8_t)edgeParam->nextChanEdgeMode); + (void)TPM_EnableChannel(base, (tpm_chnl_t)chnlId, (uint8_t)edgeParam->currChanEdgeMode); + (void)TPM_EnableChannel(base, (tpm_chnl_t)chnlIdSecond, (uint8_t)edgeParam->nextChanEdgeMode); } #endif @@ -961,7 +1036,7 @@ void TPM_SetupQuadDecode(TPM_Type *base, assert(1U == (uint8_t)FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base)); /* Disable channel 0 */ - TPM_DisableChannel(base, kTPM_Chnl_0); + (void)TPM_DisableChannel(base, kTPM_Chnl_0); uint32_t reg; @@ -991,7 +1066,7 @@ void TPM_SetupQuadDecode(TPM_Type *base, #endif /* Disable channel 1 */ - TPM_DisableChannel(base, kTPM_Chnl_0); + (void)TPM_DisableChannel(base, kTPM_Chnl_0); /* Set Phase B filter value */ reg = base->FILTER; @@ -1026,7 +1101,6 @@ void TPM_SetupQuadDecode(TPM_Type *base, /* Enable Quad decode */ base->QDCTRL |= TPM_QDCTRL_QUADEN_MASK; } - #endif /*! @@ -1149,6 +1223,13 @@ void TPM_RegisterCallBack(TPM_Type *base, tpm_callback_t callback) #endif } +/* + * $Function Coverage Justification$ + * Following functions are not covered. $ref tpm_c_ref_6$. + * - TPM_DriverIRQHandler() + * - TPM2_DriverIRQHandler() + */ + /*! * @brief TPM driver IRQ handler common entry. * @@ -1160,10 +1241,8 @@ void TPM_DriverIRQHandler(uint32_t instance) { if (instance < ARRAY_SIZE(s_tpmBases)) { - if (NULL != s_tpmCallback[instance]) - { - s_tpmCallback[instance](s_tpmBases[instance]); - } + assert(NULL != s_tpmCallback[instance]); + s_tpmCallback[instance](s_tpmBases[instance]); } SDK_ISR_EXIT_BARRIER; } @@ -1172,10 +1251,8 @@ void TPM_DriverIRQHandler(uint32_t instance) void TPM0_DriverIRQHandler(void); void TPM0_DriverIRQHandler(void) { - if (NULL != s_tpmCallback[0]) - { - s_tpmCallback[0](TPM0); - } + assert(NULL != s_tpmCallback[0]); + s_tpmCallback[0](TPM0); SDK_ISR_EXIT_BARRIER; } #endif @@ -1184,10 +1261,8 @@ void TPM0_DriverIRQHandler(void) void TPM1_DriverIRQHandler(void); void TPM1_DriverIRQHandler(void) { - if (NULL != s_tpmCallback[1]) - { - s_tpmCallback[1](TPM1); - } + assert(NULL != s_tpmCallback[1]); + s_tpmCallback[1](TPM1); SDK_ISR_EXIT_BARRIER; } #endif @@ -1196,10 +1271,8 @@ void TPM1_DriverIRQHandler(void) void TPM2_DriverIRQHandler(void); void TPM2_DriverIRQHandler(void) { - if (NULL != s_tpmCallback[2]) - { - s_tpmCallback[2](TPM2); - } + assert(NULL != s_tpmCallback[2]); + s_tpmCallback[2](TPM2); SDK_ISR_EXIT_BARRIER; } #endif diff --git a/mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.h b/mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.h index 42bb325d6..931455456 100644 --- a/mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.h +++ b/mcux/mcux-sdk-ng/drivers/tpm/fsl_tpm.h @@ -30,10 +30,25 @@ /*! @name Driver version */ /*! @{ */ -/*! @brief TPM driver version 2.3.5. */ -#define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 3, 5)) +/*! @brief TPM driver version 2.4.0. */ +#define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) /*! @} */ +/*! + * @brief Max loops to wait for writing register. + * + * When writing MOD CnV CnSC and SC register, driver will wait until register is updated. + * This parameter defines how many loops to check completion before return timeout. + * If defined as 0, driver will wait forever until completion. + */ +#ifndef TPM_TIMEOUT +#ifdef CONFIG_TPM_TIMEOUT +#define TPM_TIMEOUT CONFIG_TPM_TIMEOUT +#else +#define TPM_TIMEOUT 0 +#endif +#endif + /*! @brief Help macro to get the max counter value */ #define TPM_MAX_COUNTER_VALUE(x) ((1U != (uint8_t)FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x)) ? 0xFFFFU : 0xFFFFFFFFU) @@ -454,8 +469,9 @@ tpm_clock_prescale_t TPM_CalculateCounterClkDiv(TPM_Type *base, uint32_t counter * @param pwmFreq_Hz PWM signal frequency in Hz * @param srcClock_Hz TPM counter clock in Hz * - * @return kStatus_Success if the PWM setup was successful, - * kStatus_Error on failure + * @return kStatus_Success PWM setup successful + * kStatus_Error PWM setup failed + * kStatus_Timeout PWM setup timeout when write register CnV or MOD */ status_t TPM_SetupPwm(TPM_Type *base, const tpm_chnl_pwm_signal_param_t *chnlParams, @@ -519,11 +535,22 @@ static inline uint8_t TPM_GetChannelContorlBits(TPM_Type *base, tpm_chnl_t chnlN * * @param base TPM peripheral base address * @param chnlNumber The channel number + * @return kStatus_Success PWM setup successful + * kStatus_Timeout PWM setup timeout when write register CnSC */ -static inline void TPM_DisableChannel(TPM_Type *base, tpm_chnl_t chnlNumber) +static inline status_t TPM_DisableChannel(TPM_Type *base, tpm_chnl_t chnlNumber) { +#if TPM_TIMEOUT + uint32_t timeout = TPM_TIMEOUT; +#endif do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif /* Clear channel MSnB:MSnA and ELSnB:ELSnA to disable its output. */ base->CONTROLS[chnlNumber].CnSC &= ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); @@ -534,9 +561,10 @@ static inline void TPM_DisableChannel(TPM_Type *base, tpm_chnl_t chnlNumber) * (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) * not covered. $ref tpm_h_ref_1$. */ - } while (0U != (base->CONTROLS[chnlNumber].CnSC & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))); + + return kStatus_Success; } /*! @@ -548,15 +576,25 @@ static inline void TPM_DisableChannel(TPM_Type *base, tpm_chnl_t chnlNumber) * @param chnlNumber The channel number * @param control The contorl bits value. This is the logical OR of members of the * enumeration @ref tpm_chnl_control_bit_mask_t. + * @return kStatus_Success PWM setup successful + * kStatus_Timeout PWM setup timeout when write register CnSC */ -static inline void TPM_EnableChannel(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t control) +static inline status_t TPM_EnableChannel(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t control) { +#if TPM_TIMEOUT + uint32_t timeout = TPM_TIMEOUT; +#endif #if defined(FSL_FEATURE_TPM_CnSC_CHF_WRITE_0_CLEAR) && FSL_FEATURE_TPM_CnSC_CHF_WRITE_0_CLEAR control |= TPM_CnSC_CHF_MASK; #endif - do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif /* Set channel MSB:MSA and ELSB:ELSA bits. */ base->CONTROLS[chnlNumber].CnSC = (base->CONTROLS[chnlNumber].CnSC & @@ -573,6 +611,8 @@ static inline void TPM_EnableChannel(TPM_Type *base, tpm_chnl_t chnlNumber, uint } while ((control & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)) != (uint8_t)(base->CONTROLS[chnlNumber].CnSC & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))); + + return kStatus_Success; } /*! @@ -597,11 +637,13 @@ void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capt * @param chnlNumber The channel number * @param compareMode Action to take on the channel output when the compare condition is met * @param compareValue Value to be programmed in the CnV register. + * @return kStatus_Success PWM setup successful + * kStatus_Timeout PWM setup timeout when write register CnV */ -void TPM_SetupOutputCompare(TPM_Type *base, - tpm_chnl_t chnlNumber, - tpm_output_compare_mode_t compareMode, - uint32_t compareValue); +status_t TPM_SetupOutputCompare(TPM_Type *base, + tpm_chnl_t chnlNumber, + tpm_output_compare_mode_t compareMode, + uint32_t compareValue); #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE /*! @@ -845,9 +887,14 @@ static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask) * * @param base TPM peripheral base address * @param ticks A timer period in units of ticks, which should be equal or greater than 1. + * @return kStatus_Success PWM setup successful + * kStatus_Timeout PWM setup timeout when write register CnSC */ -static inline void TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks) +static inline status_t TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks) { +#if TPM_TIMEOUT + uint32_t timeout = TPM_TIMEOUT; +#endif if (1U != (uint8_t)FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(base)) { assert(ticks <= 0xFFFFU); @@ -863,12 +910,20 @@ static inline void TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks) */ do { +#if TPM_TIMEOUT + if (timeout-- == 0U) + { + return kStatus_Timeout; + } +#endif base->MOD = ticks; /* * $Branch Coverage Justification$ * (ticks != base->MOD) not covered. $ref tpm_h_ref_2$. */ } while (ticks != base->MOD); + + return kStatus_Success; } /*! @@ -916,9 +971,15 @@ static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource * @brief Stops the TPM counter. * * @param base TPM peripheral base address + * @return kStatus_Success PWM setup successful + * kStatus_Timeout PWM setup timeout when write register CnSC */ -static inline void TPM_StopTimer(TPM_Type *base) +static inline status_t TPM_StopTimer(TPM_Type *base) { +#if TPM_TIMEOUT + uint32_t timeout = TPM_TIMEOUT; +#endif + #if defined(FSL_FEATURE_TPM_HAS_SC_CLKS) && FSL_FEATURE_TPM_HAS_SC_CLKS /* Set clock source to none to disable counter */ base->SC &= ~(TPM_SC_CLKS_MASK); @@ -926,6 +987,12 @@ static inline void TPM_StopTimer(TPM_Type *base) /* Wait till this reads as zero acknowledging the counter is disabled */ while (0U != (base->SC & TPM_SC_CLKS_MASK)) { +#if TPM_TIMEOUT + if (--timeout == 0U) + { + return kStatus_Timeout; + } +#endif } #else /* Set clock source to none to disable counter */ @@ -934,8 +1001,16 @@ static inline void TPM_StopTimer(TPM_Type *base) /* Wait till this reads as zero acknowledging the counter is disabled */ while (0U != (base->SC & TPM_SC_CMOD_MASK)) { +#if TPM_TIMEOUT + if (--timeout == 0U) + { + return kStatus_Timeout; + } +#endif } #endif + + return kStatus_Success; } /*! @}*/ diff --git a/mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.c b/mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.c index 57134999e..e80bc96be 100644 --- a/mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.c +++ b/mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.c @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 NXP + * Copyright 2021-2023,2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -373,7 +373,8 @@ void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwCon base->TRDC_FLW_ABASE = flwConfiguration->arrayBaseAddr; base->TRDC_FLW_BCNT = flwConfiguration->blockCount; - base->TRDC_FLW_CTL = TRDC_TRDC_FLW_CTL_V(flwConfiguration->enable) | TRDC_TRDC_FLW_CTL_LK(flwConfiguration->lock); + base->TRDC_FLW_CTL = TRDC_TRDC_FLW_CTL_V(flwConfiguration->enable ? 1U : 0U) | + TRDC_TRDC_FLW_CTL_LK(flwConfiguration->lock ? 1U : 0U); } #if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || (defined(__XTENSA__))) @@ -579,26 +580,26 @@ void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, } /*! - * brief Enables the update of the selected domians. + * brief Enables the update of the selected domains. * - * After the domians' update are enabled, their regions' NSE bits can be set or clear. + * After the domains' update are enabled, their regions' NSE bits can be set or clear. * * param base TRDC peripheral base address. * param mrcIdx MRC index. - * param domianMask Bit mask of the domains to be enabled. + * param domainMask Bit mask of the domains to be enabled. * param enable True to enable, false to disable. */ -void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable) +void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask, bool enable) { assert(NULL != base); if (enable) { - base->MRC_INDEX[mrcIdx].MRC_NSE_RGN_INDIRECT |= ((uint32_t)domianMask << 16U); + base->MRC_INDEX[mrcIdx].MRC_NSE_RGN_INDIRECT |= ((uint32_t)domainMask << 16U); } else { - base->MRC_INDEX[mrcIdx].MRC_NSE_RGN_INDIRECT &= ~((uint32_t)domianMask << 16U); + base->MRC_INDEX[mrcIdx].MRC_NSE_RGN_INDIRECT &= ~((uint32_t)domainMask << 16U); } } @@ -641,7 +642,7 @@ void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask * * param base TRDC peripheral base address. * param mrcIdx MRC index. - * param domainMask Bit mask of the domians whose NSE bits to clear. + * param domainMask Bit mask of the domains whose NSE bits to clear. */ void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask) { @@ -690,7 +691,7 @@ void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_de /* Set configuration for word 1 */ regAddr += 4U; - data = TRDC_MRC_DOM0_RGD_W_VLD(config->valid) | TRDC_MRC_DOM0_RGD_W_NSE(config->nseEnable) | + data = TRDC_MRC_DOM0_RGD_W_VLD(config->valid ? 1U : 0U) | TRDC_MRC_DOM0_RGD_W_NSE(config->nseEnable ? 1U : 0U) | ((config->endAddr) & ~(TRDC_MRC_DOM0_RGD_W_VLD_MASK | TRDC_MRC_DOM0_RGD_W_NSE_MASK)); *(uint32_t *)regAddr = data; } diff --git a/mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.h b/mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.h index 59a6132a2..3f4d93365 100644 --- a/mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.h +++ b/mcux/mcux-sdk-ng/drivers/trdc/fsl_trdc.h @@ -1060,16 +1060,16 @@ void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, uint8_t regIdx); /*! - * @brief Enables the update of the selected domians. + * @brief Enables the update of the selected domains. * - * After the domians' update are enabled, their regions' NSE bits can be set or clear. + * After the domains' update are enabled, their regions' NSE bits can be set or clear. * * @param base TRDC peripheral base address. * @param mrcIdx MRC index. - * @param domianMask Bit mask of the domains to be enabled. + * @param domainMask Bit mask of the domains to be enabled. * @param enable True to enable, false to disable. */ -void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable); +void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask, bool enable); /*! * @brief Sets the NSE bits of the selected regions for domains. @@ -1100,7 +1100,7 @@ void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask * * @param base TRDC peripheral base address. * @param mrcIdx MRC index. - * @param domainMask Bit mask of the domians whose NSE bits to clear. + * @param domainMask Bit mask of the domains whose NSE bits to clear. */ void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask); diff --git a/mcux/mcux-sdk-ng/drivers/trng/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/trng/CMakeLists.txt index 783987945..bff472ea8 100644 --- a/mcux/mcux-sdk-ng/drivers/trng/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/trng/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.trng) - mcux_component_version(2.0.18) + mcux_component_version(2.0.19) mcux_add_source(SOURCES fsl_trng.c fsl_trng.h) diff --git a/mcux/mcux-sdk-ng/drivers/trng/fsl_trng.c b/mcux/mcux-sdk-ng/drivers/trng/fsl_trng.c index 406577641..ae7f37453 100644 --- a/mcux/mcux-sdk-ng/drivers/trng/fsl_trng.c +++ b/mcux/mcux-sdk-ng/drivers/trng/fsl_trng.c @@ -96,7 +96,7 @@ #define FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 1 #define FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM_VALUE 31952 -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(MIMXRT798S_cm33_core0_SERIES)) /* RT700 specific settings for the TRNG */ #define TRNG_USER_CONFIG_DEFAULT_LOCK 0 @@ -164,6 +164,49 @@ #define TRNG_ENT_COUNT TRNG_ENTA_ENT_COUNT +#elif (defined(MCXL253_cm0plus_SERIES) || defined(MCXL253_cm33_SERIES) || \ + defined(MCXL254_cm0plus_SERIES) || defined(MCXL254_cm33_SERIES) || \ + defined(MCXL255_cm0plus_SERIES) || defined(MCXL255_cm33_SERIES) || \ + defined(MCXA266_SERIES) || defined(MCXA366_SERIES)) + +#ifndef TRNG_ENT_COUNT +#define TRNG_ENT_COUNT TRNG_ENTA_ENT_COUNT +#endif + +/* MCXA/MCXL specific settings for the TRNG */ +#define TRNG_USER_CONFIG_DEFAULT_LOCK 0 +#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 32000 +#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 1024 +#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 0 +#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 2 +#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 32 + +#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 596 +#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 169) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 187 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 112) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 105 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 77) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 97 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 64) +// The following ones are unused, MCXA and MCXL RNG does not support those. +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 0 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM 0 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 0 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM 0 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 0 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM 0 +#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 0 +#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM 0 + +#define TRNG_USER_CONFIG_DEFAULT_OSCILLATOR_MODE kTRNG_DualOscillatorMode +#define TRNG_USER_CONFIG_DEFAULT_OSC2_DIV kTRNG_RingOscDiv0 + +#define FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1 +#define FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM_VALUE 30000 +#define FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 1 +#define FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM_VALUE 75000 + #else #ifndef TRNG_ENT_COUNT diff --git a/mcux/mcux-sdk-ng/drivers/trng/fsl_trng.h b/mcux/mcux-sdk-ng/drivers/trng/fsl_trng.h index e0670a119..bf6e2aaaf 100644 --- a/mcux/mcux-sdk-ng/drivers/trng/fsl_trng.h +++ b/mcux/mcux-sdk-ng/drivers/trng/fsl_trng.h @@ -23,12 +23,14 @@ /*! @name Driver version */ /*! @{ */ -/*! @brief TRNG driver version 2.0.18. +/*! @brief TRNG driver version 2.0.19. * - * Current version: 2.0.18 + * Current version: 2.0.19 * * * Change log: + * - version 2.0.19 + * - Added support for MCXA and MCXL. * - version 2.0.18 * - TRNG health checks now done in software on RT5xx and RT6xx. * - version 2.0.17 diff --git a/mcux/mcux-sdk-ng/drivers/tsi/tsi_v5/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/tsi/tsi_v5/CMakeLists.txt index 77974e5d6..bca219970 100644 --- a/mcux/mcux-sdk-ng/drivers/tsi/tsi_v5/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/tsi/tsi_v5/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.tsi_v5) - mcux_component_version(2.6.0) + mcux_component_version(2.6.1) mcux_add_source(SOURCES fsl_tsi_v5.h fsl_tsi_v5.c) diff --git a/mcux/mcux-sdk-ng/drivers/tsi/tsi_v5/fsl_tsi_v5.c b/mcux/mcux-sdk-ng/drivers/tsi/tsi_v5/fsl_tsi_v5.c index 181f9c22f..f93c9dfab 100644 --- a/mcux/mcux-sdk-ng/drivers/tsi/tsi_v5/fsl_tsi_v5.c +++ b/mcux/mcux-sdk-ng/drivers/tsi/tsi_v5/fsl_tsi_v5.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2021,2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -95,7 +95,7 @@ void TSI_InitSelfCapMode(TSI_Type *base, const tsi_selfCap_config_t *config) temp = (base->MODE) & ~(TSI_MODE_SETCLK_MASK | TSI_MODE_MODE_MASK | TSI_MODE_S_SEN_MASK); base->MODE = temp | (TSI_MODE_S_SEN(config->enableSensitivity) | TSI_MODE_SETCLK(config->commonConfig.mainClock) | TSI_MODE_MODE(config->commonConfig.mode)); - base->SHIELD |= (uint32_t)config->enableShield; + base->SHIELD = (uint32_t)config->enableShield; #endif base->GENCS = diff --git a/mcux/mcux-sdk-ng/drivers/tsi/tsi_v6/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/tsi/tsi_v6/CMakeLists.txt index b7214737e..25457f2f8 100644 --- a/mcux/mcux-sdk-ng/drivers/tsi/tsi_v6/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/tsi/tsi_v6/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.tsi_v6) - mcux_component_version(2.0.0) + mcux_component_version(2.0.1) mcux_add_source(SOURCES fsl_tsi_v6.h fsl_tsi_v6.c) diff --git a/mcux/mcux-sdk-ng/drivers/tsi/tsi_v6/fsl_tsi_v6.h b/mcux/mcux-sdk-ng/drivers/tsi/tsi_v6/fsl_tsi_v6.h index c6fc98772..c1774fc29 100644 --- a/mcux/mcux-sdk-ng/drivers/tsi/tsi_v6/fsl_tsi_v6.h +++ b/mcux/mcux-sdk-ng/drivers/tsi/tsi_v6/fsl_tsi_v6.h @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022,2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -91,18 +91,26 @@ typedef enum _tsi_sensitivity_xdn_option * * These constants define the shield pin used for HW shielding functionality. One or more shield pin can be selected. * The involved bitfield is not fix can change from device to device (KE16Z7 and KE17Z7 support 3 shield pins, other KE - * serials only support 1 shield pin). + * serials only support 1 shield pin, MCXN devices has 4 shield pins). */ typedef enum _tsi_shield { - kTSI_shieldAllOff = 0U, /*!< No pin used */ - kTSI_shield0On = 1U, /*!< Shield 0 pin used */ - kTSI_shield1On = 2U, /*!< Shield 1 pin used */ - kTSI_shield1and0On = 3U, /*!< Shield 0,1 pins used */ - kTSI_shield2On = 4U, /*!< Shield 2 pin used */ - kTSI_shield2and0On = 5U, /*!< Shield 2,0 pins used */ - kTSI_shield2and1On = 6U, /*!< Shield 2,1 pins used */ - kTSI_shieldAllOn = 7U, /*!< Shield 2,1,0 pins used */ + kTSI_shieldAllOff = 0U, /*!< No pin used */ + kTSI_shield0On = 1U, /*!< Shield 0 pin used */ + kTSI_shield1On = 2U, /*!< Shield 1 pin used */ + kTSI_shield1and0On = 3U, /*!< Shield 0,1 pins used */ + kTSI_shield2On = 4U, /*!< Shield 2 pin used */ + kTSI_shield2and0On = 5U, /*!< Shield 2,0 pins used */ + kTSI_shield2and1On = 6U, /*!< Shield 2,1 pins used */ + kTSI_shield2and1and0On = 7U, /*!< Shield 2,1,0 pins used */ + kTSI_shield3On = 8U, /*!< Shield 3 pin used */ + kTSI_shield3and0On = 9U, /*!< Shield 3,0 pins used */ + kTSI_shield3and1On = 10U, /*!< Shield 3,1 pins used */ + kTSI_shield3and1and0On = 11U, /*!< Shield 3,1,0 pins used */ + kTSI_shield3and2On = 12U, /*!< Shield 3,2 pin used */ + kTSI_shield3and2and0On = 13U, /*!< Shield 3,2,0 pins used */ + kTSI_shield3and2and1On = 14U, /*!< Shield 3,2,1 pins used */ + kTSI_shieldAllOn = 15U, /*!< Shield 3,2,1,0 pins used */ } tsi_shield_t; /*! diff --git a/mcux/mcux-sdk-ng/drivers/tspc/fsl_tspc.h b/mcux/mcux-sdk-ng/drivers/tspc/fsl_tspc.h index 7f5304ff9..00f2fe6a6 100644 --- a/mcux/mcux-sdk-ng/drivers/tspc/fsl_tspc.h +++ b/mcux/mcux-sdk-ng/drivers/tspc/fsl_tspc.h @@ -5,7 +5,7 @@ */ #ifndef FSL_TSPC_H_ -#define FSL_XTSPC_H_ +#define FSL_TSPC_H_ #include "fsl_common.h" diff --git a/mcux/mcux-sdk-ng/drivers/tstmr/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/tstmr/CMakeLists.txt index 9e9cf6027..d49b54108 100644 --- a/mcux/mcux-sdk-ng/drivers/tstmr/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/tstmr/CMakeLists.txt @@ -1,11 +1,12 @@ -# Copyright 2024 NXP +# Copyright 2024,2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.tstmr) - mcux_component_version(2.0.2) + mcux_component_version(2.1.0) mcux_add_source(SOURCES fsl_tstmr.h) + mcux_add_source(SOURCES fsl_tstmr.c) mcux_add_include(INCLUDES .) diff --git a/mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.c b/mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.c new file mode 100644 index 000000000..f319ffec2 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.c @@ -0,0 +1,137 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_tstmr.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.tstmr" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION) && FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION + +/*! + * @brief Get TSTMR instance index from base address. + * @param base TSTMR peripheral base address. + * @return Instance index. + */ +uint32_t TSTMR_GetInstance(TSTMR_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static TSTMR_Type *const s_tstmrBases[FSL_FEATURE_SOC_TSTMR_COUNT] = TSTMR_BASE_PTRS; + +/*! @brief Clock mapping for each TSTMR instance. Use kCLOCK_NOGATE for instances without clocks */ +static const clock_ip_name_t s_tstmrClockMap[FSL_FEATURE_SOC_TSTMR_COUNT] = TSTMR_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t TSTMR_GetInstance(TSTMR_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_TSTMR_COUNT; instance++) + { + if (MSDK_REG_SECURE_ADDR(s_tstmrBases[instance]) == MSDK_REG_SECURE_ADDR(base)) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_TSTMR_COUNT); + + return instance; +} + +#endif /* FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION */ + +/*! + * brief Init TSTMR. + * + * This function initializes the TSTMR module. + * + * param base TSTMR peripheral base address. + */ +void TSTMR_Init(TSTMR_Type *base) +{ +#if defined(FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION) && FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_tstmrClockMap[TSTMR_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION */ +} + +/*! + * brief Deinit TSTMR. + * + * This function deinitializes the TSTMR module. + * + * param base TSTMR peripheral base address. + */ +void TSTMR_Deinit(TSTMR_Type *base) +{ +#if defined(FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION) && FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_tstmrClockMap[TSTMR_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION */ +} + +/*! + * brief Delays for a specified number of microseconds. + * + * This function repeatedly reads the timestamp register and waits for the user-specified + * delay value. + * + * param base TSTMR peripheral base address. + * param delayInUs Delay value in microseconds. + */ +void TSTMR_DelayUs(TSTMR_Type *base, uint64_t delayInUs) +{ +#if defined(TSTMR_CLOCK_FREQUENCY_MHZ) || (defined(FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION) && \ + FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION) +#if defined(TSTMR_CLOCK_FREQUENCY_MHZ) + uint64_t targetTicks = TSTMR_CLOCK_FREQUENCY_MHZ * delayInUs; +#elif defined(FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION) && \ + FSL_FEATURE_TSTMR_HAS_CLOCK_FREQUENCY_CONFIGURATION + uint32_t instance = TSTMR_GetInstance(base); + /* Get the TSTMR clock frequency in Hz */ + uint32_t clockFreqHz = CLOCK_GetTstmrFreq(instance); + assert(clockFreqHz > 0U); + uint64_t targetTicks = (uint64_t)clockFreqHz * delayInUs / 1000000U; +#endif + /* 56-bit mask */ + const uint64_t TSTMR_MASK = 0x00FFFFFFFFFFFFFFULL; + uint64_t startTime = TSTMR_ReadTimeStamp(base); + while (true) + { + uint64_t currentTime = TSTMR_ReadTimeStamp(base); + uint64_t elapsed; + if (currentTime >= startTime) + { + elapsed = currentTime - startTime; + } + else + { + /* Timer wrapped, handle wrap around for 56 bits */ + elapsed = (TSTMR_MASK - startTime + 1U) + currentTime; + } + if (elapsed >= targetTicks) + { + break; + } + } +#else + assert(0); +#endif +} \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.h b/mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.h index cac54313d..4c19f7b42 100644 --- a/mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.h +++ b/mcux/mcux-sdk-ng/drivers/tstmr/fsl_tstmr.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2023 NXP + * Copyright 2016-2017, 2023, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -19,14 +19,9 @@ * Definitions ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.tstmr" -#endif - /*! @name Driver version */ /*! @{ */ -#define FSL_TSTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ +#define FSL_TSTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ /*! @} */ /******************************************************************************* @@ -37,12 +32,37 @@ extern "C" { #endif +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Init TSTMR. + * + * This function initializes the TSTMR module. + * + * @param base TSTMR peripheral base address. + */ +void TSTMR_Init(TSTMR_Type *base); + +/*! + * @brief Deinit TSTMR. + * + * This function deinitializes the TSTMR module. + * + * @param base TSTMR peripheral base address. + */ +void TSTMR_Deinit(TSTMR_Type *base); + +/*! @}*/ + /*! * @brief Reads the time stamp. * * This function reads the low and high registers and returns the 56-bit free running * counter value. This can be read by software at any time to determine the software ticks. - * TSTMR registers can be read with 32-bit accesses only. The TSTMR LOW read should occur first, + * TSTMR registers can be read with 32-bit accesses only. The TSTMR LOW read should occur first, * followed by the TSTMR HIGH read. * * @param base TSTMR peripheral base address. @@ -76,17 +96,7 @@ static inline uint64_t TSTMR_ReadTimeStamp(TSTMR_Type *base) * @param base TSTMR peripheral base address. * @param delayInUs Delay value in microseconds. */ -static inline void TSTMR_DelayUs(TSTMR_Type *base, uint64_t delayInUs) -{ -#if defined(TSTMR_CLOCK_FREQUENCY_MHZ) - uint64_t startTime = TSTMR_ReadTimeStamp(base); - while (TSTMR_ReadTimeStamp(base) - startTime < TSTMR_CLOCK_FREQUENCY_MHZ * delayInUs) - { - } -#else - assert(0); -#endif -} +void TSTMR_DelayUs(TSTMR_Type *base, uint64_t delayInUs); #if defined(__cplusplus) } diff --git a/mcux/mcux-sdk-ng/drivers/usdhc/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/usdhc/CMakeLists.txt index b8213ffb1..7459b904c 100644 --- a/mcux/mcux-sdk-ng/drivers/usdhc/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/usdhc/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.usdhc) - mcux_component_version(2.8.5) + mcux_component_version(2.8.6) mcux_add_source(SOURCES fsl_usdhc.c fsl_usdhc.h) diff --git a/mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.c b/mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.c index 729860301..153229dbc 100644 --- a/mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.c +++ b/mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.c @@ -783,6 +783,15 @@ static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, *(data->rxData) = s_usdhcBootDummy; } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + if (IS_USDHC_FLAG_SET(interruptStatus, kUSDHC_DataCompleteFlag)) + { + if (data->rxData != NULL) + { + DCACHE_InvalidateByRange((uintptr_t)(data->rxData), (data->blockSize) * (data->blockCount)); + } + } +#endif USDHC_ClearInterruptStatusFlags(base, ((uint32_t)kUSDHC_DataDMAFlag | (uint32_t)kUSDHC_TuningErrorFlag)); } else diff --git a/mcux/mcux-sdk-ng/drivers/wdog32/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/wdog32/CMakeLists.txt index 078362a09..84066bec7 100644 --- a/mcux/mcux-sdk-ng/drivers/wdog32/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/wdog32/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.wdog32) - mcux_component_version(2.2.0) + mcux_component_version(2.2.1) mcux_add_source(SOURCES fsl_wdog32.h fsl_wdog32.c) diff --git a/mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.c b/mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.c index 6b533829c..f193ece5a 100644 --- a/mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.c +++ b/mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.c @@ -165,11 +165,11 @@ status_t WDOG32_Init(WDOG_Type *base, const wdog32_config_t *config) RESET_ReleasePeripheralReset(s_wdogResets[WDOG32_GetInstance(base)]); #endif - value = WDOG_CS_EN((uint32_t)regConfig->enableWdog32) | WDOG_CS_CLK((uint32_t)regConfig->clockSource) | - WDOG_CS_INT((uint32_t)regConfig->enableInterrupt) | WDOG_CS_WIN((uint32_t)regConfig->enableWindowMode) | - WDOG_CS_UPDATE((uint32_t)regConfig->enableUpdate) | WDOG_CS_DBG((uint32_t)regConfig->workMode.enableDebug) | - WDOG_CS_STOP((uint32_t)regConfig->workMode.enableStop) | - WDOG_CS_WAIT((uint32_t)regConfig->workMode.enableWait) | WDOG_CS_PRES(tempPrescaler) | + value = WDOG_CS_EN((uint32_t)(regConfig->enableWdog32 ? 1: 0)) | WDOG_CS_CLK((uint32_t)regConfig->clockSource) | + WDOG_CS_INT((uint32_t)(regConfig->enableInterrupt ? 1 : 0)) | WDOG_CS_WIN((uint32_t)(regConfig->enableWindowMode ? 1 : 0)) | + WDOG_CS_UPDATE((uint32_t)(regConfig->enableUpdate ? 1 : 0)) | WDOG_CS_DBG((uint32_t)(regConfig->workMode.enableDebug ? 1 : 0)) | + WDOG_CS_STOP((uint32_t)(regConfig->workMode.enableStop ? 1 : 0)) | + WDOG_CS_WAIT((uint32_t)(regConfig->workMode.enableWait ? 1 : 0)) | WDOG_CS_PRES(tempPrescaler) | WDOG_CS_CMD32EN(1UL) | WDOG_CS_TST((uint32_t)regConfig->testMode); /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence diff --git a/mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.h b/mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.h index 2a0ef7dbc..4bcf974d6 100644 --- a/mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.h +++ b/mcux/mcux-sdk-ng/drivers/wdog32/fsl_wdog32.h @@ -32,7 +32,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief WDOG32 driver version. */ -#define FSL_WDOG32_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +#define FSL_WDOG32_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*! @} */ /*! @@ -60,7 +60,7 @@ #ifdef WDOG_CS_RCS_MASK #ifndef WDOG32_RECONFIG_TIMEOUT #ifdef CONFIG_WDOG32_RECONFIG_TIMEOUT - #define WDOG32_RECONFIG_TIMEOUT WDOG32_RECONFIG_TIMEOUT + #define WDOG32_RECONFIG_TIMEOUT CONFIG_WDOG32_RECONFIG_TIMEOUT #else #define WDOG32_RECONFIG_TIMEOUT 0U #endif @@ -431,7 +431,7 @@ static inline void WDOG32_Refresh(WDOG_Type *base) */ static inline uint16_t WDOG32_GetCounterValue(WDOG_Type *base) { - return (uint16_t)base->CNT; + return (uint16_t)(base->CNT & 0xffffu); } /*! @} */ diff --git a/mcux/mcux-sdk-ng/drivers/wwdt/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/wwdt/CMakeLists.txt index 5224a4dc7..760d94cba 100644 --- a/mcux/mcux-sdk-ng/drivers/wwdt/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/wwdt/CMakeLists.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.wwdt) - mcux_component_version(2.1.9) + mcux_component_version(2.1.10) mcux_add_source(SOURCES fsl_wwdt.h fsl_wwdt.c) diff --git a/mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.c b/mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.c index 36e92ef13..ea25d1f3e 100644 --- a/mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.c +++ b/mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -39,7 +39,7 @@ static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) +#if defined(WWDT_RSTS) /*! @brief Pointers to WWDT resets for each instance. */ static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; #endif @@ -146,7 +146,7 @@ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) +#if defined(WWDT_RSTS) /* Reset the module. */ RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); #endif diff --git a/mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.h b/mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.h index 40c90e48b..c539c5a55 100644 --- a/mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.h +++ b/mcux/mcux-sdk-ng/drivers/wwdt/fsl_wwdt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,7 +24,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief Defines WWDT driver version. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) +#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 10)) /*! @} */ /*! @name Refresh sequence */ From fd66dc01da2ea4f2552fcc30ebe6cf3222d57dd0 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:10:36 +0800 Subject: [PATCH 04/21] hal_nxp: mcux-sdk-ng: Update device/i.mx to sdk 25.09.00 Signed-off-by: Zhaoxiang Jin --- mcux/mcux-sdk-ng/devices/i.MX/SBOM.spdx.json | 12 +- .../i.MX7ULP/MCIMX7U3/MCIMX7U3_cm4_features.h | 87 +- .../i.MX7ULP/MCIMX7U5/MCIMX7U5_cm4_features.h | 87 +- .../i.MX8M/MIMX8MD6/MIMX8MD6_cm4_COMMON.h | 19 +- .../i.MX8M/MIMX8MD6/MIMX8MD6_cm4_features.h | 21 +- .../i.MX8M/MIMX8MD6/system_MIMX8MD6_cm4.c | 19 + .../i.MX8M/MIMX8MD7/MIMX8MD7_cm4_COMMON.h | 19 +- .../i.MX8M/MIMX8MD7/MIMX8MD7_cm4_features.h | 21 +- .../i.MX8M/MIMX8MD7/system_MIMX8MD7_cm4.c | 19 + .../i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_COMMON.h | 19 +- .../i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_features.h | 21 +- .../i.MX8M/MIMX8MQ5/system_MIMX8MQ5_cm4.c | 19 + .../i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_COMMON.h | 19 +- .../i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_features.h | 21 +- .../i.MX8M/MIMX8MQ6/system_MIMX8MQ6_cm4.c | 19 + .../i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_COMMON.h | 19 +- .../i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_features.h | 21 +- .../i.MX8M/MIMX8MQ7/system_MIMX8MQ7_cm4.c | 19 + .../devices/i.MX/i.MX8M/periph/PERI_ENET.h | 5 +- .../i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_COMMON.h | 31 +- .../i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_features.h | 14 +- .../i.MX8MM/MIMX8MM1/system_MIMX8MM1_cm4.c | 19 + .../i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_COMMON.h | 31 +- .../i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_features.h | 14 +- .../i.MX8MM/MIMX8MM2/system_MIMX8MM2_cm4.c | 19 + .../i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_COMMON.h | 31 +- .../i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_features.h | 14 +- .../i.MX8MM/MIMX8MM3/system_MIMX8MM3_cm4.c | 19 + .../i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_COMMON.h | 31 +- .../i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_features.h | 14 +- .../i.MX8MM/MIMX8MM4/system_MIMX8MM4_cm4.c | 19 + .../i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_COMMON.h | 31 +- .../i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_features.h | 14 +- .../i.MX8MM/MIMX8MM5/system_MIMX8MM5_cm4.c | 19 + .../i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_COMMON.h | 31 +- .../i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_features.h | 14 +- .../i.MX/i.MX8MM/MIMX8MM6/drivers/fsl_clock.h | 6 +- .../i.MX8MM/MIMX8MM6/system_MIMX8MM6_cm4.c | 19 + .../devices/i.MX/i.MX8MM/periph/PERI_ENET.h | 5 +- .../i.MX/i.MX8MM/periph/PERI_FLEXSPI.h | 818 +-- .../i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_COMMON.h | 31 +- .../i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_features.h | 14 +- .../i.MX8MN/MIMX8MN1/system_MIMX8MN1_cm7.c | 19 + .../i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_COMMON.h | 31 +- .../i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_features.h | 14 +- .../i.MX8MN/MIMX8MN2/system_MIMX8MN2_cm7.c | 19 + .../i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_COMMON.h | 31 +- .../i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_features.h | 14 +- .../i.MX8MN/MIMX8MN3/system_MIMX8MN3_cm7.c | 19 + .../i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_COMMON.h | 31 +- .../i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_features.h | 14 +- .../i.MX8MN/MIMX8MN4/system_MIMX8MN4_cm7.c | 19 + .../i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_COMMON.h | 31 +- .../i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_features.h | 14 +- .../i.MX8MN/MIMX8MN5/system_MIMX8MN5_cm7.c | 19 + .../i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_COMMON.h | 31 +- .../i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_features.h | 14 +- .../i.MX/i.MX8MN/MIMX8MN6/drivers/fsl_clock.h | 6 +- .../i.MX8MN/MIMX8MN6/system_MIMX8MN6_cm7.c | 19 + .../devices/i.MX/i.MX8MN/periph/PERI_ENET.h | 5 +- .../i.MX/i.MX8MN/periph/PERI_FLEXSPI.h | 820 +-- .../i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_COMMON.h | 19 +- .../i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_features.h | 18 +- .../i.MX8MP/MIMX8ML2/system_MIMX8ML2_cm7.c | 19 + .../i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_COMMON.h | 19 +- .../i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_features.h | 18 +- .../i.MX8MP/MIMX8ML3/system_MIMX8ML3_cm7.c | 19 + .../i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_COMMON.h | 19 +- .../i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_features.h | 18 +- .../i.MX8MP/MIMX8ML4/system_MIMX8ML4_cm7.c | 19 + .../i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_COMMON.h | 19 +- .../i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_features.h | 18 +- .../i.MX8MP/MIMX8ML5/system_MIMX8ML5_cm7.c | 19 + .../i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_COMMON.h | 19 +- .../i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_features.h | 18 +- .../i.MX8MP/MIMX8ML6/system_MIMX8ML6_cm7.c | 19 + .../i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_COMMON.h | 19 +- .../i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_features.h | 18 +- .../i.MX/i.MX8MP/MIMX8ML8/drivers/fsl_clock.h | 6 +- .../i.MX8MP/MIMX8ML8/system_MIMX8ML8_cm7.c | 19 + .../devices/i.MX/i.MX8MP/periph/PERI_ENET.h | 5 +- .../devices/i.MX/i.MX8MP/periph/PERI_USB.h | 1 - .../i.MX8ULP/MIMX8UD3/MIMX8UD3_cm33_COMMON.h | 55 +- .../MIMX8UD3/MIMX8UD3_cm33_features.h | 113 +- .../i.MX8ULP/MIMX8UD3/MIMX8UD3_dsp0_COMMON.h | 5 +- .../MIMX8UD3/MIMX8UD3_dsp0_features.h | 113 +- .../i.MX8ULP/MIMX8UD5/MIMX8UD5_cm33_COMMON.h | 55 +- .../MIMX8UD5/MIMX8UD5_cm33_features.h | 113 +- .../i.MX8ULP/MIMX8UD5/MIMX8UD5_dsp0_COMMON.h | 5 +- .../MIMX8UD5/MIMX8UD5_dsp0_features.h | 113 +- .../i.MX8ULP/MIMX8UD7/MIMX8UD7_cm33_COMMON.h | 55 +- .../MIMX8UD7/MIMX8UD7_cm33_features.h | 113 +- .../i.MX8ULP/MIMX8UD7/MIMX8UD7_dsp0_COMMON.h | 5 +- .../MIMX8UD7/MIMX8UD7_dsp0_features.h | 113 +- .../i.MX8ULP/MIMX8US3/MIMX8US3_cm33_COMMON.h | 55 +- .../MIMX8US3/MIMX8US3_cm33_features.h | 113 +- .../i.MX8ULP/MIMX8US3/MIMX8US3_dsp0_COMMON.h | 5 +- .../MIMX8US3/MIMX8US3_dsp0_features.h | 113 +- .../i.MX8ULP/MIMX8US5/MIMX8US5_cm33_COMMON.h | 55 +- .../MIMX8US5/MIMX8US5_cm33_features.h | 113 +- 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1183 ++++- .../MIMX94398/MIMX94398_cm7_core1_features.h | 58 +- .../i.MX943/MIMX94398/drivers/fsl_clock.h | 4 +- .../MIMX94398/system_MIMX94398_cm33_core1.c | 9 +- .../MIMX94398/system_MIMX94398_cm33_core1.h | 31 + .../MIMX94398/system_MIMX94398_cm7_core0.c | 9 +- .../MIMX94398/system_MIMX94398_cm7_core0.h | 13 + .../MIMX94398/system_MIMX94398_cm7_core1.c | 9 +- .../MIMX94398/system_MIMX94398_cm7_core1.h | 13 + .../i.MX/i.MX943/periph/PERI_ANALOG_AGDET.h | 19 +- .../i.MX/i.MX943/periph/PERI_ANALOG_CMU.h | 19 +- .../i.MX/i.MX943/periph/PERI_ANALOG_PMRO.h | 19 +- .../i.MX/i.MX943/periph/PERI_ANALOG_SFA.h | 19 +- .../i.MX/i.MX943/periph/PERI_ANALOG_TCU.h | 19 +- .../i.MX/i.MX943/periph/PERI_ANALOG_VDET.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_AOI.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_CMU.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_CRC.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_CSTCU.h | 27 +- .../i.MX/i.MX943/periph/PERI_AON_EIM.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_ERM.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_FCCU.h | 531 +- .../i.MX/i.MX943/periph/PERI_AON_INTM.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_LSTCU.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_MCM.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_SYSPM.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_TCU.h | 19 +- .../i.MX/i.MX943/periph/PERI_AON_TRDC_MGR.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_ARDB.h | 19 +- .../i.MX/i.MX943/periph/PERI_ATU_USB2.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_AXBS.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_BBNSM.h | 19 +- .../periph/PERI_BBSM_BLK_CTRL_BBSMMIX.h | 19 +- .../i.MX/i.MX943/periph/PERI_BBSM_TCU.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_BISS.h | 19 +- .../i.MX943/periph/PERI_BLK_CTRL_NETCMIX.h | 19 +- .../i.MX943/periph/PERI_BLK_CTRL_NS_AONMIX.h | 19 +- .../i.MX943/periph/PERI_BLK_CTRL_S_AONMIX.h | 19 +- .../i.MX943/periph/PERI_BLK_CTRL_WAKEUPMIX.h | 19 +- .../i.MX/i.MX943/periph/PERI_CACHE_ECC_MCM.h | 51 +- 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.../devices/i.MX/i.MX943/periph/PERI_ECAT.h | 19 +- .../i.MX/i.MX943/periph/PERI_ENDAT2P2.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_ENDAT3.h | 19 +- .../i.MX/i.MX943/periph/PERI_ENETC_COMMON.h | 19 +- .../i.MX/i.MX943/periph/PERI_ENETC_GLOBAL.h | 19 +- .../i.MX943/periph/PERI_ENETC_PCI_TYPE0.h | 19 +- .../i.MX/i.MX943/periph/PERI_ENETC_PF_EMDIO.h | 19 +- .../i.MX/i.MX943/periph/PERI_ENETC_PF_TMR.h | 19 +- .../i.MX/i.MX943/periph/PERI_ENETC_PORT.h | 19 +- .../i.MX/i.MX943/periph/PERI_ENETC_SI.h | 19 +- .../i.MX943/periph/PERI_ENETC_VF_PCI_TYPE0.h | 19 +- .../i.MX943/periph/PERI_ENET_PHY_CTRL_EX.h | 19 +- .../periph/PERI_ENET_PHY_MAC_ADAPTER.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_EQDC.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_EWM.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_FLEXIO.h | 29 +- .../devices/i.MX/i.MX943/periph/PERI_FRO.h | 19 +- .../i.MX/i.MX943/periph/PERI_GLITCHFILTER.h | 19 +- .../i.MX/i.MX943/periph/PERI_GPC_CPU_CTRL.h | 19 +- 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.../devices/i.MX/i.MX943/periph/PERI_LPUART.h | 65 +- .../i.MX/i.MX943/periph/PERI_M7_A7_APB_MCM.h | 19 +- .../i.MX/i.MX943/periph/PERI_M7_A7_PPB_MCM.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_M7_CMU.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_M7_EIM.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_M7_ERM.h | 19 +- .../i.MX/i.MX943/periph/PERI_M7_LSTCU.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_M7_TCU.h | 19 +- .../i.MX/i.MX943/periph/PERI_MSGINTR.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_MU.h | 39 +- .../PERI_M_E_3_WR_I_MAIN_TRANSTATFILT.h | 19 +- ...RI_M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER.h | 19 +- .../i.MX943/periph/PERI_NECTMIX_CM33_AIPS.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_CMU.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_EIM.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_ENETC.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_ERM.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_ETH_LINK.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_IERB.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_LSTCU.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_MAX_CORE.h | 19 +- .../i.MX943/periph/PERI_NETC_OCSRAM_MCM.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_PORT.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_PRIV.h | 19 +- .../i.MX943/periph/PERI_NETC_PSEUDO_LINK.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_SW.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_SW_ENETC.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_TCU.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_TCU_CM33.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_TMR_BASE.h | 19 +- .../i.MX/i.MX943/periph/PERI_NETC_TRDC_MGR.h | 19 +- .../i.MX943/periph/PERI_NETC_TRDC_MGR_CM33.h | 19 +- .../i.MX/i.MX943/periph/PERI_NEUTRON.h | 19 +- .../i.MX/i.MX943/periph/PERI_NEUTRONS.h | 39 +- .../PERI_NOC_ALWAYS_ON_MAIN_RESFAULTCNTR.h | 19 +- .../i.MX943/periph/PERI_NOC_BLK_CTRL_NOCMIX.h | 19 +- .../i.MX/i.MX943/periph/PERI_NOC_CMU.h | 19 +- .../i.MX/i.MX943/periph/PERI_NOC_EIM.h | 19 +- .../i.MX/i.MX943/periph/PERI_NOC_GICA.h | 19 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.../PERI_NOC_I_PXP_WR_I_MAIN_TRANSTATFLTR.h | 19 +- .../i.MX/i.MX943/periph/PERI_NOC_LSTCU.h | 19 +- .../PERI_NOC_M_E_0_RD_I_MAIN_TRANSTATFILT.h | 19 +- .../periph/PERI_NOC_M_E_0_RD_I_M_QOSGEN.h | 19 +- .../periph/PERI_NOC_M_E_0_WR_I_MAIN_QOSGEN.h | 19 +- .../PERI_NOC_M_E_0_WR_I_MAIN_TRANSTATFILT.h | 19 +- .../periph/PERI_NOC_M_E_1A_RD_I_MAIN_QOSGEN.h | 19 +- .../periph/PERI_NOC_M_E_1A_WR_I_MAIN_QOSGEN.h | 19 +- .../periph/PERI_NOC_M_E_1B_RD_I_MAIN_QOSGEN.h | 19 +- .../periph/PERI_NOC_M_E_1B_WR_I_MAIN_QOSGEN.h | 19 +- .../periph/PERI_NOC_M_E_3_RD_I_MAIN_QOSGEN.h | 19 +- .../PERI_NOC_M_E_3_RD_I_MAIN_TRANSTATFILT.h | 19 +- .../periph/PERI_NOC_M_E_3_WR_I_MAIN_QOSGEN.h | 19 +- .../periph/PERI_NOC_M_E_6_RD_I_MAIN_QOSGEN.h | 19 +- .../PERI_NOC_M_E_6_RD_I_MAIN_TRANSTATFILT.h | 19 +- .../periph/PERI_NOC_M_E_6_WR_I_MAIN_QOSGEN.h | 19 +- .../PERI_NOC_M_E_6_WR_I_MAIN_TRANSTATFILT.h | 19 +- .../periph/PERI_NOC_M_E_7_RD_I_MAIN_QOSGEN.h | 19 +- .../PERI_NOC_M_E_7_RD_I_MAIN_TRANSTATFILT.h | 19 +- .../periph/PERI_NOC_M_E_7_WR_I_MAIN_QOSGEN.h | 19 +- .../PERI_NOC_M_E_7_WR_I_MAIN_TRANSTATFILT.h | 19 +- .../periph/PERI_NOC_M_E_9_RD_I_MAIN_QOSGEN.h | 19 +- .../periph/PERI_NOC_M_E_9_WR_I_MAIN_QOSGEN.h | 19 +- .../PERI_NOC_M_E_9_WR_I_MAIN_TRANSTATFILT.h | 19 +- .../PERI_NOC_PROBE_LCDIF_RD_MAIN_PROBE.h | 19 +- .../PERI_NOC_PROBE_LCDIF_RD_MAIN_TRSTPROF.h | 19 +- .../periph/PERI_NOC_PROBE_M_E_0_MAIN_PROBE.h | 19 +- .../PERI_NOC_PROBE_M_E_0_MAIN_TRANSTATPROF.h | 19 +- .../periph/PERI_NOC_PROBE_M_E_3_MAIN_PROBE.h | 19 +- .../PERI_NOC_PROBE_M_E_3_MAIN_TRANSTATPROF.h | 19 +- .../periph/PERI_NOC_PROBE_M_E_6_MAIN_PROBE.h | 19 +- .../PERI_NOC_PROBE_M_E_6_MAIN_TRANSTATPROF.h | 19 +- .../periph/PERI_NOC_PROBE_M_E_7_MAIN_PROBE.h | 19 +- .../PERI_NOC_PROBE_M_E_7_MAIN_TRANSTATPROF.h | 19 +- .../periph/PERI_NOC_PROBE_M_E_9_MAIN_PROBE.h | 19 +- .../PERI_NOC_PROBE_M_E_9_MAIN_TRANSTATPROF.h | 19 +- .../periph/PERI_NOC_PROBE_PXP_RD_MAIN_PROBE.h | 19 +- .../PERI_NOC_PROBE_PXP_RD_MAIN_TRSTPROF.h | 19 +- .../periph/PERI_NOC_PROBE_PXP_WR_MAIN_PROBE.h | 19 +- .../PERI_NOC_PROBE_PXP_WR_MAIN_TRSTPROF.h | 19 +- .../i.MX/i.MX943/periph/PERI_NOC_TCU.h | 19 +- .../i.MX/i.MX943/periph/PERI_NOC_TRDC_MGR.h | 19 +- .../i.MX/i.MX943/periph/PERI_NPU_EIM.h | 19 +- .../i.MX/i.MX943/periph/PERI_NPU_ERM.h | 19 +- .../i.MX/i.MX943/periph/PERI_NPU_LSTCU.h | 19 +- .../i.MX/i.MX943/periph/PERI_NPU_TCU.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_OSC24M.h | 19 +- .../i.MX/i.MX943/periph/PERI_PCIE_DMA_IATU.h | 19 +- .../i.MX/i.MX943/periph/PERI_PCIE_EP.h | 19 +- .../i.MX/i.MX943/periph/PERI_PCIE_RC.h | 19 +- .../i.MX/i.MX943/periph/PERI_PCIE_SHADOW_EP.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_PDM.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_PLL.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_PWM.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_PXP.h | 2517 ++++++++- .../devices/i.MX/i.MX943/periph/PERI_RGPIO.h | 151 +- .../devices/i.MX/i.MX943/periph/PERI_S3MU.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_SEMA42.h | 19 +- .../i.MX/i.MX943/periph/PERI_SERDES_SS.h | 27 +- .../devices/i.MX/i.MX943/periph/PERI_SINC.h | 171 +- .../i.MX/i.MX943/periph/PERI_SRAMCTL.h | 19 +- .../i.MX/i.MX943/periph/PERI_SRC_GEN.h | 19 +- .../i.MX/i.MX943/periph/PERI_SRC_MEM.h | 19 +- .../i.MX/i.MX943/periph/PERI_SRC_XSPR.h | 19 +- .../i.MX/i.MX943/periph/PERI_SW_GLOBAL.h | 19 +- .../i.MX/i.MX943/periph/PERI_SW_PORT.h | 19 +- .../i.MX943/periph/PERI_SW_PSEUDO_MAC_PORT.h | 19 +- .../i.MX943/periph/PERI_SYS_CTR_COMPARE.h | 19 +- .../i.MX943/periph/PERI_SYS_CTR_CONTROL.h | 19 +- .../i.MX/i.MX943/periph/PERI_SYS_CTR_READ.h | 19 +- .../i.MX/i.MX943/periph/PERI_TCM_ECC_MCM.h | 35 +- .../devices/i.MX/i.MX943/periph/PERI_TMPSNS.h | 29 +- .../devices/i.MX/i.MX943/periph/PERI_TMR.h | 19 +- .../i.MX/i.MX943/periph/PERI_TMR_GLOBAL.h | 19 +- .../i.MX943/periph/PERI_TMR_PCI_HDR_TYPE0.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_TPM.h | 19 +- .../i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP1.h | 19 +- .../i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP2.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_TSTMR.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_USB.h | 79 +- .../i.MX/i.MX943/periph/PERI_USB3_GLUE.h | 19 +- .../i.MX/i.MX943/periph/PERI_USB3_PHY_TCA.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_USBNC.h | 19 +- .../i.MX/i.MX943/periph/PERI_WAKEUP_ATU.h | 19 +- .../i.MX/i.MX943/periph/PERI_WAKEUP_CMU.h | 19 +- .../i.MX/i.MX943/periph/PERI_WAKEUP_DMA_CRC.h | 19 +- .../i.MX/i.MX943/periph/PERI_WAKEUP_EIM.h | 19 +- .../i.MX/i.MX943/periph/PERI_WAKEUP_ERM.h | 19 +- .../i.MX/i.MX943/periph/PERI_WAKEUP_TCW.h | 19 +- .../periph/PERI_WAKEUP_TRDC_MGR_MEGA.h | 19 +- .../i.MX/i.MX943/periph/PERI_WAKEUP_USDHC.h | 19 +- .../periph/PERI_WAKEUP_XSPI_RESPONDER.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_WDOG.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_XBAR1.h | 1114 +--- .../devices/i.MX/i.MX943/periph/PERI_XBAR2.h | 1114 +--- .../devices/i.MX/i.MX943/periph/PERI_XBAR3.h | 1114 +--- .../devices/i.MX/i.MX943/periph/PERI_XCACHE.h | 19 +- .../devices/i.MX/i.MX943/periph/PERI_XSPI.h | 353 +- .../i.MX95/MIMX9506/MIMX9506_cm7_features.h | 104 +- .../i.MX95/MIMX9534/MIMX9534_cm7_features.h | 104 +- .../i.MX95/MIMX9536/MIMX9536_cm7_features.h | 104 +- .../i.MX95/MIMX9546/MIMX9546_cm7_features.h | 104 +- .../i.MX95/MIMX9554/MIMX9554_cm7_features.h | 104 +- .../i.MX95/MIMX9556/MIMX9556_cm7_features.h | 104 +- .../i.MX95/MIMX9574/MIMX9574_cm7_features.h | 104 +- .../i.MX95/MIMX9576/MIMX9576_cm7_features.h | 104 +- .../i.MX95/MIMX9586/MIMX9586_cm7_features.h | 104 +- .../i.MX95/MIMX9594/MIMX9594_cm7_features.h | 104 +- .../i.MX95/MIMX9596/MIMX9596_cm7_features.h | 104 +- .../i.MX95/MIMX95N4/MIMX95N4_cm7_features.h | 104 +- .../i.MX95/MIMX95N6/MIMX95N6_cm7_features.h | 104 +- .../i.MX/i.MX95/periph/PERI_USB3_CORE.h | 1 - 404 files changed, 20173 insertions(+), 9089 deletions(-) create mode 100644 mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDRC.h diff --git a/mcux/mcux-sdk-ng/devices/i.MX/SBOM.spdx.json b/mcux/mcux-sdk-ng/devices/i.MX/SBOM.spdx.json index fda536726..57dda742f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/SBOM.spdx.json +++ b/mcux/mcux-sdk-ng/devices/i.MX/SBOM.spdx.json @@ -2,20 +2,20 @@ "SPDXID": "SPDXRef-DOCUMENT", "spdxVersion": "SPDX-2.3", "creationInfo": { - "created": "2025-05-21T04:06:01Z", + "created": "2025-08-04T04:45:24Z", "creators": [ "Organization: NXP" ], "licenseListVersion": "3.20" }, - "name": "mcux-devices-imx-v25.06.00", + "name": "mcux-devices-imx-v25.09.00-pvw2", "dataLicense": "CC0-1.0", - "documentNamespace": "https://nxp.com/spdx/5136603d-0922-4812-ace1-32762b1d045f", + "documentNamespace": "https://nxp.com/spdx/2c41a390-427d-4443-91f6-3266cf2e40a2", "packages": [ { - "SPDXID": "SPDXRef-package-5136603d-0922-4812-ace1-32762b1d045f", + "SPDXID": "SPDXRef-package-2c41a390-427d-4443-91f6-3266cf2e40a2", "name": "mcux-devices-imx", - "versionInfo": "v25.06.00", + "versionInfo": "v25.09.00-pvw2", "licenseConcluded": "(BSD-3-Clause)", "licenseDeclared": "(BSD-3-Clause)", "downloadLocation": "https://github.com/nxp-mcuxpresso/mcux-devices-imx", @@ -29,7 +29,7 @@ { "spdxElementId": "SPDXRef-DOCUMENT", "relationshipType": "DESCRIBES", - "relatedSpdxElement": "SPDXRef-package-5136603d-0922-4812-ace1-32762b1d045f" + "relatedSpdxElement": "SPDXRef-package-2c41a390-427d-4443-91f6-3266cf2e40a2" } ] } \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX7ULP/MCIMX7U3/MCIMX7U3_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX7ULP/MCIMX7U3/MCIMX7U3_cm4_features.h index 1416c9c51..fdbfe4825 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX7ULP/MCIMX7U3/MCIMX7U3_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX7ULP/MCIMX7U3/MCIMX7U3_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 7.0, 2018-11-05 -** Build: b250512 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -235,8 +235,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -249,6 +247,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* CRC module features */ @@ -307,8 +307,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -337,6 +335,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -353,8 +353,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -385,14 +383,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -726,16 +728,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ - (((x) == LPUART0) ? (4) : \ - (((x) == LPUART1) ? (4) : \ - (((x) == LPUART2) ? (8) : \ - (((x) == LPUART3) ? (8) : \ - (((x) == LPUART4) ? (8) : \ - (((x) == LPUART5) ? (8) : \ - (((x) == LPUART6) ? (8) : \ - (((x) == LPUART7) ? (8) : (-1))))))))) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -778,6 +770,18 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART0) ? (4) : \ + (((x) == LPUART1) ? (4) : \ + (((x) == LPUART2) ? (8) : \ + (((x) == LPUART3) ? (8) : \ + (((x) == LPUART4) ? (8) : \ + (((x) == LPUART5) ? (8) : \ + (((x) == LPUART6) ? (8) : \ + (((x) == LPUART7) ? (8) : (-1))))))))) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -1449,15 +1453,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : (-1))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -1473,15 +1469,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : (-1))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ @@ -1523,6 +1511,33 @@ /* @brief USBPHY is 28FDSOI */ #define FSL_FEATURE_USBPHY_28FDSOI (0) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX7ULP/MCIMX7U5/MCIMX7U5_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX7ULP/MCIMX7U5/MCIMX7U5_cm4_features.h index 85b6c8644..8b4382104 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX7ULP/MCIMX7U5/MCIMX7U5_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX7ULP/MCIMX7U5/MCIMX7U5_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 7.0, 2018-11-05 -** Build: b250512 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -235,8 +235,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -249,6 +247,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* CRC module features */ @@ -307,8 +307,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -337,6 +335,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -353,8 +353,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -385,14 +383,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -726,16 +728,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ - (((x) == LPUART0) ? (4) : \ - (((x) == LPUART1) ? (4) : \ - (((x) == LPUART2) ? (8) : \ - (((x) == LPUART3) ? (8) : \ - (((x) == LPUART4) ? (8) : \ - (((x) == LPUART5) ? (8) : \ - (((x) == LPUART6) ? (8) : \ - (((x) == LPUART7) ? (8) : (-1))))))))) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -778,6 +770,18 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART0) ? (4) : \ + (((x) == LPUART1) ? (4) : \ + (((x) == LPUART2) ? (8) : \ + (((x) == LPUART3) ? (8) : \ + (((x) == LPUART4) ? (8) : \ + (((x) == LPUART5) ? (8) : \ + (((x) == LPUART6) ? (8) : \ + (((x) == LPUART7) ? (8) : (-1))))))))) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -1449,15 +1453,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : (-1))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -1473,15 +1469,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : (-1))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ @@ -1523,6 +1511,33 @@ /* @brief USBPHY is 28FDSOI */ #define FSL_FEATURE_USBPHY_28FDSOI (0) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/MIMX8MD6_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/MIMX8MD6_cm4_COMMON.h index a6fe536f5..9ffe1c7b0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/MIMX8MD6_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/MIMX8MD6_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MD6_cm4 @@ -423,15 +423,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/MIMX8MD6_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/MIMX8MD6_cm4_features.h index 41636e792..0300879bc 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/MIMX8MD6_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/MIMX8MD6_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2018-01-26 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -148,13 +148,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -178,8 +178,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -214,16 +212,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ -#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ @@ -396,6 +396,11 @@ (((x) == SPBA1) ? (0x308FFFFF) : \ (((x) == SPBA2) ? (0x300FFFFF) : (-1))) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SysTick module features */ /* @brief Systick has external reference clock. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/system_MIMX8MD6_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/system_MIMX8MD6_cm4.c index f9fe5b193..6f9a414b5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/system_MIMX8MD6_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD6/system_MIMX8MD6_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/MIMX8MD7_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/MIMX8MD7_cm4_COMMON.h index 1fa2c83ed..8b65d4d4e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/MIMX8MD7_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/MIMX8MD7_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MD7_cm4 @@ -423,15 +423,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/MIMX8MD7_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/MIMX8MD7_cm4_features.h index 63e0e41ae..066b7ae40 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/MIMX8MD7_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/MIMX8MD7_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2018-01-26 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -148,13 +148,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -178,8 +178,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -214,16 +212,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ -#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ @@ -396,6 +396,11 @@ (((x) == SPBA1) ? (0x308FFFFF) : \ (((x) == SPBA2) ? (0x300FFFFF) : (-1))) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SysTick module features */ /* @brief Systick has external reference clock. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/system_MIMX8MD7_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/system_MIMX8MD7_cm4.c index 52d52ab8a..34bd050be 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/system_MIMX8MD7_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MD7/system_MIMX8MD7_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_COMMON.h index 10f66ae7d..10efec3d2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MQ5_cm4 @@ -423,15 +423,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_features.h index d593ddcc5..7fbe84c72 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/MIMX8MQ5_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2018-01-26 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -148,13 +148,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -178,8 +178,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -214,16 +212,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ -#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ @@ -396,6 +396,11 @@ (((x) == SPBA1) ? (0x308FFFFF) : \ (((x) == SPBA2) ? (0x300FFFFF) : (-1))) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SysTick module features */ /* @brief Systick has external reference clock. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/system_MIMX8MQ5_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/system_MIMX8MQ5_cm4.c index 8611cfad6..6f70e6123 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/system_MIMX8MQ5_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ5/system_MIMX8MQ5_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_COMMON.h index f063c7ed1..a785d1bd9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MQ6_cm4 @@ -423,15 +423,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_features.h index f8856ea6d..a0eee15ac 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/MIMX8MQ6_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2018-01-26 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -148,13 +148,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -178,8 +178,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -214,16 +212,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ -#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ @@ -396,6 +396,11 @@ (((x) == SPBA1) ? (0x308FFFFF) : \ (((x) == SPBA2) ? (0x300FFFFF) : (-1))) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SysTick module features */ /* @brief Systick has external reference clock. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/system_MIMX8MQ6_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/system_MIMX8MQ6_cm4.c index be8c260d0..dd53d2f4c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/system_MIMX8MQ6_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ6/system_MIMX8MQ6_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_COMMON.h index d6e9e9f85..0afe0158f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MQ7_cm4 @@ -423,15 +423,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_features.h index a598c3fd6..96ba81615 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/MIMX8MQ7_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2018-01-26 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -148,13 +148,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -178,8 +178,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -214,16 +212,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ -#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ @@ -396,6 +396,11 @@ (((x) == SPBA1) ? (0x308FFFFF) : \ (((x) == SPBA2) ? (0x300FFFFF) : (-1))) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SysTick module features */ /* @brief Systick has external reference clock. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/system_MIMX8MQ7_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/system_MIMX8MQ7_cm4.c index 5f03250d3..d3aec2aba 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/system_MIMX8MQ7_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/MIMX8MQ7/system_MIMX8MQ7_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/periph/PERI_ENET.h index 3713e5f9c..3c07e30ca 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8M/periph/PERI_ENET.h @@ -22,7 +22,7 @@ ** MIMX8MQ7DVAJZ_cm4 ** ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET @@ -2148,9 +2148,6 @@ typedef struct { * @} */ /* end of group ENET_Register_Masks */ -/* ENET Buffer Descriptor and Buffer Address Alignment. */ -#define ENET_BUFF_ALIGNMENT (64U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_COMMON.h index d618aa59c..5ab2d19f8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MX8MMRM, Rev. 0, 02/2019 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MM1_cm4 @@ -457,25 +457,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_features.h index 6afd2b8b4..03eae1663 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/MIMX8MM1_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2019-02-18 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -150,13 +150,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -180,8 +180,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -210,15 +208,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/system_MIMX8MM1_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/system_MIMX8MM1_cm4.c index 74d8ab914..9fd25d13e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/system_MIMX8MM1_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM1/system_MIMX8MM1_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_COMMON.h index 2411e83a1..3d2cfd1ce 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MX8MMRM, Rev. 0, 02/2019 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MM2_cm4 @@ -457,25 +457,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_features.h index 0190d8741..73e2cc288 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/MIMX8MM2_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2019-02-18 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -150,13 +150,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -180,8 +180,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -210,15 +208,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/system_MIMX8MM2_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/system_MIMX8MM2_cm4.c index a7c770ae8..78165fcd4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/system_MIMX8MM2_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM2/system_MIMX8MM2_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_COMMON.h index 7b71b8463..dd4359768 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MX8MMRM, Rev. 0, 02/2019 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MM3_cm4 @@ -457,25 +457,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_features.h index 1be37c7f8..354bdad88 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/MIMX8MM3_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2019-02-18 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -150,13 +150,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -180,8 +180,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -210,15 +208,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/system_MIMX8MM3_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/system_MIMX8MM3_cm4.c index 7fe5dbba1..bb6abbdae 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/system_MIMX8MM3_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM3/system_MIMX8MM3_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_COMMON.h index a44197766..81fe52667 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MX8MMRM, Rev. 0, 02/2019 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MM4_cm4 @@ -457,25 +457,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_features.h index 30ddaa64d..87be271e3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/MIMX8MM4_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2019-02-18 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -150,13 +150,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -180,8 +180,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -210,15 +208,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/system_MIMX8MM4_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/system_MIMX8MM4_cm4.c index c0c4db658..2a8b374ec 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/system_MIMX8MM4_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM4/system_MIMX8MM4_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_COMMON.h index c1e0cdab8..ef19cbe90 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MX8MMRM, Rev. 0, 02/2019 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MM5_cm4 @@ -457,25 +457,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_features.h index b85067561..799f67e9e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/MIMX8MM5_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2019-02-18 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -150,13 +150,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -180,8 +180,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -210,15 +208,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/system_MIMX8MM5_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/system_MIMX8MM5_cm4.c index ae7da2532..ebdc8bf14 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/system_MIMX8MM5_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM5/system_MIMX8MM5_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_COMMON.h index 281a8d116..1baaff394 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MX8MMRM, Rev. 0, 02/2019 ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MM6_cm4 @@ -457,25 +457,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_features.h index 62d842fa6..5a7ef963c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/MIMX8MM6_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2019-02-18 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -150,13 +150,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -180,8 +180,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -210,15 +208,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* LMEM module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/drivers/fsl_clock.h index 108ca7a26..876aa99c5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/drivers/fsl_clock.h @@ -51,9 +51,9 @@ } /*! @brief Clock ip name array for ENET. */ -#define ENET_CLOCKS \ - { \ - kCLOCK_Enet1, \ +#define ENET_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enet1, \ } /*! @brief Clock ip name array for GPIO. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/system_MIMX8MM6_cm4.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/system_MIMX8MM6_cm4.c index 537aad18b..d855856c6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/system_MIMX8MM6_cm4.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/MIMX8MM6/system_MIMX8MM6_cm4.c @@ -64,6 +64,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/periph/PERI_ENET.h index d782ea079..2432a1830 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/periph/PERI_ENET.h @@ -26,7 +26,7 @@ ** MIMX8MM6DVTLZ_cm4 ** ** Version: rev. 5.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET @@ -2156,9 +2156,6 @@ typedef struct { * @} */ /* end of group ENET_Register_Masks */ -/* ENET Buffer Descriptor and Buffer Address Alignment. */ -#define ENET_BUFF_ALIGNMENT (64U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/periph/PERI_FLEXSPI.h index bd7b21703..1e1bbf9aa 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MM/periph/PERI_FLEXSPI.h @@ -29,7 +29,7 @@ ** Build: b250521 ** ** Abstract: -** CMSIS Peripheral Access Layer for FlexSPI +** CMSIS Peripheral Access Layer for FLEXSPI ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2025 NXP @@ -58,9 +58,9 @@ * @file PERI_FLEXSPI.h * @version 5.0 * @date 2024-10-29 - * @brief CMSIS Peripheral Access Layer for FlexSPI + * @brief CMSIS Peripheral Access Layer for FLEXSPI * - * CMSIS Peripheral Access Layer for FlexSPI + * CMSIS Peripheral Access Layer for FLEXSPI */ #if !defined(PERI_FLEXSPI_H_) @@ -124,25 +124,25 @@ #endif /* ---------------------------------------------------------------------------- - -- FlexSPI Peripheral Access Layer + -- FLEXSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup FlexSPI_Peripheral_Access_Layer FlexSPI Peripheral Access Layer + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer * @{ */ -/** FlexSPI - Size of Registers Arrays */ -#define FlexSPI_AHBRXBUFXCR0_COUNT 8u -#define FlexSPI_FLSHXCR0_COUNT 4u -#define FlexSPI_FLSHXCR1_COUNT 4u -#define FlexSPI_FLSHXCR2_COUNT 4u -#define FlexSPI_DLLXCR_COUNT 2u -#define FlexSPI_RFDR_COUNT 32u -#define FlexSPI_TFDR_COUNT 32u -#define FlexSPI_LUT_COUNT 128u - -/** FlexSPI - Register Layout Typedef */ +/** FLEXSPI - Size of Registers Arrays */ +#define FLEXSPI_AHBRXBUFXCR0_COUNT 8u +#define FLEXSPI_FLSHXCR0_COUNT 4u +#define FLEXSPI_FLSHXCR1_COUNT 4u +#define FLEXSPI_FLSHXCR2_COUNT 4u +#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_RFDR_COUNT 32u +#define FLEXSPI_TFDR_COUNT 32u +#define FLEXSPI_LUT_COUNT 128u + +/** FLEXSPI - Register Layout Typedef */ typedef struct { __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ @@ -152,11 +152,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FlexSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; - __IO uint32_t FLSHCR0[FlexSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FlexSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FlexSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -167,7 +167,7 @@ typedef struct { __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */ __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FlexSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -176,61 +176,61 @@ typedef struct { __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ uint8_t RESERVED_5[8]; - __I uint32_t RFDR[FlexSPI_RFDR_COUNT]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ - __O uint32_t TFDR[FlexSPI_TFDR_COUNT]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ - __IO uint32_t LUT[FlexSPI_LUT_COUNT]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */ -} FlexSPI_Type; + __I uint32_t RFDR[FLEXSPI_RFDR_COUNT]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[FLEXSPI_TFDR_COUNT]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[FLEXSPI_LUT_COUNT]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */ +} FLEXSPI_Type; /* ---------------------------------------------------------------------------- - -- FlexSPI Register Masks + -- FLEXSPI Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup FlexSPI_Register_Masks FlexSPI Register Masks + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks * @{ */ /*! @name MCR0 - Module Control Register 0 */ /*! @{ */ -#define FlexSPI_MCR0_SWRESET_MASK (0x1U) -#define FlexSPI_MCR0_SWRESET_SHIFT (0U) +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) /*! SWRESET - Software Reset */ -#define FlexSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SWRESET_SHIFT)) & FlexSPI_MCR0_SWRESET_MASK) +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) -#define FlexSPI_MCR0_MDIS_MASK (0x2U) -#define FlexSPI_MCR0_MDIS_SHIFT (1U) +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) /*! MDIS - Module Disable */ -#define FlexSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_MDIS_SHIFT)) & FlexSPI_MCR0_MDIS_MASK) +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) -#define FlexSPI_MCR0_RXCLKSRC_MASK (0x30U) -#define FlexSPI_MCR0_RXCLKSRC_SHIFT (4U) +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) /*! RXCLKSRC - Sample Clock source selection for Flash Reading * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. * 0b10..Reserved * 0b11..Flash provided Read strobe and input from DQS pad */ -#define FlexSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_RXCLKSRC_SHIFT)) & FlexSPI_MCR0_RXCLKSRC_MASK) +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) -#define FlexSPI_MCR0_ARDFEN_MASK (0x40U) -#define FlexSPI_MCR0_ARDFEN_SHIFT (6U) +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. */ -#define FlexSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ARDFEN_SHIFT)) & FlexSPI_MCR0_ARDFEN_MASK) +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) -#define FlexSPI_MCR0_ATDFEN_MASK (0x80U) -#define FlexSPI_MCR0_ATDFEN_SHIFT (7U) +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. */ -#define FlexSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ATDFEN_SHIFT)) & FlexSPI_MCR0_ATDFEN_MASK) +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) -#define FlexSPI_MCR0_SERCLKDIV_MASK (0x700U) -#define FlexSPI_MCR0_SERCLKDIV_SHIFT (8U) +#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) +#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. * 0b000..Divided by 1 * 0b001..Divided by 2 @@ -241,80 +241,80 @@ typedef struct { * 0b110..Divided by 7 * 0b111..Divided by 8 */ -#define FlexSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SERCLKDIV_SHIFT)) & FlexSPI_MCR0_SERCLKDIV_MASK) +#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) -#define FlexSPI_MCR0_HSEN_MASK (0x800U) -#define FlexSPI_MCR0_HSEN_SHIFT (11U) +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) /*! HSEN - Half Speed Serial Flash access Enable. * 0b0..Disable divide by 2 of serial flash clock for half speed commands. * 0b1..Enable divide by 2 of serial flash clock for half speed commands. */ -#define FlexSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_HSEN_SHIFT)) & FlexSPI_MCR0_HSEN_MASK) +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) -#define FlexSPI_MCR0_DOZEEN_MASK (0x1000U) -#define FlexSPI_MCR0_DOZEEN_SHIFT (12U) +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) /*! DOZEEN - Doze mode enable bit * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. */ -#define FlexSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_DOZEEN_SHIFT)) & FlexSPI_MCR0_DOZEEN_MASK) +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) -#define FlexSPI_MCR0_COMBINATIONEN_MASK (0x2000U) -#define FlexSPI_MCR0_COMBINATIONEN_SHIFT (13U) +#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) +#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) /*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]). * 0b0..Disable. * 0b1..Enable. */ -#define FlexSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_COMBINATIONEN_SHIFT)) & FlexSPI_MCR0_COMBINATIONEN_MASK) +#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) -#define FlexSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) -#define FlexSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). * 0b0..Disable. * 0b1..Enable. */ -#define FlexSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SCKFREERUNEN_SHIFT)) & FlexSPI_MCR0_SCKFREERUNEN_MASK) +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) -#define FlexSPI_MCR0_LEARNEN_MASK (0x8000U) -#define FlexSPI_MCR0_LEARNEN_SHIFT (15U) +#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) +#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) /*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is * disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction * is correctly executed. * 0b0..Disable. * 0b1..Enable. */ -#define FlexSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_LEARNEN_SHIFT)) & FlexSPI_MCR0_LEARNEN_MASK) +#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) -#define FlexSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) -#define FlexSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) /*! IPGRANTWAIT - Time out wait cycle for IP command grant. */ -#define FlexSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_IPGRANTWAIT_SHIFT)) & FlexSPI_MCR0_IPGRANTWAIT_MASK) +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) -#define FlexSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) -#define FlexSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) /*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. */ -#define FlexSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FlexSPI_MCR0_AHBGRANTWAIT_MASK) +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) /*! @} */ /*! @name MCR1 - Module Control Register 1 */ /*! @{ */ -#define FlexSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) -#define FlexSPI_MCR1_AHBBUSWAIT_SHIFT (0U) -#define FlexSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR1_AHBBUSWAIT_SHIFT)) & FlexSPI_MCR1_AHBBUSWAIT_MASK) +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) -#define FlexSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) -#define FlexSPI_MCR1_SEQWAIT_SHIFT (16U) -#define FlexSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR1_SEQWAIT_SHIFT)) & FlexSPI_MCR1_SEQWAIT_MASK) +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) /*! @} */ /*! @name MCR2 - Module Control Register 2 */ /*! @{ */ -#define FlexSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) -#define FlexSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned * automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP @@ -322,17 +322,17 @@ typedef struct { * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. */ -#define FlexSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FlexSPI_MCR2_CLRAHBBUFOPT_MASK) +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) -#define FlexSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) -#define FlexSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) /*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is * written with 0x1. This bit will be auto-cleared immediately. */ -#define FlexSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FlexSPI_MCR2_CLRLEARNPHASE_MASK) +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) -#define FlexSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) -#define FlexSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash * A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, @@ -340,45 +340,45 @@ typedef struct { * ignored. * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. */ -#define FlexSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FlexSPI_MCR2_SAMEDEVICEEN_MASK) +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) -#define FlexSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) -#define FlexSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to * A_SCLK). In this case, port B flash access is not available. After changing the value of this * field, MCR0[SWRESET] should be set. - * 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. * 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available. + * 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. */ -#define FlexSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FlexSPI_MCR2_SCKBDIFFOPT_MASK) +#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) -#define FlexSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) -#define FlexSPI_MCR2_RESUMEWAIT_SHIFT (24U) +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) /*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. */ -#define FlexSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_RESUMEWAIT_SHIFT)) & FlexSPI_MCR2_RESUMEWAIT_MASK) +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) /*! @} */ /*! @name AHBCR - AHB Bus Control Register */ /*! @{ */ -#define FlexSPI_AHBCR_APAREN_MASK (0x1U) -#define FlexSPI_AHBCR_APAREN_SHIFT (0U) +#define FLEXSPI_AHBCR_APAREN_MASK (0x1U) +#define FLEXSPI_AHBCR_APAREN_SHIFT (0U) /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . * 0b0..Flash will be accessed in Individual mode. * 0b1..Flash will be accessed in Parallel mode. */ -#define FlexSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_APAREN_SHIFT)) & FlexSPI_AHBCR_APAREN_MASK) +#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) -#define FlexSPI_AHBCR_CACHABLEEN_MASK (0x8U) -#define FlexSPI_AHBCR_CACHABLEEN_SHIFT (3U) +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) /*! CACHABLEEN - Enable AHB bus cachable read access support. * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. */ -#define FlexSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_CACHABLEEN_SHIFT)) & FlexSPI_AHBCR_CACHABLEEN_MASK) +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) -#define FlexSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) -#define FlexSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat * of AHB write access, refer for more details about AHB bufferable write. * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus @@ -386,292 +386,292 @@ typedef struct { * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is * granted by arbitrator and will not wait for AHB command finished. */ -#define FlexSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FlexSPI_AHBCR_BUFFERABLEEN_MASK) +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) -#define FlexSPI_AHBCR_PREFETCHEN_MASK (0x20U) -#define FlexSPI_AHBCR_PREFETCHEN_SHIFT (5U) +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) /*! PREFETCHEN - AHB Read Prefetch Enable. */ -#define FlexSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_PREFETCHEN_SHIFT)) & FlexSPI_AHBCR_PREFETCHEN_MASK) +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) -#define FlexSPI_AHBCR_READADDROPT_MASK (0x40U) -#define FlexSPI_AHBCR_READADDROPT_SHIFT (6U) +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB * burst required to meet the alignment requirement. */ -#define FlexSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_READADDROPT_SHIFT)) & FlexSPI_AHBCR_READADDROPT_MASK) +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable Register */ /*! @{ */ -#define FlexSPI_INTEN_IPCMDDONEEN_MASK (0x1U) -#define FlexSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) /*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. */ -#define FlexSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDDONEEN_SHIFT)) & FlexSPI_INTEN_IPCMDDONEEN_MASK) +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) -#define FlexSPI_INTEN_IPCMDGEEN_MASK (0x2U) -#define FlexSPI_INTEN_IPCMDGEEN_SHIFT (1U) +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) /*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. */ -#define FlexSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDGEEN_SHIFT)) & FlexSPI_INTEN_IPCMDGEEN_MASK) +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) -#define FlexSPI_INTEN_AHBCMDGEEN_MASK (0x4U) -#define FlexSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) /*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. */ -#define FlexSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBCMDGEEN_SHIFT)) & FlexSPI_INTEN_AHBCMDGEEN_MASK) +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) -#define FlexSPI_INTEN_IPCMDERREN_MASK (0x8U) -#define FlexSPI_INTEN_IPCMDERREN_SHIFT (3U) +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) /*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. */ -#define FlexSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDERREN_SHIFT)) & FlexSPI_INTEN_IPCMDERREN_MASK) +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) -#define FlexSPI_INTEN_AHBCMDERREN_MASK (0x10U) -#define FlexSPI_INTEN_AHBCMDERREN_SHIFT (4U) +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) /*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. */ -#define FlexSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBCMDERREN_SHIFT)) & FlexSPI_INTEN_AHBCMDERREN_MASK) +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) -#define FlexSPI_INTEN_IPRXWAEN_MASK (0x20U) -#define FlexSPI_INTEN_IPRXWAEN_SHIFT (5U) +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) /*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. */ -#define FlexSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPRXWAEN_SHIFT)) & FlexSPI_INTEN_IPRXWAEN_MASK) +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) -#define FlexSPI_INTEN_IPTXWEEN_MASK (0x40U) -#define FlexSPI_INTEN_IPTXWEEN_SHIFT (6U) +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) /*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. */ -#define FlexSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPTXWEEN_SHIFT)) & FlexSPI_INTEN_IPTXWEEN_MASK) +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) -#define FlexSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) -#define FlexSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) +#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) +#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) /*! DATALEARNFAILEN - Data Learning failed interrupt enable. */ -#define FlexSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FlexSPI_INTEN_DATALEARNFAILEN_MASK) +#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) -#define FlexSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) -#define FlexSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) /*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. */ -#define FlexSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FlexSPI_INTEN_SCKSTOPBYRDEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) -#define FlexSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) -#define FlexSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) /*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. */ -#define FlexSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FlexSPI_INTEN_SCKSTOPBYWREN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) -#define FlexSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) -#define FlexSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) /*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. */ -#define FlexSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FlexSPI_INTEN_AHBBUSTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) -#define FlexSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) -#define FlexSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) /*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. */ -#define FlexSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FlexSPI_INTEN_SEQTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) /*! @} */ /*! @name INTR - Interrupt Register */ /*! @{ */ -#define FlexSPI_INTR_IPCMDDONE_MASK (0x1U) -#define FlexSPI_INTR_IPCMDDONE_SHIFT (0U) +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) /*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also * generated when there is IPCMDGE or IPCMDERR interrupt generated. */ -#define FlexSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDDONE_SHIFT)) & FlexSPI_INTR_IPCMDDONE_MASK) +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) -#define FlexSPI_INTR_IPCMDGE_MASK (0x2U) -#define FlexSPI_INTR_IPCMDGE_SHIFT (1U) +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) /*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. */ -#define FlexSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDGE_SHIFT)) & FlexSPI_INTR_IPCMDGE_MASK) +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) -#define FlexSPI_INTR_AHBCMDGE_MASK (0x4U) -#define FlexSPI_INTR_AHBCMDGE_SHIFT (2U) +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) /*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. */ -#define FlexSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBCMDGE_SHIFT)) & FlexSPI_INTR_AHBCMDGE_MASK) +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) -#define FlexSPI_INTR_IPCMDERR_MASK (0x8U) -#define FlexSPI_INTR_IPCMDERR_SHIFT (3U) +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) /*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for * IP command, this command will be ignored and not executed at all. */ -#define FlexSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDERR_SHIFT)) & FlexSPI_INTR_IPCMDERR_MASK) +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) -#define FlexSPI_INTR_AHBCMDERR_MASK (0x10U) -#define FlexSPI_INTR_AHBCMDERR_SHIFT (4U) +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) /*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for * AHB command, this command will be ignored and not executed at all. */ -#define FlexSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBCMDERR_SHIFT)) & FlexSPI_INTR_AHBCMDERR_MASK) +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) -#define FlexSPI_INTR_IPRXWA_MASK (0x20U) -#define FlexSPI_INTR_IPRXWA_SHIFT (5U) +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) /*! IPRXWA - IP RX FIFO watermark available interrupt. */ -#define FlexSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPRXWA_SHIFT)) & FlexSPI_INTR_IPRXWA_MASK) +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) -#define FlexSPI_INTR_IPTXWE_MASK (0x40U) -#define FlexSPI_INTR_IPTXWE_SHIFT (6U) +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) /*! IPTXWE - IP TX FIFO watermark empty interrupt. */ -#define FlexSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPTXWE_SHIFT)) & FlexSPI_INTR_IPTXWE_MASK) +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) -#define FlexSPI_INTR_DATALEARNFAIL_MASK (0x80U) -#define FlexSPI_INTR_DATALEARNFAIL_SHIFT (7U) +#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) +#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) /*! DATALEARNFAIL - Data Learning failed interrupt. */ -#define FlexSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_DATALEARNFAIL_SHIFT)) & FlexSPI_INTR_DATALEARNFAIL_MASK) +#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) -#define FlexSPI_INTR_SCKSTOPBYRD_MASK (0x100U) -#define FlexSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) /*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt. */ -#define FlexSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SCKSTOPBYRD_SHIFT)) & FlexSPI_INTR_SCKSTOPBYRD_MASK) +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) -#define FlexSPI_INTR_SCKSTOPBYWR_MASK (0x200U) -#define FlexSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) /*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt. */ -#define FlexSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SCKSTOPBYWR_SHIFT)) & FlexSPI_INTR_SCKSTOPBYWR_MASK) +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) -#define FlexSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) -#define FlexSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) /*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. */ -#define FlexSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FlexSPI_INTR_AHBBUSTIMEOUT_MASK) +#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) -#define FlexSPI_INTR_SEQTIMEOUT_MASK (0x800U) -#define FlexSPI_INTR_SEQTIMEOUT_SHIFT (11U) +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) /*! SEQTIMEOUT - Sequence execution timeout interrupt. */ -#define FlexSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SEQTIMEOUT_SHIFT)) & FlexSPI_INTR_SEQTIMEOUT_MASK) +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) /*! @} */ /*! @name LUTKEY - LUT Key Register */ /*! @{ */ -#define FlexSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) -#define FlexSPI_LUTKEY_KEY_SHIFT (0U) +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) /*! KEY - The Key to lock or unlock LUT. */ -#define FlexSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTKEY_KEY_SHIFT)) & FlexSPI_LUTKEY_KEY_MASK) +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) /*! @} */ /*! @name LUTCR - LUT Control Register */ /*! @{ */ -#define FlexSPI_LUTCR_LOCK_MASK (0x1U) -#define FlexSPI_LUTCR_LOCK_SHIFT (0U) +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) /*! LOCK - Lock LUT */ -#define FlexSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTCR_LOCK_SHIFT)) & FlexSPI_LUTCR_LOCK_MASK) +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) -#define FlexSPI_LUTCR_UNLOCK_MASK (0x2U) -#define FlexSPI_LUTCR_UNLOCK_SHIFT (1U) +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) /*! UNLOCK - Unlock LUT */ -#define FlexSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTCR_UNLOCK_SHIFT)) & FlexSPI_LUTCR_UNLOCK_MASK) +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) /*! @} */ /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */ /*! @{ */ -#define FlexSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) -#define FlexSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) /*! BUFSZ - AHB RX Buffer Size in 64 bits. */ -#define FlexSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FlexSPI_AHBRXBUFCR0_BUFSZ_MASK) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) -#define FlexSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) -#define FlexSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) /*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). */ -#define FlexSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FlexSPI_AHBRXBUFCR0_MSTRID_MASK) +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) -#define FlexSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) -#define FlexSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) /*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. */ -#define FlexSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FlexSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) -#define FlexSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) -#define FlexSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) /*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. */ -#define FlexSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FlexSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FlexSPI_AHBRXBUFCR0 */ -#define FlexSPI_AHBRXBUFCR0_COUNT (8U) +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ -#define FlexSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) -#define FlexSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) /*! FLSHSZ - Flash Size in KByte. */ -#define FlexSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR0_FLSHSZ_SHIFT)) & FlexSPI_FLSHCR0_FLSHSZ_MASK) +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ -/* The count of FlexSPI_FLSHCR0 */ -#define FlexSPI_FLSHCR0_COUNT (4U) +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ -#define FlexSPI_FLSHCR1_TCSS_MASK (0x1FU) -#define FlexSPI_FLSHCR1_TCSS_SHIFT (0U) +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) /*! TCSS - Serial Flash CS setup time. */ -#define FlexSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_TCSS_SHIFT)) & FlexSPI_FLSHCR1_TCSS_MASK) +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) -#define FlexSPI_FLSHCR1_TCSH_MASK (0x3E0U) -#define FlexSPI_FLSHCR1_TCSH_SHIFT (5U) +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) /*! TCSH - Serial Flash CS Hold time. */ -#define FlexSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_TCSH_SHIFT)) & FlexSPI_FLSHCR1_TCSH_MASK) +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) -#define FlexSPI_FLSHCR1_WA_MASK (0x400U) -#define FlexSPI_FLSHCR1_WA_SHIFT (10U) +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) /*! WA - Word Addressable. */ -#define FlexSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_WA_SHIFT)) & FlexSPI_FLSHCR1_WA_MASK) +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) -#define FlexSPI_FLSHCR1_CAS_MASK (0x7800U) -#define FlexSPI_FLSHCR1_CAS_SHIFT (11U) +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) /*! CAS - Column Address Size. */ -#define FlexSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CAS_SHIFT)) & FlexSPI_FLSHCR1_CAS_MASK) +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) -#define FlexSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) -#define FlexSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) /*! CSINTERVALUNIT - CS interval unit * 0b0..The CS interval unit is 1 serial clock cycle * 0b1..The CS interval unit is 256 serial clock cycle */ -#define FlexSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FlexSPI_FLSHCR1_CSINTERVALUNIT_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) -#define FlexSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) -#define FlexSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) /*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection * deassertion and flash device Chip selection assertion. If external flash has a limitation on * the interval between command sequences, this field should be set accordingly. If there is no * limitation, set this field with value 0x0. */ -#define FlexSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FlexSPI_FLSHCR1_CSINTERVAL_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FlexSPI_FLSHCR1 */ -#define FlexSPI_FLSHCR1_COUNT (4U) +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ -#define FlexSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) -#define FlexSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) /*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. */ -#define FlexSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_ARDSEQID_SHIFT)) & FlexSPI_FLSHCR2_ARDSEQID_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) -#define FlexSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) -#define FlexSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) /*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. */ -#define FlexSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FlexSPI_FLSHCR2_ARDSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) -#define FlexSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) -#define FlexSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) /*! AWRSEQID - Sequence Index for AHB Write triggered Command. */ -#define FlexSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRSEQID_SHIFT)) & FlexSPI_FLSHCR2_AWRSEQID_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) -#define FlexSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) -#define FlexSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) /*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. */ -#define FlexSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FlexSPI_FLSHCR2_AWRSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) -#define FlexSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) -#define FlexSPI_FLSHCR2_AWRWAIT_SHIFT (16U) -#define FlexSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRWAIT_SHIFT)) & FlexSPI_FLSHCR2_AWRWAIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) -#define FlexSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) -#define FlexSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) /*! AWRWAITUNIT - AWRWAIT unit * 0b000..The AWRWAIT unit is 2 ahb clock cycle * 0b001..The AWRWAIT unit is 8 ahb clock cycle @@ -682,206 +682,206 @@ typedef struct { * 0b110..The AWRWAIT unit is 8192 ahb clock cycle * 0b111..The AWRWAIT unit is 32768 ahb clock cycle */ -#define FlexSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FlexSPI_FLSHCR2_AWRWAITUNIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) -#define FlexSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) -#define FlexSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. * Refer Programmable Sequence Engine for details. */ -#define FlexSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FlexSPI_FLSHCR2_CLRINSTRPTR_MASK) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FlexSPI_FLSHCR2 */ -#define FlexSPI_FLSHCR2_COUNT (4U) +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ -#define FlexSPI_FLSHCR4_WMOPT1_MASK (0x1U) -#define FlexSPI_FLSHCR4_WMOPT1_SHIFT (0U) +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write * burst start address alignment when flash is accessed in individual mode. * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write * burst start address alignment when flash is accessed in individual mode. */ -#define FlexSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMOPT1_SHIFT)) & FlexSPI_FLSHCR4_WMOPT1_MASK) +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) -#define FlexSPI_FLSHCR4_WMENA_MASK (0x4U) -#define FlexSPI_FLSHCR4_WMENA_SHIFT (2U) +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for * memory device on port A, this bit must be set. * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ -#define FlexSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMENA_SHIFT)) & FlexSPI_FLSHCR4_WMENA_MASK) +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) -#define FlexSPI_FLSHCR4_WMENB_MASK (0x8U) -#define FlexSPI_FLSHCR4_WMENB_SHIFT (3U) +#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) +#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for * memory device on port B, this bit must be set. * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ -#define FlexSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMENB_SHIFT)) & FlexSPI_FLSHCR4_WMENB_MASK) +#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) /*! @} */ /*! @name IPCR0 - IP Control Register 0 */ /*! @{ */ -#define FlexSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) -#define FlexSPI_IPCR0_SFAR_SHIFT (0U) +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) /*! SFAR - Serial Flash Address for IP command. */ -#define FlexSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR0_SFAR_SHIFT)) & FlexSPI_IPCR0_SFAR_MASK) +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) /*! @} */ /*! @name IPCR1 - IP Control Register 1 */ /*! @{ */ -#define FlexSPI_IPCR1_IDATSZ_MASK (0xFFFFU) -#define FlexSPI_IPCR1_IDATSZ_SHIFT (0U) +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) /*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. */ -#define FlexSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_IDATSZ_SHIFT)) & FlexSPI_IPCR1_IDATSZ_MASK) +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) -#define FlexSPI_IPCR1_ISEQID_MASK (0x1F0000U) -#define FlexSPI_IPCR1_ISEQID_SHIFT (16U) +#define FLEXSPI_IPCR1_ISEQID_MASK (0x1F0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) /*! ISEQID - Sequence Index in LUT for IP command. */ -#define FlexSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_ISEQID_SHIFT)) & FlexSPI_IPCR1_ISEQID_MASK) +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) -#define FlexSPI_IPCR1_ISEQNUM_MASK (0x7000000U) -#define FlexSPI_IPCR1_ISEQNUM_SHIFT (24U) +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */ -#define FlexSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_ISEQNUM_SHIFT)) & FlexSPI_IPCR1_ISEQNUM_MASK) +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) -#define FlexSPI_IPCR1_IPAREN_MASK (0x80000000U) -#define FlexSPI_IPCR1_IPAREN_SHIFT (31U) +#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) +#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) /*! IPAREN - Parallel mode Enabled for IP command. * 0b0..Flash will be accessed in Individual mode. * 0b1..Flash will be accessed in Parallel mode. */ -#define FlexSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_IPAREN_SHIFT)) & FlexSPI_IPCR1_IPAREN_MASK) +#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) /*! @} */ /*! @name IPCMD - IP Command Register */ /*! @{ */ -#define FlexSPI_IPCMD_TRG_MASK (0x1U) -#define FlexSPI_IPCMD_TRG_SHIFT (0U) +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) /*! TRG - Setting this bit will trigger an IP Command. */ -#define FlexSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCMD_TRG_SHIFT)) & FlexSPI_IPCMD_TRG_MASK) +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) /*! @} */ /*! @name DLPR - Data Learn Pattern Register */ /*! @{ */ -#define FlexSPI_DLPR_DLP_MASK (0xFFFFFFFFU) -#define FlexSPI_DLPR_DLP_SHIFT (0U) +#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) +#define FLEXSPI_DLPR_DLP_SHIFT (0U) /*! DLP - Data Learning Pattern. */ -#define FlexSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLPR_DLP_SHIFT)) & FlexSPI_DLPR_DLP_MASK) +#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) /*! @} */ /*! @name IPRXFCR - IP RX FIFO Control Register */ /*! @{ */ -#define FlexSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) -#define FlexSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) /*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. */ -#define FlexSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FlexSPI_IPRXFCR_CLRIPRXF_MASK) +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) -#define FlexSPI_IPRXFCR_RXDMAEN_MASK (0x2U) -#define FlexSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) /*! RXDMAEN - IP RX FIFO reading by DMA enabled. * 0b0..IP RX FIFO would be read by processor. * 0b1..IP RX FIFO would be read by DMA. */ -#define FlexSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_RXDMAEN_SHIFT)) & FlexSPI_IPRXFCR_RXDMAEN_MASK) +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) -#define FlexSPI_IPRXFCR_RXWMRK_MASK (0xFCU) -#define FlexSPI_IPRXFCR_RXWMRK_SHIFT (2U) +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0xFCU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) /*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. */ -#define FlexSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_RXWMRK_SHIFT)) & FlexSPI_IPRXFCR_RXWMRK_MASK) +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) /*! @} */ /*! @name IPTXFCR - IP TX FIFO Control Register */ /*! @{ */ -#define FlexSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) -#define FlexSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) /*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. */ -#define FlexSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FlexSPI_IPTXFCR_CLRIPTXF_MASK) +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) -#define FlexSPI_IPTXFCR_TXDMAEN_MASK (0x2U) -#define FlexSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) /*! TXDMAEN - IP TX FIFO filling by DMA enabled. * 0b0..IP TX FIFO would be filled by processor. * 0b1..IP TX FIFO would be filled by DMA. */ -#define FlexSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_TXDMAEN_SHIFT)) & FlexSPI_IPTXFCR_TXDMAEN_MASK) +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) -#define FlexSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) -#define FlexSPI_IPTXFCR_TXWMRK_SHIFT (2U) +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) /*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. */ -#define FlexSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_TXWMRK_SHIFT)) & FlexSPI_IPTXFCR_TXWMRK_MASK) +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) /*! @} */ /*! @name DLLCR - DLL Control Register 0 */ /*! @{ */ -#define FlexSPI_DLLCR_DLLEN_MASK (0x1U) -#define FlexSPI_DLLCR_DLLEN_SHIFT (0U) +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) /*! DLLEN - DLL calibration enable. */ -#define FlexSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_DLLEN_SHIFT)) & FlexSPI_DLLCR_DLLEN_MASK) +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) -#define FlexSPI_DLLCR_DLLRESET_MASK (0x2U) -#define FlexSPI_DLLCR_DLLRESET_SHIFT (1U) +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) /*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the * DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset * action is edge triggered, so software need to clear this bit after set this bit (no delay * limitation). */ -#define FlexSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_DLLRESET_SHIFT)) & FlexSPI_DLLCR_DLLRESET_MASK) +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) -#define FlexSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) -#define FlexSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) /*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). */ -#define FlexSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FlexSPI_DLLCR_SLVDLYTARGET_MASK) +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) -#define FlexSPI_DLLCR_OVRDEN_MASK (0x100U) -#define FlexSPI_DLLCR_OVRDEN_SHIFT (8U) +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) /*! OVRDEN - Slave clock delay line delay cell number selection override enable. */ -#define FlexSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_OVRDEN_SHIFT)) & FlexSPI_DLLCR_OVRDEN_MASK) +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) -#define FlexSPI_DLLCR_OVRDVAL_MASK (0x7E00U) -#define FlexSPI_DLLCR_OVRDVAL_SHIFT (9U) +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) /*! OVRDVAL - Slave clock delay line delay cell number selection override value. */ -#define FlexSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_OVRDVAL_SHIFT)) & FlexSPI_DLLCR_OVRDVAL_MASK) +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FlexSPI_DLLCR */ -#define FlexSPI_DLLCR_COUNT (2U) +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) /*! @name STS0 - Status Register 0 */ /*! @{ */ -#define FlexSPI_STS0_SEQIDLE_MASK (0x1U) -#define FlexSPI_STS0_SEQIDLE_SHIFT (0U) +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) /*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command * sequence executing on FlexSPI interface. */ -#define FlexSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_SEQIDLE_SHIFT)) & FlexSPI_STS0_SEQIDLE_MASK) +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) -#define FlexSPI_STS0_ARBIDLE_MASK (0x2U) -#define FlexSPI_STS0_ARBIDLE_SHIFT (1U) +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) /*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command * sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state * (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So * this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. */ -#define FlexSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_ARBIDLE_SHIFT)) & FlexSPI_STS0_ARBIDLE_MASK) +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) -#define FlexSPI_STS0_ARBCMDSRC_MASK (0xCU) -#define FlexSPI_STS0_ARBCMDSRC_SHIFT (2U) +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). * 0b00..Triggered by AHB read command (triggered by AHB read). @@ -889,31 +889,31 @@ typedef struct { * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). * 0b11..Triggered by suspended command (resumed). */ -#define FlexSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_ARBCMDSRC_SHIFT)) & FlexSPI_STS0_ARBCMDSRC_MASK) +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) -#define FlexSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) -#define FlexSPI_STS0_DATALEARNPHASEA_SHIFT (4U) +#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) +#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) /*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning. */ -#define FlexSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_DATALEARNPHASEA_SHIFT)) & FlexSPI_STS0_DATALEARNPHASEA_MASK) +#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) -#define FlexSPI_STS0_DATALEARNPHASEB_MASK (0xF00U) -#define FlexSPI_STS0_DATALEARNPHASEB_SHIFT (8U) +#define FLEXSPI_STS0_DATALEARNPHASEB_MASK (0xF00U) +#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT (8U) /*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning. */ -#define FlexSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_DATALEARNPHASEB_SHIFT)) & FlexSPI_STS0_DATALEARNPHASEB_MASK) +#define FLEXSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK) /*! @} */ /*! @name STS1 - Status Register 1 */ /*! @{ */ -#define FlexSPI_STS1_AHBCMDERRID_MASK (0x1FU) -#define FlexSPI_STS1_AHBCMDERRID_SHIFT (0U) +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0x1FU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) /*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field * will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). */ -#define FlexSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_AHBCMDERRID_SHIFT)) & FlexSPI_STS1_AHBCMDERRID_MASK) +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) -#define FlexSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) -#define FlexSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be * cleared when INTR[AHBCMDERR] is write-1-clear(w1c). * 0b0000..No error. @@ -923,17 +923,17 @@ typedef struct { * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. * 0b1110..Sequence execution timeout. */ -#define FlexSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_AHBCMDERRCODE_SHIFT)) & FlexSPI_STS1_AHBCMDERRCODE_MASK) +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) -#define FlexSPI_STS1_IPCMDERRID_MASK (0x1F0000U) -#define FlexSPI_STS1_IPCMDERRID_SHIFT (16U) +#define FLEXSPI_STS1_IPCMDERRID_MASK (0x1F0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) /*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be * cleared when INTR[IPCMDERR] is write-1-clear(w1c). */ -#define FlexSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_IPCMDERRID_SHIFT)) & FlexSPI_STS1_IPCMDERRID_MASK) +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) -#define FlexSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) -#define FlexSPI_STS1_IPCMDERRCODE_SHIFT (24U) +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be * cleared when INTR[IPCMDERR] is write-1-clear(w1c). * 0b0000..No error. @@ -945,161 +945,161 @@ typedef struct { * 0b1110..Sequence execution timeout. * 0b1111..Flash boundary crossed. */ -#define FlexSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_IPCMDERRCODE_SHIFT)) & FlexSPI_STS1_IPCMDERRCODE_MASK) +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) /*! @} */ /*! @name STS2 - Status Register 2 */ /*! @{ */ -#define FlexSPI_STS2_ASLVLOCK_MASK (0x1U) -#define FlexSPI_STS2_ASLVLOCK_SHIFT (0U) +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) /*! ASLVLOCK - Flash A sample clock slave delay line locked. */ -#define FlexSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_ASLVLOCK_SHIFT)) & FlexSPI_STS2_ASLVLOCK_MASK) +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) -#define FlexSPI_STS2_AREFLOCK_MASK (0x2U) -#define FlexSPI_STS2_AREFLOCK_SHIFT (1U) +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) /*! AREFLOCK - Flash A sample clock reference delay line locked. */ -#define FlexSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_AREFLOCK_SHIFT)) & FlexSPI_STS2_AREFLOCK_MASK) +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) -#define FlexSPI_STS2_ASLVSEL_MASK (0xFCU) -#define FlexSPI_STS2_ASLVSEL_SHIFT (2U) +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) /*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . */ -#define FlexSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_ASLVSEL_SHIFT)) & FlexSPI_STS2_ASLVSEL_MASK) +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) -#define FlexSPI_STS2_AREFSEL_MASK (0x3F00U) -#define FlexSPI_STS2_AREFSEL_SHIFT (8U) +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) /*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. */ -#define FlexSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_AREFSEL_SHIFT)) & FlexSPI_STS2_AREFSEL_MASK) +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) -#define FlexSPI_STS2_BSLVLOCK_MASK (0x10000U) -#define FlexSPI_STS2_BSLVLOCK_SHIFT (16U) +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) /*! BSLVLOCK - Flash B sample clock slave delay line locked. */ -#define FlexSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BSLVLOCK_SHIFT)) & FlexSPI_STS2_BSLVLOCK_MASK) +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) -#define FlexSPI_STS2_BREFLOCK_MASK (0x20000U) -#define FlexSPI_STS2_BREFLOCK_SHIFT (17U) +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) /*! BREFLOCK - Flash B sample clock reference delay line locked. */ -#define FlexSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BREFLOCK_SHIFT)) & FlexSPI_STS2_BREFLOCK_MASK) +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) -#define FlexSPI_STS2_BSLVSEL_MASK (0xFC0000U) -#define FlexSPI_STS2_BSLVSEL_SHIFT (18U) +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) /*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection. */ -#define FlexSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BSLVSEL_SHIFT)) & FlexSPI_STS2_BSLVSEL_MASK) +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) -#define FlexSPI_STS2_BREFSEL_MASK (0x3F000000U) -#define FlexSPI_STS2_BREFSEL_SHIFT (24U) +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) /*! BREFSEL - Flash B sample clock reference delay line delay cell number selection. */ -#define FlexSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BREFSEL_SHIFT)) & FlexSPI_STS2_BREFSEL_MASK) +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) /*! @} */ /*! @name AHBSPNDSTS - AHB Suspend Status Register */ /*! @{ */ -#define FlexSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) -#define FlexSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) /*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. */ -#define FlexSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FlexSPI_AHBSPNDSTS_ACTIVE_MASK) +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) -#define FlexSPI_AHBSPNDSTS_BUFID_MASK (0xEU) -#define FlexSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) /*! BUFID - AHB RX BUF ID for suspended command sequence. */ -#define FlexSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_BUFID_SHIFT)) & FlexSPI_AHBSPNDSTS_BUFID_MASK) +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) -#define FlexSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) -#define FlexSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) /*! DATLFT - Left Data size for suspended command sequence (in byte). */ -#define FlexSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FlexSPI_AHBSPNDSTS_DATLFT_MASK) +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) /*! @} */ /*! @name IPRXFSTS - IP RX FIFO Status Register */ /*! @{ */ -#define FlexSPI_IPRXFSTS_FILL_MASK (0xFFU) -#define FlexSPI_IPRXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) /*! FILL - Fill level of IP RX FIFO. */ -#define FlexSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFSTS_FILL_SHIFT)) & FlexSPI_IPRXFSTS_FILL_MASK) +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) -#define FlexSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) -#define FlexSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) /*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. */ -#define FlexSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFSTS_RDCNTR_SHIFT)) & FlexSPI_IPRXFSTS_RDCNTR_MASK) +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) /*! @} */ /*! @name IPTXFSTS - IP TX FIFO Status Register */ /*! @{ */ -#define FlexSPI_IPTXFSTS_FILL_MASK (0xFFU) -#define FlexSPI_IPTXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) /*! FILL - Fill level of IP TX FIFO. */ -#define FlexSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFSTS_FILL_SHIFT)) & FlexSPI_IPTXFSTS_FILL_MASK) +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) -#define FlexSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) -#define FlexSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) /*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. */ -#define FlexSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFSTS_WRCNTR_SHIFT)) & FlexSPI_IPTXFSTS_WRCNTR_MASK) +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) /*! @} */ /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ /*! @{ */ -#define FlexSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) -#define FlexSPI_RFDR_RXDATA_SHIFT (0U) +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) /*! RXDATA - RX Data */ -#define FlexSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_RFDR_RXDATA_SHIFT)) & FlexSPI_RFDR_RXDATA_MASK) +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) /*! @} */ /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ /*! @{ */ -#define FlexSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) -#define FlexSPI_TFDR_TXDATA_SHIFT (0U) +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) /*! TXDATA - TX Data */ -#define FlexSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_TFDR_TXDATA_SHIFT)) & FlexSPI_TFDR_TXDATA_MASK) +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) /*! @} */ /*! @name LUT - LUT 0..LUT 127 */ /*! @{ */ -#define FlexSPI_LUT_OPERAND0_MASK (0xFFU) -#define FlexSPI_LUT_OPERAND0_SHIFT (0U) +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) /*! OPERAND0 - OPERAND0 */ -#define FlexSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPERAND0_SHIFT)) & FlexSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) -#define FlexSPI_LUT_NUM_PADS0_MASK (0x300U) -#define FlexSPI_LUT_NUM_PADS0_SHIFT (8U) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) /*! NUM_PADS0 - NUM_PADS0 */ -#define FlexSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_NUM_PADS0_SHIFT)) & FlexSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) -#define FlexSPI_LUT_OPCODE0_MASK (0xFC00U) -#define FlexSPI_LUT_OPCODE0_SHIFT (10U) +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) /*! OPCODE0 - OPCODE */ -#define FlexSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPCODE0_SHIFT)) & FlexSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) -#define FlexSPI_LUT_OPERAND1_MASK (0xFF0000U) -#define FlexSPI_LUT_OPERAND1_SHIFT (16U) +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) /*! OPERAND1 - OPERAND1 */ -#define FlexSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPERAND1_SHIFT)) & FlexSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) -#define FlexSPI_LUT_NUM_PADS1_MASK (0x3000000U) -#define FlexSPI_LUT_NUM_PADS1_SHIFT (24U) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) /*! NUM_PADS1 - NUM_PADS1 */ -#define FlexSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_NUM_PADS1_SHIFT)) & FlexSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) -#define FlexSPI_LUT_OPCODE1_MASK (0xFC000000U) -#define FlexSPI_LUT_OPCODE1_SHIFT (26U) +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) /*! OPCODE1 - OPCODE1 */ -#define FlexSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPCODE1_SHIFT)) & FlexSPI_LUT_OPCODE1_MASK) +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) /*! @} */ /*! * @} - */ /* end of group FlexSPI_Register_Masks */ + */ /* end of group FLEXSPI_Register_Masks */ /*! * @} - */ /* end of group FlexSPI_Peripheral_Access_Layer */ + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ /* diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_COMMON.h index d26351063..0cb9ceb74 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MX8MNRM, Rev.B, 07/2019 ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MN1_cm7 @@ -458,25 +458,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_features.h index d6c5e3064..985798f54 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/MIMX8MN1_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2019-09-23 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -142,13 +142,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -172,8 +172,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -202,15 +200,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/system_MIMX8MN1_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/system_MIMX8MN1_cm7.c index d28def96c..d4227e007 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/system_MIMX8MN1_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN1/system_MIMX8MN1_cm7.c @@ -58,6 +58,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_COMMON.h index 977232546..d5cfd34f1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MX8MNRM, Rev.B, 07/2019 ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MN2_cm7 @@ -456,25 +456,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_features.h index af2e30764..8462d4814 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/MIMX8MN2_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2019-09-23 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -142,13 +142,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -172,8 +172,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -202,15 +200,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/system_MIMX8MN2_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/system_MIMX8MN2_cm7.c index ff2a2fa24..9ccfb9fd2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/system_MIMX8MN2_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN2/system_MIMX8MN2_cm7.c @@ -56,6 +56,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_COMMON.h index 10b8a2936..1117a7ca4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MX8MNRM, Rev.B, 07/2019 ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MN3_cm7 @@ -458,25 +458,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_features.h index e18fc0315..590e641fa 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/MIMX8MN3_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2019-09-23 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -142,13 +142,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -172,8 +172,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -202,15 +200,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/system_MIMX8MN3_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/system_MIMX8MN3_cm7.c index 08f266d59..f4e79edc4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/system_MIMX8MN3_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN3/system_MIMX8MN3_cm7.c @@ -58,6 +58,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_COMMON.h index d905c160c..583309a30 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MX8MNRM, Rev.B, 07/2019 ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MN4_cm7 @@ -456,25 +456,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_features.h index 42347ccb2..35790371b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/MIMX8MN4_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2019-09-23 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -142,13 +142,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -172,8 +172,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -202,15 +200,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/system_MIMX8MN4_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/system_MIMX8MN4_cm7.c index 86ed9756f..1e3cfaa80 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/system_MIMX8MN4_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN4/system_MIMX8MN4_cm7.c @@ -56,6 +56,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_COMMON.h index 2b6efd506..0938487f6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MX8MNRM, Rev.B, 07/2019 ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MN5_cm7 @@ -458,25 +458,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_features.h index 332e2680f..c993b9f34 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/MIMX8MN5_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2019-09-23 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -142,13 +142,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -172,8 +172,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -202,15 +200,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/system_MIMX8MN5_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/system_MIMX8MN5_cm7.c index 1d1572a12..a11a40e57 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/system_MIMX8MN5_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN5/system_MIMX8MN5_cm7.c @@ -58,6 +58,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_COMMON.h index b09aa9192..cc01c12fe 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MX8MNRM, Rev.B, 07/2019 ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MN6_cm7 @@ -456,25 +456,28 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) -/* FlexSPI - Peripheral instance base addresses */ + +/* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FlexSPI peripheral base addresses */ -#define FlexSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FlexSPI peripheral base pointers */ -#define FlexSPI_BASE_PTRS { FLEXSPI } +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_features.h index 19433f8aa..580ad320a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/MIMX8MN6_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2019-09-23 -** Build: b250506 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -142,13 +142,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* GPC module features */ @@ -172,8 +172,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -202,15 +200,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/drivers/fsl_clock.h index 93c11eacd..1f910a3d0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/drivers/fsl_clock.h @@ -51,9 +51,9 @@ } /*! @brief Clock ip name array for ENET. */ -#define ENET_CLOCKS \ - { \ - kCLOCK_Enet1, \ +#define ENET_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enet1, \ } /*! @brief Clock ip name array for GPIO. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/system_MIMX8MN6_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/system_MIMX8MN6_cm7.c index 3450d7dc7..059dad20a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/system_MIMX8MN6_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/MIMX8MN6/system_MIMX8MN6_cm7.c @@ -56,6 +56,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/periph/PERI_ENET.h index 0e833124b..665a6de6d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/periph/PERI_ENET.h @@ -38,7 +38,7 @@ ** MIMX8MN6DVTJZ_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET @@ -2164,9 +2164,6 @@ typedef struct { * @} */ /* end of group ENET_Register_Masks */ -/* ENET Buffer Descriptor and Buffer Address Alignment. */ -#define ENET_BUFF_ALIGNMENT (64U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/periph/PERI_FLEXSPI.h index 3ba86935a..570a85eb5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MN/periph/PERI_FLEXSPI.h @@ -38,10 +38,10 @@ ** MIMX8MN6DVTJZ_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: -** CMSIS Peripheral Access Layer for FlexSPI +** CMSIS Peripheral Access Layer for FLEXSPI ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2025 NXP @@ -66,9 +66,9 @@ * @file PERI_FLEXSPI.h * @version 3.0 * @date 2024-10-29 - * @brief CMSIS Peripheral Access Layer for FlexSPI + * @brief CMSIS Peripheral Access Layer for FLEXSPI * - * CMSIS Peripheral Access Layer for FlexSPI + * CMSIS Peripheral Access Layer for FLEXSPI */ #if !defined(PERI_FLEXSPI_H_) @@ -132,25 +132,25 @@ #endif /* ---------------------------------------------------------------------------- - -- FlexSPI Peripheral Access Layer + -- FLEXSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup FlexSPI_Peripheral_Access_Layer FlexSPI Peripheral Access Layer + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer * @{ */ -/** FlexSPI - Size of Registers Arrays */ -#define FlexSPI_AHBRXBUFXCR0_COUNT 8u -#define FlexSPI_FLSHXCR0_COUNT 4u -#define FlexSPI_FLSHXCR1_COUNT 4u -#define FlexSPI_FLSHXCR2_COUNT 4u -#define FlexSPI_DLLXCR_COUNT 2u -#define FlexSPI_RFDR_COUNT 32u -#define FlexSPI_TFDR_COUNT 32u -#define FlexSPI_LUT_COUNT 128u - -/** FlexSPI - Register Layout Typedef */ +/** FLEXSPI - Size of Registers Arrays */ +#define FLEXSPI_AHBRXBUFXCR0_COUNT 8u +#define FLEXSPI_FLSHXCR0_COUNT 4u +#define FLEXSPI_FLSHXCR1_COUNT 4u +#define FLEXSPI_FLSHXCR2_COUNT 4u +#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_RFDR_COUNT 32u +#define FLEXSPI_TFDR_COUNT 32u +#define FLEXSPI_LUT_COUNT 128u + +/** FLEXSPI - Register Layout Typedef */ typedef struct { __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ @@ -160,11 +160,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FlexSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; - __IO uint32_t FLSHCR0[FlexSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FlexSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FlexSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -175,7 +175,7 @@ typedef struct { __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */ __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FlexSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -184,61 +184,61 @@ typedef struct { __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ uint8_t RESERVED_5[8]; - __I uint32_t RFDR[FlexSPI_RFDR_COUNT]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ - __O uint32_t TFDR[FlexSPI_TFDR_COUNT]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ - __IO uint32_t LUT[FlexSPI_LUT_COUNT]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */ -} FlexSPI_Type; + __I uint32_t RFDR[FLEXSPI_RFDR_COUNT]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[FLEXSPI_TFDR_COUNT]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[FLEXSPI_LUT_COUNT]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */ +} FLEXSPI_Type; /* ---------------------------------------------------------------------------- - -- FlexSPI Register Masks + -- FLEXSPI Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup FlexSPI_Register_Masks FlexSPI Register Masks + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks * @{ */ /*! @name MCR0 - Module Control Register 0 */ /*! @{ */ -#define FlexSPI_MCR0_SWRESET_MASK (0x1U) -#define FlexSPI_MCR0_SWRESET_SHIFT (0U) +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) /*! SWRESET - Software Reset */ -#define FlexSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SWRESET_SHIFT)) & FlexSPI_MCR0_SWRESET_MASK) +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) -#define FlexSPI_MCR0_MDIS_MASK (0x2U) -#define FlexSPI_MCR0_MDIS_SHIFT (1U) +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) /*! MDIS - Module Disable */ -#define FlexSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_MDIS_SHIFT)) & FlexSPI_MCR0_MDIS_MASK) +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) -#define FlexSPI_MCR0_RXCLKSRC_MASK (0x30U) -#define FlexSPI_MCR0_RXCLKSRC_SHIFT (4U) +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) /*! RXCLKSRC - Sample Clock source selection for Flash Reading * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. * 0b10..Reserved * 0b11..Flash provided Read strobe and input from DQS pad */ -#define FlexSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_RXCLKSRC_SHIFT)) & FlexSPI_MCR0_RXCLKSRC_MASK) +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) -#define FlexSPI_MCR0_ARDFEN_MASK (0x40U) -#define FlexSPI_MCR0_ARDFEN_SHIFT (6U) +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. */ -#define FlexSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ARDFEN_SHIFT)) & FlexSPI_MCR0_ARDFEN_MASK) +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) -#define FlexSPI_MCR0_ATDFEN_MASK (0x80U) -#define FlexSPI_MCR0_ATDFEN_SHIFT (7U) +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. */ -#define FlexSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ATDFEN_SHIFT)) & FlexSPI_MCR0_ATDFEN_MASK) +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) -#define FlexSPI_MCR0_SERCLKDIV_MASK (0x700U) -#define FlexSPI_MCR0_SERCLKDIV_SHIFT (8U) +#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) +#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. * 0b000..Divided by 1 * 0b001..Divided by 2 @@ -249,80 +249,80 @@ typedef struct { * 0b110..Divided by 7 * 0b111..Divided by 8 */ -#define FlexSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SERCLKDIV_SHIFT)) & FlexSPI_MCR0_SERCLKDIV_MASK) +#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) -#define FlexSPI_MCR0_HSEN_MASK (0x800U) -#define FlexSPI_MCR0_HSEN_SHIFT (11U) +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) /*! HSEN - Half Speed Serial Flash access Enable. * 0b0..Disable divide by 2 of serial flash clock for half speed commands. * 0b1..Enable divide by 2 of serial flash clock for half speed commands. */ -#define FlexSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_HSEN_SHIFT)) & FlexSPI_MCR0_HSEN_MASK) +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) -#define FlexSPI_MCR0_DOZEEN_MASK (0x1000U) -#define FlexSPI_MCR0_DOZEEN_SHIFT (12U) +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) /*! DOZEEN - Doze mode enable bit * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. */ -#define FlexSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_DOZEEN_SHIFT)) & FlexSPI_MCR0_DOZEEN_MASK) +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) -#define FlexSPI_MCR0_COMBINATIONEN_MASK (0x2000U) -#define FlexSPI_MCR0_COMBINATIONEN_SHIFT (13U) +#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) +#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) /*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]). * 0b0..Disable. * 0b1..Enable. */ -#define FlexSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_COMBINATIONEN_SHIFT)) & FlexSPI_MCR0_COMBINATIONEN_MASK) +#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) -#define FlexSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) -#define FlexSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). * 0b0..Disable. * 0b1..Enable. */ -#define FlexSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SCKFREERUNEN_SHIFT)) & FlexSPI_MCR0_SCKFREERUNEN_MASK) +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) -#define FlexSPI_MCR0_LEARNEN_MASK (0x8000U) -#define FlexSPI_MCR0_LEARNEN_SHIFT (15U) +#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) +#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) /*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is * disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction * is correctly executed. * 0b0..Disable. * 0b1..Enable. */ -#define FlexSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_LEARNEN_SHIFT)) & FlexSPI_MCR0_LEARNEN_MASK) +#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) -#define FlexSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) -#define FlexSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) /*! IPGRANTWAIT - Time out wait cycle for IP command grant. */ -#define FlexSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_IPGRANTWAIT_SHIFT)) & FlexSPI_MCR0_IPGRANTWAIT_MASK) +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) -#define FlexSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) -#define FlexSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) /*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. */ -#define FlexSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FlexSPI_MCR0_AHBGRANTWAIT_MASK) +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) /*! @} */ /*! @name MCR1 - Module Control Register 1 */ /*! @{ */ -#define FlexSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) -#define FlexSPI_MCR1_AHBBUSWAIT_SHIFT (0U) -#define FlexSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR1_AHBBUSWAIT_SHIFT)) & FlexSPI_MCR1_AHBBUSWAIT_MASK) +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) -#define FlexSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) -#define FlexSPI_MCR1_SEQWAIT_SHIFT (16U) -#define FlexSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR1_SEQWAIT_SHIFT)) & FlexSPI_MCR1_SEQWAIT_MASK) +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) /*! @} */ /*! @name MCR2 - Module Control Register 2 */ /*! @{ */ -#define FlexSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) -#define FlexSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned * automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP @@ -330,17 +330,17 @@ typedef struct { * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. */ -#define FlexSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FlexSPI_MCR2_CLRAHBBUFOPT_MASK) +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) -#define FlexSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) -#define FlexSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) /*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is * written with 0x1. This bit will be auto-cleared immediately. */ -#define FlexSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FlexSPI_MCR2_CLRLEARNPHASE_MASK) +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) -#define FlexSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) -#define FlexSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash * A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, @@ -348,45 +348,45 @@ typedef struct { * ignored. * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. */ -#define FlexSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FlexSPI_MCR2_SAMEDEVICEEN_MASK) +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) -#define FlexSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) -#define FlexSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to * A_SCLK). In this case, port B flash access is not available. After changing the value of this * field, MCR0[SWRESET] should be set. - * 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. * 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available. + * 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. */ -#define FlexSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FlexSPI_MCR2_SCKBDIFFOPT_MASK) +#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) -#define FlexSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) -#define FlexSPI_MCR2_RESUMEWAIT_SHIFT (24U) +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) /*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. */ -#define FlexSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_RESUMEWAIT_SHIFT)) & FlexSPI_MCR2_RESUMEWAIT_MASK) +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) /*! @} */ /*! @name AHBCR - AHB Bus Control Register */ /*! @{ */ -#define FlexSPI_AHBCR_APAREN_MASK (0x1U) -#define FlexSPI_AHBCR_APAREN_SHIFT (0U) +#define FLEXSPI_AHBCR_APAREN_MASK (0x1U) +#define FLEXSPI_AHBCR_APAREN_SHIFT (0U) /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . * 0b0..Flash will be accessed in Individual mode. * 0b1..Flash will be accessed in Parallel mode. */ -#define FlexSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_APAREN_SHIFT)) & FlexSPI_AHBCR_APAREN_MASK) +#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) -#define FlexSPI_AHBCR_CACHABLEEN_MASK (0x8U) -#define FlexSPI_AHBCR_CACHABLEEN_SHIFT (3U) +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) /*! CACHABLEEN - Enable AHB bus cachable read access support. * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. */ -#define FlexSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_CACHABLEEN_SHIFT)) & FlexSPI_AHBCR_CACHABLEEN_MASK) +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) -#define FlexSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) -#define FlexSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat * of AHB write access, refer for more details about AHB bufferable write. * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus @@ -394,292 +394,292 @@ typedef struct { * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is * granted by arbitrator and will not wait for AHB command finished. */ -#define FlexSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FlexSPI_AHBCR_BUFFERABLEEN_MASK) +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) -#define FlexSPI_AHBCR_PREFETCHEN_MASK (0x20U) -#define FlexSPI_AHBCR_PREFETCHEN_SHIFT (5U) +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) /*! PREFETCHEN - AHB Read Prefetch Enable. */ -#define FlexSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_PREFETCHEN_SHIFT)) & FlexSPI_AHBCR_PREFETCHEN_MASK) +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) -#define FlexSPI_AHBCR_READADDROPT_MASK (0x40U) -#define FlexSPI_AHBCR_READADDROPT_SHIFT (6U) +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB * burst required to meet the alignment requirement. */ -#define FlexSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_READADDROPT_SHIFT)) & FlexSPI_AHBCR_READADDROPT_MASK) +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable Register */ /*! @{ */ -#define FlexSPI_INTEN_IPCMDDONEEN_MASK (0x1U) -#define FlexSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) /*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. */ -#define FlexSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDDONEEN_SHIFT)) & FlexSPI_INTEN_IPCMDDONEEN_MASK) +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) -#define FlexSPI_INTEN_IPCMDGEEN_MASK (0x2U) -#define FlexSPI_INTEN_IPCMDGEEN_SHIFT (1U) +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) /*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. */ -#define FlexSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDGEEN_SHIFT)) & FlexSPI_INTEN_IPCMDGEEN_MASK) +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) -#define FlexSPI_INTEN_AHBCMDGEEN_MASK (0x4U) -#define FlexSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) /*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. */ -#define FlexSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBCMDGEEN_SHIFT)) & FlexSPI_INTEN_AHBCMDGEEN_MASK) +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) -#define FlexSPI_INTEN_IPCMDERREN_MASK (0x8U) -#define FlexSPI_INTEN_IPCMDERREN_SHIFT (3U) +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) /*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. */ -#define FlexSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDERREN_SHIFT)) & FlexSPI_INTEN_IPCMDERREN_MASK) +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) -#define FlexSPI_INTEN_AHBCMDERREN_MASK (0x10U) -#define FlexSPI_INTEN_AHBCMDERREN_SHIFT (4U) +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) /*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. */ -#define FlexSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBCMDERREN_SHIFT)) & FlexSPI_INTEN_AHBCMDERREN_MASK) +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) -#define FlexSPI_INTEN_IPRXWAEN_MASK (0x20U) -#define FlexSPI_INTEN_IPRXWAEN_SHIFT (5U) +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) /*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. */ -#define FlexSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPRXWAEN_SHIFT)) & FlexSPI_INTEN_IPRXWAEN_MASK) +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) -#define FlexSPI_INTEN_IPTXWEEN_MASK (0x40U) -#define FlexSPI_INTEN_IPTXWEEN_SHIFT (6U) +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) /*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. */ -#define FlexSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPTXWEEN_SHIFT)) & FlexSPI_INTEN_IPTXWEEN_MASK) +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) -#define FlexSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) -#define FlexSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) +#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) +#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) /*! DATALEARNFAILEN - Data Learning failed interrupt enable. */ -#define FlexSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FlexSPI_INTEN_DATALEARNFAILEN_MASK) +#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) -#define FlexSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) -#define FlexSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) /*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. */ -#define FlexSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FlexSPI_INTEN_SCKSTOPBYRDEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) -#define FlexSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) -#define FlexSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) /*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. */ -#define FlexSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FlexSPI_INTEN_SCKSTOPBYWREN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) -#define FlexSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) -#define FlexSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) /*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. */ -#define FlexSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FlexSPI_INTEN_AHBBUSTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) -#define FlexSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) -#define FlexSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) /*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. */ -#define FlexSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FlexSPI_INTEN_SEQTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) /*! @} */ /*! @name INTR - Interrupt Register */ /*! @{ */ -#define FlexSPI_INTR_IPCMDDONE_MASK (0x1U) -#define FlexSPI_INTR_IPCMDDONE_SHIFT (0U) +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) /*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also * generated when there is IPCMDGE or IPCMDERR interrupt generated. */ -#define FlexSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDDONE_SHIFT)) & FlexSPI_INTR_IPCMDDONE_MASK) +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) -#define FlexSPI_INTR_IPCMDGE_MASK (0x2U) -#define FlexSPI_INTR_IPCMDGE_SHIFT (1U) +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) /*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. */ -#define FlexSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDGE_SHIFT)) & FlexSPI_INTR_IPCMDGE_MASK) +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) -#define FlexSPI_INTR_AHBCMDGE_MASK (0x4U) -#define FlexSPI_INTR_AHBCMDGE_SHIFT (2U) +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) /*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. */ -#define FlexSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBCMDGE_SHIFT)) & FlexSPI_INTR_AHBCMDGE_MASK) +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) -#define FlexSPI_INTR_IPCMDERR_MASK (0x8U) -#define FlexSPI_INTR_IPCMDERR_SHIFT (3U) +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) /*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for * IP command, this command will be ignored and not executed at all. */ -#define FlexSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDERR_SHIFT)) & FlexSPI_INTR_IPCMDERR_MASK) +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) -#define FlexSPI_INTR_AHBCMDERR_MASK (0x10U) -#define FlexSPI_INTR_AHBCMDERR_SHIFT (4U) +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) /*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for * AHB command, this command will be ignored and not executed at all. */ -#define FlexSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBCMDERR_SHIFT)) & FlexSPI_INTR_AHBCMDERR_MASK) +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) -#define FlexSPI_INTR_IPRXWA_MASK (0x20U) -#define FlexSPI_INTR_IPRXWA_SHIFT (5U) +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) /*! IPRXWA - IP RX FIFO watermark available interrupt. */ -#define FlexSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPRXWA_SHIFT)) & FlexSPI_INTR_IPRXWA_MASK) +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) -#define FlexSPI_INTR_IPTXWE_MASK (0x40U) -#define FlexSPI_INTR_IPTXWE_SHIFT (6U) +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) /*! IPTXWE - IP TX FIFO watermark empty interrupt. */ -#define FlexSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPTXWE_SHIFT)) & FlexSPI_INTR_IPTXWE_MASK) +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) -#define FlexSPI_INTR_DATALEARNFAIL_MASK (0x80U) -#define FlexSPI_INTR_DATALEARNFAIL_SHIFT (7U) +#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) +#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) /*! DATALEARNFAIL - Data Learning failed interrupt. */ -#define FlexSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_DATALEARNFAIL_SHIFT)) & FlexSPI_INTR_DATALEARNFAIL_MASK) +#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) -#define FlexSPI_INTR_SCKSTOPBYRD_MASK (0x100U) -#define FlexSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) /*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt. */ -#define FlexSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SCKSTOPBYRD_SHIFT)) & FlexSPI_INTR_SCKSTOPBYRD_MASK) +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) -#define FlexSPI_INTR_SCKSTOPBYWR_MASK (0x200U) -#define FlexSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) /*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt. */ -#define FlexSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SCKSTOPBYWR_SHIFT)) & FlexSPI_INTR_SCKSTOPBYWR_MASK) +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) -#define FlexSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) -#define FlexSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) /*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. */ -#define FlexSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FlexSPI_INTR_AHBBUSTIMEOUT_MASK) +#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) -#define FlexSPI_INTR_SEQTIMEOUT_MASK (0x800U) -#define FlexSPI_INTR_SEQTIMEOUT_SHIFT (11U) +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) /*! SEQTIMEOUT - Sequence execution timeout interrupt. */ -#define FlexSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SEQTIMEOUT_SHIFT)) & FlexSPI_INTR_SEQTIMEOUT_MASK) +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) /*! @} */ /*! @name LUTKEY - LUT Key Register */ /*! @{ */ -#define FlexSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) -#define FlexSPI_LUTKEY_KEY_SHIFT (0U) +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) /*! KEY - The Key to lock or unlock LUT. */ -#define FlexSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTKEY_KEY_SHIFT)) & FlexSPI_LUTKEY_KEY_MASK) +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) /*! @} */ /*! @name LUTCR - LUT Control Register */ /*! @{ */ -#define FlexSPI_LUTCR_LOCK_MASK (0x1U) -#define FlexSPI_LUTCR_LOCK_SHIFT (0U) +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) /*! LOCK - Lock LUT */ -#define FlexSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTCR_LOCK_SHIFT)) & FlexSPI_LUTCR_LOCK_MASK) +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) -#define FlexSPI_LUTCR_UNLOCK_MASK (0x2U) -#define FlexSPI_LUTCR_UNLOCK_SHIFT (1U) +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) /*! UNLOCK - Unlock LUT */ -#define FlexSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTCR_UNLOCK_SHIFT)) & FlexSPI_LUTCR_UNLOCK_MASK) +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) /*! @} */ /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */ /*! @{ */ -#define FlexSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) -#define FlexSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) /*! BUFSZ - AHB RX Buffer Size in 64 bits. */ -#define FlexSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FlexSPI_AHBRXBUFCR0_BUFSZ_MASK) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) -#define FlexSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) -#define FlexSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) /*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). */ -#define FlexSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FlexSPI_AHBRXBUFCR0_MSTRID_MASK) +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) -#define FlexSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) -#define FlexSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) /*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. */ -#define FlexSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FlexSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) -#define FlexSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) -#define FlexSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) /*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. */ -#define FlexSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FlexSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FlexSPI_AHBRXBUFCR0 */ -#define FlexSPI_AHBRXBUFCR0_COUNT (8U) +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ -#define FlexSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) -#define FlexSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) /*! FLSHSZ - Flash Size in KByte. */ -#define FlexSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR0_FLSHSZ_SHIFT)) & FlexSPI_FLSHCR0_FLSHSZ_MASK) +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ -/* The count of FlexSPI_FLSHCR0 */ -#define FlexSPI_FLSHCR0_COUNT (4U) +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ -#define FlexSPI_FLSHCR1_TCSS_MASK (0x1FU) -#define FlexSPI_FLSHCR1_TCSS_SHIFT (0U) +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) /*! TCSS - Serial Flash CS setup time. */ -#define FlexSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_TCSS_SHIFT)) & FlexSPI_FLSHCR1_TCSS_MASK) +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) -#define FlexSPI_FLSHCR1_TCSH_MASK (0x3E0U) -#define FlexSPI_FLSHCR1_TCSH_SHIFT (5U) +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) /*! TCSH - Serial Flash CS Hold time. */ -#define FlexSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_TCSH_SHIFT)) & FlexSPI_FLSHCR1_TCSH_MASK) +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) -#define FlexSPI_FLSHCR1_WA_MASK (0x400U) -#define FlexSPI_FLSHCR1_WA_SHIFT (10U) +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) /*! WA - Word Addressable. */ -#define FlexSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_WA_SHIFT)) & FlexSPI_FLSHCR1_WA_MASK) +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) -#define FlexSPI_FLSHCR1_CAS_MASK (0x7800U) -#define FlexSPI_FLSHCR1_CAS_SHIFT (11U) +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) /*! CAS - Column Address Size. */ -#define FlexSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CAS_SHIFT)) & FlexSPI_FLSHCR1_CAS_MASK) +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) -#define FlexSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) -#define FlexSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) /*! CSINTERVALUNIT - CS interval unit * 0b0..The CS interval unit is 1 serial clock cycle * 0b1..The CS interval unit is 256 serial clock cycle */ -#define FlexSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FlexSPI_FLSHCR1_CSINTERVALUNIT_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) -#define FlexSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) -#define FlexSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) /*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection * deassertion and flash device Chip selection assertion. If external flash has a limitation on * the interval between command sequences, this field should be set accordingly. If there is no * limitation, set this field with value 0x0. */ -#define FlexSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FlexSPI_FLSHCR1_CSINTERVAL_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FlexSPI_FLSHCR1 */ -#define FlexSPI_FLSHCR1_COUNT (4U) +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ -#define FlexSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) -#define FlexSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) /*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. */ -#define FlexSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_ARDSEQID_SHIFT)) & FlexSPI_FLSHCR2_ARDSEQID_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) -#define FlexSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) -#define FlexSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) /*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. */ -#define FlexSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FlexSPI_FLSHCR2_ARDSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) -#define FlexSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) -#define FlexSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) /*! AWRSEQID - Sequence Index for AHB Write triggered Command. */ -#define FlexSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRSEQID_SHIFT)) & FlexSPI_FLSHCR2_AWRSEQID_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) -#define FlexSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) -#define FlexSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) /*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. */ -#define FlexSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FlexSPI_FLSHCR2_AWRSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) -#define FlexSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) -#define FlexSPI_FLSHCR2_AWRWAIT_SHIFT (16U) -#define FlexSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRWAIT_SHIFT)) & FlexSPI_FLSHCR2_AWRWAIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) -#define FlexSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) -#define FlexSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) /*! AWRWAITUNIT - AWRWAIT unit * 0b000..The AWRWAIT unit is 2 ahb clock cycle * 0b001..The AWRWAIT unit is 8 ahb clock cycle @@ -690,206 +690,206 @@ typedef struct { * 0b110..The AWRWAIT unit is 8192 ahb clock cycle * 0b111..The AWRWAIT unit is 32768 ahb clock cycle */ -#define FlexSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FlexSPI_FLSHCR2_AWRWAITUNIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) -#define FlexSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) -#define FlexSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. * Refer Programmable Sequence Engine for details. */ -#define FlexSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FlexSPI_FLSHCR2_CLRINSTRPTR_MASK) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FlexSPI_FLSHCR2 */ -#define FlexSPI_FLSHCR2_COUNT (4U) +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ -#define FlexSPI_FLSHCR4_WMOPT1_MASK (0x1U) -#define FlexSPI_FLSHCR4_WMOPT1_SHIFT (0U) +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write * burst start address alignment when flash is accessed in individual mode. * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write * burst start address alignment when flash is accessed in individual mode. */ -#define FlexSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMOPT1_SHIFT)) & FlexSPI_FLSHCR4_WMOPT1_MASK) +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) -#define FlexSPI_FLSHCR4_WMENA_MASK (0x4U) -#define FlexSPI_FLSHCR4_WMENA_SHIFT (2U) +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for * memory device on port A, this bit must be set. * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ -#define FlexSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMENA_SHIFT)) & FlexSPI_FLSHCR4_WMENA_MASK) +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) -#define FlexSPI_FLSHCR4_WMENB_MASK (0x8U) -#define FlexSPI_FLSHCR4_WMENB_SHIFT (3U) +#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) +#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for * memory device on port B, this bit must be set. * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ -#define FlexSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMENB_SHIFT)) & FlexSPI_FLSHCR4_WMENB_MASK) +#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) /*! @} */ /*! @name IPCR0 - IP Control Register 0 */ /*! @{ */ -#define FlexSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) -#define FlexSPI_IPCR0_SFAR_SHIFT (0U) +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) /*! SFAR - Serial Flash Address for IP command. */ -#define FlexSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR0_SFAR_SHIFT)) & FlexSPI_IPCR0_SFAR_MASK) +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) /*! @} */ /*! @name IPCR1 - IP Control Register 1 */ /*! @{ */ -#define FlexSPI_IPCR1_IDATSZ_MASK (0xFFFFU) -#define FlexSPI_IPCR1_IDATSZ_SHIFT (0U) +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) /*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. */ -#define FlexSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_IDATSZ_SHIFT)) & FlexSPI_IPCR1_IDATSZ_MASK) +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) -#define FlexSPI_IPCR1_ISEQID_MASK (0x1F0000U) -#define FlexSPI_IPCR1_ISEQID_SHIFT (16U) +#define FLEXSPI_IPCR1_ISEQID_MASK (0x1F0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) /*! ISEQID - Sequence Index in LUT for IP command. */ -#define FlexSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_ISEQID_SHIFT)) & FlexSPI_IPCR1_ISEQID_MASK) +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) -#define FlexSPI_IPCR1_ISEQNUM_MASK (0x7000000U) -#define FlexSPI_IPCR1_ISEQNUM_SHIFT (24U) +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */ -#define FlexSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_ISEQNUM_SHIFT)) & FlexSPI_IPCR1_ISEQNUM_MASK) +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) -#define FlexSPI_IPCR1_IPAREN_MASK (0x80000000U) -#define FlexSPI_IPCR1_IPAREN_SHIFT (31U) +#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) +#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) /*! IPAREN - Parallel mode Enabled for IP command. * 0b0..Flash will be accessed in Individual mode. * 0b1..Flash will be accessed in Parallel mode. */ -#define FlexSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_IPAREN_SHIFT)) & FlexSPI_IPCR1_IPAREN_MASK) +#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) /*! @} */ /*! @name IPCMD - IP Command Register */ /*! @{ */ -#define FlexSPI_IPCMD_TRG_MASK (0x1U) -#define FlexSPI_IPCMD_TRG_SHIFT (0U) +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) /*! TRG - Setting this bit will trigger an IP Command. */ -#define FlexSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCMD_TRG_SHIFT)) & FlexSPI_IPCMD_TRG_MASK) +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) /*! @} */ /*! @name DLPR - Data Learn Pattern Register */ /*! @{ */ -#define FlexSPI_DLPR_DLP_MASK (0xFFFFFFFFU) -#define FlexSPI_DLPR_DLP_SHIFT (0U) +#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) +#define FLEXSPI_DLPR_DLP_SHIFT (0U) /*! DLP - Data Learning Pattern. */ -#define FlexSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLPR_DLP_SHIFT)) & FlexSPI_DLPR_DLP_MASK) +#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) /*! @} */ /*! @name IPRXFCR - IP RX FIFO Control Register */ /*! @{ */ -#define FlexSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) -#define FlexSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) /*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. */ -#define FlexSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FlexSPI_IPRXFCR_CLRIPRXF_MASK) +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) -#define FlexSPI_IPRXFCR_RXDMAEN_MASK (0x2U) -#define FlexSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) /*! RXDMAEN - IP RX FIFO reading by DMA enabled. * 0b0..IP RX FIFO would be read by processor. * 0b1..IP RX FIFO would be read by DMA. */ -#define FlexSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_RXDMAEN_SHIFT)) & FlexSPI_IPRXFCR_RXDMAEN_MASK) +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) -#define FlexSPI_IPRXFCR_RXWMRK_MASK (0xFCU) -#define FlexSPI_IPRXFCR_RXWMRK_SHIFT (2U) +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0xFCU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) /*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. */ -#define FlexSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_RXWMRK_SHIFT)) & FlexSPI_IPRXFCR_RXWMRK_MASK) +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) /*! @} */ /*! @name IPTXFCR - IP TX FIFO Control Register */ /*! @{ */ -#define FlexSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) -#define FlexSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) /*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. */ -#define FlexSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FlexSPI_IPTXFCR_CLRIPTXF_MASK) +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) -#define FlexSPI_IPTXFCR_TXDMAEN_MASK (0x2U) -#define FlexSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) /*! TXDMAEN - IP TX FIFO filling by DMA enabled. * 0b0..IP TX FIFO would be filled by processor. * 0b1..IP TX FIFO would be filled by DMA. */ -#define FlexSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_TXDMAEN_SHIFT)) & FlexSPI_IPTXFCR_TXDMAEN_MASK) +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) -#define FlexSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) -#define FlexSPI_IPTXFCR_TXWMRK_SHIFT (2U) +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) /*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. */ -#define FlexSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_TXWMRK_SHIFT)) & FlexSPI_IPTXFCR_TXWMRK_MASK) +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) /*! @} */ /*! @name DLLCR - DLL Control Register 0 */ /*! @{ */ -#define FlexSPI_DLLCR_DLLEN_MASK (0x1U) -#define FlexSPI_DLLCR_DLLEN_SHIFT (0U) +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) /*! DLLEN - DLL calibration enable. */ -#define FlexSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_DLLEN_SHIFT)) & FlexSPI_DLLCR_DLLEN_MASK) +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) -#define FlexSPI_DLLCR_DLLRESET_MASK (0x2U) -#define FlexSPI_DLLCR_DLLRESET_SHIFT (1U) +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) /*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the * DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset * action is edge triggered, so software need to clear this bit after set this bit (no delay * limitation). */ -#define FlexSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_DLLRESET_SHIFT)) & FlexSPI_DLLCR_DLLRESET_MASK) +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) -#define FlexSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) -#define FlexSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) /*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). */ -#define FlexSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FlexSPI_DLLCR_SLVDLYTARGET_MASK) +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) -#define FlexSPI_DLLCR_OVRDEN_MASK (0x100U) -#define FlexSPI_DLLCR_OVRDEN_SHIFT (8U) +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) /*! OVRDEN - Slave clock delay line delay cell number selection override enable. */ -#define FlexSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_OVRDEN_SHIFT)) & FlexSPI_DLLCR_OVRDEN_MASK) +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) -#define FlexSPI_DLLCR_OVRDVAL_MASK (0x7E00U) -#define FlexSPI_DLLCR_OVRDVAL_SHIFT (9U) +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) /*! OVRDVAL - Slave clock delay line delay cell number selection override value. */ -#define FlexSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_OVRDVAL_SHIFT)) & FlexSPI_DLLCR_OVRDVAL_MASK) +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FlexSPI_DLLCR */ -#define FlexSPI_DLLCR_COUNT (2U) +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) /*! @name STS0 - Status Register 0 */ /*! @{ */ -#define FlexSPI_STS0_SEQIDLE_MASK (0x1U) -#define FlexSPI_STS0_SEQIDLE_SHIFT (0U) +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) /*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command * sequence executing on FlexSPI interface. */ -#define FlexSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_SEQIDLE_SHIFT)) & FlexSPI_STS0_SEQIDLE_MASK) +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) -#define FlexSPI_STS0_ARBIDLE_MASK (0x2U) -#define FlexSPI_STS0_ARBIDLE_SHIFT (1U) +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) /*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command * sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state * (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So * this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. */ -#define FlexSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_ARBIDLE_SHIFT)) & FlexSPI_STS0_ARBIDLE_MASK) +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) -#define FlexSPI_STS0_ARBCMDSRC_MASK (0xCU) -#define FlexSPI_STS0_ARBCMDSRC_SHIFT (2U) +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). * 0b00..Triggered by AHB read command (triggered by AHB read). @@ -897,31 +897,31 @@ typedef struct { * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). * 0b11..Triggered by suspended command (resumed). */ -#define FlexSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_ARBCMDSRC_SHIFT)) & FlexSPI_STS0_ARBCMDSRC_MASK) +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) -#define FlexSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) -#define FlexSPI_STS0_DATALEARNPHASEA_SHIFT (4U) +#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) +#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) /*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning. */ -#define FlexSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_DATALEARNPHASEA_SHIFT)) & FlexSPI_STS0_DATALEARNPHASEA_MASK) +#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) -#define FlexSPI_STS0_DATALEARNPHASEB_MASK (0xF00U) -#define FlexSPI_STS0_DATALEARNPHASEB_SHIFT (8U) +#define FLEXSPI_STS0_DATALEARNPHASEB_MASK (0xF00U) +#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT (8U) /*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning. */ -#define FlexSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_DATALEARNPHASEB_SHIFT)) & FlexSPI_STS0_DATALEARNPHASEB_MASK) +#define FLEXSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK) /*! @} */ /*! @name STS1 - Status Register 1 */ /*! @{ */ -#define FlexSPI_STS1_AHBCMDERRID_MASK (0x1FU) -#define FlexSPI_STS1_AHBCMDERRID_SHIFT (0U) +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0x1FU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) /*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field * will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). */ -#define FlexSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_AHBCMDERRID_SHIFT)) & FlexSPI_STS1_AHBCMDERRID_MASK) +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) -#define FlexSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) -#define FlexSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be * cleared when INTR[AHBCMDERR] is write-1-clear(w1c). * 0b0000..No error. @@ -931,17 +931,17 @@ typedef struct { * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. * 0b1110..Sequence execution timeout. */ -#define FlexSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_AHBCMDERRCODE_SHIFT)) & FlexSPI_STS1_AHBCMDERRCODE_MASK) +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) -#define FlexSPI_STS1_IPCMDERRID_MASK (0x1F0000U) -#define FlexSPI_STS1_IPCMDERRID_SHIFT (16U) +#define FLEXSPI_STS1_IPCMDERRID_MASK (0x1F0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) /*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be * cleared when INTR[IPCMDERR] is write-1-clear(w1c). */ -#define FlexSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_IPCMDERRID_SHIFT)) & FlexSPI_STS1_IPCMDERRID_MASK) +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) -#define FlexSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) -#define FlexSPI_STS1_IPCMDERRCODE_SHIFT (24U) +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be * cleared when INTR[IPCMDERR] is write-1-clear(w1c). * 0b0000..No error. @@ -953,161 +953,161 @@ typedef struct { * 0b1110..Sequence execution timeout. * 0b1111..Flash boundary crossed. */ -#define FlexSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_IPCMDERRCODE_SHIFT)) & FlexSPI_STS1_IPCMDERRCODE_MASK) +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) /*! @} */ /*! @name STS2 - Status Register 2 */ /*! @{ */ -#define FlexSPI_STS2_ASLVLOCK_MASK (0x1U) -#define FlexSPI_STS2_ASLVLOCK_SHIFT (0U) +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) /*! ASLVLOCK - Flash A sample clock slave delay line locked. */ -#define FlexSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_ASLVLOCK_SHIFT)) & FlexSPI_STS2_ASLVLOCK_MASK) +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) -#define FlexSPI_STS2_AREFLOCK_MASK (0x2U) -#define FlexSPI_STS2_AREFLOCK_SHIFT (1U) +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) /*! AREFLOCK - Flash A sample clock reference delay line locked. */ -#define FlexSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_AREFLOCK_SHIFT)) & FlexSPI_STS2_AREFLOCK_MASK) +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) -#define FlexSPI_STS2_ASLVSEL_MASK (0xFCU) -#define FlexSPI_STS2_ASLVSEL_SHIFT (2U) +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) /*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . */ -#define FlexSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_ASLVSEL_SHIFT)) & FlexSPI_STS2_ASLVSEL_MASK) +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) -#define FlexSPI_STS2_AREFSEL_MASK (0x3F00U) -#define FlexSPI_STS2_AREFSEL_SHIFT (8U) +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) /*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. */ -#define FlexSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_AREFSEL_SHIFT)) & FlexSPI_STS2_AREFSEL_MASK) +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) -#define FlexSPI_STS2_BSLVLOCK_MASK (0x10000U) -#define FlexSPI_STS2_BSLVLOCK_SHIFT (16U) +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) /*! BSLVLOCK - Flash B sample clock slave delay line locked. */ -#define FlexSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BSLVLOCK_SHIFT)) & FlexSPI_STS2_BSLVLOCK_MASK) +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) -#define FlexSPI_STS2_BREFLOCK_MASK (0x20000U) -#define FlexSPI_STS2_BREFLOCK_SHIFT (17U) +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) /*! BREFLOCK - Flash B sample clock reference delay line locked. */ -#define FlexSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BREFLOCK_SHIFT)) & FlexSPI_STS2_BREFLOCK_MASK) +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) -#define FlexSPI_STS2_BSLVSEL_MASK (0xFC0000U) -#define FlexSPI_STS2_BSLVSEL_SHIFT (18U) +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) /*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection. */ -#define FlexSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BSLVSEL_SHIFT)) & FlexSPI_STS2_BSLVSEL_MASK) +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) -#define FlexSPI_STS2_BREFSEL_MASK (0x3F000000U) -#define FlexSPI_STS2_BREFSEL_SHIFT (24U) +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) /*! BREFSEL - Flash B sample clock reference delay line delay cell number selection. */ -#define FlexSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BREFSEL_SHIFT)) & FlexSPI_STS2_BREFSEL_MASK) +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) /*! @} */ /*! @name AHBSPNDSTS - AHB Suspend Status Register */ /*! @{ */ -#define FlexSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) -#define FlexSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) /*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. */ -#define FlexSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FlexSPI_AHBSPNDSTS_ACTIVE_MASK) +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) -#define FlexSPI_AHBSPNDSTS_BUFID_MASK (0xEU) -#define FlexSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) /*! BUFID - AHB RX BUF ID for suspended command sequence. */ -#define FlexSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_BUFID_SHIFT)) & FlexSPI_AHBSPNDSTS_BUFID_MASK) +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) -#define FlexSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) -#define FlexSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) /*! DATLFT - Left Data size for suspended command sequence (in byte). */ -#define FlexSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FlexSPI_AHBSPNDSTS_DATLFT_MASK) +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) /*! @} */ /*! @name IPRXFSTS - IP RX FIFO Status Register */ /*! @{ */ -#define FlexSPI_IPRXFSTS_FILL_MASK (0xFFU) -#define FlexSPI_IPRXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) /*! FILL - Fill level of IP RX FIFO. */ -#define FlexSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFSTS_FILL_SHIFT)) & FlexSPI_IPRXFSTS_FILL_MASK) +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) -#define FlexSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) -#define FlexSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) /*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. */ -#define FlexSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFSTS_RDCNTR_SHIFT)) & FlexSPI_IPRXFSTS_RDCNTR_MASK) +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) /*! @} */ /*! @name IPTXFSTS - IP TX FIFO Status Register */ /*! @{ */ -#define FlexSPI_IPTXFSTS_FILL_MASK (0xFFU) -#define FlexSPI_IPTXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) /*! FILL - Fill level of IP TX FIFO. */ -#define FlexSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFSTS_FILL_SHIFT)) & FlexSPI_IPTXFSTS_FILL_MASK) +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) -#define FlexSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) -#define FlexSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) /*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. */ -#define FlexSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFSTS_WRCNTR_SHIFT)) & FlexSPI_IPTXFSTS_WRCNTR_MASK) +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) /*! @} */ /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ /*! @{ */ -#define FlexSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) -#define FlexSPI_RFDR_RXDATA_SHIFT (0U) +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) /*! RXDATA - RX Data */ -#define FlexSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_RFDR_RXDATA_SHIFT)) & FlexSPI_RFDR_RXDATA_MASK) +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) /*! @} */ /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ /*! @{ */ -#define FlexSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) -#define FlexSPI_TFDR_TXDATA_SHIFT (0U) +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) /*! TXDATA - TX Data */ -#define FlexSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_TFDR_TXDATA_SHIFT)) & FlexSPI_TFDR_TXDATA_MASK) +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) /*! @} */ /*! @name LUT - LUT 0..LUT 127 */ /*! @{ */ -#define FlexSPI_LUT_OPERAND0_MASK (0xFFU) -#define FlexSPI_LUT_OPERAND0_SHIFT (0U) +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) /*! OPERAND0 - OPERAND0 */ -#define FlexSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPERAND0_SHIFT)) & FlexSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) -#define FlexSPI_LUT_NUM_PADS0_MASK (0x300U) -#define FlexSPI_LUT_NUM_PADS0_SHIFT (8U) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) /*! NUM_PADS0 - NUM_PADS0 */ -#define FlexSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_NUM_PADS0_SHIFT)) & FlexSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) -#define FlexSPI_LUT_OPCODE0_MASK (0xFC00U) -#define FlexSPI_LUT_OPCODE0_SHIFT (10U) +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) /*! OPCODE0 - OPCODE */ -#define FlexSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPCODE0_SHIFT)) & FlexSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) -#define FlexSPI_LUT_OPERAND1_MASK (0xFF0000U) -#define FlexSPI_LUT_OPERAND1_SHIFT (16U) +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) /*! OPERAND1 - OPERAND1 */ -#define FlexSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPERAND1_SHIFT)) & FlexSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) -#define FlexSPI_LUT_NUM_PADS1_MASK (0x3000000U) -#define FlexSPI_LUT_NUM_PADS1_SHIFT (24U) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) /*! NUM_PADS1 - NUM_PADS1 */ -#define FlexSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_NUM_PADS1_SHIFT)) & FlexSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) -#define FlexSPI_LUT_OPCODE1_MASK (0xFC000000U) -#define FlexSPI_LUT_OPCODE1_SHIFT (26U) +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) /*! OPCODE1 - OPCODE1 */ -#define FlexSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPCODE1_SHIFT)) & FlexSPI_LUT_OPCODE1_MASK) +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) /*! @} */ /*! * @} - */ /* end of group FlexSPI_Register_Masks */ + */ /* end of group FLEXSPI_Register_Masks */ /*! * @} - */ /* end of group FlexSPI_Peripheral_Access_Layer */ + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ /* diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_COMMON.h index 65b864635..cd7cd96cd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MPRM, Rev.D, 12/2020 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8ML2_cm7 @@ -616,15 +616,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ /** Peripheral ENET_QOS base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_features.h index b04158d57..5fea09efd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/MIMX8ML2_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2021-03-01 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -236,13 +236,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -322,6 +322,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* IGPIO module features */ @@ -339,8 +343,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -369,15 +371,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/system_MIMX8ML2_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/system_MIMX8ML2_cm7.c index 1bd13b7f7..55dd9da44 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/system_MIMX8ML2_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML2/system_MIMX8ML2_cm7.c @@ -66,6 +66,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_COMMON.h index dc3163f52..a31af33bb 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MPRM, Rev.D, 12/2020 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8ML3_cm7 @@ -616,15 +616,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ /** Peripheral ENET_QOS base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_features.h index 087727541..ee1f1d96a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/MIMX8ML3_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2021-03-01 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -236,13 +236,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -322,6 +322,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* IGPIO module features */ @@ -339,8 +343,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -369,15 +371,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/system_MIMX8ML3_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/system_MIMX8ML3_cm7.c index add419787..8dfd6e5b7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/system_MIMX8ML3_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML3/system_MIMX8ML3_cm7.c @@ -66,6 +66,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_COMMON.h index def8b11de..ad6fbd536 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MPRM, Rev.D, 12/2020 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8ML4_cm7 @@ -616,15 +616,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ /** Peripheral ENET_QOS base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_features.h index 393432455..e6781e7f6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/MIMX8ML4_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2021-03-01 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -236,13 +236,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -322,6 +322,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* IGPIO module features */ @@ -339,8 +343,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -369,15 +371,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/system_MIMX8ML4_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/system_MIMX8ML4_cm7.c index 738709c33..b9c66d71a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/system_MIMX8ML4_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML4/system_MIMX8ML4_cm7.c @@ -66,6 +66,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_COMMON.h index 9f3ef9487..ce268e52a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MPRM, Rev.D, 12/2020 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8ML5_cm7 @@ -616,15 +616,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ /** Peripheral ENET_QOS base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_features.h index cb2de2784..27929d14a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/MIMX8ML5_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2021-03-01 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -236,13 +236,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -322,6 +322,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* IGPIO module features */ @@ -339,8 +343,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -369,15 +371,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/system_MIMX8ML5_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/system_MIMX8ML5_cm7.c index 9cc4f8238..f0704adc5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/system_MIMX8ML5_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML5/system_MIMX8ML5_cm7.c @@ -66,6 +66,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_COMMON.h index 9f9f00a9b..3c1af93dd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MPRM, Rev.D, 12/2020 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8ML6_cm7 @@ -616,15 +616,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ /** Peripheral ENET_QOS base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_features.h index c7c300e1f..5e8e756ca 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/MIMX8ML6_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2021-03-01 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -236,13 +236,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -322,6 +322,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* IGPIO module features */ @@ -339,8 +343,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -369,15 +371,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/system_MIMX8ML6_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/system_MIMX8ML6_cm7.c index 4ed6a8cae..0d3aafb31 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/system_MIMX8ML6_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML6/system_MIMX8ML6_cm7.c @@ -66,6 +66,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_COMMON.h index 7411c297f..f83dee92b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX8MPRM, Rev.D, 12/2020 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8ML8_cm7 @@ -616,15 +616,18 @@ typedef enum IRQn { /** Peripheral ENET1 base pointer */ #define ENET1 ((ENET_Type *)ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET1_BASE } +#define ENET_BASE_ADDRS { 0u, ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET1 } +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET1_IRQn } -#define ENET_Receive_IRQS { ENET1_IRQn } -#define ENET_Error_IRQS { ENET1_IRQn } -#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +#define ENET_Ts_IRQS { NotAvail_IRQn, ENET1_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ /** Peripheral ENET_QOS base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_features.h index 15cd47107..eb6bb65a1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/MIMX8ML8_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2021-03-01 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -236,13 +236,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -322,6 +322,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* IGPIO module features */ @@ -339,8 +343,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -369,15 +371,17 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) -/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ +/* @brief SAI5 and SAI6 share one irq number. */ #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) /* ISI module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/drivers/fsl_clock.h index 398589d22..9e9e6cbb3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/drivers/fsl_clock.h @@ -57,9 +57,9 @@ } /*! @brief Clock ip name array for ENET. */ -#define ENET_CLOCKS \ - { \ - kCLOCK_Enet1, \ +#define ENET_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enet1, \ } /*! @brief Clock ip name array for ENET_QOS. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/system_MIMX8ML8_cm7.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/system_MIMX8ML8_cm7.c index 725c6ef11..f0f0c69ea 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/system_MIMX8ML8_cm7.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/MIMX8ML8/system_MIMX8ML8_cm7.c @@ -66,6 +66,25 @@ */ #define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off)))) +extern void Reset_Handler(void); + +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t __StackTop; +__attribute__((section(".stacktop_and_pc"))) +#elif defined(__ICCARM__) +extern void __StackTop; +#pragma location = ".stacktop_and_pc" +#else +#error Compiler not supported! +#endif + +/* + * stackTopAndPc[0]: stack top address + * stackTopAndPc[1]: pc + * Linux will copy stack top address and pc to load address. + */ +const uint32_t stackTopAndPc[2] = { (uint32_t)&__StackTop, (uint32_t)Reset_Handler}; + /******************************************************************************* * Prototypes ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_ENET.h index 2eaf7dba4..1bcc5e8be 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_ENET.h @@ -34,7 +34,7 @@ ** MIMX8ML8DVNLZ_dsp ** ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET @@ -2192,9 +2192,6 @@ typedef struct { * @} */ /* end of group ENET_Register_Masks */ -/* ENET Buffer Descriptor and Buffer Address Alignment. */ -#define ENET_BUFF_ALIGNMENT (64U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_USB.h index 2639ca0f0..5499a4bfb 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_USB.h @@ -168,7 +168,6 @@ typedef struct { __I uint32_t HCCPARAMS2; /**< Host Controller Capability Parameters 2, offset: 0x1C */ __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x20 */ __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x24 */ -#undef PAGESIZE __I uint32_t PAGESIZE; /**< Page Size Register, offset: 0x28 */ uint8_t RESERVED_0[8]; __IO uint32_t DNCTRL; /**< Device Notification Register, offset: 0x34 */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_cm33_COMMON.h index e9d3abc0e..0aa447f54 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8UD3_cm33 @@ -944,6 +944,9 @@ typedef enum IRQn { /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } #endif +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EPDC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1107,31 +1110,31 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x14000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x50000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x70000000u) -#else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x04000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x40000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x60000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x14000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x50000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x70000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x04000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x40000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x60000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_cm33_features.h index 830eb5b85..bf3dd7f37 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -299,6 +299,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -330,8 +334,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -344,6 +346,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -468,13 +472,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -488,8 +492,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -518,19 +520,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -553,14 +603,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -661,8 +711,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -705,6 +753,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -833,8 +885,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -871,20 +921,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -909,16 +968,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -934,16 +984,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_dsp0_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_dsp0_COMMON.h index a2a63797f..d71216dd7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_dsp0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_dsp0_COMMON.h @@ -7,7 +7,7 @@ ** Compiler: Xtensa Compiler ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** Peripheral Access Layer for MIMX8UD3_dsp0 @@ -358,6 +358,9 @@ typedef enum IRQn { #define ENET_BASE_ADDRS { ENET_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EPDC - Peripheral instance base addresses */ /** Peripheral EPDC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_dsp0_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_dsp0_features.h index 2003d7c3d..7f9414571 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_dsp0_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD3/MIMX8UD3_dsp0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -299,6 +299,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -330,8 +334,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -344,6 +346,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -468,13 +472,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -488,8 +492,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -518,19 +520,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -553,14 +603,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -661,8 +711,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -705,6 +753,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -833,8 +885,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -871,20 +921,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -909,16 +968,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -934,16 +984,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_cm33_COMMON.h index fe96aa464..328479e77 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8UD5_cm33 @@ -944,6 +944,9 @@ typedef enum IRQn { /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } #endif +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EWM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1076,31 +1079,31 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x14000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x50000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x70000000u) -#else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x04000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x40000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x60000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x14000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x50000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x70000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x04000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x40000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x60000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_cm33_features.h index 58eedb4e0..5a807d10a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -297,6 +297,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -328,8 +332,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -342,6 +344,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -466,13 +470,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -486,8 +490,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -516,19 +518,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -551,14 +601,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -659,8 +709,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -703,6 +751,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -831,8 +883,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -869,20 +919,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -907,16 +966,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -932,16 +982,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_dsp0_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_dsp0_COMMON.h index 3121fb044..f341958de 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_dsp0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_dsp0_COMMON.h @@ -7,7 +7,7 @@ ** Compiler: Xtensa Compiler ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** Peripheral Access Layer for MIMX8UD5_dsp0 @@ -358,6 +358,9 @@ typedef enum IRQn { #define ENET_BASE_ADDRS { ENET_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EWM - Peripheral instance base addresses */ /** Peripheral EWM0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_dsp0_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_dsp0_features.h index 71f229520..4406eefe5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_dsp0_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD5/MIMX8UD5_dsp0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -297,6 +297,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -328,8 +332,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -342,6 +344,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -466,13 +470,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -486,8 +490,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -516,19 +518,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -551,14 +601,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -659,8 +709,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -703,6 +751,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -831,8 +883,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -869,20 +919,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -907,16 +966,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -932,16 +982,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_cm33_COMMON.h index 2b53a133d..e149366f4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8UD7_cm33 @@ -944,6 +944,9 @@ typedef enum IRQn { /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } #endif +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EPDC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1107,31 +1110,31 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x14000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x50000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x70000000u) -#else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x04000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x40000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x60000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x14000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x50000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x70000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x04000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x40000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x60000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_cm33_features.h index 636a51e09..707d3c1f1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -299,6 +299,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -330,8 +334,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -344,6 +346,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -468,13 +472,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -488,8 +492,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -518,19 +520,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -553,14 +603,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -661,8 +711,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -705,6 +753,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -833,8 +885,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -871,20 +921,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -909,16 +968,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -934,16 +984,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_dsp0_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_dsp0_COMMON.h index 4a4721ebd..44e9b9fb0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_dsp0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_dsp0_COMMON.h @@ -7,7 +7,7 @@ ** Compiler: Xtensa Compiler ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** Peripheral Access Layer for MIMX8UD7_dsp0 @@ -358,6 +358,9 @@ typedef enum IRQn { #define ENET_BASE_ADDRS { ENET_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EPDC - Peripheral instance base addresses */ /** Peripheral EPDC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_dsp0_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_dsp0_features.h index 758041bee..d9628c449 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_dsp0_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8UD7/MIMX8UD7_dsp0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -299,6 +299,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -330,8 +334,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -344,6 +346,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -468,13 +472,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -488,8 +492,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -518,19 +520,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -553,14 +603,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -661,8 +711,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -705,6 +753,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -833,8 +885,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -871,20 +921,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -909,16 +968,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -934,16 +984,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_cm33_COMMON.h index 37f204b62..f49a31211 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8US3_cm33 @@ -944,6 +944,9 @@ typedef enum IRQn { /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } #endif +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EPDC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1107,31 +1110,31 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x14000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x50000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x70000000u) -#else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x04000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x40000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x60000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x14000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x50000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x70000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x04000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x40000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x60000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_cm33_features.h index f9d0d1ced..56afc54aa 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -299,6 +299,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -330,8 +334,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -344,6 +346,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -468,13 +472,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -488,8 +492,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -518,19 +520,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -553,14 +603,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -661,8 +711,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -705,6 +753,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -833,8 +885,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -871,20 +921,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -909,16 +968,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -934,16 +984,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_dsp0_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_dsp0_COMMON.h index e95cb745f..a02ac1524 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_dsp0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_dsp0_COMMON.h @@ -7,7 +7,7 @@ ** Compiler: Xtensa Compiler ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** Peripheral Access Layer for MIMX8US3_dsp0 @@ -358,6 +358,9 @@ typedef enum IRQn { #define ENET_BASE_ADDRS { ENET_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EPDC - Peripheral instance base addresses */ /** Peripheral EPDC base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_dsp0_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_dsp0_features.h index 76b2aa762..605d21b9c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_dsp0_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US3/MIMX8US3_dsp0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -299,6 +299,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -330,8 +334,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -344,6 +346,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -468,13 +472,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -488,8 +492,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -518,19 +520,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -553,14 +603,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -661,8 +711,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -705,6 +753,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -833,8 +885,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -871,20 +921,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -909,16 +968,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -934,16 +984,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_cm33_COMMON.h index 4b82fa9f2..506e85ad9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8US5_cm33 @@ -944,6 +944,9 @@ typedef enum IRQn { /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } #endif +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EWM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1076,31 +1079,31 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x14000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x50000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x70000000u) -#else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } -/* FlexSPI0 AMBA base address. */ -#define FlexSPI0_AMBA_BASE (0x04000000u) -/* FlexSPI1 AMBA base address. */ -#define FlexSPI1_AMBA_BASE (0x40000000u) -/* FlexSPI2 AMBA base address. */ -#define FlexSPI2_AMBA_BASE (0x60000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x14000000u}, {0x50000000u}, {0x70000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1BFFFFFFu}, {0x5FFFFFFFu}, {0x7FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x14000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x50000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x70000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x04000000u}, {0x40000000u}, {0x60000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0BFFFFFFu}, {0x4FFFFFFFu}, {0x6FFFFFFFu} } + /* FlexSPI0 AMBA base address. */ + #define FlexSPI0_AMBA_BASE (0x04000000u) + /* FlexSPI1 AMBA base address. */ + #define FlexSPI1_AMBA_BASE (0x40000000u) + /* FlexSPI2 AMBA base address. */ + #define FlexSPI2_AMBA_BASE (0x60000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_cm33_features.h index 9a12a1ad4..d1c89f82c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -297,6 +297,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -328,8 +332,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -342,6 +344,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -466,13 +470,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -486,8 +490,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -516,19 +518,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -551,14 +601,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -659,8 +709,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -703,6 +751,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -831,8 +883,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -869,20 +919,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -907,16 +966,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -932,16 +982,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_dsp0_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_dsp0_COMMON.h index 5a8c5ac94..0766321d8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_dsp0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_dsp0_COMMON.h @@ -7,7 +7,7 @@ ** Compiler: Xtensa Compiler ** Reference manual: IMX8ULPRM, Rev. D, December. 2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** Peripheral Access Layer for MIMX8US5_dsp0 @@ -358,6 +358,9 @@ typedef enum IRQn { #define ENET_BASE_ADDRS { ENET_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* EWM - Peripheral instance base addresses */ /** Peripheral EWM0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_dsp0_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_dsp0_features.h index ed85b85ab..e5d098b77 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_dsp0_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/MIMX8US5/MIMX8US5_dsp0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 5.0, 2023-04-27 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -297,6 +297,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CASPER module features */ @@ -328,8 +332,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -342,6 +344,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -466,13 +470,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -486,8 +490,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -516,19 +518,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -551,14 +601,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (1) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -659,8 +709,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -703,6 +751,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_CSI2RX module features */ @@ -831,8 +883,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -869,20 +919,29 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (1) + /* TPM module features */ /* @brief Number of channels. */ @@ -907,16 +966,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -932,16 +982,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (0) : \ - (((x) == TPM3) ? (1) : \ - (((x) == TPM4) ? (1) : \ - (((x) == TPM5) ? (0) : \ - (((x) == TPM6) ? (0) : \ - (((x) == TPM7) ? (1) : \ - (((x) == TPM8) ? (1) : (-1)))))))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/periph/PERI_ENET.h index bd4df802d..6156e5853 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8ULP/periph/PERI_ENET.h @@ -62,7 +62,7 @@ ** MIMX8US5DVP08_dsp1 ** ** Version: rev. 6.0, 2024-10-29 -** Build: b250521 +** Build: b250815 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET @@ -1933,9 +1933,6 @@ typedef struct { * @} */ /* end of group ENET_Register_Masks */ -/* ENET Buffer Descriptor and Buffer Address Alignment. */ -#define ENET_BUFF_ALIGNMENT (64U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_COMMON.h index f08c80dd9..560a0f45e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9301_cm33 @@ -904,6 +904,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1013,37 +1016,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3360,13 +3363,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3381,12 +3384,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_features.h index 82da94c20..c5ebd03e8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9301/MIMX9301_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_COMMON.h index 76209860f..7b35479a6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9302_cm33 @@ -904,6 +904,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1013,37 +1016,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3360,13 +3363,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3381,12 +3384,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_features.h index c53dba803..ea439b029 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9302/MIMX9302_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_COMMON.h index 5c7ec5b8f..1ba89817c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9311_cm33 @@ -905,6 +905,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1014,37 +1017,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3361,13 +3364,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3382,12 +3385,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_features.h index fb4468e41..3a0c31a84 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9311/MIMX9311_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_COMMON.h index 6ec84f590..3cfda5964 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9312_cm33 @@ -905,6 +905,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1014,37 +1017,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3361,13 +3364,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3382,12 +3385,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_features.h index 5ef15eb8e..3bc0d3c02 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9312/MIMX9312_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_COMMON.h index c0098ab72..545ac17cd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9321_cm33 @@ -905,6 +905,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1014,37 +1017,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3361,13 +3364,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3382,12 +3385,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_features.h index 01b0169fb..24b02b388 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9321/MIMX9321_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_COMMON.h index 0a151e67b..d844c04a2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9322_cm33 @@ -905,6 +905,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1014,37 +1017,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3361,13 +3364,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3382,12 +3385,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_features.h index 37c8851f8..d81ef7300 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9322/MIMX9322_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_COMMON.h index a0dde7423..a81ccc76f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9331_cm33 @@ -906,6 +906,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1015,37 +1018,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3362,13 +3365,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3383,12 +3386,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_features.h index d95a0bcb0..72d510dc7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9331/MIMX9331_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_COMMON.h index 42dfa431b..1ab78116e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9332_cm33 @@ -906,6 +906,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1015,37 +1018,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3362,13 +3365,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3383,12 +3386,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_features.h index 74e2dff7e..f840a1e27 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9332/MIMX9332_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_COMMON.h index c2dfa6c9e..181c8720b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9351_cm33 @@ -906,6 +906,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1015,37 +1018,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3362,13 +3365,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3383,12 +3386,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_features.h index cce08a70a..b6dab8961 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9351/MIMX9351_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_COMMON.h index f201891f7..884619426 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMX93RM, Internal, November. 2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9352_cm33 @@ -906,6 +906,9 @@ typedef enum IRQn { #define ENET_Error_IRQS { ENET_IRQn } #define ENET_1588_Timer_IRQS { ENET_IRQn } #define ENET_Ts_IRQS { ENET_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + /* ENET_QOS - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1015,37 +1018,37 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } - #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } - #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x38000000u) - #define FlexSPI_AMBA_BASE_NS (0x28000000u) + #define FlexSPI_AMBA_BASE (0x38000000u) + #define FlexSPI_AMBA_BASE_NS (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x38000000u) - #define FlexSPI_ASFM_BASE_NS (0x28000000u) + #define FlexSPI_ASFM_BASE (0x38000000u) + #define FlexSPI_ASFM_BASE_NS (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x57420000u) - #define FlexSPI_ARDF_BASE_NS (0x47420000u) + #define FlexSPI_ARDF_BASE (0x57420000u) + #define FlexSPI_ARDF_BASE_NS (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x57430000u) - #define FlexSPI_ATDF_BASE_NS (0x47430000u) + #define FlexSPI_ATDF_BASE (0x57430000u) + #define FlexSPI_ATDF_BASE_NS (0x47430000u) #else - /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } - /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x2FFFFFFFu} } /* FlexSPI AMBA address. */ - #define FlexSPI_AMBA_BASE (0x28000000u) + #define FlexSPI_AMBA_BASE (0x28000000u) /* FlexSPI ASFM address. */ - #define FlexSPI_ASFM_BASE (0x28000000u) + #define FlexSPI_ASFM_BASE (0x28000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI_ARDF_BASE (0x47420000u) + #define FlexSPI_ARDF_BASE (0x47420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI_ATDF_BASE (0x47430000u) + #define FlexSPI_ATDF_BASE (0x47430000u) #endif @@ -3362,13 +3365,13 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3_NS ((USDHC_Type *)USDHC3_BASE_NS) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS_NS { USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } + #define USDHC_BASE_ADDRS_NS { 0u, USDHC1_BASE_NS, USDHC2_BASE_NS, USDHC3_BASE_NS } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS_NS { USDHC1_NS, USDHC2_NS, USDHC3_NS } + #define USDHC_BASE_PTRS_NS { (USDHC_Type *)0u, USDHC1_NS, USDHC2_NS, USDHC3_NS } #else /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x42850000u) @@ -3383,12 +3386,12 @@ typedef enum IRQn { /** Peripheral USDHC3 base pointer */ #define USDHC3 ((USDHC_Type *)USDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ - #define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } + #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } /** Array initializer of USDHC peripheral base pointers */ - #define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } + #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 } #endif /** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } +#define USDHC_IRQS { NotAvail_IRQn, uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* WAKEUP_AHBRM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_features.h index 51af41bba..6a9a22bbe 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/MIMX9352/MIMX9352_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250506 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -189,6 +189,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* EDMA module features */ @@ -309,13 +313,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -325,8 +329,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -355,6 +357,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -371,7 +375,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -388,6 +392,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -410,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -512,8 +542,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +584,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -638,8 +670,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -674,14 +704,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET.h index 01cf1d751..9a0c21750 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_ENET.h @@ -66,7 +66,7 @@ ** MIMX9352XVVXM_cm33 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250818 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET @@ -2313,9 +2313,6 @@ typedef struct { * @} */ /* end of group ENET_Register_Masks */ -/* ENET Buffer Descriptor and Buffer Address Alignment. */ -#define ENET_BUFF_ALIGNMENT (64U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXSPI.h index a7c5a1383..4dd2de593 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX93/periph/PERI_FLEXSPI.h @@ -66,7 +66,7 @@ ** MIMX9352XVVXM_cm33 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -183,11 +183,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 8u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 8u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 128u @@ -202,11 +202,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -217,7 +217,7 @@ typedef struct { __IO uint32_t DLPR; /**< Data Learning Pattern, offset: 0xB4 */ __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[24]; __I uint32_t STS0; /**< Status 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status 1, offset: 0xE4 */ @@ -797,9 +797,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) - /*! @name FLSHCR0 - Flash Control 0 */ /*! @{ */ @@ -817,9 +814,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_ADDRSHIFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT)) & FLEXSPI_FLSHCR0_ADDRSHIFT_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control 1 */ /*! @{ */ @@ -860,9 +854,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control 2 */ /*! @{ */ @@ -911,9 +902,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control 4 */ /*! @{ */ @@ -1088,9 +1076,6 @@ typedef struct { #define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status 0 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_COMMON.h index a9804f968..988401fe0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_COMMON.h @@ -4116,7 +4116,6 @@ typedef enum } \ } #include "fsl_elec_spec.h" -#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (1700000000UL) /* XSPI - Peripheral instance base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_features.h index 217477baa..72ef67d26 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_features.h @@ -605,7 +605,7 @@ /* MEMORY module features */ /* @brief Memory map has offset between subsystems. */ -#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (0) +#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1) /* MU module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0.h index f08a934e8..ca4b4b717 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0.h @@ -30,8 +30,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: iMX943RM rev1 draftK -** Version: rev. 1.0, 2023-11-01 -** Build: b250115 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX94398_cm33_core0 @@ -66,14 +66,17 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX94398_cm33_core0.h - * @version 1.0 - * @date 2023-11-01 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX94398_cm33_core0 * * CMSIS Peripheral Access Layer for MIMX94398_cm33_core0 @@ -121,9 +124,9 @@ #include "PERI_CCMSRCGPC_TCU.h" #include "PERI_CORTEXA_TCU.h" #include "PERI_DCIF.h" +#include "PERI_DDRC.h" #include "PERI_DDR_BLK_CTRL_DDRMIX.h" #include "PERI_DDR_CMU.h" -#include "PERI_DDR_DDRC.h" #include "PERI_DDR_LSTCU.h" #include "PERI_DDR_TCU.h" #include "PERI_DISPLAY_BLK_CTRL_DISPLAYMIX.h" @@ -314,8 +317,6 @@ #include "PERI_WAKEUP_DMA_CRC.h" #include "PERI_WAKEUP_EIM.h" #include "PERI_WAKEUP_ERM.h" -#include "PERI_WAKEUP_GPT.h" -#include "PERI_WAKEUP_SAI.h" #include "PERI_WAKEUP_TCW.h" #include "PERI_WAKEUP_TRDC_MGR_MEGA.h" #include "PERI_WAKEUP_USDHC.h" diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0_COMMON.h index 45385e014..61950fcd8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0_COMMON.h @@ -30,8 +30,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: iMX943RM rev1 draftK -** Version: rev. 1.0, 2023-11-01 -** Build: b250115 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX94398_cm33_core0 @@ -66,14 +66,17 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX94398_cm33_core0_COMMON.h - * @version 1.0 - * @date 2023-11-01 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX94398_cm33_core0 * * CMSIS Peripheral Access Layer for MIMX94398_cm33_core0 @@ -84,7 +87,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -946,6 +949,1095 @@ typedef enum IRQn { /* CPU specific feature definitions */ #include "MIMX94398_cm33_core0_features.h" +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +typedef enum _xbar_input_signal +{ + kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ + kXBAR1_InputLogicHigh = 1|0x10000U, /**< LOGIC_HIGH output assigned to XBAR1_IN1 input. */ + kXBAR1_InputLogicLow1 = 2|0x10000U, /**< LOGIC_LOW1 output assigned to XBAR1_IN2 input. */ + kXBAR1_InputLogicHigh1 = 3|0x10000U, /**< LOGIC_HIGH1 output assigned to XBAR1_IN3 input. */ + kXBAR1_InputIomuxXbarIn04 = 4|0x10000U, /**< IOMUX_XBAR_IN04 output assigned to XBAR1_IN4 input. */ + kXBAR1_InputIomuxXbarIn05 = 5|0x10000U, /**< IOMUX_XBAR_IN05 output assigned to XBAR1_IN5 input. */ + kXBAR1_InputIomuxXbarIn06 = 6|0x10000U, /**< IOMUX_XBAR_IN06 output assigned to XBAR1_IN6 input. */ + kXBAR1_InputIomuxXbarIn07 = 7|0x10000U, /**< IOMUX_XBAR_IN07 output assigned to XBAR1_IN7 input. */ + kXBAR1_InputIomuxXbarIn08 = 8|0x10000U, /**< IOMUX_XBAR_IN08 output assigned to XBAR1_IN8 input. */ + kXBAR1_InputIomuxXbarIn09 = 9|0x10000U, /**< IOMUX_XBAR_IN09 output assigned to XBAR1_IN9 input. */ + kXBAR1_InputIomuxXbarIn10 = 10|0x10000U, /**< IOMUX_XBAR_IN10 output assigned to XBAR1_IN10 input. */ + kXBAR1_InputIomuxXbarIn11 = 11|0x10000U, /**< IOMUX_XBAR_IN11 output assigned to XBAR1_IN11 input. */ + kXBAR1_InputIomuxXbarIn12 = 12|0x10000U, /**< IOMUX_XBAR_IN12 output assigned to XBAR1_IN12 input. */ + kXBAR1_InputIomuxXbarIn13 = 13|0x10000U, /**< IOMUX_XBAR_IN13 output assigned to XBAR1_IN13 input. */ + kXBAR1_InputIomuxXbarIn14 = 14|0x10000U, /**< IOMUX_XBAR_IN14 output assigned to XBAR1_IN14 input. */ + kXBAR1_InputIomuxXbarIn15 = 15|0x10000U, /**< IOMUX_XBAR_IN15 output assigned to XBAR1_IN15 input. */ + kXBAR1_InputIomuxXbarIn16 = 16|0x10000U, /**< IOMUX_XBAR_IN16 output assigned to XBAR1_IN16 input. */ + kXBAR1_InputIomuxXbarIn17 = 17|0x10000U, /**< IOMUX_XBAR_IN17 output assigned to XBAR1_IN17 input. */ + kXBAR1_InputIomuxXbarIn18 = 18|0x10000U, /**< IOMUX_XBAR_IN18 output assigned to XBAR1_IN18 input. */ + kXBAR1_InputIomuxXbarIn19 = 19|0x10000U, /**< IOMUX_XBAR_IN19 output assigned to XBAR1_IN19 input. */ + kXBAR1_InputIomuxXbarIn20 = 20|0x10000U, /**< IOMUX_XBAR_IN20 output assigned to XBAR1_IN20 input. */ + kXBAR1_InputIomuxXbarIn21 = 21|0x10000U, /**< IOMUX_XBAR_IN21 output assigned to XBAR1_IN21 input. */ + kXBAR1_InputIomuxXbarIn22 = 22|0x10000U, /**< IOMUX_XBAR_IN22 output assigned to XBAR1_IN22 input. */ + kXBAR1_InputIomuxXbarIn23 = 23|0x10000U, /**< IOMUX_XBAR_IN23 output assigned to XBAR1_IN23 input. */ + kXBAR1_InputIomuxXbarIn24 = 24|0x10000U, /**< IOMUX_XBAR_IN24 output assigned to XBAR1_IN24 input. */ + kXBAR1_InputIomuxXbarIn25 = 25|0x10000U, /**< IOMUX_XBAR_IN25 output assigned to XBAR1_IN25 input. */ + kXBAR1_InputIomuxXbarIn26 = 26|0x10000U, /**< IOMUX_XBAR_IN26 output assigned to XBAR1_IN26 input. */ + kXBAR1_InputIomuxXbarIn27 = 27|0x10000U, /**< IOMUX_XBAR_IN27 output assigned to XBAR1_IN27 input. */ + kXBAR1_InputIomuxXbarIn28 = 28|0x10000U, /**< IOMUX_XBAR_IN28 output assigned to XBAR1_IN28 input. */ + kXBAR1_InputIomuxXbarIn29 = 29|0x10000U, /**< IOMUX_XBAR_IN29 output assigned to XBAR1_IN29 input. */ + kXBAR1_InputIomuxXbarIn30 = 30|0x10000U, /**< IOMUX_XBAR_IN30 output assigned to XBAR1_IN30 input. */ + kXBAR1_InputIomuxXbarIn31 = 31|0x10000U, /**< IOMUX_XBAR_IN31 output assigned to XBAR1_IN31 input. */ + kXBAR1_InputIomuxXbarIn32 = 32|0x10000U, /**< IOMUX_XBAR_IN32 output assigned to XBAR1_IN32 input. */ + kXBAR1_InputIomuxXbarIn33 = 33|0x10000U, /**< IOMUX_XBAR_IN33 output assigned to XBAR1_IN33 input. */ + kXBAR1_InputIomuxXbarIn34 = 34|0x10000U, /**< IOMUX_XBAR_IN34 output assigned to XBAR1_IN34 input. */ + kXBAR1_InputIomuxXbarIn35 = 35|0x10000U, /**< IOMUX_XBAR_IN35 output assigned to XBAR1_IN35 input. */ + kXBAR1_InputIomuxXbarIn36 = 36|0x10000U, /**< IOMUX_XBAR_IN36 output assigned to XBAR1_IN36 input. */ + kXBAR1_InputIomuxXbarIn37 = 37|0x10000U, /**< IOMUX_XBAR_IN37 output assigned to XBAR1_IN37 input. */ + kXBAR1_InputIomuxXbarIn38 = 38|0x10000U, /**< IOMUX_XBAR_IN38 output assigned to XBAR1_IN38 input. */ + kXBAR1_InputIomuxXbarIn39 = 39|0x10000U, /**< IOMUX_XBAR_IN39 output assigned to XBAR1_IN39 input. */ + kXBAR1_InputIomuxXbarIn40 = 40|0x10000U, /**< IOMUX_XBAR_IN40 output assigned to XBAR1_IN40 input. */ + kXBAR1_InputIomuxXbarIn41 = 41|0x10000U, /**< IOMUX_XBAR_IN41 output assigned to XBAR1_IN41 input. */ + kXBAR1_InputIomuxXbarIn42 = 42|0x10000U, /**< IOMUX_XBAR_IN42 output assigned to XBAR1_IN42 input. */ + kXBAR1_InputIomuxXbarIn43 = 43|0x10000U, /**< IOMUX_XBAR_IN43 output assigned to XBAR1_IN43 input. */ + kXBAR1_InputIomuxXbarIn44 = 44|0x10000U, /**< IOMUX_XBAR_IN44 output assigned to XBAR1_IN44 input. */ + kXBAR1_InputIomuxXbarIn45 = 45|0x10000U, /**< IOMUX_XBAR_IN45 output assigned to XBAR1_IN45 input. */ + kXBAR1_InputIomuxXbarIn46 = 46|0x10000U, /**< IOMUX_XBAR_IN46 output assigned to XBAR1_IN46 input. */ + kXBAR1_InputIomuxXbarIn47 = 47|0x10000U, /**< IOMUX_XBAR_IN47 output assigned to XBAR1_IN47 input. */ + kXBAR1_InputIomuxXbarIn48 = 48|0x10000U, /**< IOMUX_XBAR_IN48 output assigned to XBAR1_IN48 input. */ + kXBAR1_InputQtimer1Timer0 = 49|0x10000U, /**< QTIMER1_TIMER0 output assigned to XBAR1_IN49 input. */ + kXBAR1_InputQtimer1Timer1 = 50|0x10000U, /**< QTIMER1_TIMER1 output assigned to XBAR1_IN50 input. */ + kXBAR1_InputQtimer1Timer2 = 51|0x10000U, /**< QTIMER1_TIMER2 output assigned to XBAR1_IN51 input. */ + kXBAR1_InputQtimer1Timer3 = 52|0x10000U, /**< QTIMER1_TIMER3 output assigned to XBAR1_IN52 input. */ + kXBAR1_InputQtimer2Timer0 = 53|0x10000U, /**< QTIMER2_TIMER0 output assigned to XBAR1_IN53 input. */ + kXBAR1_InputQtimer2Timer1 = 54|0x10000U, /**< QTIMER2_TIMER1 output assigned to XBAR1_IN54 input. */ + kXBAR1_InputQtimer2Timer2 = 55|0x10000U, /**< QTIMER2_TIMER2 output assigned to XBAR1_IN55 input. */ + kXBAR1_InputQtimer2Timer3 = 56|0x10000U, /**< QTIMER2_TIMER3 output assigned to XBAR1_IN56 input. */ + kXBAR1_InputQtimer3Timer0 = 57|0x10000U, /**< QTIMER3_TIMER0 output assigned to XBAR1_IN57 input. */ + kXBAR1_InputQtimer3Timer1 = 58|0x10000U, /**< QTIMER3_TIMER1 output assigned to XBAR1_IN58 input. */ + kXBAR1_InputQtimer3Timer2 = 59|0x10000U, /**< QTIMER3_TIMER2 output assigned to XBAR1_IN59 input. */ + kXBAR1_InputQtimer3Timer3 = 60|0x10000U, /**< QTIMER3_TIMER3 output assigned to XBAR1_IN60 input. */ + kXBAR1_InputQtimer4Timer0 = 61|0x10000U, /**< QTIMER4_TIMER0 output assigned to XBAR1_IN61 input. */ + kXBAR1_InputQtimer4Timer1 = 62|0x10000U, /**< QTIMER4_TIMER1 output assigned to XBAR1_IN62 input. */ + kXBAR1_InputQtimer4Timer2 = 63|0x10000U, /**< QTIMER4_TIMER2 output assigned to XBAR1_IN63 input. */ + kXBAR1_InputQtimer4Timer3 = 64|0x10000U, /**< QTIMER4_TIMER3 output assigned to XBAR1_IN64 input. */ + kXBAR1_InputQtimer5Timer0 = 65|0x10000U, /**< QTIMER5_TIMER0 output assigned to XBAR1_IN65 input. */ + kXBAR1_InputQtimer5Timer1 = 66|0x10000U, /**< QTIMER5_TIMER1 output assigned to XBAR1_IN66 input. */ + kXBAR1_InputQtimer5Timer2 = 67|0x10000U, /**< QTIMER5_TIMER2 output assigned to XBAR1_IN67 input. */ + kXBAR1_InputQtimer5Timer3 = 68|0x10000U, /**< QTIMER5_TIMER3 output assigned to XBAR1_IN68 input. */ + kXBAR1_InputQtimer6Timer0 = 69|0x10000U, /**< QTIMER6_TIMER0 output assigned to XBAR1_IN69 input. */ + kXBAR1_InputQtimer6Timer1 = 70|0x10000U, /**< QTIMER6_TIMER1 output assigned to XBAR1_IN70 input. */ + kXBAR1_InputQtimer6Timer2 = 71|0x10000U, /**< QTIMER6_TIMER2 output assigned to XBAR1_IN71 input. */ + kXBAR1_InputQtimer6Timer3 = 72|0x10000U, /**< QTIMER6_TIMER3 output assigned to XBAR1_IN72 input. */ + kXBAR1_InputQtimer7Timer0 = 73|0x10000U, /**< QTIMER7_TIMER0 output assigned to XBAR1_IN73 input. */ + kXBAR1_InputQtimer7Timer1 = 74|0x10000U, /**< QTIMER7_TIMER1 output assigned to XBAR1_IN74 input. */ + kXBAR1_InputQtimer7Timer2 = 75|0x10000U, /**< QTIMER7_TIMER2 output assigned to XBAR1_IN75 input. */ + kXBAR1_InputQtimer7Timer3 = 76|0x10000U, /**< QTIMER7_TIMER3 output assigned to XBAR1_IN76 input. */ + kXBAR1_InputQtimer8Timer0 = 77|0x10000U, /**< QTIMER8_TIMER0 output assigned to XBAR1_IN77 input. */ + kXBAR1_InputQtimer8Timer1 = 78|0x10000U, /**< QTIMER8_TIMER1 output assigned to XBAR1_IN78 input. */ + kXBAR1_InputQtimer8Timer2 = 79|0x10000U, /**< QTIMER8_TIMER2 output assigned to XBAR1_IN79 input. */ + kXBAR1_InputQtimer8Timer3 = 80|0x10000U, /**< QTIMER8_TIMER3 output assigned to XBAR1_IN80 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger0 = 81|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR1_IN81 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger0 = 82|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER0 output assigned to XBAR1_IN82 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger1 = 83|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR1_IN83 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger1 = 84|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER1 output assigned to XBAR1_IN84 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger2 = 85|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR1_IN85 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger2 = 86|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER2 output assigned to XBAR1_IN86 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger3 = 87|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR1_IN87 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger3 = 88|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER3 output assigned to XBAR1_IN88 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger0 = 89|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR1_IN89 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger0 = 90|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER0 output assigned to XBAR1_IN90 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger1 = 91|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR1_IN91 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger1 = 92|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER1 output assigned to XBAR1_IN92 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger2 = 93|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR1_IN93 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger2 = 94|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER2 output assigned to XBAR1_IN94 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger3 = 95|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR1_IN95 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger3 = 96|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER3 output assigned to XBAR1_IN96 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger0 = 97|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR1_IN97 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger0 = 98|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER0 output assigned to XBAR1_IN98 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger1 = 99|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR1_IN99 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger1 = 100|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER1 output assigned to XBAR1_IN100 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger2 = 101|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR1_IN101 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger2 = 102|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER2 output assigned to XBAR1_IN102 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger3 = 103|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR1_IN103 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger3 = 104|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER3 output assigned to XBAR1_IN104 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger0 = 105|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR1_IN105 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger0 = 106|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER0 output assigned to XBAR1_IN106 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger1 = 107|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR1_IN107 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger1 = 108|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER1 output assigned to XBAR1_IN108 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger2 = 109|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR1_IN109 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger2 = 110|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER2 output assigned to XBAR1_IN110 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger3 = 111|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR1_IN111 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger3 = 112|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER3 output assigned to XBAR1_IN112 input. */ + kXBAR1_InputLpit1LpitTrigOut0 = 113|0x10000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR1_IN113 input. */ + kXBAR1_InputLpit1LpitTrigOut1 = 114|0x10000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR1_IN114 input. */ + kXBAR1_InputLpit1LpitTrigOut2 = 115|0x10000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR1_IN115 input. */ + kXBAR1_InputLpit1LpitTrigOut3 = 116|0x10000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR1_IN116 input. */ + kXBAR1_InputLpit2LpitTrigOut0 = 117|0x10000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR1_IN117 input. */ + kXBAR1_InputLpit2LpitTrigOut1 = 118|0x10000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR1_IN118 input. */ + kXBAR1_InputLpit2LpitTrigOut2 = 119|0x10000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR1_IN119 input. */ + kXBAR1_InputLpit2LpitTrigOut3 = 120|0x10000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR1_IN120 input. */ + kXBAR1_InputLpit3LpitTrigOut0 = 121|0x10000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR1_IN121 input. */ + kXBAR1_InputLpit3LpitTrigOut1 = 122|0x10000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR1_IN122 input. */ + kXBAR1_InputLpit3LpitTrigOut2 = 123|0x10000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR1_IN123 input. */ + kXBAR1_InputLpit3LpitTrigOut3 = 124|0x10000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR1_IN124 input. */ + kXBAR1_InputTriggerSyncSyncOut0 = 125|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT0 output assigned to XBAR1_IN125 input. */ + kXBAR1_InputTriggerSyncSyncOut1 = 126|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT1 output assigned to XBAR1_IN126 input. */ + kXBAR1_InputTriggerSyncSyncOut2 = 127|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT2 output assigned to XBAR1_IN127 input. */ + kXBAR1_InputTriggerSyncSyncOut3 = 128|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT3 output assigned to XBAR1_IN128 input. */ + kXBAR1_InputEdma2DmaTriggerOut0 = 129|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN129 input. */ + kXBAR1_InputEdma2DmaTriggerOut1 = 130|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN130 input. */ + kXBAR1_InputEdma2DmaTriggerOut2 = 131|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN131 input. */ + kXBAR1_InputEdma2DmaTriggerOut3 = 132|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN132 input. */ + kXBAR1_InputEdma2DmaTriggerOut4 = 133|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN133 input. */ + kXBAR1_InputEdma2DmaTriggerOut5 = 134|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN134 input. */ + kXBAR1_InputEdma2DmaTriggerOut6 = 135|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN135 input. */ + kXBAR1_InputEdma2DmaTriggerOut7 = 136|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN136 input. */ + kXBAR1_InputEdma1DmaTriggerOut0 = 137|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN137 input. */ + kXBAR1_InputEdma1DmaTriggerOut1 = 138|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN138 input. */ + kXBAR1_InputEdma1DmaTriggerOut2 = 139|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN139 input. */ + kXBAR1_InputEdma1DmaTriggerOut3 = 140|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN140 input. */ + kXBAR1_InputEdma1DmaTriggerOut4 = 141|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN141 input. */ + kXBAR1_InputEdma1DmaTriggerOut5 = 142|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN142 input. */ + kXBAR1_InputEdma1DmaTriggerOut6 = 143|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN143 input. */ + kXBAR1_InputEdma1DmaTriggerOut7 = 144|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN144 input. */ + kXBAR1_InputEdma3DmaTriggerOut0 = 145|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN145 input. */ + kXBAR1_InputEdma3DmaTriggerOut1 = 146|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN146 input. */ + kXBAR1_InputEdma3DmaTriggerOut2 = 147|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN147 input. */ + kXBAR1_InputEdma3DmaTriggerOut3 = 148|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN148 input. */ + kXBAR1_InputEdma3DmaTriggerOut4 = 149|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN149 input. */ + kXBAR1_InputEdma3DmaTriggerOut5 = 150|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN150 input. */ + kXBAR1_InputEdma3DmaTriggerOut6 = 151|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN151 input. */ + kXBAR1_InputEdma3DmaTriggerOut7 = 152|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN152 input. */ + kXBAR1_InputEdma4DmaTriggerOut0 = 153|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN153 input. */ + kXBAR1_InputEdma4DmaTriggerOut1 = 154|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN154 input. */ + kXBAR1_InputEdma4DmaTriggerOut2 = 155|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN155 input. */ + kXBAR1_InputEdma4DmaTriggerOut3 = 156|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN156 input. */ + kXBAR1_InputEdma4DmaTriggerOut4 = 157|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN157 input. */ + kXBAR1_InputEdma4DmaTriggerOut5 = 158|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN158 input. */ + kXBAR1_InputEdma4DmaTriggerOut6 = 159|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN159 input. */ + kXBAR1_InputEdma4DmaTriggerOut7 = 160|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN160 input. */ + kXBAR1_InputAdc1IpiIntEoc = 161|0x10000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR1_IN161 input. */ + kXBAR1_InputAdc1IpiIntWd = 162|0x10000U, /**< ADC1_IPI_INT_WD output assigned to XBAR1_IN162 input. */ + kXBAR1_InputTpm1LptpmChTrigger0 = 163|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN163 input. */ + kXBAR1_InputTpm1LptpmChTrigger1 = 164|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN164 input. */ + kXBAR1_InputTpm1LptpmChTrigger2 = 165|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN165 input. */ + kXBAR1_InputTpm1LptpmChTrigger3 = 166|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN166 input. */ + kXBAR1_InputTpm1LptpmTrigger = 167|0x10000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR1_IN167 input. */ + kXBAR1_InputTpm2LptpmChTrigger0 = 168|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN168 input. */ + kXBAR1_InputTpm2LptpmChTrigger1 = 169|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN169 input. */ + kXBAR1_InputTpm2LptpmChTrigger2 = 170|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN170 input. */ + kXBAR1_InputTpm2LptpmChTrigger3 = 171|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN171 input. */ + kXBAR1_InputTpm2LptpmTrigger = 172|0x10000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR1_IN172 input. */ + kXBAR1_InputTpm3LptpmChTrigger0 = 173|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN173 input. */ + kXBAR1_InputTpm3LptpmChTrigger1 = 174|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN174 input. */ + kXBAR1_InputTpm3LptpmChTrigger2 = 175|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN175 input. */ + kXBAR1_InputTpm3LptpmChTrigger3 = 176|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN176 input. */ + kXBAR1_InputTpm3LptpmTrigger = 177|0x10000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR1_IN177 input. */ + kXBAR1_InputTpm4LptpmChTrigger0 = 178|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN178 input. */ + kXBAR1_InputTpm4LptpmChTrigger1 = 179|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN179 input. */ + kXBAR1_InputTpm4LptpmChTrigger2 = 180|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN180 input. */ + kXBAR1_InputTpm4LptpmChTrigger3 = 181|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN181 input. */ + kXBAR1_InputTpm4LptpmTrigger = 182|0x10000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR1_IN182 input. */ + kXBAR1_InputTpm5LptpmChTrigger0 = 183|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN183 input. */ + kXBAR1_InputTpm5LptpmChTrigger1 = 184|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN184 input. */ + kXBAR1_InputTpm5LptpmChTrigger2 = 185|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN185 input. */ + kXBAR1_InputTpm5LptpmChTrigger3 = 186|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN186 input. */ + kXBAR1_InputTpm5LptpmTrigger = 187|0x10000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR1_IN187 input. */ + kXBAR1_InputTpm6LptpmChTrigger0 = 188|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN188 input. */ + kXBAR1_InputTpm6LptpmChTrigger1 = 189|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN189 input. */ + kXBAR1_InputTpm6LptpmChTrigger2 = 190|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN190 input. */ + kXBAR1_InputTpm6LptpmChTrigger3 = 191|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN191 input. */ + kXBAR1_InputTpm6LptpmTrigger = 192|0x10000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR1_IN192 input. */ + kXBAR1_InputLptmr1LptimerTriggerDelay = 193|0x10000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN193 input. */ + kXBAR1_InputLptmr2LptimerTriggerDelay = 194|0x10000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN194 input. */ + kXBAR1_InputLogicLow2 = 195|0x10000U, /**< LOGIC_LOW2 output assigned to XBAR1_IN195 input. */ + kXBAR1_InputNetcTmr11588Pp1 = 196|0x10000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR1_IN196 input. */ + kXBAR1_InputNetcTmr11588Pp2 = 197|0x10000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR1_IN197 input. */ + kXBAR1_InputNetcTmr11588Pp3 = 198|0x10000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR1_IN198 input. */ + kXBAR1_InputNetcTmr11588Alarm1 = 199|0x10000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR1_IN199 input. */ + kXBAR1_InputNetcTmr11588Alarm2 = 200|0x10000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR1_IN200 input. */ + kXBAR1_InputNetcTmr21588Pp1 = 201|0x10000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR1_IN201 input. */ + kXBAR1_InputNetcTmr21588Pp2 = 202|0x10000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR1_IN202 input. */ + kXBAR1_InputNetcTmr21588Pp3 = 203|0x10000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR1_IN203 input. */ + kXBAR1_InputNetcTmr21588Alarm1 = 204|0x10000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR1_IN204 input. */ + kXBAR1_InputNetcTmr21588Alarm2 = 205|0x10000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR1_IN205 input. */ + kXBAR1_InputNetcTmr31588Pp1 = 206|0x10000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR1_IN206 input. */ + kXBAR1_InputNetcTmr31588Pp2 = 207|0x10000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR1_IN207 input. */ + kXBAR1_InputNetcTmr31588Pp3 = 208|0x10000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR1_IN208 input. */ + kXBAR1_InputNetcTmr31588Alarm1 = 209|0x10000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR1_IN209 input. */ + kXBAR1_InputNetcTmr31588Alarm2 = 210|0x10000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR1_IN210 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak0 = 211|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR1_IN211 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak1 = 212|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR1_IN212 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak2 = 213|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR1_IN213 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak3 = 214|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR1_IN214 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak0 = 215|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR1_IN215 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak1 = 216|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR1_IN216 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak2 = 217|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR1_IN217 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak3 = 218|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR1_IN218 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak0 = 219|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR1_IN219 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak1 = 220|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR1_IN220 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak2 = 221|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR1_IN221 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak3 = 222|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR1_IN222 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak0 = 223|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR1_IN223 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak1 = 224|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR1_IN224 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak2 = 225|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR1_IN225 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak3 = 226|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR1_IN226 input. */ + kXBAR1_InputAoi1AoiOut0 = 227|0x10000U, /**< AOI1_AOI_OUT0 output assigned to XBAR1_IN227 input. */ + kXBAR1_InputAoi1AoiOut1 = 228|0x10000U, /**< AOI1_AOI_OUT1 output assigned to XBAR1_IN228 input. */ + kXBAR1_InputAoi1AoiOut2 = 229|0x10000U, /**< AOI1_AOI_OUT2 output assigned to XBAR1_IN229 input. */ + kXBAR1_InputAoi1AoiOut3 = 230|0x10000U, /**< AOI1_AOI_OUT3 output assigned to XBAR1_IN230 input. */ + kXBAR1_InputAoi2AoiOut0 = 231|0x10000U, /**< AOI2_AOI_OUT0 output assigned to XBAR1_IN231 input. */ + kXBAR1_InputAoi2AoiOut1 = 232|0x10000U, /**< AOI2_AOI_OUT1 output assigned to XBAR1_IN232 input. */ + kXBAR1_InputAoi2AoiOut2 = 233|0x10000U, /**< AOI2_AOI_OUT2 output assigned to XBAR1_IN233 input. */ + kXBAR1_InputAoi2AoiOut3 = 234|0x10000U, /**< AOI2_AOI_OUT3 output assigned to XBAR1_IN234 input. */ + kXBAR1_InputTriggerSyncSyncOut4 = 235|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT4 output assigned to XBAR1_IN235 input. */ + kXBAR1_InputTriggerSyncSyncOut5 = 236|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT5 output assigned to XBAR1_IN236 input. */ + kXBAR1_InputTriggerSyncSyncOut6 = 237|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT6 output assigned to XBAR1_IN237 input. */ + kXBAR1_InputTriggerSyncSyncOut7 = 238|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT7 output assigned to XBAR1_IN238 input. */ + kXBAR1_InputAoi3AoiOut0 = 239|0x10000U, /**< AOI3_AOI_OUT0 output assigned to XBAR1_IN239 input. */ + kXBAR1_InputAoi3AoiOut1 = 240|0x10000U, /**< AOI3_AOI_OUT1 output assigned to XBAR1_IN240 input. */ + kXBAR1_InputAoi3AoiOut2 = 241|0x10000U, /**< AOI3_AOI_OUT2 output assigned to XBAR1_IN241 input. */ + kXBAR1_InputAoi3AoiOut3 = 242|0x10000U, /**< AOI3_AOI_OUT3 output assigned to XBAR1_IN242 input. */ + kXBAR1_InputAoi4AoiOut0 = 243|0x10000U, /**< AOI4_AOI_OUT0 output assigned to XBAR1_IN243 input. */ + kXBAR1_InputAoi4AoiOut1 = 244|0x10000U, /**< AOI4_AOI_OUT1 output assigned to XBAR1_IN244 input. */ + kXBAR1_InputAoi4AoiOut2 = 245|0x10000U, /**< AOI4_AOI_OUT2 output assigned to XBAR1_IN245 input. */ + kXBAR1_InputAoi4AoiOut3 = 246|0x10000U, /**< AOI4_AOI_OUT3 output assigned to XBAR1_IN246 input. */ + kXBAR1_InputEcatSyncOut0 = 247|0x10000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR1_IN247 input. */ + kXBAR1_InputEcatSyncOut1 = 248|0x10000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR1_IN248 input. */ + kXBAR1_InputFccuVfccuReactionsOut11 = 249|0x10000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR1_IN249 input. */ + kXBAR1_InputGpt1IppDoCmpout1 = 250|0x10000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR1_IN250 input. */ + kXBAR1_InputGpt1IppDoCmpout2 = 251|0x10000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR1_IN251 input. */ + kXBAR1_InputGpt1IppDoCmpout3 = 252|0x10000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR1_IN252 input. */ + kXBAR1_InputGpt2IppDoCmpout1 = 253|0x10000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR1_IN253 input. */ + kXBAR1_InputGpt2IppDoCmpout2 = 254|0x10000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR1_IN254 input. */ + kXBAR1_InputGpt2IppDoCmpout3 = 255|0x10000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR1_IN255 input. */ + kXBAR1_InputGpt3IppDoCmpout1 = 256|0x10000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR1_IN256 input. */ + kXBAR1_InputGpt3IppDoCmpout2 = 257|0x10000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR1_IN257 input. */ + kXBAR1_InputGpt3IppDoCmpout3 = 258|0x10000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR1_IN258 input. */ + kXBAR1_InputGpt4IppDoCmpout1 = 259|0x10000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR1_IN259 input. */ + kXBAR1_InputGpt4IppDoCmpout2 = 260|0x10000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR1_IN260 input. */ + kXBAR1_InputGpt4IppDoCmpout3 = 261|0x10000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR1_IN261 input. */ + kXBAR1_InputFlexio1FlexioTriggerOut0 = 262|0x10000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN262 input. */ + kXBAR1_InputFlexio2FlexioTriggerOut0 = 263|0x10000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN263 input. */ + kXBAR1_InputFlexio3FlexioTriggerOut0 = 264|0x10000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN264 input. */ + kXBAR1_InputFlexio4FlexioTriggerOut0 = 265|0x10000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN265 input. */ + kXBAR1_InputGpio1IpiIntRgpio0 = 266|0x10000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR1_IN266 input. */ + kXBAR1_InputGpio2IpiIntRgpio0 = 267|0x10000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR1_IN267 input. */ + kXBAR1_InputGpio3IpiIntRgpio0 = 268|0x10000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR1_IN268 input. */ + kXBAR1_InputGpio4IpiIntRgpio0 = 269|0x10000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR1_IN269 input. */ + kXBAR1_InputGpio5IpiIntRgpio0 = 270|0x10000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR1_IN270 input. */ + kXBAR1_InputGpio6IpiIntRgpio0 = 271|0x10000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR1_IN271 input. */ + kXBAR1_InputGpio7IpiIntRgpio0 = 272|0x10000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR1_IN272 input. */ + kXBAR1_InputCm33Txev = 273|0x10000U, /**< CM33_TXEV output assigned to XBAR1_IN273 input. */ + kXBAR1_InputCm33SyncTxev = 274|0x10000U, /**< CM33_SYNC_TXEV output assigned to XBAR1_IN274 input. */ + kXBAR1_InputEndat21SiN = 275|0x10000U, /**< ENDAT2_1_SI_N output assigned to XBAR1_IN275 input. */ + kXBAR1_InputEndat21TimerN = 276|0x10000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR1_IN276 input. */ + kXBAR1_InputEndat22SiN = 277|0x10000U, /**< ENDAT2_2_SI_N output assigned to XBAR1_IN277 input. */ + kXBAR1_InputEndat22TimerN = 278|0x10000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR1_IN278 input. */ + kXBAR1_InputBissEot = 279|0x10000U, /**< BISS_EOT output assigned to XBAR1_IN279 input. */ + kXBAR1_InputTriggerSyncSyncOut8 = 280|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT8 output assigned to XBAR1_IN280 input. */ + kXBAR1_InputTriggerSyncSyncOut9 = 281|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT9 output assigned to XBAR1_IN281 input. */ + kXBAR1_InputTriggerSyncSyncOut10 = 282|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT10 output assigned to XBAR1_IN282 input. */ + kXBAR1_InputTriggerSyncSyncOut11 = 283|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT11 output assigned to XBAR1_IN283 input. */ + kXBAR1_InputTriggerSyncSyncOut12 = 284|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT12 output assigned to XBAR1_IN284 input. */ + kXBAR1_InputTriggerSyncSyncOut13 = 285|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT13 output assigned to XBAR1_IN285 input. */ + kXBAR1_InputTriggerSyncSyncOut14 = 286|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT14 output assigned to XBAR1_IN286 input. */ + kXBAR1_InputTriggerSyncSyncOut15 = 287|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT15 output assigned to XBAR1_IN287 input. */ + kXBAR1_InputEcatResetOut = 288|0x10000U, /**< ECAT_RESET_OUT output assigned to XBAR1_IN288 input. */ + kXBAR1_InputHiperface1FastPosRcvdEvt = 289|0x10000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR1_IN289 input. */ + kXBAR1_InputHiperface2FastPosRcvdEvt = 290|0x10000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR1_IN290 input. */ + kXBAR2_InputLogicLow = 0|0x20000U, /**< LOGIC_LOW output assigned to XBAR2_IN0 input. */ + kXBAR2_InputLogicHigh = 1|0x20000U, /**< LOGIC_HIGH output assigned to XBAR2_IN1 input. */ + kXBAR2_InputLogicLow1 = 2|0x20000U, /**< LOGIC_LOW1 output assigned to XBAR2_IN2 input. */ + kXBAR2_InputLogicHigh1 = 3|0x20000U, /**< LOGIC_HIGH1 output assigned to XBAR2_IN3 input. */ + kXBAR2_InputQtimer1Timer0 = 4|0x20000U, /**< QTIMER1_TIMER0 output assigned to XBAR2_IN4 input. */ + kXBAR2_InputQtimer1Timer1 = 5|0x20000U, /**< QTIMER1_TIMER1 output assigned to XBAR2_IN5 input. */ + kXBAR2_InputQtimer1Timer2 = 6|0x20000U, /**< QTIMER1_TIMER2 output assigned to XBAR2_IN6 input. */ + kXBAR2_InputQtimer1Timer3 = 7|0x20000U, /**< QTIMER1_TIMER3 output assigned to XBAR2_IN7 input. */ + kXBAR2_InputQtimer2Timer0 = 8|0x20000U, /**< QTIMER2_TIMER0 output assigned to XBAR2_IN8 input. */ + kXBAR2_InputQtimer2Timer1 = 9|0x20000U, /**< QTIMER2_TIMER1 output assigned to XBAR2_IN9 input. */ + kXBAR2_InputQtimer2Timer2 = 10|0x20000U, /**< QTIMER2_TIMER2 output assigned to XBAR2_IN10 input. */ + kXBAR2_InputQtimer2Timer3 = 11|0x20000U, /**< QTIMER2_TIMER3 output assigned to XBAR2_IN11 input. */ + kXBAR2_InputQtimer3Timer0 = 12|0x20000U, /**< QTIMER3_TIMER0 output assigned to XBAR2_IN12 input. */ + kXBAR2_InputQtimer3Timer1 = 13|0x20000U, /**< QTIMER3_TIMER1 output assigned to XBAR2_IN13 input. */ + kXBAR2_InputQtimer3Timer2 = 14|0x20000U, /**< QTIMER3_TIMER2 output assigned to XBAR2_IN14 input. */ + kXBAR2_InputQtimer3Timer3 = 15|0x20000U, /**< QTIMER3_TIMER3 output assigned to XBAR2_IN15 input. */ + kXBAR2_InputQtimer4Timer0 = 16|0x20000U, /**< QTIMER4_TIMER0 output assigned to XBAR2_IN16 input. */ + kXBAR2_InputQtimer4Timer1 = 17|0x20000U, /**< QTIMER4_TIMER1 output assigned to XBAR2_IN17 input. */ + kXBAR2_InputQtimer4Timer2 = 18|0x20000U, /**< QTIMER4_TIMER2 output assigned to XBAR2_IN18 input. */ + kXBAR2_InputQtimer4Timer3 = 19|0x20000U, /**< QTIMER4_TIMER3 output assigned to XBAR2_IN19 input. */ + kXBAR2_InputQtimer5Timer0 = 20|0x20000U, /**< QTIMER5_TIMER0 output assigned to XBAR2_IN20 input. */ + kXBAR2_InputQtimer5Timer1 = 21|0x20000U, /**< QTIMER5_TIMER1 output assigned to XBAR2_IN21 input. */ + kXBAR2_InputQtimer5Timer2 = 22|0x20000U, /**< QTIMER5_TIMER2 output assigned to XBAR2_IN22 input. */ + kXBAR2_InputQtimer5Timer3 = 23|0x20000U, /**< QTIMER5_TIMER3 output assigned to XBAR2_IN23 input. */ + kXBAR2_InputQtimer6Timer0 = 24|0x20000U, /**< QTIMER6_TIMER0 output assigned to XBAR2_IN24 input. */ + kXBAR2_InputQtimer6Timer1 = 25|0x20000U, /**< QTIMER6_TIMER1 output assigned to XBAR2_IN25 input. */ + kXBAR2_InputQtimer6Timer2 = 26|0x20000U, /**< QTIMER6_TIMER2 output assigned to XBAR2_IN26 input. */ + kXBAR2_InputQtimer6Timer3 = 27|0x20000U, /**< QTIMER6_TIMER3 output assigned to XBAR2_IN27 input. */ + kXBAR2_InputQtimer7Timer0 = 28|0x20000U, /**< QTIMER7_TIMER0 output assigned to XBAR2_IN28 input. */ + kXBAR2_InputQtimer7Timer1 = 29|0x20000U, /**< QTIMER7_TIMER1 output assigned to XBAR2_IN29 input. */ + kXBAR2_InputQtimer7Timer2 = 30|0x20000U, /**< QTIMER7_TIMER2 output assigned to XBAR2_IN30 input. */ + kXBAR2_InputQtimer7Timer3 = 31|0x20000U, /**< QTIMER7_TIMER3 output assigned to XBAR2_IN31 input. */ + kXBAR2_InputQtimer8Timer0 = 32|0x20000U, /**< QTIMER8_TIMER0 output assigned to XBAR2_IN32 input. */ + kXBAR2_InputQtimer8Timer1 = 33|0x20000U, /**< QTIMER8_TIMER1 output assigned to XBAR2_IN33 input. */ + kXBAR2_InputQtimer8Timer2 = 34|0x20000U, /**< QTIMER8_TIMER2 output assigned to XBAR2_IN34 input. */ + kXBAR2_InputQtimer8Timer3 = 35|0x20000U, /**< QTIMER8_TIMER3 output assigned to XBAR2_IN35 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger0 = 36|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR2_IN36 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger1 = 37|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR2_IN37 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger2 = 38|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR2_IN38 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger3 = 39|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR2_IN39 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger0 = 40|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR2_IN40 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger1 = 41|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR2_IN41 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger2 = 42|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR2_IN42 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger3 = 43|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR2_IN43 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger0 = 44|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR2_IN44 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger1 = 45|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR2_IN45 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger2 = 46|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR2_IN46 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger3 = 47|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR2_IN47 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger0 = 48|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR2_IN48 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger1 = 49|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR2_IN49 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger2 = 50|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR2_IN50 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger3 = 51|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR2_IN51 input. */ + kXBAR2_InputLpit1LpitTrigOut0 = 52|0x20000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR2_IN52 input. */ + kXBAR2_InputLpit1LpitTrigOut1 = 53|0x20000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR2_IN53 input. */ + kXBAR2_InputLpit1LpitTrigOut2 = 54|0x20000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR2_IN54 input. */ + kXBAR2_InputLpit1LpitTrigOut3 = 55|0x20000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR2_IN55 input. */ + kXBAR2_InputLpit2LpitTrigOut0 = 56|0x20000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR2_IN56 input. */ + kXBAR2_InputLpit2LpitTrigOut1 = 57|0x20000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR2_IN57 input. */ + kXBAR2_InputLpit2LpitTrigOut2 = 58|0x20000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR2_IN58 input. */ + kXBAR2_InputLpit2LpitTrigOut3 = 59|0x20000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR2_IN59 input. */ + kXBAR2_InputLpit3LpitTrigOut0 = 60|0x20000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR2_IN60 input. */ + kXBAR2_InputLpit3LpitTrigOut1 = 61|0x20000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR2_IN61 input. */ + kXBAR2_InputLpit3LpitTrigOut2 = 62|0x20000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR2_IN62 input. */ + kXBAR2_InputLpit3LpitTrigOut3 = 63|0x20000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR2_IN63 input. */ + kXBAR2_InputEdma2DmaTriggerOut0 = 64|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN64 input. */ + kXBAR2_InputEdma2DmaTriggerOut1 = 65|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN65 input. */ + kXBAR2_InputEdma2DmaTriggerOut2 = 66|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN66 input. */ + kXBAR2_InputEdma2DmaTriggerOut3 = 67|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN67 input. */ + kXBAR2_InputEdma2DmaTriggerOut4 = 68|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN68 input. */ + kXBAR2_InputEdma2DmaTriggerOut5 = 69|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN69 input. */ + kXBAR2_InputEdma2DmaTriggerOut6 = 70|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN70 input. */ + kXBAR2_InputEdma2DmaTriggerOut7 = 71|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN71 input. */ + kXBAR2_InputEdma1DmaTriggerOut0 = 72|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN72 input. */ + kXBAR2_InputEdma1DmaTriggerOut1 = 73|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN73 input. */ + kXBAR2_InputEdma1DmaTriggerOut2 = 74|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN74 input. */ + kXBAR2_InputEdma1DmaTriggerOut3 = 75|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN75 input. */ + kXBAR2_InputEdma1DmaTriggerOut4 = 76|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN76 input. */ + kXBAR2_InputEdma1DmaTriggerOut5 = 77|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN77 input. */ + kXBAR2_InputEdma1DmaTriggerOut6 = 78|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN78 input. */ + kXBAR2_InputEdma1DmaTriggerOut7 = 79|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN79 input. */ + kXBAR2_InputEdma3DmaTriggerOut0 = 80|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN80 input. */ + kXBAR2_InputEdma3DmaTriggerOut1 = 81|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN81 input. */ + kXBAR2_InputEdma3DmaTriggerOut2 = 82|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN82 input. */ + kXBAR2_InputEdma3DmaTriggerOut3 = 83|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN83 input. */ + kXBAR2_InputEdma3DmaTriggerOut4 = 84|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN84 input. */ + kXBAR2_InputEdma3DmaTriggerOut5 = 85|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN85 input. */ + kXBAR2_InputEdma3DmaTriggerOut6 = 86|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN86 input. */ + kXBAR2_InputEdma3DmaTriggerOut7 = 87|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN87 input. */ + kXBAR2_InputEdma4DmaTriggerOut0 = 88|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN88 input. */ + kXBAR2_InputEdma4DmaTriggerOut1 = 89|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN89 input. */ + kXBAR2_InputEdma4DmaTriggerOut2 = 90|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN90 input. */ + kXBAR2_InputEdma4DmaTriggerOut3 = 91|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN91 input. */ + kXBAR2_InputEdma4DmaTriggerOut4 = 92|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN92 input. */ + kXBAR2_InputEdma4DmaTriggerOut5 = 93|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN93 input. */ + kXBAR2_InputEdma4DmaTriggerOut6 = 94|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN94 input. */ + kXBAR2_InputEdma4DmaTriggerOut7 = 95|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN95 input. */ + kXBAR2_InputAdc1IpiIntEoc = 96|0x20000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR2_IN96 input. */ + kXBAR2_InputAdc1IpiIntWd = 97|0x20000U, /**< ADC1_IPI_INT_WD output assigned to XBAR2_IN97 input. */ + kXBAR2_InputTpm1LptpmChTrigger0 = 98|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN98 input. */ + kXBAR2_InputTpm1LptpmChTrigger1 = 99|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN99 input. */ + kXBAR2_InputTpm1LptpmChTrigger2 = 100|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN100 input. */ + kXBAR2_InputTpm1LptpmChTrigger3 = 101|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN101 input. */ + kXBAR2_InputTpm1LptpmTrigger = 102|0x20000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR2_IN102 input. */ + kXBAR2_InputTpm2LptpmChTrigger0 = 103|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN103 input. */ + kXBAR2_InputTpm2LptpmChTrigger1 = 104|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN104 input. */ + kXBAR2_InputTpm2LptpmChTrigger2 = 105|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN105 input. */ + kXBAR2_InputTpm2LptpmChTrigger3 = 106|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN106 input. */ + kXBAR2_InputTpm2LptpmTrigger = 107|0x20000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR2_IN107 input. */ + kXBAR2_InputTpm3LptpmChTrigger0 = 108|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN108 input. */ + kXBAR2_InputTpm3LptpmChTrigger1 = 109|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN109 input. */ + kXBAR2_InputTpm3LptpmChTrigger2 = 110|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN110 input. */ + kXBAR2_InputTpm3LptpmChTrigger3 = 111|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN111 input. */ + kXBAR2_InputTpm3LptpmTrigger = 112|0x20000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR2_IN112 input. */ + kXBAR2_InputTpm4LptpmChTrigger0 = 113|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN113 input. */ + kXBAR2_InputTpm4LptpmChTrigger1 = 114|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN114 input. */ + kXBAR2_InputTpm4LptpmChTrigger2 = 115|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN115 input. */ + kXBAR2_InputTpm4LptpmChTrigger3 = 116|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN116 input. */ + kXBAR2_InputTpm4LptpmTrigger = 117|0x20000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR2_IN117 input. */ + kXBAR2_InputTpm5LptpmChTrigger0 = 118|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN118 input. */ + kXBAR2_InputTpm5LptpmChTrigger1 = 119|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN119 input. */ + kXBAR2_InputTpm5LptpmChTrigger2 = 120|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN120 input. */ + kXBAR2_InputTpm5LptpmChTrigger3 = 121|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN121 input. */ + kXBAR2_InputTpm5LptpmTrigger = 122|0x20000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR2_IN122 input. */ + kXBAR2_InputTpm6LptpmChTrigger0 = 123|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN123 input. */ + kXBAR2_InputTpm6LptpmChTrigger1 = 124|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN124 input. */ + kXBAR2_InputTpm6LptpmChTrigger2 = 125|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN125 input. */ + kXBAR2_InputTpm6LptpmChTrigger3 = 126|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN126 input. */ + kXBAR2_InputTpm6LptpmTrigger = 127|0x20000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR2_IN127 input. */ + kXBAR2_InputLptmr1LptimerTriggerDelay = 128|0x20000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN128 input. */ + kXBAR2_InputLptmr2LptimerTriggerDelay = 129|0x20000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN129 input. */ + kXBAR2_InputLogicLow2 = 130|0x20000U, /**< LOGIC_LOW2 output assigned to XBAR2_IN130 input. */ + kXBAR2_InputNetcTmr11588Pp1 = 131|0x20000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR2_IN131 input. */ + kXBAR2_InputNetcTmr11588Pp2 = 132|0x20000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR2_IN132 input. */ + kXBAR2_InputNetcTmr11588Pp3 = 133|0x20000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR2_IN133 input. */ + kXBAR2_InputNetcTmr11588Alarm1 = 134|0x20000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR2_IN134 input. */ + kXBAR2_InputNetcTmr11588Alarm2 = 135|0x20000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR2_IN135 input. */ + kXBAR2_InputNetcTmr21588Pp1 = 136|0x20000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR2_IN136 input. */ + kXBAR2_InputNetcTmr21588Pp2 = 137|0x20000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR2_IN137 input. */ + kXBAR2_InputNetcTmr21588Pp3 = 138|0x20000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR2_IN138 input. */ + kXBAR2_InputNetcTmr21588Alarm1 = 139|0x20000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR2_IN139 input. */ + kXBAR2_InputNetcTmr21588Alarm2 = 140|0x20000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR2_IN140 input. */ + kXBAR2_InputNetcTmr31588Pp1 = 141|0x20000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR2_IN141 input. */ + kXBAR2_InputNetcTmr31588Pp2 = 142|0x20000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR2_IN142 input. */ + kXBAR2_InputNetcTmr31588Pp3 = 143|0x20000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR2_IN143 input. */ + kXBAR2_InputNetcTmr31588Alarm1 = 144|0x20000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR2_IN144 input. */ + kXBAR2_InputNetcTmr31588Alarm2 = 145|0x20000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR2_IN145 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak0 = 146|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR2_IN146 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak1 = 147|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR2_IN147 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak2 = 148|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR2_IN148 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak3 = 149|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR2_IN149 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak0 = 150|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR2_IN150 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak1 = 151|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR2_IN151 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak2 = 152|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR2_IN152 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak3 = 153|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR2_IN153 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak0 = 154|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR2_IN154 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak1 = 155|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR2_IN155 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak2 = 156|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR2_IN156 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak3 = 157|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR2_IN157 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak0 = 158|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR2_IN158 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak1 = 159|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR2_IN159 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak2 = 160|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR2_IN160 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak3 = 161|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR2_IN161 input. */ + kXBAR2_InputSinc1PulseTrg0 = 162|0x20000U, /**< SINC1_PULSE_TRG0 output assigned to XBAR2_IN162 input. */ + kXBAR2_InputSinc1PulseTrg1 = 163|0x20000U, /**< SINC1_PULSE_TRG1 output assigned to XBAR2_IN163 input. */ + kXBAR2_InputSinc1PulseTrg2 = 164|0x20000U, /**< SINC1_PULSE_TRG2 output assigned to XBAR2_IN164 input. */ + kXBAR2_InputSinc1PulseTrg3 = 165|0x20000U, /**< SINC1_PULSE_TRG3 output assigned to XBAR2_IN165 input. */ + kXBAR2_InputSinc3PulseTrg0 = 166|0x20000U, /**< SINC3_PULSE_TRG0 output assigned to XBAR2_IN166 input. */ + kXBAR2_InputSinc3PulseTrg1 = 167|0x20000U, /**< SINC3_PULSE_TRG1 output assigned to XBAR2_IN167 input. */ + kXBAR2_InputSinc3PulseTrg2 = 168|0x20000U, /**< SINC3_PULSE_TRG2 output assigned to XBAR2_IN168 input. */ + kXBAR2_InputSinc3PulseTrg3 = 169|0x20000U, /**< SINC3_PULSE_TRG3 output assigned to XBAR2_IN169 input. */ + kXBAR2_InputEcatSyncOut0 = 170|0x20000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR2_IN170 input. */ + kXBAR2_InputEcatSyncOut1 = 171|0x20000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR2_IN171 input. */ + kXBAR2_InputFccuVfccuReactionsOut11 = 172|0x20000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR2_IN172 input. */ + kXBAR2_InputGpt1IppDoCmpout1 = 173|0x20000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR2_IN173 input. */ + kXBAR2_InputGpt1IppDoCmpout2 = 174|0x20000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR2_IN174 input. */ + kXBAR2_InputGpt1IppDoCmpout3 = 175|0x20000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR2_IN175 input. */ + kXBAR2_InputGpt2IppDoCmpout1 = 176|0x20000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR2_IN176 input. */ + kXBAR2_InputGpt2IppDoCmpout2 = 177|0x20000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR2_IN177 input. */ + kXBAR2_InputGpt2IppDoCmpout3 = 178|0x20000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR2_IN178 input. */ + kXBAR2_InputGpt3IppDoCmpout1 = 179|0x20000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR2_IN179 input. */ + kXBAR2_InputGpt3IppDoCmpout2 = 180|0x20000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR2_IN180 input. */ + kXBAR2_InputGpt3IppDoCmpout3 = 181|0x20000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR2_IN181 input. */ + kXBAR2_InputGpt4IppDoCmpout1 = 182|0x20000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR2_IN182 input. */ + kXBAR2_InputGpt4IppDoCmpout2 = 183|0x20000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR2_IN183 input. */ + kXBAR2_InputGpt4IppDoCmpout3 = 184|0x20000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR2_IN184 input. */ + kXBAR2_InputFlexio1FlexioTriggerOut0 = 185|0x20000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN185 input. */ + kXBAR2_InputFlexio2FlexioTriggerOut0 = 186|0x20000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN186 input. */ + kXBAR2_InputFlexio3FlexioTriggerOut0 = 187|0x20000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN187 input. */ + kXBAR2_InputFlexio4FlexioTriggerOut0 = 188|0x20000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN188 input. */ + kXBAR2_InputGpio1IpiIntRgpio0 = 189|0x20000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR2_IN189 input. */ + kXBAR2_InputGpio2IpiIntRgpio0 = 190|0x20000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR2_IN190 input. */ + kXBAR2_InputGpio3IpiIntRgpio0 = 191|0x20000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR2_IN191 input. */ + kXBAR2_InputGpio4IpiIntRgpio0 = 192|0x20000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR2_IN192 input. */ + kXBAR2_InputGpio5IpiIntRgpio0 = 193|0x20000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR2_IN193 input. */ + kXBAR2_InputGpio6IpiIntRgpio0 = 194|0x20000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR2_IN194 input. */ + kXBAR2_InputGpio7IpiIntRgpio0 = 195|0x20000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR2_IN195 input. */ + kXBAR2_InputCm33Txev = 196|0x20000U, /**< CM33_TXEV output assigned to XBAR2_IN196 input. */ + kXBAR2_InputCm33SyncTxev = 197|0x20000U, /**< CM33_SYNC_TXEV output assigned to XBAR2_IN197 input. */ + kXBAR2_InputEndat21SiN = 198|0x20000U, /**< ENDAT2_1_SI_N output assigned to XBAR2_IN198 input. */ + kXBAR2_InputEndat21TimerN = 199|0x20000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR2_IN199 input. */ + kXBAR2_InputEndat22SiN = 200|0x20000U, /**< ENDAT2_2_SI_N output assigned to XBAR2_IN200 input. */ + kXBAR2_InputEndat22TimerN = 201|0x20000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR2_IN201 input. */ + kXBAR2_InputBissEot = 202|0x20000U, /**< BISS_EOT output assigned to XBAR2_IN202 input. */ + kXBAR2_InputEnc1PosMatch0 = 203|0x20000U, /**< ENC1_POS_MATCH0 output assigned to XBAR2_IN203 input. */ + kXBAR2_InputEnc1PosMatch1 = 204|0x20000U, /**< ENC1_POS_MATCH1 output assigned to XBAR2_IN204 input. */ + kXBAR2_InputEnc1PosMatch2 = 205|0x20000U, /**< ENC1_POS_MATCH2 output assigned to XBAR2_IN205 input. */ + kXBAR2_InputEnc1PosMatch3 = 206|0x20000U, /**< ENC1_POS_MATCH3 output assigned to XBAR2_IN206 input. */ + kXBAR2_InputEnc1CompFlg0 = 207|0x20000U, /**< ENC1_COMP_FLG0 output assigned to XBAR2_IN207 input. */ + kXBAR2_InputEnc1CompFlg1 = 208|0x20000U, /**< ENC1_COMP_FLG1 output assigned to XBAR2_IN208 input. */ + kXBAR2_InputEnc1CompFlg2 = 209|0x20000U, /**< ENC1_COMP_FLG2 output assigned to XBAR2_IN209 input. */ + kXBAR2_InputEnc1CompFlg3 = 210|0x20000U, /**< ENC1_COMP_FLG3 output assigned to XBAR2_IN210 input. */ + kXBAR2_InputEnc1CntDn = 211|0x20000U, /**< ENC1_CNT_DN output assigned to XBAR2_IN211 input. */ + kXBAR2_InputEnc1CntUp = 212|0x20000U, /**< ENC1_CNT_UP output assigned to XBAR2_IN212 input. */ + kXBAR2_InputEnc1Dir = 213|0x20000U, /**< ENC1_DIR output assigned to XBAR2_IN213 input. */ + kXBAR2_InputEnc3PosMatch0 = 214|0x20000U, /**< ENC3_POS_MATCH0 output assigned to XBAR2_IN214 input. */ + kXBAR2_InputEnc3PosMatch1 = 215|0x20000U, /**< ENC3_POS_MATCH1 output assigned to XBAR2_IN215 input. */ + kXBAR2_InputEnc3PosMatch2 = 216|0x20000U, /**< ENC3_POS_MATCH2 output assigned to XBAR2_IN216 input. */ + kXBAR2_InputEnc3PosMatch3 = 217|0x20000U, /**< ENC3_POS_MATCH3 output assigned to XBAR2_IN217 input. */ + kXBAR2_InputEnc3CompFlg0 = 218|0x20000U, /**< ENC3_COMP_FLG0 output assigned to XBAR2_IN218 input. */ + kXBAR2_InputEnc3CompFlg1 = 219|0x20000U, /**< ENC3_COMP_FLG1 output assigned to XBAR2_IN219 input. */ + kXBAR2_InputEnc3CompFlg2 = 220|0x20000U, /**< ENC3_COMP_FLG2 output assigned to XBAR2_IN220 input. */ + kXBAR2_InputEnc3CompFlg3 = 221|0x20000U, /**< ENC3_COMP_FLG3 output assigned to XBAR2_IN221 input. */ + kXBAR2_InputEnc3CntDn = 222|0x20000U, /**< ENC3_CNT_DN output assigned to XBAR2_IN222 input. */ + kXBAR2_InputEnc3CntUp = 223|0x20000U, /**< ENC3_CNT_UP output assigned to XBAR2_IN223 input. */ + kXBAR2_InputEnc3Dir = 224|0x20000U, /**< ENC3_DIR output assigned to XBAR2_IN224 input. */ + kXBAR2_InputHiperface1FastPosRcvdEvt = 225|0x20000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR2_IN225 input. */ + kXBAR2_InputHiperface2FastPosRcvdEvt = 226|0x20000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR2_IN226 input. */ + kXBAR3_InputLogicLow = 0|0x30000U, /**< LOGIC_LOW output assigned to XBAR3_IN0 input. */ + kXBAR3_InputLogicHigh = 1|0x30000U, /**< LOGIC_HIGH output assigned to XBAR3_IN1 input. */ + kXBAR3_InputLogicLow1 = 2|0x30000U, /**< LOGIC_LOW1 output assigned to XBAR3_IN2 input. */ + kXBAR3_InputLogicHigh1 = 3|0x30000U, /**< LOGIC_HIGH1 output assigned to XBAR3_IN3 input. */ + kXBAR3_InputQtimer1Timer0 = 4|0x30000U, /**< QTIMER1_TIMER0 output assigned to XBAR3_IN4 input. */ + kXBAR3_InputQtimer1Timer1 = 5|0x30000U, /**< QTIMER1_TIMER1 output assigned to XBAR3_IN5 input. */ + kXBAR3_InputQtimer1Timer2 = 6|0x30000U, /**< QTIMER1_TIMER2 output assigned to XBAR3_IN6 input. */ + kXBAR3_InputQtimer1Timer3 = 7|0x30000U, /**< QTIMER1_TIMER3 output assigned to XBAR3_IN7 input. */ + kXBAR3_InputQtimer2Timer0 = 8|0x30000U, /**< QTIMER2_TIMER0 output assigned to XBAR3_IN8 input. */ + kXBAR3_InputQtimer2Timer1 = 9|0x30000U, /**< QTIMER2_TIMER1 output assigned to XBAR3_IN9 input. */ + kXBAR3_InputQtimer2Timer2 = 10|0x30000U, /**< QTIMER2_TIMER2 output assigned to XBAR3_IN10 input. */ + kXBAR3_InputQtimer2Timer3 = 11|0x30000U, /**< QTIMER2_TIMER3 output assigned to XBAR3_IN11 input. */ + kXBAR3_InputQtimer3Timer0 = 12|0x30000U, /**< QTIMER3_TIMER0 output assigned to XBAR3_IN12 input. */ + kXBAR3_InputQtimer3Timer1 = 13|0x30000U, /**< QTIMER3_TIMER1 output assigned to XBAR3_IN13 input. */ + kXBAR3_InputQtimer3Timer2 = 14|0x30000U, /**< QTIMER3_TIMER2 output assigned to XBAR3_IN14 input. */ + kXBAR3_InputQtimer3Timer3 = 15|0x30000U, /**< QTIMER3_TIMER3 output assigned to XBAR3_IN15 input. */ + kXBAR3_InputQtimer4Timer0 = 16|0x30000U, /**< QTIMER4_TIMER0 output assigned to XBAR3_IN16 input. */ + kXBAR3_InputQtimer4Timer1 = 17|0x30000U, /**< QTIMER4_TIMER1 output assigned to XBAR3_IN17 input. */ + kXBAR3_InputQtimer4Timer2 = 18|0x30000U, /**< QTIMER4_TIMER2 output assigned to XBAR3_IN18 input. */ + kXBAR3_InputQtimer4Timer3 = 19|0x30000U, /**< QTIMER4_TIMER3 output assigned to XBAR3_IN19 input. */ + kXBAR3_InputQtimer5Timer0 = 20|0x30000U, /**< QTIMER5_TIMER0 output assigned to XBAR3_IN20 input. */ + kXBAR3_InputQtimer5Timer1 = 21|0x30000U, /**< QTIMER5_TIMER1 output assigned to XBAR3_IN21 input. */ + kXBAR3_InputQtimer5Timer2 = 22|0x30000U, /**< QTIMER5_TIMER2 output assigned to XBAR3_IN22 input. */ + kXBAR3_InputQtimer5Timer3 = 23|0x30000U, /**< QTIMER5_TIMER3 output assigned to XBAR3_IN23 input. */ + kXBAR3_InputQtimer6Timer0 = 24|0x30000U, /**< QTIMER6_TIMER0 output assigned to XBAR3_IN24 input. */ + kXBAR3_InputQtimer6Timer1 = 25|0x30000U, /**< QTIMER6_TIMER1 output assigned to XBAR3_IN25 input. */ + kXBAR3_InputQtimer6Timer2 = 26|0x30000U, /**< QTIMER6_TIMER2 output assigned to XBAR3_IN26 input. */ + kXBAR3_InputQtimer6Timer3 = 27|0x30000U, /**< QTIMER6_TIMER3 output assigned to XBAR3_IN27 input. */ + kXBAR3_InputQtimer7Timer0 = 28|0x30000U, /**< QTIMER7_TIMER0 output assigned to XBAR3_IN28 input. */ + kXBAR3_InputQtimer7Timer1 = 29|0x30000U, /**< QTIMER7_TIMER1 output assigned to XBAR3_IN29 input. */ + kXBAR3_InputQtimer7Timer2 = 30|0x30000U, /**< QTIMER7_TIMER2 output assigned to XBAR3_IN30 input. */ + kXBAR3_InputQtimer7Timer3 = 31|0x30000U, /**< QTIMER7_TIMER3 output assigned to XBAR3_IN31 input. */ + kXBAR3_InputQtimer8Timer0 = 32|0x30000U, /**< QTIMER8_TIMER0 output assigned to XBAR3_IN32 input. */ + kXBAR3_InputQtimer8Timer1 = 33|0x30000U, /**< QTIMER8_TIMER1 output assigned to XBAR3_IN33 input. */ + kXBAR3_InputQtimer8Timer2 = 34|0x30000U, /**< QTIMER8_TIMER2 output assigned to XBAR3_IN34 input. */ + kXBAR3_InputQtimer8Timer3 = 35|0x30000U, /**< QTIMER8_TIMER3 output assigned to XBAR3_IN35 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger0 = 36|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR3_IN36 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger1 = 37|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR3_IN37 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger2 = 38|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR3_IN38 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger3 = 39|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR3_IN39 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger0 = 40|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR3_IN40 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger1 = 41|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR3_IN41 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger2 = 42|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR3_IN42 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger3 = 43|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR3_IN43 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger0 = 44|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR3_IN44 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger1 = 45|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR3_IN45 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger2 = 46|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR3_IN46 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger3 = 47|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR3_IN47 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger0 = 48|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR3_IN48 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger1 = 49|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR3_IN49 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger2 = 50|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR3_IN50 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger3 = 51|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR3_IN51 input. */ + kXBAR3_InputLpit1LpitTrigOut0 = 52|0x30000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR3_IN52 input. */ + kXBAR3_InputLpit1LpitTrigOut1 = 53|0x30000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR3_IN53 input. */ + kXBAR3_InputLpit1LpitTrigOut2 = 54|0x30000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR3_IN54 input. */ + kXBAR3_InputLpit1LpitTrigOut3 = 55|0x30000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR3_IN55 input. */ + kXBAR3_InputLpit2LpitTrigOut0 = 56|0x30000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR3_IN56 input. */ + kXBAR3_InputLpit2LpitTrigOut1 = 57|0x30000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR3_IN57 input. */ + kXBAR3_InputLpit2LpitTrigOut2 = 58|0x30000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR3_IN58 input. */ + kXBAR3_InputLpit2LpitTrigOut3 = 59|0x30000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR3_IN59 input. */ + kXBAR3_InputLpit3LpitTrigOut0 = 60|0x30000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR3_IN60 input. */ + kXBAR3_InputLpit3LpitTrigOut1 = 61|0x30000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR3_IN61 input. */ + kXBAR3_InputLpit3LpitTrigOut2 = 62|0x30000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR3_IN62 input. */ + kXBAR3_InputLpit3LpitTrigOut3 = 63|0x30000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR3_IN63 input. */ + kXBAR3_InputEdma2DmaTriggerOut0 = 64|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN64 input. */ + kXBAR3_InputEdma2DmaTriggerOut1 = 65|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN65 input. */ + kXBAR3_InputEdma2DmaTriggerOut2 = 66|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN66 input. */ + kXBAR3_InputEdma2DmaTriggerOut3 = 67|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN67 input. */ + kXBAR3_InputEdma2DmaTriggerOut4 = 68|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN68 input. */ + kXBAR3_InputEdma2DmaTriggerOut5 = 69|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN69 input. */ + kXBAR3_InputEdma2DmaTriggerOut6 = 70|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN70 input. */ + kXBAR3_InputEdma2DmaTriggerOut7 = 71|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN71 input. */ + kXBAR3_InputEdma1DmaTriggerOut0 = 72|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN72 input. */ + kXBAR3_InputEdma1DmaTriggerOut1 = 73|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN73 input. */ + kXBAR3_InputEdma1DmaTriggerOut2 = 74|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN74 input. */ + kXBAR3_InputEdma1DmaTriggerOut3 = 75|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN75 input. */ + kXBAR3_InputEdma1DmaTriggerOut4 = 76|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN76 input. */ + kXBAR3_InputEdma1DmaTriggerOut5 = 77|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN77 input. */ + kXBAR3_InputEdma1DmaTriggerOut6 = 78|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN78 input. */ + kXBAR3_InputEdma1DmaTriggerOut7 = 79|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN79 input. */ + kXBAR3_InputEdma3DmaTriggerOut0 = 80|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN80 input. */ + kXBAR3_InputEdma3DmaTriggerOut1 = 81|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN81 input. */ + kXBAR3_InputEdma3DmaTriggerOut2 = 82|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN82 input. */ + kXBAR3_InputEdma3DmaTriggerOut3 = 83|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN83 input. */ + kXBAR3_InputEdma3DmaTriggerOut4 = 84|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN84 input. */ + kXBAR3_InputEdma3DmaTriggerOut5 = 85|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN85 input. */ + kXBAR3_InputEdma3DmaTriggerOut6 = 86|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN86 input. */ + kXBAR3_InputEdma3DmaTriggerOut7 = 87|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN87 input. */ + kXBAR3_InputEdma4DmaTriggerOut0 = 88|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN88 input. */ + kXBAR3_InputEdma4DmaTriggerOut1 = 89|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN89 input. */ + kXBAR3_InputEdma4DmaTriggerOut2 = 90|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN90 input. */ + kXBAR3_InputEdma4DmaTriggerOut3 = 91|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN91 input. */ + kXBAR3_InputEdma4DmaTriggerOut4 = 92|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN92 input. */ + kXBAR3_InputEdma4DmaTriggerOut5 = 93|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN93 input. */ + kXBAR3_InputEdma4DmaTriggerOut6 = 94|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN94 input. */ + kXBAR3_InputEdma4DmaTriggerOut7 = 95|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN95 input. */ + kXBAR3_InputAdc1IpiIntEoc = 96|0x30000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR3_IN96 input. */ + kXBAR3_InputAdc1IpiIntWd = 97|0x30000U, /**< ADC1_IPI_INT_WD output assigned to XBAR3_IN97 input. */ + kXBAR3_InputTpm1LptpmChTrigger0 = 98|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN98 input. */ + kXBAR3_InputTpm1LptpmChTrigger1 = 99|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN99 input. */ + kXBAR3_InputTpm1LptpmChTrigger2 = 100|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN100 input. */ + kXBAR3_InputTpm1LptpmChTrigger3 = 101|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN101 input. */ + kXBAR3_InputTpm1LptpmTrigger = 102|0x30000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR3_IN102 input. */ + kXBAR3_InputTpm2LptpmChTrigger0 = 103|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN103 input. */ + kXBAR3_InputTpm2LptpmChTrigger1 = 104|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN104 input. */ + kXBAR3_InputTpm2LptpmChTrigger2 = 105|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN105 input. */ + kXBAR3_InputTpm2LptpmChTrigger3 = 106|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN106 input. */ + kXBAR3_InputTpm2LptpmTrigger = 107|0x30000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR3_IN107 input. */ + kXBAR3_InputTpm3LptpmChTrigger0 = 108|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN108 input. */ + kXBAR3_InputTpm3LptpmChTrigger1 = 109|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN109 input. */ + kXBAR3_InputTpm3LptpmChTrigger2 = 110|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN110 input. */ + kXBAR3_InputTpm3LptpmChTrigger3 = 111|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN111 input. */ + kXBAR3_InputTpm3LptpmTrigger = 112|0x30000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR3_IN112 input. */ + kXBAR3_InputTpm4LptpmChTrigger0 = 113|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN113 input. */ + kXBAR3_InputTpm4LptpmChTrigger1 = 114|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN114 input. */ + kXBAR3_InputTpm4LptpmChTrigger2 = 115|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN115 input. */ + kXBAR3_InputTpm4LptpmChTrigger3 = 116|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN116 input. */ + kXBAR3_InputTpm4LptpmTrigger = 117|0x30000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR3_IN117 input. */ + kXBAR3_InputTpm5LptpmChTrigger0 = 118|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN118 input. */ + kXBAR3_InputTpm5LptpmChTrigger1 = 119|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN119 input. */ + kXBAR3_InputTpm5LptpmChTrigger2 = 120|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN120 input. */ + kXBAR3_InputTpm5LptpmChTrigger3 = 121|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN121 input. */ + kXBAR3_InputTpm5LptpmTrigger = 122|0x30000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR3_IN122 input. */ + kXBAR3_InputTpm6LptpmChTrigger0 = 123|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN123 input. */ + kXBAR3_InputTpm6LptpmChTrigger1 = 124|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN124 input. */ + kXBAR3_InputTpm6LptpmChTrigger2 = 125|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN125 input. */ + kXBAR3_InputTpm6LptpmChTrigger3 = 126|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN126 input. */ + kXBAR3_InputTpm6LptpmTrigger = 127|0x30000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR3_IN127 input. */ + kXBAR3_InputLptmr1LptimerTriggerDelay = 128|0x30000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN128 input. */ + kXBAR3_InputLptmr2LptimerTriggerDelay = 129|0x30000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN129 input. */ + kXBAR3_InputLogicLow2 = 130|0x30000U, /**< LOGIC_LOW2 output assigned to XBAR3_IN130 input. */ + kXBAR3_InputNetcTmr11588Pp1 = 131|0x30000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR3_IN131 input. */ + kXBAR3_InputNetcTmr11588Pp2 = 132|0x30000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR3_IN132 input. */ + kXBAR3_InputNetcTmr11588Pp3 = 133|0x30000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR3_IN133 input. */ + kXBAR3_InputNetcTmr11588Alarm1 = 134|0x30000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR3_IN134 input. */ + kXBAR3_InputNetcTmr11588Alarm2 = 135|0x30000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR3_IN135 input. */ + kXBAR3_InputNetcTmr21588Pp1 = 136|0x30000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR3_IN136 input. */ + kXBAR3_InputNetcTmr21588Pp2 = 137|0x30000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR3_IN137 input. */ + kXBAR3_InputNetcTmr21588Pp3 = 138|0x30000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR3_IN138 input. */ + kXBAR3_InputNetcTmr21588Alarm1 = 139|0x30000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR3_IN139 input. */ + kXBAR3_InputNetcTmr21588Alarm2 = 140|0x30000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR3_IN140 input. */ + kXBAR3_InputNetcTmr31588Pp1 = 141|0x30000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR3_IN141 input. */ + kXBAR3_InputNetcTmr31588Pp2 = 142|0x30000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR3_IN142 input. */ + kXBAR3_InputNetcTmr31588Pp3 = 143|0x30000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR3_IN143 input. */ + kXBAR3_InputNetcTmr31588Alarm1 = 144|0x30000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR3_IN144 input. */ + kXBAR3_InputNetcTmr31588Alarm2 = 145|0x30000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR3_IN145 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak0 = 146|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR3_IN146 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak1 = 147|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR3_IN147 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak2 = 148|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR3_IN148 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak3 = 149|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR3_IN149 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak0 = 150|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR3_IN150 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak1 = 151|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR3_IN151 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak2 = 152|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR3_IN152 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak3 = 153|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR3_IN153 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak0 = 154|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR3_IN154 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak1 = 155|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR3_IN155 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak2 = 156|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR3_IN156 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak3 = 157|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR3_IN157 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak0 = 158|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR3_IN158 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak1 = 159|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR3_IN159 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak2 = 160|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR3_IN160 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak3 = 161|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR3_IN161 input. */ + kXBAR3_InputSinc2PulseTrg0 = 162|0x30000U, /**< SINC2_PULSE_TRG0 output assigned to XBAR3_IN162 input. */ + kXBAR3_InputSinc2PulseTrg1 = 163|0x30000U, /**< SINC2_PULSE_TRG1 output assigned to XBAR3_IN163 input. */ + kXBAR3_InputSinc2PulseTrg2 = 164|0x30000U, /**< SINC2_PULSE_TRG2 output assigned to XBAR3_IN164 input. */ + kXBAR3_InputSinc2PulseTrg3 = 165|0x30000U, /**< SINC2_PULSE_TRG3 output assigned to XBAR3_IN165 input. */ + kXBAR3_InputSinc4PulseTrg0 = 166|0x30000U, /**< SINC4_PULSE_TRG0 output assigned to XBAR3_IN166 input. */ + kXBAR3_InputSinc4PulseTrg1 = 167|0x30000U, /**< SINC4_PULSE_TRG1 output assigned to XBAR3_IN167 input. */ + kXBAR3_InputSinc4PulseTrg2 = 168|0x30000U, /**< SINC4_PULSE_TRG2 output assigned to XBAR3_IN168 input. */ + kXBAR3_InputSinc4PulseTrg3 = 169|0x30000U, /**< SINC4_PULSE_TRG3 output assigned to XBAR3_IN169 input. */ + kXBAR3_InputEcatSyncOut0 = 170|0x30000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR3_IN170 input. */ + kXBAR3_InputEcatSyncOut1 = 171|0x30000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR3_IN171 input. */ + kXBAR3_InputFccuVfccuReactionsOut11 = 172|0x30000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR3_IN172 input. */ + kXBAR3_InputGpt1IppDoCmpout1 = 173|0x30000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR3_IN173 input. */ + kXBAR3_InputGpt1IppDoCmpout2 = 174|0x30000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR3_IN174 input. */ + kXBAR3_InputGpt1IppDoCmpout3 = 175|0x30000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR3_IN175 input. */ + kXBAR3_InputGpt2IppDoCmpout1 = 176|0x30000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR3_IN176 input. */ + kXBAR3_InputGpt2IppDoCmpout2 = 177|0x30000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR3_IN177 input. */ + kXBAR3_InputGpt2IppDoCmpout3 = 178|0x30000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR3_IN178 input. */ + kXBAR3_InputGpt3IppDoCmpout1 = 179|0x30000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR3_IN179 input. */ + kXBAR3_InputGpt3IppDoCmpout2 = 180|0x30000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR3_IN180 input. */ + kXBAR3_InputGpt3IppDoCmpout3 = 181|0x30000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR3_IN181 input. */ + kXBAR3_InputGpt4IppDoCmpout1 = 182|0x30000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR3_IN182 input. */ + kXBAR3_InputGpt4IppDoCmpout2 = 183|0x30000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR3_IN183 input. */ + kXBAR3_InputGpt4IppDoCmpout3 = 184|0x30000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR3_IN184 input. */ + kXBAR3_InputFlexio1FlexioTriggerOut0 = 185|0x30000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN185 input. */ + kXBAR3_InputFlexio2FlexioTriggerOut0 = 186|0x30000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN186 input. */ + kXBAR3_InputFlexio3FlexioTriggerOut0 = 187|0x30000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN187 input. */ + kXBAR3_InputFlexio4FlexioTriggerOut0 = 188|0x30000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN188 input. */ + kXBAR3_InputGpio1IpiIntRgpio0 = 189|0x30000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR3_IN189 input. */ + kXBAR3_InputGpio2IpiIntRgpio0 = 190|0x30000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR3_IN190 input. */ + kXBAR3_InputGpio3IpiIntRgpio0 = 191|0x30000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR3_IN191 input. */ + kXBAR3_InputGpio4IpiIntRgpio0 = 192|0x30000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR3_IN192 input. */ + kXBAR3_InputGpio5IpiIntRgpio0 = 193|0x30000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR3_IN193 input. */ + kXBAR3_InputGpio6IpiIntRgpio0 = 194|0x30000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR3_IN194 input. */ + kXBAR3_InputGpio7IpiIntRgpio0 = 195|0x30000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR3_IN195 input. */ + kXBAR3_InputCm33Txev = 196|0x30000U, /**< CM33_TXEV output assigned to XBAR3_IN196 input. */ + kXBAR3_InputCm33SyncTxev = 197|0x30000U, /**< CM33_SYNC_TXEV output assigned to XBAR3_IN197 input. */ + kXBAR3_InputEndat21SiN = 198|0x30000U, /**< ENDAT2_1_SI_N output assigned to XBAR3_IN198 input. */ + kXBAR3_InputEndat21TimerN = 199|0x30000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR3_IN199 input. */ + kXBAR3_InputEndat22SiN = 200|0x30000U, /**< ENDAT2_2_SI_N output assigned to XBAR3_IN200 input. */ + kXBAR3_InputEndat22TimerN = 201|0x30000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR3_IN201 input. */ + kXBAR3_InputBissEot = 202|0x30000U, /**< BISS_EOT output assigned to XBAR3_IN202 input. */ + kXBAR3_InputEnc2PosMatch0 = 203|0x30000U, /**< ENC2_POS_MATCH0 output assigned to XBAR3_IN203 input. */ + kXBAR3_InputEnc2PosMatch1 = 204|0x30000U, /**< ENC2_POS_MATCH1 output assigned to XBAR3_IN204 input. */ + kXBAR3_InputEnc2PosMatch2 = 205|0x30000U, /**< ENC2_POS_MATCH2 output assigned to XBAR3_IN205 input. */ + kXBAR3_InputEnc2PosMatch3 = 206|0x30000U, /**< ENC2_POS_MATCH3 output assigned to XBAR3_IN206 input. */ + kXBAR3_InputEnc2CompFlg0 = 207|0x30000U, /**< ENC2_COMP_FLG0 output assigned to XBAR3_IN207 input. */ + kXBAR3_InputEnc2CompFlg1 = 208|0x30000U, /**< ENC2_COMP_FLG1 output assigned to XBAR3_IN208 input. */ + kXBAR3_InputEnc2CompFlg2 = 209|0x30000U, /**< ENC2_COMP_FLG2 output assigned to XBAR3_IN209 input. */ + kXBAR3_InputEnc2CompFlg3 = 210|0x30000U, /**< ENC2_COMP_FLG3 output assigned to XBAR3_IN210 input. */ + kXBAR3_InputEnc2CntDn = 211|0x30000U, /**< ENC2_CNT_DN output assigned to XBAR3_IN211 input. */ + kXBAR3_InputEnc2CntUp = 212|0x30000U, /**< ENC2_CNT_UP output assigned to XBAR3_IN212 input. */ + kXBAR3_InputEnc2Dir = 213|0x30000U, /**< ENC2_DIR output assigned to XBAR3_IN213 input. */ + kXBAR3_InputEnc4PosMatch0 = 214|0x30000U, /**< ENC4_POS_MATCH0 output assigned to XBAR3_IN214 input. */ + kXBAR3_InputEnc4PosMatch1 = 215|0x30000U, /**< ENC4_POS_MATCH1 output assigned to XBAR3_IN215 input. */ + kXBAR3_InputEnc4PosMatch2 = 216|0x30000U, /**< ENC4_POS_MATCH2 output assigned to XBAR3_IN216 input. */ + kXBAR3_InputEnc4PosMatch3 = 217|0x30000U, /**< ENC4_POS_MATCH3 output assigned to XBAR3_IN217 input. */ + kXBAR3_InputEnc4CompFlg0 = 218|0x30000U, /**< ENC4_COMP_FLG0 output assigned to XBAR3_IN218 input. */ + kXBAR3_InputEnc4CompFlg1 = 219|0x30000U, /**< ENC4_COMP_FLG1 output assigned to XBAR3_IN219 input. */ + kXBAR3_InputEnc4CompFlg2 = 220|0x30000U, /**< ENC4_COMP_FLG2 output assigned to XBAR3_IN220 input. */ + kXBAR3_InputEnc4CompFlg3 = 221|0x30000U, /**< ENC4_COMP_FLG3 output assigned to XBAR3_IN221 input. */ + kXBAR3_InputEnc4CntDn = 222|0x30000U, /**< ENC4_CNT_DN output assigned to XBAR3_IN222 input. */ + kXBAR3_InputEnc4CntUp = 223|0x30000U, /**< ENC4_CNT_UP output assigned to XBAR3_IN223 input. */ + kXBAR3_InputEnc4Dir = 224|0x30000U, /**< ENC4_DIR output assigned to XBAR3_IN224 input. */ + kXBAR3_InputHiperface1FastPosRcvdEvt = 225|0x30000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR3_IN225 input. */ + kXBAR3_InputHiperface2FastPosRcvdEvt = 226|0x30000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR3_IN226 input. */ +} xbar_input_signal_t; + +typedef enum _xbar_output_signal +{ + kXBAR1_OutputEdma4IpdReq76 = 0|0x10000U, /**< XBAR1_OUT0 output assigned to EDMA4_IPD_REQ76 */ + kXBAR1_OutputEdma4IpdReq77 = 1|0x10000U, /**< XBAR1_OUT1 output assigned to EDMA4_IPD_REQ77 */ + kXBAR1_OutputEdma4IpdReq78 = 2|0x10000U, /**< XBAR1_OUT2 output assigned to EDMA4_IPD_REQ78 */ + kXBAR1_OutputEdma4IpdReq79 = 3|0x10000U, /**< XBAR1_OUT3 output assigned to EDMA4_IPD_REQ79 */ + kXBAR1_OutputIomuxXbarOut04 = 4|0x10000U, /**< XBAR1_OUT4 output assigned to IOMUX_XBAR_OUT04 */ + kXBAR1_OutputIomuxXbarOut05 = 5|0x10000U, /**< XBAR1_OUT5 output assigned to IOMUX_XBAR_OUT05 */ + kXBAR1_OutputIomuxXbarOut06 = 6|0x10000U, /**< XBAR1_OUT6 output assigned to IOMUX_XBAR_OUT06 */ + kXBAR1_OutputIomuxXbarOut07 = 7|0x10000U, /**< XBAR1_OUT7 output assigned to IOMUX_XBAR_OUT07 */ + kXBAR1_OutputIomuxXbarOut08 = 8|0x10000U, /**< XBAR1_OUT8 output assigned to IOMUX_XBAR_OUT08 */ + kXBAR1_OutputIomuxXbarOut09 = 9|0x10000U, /**< XBAR1_OUT9 output assigned to IOMUX_XBAR_OUT09 */ + kXBAR1_OutputIomuxXbarOut10 = 10|0x10000U, /**< XBAR1_OUT10 output assigned to IOMUX_XBAR_OUT10 */ + kXBAR1_OutputIomuxXbarOut11 = 11|0x10000U, /**< XBAR1_OUT11 output assigned to IOMUX_XBAR_OUT11 */ + kXBAR1_OutputIomuxXbarOut12 = 12|0x10000U, /**< XBAR1_OUT12 output assigned to IOMUX_XBAR_OUT12 */ + kXBAR1_OutputIomuxXbarOut13 = 13|0x10000U, /**< XBAR1_OUT13 output assigned to IOMUX_XBAR_OUT13 */ + kXBAR1_OutputIomuxXbarOut14 = 14|0x10000U, /**< XBAR1_OUT14 output assigned to IOMUX_XBAR_OUT14 */ + kXBAR1_OutputIomuxXbarOut15 = 15|0x10000U, /**< XBAR1_OUT15 output assigned to IOMUX_XBAR_OUT15 */ + kXBAR1_OutputIomuxXbarOut16 = 16|0x10000U, /**< XBAR1_OUT16 output assigned to IOMUX_XBAR_OUT16 */ + kXBAR1_OutputIomuxXbarOut17 = 17|0x10000U, /**< XBAR1_OUT17 output assigned to IOMUX_XBAR_OUT17 */ + kXBAR1_OutputIomuxXbarOut18 = 18|0x10000U, /**< XBAR1_OUT18 output assigned to IOMUX_XBAR_OUT18 */ + kXBAR1_OutputIomuxXbarOut19 = 19|0x10000U, /**< XBAR1_OUT19 output assigned to IOMUX_XBAR_OUT19 */ + kXBAR1_OutputIomuxXbarOut20 = 20|0x10000U, /**< XBAR1_OUT20 output assigned to IOMUX_XBAR_OUT20 */ + kXBAR1_OutputIomuxXbarOut21 = 21|0x10000U, /**< XBAR1_OUT21 output assigned to IOMUX_XBAR_OUT21 */ + kXBAR1_OutputIomuxXbarOut22 = 22|0x10000U, /**< XBAR1_OUT22 output assigned to IOMUX_XBAR_OUT22 */ + kXBAR1_OutputIomuxXbarOut23 = 23|0x10000U, /**< XBAR1_OUT23 output assigned to IOMUX_XBAR_OUT23 */ + kXBAR1_OutputIomuxXbarOut24 = 24|0x10000U, /**< XBAR1_OUT24 output assigned to IOMUX_XBAR_OUT24 */ + kXBAR1_OutputIomuxXbarOut25 = 25|0x10000U, /**< XBAR1_OUT25 output assigned to IOMUX_XBAR_OUT25 */ + kXBAR1_OutputIomuxXbarOut26 = 26|0x10000U, /**< XBAR1_OUT26 output assigned to IOMUX_XBAR_OUT26 */ + kXBAR1_OutputIomuxXbarOut27 = 27|0x10000U, /**< XBAR1_OUT27 output assigned to IOMUX_XBAR_OUT27 */ + kXBAR1_OutputIomuxXbarOut28 = 28|0x10000U, /**< XBAR1_OUT28 output assigned to IOMUX_XBAR_OUT28 */ + kXBAR1_OutputIomuxXbarOut29 = 29|0x10000U, /**< XBAR1_OUT29 output assigned to IOMUX_XBAR_OUT29 */ + kXBAR1_OutputIomuxXbarOut30 = 30|0x10000U, /**< XBAR1_OUT30 output assigned to IOMUX_XBAR_OUT30 */ + kXBAR1_OutputIomuxXbarOut31 = 31|0x10000U, /**< XBAR1_OUT31 output assigned to IOMUX_XBAR_OUT31 */ + kXBAR1_OutputIomuxXbarOut32 = 32|0x10000U, /**< XBAR1_OUT32 output assigned to IOMUX_XBAR_OUT32 */ + kXBAR1_OutputIomuxXbarOut33 = 33|0x10000U, /**< XBAR1_OUT33 output assigned to IOMUX_XBAR_OUT33 */ + kXBAR1_OutputIomuxXbarOut34 = 34|0x10000U, /**< XBAR1_OUT34 output assigned to IOMUX_XBAR_OUT34 */ + kXBAR1_OutputIomuxXbarOut35 = 35|0x10000U, /**< XBAR1_OUT35 output assigned to IOMUX_XBAR_OUT35 */ + kXBAR1_OutputIomuxXbarOut36 = 36|0x10000U, /**< XBAR1_OUT36 output assigned to IOMUX_XBAR_OUT36 */ + kXBAR1_OutputIomuxXbarOut37 = 37|0x10000U, /**< XBAR1_OUT37 output assigned to IOMUX_XBAR_OUT37 */ + kXBAR1_OutputIomuxXbarOut38 = 38|0x10000U, /**< XBAR1_OUT38 output assigned to IOMUX_XBAR_OUT38 */ + kXBAR1_OutputIomuxXbarOut39 = 39|0x10000U, /**< XBAR1_OUT39 output assigned to IOMUX_XBAR_OUT39 */ + kXBAR1_OutputIomuxXbarOut40 = 40|0x10000U, /**< XBAR1_OUT40 output assigned to IOMUX_XBAR_OUT40 */ + kXBAR1_OutputTriggerSyncAsyncIn0 = 41|0x10000U, /**< XBAR1_OUT41 output assigned to TRIGGER_SYNC_ASYNC_IN0 */ + kXBAR1_OutputTriggerSyncAsyncIn1 = 42|0x10000U, /**< XBAR1_OUT42 output assigned to TRIGGER_SYNC_ASYNC_IN1 */ + kXBAR1_OutputTriggerSyncAsyncIn2 = 43|0x10000U, /**< XBAR1_OUT43 output assigned to TRIGGER_SYNC_ASYNC_IN2 */ + kXBAR1_OutputTriggerSyncAsyncIn3 = 44|0x10000U, /**< XBAR1_OUT44 output assigned to TRIGGER_SYNC_ASYNC_IN3 */ + kXBAR1_OutputTriggerSyncAsyncIn4 = 45|0x10000U, /**< XBAR1_OUT45 output assigned to TRIGGER_SYNC_ASYNC_IN4 */ + kXBAR1_OutputTriggerSyncAsyncIn5 = 46|0x10000U, /**< XBAR1_OUT46 output assigned to TRIGGER_SYNC_ASYNC_IN5 */ + kXBAR1_OutputTriggerSyncAsyncIn6 = 47|0x10000U, /**< XBAR1_OUT47 output assigned to TRIGGER_SYNC_ASYNC_IN6 */ + kXBAR1_OutputTriggerSyncAsyncIn7 = 48|0x10000U, /**< XBAR1_OUT48 output assigned to TRIGGER_SYNC_ASYNC_IN7 */ + kXBAR1_OutputFlexpwm1Exta0 = 49|0x10000U, /**< XBAR1_OUT49 output assigned to FLEXPWM1_EXTA0 */ + kXBAR1_OutputFlexpwm1Exta1 = 50|0x10000U, /**< XBAR1_OUT50 output assigned to FLEXPWM1_EXTA1 */ + kXBAR1_OutputFlexpwm1Exta2 = 51|0x10000U, /**< XBAR1_OUT51 output assigned to FLEXPWM1_EXTA2 */ + kXBAR1_OutputFlexpwm1Exta3 = 52|0x10000U, /**< XBAR1_OUT52 output assigned to FLEXPWM1_EXTA3 */ + kXBAR1_OutputFlexpwm1ExtSync0 = 53|0x10000U, /**< XBAR1_OUT53 output assigned to FLEXPWM1_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm1ExtSync1 = 54|0x10000U, /**< XBAR1_OUT54 output assigned to FLEXPWM1_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm1ExtSync2 = 55|0x10000U, /**< XBAR1_OUT55 output assigned to FLEXPWM1_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm1ExtSync3 = 56|0x10000U, /**< XBAR1_OUT56 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm1ExtClk = 57|0x10000U, /**< XBAR1_OUT57 output assigned to FLEXPWM1_EXT_CLK */ + kXBAR1_OutputFlexpwm1IppIndFault0 = 58|0x10000U, /**< XBAR1_OUT58 output assigned to FLEXPWM1_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm1IppIndFault1 = 59|0x10000U, /**< XBAR1_OUT59 output assigned to FLEXPWM1_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm1IppIndFault2 = 60|0x10000U, /**< XBAR1_OUT60 output assigned to FLEXPWM1_IPP_IND_FAULT2 */ + kXBAR1_OutputFlexpwm1IppIndFault3 = 61|0x10000U, /**< XBAR1_OUT61 output assigned to FLEXPWM1_IPP_IND_FAULT3 */ + kXBAR1_OutputFlexpwm1ExtForce = 62|0x10000U, /**< XBAR1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */ + kXBAR1_OutputFlexpwm2Exta0 = 63|0x10000U, /**< XBAR1_OUT63 output assigned to FLEXPWM2_EXTA0 */ + kXBAR1_OutputFlexpwm2Exta1 = 64|0x10000U, /**< XBAR1_OUT64 output assigned to FLEXPWM2_EXTA1 */ + kXBAR1_OutputFlexpwm2Exta2 = 65|0x10000U, /**< XBAR1_OUT65 output assigned to FLEXPWM2_EXTA2 */ + kXBAR1_OutputFlexpwm2Exta3 = 66|0x10000U, /**< XBAR1_OUT66 output assigned to FLEXPWM2_EXTA3 */ + kXBAR1_OutputFlexpwm2ExtSync0 = 67|0x10000U, /**< XBAR1_OUT67 output assigned to FLEXPWM2_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm2ExtSync1 = 68|0x10000U, /**< XBAR1_OUT68 output assigned to FLEXPWM2_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm2ExtSync2 = 69|0x10000U, /**< XBAR1_OUT69 output assigned to FLEXPWM2_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm2ExtSync3 = 70|0x10000U, /**< XBAR1_OUT70 output assigned to FLEXPWM2_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm2ExtClk = 71|0x10000U, /**< XBAR1_OUT71 output assigned to FLEXPWM2_EXT_CLK */ + kXBAR1_OutputFlexpwm2IppIndFault0 = 72|0x10000U, /**< XBAR1_OUT72 output assigned to FLEXPWM2_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm2IppIndFault1 = 73|0x10000U, /**< XBAR1_OUT73 output assigned to FLEXPWM2_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm2ExtForce = 74|0x10000U, /**< XBAR1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */ + kXBAR1_OutputFlexpwm3Exta0 = 75|0x10000U, /**< XBAR1_OUT75 output assigned to FLEXPWM3_EXTA0 */ + kXBAR1_OutputFlexpwm3Exta1 = 76|0x10000U, /**< XBAR1_OUT76 output assigned to FLEXPWM3_EXTA1 */ + kXBAR1_OutputFlexpwm3Exta2 = 77|0x10000U, /**< XBAR1_OUT77 output assigned to FLEXPWM3_EXTA2 */ + kXBAR1_OutputFlexpwm3Exta3 = 78|0x10000U, /**< XBAR1_OUT78 output assigned to FLEXPWM3_EXTA3 */ + kXBAR1_OutputFlexpwm3ExtClk = 79|0x10000U, /**< XBAR1_OUT79 output assigned to FLEXPWM3_EXT_CLK */ + kXBAR1_OutputFlexpwm3ExtSync0 = 80|0x10000U, /**< XBAR1_OUT80 output assigned to FLEXPWM3_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm3ExtSync1 = 81|0x10000U, /**< XBAR1_OUT81 output assigned to FLEXPWM3_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm3ExtSync2 = 82|0x10000U, /**< XBAR1_OUT82 output assigned to FLEXPWM3_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm3ExtSync3 = 83|0x10000U, /**< XBAR1_OUT83 output assigned to FLEXPWM3_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm3IppIndFault0 = 84|0x10000U, /**< XBAR1_OUT84 output assigned to FLEXPWM3_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm3IppIndFault1 = 85|0x10000U, /**< XBAR1_OUT85 output assigned to FLEXPWM3_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm3ExtForce = 86|0x10000U, /**< XBAR1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */ + kXBAR1_OutputFlexpwm4ExtSync0 = 87|0x10000U, /**< XBAR1_OUT87 output assigned to FLEXPWM4_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm4ExtSync1 = 88|0x10000U, /**< XBAR1_OUT88 output assigned to FLEXPWM4_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm4ExtSync2 = 89|0x10000U, /**< XBAR1_OUT89 output assigned to FLEXPWM4_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm4ExtSync3 = 90|0x10000U, /**< XBAR1_OUT90 output assigned to FLEXPWM4_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm4IppIndFault0 = 91|0x10000U, /**< XBAR1_OUT91 output assigned to FLEXPWM4_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm4IppIndFault1 = 92|0x10000U, /**< XBAR1_OUT92 output assigned to FLEXPWM4_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm4ExtForce = 93|0x10000U, /**< XBAR1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */ + kXBAR1_OutputEnc1PhaseAInput = 94|0x10000U, /**< XBAR1_OUT94 output assigned to ENC1_PHASE_A_INPUT */ + kXBAR1_OutputEnc1PhaseBInput = 95|0x10000U, /**< XBAR1_OUT95 output assigned to ENC1_PHASE_B_INPUT */ + kXBAR1_OutputEnc1Index = 96|0x10000U, /**< XBAR1_OUT96 output assigned to ENC1_INDEX */ + kXBAR1_OutputEnc1Home = 97|0x10000U, /**< XBAR1_OUT97 output assigned to ENC1_HOME */ + kXBAR1_OutputEnc1Trigger = 98|0x10000U, /**< XBAR1_OUT98 output assigned to ENC1_TRIGGER */ + kXBAR1_OutputEnc2PhaseAInput = 99|0x10000U, /**< XBAR1_OUT99 output assigned to ENC2_PHASE_A_INPUT */ + kXBAR1_OutputEnc2PhaseBInput = 100|0x10000U, /**< XBAR1_OUT100 output assigned to ENC2_PHASE_B_INPUT */ + kXBAR1_OutputEnc2Index = 101|0x10000U, /**< XBAR1_OUT101 output assigned to ENC2_INDEX */ + kXBAR1_OutputEnc2Home = 102|0x10000U, /**< XBAR1_OUT102 output assigned to ENC2_HOME */ + kXBAR1_OutputEnc2Trigger = 103|0x10000U, /**< XBAR1_OUT103 output assigned to ENC2_TRIGGER */ + kXBAR1_OutputEnc3PhaseAInput = 104|0x10000U, /**< XBAR1_OUT104 output assigned to ENC3_PHASE_A_INPUT */ + kXBAR1_OutputEnc3PhaseBInput = 105|0x10000U, /**< XBAR1_OUT105 output assigned to ENC3_PHASE_B_INPUT */ + kXBAR1_OutputEnc3Index = 106|0x10000U, /**< XBAR1_OUT106 output assigned to ENC3_INDEX */ + kXBAR1_OutputEnc3Home = 107|0x10000U, /**< XBAR1_OUT107 output assigned to ENC3_HOME */ + kXBAR1_OutputEnc3Trigger = 108|0x10000U, /**< XBAR1_OUT108 output assigned to ENC3_TRIGGER */ + kXBAR1_OutputEnc4PhaseAInput = 109|0x10000U, /**< XBAR1_OUT109 output assigned to ENC4_PHASE_A_INPUT */ + kXBAR1_OutputEnc4PhaseBInput = 110|0x10000U, /**< XBAR1_OUT110 output assigned to ENC4_PHASE_B_INPUT */ + kXBAR1_OutputEnc4Index = 111|0x10000U, /**< XBAR1_OUT111 output assigned to ENC4_INDEX */ + kXBAR1_OutputEnc4Home = 112|0x10000U, /**< XBAR1_OUT112 output assigned to ENC4_HOME */ + kXBAR1_OutputEnc4Trigger = 113|0x10000U, /**< XBAR1_OUT113 output assigned to ENC4_TRIGGER */ + kXBAR1_OutputQtimer1Tmr0Input = 114|0x10000U, /**< XBAR1_OUT114 output assigned to QTIMER1_TMR0_INPUT */ + kXBAR1_OutputQtimer1Tmr1Input = 115|0x10000U, /**< XBAR1_OUT115 output assigned to QTIMER1_TMR1_INPUT */ + kXBAR1_OutputQtimer1Tmr2Input = 116|0x10000U, /**< XBAR1_OUT116 output assigned to QTIMER1_TMR2_INPUT */ + kXBAR1_OutputQtimer1Tmr3Input = 117|0x10000U, /**< XBAR1_OUT117 output assigned to QTIMER1_TMR3_INPUT */ + kXBAR1_OutputQtimer2Tmr0Input = 118|0x10000U, /**< XBAR1_OUT118 output assigned to QTIMER2_TMR0_INPUT */ + kXBAR1_OutputQtimer2Tmr1Input = 119|0x10000U, /**< XBAR1_OUT119 output assigned to QTIMER2_TMR1_INPUT */ + kXBAR1_OutputQtimer2Tmr2Input = 120|0x10000U, /**< XBAR1_OUT120 output assigned to QTIMER2_TMR2_INPUT */ + kXBAR1_OutputQtimer2Tmr3Input = 121|0x10000U, /**< XBAR1_OUT121 output assigned to QTIMER2_TMR3_INPUT */ + kXBAR1_OutputQtimer3Tmr0Input = 122|0x10000U, /**< XBAR1_OUT122 output assigned to QTIMER3_TMR0_INPUT */ + kXBAR1_OutputQtimer3Tmr1Input = 123|0x10000U, /**< XBAR1_OUT123 output assigned to QTIMER3_TMR1_INPUT */ + kXBAR1_OutputQtimer3Tmr2Input = 124|0x10000U, /**< XBAR1_OUT124 output assigned to QTIMER3_TMR2_INPUT */ + kXBAR1_OutputQtimer3Tmr3Input = 125|0x10000U, /**< XBAR1_OUT125 output assigned to QTIMER3_TMR3_INPUT */ + kXBAR1_OutputQtimer4Tmr0Input = 126|0x10000U, /**< XBAR1_OUT126 output assigned to QTIMER4_TMR0_INPUT */ + kXBAR1_OutputQtimer4Tmr1Input = 127|0x10000U, /**< XBAR1_OUT127 output assigned to QTIMER4_TMR1_INPUT */ + kXBAR1_OutputQtimer4Tmr2Input = 128|0x10000U, /**< XBAR1_OUT128 output assigned to QTIMER4_TMR2_INPUT */ + kXBAR1_OutputQtimer4Tmr3Input = 129|0x10000U, /**< XBAR1_OUT129 output assigned to QTIMER4_TMR3_INPUT */ + kXBAR1_OutputQtimer5Tmr0Input = 130|0x10000U, /**< XBAR1_OUT130 output assigned to QTIMER5_TMR0_INPUT */ + kXBAR1_OutputQtimer5Tmr1Input = 131|0x10000U, /**< XBAR1_OUT131 output assigned to QTIMER5_TMR1_INPUT */ + kXBAR1_OutputQtimer5Tmr2Input = 132|0x10000U, /**< XBAR1_OUT132 output assigned to QTIMER5_TMR2_INPUT */ + kXBAR1_OutputQtimer5Tmr3Input = 133|0x10000U, /**< XBAR1_OUT133 output assigned to QTIMER5_TMR3_INPUT */ + kXBAR1_OutputQtimer6Tmr0Input = 134|0x10000U, /**< XBAR1_OUT134 output assigned to QTIMER6_TMR0_INPUT */ + kXBAR1_OutputQtimer6Tmr1Input = 135|0x10000U, /**< XBAR1_OUT135 output assigned to QTIMER6_TMR1_INPUT */ + kXBAR1_OutputQtimer6Tmr2Input = 136|0x10000U, /**< XBAR1_OUT136 output assigned to QTIMER6_TMR2_INPUT */ + kXBAR1_OutputQtimer6Tmr3Input = 137|0x10000U, /**< XBAR1_OUT137 output assigned to QTIMER6_TMR3_INPUT */ + kXBAR1_OutputQtimer7Tmr0Input = 138|0x10000U, /**< XBAR1_OUT138 output assigned to QTIMER7_TMR0_INPUT */ + kXBAR1_OutputQtimer7Tmr1Input = 139|0x10000U, /**< XBAR1_OUT139 output assigned to QTIMER7_TMR1_INPUT */ + kXBAR1_OutputQtimer7Tmr2Input = 140|0x10000U, /**< XBAR1_OUT140 output assigned to QTIMER7_TMR2_INPUT */ + kXBAR1_OutputQtimer7Tmr3Input = 141|0x10000U, /**< XBAR1_OUT141 output assigned to QTIMER7_TMR3_INPUT */ + kXBAR1_OutputQtimer8Tmr0Input = 142|0x10000U, /**< XBAR1_OUT142 output assigned to QTIMER8_TMR0_INPUT */ + kXBAR1_OutputQtimer8Tmr1Input = 143|0x10000U, /**< XBAR1_OUT143 output assigned to QTIMER8_TMR1_INPUT */ + kXBAR1_OutputQtimer8Tmr2Input = 144|0x10000U, /**< XBAR1_OUT144 output assigned to QTIMER8_TMR2_INPUT */ + kXBAR1_OutputQtimer8Tmr3Input = 145|0x10000U, /**< XBAR1_OUT145 output assigned to QTIMER8_TMR3_INPUT */ + kXBAR1_OutputEwmEwmIn = 146|0x10000U, /**< XBAR1_OUT146 output assigned to EWM_EWM_IN */ + kXBAR1_OutputAnamixGlueTrgmuxInjectionTrg = 147|0x10000U, /**< XBAR1_OUT147 output assigned to ANAMIX_GLUE_TRGMUX_INJECTION_TRG */ + kXBAR1_OutputAnamixGlueTrgmuxStartTrg = 148|0x10000U, /**< XBAR1_OUT148 output assigned to ANAMIX_GLUE_TRGMUX_START_TRG */ + kXBAR1_OutputSinc1ExtTrigger0 = 149|0x10000U, /**< XBAR1_OUT149 output assigned to SINC1_EXT_TRIGGER0 */ + kXBAR1_OutputSinc1ExtTrigger1 = 150|0x10000U, /**< XBAR1_OUT150 output assigned to SINC1_EXT_TRIGGER1 */ + kXBAR1_OutputSinc1ExtTrigger2 = 151|0x10000U, /**< XBAR1_OUT151 output assigned to SINC1_EXT_TRIGGER2 */ + kXBAR1_OutputSinc1ExtTrigger3 = 152|0x10000U, /**< XBAR1_OUT152 output assigned to SINC1_EXT_TRIGGER3 */ + kXBAR1_OutputFlexio1FlexioTriggerIn0 = 153|0x10000U, /**< XBAR1_OUT153 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio1FlexioTriggerIn1 = 154|0x10000U, /**< XBAR1_OUT154 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio2FlexioTriggerIn0 = 155|0x10000U, /**< XBAR1_OUT155 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio2FlexioTriggerIn1 = 156|0x10000U, /**< XBAR1_OUT156 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio3FlexioTriggerIn0 = 157|0x10000U, /**< XBAR1_OUT157 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio3FlexioTriggerIn1 = 158|0x10000U, /**< XBAR1_OUT158 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio4FlexioTriggerIn0 = 159|0x10000U, /**< XBAR1_OUT159 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio4FlexioTriggerIn1 = 160|0x10000U, /**< XBAR1_OUT160 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputLpi2c1Lpi2cTrgInput = 161|0x10000U, /**< XBAR1_OUT161 output assigned to LPI2C1_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c2Lpi2cTrgInput = 162|0x10000U, /**< XBAR1_OUT162 output assigned to LPI2C2_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c3Lpi2cTrgInput = 163|0x10000U, /**< XBAR1_OUT163 output assigned to LPI2C3_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c4Lpi2cTrgInput = 164|0x10000U, /**< XBAR1_OUT164 output assigned to LPI2C4_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c5Lpi2cTrgInput = 165|0x10000U, /**< XBAR1_OUT165 output assigned to LPI2C5_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c6Lpi2cTrgInput = 166|0x10000U, /**< XBAR1_OUT166 output assigned to LPI2C6_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c7Lpi2cTrgInput = 167|0x10000U, /**< XBAR1_OUT167 output assigned to LPI2C7_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c8Lpi2cTrgInput = 168|0x10000U, /**< XBAR1_OUT168 output assigned to LPI2C8_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpspi1LpspiTrgInput = 169|0x10000U, /**< XBAR1_OUT169 output assigned to LPSPI1_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi2LpspiTrgInput = 170|0x10000U, /**< XBAR1_OUT170 output assigned to LPSPI2_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi3LpspiTrgInput = 171|0x10000U, /**< XBAR1_OUT171 output assigned to LPSPI3_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi4LpspiTrgInput = 172|0x10000U, /**< XBAR1_OUT172 output assigned to LPSPI4_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi5LpspiTrgInput = 173|0x10000U, /**< XBAR1_OUT173 output assigned to LPSPI5_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi6LpspiTrgInput = 174|0x10000U, /**< XBAR1_OUT174 output assigned to LPSPI6_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi7LpspiTrgInput = 175|0x10000U, /**< XBAR1_OUT175 output assigned to LPSPI7_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi8LpspiTrgInput = 176|0x10000U, /**< XBAR1_OUT176 output assigned to LPSPI8_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpuart1LpuartTrgInput = 177|0x10000U, /**< XBAR1_OUT177 output assigned to LPUART1_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart2LpuartTrgInput = 178|0x10000U, /**< XBAR1_OUT178 output assigned to LPUART2_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart3LpuartTrgInput = 179|0x10000U, /**< XBAR1_OUT179 output assigned to LPUART3_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart4LpuartTrgInput = 180|0x10000U, /**< XBAR1_OUT180 output assigned to LPUART4_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart5LpuartTrgInput = 181|0x10000U, /**< XBAR1_OUT181 output assigned to LPUART5_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart6LpuartTrgInput = 182|0x10000U, /**< XBAR1_OUT182 output assigned to LPUART6_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart7LpuartTrgInput = 183|0x10000U, /**< XBAR1_OUT183 output assigned to LPUART7_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart8LpuartTrgInput = 184|0x10000U, /**< XBAR1_OUT184 output assigned to LPUART8_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart9LpuartTrgInput = 185|0x10000U, /**< XBAR1_OUT185 output assigned to LPUART9_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart10LpuartTrgInput = 186|0x10000U, /**< XBAR1_OUT186 output assigned to LPUART10_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart11LpuartTrgInput = 187|0x10000U, /**< XBAR1_OUT187 output assigned to LPUART11_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart12LpuartTrgInput = 188|0x10000U, /**< XBAR1_OUT188 output assigned to LPUART12_LPUART_TRG_INPUT */ + kXBAR1_OutputLpit1LpitExtTrigIn0 = 189|0x10000U, /**< XBAR1_OUT189 output assigned to LPIT1_LPIT_EXT_TRIG_IN0 */ + kXBAR1_OutputLpit1LpitExtTrigIn1 = 190|0x10000U, /**< XBAR1_OUT190 output assigned to LPIT1_LPIT_EXT_TRIG_IN1 */ + kXBAR1_OutputLpit1LpitExtTrigIn2 = 191|0x10000U, /**< XBAR1_OUT191 output assigned to LPIT1_LPIT_EXT_TRIG_IN2 */ + kXBAR1_OutputLpit1LpitExtTrigIn3 = 192|0x10000U, /**< XBAR1_OUT192 output assigned to LPIT1_LPIT_EXT_TRIG_IN3 */ + kXBAR1_OutputTpm1LptpmTriggerIn0 = 193|0x10000U, /**< XBAR1_OUT193 output assigned to TPM1_LPTPM_TRIGGER_IN0 */ + kXBAR1_OutputTpm1LptpmTriggerIn1 = 194|0x10000U, /**< XBAR1_OUT194 output assigned to TPM1_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm2LptpmTriggerIn1 = 195|0x10000U, /**< XBAR1_OUT195 output assigned to TPM2_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm3LptpmTriggerIn1 = 196|0x10000U, /**< XBAR1_OUT196 output assigned to TPM3_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm1LptpmTriggerIn2 = 197|0x10000U, /**< XBAR1_OUT197 output assigned to TPM1_LPTPM_TRIGGER_IN2 */ + kXBAR1_OutputTpm1LptpmTriggerIn3 = 198|0x10000U, /**< XBAR1_OUT198 output assigned to TPM1_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm2LptpmTriggerIn3 = 199|0x10000U, /**< XBAR1_OUT199 output assigned to TPM2_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm3LptpmTriggerIn3 = 200|0x10000U, /**< XBAR1_OUT200 output assigned to TPM3_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm4LptpmTriggerIn0 = 201|0x10000U, /**< XBAR1_OUT201 output assigned to TPM4_LPTPM_TRIGGER_IN0 */ + kXBAR1_OutputTpm4LptpmTriggerIn1 = 202|0x10000U, /**< XBAR1_OUT202 output assigned to TPM4_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm5LptpmTriggerIn1 = 203|0x10000U, /**< XBAR1_OUT203 output assigned to TPM5_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm6LptpmTriggerIn1 = 204|0x10000U, /**< XBAR1_OUT204 output assigned to TPM6_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm4LptpmTriggerIn2 = 205|0x10000U, /**< XBAR1_OUT205 output assigned to TPM4_LPTPM_TRIGGER_IN2 */ + kXBAR1_OutputTpm4LptpmTriggerIn3 = 206|0x10000U, /**< XBAR1_OUT206 output assigned to TPM4_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm5LptpmTriggerIn3 = 207|0x10000U, /**< XBAR1_OUT207 output assigned to TPM5_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm6LptpmTriggerIn3 = 208|0x10000U, /**< XBAR1_OUT208 output assigned to TPM6_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputNetcTmr11588Trig1 = 209|0x10000U, /**< XBAR1_OUT209 output assigned to NETC_TMR1_1588_TRIG1 */ + kXBAR1_OutputNetcTmr11588Trig2 = 210|0x10000U, /**< XBAR1_OUT210 output assigned to NETC_TMR1_1588_TRIG2 */ + kXBAR1_OutputNetcTmr21588Trig1 = 211|0x10000U, /**< XBAR1_OUT211 output assigned to NETC_TMR2_1588_TRIG1 */ + kXBAR1_OutputNetcTmr21588Trig2 = 212|0x10000U, /**< XBAR1_OUT212 output assigned to NETC_TMR2_1588_TRIG2 */ + kXBAR1_OutputNetcTmr31588Trig1 = 213|0x10000U, /**< XBAR1_OUT213 output assigned to NETC_TMR3_1588_TRIG1 */ + kXBAR1_OutputNetcTmr31588Trig2 = 214|0x10000U, /**< XBAR1_OUT214 output assigned to NETC_TMR3_1588_TRIG2 */ + kXBAR1_OutputEnc1Icap1 = 215|0x10000U, /**< XBAR1_OUT215 output assigned to ENC1_ICAP1 */ + kXBAR1_OutputEnc1Icap2 = 216|0x10000U, /**< XBAR1_OUT216 output assigned to ENC1_ICAP2 */ + kXBAR1_OutputEnc1Icap3 = 217|0x10000U, /**< XBAR1_OUT217 output assigned to ENC1_ICAP3 */ + kXBAR1_OutputEnc2Icap1 = 218|0x10000U, /**< XBAR1_OUT218 output assigned to ENC2_ICAP1 */ + kXBAR1_OutputEnc2Icap2 = 219|0x10000U, /**< XBAR1_OUT219 output assigned to ENC2_ICAP2 */ + kXBAR1_OutputEnc2Icap3 = 220|0x10000U, /**< XBAR1_OUT220 output assigned to ENC2_ICAP3 */ + kXBAR1_OutputEnc3Icap1 = 221|0x10000U, /**< XBAR1_OUT221 output assigned to ENC3_ICAP1 */ + kXBAR1_OutputEnc3Icap2 = 222|0x10000U, /**< XBAR1_OUT222 output assigned to ENC3_ICAP2 */ + kXBAR1_OutputEnc3Icap3 = 223|0x10000U, /**< XBAR1_OUT223 output assigned to ENC3_ICAP3 */ + kXBAR1_OutputEnc4Icap1 = 224|0x10000U, /**< XBAR1_OUT224 output assigned to ENC4_ICAP1 */ + kXBAR1_OutputEnc4Icap2 = 225|0x10000U, /**< XBAR1_OUT225 output assigned to ENC4_ICAP2 */ + kXBAR1_OutputEnc4Icap3 = 226|0x10000U, /**< XBAR1_OUT226 output assigned to ENC4_ICAP3 */ + kXBAR1_OutputEcatLatchIn0 = 227|0x10000U, /**< XBAR1_OUT227 output assigned to ECAT_LATCH_IN0 */ + kXBAR1_OutputEcatLatchIn1 = 228|0x10000U, /**< XBAR1_OUT228 output assigned to ECAT_LATCH_IN1 */ + kXBAR1_OutputSafetyClkMonDutClk = 229|0x10000U, /**< XBAR1_OUT229 output assigned to SAFETY_CLK_MON_DUT_CLK */ + kXBAR1_OutputEndat21StrN = 230|0x10000U, /**< XBAR1_OUT230 output assigned to ENDAT2_1_STR_N */ + kXBAR1_OutputEndat21Ir6N = 231|0x10000U, /**< XBAR1_OUT231 output assigned to ENDAT2_1_IR6_N */ + kXBAR1_OutputEndat21Ir7N = 232|0x10000U, /**< XBAR1_OUT232 output assigned to ENDAT2_1_IR7_N */ + kXBAR1_OutputEndat22StrN = 233|0x10000U, /**< XBAR1_OUT233 output assigned to ENDAT2_2_STR_N */ + kXBAR1_OutputEndat22Ir6N = 234|0x10000U, /**< XBAR1_OUT234 output assigned to ENDAT2_2_IR6_N */ + kXBAR1_OutputEndat22Ir7N = 235|0x10000U, /**< XBAR1_OUT235 output assigned to ENDAT2_2_IR7_N */ + kXBAR1_OutputEndat3HwStrobe = 236|0x10000U, /**< XBAR1_OUT236 output assigned to ENDAT3_HW_STROBE */ + kXBAR1_OutputBissGetsens = 237|0x10000U, /**< XBAR1_OUT237 output assigned to BISS_GETSENS */ + kXBAR1_OutputSinc3ExtTrigger2 = 238|0x10000U, /**< XBAR1_OUT238 output assigned to SINC3_EXT_TRIGGER2 */ + kXBAR1_OutputSinc3ExtTrigger3 = 239|0x10000U, /**< XBAR1_OUT239 output assigned to SINC3_EXT_TRIGGER3 */ + kXBAR1_OutputHiperface1SyncXbar = 240|0x10000U, /**< XBAR1_OUT240 output assigned to HIPERFACE1_SYNC_XBAR */ + kXBAR1_OutputHiperface2SyncXbar = 241|0x10000U, /**< XBAR1_OUT241 output assigned to HIPERFACE2_SYNC_XBAR */ + kXBAR1_OutputTriggerSyncAsyncIn8 = 242|0x10000U, /**< XBAR1_OUT242 output assigned to TRIGGER_SYNC_ASYNC_IN8 */ + kXBAR1_OutputTriggerSyncAsyncIn9 = 243|0x10000U, /**< XBAR1_OUT243 output assigned to TRIGGER_SYNC_ASYNC_IN9 */ + kXBAR1_OutputTriggerSyncAsyncIn10 = 244|0x10000U, /**< XBAR1_OUT244 output assigned to TRIGGER_SYNC_ASYNC_IN10 */ + kXBAR1_OutputTriggerSyncAsyncIn11 = 245|0x10000U, /**< XBAR1_OUT245 output assigned to TRIGGER_SYNC_ASYNC_IN11 */ + kXBAR1_OutputTriggerSyncAsyncIn12 = 246|0x10000U, /**< XBAR1_OUT246 output assigned to TRIGGER_SYNC_ASYNC_IN12 */ + kXBAR1_OutputTriggerSyncAsyncIn13 = 247|0x10000U, /**< XBAR1_OUT247 output assigned to TRIGGER_SYNC_ASYNC_IN13 */ + kXBAR1_OutputTriggerSyncAsyncIn14 = 248|0x10000U, /**< XBAR1_OUT248 output assigned to TRIGGER_SYNC_ASYNC_IN14 */ + kXBAR1_OutputTriggerSyncAsyncIn15 = 249|0x10000U, /**< XBAR1_OUT249 output assigned to TRIGGER_SYNC_ASYNC_IN15 */ + kXBAR1_OutputSinc2ExtTrigger0 = 250|0x10000U, /**< XBAR1_OUT250 output assigned to SINC2_EXT_TRIGGER0 */ + kXBAR1_OutputSinc2ExtTrigger1 = 251|0x10000U, /**< XBAR1_OUT251 output assigned to SINC2_EXT_TRIGGER1 */ + kXBAR1_OutputSinc2ExtTrigger2 = 252|0x10000U, /**< XBAR1_OUT252 output assigned to SINC2_EXT_TRIGGER2 */ + kXBAR1_OutputSinc2ExtTrigger3 = 253|0x10000U, /**< XBAR1_OUT253 output assigned to SINC2_EXT_TRIGGER3 */ + kXBAR1_OutputSinc3ExtTrigger0 = 254|0x10000U, /**< XBAR1_OUT254 output assigned to SINC3_EXT_TRIGGER0 */ + kXBAR1_OutputSinc3ExtTrigger1 = 255|0x10000U, /**< XBAR1_OUT255 output assigned to SINC3_EXT_TRIGGER1 */ + kXBAR2_OutputAoi1In00 = 0|0x20000U, /**< XBAR2_OUT0 output assigned to AOI1_IN00 */ + kXBAR2_OutputAoi1In01 = 1|0x20000U, /**< XBAR2_OUT1 output assigned to AOI1_IN01 */ + kXBAR2_OutputAoi1In02 = 2|0x20000U, /**< XBAR2_OUT2 output assigned to AOI1_IN02 */ + kXBAR2_OutputAoi1In03 = 3|0x20000U, /**< XBAR2_OUT3 output assigned to AOI1_IN03 */ + kXBAR2_OutputAoi1In04 = 4|0x20000U, /**< XBAR2_OUT4 output assigned to AOI1_IN04 */ + kXBAR2_OutputAoi1In05 = 5|0x20000U, /**< XBAR2_OUT5 output assigned to AOI1_IN05 */ + kXBAR2_OutputAoi1In06 = 6|0x20000U, /**< XBAR2_OUT6 output assigned to AOI1_IN06 */ + kXBAR2_OutputAoi1In07 = 7|0x20000U, /**< XBAR2_OUT7 output assigned to AOI1_IN07 */ + kXBAR2_OutputAoi1In08 = 8|0x20000U, /**< XBAR2_OUT8 output assigned to AOI1_IN08 */ + kXBAR2_OutputAoi1In09 = 9|0x20000U, /**< XBAR2_OUT9 output assigned to AOI1_IN09 */ + kXBAR2_OutputAoi1In10 = 10|0x20000U, /**< XBAR2_OUT10 output assigned to AOI1_IN10 */ + kXBAR2_OutputAoi1In11 = 11|0x20000U, /**< XBAR2_OUT11 output assigned to AOI1_IN11 */ + kXBAR2_OutputAoi1In12 = 12|0x20000U, /**< XBAR2_OUT12 output assigned to AOI1_IN12 */ + kXBAR2_OutputAoi1In13 = 13|0x20000U, /**< XBAR2_OUT13 output assigned to AOI1_IN13 */ + kXBAR2_OutputAoi1In14 = 14|0x20000U, /**< XBAR2_OUT14 output assigned to AOI1_IN14 */ + kXBAR2_OutputAoi1In15 = 15|0x20000U, /**< XBAR2_OUT15 output assigned to AOI1_IN15 */ + kXBAR2_OutputAoi3In00 = 16|0x20000U, /**< XBAR2_OUT16 output assigned to AOI3_IN00 */ + kXBAR2_OutputAoi3In01 = 17|0x20000U, /**< XBAR2_OUT17 output assigned to AOI3_IN01 */ + kXBAR2_OutputAoi3In02 = 18|0x20000U, /**< XBAR2_OUT18 output assigned to AOI3_IN02 */ + kXBAR2_OutputAoi3In03 = 19|0x20000U, /**< XBAR2_OUT19 output assigned to AOI3_IN03 */ + kXBAR2_OutputAoi3In04 = 20|0x20000U, /**< XBAR2_OUT20 output assigned to AOI3_IN04 */ + kXBAR2_OutputAoi3In05 = 21|0x20000U, /**< XBAR2_OUT21 output assigned to AOI3_IN05 */ + kXBAR2_OutputAoi3In06 = 22|0x20000U, /**< XBAR2_OUT22 output assigned to AOI3_IN06 */ + kXBAR2_OutputAoi3In07 = 23|0x20000U, /**< XBAR2_OUT23 output assigned to AOI3_IN07 */ + kXBAR2_OutputAoi3In08 = 24|0x20000U, /**< XBAR2_OUT24 output assigned to AOI3_IN08 */ + kXBAR2_OutputAoi3In09 = 25|0x20000U, /**< XBAR2_OUT25 output assigned to AOI3_IN09 */ + kXBAR2_OutputAoi3In10 = 26|0x20000U, /**< XBAR2_OUT26 output assigned to AOI3_IN10 */ + kXBAR2_OutputAoi3In11 = 27|0x20000U, /**< XBAR2_OUT27 output assigned to AOI3_IN11 */ + kXBAR2_OutputAoi3In12 = 28|0x20000U, /**< XBAR2_OUT28 output assigned to AOI3_IN12 */ + kXBAR2_OutputAoi3In13 = 29|0x20000U, /**< XBAR2_OUT29 output assigned to AOI3_IN13 */ + kXBAR2_OutputAoi3In14 = 30|0x20000U, /**< XBAR2_OUT30 output assigned to AOI3_IN14 */ + kXBAR2_OutputAoi3In15 = 31|0x20000U, /**< XBAR2_OUT31 output assigned to AOI3_IN15 */ + kXBAR3_OutputAoi2In00 = 0|0x30000U, /**< XBAR3_OUT0 output assigned to AOI2_IN00 */ + kXBAR3_OutputAoi2In01 = 1|0x30000U, /**< XBAR3_OUT1 output assigned to AOI2_IN01 */ + kXBAR3_OutputAoi2In02 = 2|0x30000U, /**< XBAR3_OUT2 output assigned to AOI2_IN02 */ + kXBAR3_OutputAoi2In03 = 3|0x30000U, /**< XBAR3_OUT3 output assigned to AOI2_IN03 */ + kXBAR3_OutputAoi2In04 = 4|0x30000U, /**< XBAR3_OUT4 output assigned to AOI2_IN04 */ + kXBAR3_OutputAoi2In05 = 5|0x30000U, /**< XBAR3_OUT5 output assigned to AOI2_IN05 */ + kXBAR3_OutputAoi2In06 = 6|0x30000U, /**< XBAR3_OUT6 output assigned to AOI2_IN06 */ + kXBAR3_OutputAoi2In07 = 7|0x30000U, /**< XBAR3_OUT7 output assigned to AOI2_IN07 */ + kXBAR3_OutputAoi2In08 = 8|0x30000U, /**< XBAR3_OUT8 output assigned to AOI2_IN08 */ + kXBAR3_OutputAoi2In09 = 9|0x30000U, /**< XBAR3_OUT9 output assigned to AOI2_IN09 */ + kXBAR3_OutputAoi2In10 = 10|0x30000U, /**< XBAR3_OUT10 output assigned to AOI2_IN10 */ + kXBAR3_OutputAoi2In11 = 11|0x30000U, /**< XBAR3_OUT11 output assigned to AOI2_IN11 */ + kXBAR3_OutputAoi2In12 = 12|0x30000U, /**< XBAR3_OUT12 output assigned to AOI2_IN12 */ + kXBAR3_OutputAoi2In13 = 13|0x30000U, /**< XBAR3_OUT13 output assigned to AOI2_IN13 */ + kXBAR3_OutputAoi2In14 = 14|0x30000U, /**< XBAR3_OUT14 output assigned to AOI2_IN14 */ + kXBAR3_OutputAoi2In15 = 15|0x30000U, /**< XBAR3_OUT15 output assigned to AOI2_IN15 */ + kXBAR3_OutputAoi4In00 = 16|0x30000U, /**< XBAR3_OUT16 output assigned to AOI4_IN00 */ + kXBAR3_OutputAoi4In01 = 17|0x30000U, /**< XBAR3_OUT17 output assigned to AOI4_IN01 */ + kXBAR3_OutputAoi4In02 = 18|0x30000U, /**< XBAR3_OUT18 output assigned to AOI4_IN02 */ + kXBAR3_OutputAoi4In03 = 19|0x30000U, /**< XBAR3_OUT19 output assigned to AOI4_IN03 */ + kXBAR3_OutputAoi4In04 = 20|0x30000U, /**< XBAR3_OUT20 output assigned to AOI4_IN04 */ + kXBAR3_OutputAoi4In05 = 21|0x30000U, /**< XBAR3_OUT21 output assigned to AOI4_IN05 */ + kXBAR3_OutputAoi4In06 = 22|0x30000U, /**< XBAR3_OUT22 output assigned to AOI4_IN06 */ + kXBAR3_OutputAoi4In07 = 23|0x30000U, /**< XBAR3_OUT23 output assigned to AOI4_IN07 */ + kXBAR3_OutputAoi4In08 = 24|0x30000U, /**< XBAR3_OUT24 output assigned to AOI4_IN08 */ + kXBAR3_OutputAoi4In09 = 25|0x30000U, /**< XBAR3_OUT25 output assigned to AOI4_IN09 */ + kXBAR3_OutputAoi4In10 = 26|0x30000U, /**< XBAR3_OUT26 output assigned to AOI4_IN10 */ + kXBAR3_OutputAoi4In11 = 27|0x30000U, /**< XBAR3_OUT27 output assigned to AOI4_IN11 */ + kXBAR3_OutputAoi4In12 = 28|0x30000U, /**< XBAR3_OUT28 output assigned to AOI4_IN12 */ + kXBAR3_OutputAoi4In13 = 29|0x30000U, /**< XBAR3_OUT29 output assigned to AOI4_IN13 */ + kXBAR3_OutputAoi4In14 = 30|0x30000U, /**< XBAR3_OUT30 output assigned to AOI4_IN14 */ + kXBAR3_OutputAoi4In15 = 31|0x30000U, /**< XBAR3_OUT31 output assigned to AOI4_IN15 */ +} xbar_output_signal_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ADC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ADC base address */ @@ -2187,6 +3279,35 @@ typedef enum IRQn { #define DCIF_BASE_PTRS { DCIF } #endif +/* DDRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DDRC base address */ + #define DDRC_BASE (0x5E080000u) + /** Peripheral DDRC base address */ + #define DDRC_BASE_NS (0x4E080000u) + /** Peripheral DDRC base pointer */ + #define DDRC ((DDRC_Type *)DDRC_BASE) + /** Peripheral DDRC base pointer */ + #define DDRC_NS ((DDRC_Type *)DDRC_BASE_NS) + /** Array initializer of DDRC peripheral base addresses */ + #define DDRC_BASE_ADDRS { DDRC_BASE } + /** Array initializer of DDRC peripheral base pointers */ + #define DDRC_BASE_PTRS { DDRC } + /** Array initializer of DDRC peripheral base addresses */ + #define DDRC_BASE_ADDRS_NS { DDRC_BASE_NS } + /** Array initializer of DDRC peripheral base pointers */ + #define DDRC_BASE_PTRS_NS { DDRC_NS } +#else + /** Peripheral DDRC base address */ + #define DDRC_BASE (0x4E080000u) + /** Peripheral DDRC base pointer */ + #define DDRC ((DDRC_Type *)DDRC_BASE) + /** Array initializer of DDRC peripheral base addresses */ + #define DDRC_BASE_ADDRS { DDRC_BASE } + /** Array initializer of DDRC peripheral base pointers */ + #define DDRC_BASE_PTRS { DDRC } +#endif + /* DDR_BLK_CTRL_DDRMIX - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral BLK_CTRL_DDRMIX base address */ @@ -2257,35 +3378,6 @@ typedef enum IRQn { #define DDR_CMU_BASE_PTRS { DDRC__CMU_1, DDRC__CMU_2 } #endif -/* DDR_DDRC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DDRC base address */ - #define DDRC_BASE (0x5E080000u) - /** Peripheral DDRC base address */ - #define DDRC_BASE_NS (0x4E080000u) - /** Peripheral DDRC base pointer */ - #define DDRC ((DDR_DDRC_Type *)DDRC_BASE) - /** Peripheral DDRC base pointer */ - #define DDRC_NS ((DDR_DDRC_Type *)DDRC_BASE_NS) - /** Array initializer of DDR_DDRC peripheral base addresses */ - #define DDR_DDRC_BASE_ADDRS { DDRC_BASE } - /** Array initializer of DDR_DDRC peripheral base pointers */ - #define DDR_DDRC_BASE_PTRS { DDRC } - /** Array initializer of DDR_DDRC peripheral base addresses */ - #define DDR_DDRC_BASE_ADDRS_NS { DDRC_BASE_NS } - /** Array initializer of DDR_DDRC peripheral base pointers */ - #define DDR_DDRC_BASE_PTRS_NS { DDRC_NS } -#else - /** Peripheral DDRC base address */ - #define DDRC_BASE (0x4E080000u) - /** Peripheral DDRC base pointer */ - #define DDRC ((DDR_DDRC_Type *)DDRC_BASE) - /** Array initializer of DDR_DDRC peripheral base addresses */ - #define DDR_DDRC_BASE_ADDRS { DDRC_BASE } - /** Array initializer of DDR_DDRC peripheral base pointers */ - #define DDR_DDRC_BASE_PTRS { DDRC } -#endif - /* DDR_LSTCU - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral DDRC__LSTCU base address */ @@ -3571,23 +4663,59 @@ typedef enum IRQn { #define GPT1 ((GPT_Type *)GPT1_BASE) /** Peripheral GPT1 base pointer */ #define GPT1_NS ((GPT_Type *)GPT1_BASE_NS) + /** Peripheral GPT2 base address */ + #define GPT2_BASE (0x528A0000u) + /** Peripheral GPT2 base address */ + #define GPT2_BASE_NS (0x428A0000u) + /** Peripheral GPT2 base pointer */ + #define GPT2 ((GPT_Type *)GPT2_BASE) + /** Peripheral GPT2 base pointer */ + #define GPT2_NS ((GPT_Type *)GPT2_BASE_NS) + /** Peripheral GPT3 base address */ + #define GPT3_BASE (0x528B0000u) + /** Peripheral GPT3 base address */ + #define GPT3_BASE_NS (0x428B0000u) + /** Peripheral GPT3 base pointer */ + #define GPT3 ((GPT_Type *)GPT3_BASE) + /** Peripheral GPT3 base pointer */ + #define GPT3_NS ((GPT_Type *)GPT3_BASE_NS) + /** Peripheral GPT4 base address */ + #define GPT4_BASE (0x528C0000u) + /** Peripheral GPT4 base address */ + #define GPT4_BASE_NS (0x428C0000u) + /** Peripheral GPT4 base pointer */ + #define GPT4 ((GPT_Type *)GPT4_BASE) + /** Peripheral GPT4 base pointer */ + #define GPT4_NS ((GPT_Type *)GPT4_BASE_NS) /** Array initializer of GPT peripheral base addresses */ - #define GPT_BASE_ADDRS { GPT1_BASE } + #define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE } /** Array initializer of GPT peripheral base pointers */ - #define GPT_BASE_PTRS { GPT1 } + #define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4 } /** Array initializer of GPT peripheral base addresses */ - #define GPT_BASE_ADDRS_NS { GPT1_BASE_NS } + #define GPT_BASE_ADDRS_NS { 0u, GPT1_BASE_NS, GPT2_BASE_NS, GPT3_BASE_NS, GPT4_BASE_NS } /** Array initializer of GPT peripheral base pointers */ - #define GPT_BASE_PTRS_NS { GPT1_NS } + #define GPT_BASE_PTRS_NS { (GPT_Type *)0u, GPT1_NS, GPT2_NS, GPT3_NS, GPT4_NS } #else /** Peripheral GPT1 base address */ #define GPT1_BASE (0x446F0000u) /** Peripheral GPT1 base pointer */ #define GPT1 ((GPT_Type *)GPT1_BASE) + /** Peripheral GPT2 base address */ + #define GPT2_BASE (0x428A0000u) + /** Peripheral GPT2 base pointer */ + #define GPT2 ((GPT_Type *)GPT2_BASE) + /** Peripheral GPT3 base address */ + #define GPT3_BASE (0x428B0000u) + /** Peripheral GPT3 base pointer */ + #define GPT3 ((GPT_Type *)GPT3_BASE) + /** Peripheral GPT4 base address */ + #define GPT4_BASE (0x428C0000u) + /** Peripheral GPT4 base pointer */ + #define GPT4 ((GPT_Type *)GPT4_BASE) /** Array initializer of GPT peripheral base addresses */ - #define GPT_BASE_ADDRS { GPT1_BASE } + #define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE } /** Array initializer of GPT peripheral base pointers */ - #define GPT_BASE_PTRS { GPT1 } + #define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4 } #endif /* HIPERFACE - Peripheral instance base addresses */ @@ -3728,6 +4856,14 @@ typedef enum IRQn { #define SAI1 ((I2S_Type *)SAI1_BASE) /** Peripheral SAI1 base pointer */ #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Peripheral SAI2 base address */ + #define SAI2_BASE (0x52650000u) + /** Peripheral SAI2 base address */ + #define SAI2_BASE_NS (0x42650000u) + /** Peripheral SAI2 base pointer */ + #define SAI2 ((I2S_Type *)SAI2_BASE) + /** Peripheral SAI2 base pointer */ + #define SAI2_NS ((I2S_Type *)SAI2_BASE_NS) /** Peripheral SAI3 base address */ #define SAI3_BASE (0x52660000u) /** Peripheral SAI3 base address */ @@ -3745,18 +4881,22 @@ typedef enum IRQn { /** Peripheral SAI4 base pointer */ #define SAI4_NS ((I2S_Type *)SAI4_BASE_NS) /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { 0u, SAI1_BASE, 0u, SAI3_BASE, SAI4_BASE } + #define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE } /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, (I2S_Type *)0u, SAI3, SAI4 } + #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 } /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { 0u, SAI1_BASE_NS, 0u, SAI3_BASE_NS, SAI4_BASE_NS } + #define I2S_BASE_ADDRS_NS { 0u, SAI1_BASE_NS, SAI2_BASE_NS, SAI3_BASE_NS, SAI4_BASE_NS } /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { (I2S_Type *)0u, SAI1_NS, (I2S_Type *)0u, SAI3_NS, SAI4_NS } + #define I2S_BASE_PTRS_NS { (I2S_Type *)0u, SAI1_NS, SAI2_NS, SAI3_NS, SAI4_NS } #else /** Peripheral SAI1 base address */ #define SAI1_BASE (0x443B0000u) /** Peripheral SAI1 base pointer */ #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI2 base address */ + #define SAI2_BASE (0x42650000u) + /** Peripheral SAI2 base pointer */ + #define SAI2 ((I2S_Type *)SAI2_BASE) /** Peripheral SAI3 base address */ #define SAI3_BASE (0x42660000u) /** Peripheral SAI3 base pointer */ @@ -3766,13 +4906,13 @@ typedef enum IRQn { /** Peripheral SAI4 base pointer */ #define SAI4 ((I2S_Type *)SAI4_BASE) /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { 0u, SAI1_BASE, 0u, SAI3_BASE, SAI4_BASE } + #define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE } /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, (I2S_Type *)0u, SAI3, SAI4 } + #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 } #endif /** Interrupt vectors for the I2S peripheral type */ -#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, NotAvail_IRQn, SAI3_IRQn, SAI4_IRQn } -#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, NotAvail_IRQn, SAI3_IRQn, SAI4_IRQn } +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn } /* I3C - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -4393,7 +5533,7 @@ typedef enum IRQn { #define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12 } #endif /** Interrupt vectors for the LPUART peripheral type */ -#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn } +#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn } /* M7_A7_APB_MCM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -4777,6 +5917,8 @@ typedef enum IRQn { /** Array initializer of MSGINTR peripheral base pointers */ #define MSGINTR_BASE_PTRS { (MSGINTR_Type *)0u, MSGINTR1, MSGINTR2, MSGINTR3, MSGINTR4, MSGINTR5, MSGINTR6, MSGINTR7, MSGINTR8 } #endif +/** Interrupt vectors for the MSGINTR peripheral type */ +#define MSGINTR_IRQS { NotAvail_IRQn, MSGINTR1_IRQn, MSGINTR2_IRQn, MSGINTR3_IRQn, MSGINTR4_IRQn, MSGINTR5_IRQn, MSGINTR6_IRQn, MSGINTR7_IRQn, MSGINTR8_IRQn } /* MU - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -10060,13 +11202,13 @@ typedef enum IRQn { /** Peripheral TMR8 base pointer */ #define TMR8_NS ((TMR_Type *)TMR8_BASE_NS) /** Array initializer of TMR peripheral base addresses */ - #define TMR_BASE_ADDRS { TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } + #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } /** Array initializer of TMR peripheral base pointers */ - #define TMR_BASE_PTRS { TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } + #define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } /** Array initializer of TMR peripheral base addresses */ - #define TMR_BASE_ADDRS_NS { TMR1_BASE_NS, TMR2_BASE_NS, TMR3_BASE_NS, TMR4_BASE_NS, TMR5_BASE_NS, TMR6_BASE_NS, TMR7_BASE_NS, TMR8_BASE_NS } + #define TMR_BASE_ADDRS_NS { 0u, TMR1_BASE_NS, TMR2_BASE_NS, TMR3_BASE_NS, TMR4_BASE_NS, TMR5_BASE_NS, TMR6_BASE_NS, TMR7_BASE_NS, TMR8_BASE_NS } /** Array initializer of TMR peripheral base pointers */ - #define TMR_BASE_PTRS_NS { TMR1_NS, TMR2_NS, TMR3_NS, TMR4_NS, TMR5_NS, TMR6_NS, TMR7_NS, TMR8_NS } + #define TMR_BASE_PTRS_NS { (TMR_Type *)0u, TMR1_NS, TMR2_NS, TMR3_NS, TMR4_NS, TMR5_NS, TMR6_NS, TMR7_NS, TMR8_NS } #else /** Peripheral TMR1 base address */ #define TMR1_BASE (0x428D0000u) @@ -10101,9 +11243,9 @@ typedef enum IRQn { /** Peripheral TMR8 base pointer */ #define TMR8 ((TMR_Type *)TMR8_BASE) /** Array initializer of TMR peripheral base addresses */ - #define TMR_BASE_ADDRS { TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } + #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } /** Array initializer of TMR peripheral base pointers */ - #define TMR_BASE_PTRS { TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } + #define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } #endif /* TMR_GLOBAL - Peripheral instance base addresses */ @@ -10723,88 +11865,6 @@ typedef enum IRQn { #define WAKEUP_ERM_BASE_PTRS { WAKEUP__ERM } #endif -/* WAKEUP_GPT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GPT2 base address */ - #define GPT2_BASE (0x528A0000u) - /** Peripheral GPT2 base address */ - #define GPT2_BASE_NS (0x428A0000u) - /** Peripheral GPT2 base pointer */ - #define GPT2 ((WAKEUP_GPT_Type *)GPT2_BASE) - /** Peripheral GPT2 base pointer */ - #define GPT2_NS ((WAKEUP_GPT_Type *)GPT2_BASE_NS) - /** Peripheral GPT3 base address */ - #define GPT3_BASE (0x528B0000u) - /** Peripheral GPT3 base address */ - #define GPT3_BASE_NS (0x428B0000u) - /** Peripheral GPT3 base pointer */ - #define GPT3 ((WAKEUP_GPT_Type *)GPT3_BASE) - /** Peripheral GPT3 base pointer */ - #define GPT3_NS ((WAKEUP_GPT_Type *)GPT3_BASE_NS) - /** Peripheral GPT4 base address */ - #define GPT4_BASE (0x528C0000u) - /** Peripheral GPT4 base address */ - #define GPT4_BASE_NS (0x428C0000u) - /** Peripheral GPT4 base pointer */ - #define GPT4 ((WAKEUP_GPT_Type *)GPT4_BASE) - /** Peripheral GPT4 base pointer */ - #define GPT4_NS ((WAKEUP_GPT_Type *)GPT4_BASE_NS) - /** Array initializer of WAKEUP_GPT peripheral base addresses */ - #define WAKEUP_GPT_BASE_ADDRS { 0u, 0u, GPT2_BASE, GPT3_BASE, GPT4_BASE } - /** Array initializer of WAKEUP_GPT peripheral base pointers */ - #define WAKEUP_GPT_BASE_PTRS { (WAKEUP_GPT_Type *)0u, (WAKEUP_GPT_Type *)0u, GPT2, GPT3, GPT4 } - /** Array initializer of WAKEUP_GPT peripheral base addresses */ - #define WAKEUP_GPT_BASE_ADDRS_NS { 0u, 0u, GPT2_BASE_NS, GPT3_BASE_NS, GPT4_BASE_NS } - /** Array initializer of WAKEUP_GPT peripheral base pointers */ - #define WAKEUP_GPT_BASE_PTRS_NS { (WAKEUP_GPT_Type *)0u, (WAKEUP_GPT_Type *)0u, GPT2_NS, GPT3_NS, GPT4_NS } -#else - /** Peripheral GPT2 base address */ - #define GPT2_BASE (0x428A0000u) - /** Peripheral GPT2 base pointer */ - #define GPT2 ((WAKEUP_GPT_Type *)GPT2_BASE) - /** Peripheral GPT3 base address */ - #define GPT3_BASE (0x428B0000u) - /** Peripheral GPT3 base pointer */ - #define GPT3 ((WAKEUP_GPT_Type *)GPT3_BASE) - /** Peripheral GPT4 base address */ - #define GPT4_BASE (0x428C0000u) - /** Peripheral GPT4 base pointer */ - #define GPT4 ((WAKEUP_GPT_Type *)GPT4_BASE) - /** Array initializer of WAKEUP_GPT peripheral base addresses */ - #define WAKEUP_GPT_BASE_ADDRS { 0u, 0u, GPT2_BASE, GPT3_BASE, GPT4_BASE } - /** Array initializer of WAKEUP_GPT peripheral base pointers */ - #define WAKEUP_GPT_BASE_PTRS { (WAKEUP_GPT_Type *)0u, (WAKEUP_GPT_Type *)0u, GPT2, GPT3, GPT4 } -#endif - -/* WAKEUP_SAI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral WAKEUP__SAI2 base address */ - #define WAKEUP__SAI2_BASE (0x52650000u) - /** Peripheral WAKEUP__SAI2 base address */ - #define WAKEUP__SAI2_BASE_NS (0x42650000u) - /** Peripheral WAKEUP__SAI2 base pointer */ - #define WAKEUP__SAI2 ((WAKEUP_SAI_Type *)WAKEUP__SAI2_BASE) - /** Peripheral WAKEUP__SAI2 base pointer */ - #define WAKEUP__SAI2_NS ((WAKEUP_SAI_Type *)WAKEUP__SAI2_BASE_NS) - /** Array initializer of WAKEUP_SAI peripheral base addresses */ - #define WAKEUP_SAI_BASE_ADDRS { WAKEUP__SAI2_BASE } - /** Array initializer of WAKEUP_SAI peripheral base pointers */ - #define WAKEUP_SAI_BASE_PTRS { WAKEUP__SAI2 } - /** Array initializer of WAKEUP_SAI peripheral base addresses */ - #define WAKEUP_SAI_BASE_ADDRS_NS { WAKEUP__SAI2_BASE_NS } - /** Array initializer of WAKEUP_SAI peripheral base pointers */ - #define WAKEUP_SAI_BASE_PTRS_NS { WAKEUP__SAI2_NS } -#else - /** Peripheral WAKEUP__SAI2 base address */ - #define WAKEUP__SAI2_BASE (0x42650000u) - /** Peripheral WAKEUP__SAI2 base pointer */ - #define WAKEUP__SAI2 ((WAKEUP_SAI_Type *)WAKEUP__SAI2_BASE) - /** Array initializer of WAKEUP_SAI peripheral base addresses */ - #define WAKEUP_SAI_BASE_ADDRS { WAKEUP__SAI2_BASE } - /** Array initializer of WAKEUP_SAI peripheral base pointers */ - #define WAKEUP_SAI_BASE_PTRS { WAKEUP__SAI2 } -#endif - /* WAKEUP_TCW - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral WAKEUP__TCW base address */ @@ -11543,3 +12603,4 @@ typedef enum #endif /* MIMX94398_CM33_CORE0_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0_features.h index 4787ae00b..dcc3674b0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2023-11-01 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -53,8 +53,8 @@ #define FSL_FEATURE_SOC_AXBS_COUNT (2) /* @brief BBNSM availability on the SoC. */ #define FSL_FEATURE_SOC_BBNSM_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (1) +/* @brief DDRC availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_COUNT (1) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (4) /* @brief EIM availability on the SoC. */ @@ -74,7 +74,7 @@ /* @brief I3C availability on the SoC. */ #define FSL_FEATURE_SOC_I3C_COUNT (2) /* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (3) +#define FSL_FEATURE_SOC_I2S_COUNT (4) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ @@ -134,6 +134,8 @@ #define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) /* @brief Self-test threshold counts of ADC. */ #define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) +/* @brief Has external trigger or not. */ +#define FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER (1) /* AOI module features */ @@ -231,6 +233,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* TMPSNS module features */ @@ -400,8 +406,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -430,6 +434,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* RGPIO module features */ @@ -459,14 +465,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -565,8 +571,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -609,6 +613,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -771,6 +779,18 @@ #define FSL_FEATURE_NETC_HAS_NO_XGMII (1) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (1) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (1) /* @brief NXP Switch port group support. */ @@ -863,18 +883,18 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ + (((x) == SAI2) ? (128) : \ (((x) == SAI3) ? (128) : \ - (((x) == SAI4) ? (128) : (-1)))) + (((x) == SAI4) ? (128) : (-1))))) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ (((x) == SAI1) ? (2) : \ + (((x) == SAI2) ? (1) : \ (((x) == SAI3) ? (1) : \ - (((x) == SAI4) ? (1) : (-1)))) + (((x) == SAI4) ? (1) : (-1))))) /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ @@ -899,14 +919,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1.h index 101a0d824..1ebfdb60e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1.h @@ -30,8 +30,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: iMX943RM rev1 draftK -** Version: rev. 1.0, 2023-11-01 -** Build: b250115 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX94398_cm33_core1 @@ -66,14 +66,17 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX94398_cm33_core1.h - * @version 1.0 - * @date 2023-11-01 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX94398_cm33_core1 * * CMSIS Peripheral Access Layer for MIMX94398_cm33_core1 @@ -121,9 +124,9 @@ #include "PERI_CCMSRCGPC_TCU.h" #include "PERI_CORTEXA_TCU.h" #include "PERI_DCIF.h" +#include "PERI_DDRC.h" #include "PERI_DDR_BLK_CTRL_DDRMIX.h" #include "PERI_DDR_CMU.h" -#include "PERI_DDR_DDRC.h" #include "PERI_DDR_LSTCU.h" #include "PERI_DDR_TCU.h" #include "PERI_DISPLAY_BLK_CTRL_DISPLAYMIX.h" @@ -314,8 +317,6 @@ #include "PERI_WAKEUP_DMA_CRC.h" #include "PERI_WAKEUP_EIM.h" #include "PERI_WAKEUP_ERM.h" -#include "PERI_WAKEUP_GPT.h" -#include "PERI_WAKEUP_SAI.h" #include "PERI_WAKEUP_TCW.h" #include "PERI_WAKEUP_TRDC_MGR_MEGA.h" #include "PERI_WAKEUP_USDHC.h" diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1_COMMON.h index 8a272de79..854cbb6e0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1_COMMON.h @@ -30,8 +30,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: iMX943RM rev1 draftK -** Version: rev. 1.0, 2023-11-01 -** Build: b250217 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX94398_cm33_core1 @@ -66,14 +66,17 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX94398_cm33_core1_COMMON.h - * @version 1.0 - * @date 2023-11-01 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX94398_cm33_core1 * * CMSIS Peripheral Access Layer for MIMX94398_cm33_core1 @@ -84,7 +87,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -946,6 +949,1095 @@ typedef enum IRQn { /* CPU specific feature definitions */ #include "MIMX94398_cm33_core1_features.h" +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +typedef enum _xbar_input_signal +{ + kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ + kXBAR1_InputLogicHigh = 1|0x10000U, /**< LOGIC_HIGH output assigned to XBAR1_IN1 input. */ + kXBAR1_InputLogicLow1 = 2|0x10000U, /**< LOGIC_LOW1 output assigned to XBAR1_IN2 input. */ + kXBAR1_InputLogicHigh1 = 3|0x10000U, /**< LOGIC_HIGH1 output assigned to XBAR1_IN3 input. */ + kXBAR1_InputIomuxXbarIn04 = 4|0x10000U, /**< IOMUX_XBAR_IN04 output assigned to XBAR1_IN4 input. */ + kXBAR1_InputIomuxXbarIn05 = 5|0x10000U, /**< IOMUX_XBAR_IN05 output assigned to XBAR1_IN5 input. */ + kXBAR1_InputIomuxXbarIn06 = 6|0x10000U, /**< IOMUX_XBAR_IN06 output assigned to XBAR1_IN6 input. */ + kXBAR1_InputIomuxXbarIn07 = 7|0x10000U, /**< IOMUX_XBAR_IN07 output assigned to XBAR1_IN7 input. */ + kXBAR1_InputIomuxXbarIn08 = 8|0x10000U, /**< IOMUX_XBAR_IN08 output assigned to XBAR1_IN8 input. */ + kXBAR1_InputIomuxXbarIn09 = 9|0x10000U, /**< IOMUX_XBAR_IN09 output assigned to XBAR1_IN9 input. */ + kXBAR1_InputIomuxXbarIn10 = 10|0x10000U, /**< IOMUX_XBAR_IN10 output assigned to XBAR1_IN10 input. */ + kXBAR1_InputIomuxXbarIn11 = 11|0x10000U, /**< IOMUX_XBAR_IN11 output assigned to XBAR1_IN11 input. */ + kXBAR1_InputIomuxXbarIn12 = 12|0x10000U, /**< IOMUX_XBAR_IN12 output assigned to XBAR1_IN12 input. */ + kXBAR1_InputIomuxXbarIn13 = 13|0x10000U, /**< IOMUX_XBAR_IN13 output assigned to XBAR1_IN13 input. */ + kXBAR1_InputIomuxXbarIn14 = 14|0x10000U, /**< IOMUX_XBAR_IN14 output assigned to XBAR1_IN14 input. */ + kXBAR1_InputIomuxXbarIn15 = 15|0x10000U, /**< IOMUX_XBAR_IN15 output assigned to XBAR1_IN15 input. */ + kXBAR1_InputIomuxXbarIn16 = 16|0x10000U, /**< IOMUX_XBAR_IN16 output assigned to XBAR1_IN16 input. */ + kXBAR1_InputIomuxXbarIn17 = 17|0x10000U, /**< IOMUX_XBAR_IN17 output assigned to XBAR1_IN17 input. */ + kXBAR1_InputIomuxXbarIn18 = 18|0x10000U, /**< IOMUX_XBAR_IN18 output assigned to XBAR1_IN18 input. */ + kXBAR1_InputIomuxXbarIn19 = 19|0x10000U, /**< IOMUX_XBAR_IN19 output assigned to XBAR1_IN19 input. */ + kXBAR1_InputIomuxXbarIn20 = 20|0x10000U, /**< IOMUX_XBAR_IN20 output assigned to XBAR1_IN20 input. */ + kXBAR1_InputIomuxXbarIn21 = 21|0x10000U, /**< IOMUX_XBAR_IN21 output assigned to XBAR1_IN21 input. */ + kXBAR1_InputIomuxXbarIn22 = 22|0x10000U, /**< IOMUX_XBAR_IN22 output assigned to XBAR1_IN22 input. */ + kXBAR1_InputIomuxXbarIn23 = 23|0x10000U, /**< IOMUX_XBAR_IN23 output assigned to XBAR1_IN23 input. */ + kXBAR1_InputIomuxXbarIn24 = 24|0x10000U, /**< IOMUX_XBAR_IN24 output assigned to XBAR1_IN24 input. */ + kXBAR1_InputIomuxXbarIn25 = 25|0x10000U, /**< IOMUX_XBAR_IN25 output assigned to XBAR1_IN25 input. */ + kXBAR1_InputIomuxXbarIn26 = 26|0x10000U, /**< IOMUX_XBAR_IN26 output assigned to XBAR1_IN26 input. */ + kXBAR1_InputIomuxXbarIn27 = 27|0x10000U, /**< IOMUX_XBAR_IN27 output assigned to XBAR1_IN27 input. */ + kXBAR1_InputIomuxXbarIn28 = 28|0x10000U, /**< IOMUX_XBAR_IN28 output assigned to XBAR1_IN28 input. */ + kXBAR1_InputIomuxXbarIn29 = 29|0x10000U, /**< IOMUX_XBAR_IN29 output assigned to XBAR1_IN29 input. */ + kXBAR1_InputIomuxXbarIn30 = 30|0x10000U, /**< IOMUX_XBAR_IN30 output assigned to XBAR1_IN30 input. */ + kXBAR1_InputIomuxXbarIn31 = 31|0x10000U, /**< IOMUX_XBAR_IN31 output assigned to XBAR1_IN31 input. */ + kXBAR1_InputIomuxXbarIn32 = 32|0x10000U, /**< IOMUX_XBAR_IN32 output assigned to XBAR1_IN32 input. */ + kXBAR1_InputIomuxXbarIn33 = 33|0x10000U, /**< IOMUX_XBAR_IN33 output assigned to XBAR1_IN33 input. */ + kXBAR1_InputIomuxXbarIn34 = 34|0x10000U, /**< IOMUX_XBAR_IN34 output assigned to XBAR1_IN34 input. */ + kXBAR1_InputIomuxXbarIn35 = 35|0x10000U, /**< IOMUX_XBAR_IN35 output assigned to XBAR1_IN35 input. */ + kXBAR1_InputIomuxXbarIn36 = 36|0x10000U, /**< IOMUX_XBAR_IN36 output assigned to XBAR1_IN36 input. */ + kXBAR1_InputIomuxXbarIn37 = 37|0x10000U, /**< IOMUX_XBAR_IN37 output assigned to XBAR1_IN37 input. */ + kXBAR1_InputIomuxXbarIn38 = 38|0x10000U, /**< IOMUX_XBAR_IN38 output assigned to XBAR1_IN38 input. */ + kXBAR1_InputIomuxXbarIn39 = 39|0x10000U, /**< IOMUX_XBAR_IN39 output assigned to XBAR1_IN39 input. */ + kXBAR1_InputIomuxXbarIn40 = 40|0x10000U, /**< IOMUX_XBAR_IN40 output assigned to XBAR1_IN40 input. */ + kXBAR1_InputIomuxXbarIn41 = 41|0x10000U, /**< IOMUX_XBAR_IN41 output assigned to XBAR1_IN41 input. */ + kXBAR1_InputIomuxXbarIn42 = 42|0x10000U, /**< IOMUX_XBAR_IN42 output assigned to XBAR1_IN42 input. */ + kXBAR1_InputIomuxXbarIn43 = 43|0x10000U, /**< IOMUX_XBAR_IN43 output assigned to XBAR1_IN43 input. */ + kXBAR1_InputIomuxXbarIn44 = 44|0x10000U, /**< IOMUX_XBAR_IN44 output assigned to XBAR1_IN44 input. */ + kXBAR1_InputIomuxXbarIn45 = 45|0x10000U, /**< IOMUX_XBAR_IN45 output assigned to XBAR1_IN45 input. */ + kXBAR1_InputIomuxXbarIn46 = 46|0x10000U, /**< IOMUX_XBAR_IN46 output assigned to XBAR1_IN46 input. */ + kXBAR1_InputIomuxXbarIn47 = 47|0x10000U, /**< IOMUX_XBAR_IN47 output assigned to XBAR1_IN47 input. */ + kXBAR1_InputIomuxXbarIn48 = 48|0x10000U, /**< IOMUX_XBAR_IN48 output assigned to XBAR1_IN48 input. */ + kXBAR1_InputQtimer1Timer0 = 49|0x10000U, /**< QTIMER1_TIMER0 output assigned to XBAR1_IN49 input. */ + kXBAR1_InputQtimer1Timer1 = 50|0x10000U, /**< QTIMER1_TIMER1 output assigned to XBAR1_IN50 input. */ + kXBAR1_InputQtimer1Timer2 = 51|0x10000U, /**< QTIMER1_TIMER2 output assigned to XBAR1_IN51 input. */ + kXBAR1_InputQtimer1Timer3 = 52|0x10000U, /**< QTIMER1_TIMER3 output assigned to XBAR1_IN52 input. */ + kXBAR1_InputQtimer2Timer0 = 53|0x10000U, /**< QTIMER2_TIMER0 output assigned to XBAR1_IN53 input. */ + kXBAR1_InputQtimer2Timer1 = 54|0x10000U, /**< QTIMER2_TIMER1 output assigned to XBAR1_IN54 input. */ + kXBAR1_InputQtimer2Timer2 = 55|0x10000U, /**< QTIMER2_TIMER2 output assigned to XBAR1_IN55 input. */ + kXBAR1_InputQtimer2Timer3 = 56|0x10000U, /**< QTIMER2_TIMER3 output assigned to XBAR1_IN56 input. */ + kXBAR1_InputQtimer3Timer0 = 57|0x10000U, /**< QTIMER3_TIMER0 output assigned to XBAR1_IN57 input. */ + kXBAR1_InputQtimer3Timer1 = 58|0x10000U, /**< QTIMER3_TIMER1 output assigned to XBAR1_IN58 input. */ + kXBAR1_InputQtimer3Timer2 = 59|0x10000U, /**< QTIMER3_TIMER2 output assigned to XBAR1_IN59 input. */ + kXBAR1_InputQtimer3Timer3 = 60|0x10000U, /**< QTIMER3_TIMER3 output assigned to XBAR1_IN60 input. */ + kXBAR1_InputQtimer4Timer0 = 61|0x10000U, /**< QTIMER4_TIMER0 output assigned to XBAR1_IN61 input. */ + kXBAR1_InputQtimer4Timer1 = 62|0x10000U, /**< QTIMER4_TIMER1 output assigned to XBAR1_IN62 input. */ + kXBAR1_InputQtimer4Timer2 = 63|0x10000U, /**< QTIMER4_TIMER2 output assigned to XBAR1_IN63 input. */ + kXBAR1_InputQtimer4Timer3 = 64|0x10000U, /**< QTIMER4_TIMER3 output assigned to XBAR1_IN64 input. */ + kXBAR1_InputQtimer5Timer0 = 65|0x10000U, /**< QTIMER5_TIMER0 output assigned to XBAR1_IN65 input. */ + kXBAR1_InputQtimer5Timer1 = 66|0x10000U, /**< QTIMER5_TIMER1 output assigned to XBAR1_IN66 input. */ + kXBAR1_InputQtimer5Timer2 = 67|0x10000U, /**< QTIMER5_TIMER2 output assigned to XBAR1_IN67 input. */ + kXBAR1_InputQtimer5Timer3 = 68|0x10000U, /**< QTIMER5_TIMER3 output assigned to XBAR1_IN68 input. */ + kXBAR1_InputQtimer6Timer0 = 69|0x10000U, /**< QTIMER6_TIMER0 output assigned to XBAR1_IN69 input. */ + kXBAR1_InputQtimer6Timer1 = 70|0x10000U, /**< QTIMER6_TIMER1 output assigned to XBAR1_IN70 input. */ + kXBAR1_InputQtimer6Timer2 = 71|0x10000U, /**< QTIMER6_TIMER2 output assigned to XBAR1_IN71 input. */ + kXBAR1_InputQtimer6Timer3 = 72|0x10000U, /**< QTIMER6_TIMER3 output assigned to XBAR1_IN72 input. */ + kXBAR1_InputQtimer7Timer0 = 73|0x10000U, /**< QTIMER7_TIMER0 output assigned to XBAR1_IN73 input. */ + kXBAR1_InputQtimer7Timer1 = 74|0x10000U, /**< QTIMER7_TIMER1 output assigned to XBAR1_IN74 input. */ + kXBAR1_InputQtimer7Timer2 = 75|0x10000U, /**< QTIMER7_TIMER2 output assigned to XBAR1_IN75 input. */ + kXBAR1_InputQtimer7Timer3 = 76|0x10000U, /**< QTIMER7_TIMER3 output assigned to XBAR1_IN76 input. */ + kXBAR1_InputQtimer8Timer0 = 77|0x10000U, /**< QTIMER8_TIMER0 output assigned to XBAR1_IN77 input. */ + kXBAR1_InputQtimer8Timer1 = 78|0x10000U, /**< QTIMER8_TIMER1 output assigned to XBAR1_IN78 input. */ + kXBAR1_InputQtimer8Timer2 = 79|0x10000U, /**< QTIMER8_TIMER2 output assigned to XBAR1_IN79 input. */ + kXBAR1_InputQtimer8Timer3 = 80|0x10000U, /**< QTIMER8_TIMER3 output assigned to XBAR1_IN80 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger0 = 81|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR1_IN81 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger0 = 82|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER0 output assigned to XBAR1_IN82 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger1 = 83|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR1_IN83 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger1 = 84|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER1 output assigned to XBAR1_IN84 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger2 = 85|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR1_IN85 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger2 = 86|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER2 output assigned to XBAR1_IN86 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger3 = 87|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR1_IN87 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger3 = 88|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER3 output assigned to XBAR1_IN88 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger0 = 89|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR1_IN89 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger0 = 90|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER0 output assigned to XBAR1_IN90 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger1 = 91|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR1_IN91 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger1 = 92|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER1 output assigned to XBAR1_IN92 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger2 = 93|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR1_IN93 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger2 = 94|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER2 output assigned to XBAR1_IN94 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger3 = 95|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR1_IN95 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger3 = 96|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER3 output assigned to XBAR1_IN96 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger0 = 97|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR1_IN97 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger0 = 98|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER0 output assigned to XBAR1_IN98 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger1 = 99|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR1_IN99 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger1 = 100|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER1 output assigned to XBAR1_IN100 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger2 = 101|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR1_IN101 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger2 = 102|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER2 output assigned to XBAR1_IN102 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger3 = 103|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR1_IN103 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger3 = 104|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER3 output assigned to XBAR1_IN104 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger0 = 105|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR1_IN105 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger0 = 106|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER0 output assigned to XBAR1_IN106 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger1 = 107|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR1_IN107 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger1 = 108|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER1 output assigned to XBAR1_IN108 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger2 = 109|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR1_IN109 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger2 = 110|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER2 output assigned to XBAR1_IN110 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger3 = 111|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR1_IN111 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger3 = 112|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER3 output assigned to XBAR1_IN112 input. */ + kXBAR1_InputLpit1LpitTrigOut0 = 113|0x10000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR1_IN113 input. */ + kXBAR1_InputLpit1LpitTrigOut1 = 114|0x10000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR1_IN114 input. */ + kXBAR1_InputLpit1LpitTrigOut2 = 115|0x10000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR1_IN115 input. */ + kXBAR1_InputLpit1LpitTrigOut3 = 116|0x10000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR1_IN116 input. */ + kXBAR1_InputLpit2LpitTrigOut0 = 117|0x10000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR1_IN117 input. */ + kXBAR1_InputLpit2LpitTrigOut1 = 118|0x10000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR1_IN118 input. */ + kXBAR1_InputLpit2LpitTrigOut2 = 119|0x10000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR1_IN119 input. */ + kXBAR1_InputLpit2LpitTrigOut3 = 120|0x10000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR1_IN120 input. */ + kXBAR1_InputLpit3LpitTrigOut0 = 121|0x10000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR1_IN121 input. */ + kXBAR1_InputLpit3LpitTrigOut1 = 122|0x10000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR1_IN122 input. */ + kXBAR1_InputLpit3LpitTrigOut2 = 123|0x10000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR1_IN123 input. */ + kXBAR1_InputLpit3LpitTrigOut3 = 124|0x10000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR1_IN124 input. */ + kXBAR1_InputTriggerSyncSyncOut0 = 125|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT0 output assigned to XBAR1_IN125 input. */ + kXBAR1_InputTriggerSyncSyncOut1 = 126|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT1 output assigned to XBAR1_IN126 input. */ + kXBAR1_InputTriggerSyncSyncOut2 = 127|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT2 output assigned to XBAR1_IN127 input. */ + kXBAR1_InputTriggerSyncSyncOut3 = 128|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT3 output assigned to XBAR1_IN128 input. */ + kXBAR1_InputEdma2DmaTriggerOut0 = 129|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN129 input. */ + kXBAR1_InputEdma2DmaTriggerOut1 = 130|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN130 input. */ + kXBAR1_InputEdma2DmaTriggerOut2 = 131|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN131 input. */ + kXBAR1_InputEdma2DmaTriggerOut3 = 132|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN132 input. */ + kXBAR1_InputEdma2DmaTriggerOut4 = 133|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN133 input. */ + kXBAR1_InputEdma2DmaTriggerOut5 = 134|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN134 input. */ + kXBAR1_InputEdma2DmaTriggerOut6 = 135|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN135 input. */ + kXBAR1_InputEdma2DmaTriggerOut7 = 136|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN136 input. */ + kXBAR1_InputEdma1DmaTriggerOut0 = 137|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN137 input. */ + kXBAR1_InputEdma1DmaTriggerOut1 = 138|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN138 input. */ + kXBAR1_InputEdma1DmaTriggerOut2 = 139|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN139 input. */ + kXBAR1_InputEdma1DmaTriggerOut3 = 140|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN140 input. */ + kXBAR1_InputEdma1DmaTriggerOut4 = 141|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN141 input. */ + kXBAR1_InputEdma1DmaTriggerOut5 = 142|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN142 input. */ + kXBAR1_InputEdma1DmaTriggerOut6 = 143|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN143 input. */ + kXBAR1_InputEdma1DmaTriggerOut7 = 144|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN144 input. */ + kXBAR1_InputEdma3DmaTriggerOut0 = 145|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN145 input. */ + kXBAR1_InputEdma3DmaTriggerOut1 = 146|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN146 input. */ + kXBAR1_InputEdma3DmaTriggerOut2 = 147|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN147 input. */ + kXBAR1_InputEdma3DmaTriggerOut3 = 148|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN148 input. */ + kXBAR1_InputEdma3DmaTriggerOut4 = 149|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN149 input. */ + kXBAR1_InputEdma3DmaTriggerOut5 = 150|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN150 input. */ + kXBAR1_InputEdma3DmaTriggerOut6 = 151|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN151 input. */ + kXBAR1_InputEdma3DmaTriggerOut7 = 152|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN152 input. */ + kXBAR1_InputEdma4DmaTriggerOut0 = 153|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN153 input. */ + kXBAR1_InputEdma4DmaTriggerOut1 = 154|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN154 input. */ + kXBAR1_InputEdma4DmaTriggerOut2 = 155|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN155 input. */ + kXBAR1_InputEdma4DmaTriggerOut3 = 156|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN156 input. */ + kXBAR1_InputEdma4DmaTriggerOut4 = 157|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN157 input. */ + kXBAR1_InputEdma4DmaTriggerOut5 = 158|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN158 input. */ + kXBAR1_InputEdma4DmaTriggerOut6 = 159|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN159 input. */ + kXBAR1_InputEdma4DmaTriggerOut7 = 160|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN160 input. */ + kXBAR1_InputAdc1IpiIntEoc = 161|0x10000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR1_IN161 input. */ + kXBAR1_InputAdc1IpiIntWd = 162|0x10000U, /**< ADC1_IPI_INT_WD output assigned to XBAR1_IN162 input. */ + kXBAR1_InputTpm1LptpmChTrigger0 = 163|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN163 input. */ + kXBAR1_InputTpm1LptpmChTrigger1 = 164|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN164 input. */ + kXBAR1_InputTpm1LptpmChTrigger2 = 165|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN165 input. */ + kXBAR1_InputTpm1LptpmChTrigger3 = 166|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN166 input. */ + kXBAR1_InputTpm1LptpmTrigger = 167|0x10000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR1_IN167 input. */ + kXBAR1_InputTpm2LptpmChTrigger0 = 168|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN168 input. */ + kXBAR1_InputTpm2LptpmChTrigger1 = 169|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN169 input. */ + kXBAR1_InputTpm2LptpmChTrigger2 = 170|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN170 input. */ + kXBAR1_InputTpm2LptpmChTrigger3 = 171|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN171 input. */ + kXBAR1_InputTpm2LptpmTrigger = 172|0x10000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR1_IN172 input. */ + kXBAR1_InputTpm3LptpmChTrigger0 = 173|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN173 input. */ + kXBAR1_InputTpm3LptpmChTrigger1 = 174|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN174 input. */ + kXBAR1_InputTpm3LptpmChTrigger2 = 175|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN175 input. */ + kXBAR1_InputTpm3LptpmChTrigger3 = 176|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN176 input. */ + kXBAR1_InputTpm3LptpmTrigger = 177|0x10000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR1_IN177 input. */ + kXBAR1_InputTpm4LptpmChTrigger0 = 178|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN178 input. */ + kXBAR1_InputTpm4LptpmChTrigger1 = 179|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN179 input. */ + kXBAR1_InputTpm4LptpmChTrigger2 = 180|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN180 input. */ + kXBAR1_InputTpm4LptpmChTrigger3 = 181|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN181 input. */ + kXBAR1_InputTpm4LptpmTrigger = 182|0x10000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR1_IN182 input. */ + kXBAR1_InputTpm5LptpmChTrigger0 = 183|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN183 input. */ + kXBAR1_InputTpm5LptpmChTrigger1 = 184|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN184 input. */ + kXBAR1_InputTpm5LptpmChTrigger2 = 185|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN185 input. */ + kXBAR1_InputTpm5LptpmChTrigger3 = 186|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN186 input. */ + kXBAR1_InputTpm5LptpmTrigger = 187|0x10000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR1_IN187 input. */ + kXBAR1_InputTpm6LptpmChTrigger0 = 188|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN188 input. */ + kXBAR1_InputTpm6LptpmChTrigger1 = 189|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN189 input. */ + kXBAR1_InputTpm6LptpmChTrigger2 = 190|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN190 input. */ + kXBAR1_InputTpm6LptpmChTrigger3 = 191|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN191 input. */ + kXBAR1_InputTpm6LptpmTrigger = 192|0x10000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR1_IN192 input. */ + kXBAR1_InputLptmr1LptimerTriggerDelay = 193|0x10000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN193 input. */ + kXBAR1_InputLptmr2LptimerTriggerDelay = 194|0x10000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN194 input. */ + kXBAR1_InputLogicLow2 = 195|0x10000U, /**< LOGIC_LOW2 output assigned to XBAR1_IN195 input. */ + kXBAR1_InputNetcTmr11588Pp1 = 196|0x10000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR1_IN196 input. */ + kXBAR1_InputNetcTmr11588Pp2 = 197|0x10000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR1_IN197 input. */ + kXBAR1_InputNetcTmr11588Pp3 = 198|0x10000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR1_IN198 input. */ + kXBAR1_InputNetcTmr11588Alarm1 = 199|0x10000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR1_IN199 input. */ + kXBAR1_InputNetcTmr11588Alarm2 = 200|0x10000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR1_IN200 input. */ + kXBAR1_InputNetcTmr21588Pp1 = 201|0x10000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR1_IN201 input. */ + kXBAR1_InputNetcTmr21588Pp2 = 202|0x10000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR1_IN202 input. */ + kXBAR1_InputNetcTmr21588Pp3 = 203|0x10000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR1_IN203 input. */ + kXBAR1_InputNetcTmr21588Alarm1 = 204|0x10000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR1_IN204 input. */ + kXBAR1_InputNetcTmr21588Alarm2 = 205|0x10000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR1_IN205 input. */ + kXBAR1_InputNetcTmr31588Pp1 = 206|0x10000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR1_IN206 input. */ + kXBAR1_InputNetcTmr31588Pp2 = 207|0x10000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR1_IN207 input. */ + kXBAR1_InputNetcTmr31588Pp3 = 208|0x10000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR1_IN208 input. */ + kXBAR1_InputNetcTmr31588Alarm1 = 209|0x10000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR1_IN209 input. */ + kXBAR1_InputNetcTmr31588Alarm2 = 210|0x10000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR1_IN210 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak0 = 211|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR1_IN211 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak1 = 212|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR1_IN212 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak2 = 213|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR1_IN213 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak3 = 214|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR1_IN214 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak0 = 215|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR1_IN215 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak1 = 216|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR1_IN216 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak2 = 217|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR1_IN217 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak3 = 218|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR1_IN218 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak0 = 219|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR1_IN219 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak1 = 220|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR1_IN220 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak2 = 221|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR1_IN221 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak3 = 222|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR1_IN222 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak0 = 223|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR1_IN223 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak1 = 224|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR1_IN224 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak2 = 225|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR1_IN225 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak3 = 226|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR1_IN226 input. */ + kXBAR1_InputAoi1AoiOut0 = 227|0x10000U, /**< AOI1_AOI_OUT0 output assigned to XBAR1_IN227 input. */ + kXBAR1_InputAoi1AoiOut1 = 228|0x10000U, /**< AOI1_AOI_OUT1 output assigned to XBAR1_IN228 input. */ + kXBAR1_InputAoi1AoiOut2 = 229|0x10000U, /**< AOI1_AOI_OUT2 output assigned to XBAR1_IN229 input. */ + kXBAR1_InputAoi1AoiOut3 = 230|0x10000U, /**< AOI1_AOI_OUT3 output assigned to XBAR1_IN230 input. */ + kXBAR1_InputAoi2AoiOut0 = 231|0x10000U, /**< AOI2_AOI_OUT0 output assigned to XBAR1_IN231 input. */ + kXBAR1_InputAoi2AoiOut1 = 232|0x10000U, /**< AOI2_AOI_OUT1 output assigned to XBAR1_IN232 input. */ + kXBAR1_InputAoi2AoiOut2 = 233|0x10000U, /**< AOI2_AOI_OUT2 output assigned to XBAR1_IN233 input. */ + kXBAR1_InputAoi2AoiOut3 = 234|0x10000U, /**< AOI2_AOI_OUT3 output assigned to XBAR1_IN234 input. */ + kXBAR1_InputTriggerSyncSyncOut4 = 235|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT4 output assigned to XBAR1_IN235 input. */ + kXBAR1_InputTriggerSyncSyncOut5 = 236|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT5 output assigned to XBAR1_IN236 input. */ + kXBAR1_InputTriggerSyncSyncOut6 = 237|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT6 output assigned to XBAR1_IN237 input. */ + kXBAR1_InputTriggerSyncSyncOut7 = 238|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT7 output assigned to XBAR1_IN238 input. */ + kXBAR1_InputAoi3AoiOut0 = 239|0x10000U, /**< AOI3_AOI_OUT0 output assigned to XBAR1_IN239 input. */ + kXBAR1_InputAoi3AoiOut1 = 240|0x10000U, /**< AOI3_AOI_OUT1 output assigned to XBAR1_IN240 input. */ + kXBAR1_InputAoi3AoiOut2 = 241|0x10000U, /**< AOI3_AOI_OUT2 output assigned to XBAR1_IN241 input. */ + kXBAR1_InputAoi3AoiOut3 = 242|0x10000U, /**< AOI3_AOI_OUT3 output assigned to XBAR1_IN242 input. */ + kXBAR1_InputAoi4AoiOut0 = 243|0x10000U, /**< AOI4_AOI_OUT0 output assigned to XBAR1_IN243 input. */ + kXBAR1_InputAoi4AoiOut1 = 244|0x10000U, /**< AOI4_AOI_OUT1 output assigned to XBAR1_IN244 input. */ + kXBAR1_InputAoi4AoiOut2 = 245|0x10000U, /**< AOI4_AOI_OUT2 output assigned to XBAR1_IN245 input. */ + kXBAR1_InputAoi4AoiOut3 = 246|0x10000U, /**< AOI4_AOI_OUT3 output assigned to XBAR1_IN246 input. */ + kXBAR1_InputEcatSyncOut0 = 247|0x10000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR1_IN247 input. */ + kXBAR1_InputEcatSyncOut1 = 248|0x10000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR1_IN248 input. */ + kXBAR1_InputFccuVfccuReactionsOut11 = 249|0x10000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR1_IN249 input. */ + kXBAR1_InputGpt1IppDoCmpout1 = 250|0x10000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR1_IN250 input. */ + kXBAR1_InputGpt1IppDoCmpout2 = 251|0x10000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR1_IN251 input. */ + kXBAR1_InputGpt1IppDoCmpout3 = 252|0x10000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR1_IN252 input. */ + kXBAR1_InputGpt2IppDoCmpout1 = 253|0x10000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR1_IN253 input. */ + kXBAR1_InputGpt2IppDoCmpout2 = 254|0x10000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR1_IN254 input. */ + kXBAR1_InputGpt2IppDoCmpout3 = 255|0x10000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR1_IN255 input. */ + kXBAR1_InputGpt3IppDoCmpout1 = 256|0x10000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR1_IN256 input. */ + kXBAR1_InputGpt3IppDoCmpout2 = 257|0x10000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR1_IN257 input. */ + kXBAR1_InputGpt3IppDoCmpout3 = 258|0x10000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR1_IN258 input. */ + kXBAR1_InputGpt4IppDoCmpout1 = 259|0x10000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR1_IN259 input. */ + kXBAR1_InputGpt4IppDoCmpout2 = 260|0x10000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR1_IN260 input. */ + kXBAR1_InputGpt4IppDoCmpout3 = 261|0x10000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR1_IN261 input. */ + kXBAR1_InputFlexio1FlexioTriggerOut0 = 262|0x10000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN262 input. */ + kXBAR1_InputFlexio2FlexioTriggerOut0 = 263|0x10000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN263 input. */ + kXBAR1_InputFlexio3FlexioTriggerOut0 = 264|0x10000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN264 input. */ + kXBAR1_InputFlexio4FlexioTriggerOut0 = 265|0x10000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN265 input. */ + kXBAR1_InputGpio1IpiIntRgpio0 = 266|0x10000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR1_IN266 input. */ + kXBAR1_InputGpio2IpiIntRgpio0 = 267|0x10000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR1_IN267 input. */ + kXBAR1_InputGpio3IpiIntRgpio0 = 268|0x10000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR1_IN268 input. */ + kXBAR1_InputGpio4IpiIntRgpio0 = 269|0x10000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR1_IN269 input. */ + kXBAR1_InputGpio5IpiIntRgpio0 = 270|0x10000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR1_IN270 input. */ + kXBAR1_InputGpio6IpiIntRgpio0 = 271|0x10000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR1_IN271 input. */ + kXBAR1_InputGpio7IpiIntRgpio0 = 272|0x10000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR1_IN272 input. */ + kXBAR1_InputCm33Txev = 273|0x10000U, /**< CM33_TXEV output assigned to XBAR1_IN273 input. */ + kXBAR1_InputCm33SyncTxev = 274|0x10000U, /**< CM33_SYNC_TXEV output assigned to XBAR1_IN274 input. */ + kXBAR1_InputEndat21SiN = 275|0x10000U, /**< ENDAT2_1_SI_N output assigned to XBAR1_IN275 input. */ + kXBAR1_InputEndat21TimerN = 276|0x10000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR1_IN276 input. */ + kXBAR1_InputEndat22SiN = 277|0x10000U, /**< ENDAT2_2_SI_N output assigned to XBAR1_IN277 input. */ + kXBAR1_InputEndat22TimerN = 278|0x10000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR1_IN278 input. */ + kXBAR1_InputBissEot = 279|0x10000U, /**< BISS_EOT output assigned to XBAR1_IN279 input. */ + kXBAR1_InputTriggerSyncSyncOut8 = 280|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT8 output assigned to XBAR1_IN280 input. */ + kXBAR1_InputTriggerSyncSyncOut9 = 281|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT9 output assigned to XBAR1_IN281 input. */ + kXBAR1_InputTriggerSyncSyncOut10 = 282|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT10 output assigned to XBAR1_IN282 input. */ + kXBAR1_InputTriggerSyncSyncOut11 = 283|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT11 output assigned to XBAR1_IN283 input. */ + kXBAR1_InputTriggerSyncSyncOut12 = 284|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT12 output assigned to XBAR1_IN284 input. */ + kXBAR1_InputTriggerSyncSyncOut13 = 285|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT13 output assigned to XBAR1_IN285 input. */ + kXBAR1_InputTriggerSyncSyncOut14 = 286|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT14 output assigned to XBAR1_IN286 input. */ + kXBAR1_InputTriggerSyncSyncOut15 = 287|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT15 output assigned to XBAR1_IN287 input. */ + kXBAR1_InputEcatResetOut = 288|0x10000U, /**< ECAT_RESET_OUT output assigned to XBAR1_IN288 input. */ + kXBAR1_InputHiperface1FastPosRcvdEvt = 289|0x10000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR1_IN289 input. */ + kXBAR1_InputHiperface2FastPosRcvdEvt = 290|0x10000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR1_IN290 input. */ + kXBAR2_InputLogicLow = 0|0x20000U, /**< LOGIC_LOW output assigned to XBAR2_IN0 input. */ + kXBAR2_InputLogicHigh = 1|0x20000U, /**< LOGIC_HIGH output assigned to XBAR2_IN1 input. */ + kXBAR2_InputLogicLow1 = 2|0x20000U, /**< LOGIC_LOW1 output assigned to XBAR2_IN2 input. */ + kXBAR2_InputLogicHigh1 = 3|0x20000U, /**< LOGIC_HIGH1 output assigned to XBAR2_IN3 input. */ + kXBAR2_InputQtimer1Timer0 = 4|0x20000U, /**< QTIMER1_TIMER0 output assigned to XBAR2_IN4 input. */ + kXBAR2_InputQtimer1Timer1 = 5|0x20000U, /**< QTIMER1_TIMER1 output assigned to XBAR2_IN5 input. */ + kXBAR2_InputQtimer1Timer2 = 6|0x20000U, /**< QTIMER1_TIMER2 output assigned to XBAR2_IN6 input. */ + kXBAR2_InputQtimer1Timer3 = 7|0x20000U, /**< QTIMER1_TIMER3 output assigned to XBAR2_IN7 input. */ + kXBAR2_InputQtimer2Timer0 = 8|0x20000U, /**< QTIMER2_TIMER0 output assigned to XBAR2_IN8 input. */ + kXBAR2_InputQtimer2Timer1 = 9|0x20000U, /**< QTIMER2_TIMER1 output assigned to XBAR2_IN9 input. */ + kXBAR2_InputQtimer2Timer2 = 10|0x20000U, /**< QTIMER2_TIMER2 output assigned to XBAR2_IN10 input. */ + kXBAR2_InputQtimer2Timer3 = 11|0x20000U, /**< QTIMER2_TIMER3 output assigned to XBAR2_IN11 input. */ + kXBAR2_InputQtimer3Timer0 = 12|0x20000U, /**< QTIMER3_TIMER0 output assigned to XBAR2_IN12 input. */ + kXBAR2_InputQtimer3Timer1 = 13|0x20000U, /**< QTIMER3_TIMER1 output assigned to XBAR2_IN13 input. */ + kXBAR2_InputQtimer3Timer2 = 14|0x20000U, /**< QTIMER3_TIMER2 output assigned to XBAR2_IN14 input. */ + kXBAR2_InputQtimer3Timer3 = 15|0x20000U, /**< QTIMER3_TIMER3 output assigned to XBAR2_IN15 input. */ + kXBAR2_InputQtimer4Timer0 = 16|0x20000U, /**< QTIMER4_TIMER0 output assigned to XBAR2_IN16 input. */ + kXBAR2_InputQtimer4Timer1 = 17|0x20000U, /**< QTIMER4_TIMER1 output assigned to XBAR2_IN17 input. */ + kXBAR2_InputQtimer4Timer2 = 18|0x20000U, /**< QTIMER4_TIMER2 output assigned to XBAR2_IN18 input. */ + kXBAR2_InputQtimer4Timer3 = 19|0x20000U, /**< QTIMER4_TIMER3 output assigned to XBAR2_IN19 input. */ + kXBAR2_InputQtimer5Timer0 = 20|0x20000U, /**< QTIMER5_TIMER0 output assigned to XBAR2_IN20 input. */ + kXBAR2_InputQtimer5Timer1 = 21|0x20000U, /**< QTIMER5_TIMER1 output assigned to XBAR2_IN21 input. */ + kXBAR2_InputQtimer5Timer2 = 22|0x20000U, /**< QTIMER5_TIMER2 output assigned to XBAR2_IN22 input. */ + kXBAR2_InputQtimer5Timer3 = 23|0x20000U, /**< QTIMER5_TIMER3 output assigned to XBAR2_IN23 input. */ + kXBAR2_InputQtimer6Timer0 = 24|0x20000U, /**< QTIMER6_TIMER0 output assigned to XBAR2_IN24 input. */ + kXBAR2_InputQtimer6Timer1 = 25|0x20000U, /**< QTIMER6_TIMER1 output assigned to XBAR2_IN25 input. */ + kXBAR2_InputQtimer6Timer2 = 26|0x20000U, /**< QTIMER6_TIMER2 output assigned to XBAR2_IN26 input. */ + kXBAR2_InputQtimer6Timer3 = 27|0x20000U, /**< QTIMER6_TIMER3 output assigned to XBAR2_IN27 input. */ + kXBAR2_InputQtimer7Timer0 = 28|0x20000U, /**< QTIMER7_TIMER0 output assigned to XBAR2_IN28 input. */ + kXBAR2_InputQtimer7Timer1 = 29|0x20000U, /**< QTIMER7_TIMER1 output assigned to XBAR2_IN29 input. */ + kXBAR2_InputQtimer7Timer2 = 30|0x20000U, /**< QTIMER7_TIMER2 output assigned to XBAR2_IN30 input. */ + kXBAR2_InputQtimer7Timer3 = 31|0x20000U, /**< QTIMER7_TIMER3 output assigned to XBAR2_IN31 input. */ + kXBAR2_InputQtimer8Timer0 = 32|0x20000U, /**< QTIMER8_TIMER0 output assigned to XBAR2_IN32 input. */ + kXBAR2_InputQtimer8Timer1 = 33|0x20000U, /**< QTIMER8_TIMER1 output assigned to XBAR2_IN33 input. */ + kXBAR2_InputQtimer8Timer2 = 34|0x20000U, /**< QTIMER8_TIMER2 output assigned to XBAR2_IN34 input. */ + kXBAR2_InputQtimer8Timer3 = 35|0x20000U, /**< QTIMER8_TIMER3 output assigned to XBAR2_IN35 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger0 = 36|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR2_IN36 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger1 = 37|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR2_IN37 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger2 = 38|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR2_IN38 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger3 = 39|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR2_IN39 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger0 = 40|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR2_IN40 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger1 = 41|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR2_IN41 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger2 = 42|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR2_IN42 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger3 = 43|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR2_IN43 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger0 = 44|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR2_IN44 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger1 = 45|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR2_IN45 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger2 = 46|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR2_IN46 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger3 = 47|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR2_IN47 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger0 = 48|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR2_IN48 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger1 = 49|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR2_IN49 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger2 = 50|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR2_IN50 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger3 = 51|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR2_IN51 input. */ + kXBAR2_InputLpit1LpitTrigOut0 = 52|0x20000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR2_IN52 input. */ + kXBAR2_InputLpit1LpitTrigOut1 = 53|0x20000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR2_IN53 input. */ + kXBAR2_InputLpit1LpitTrigOut2 = 54|0x20000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR2_IN54 input. */ + kXBAR2_InputLpit1LpitTrigOut3 = 55|0x20000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR2_IN55 input. */ + kXBAR2_InputLpit2LpitTrigOut0 = 56|0x20000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR2_IN56 input. */ + kXBAR2_InputLpit2LpitTrigOut1 = 57|0x20000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR2_IN57 input. */ + kXBAR2_InputLpit2LpitTrigOut2 = 58|0x20000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR2_IN58 input. */ + kXBAR2_InputLpit2LpitTrigOut3 = 59|0x20000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR2_IN59 input. */ + kXBAR2_InputLpit3LpitTrigOut0 = 60|0x20000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR2_IN60 input. */ + kXBAR2_InputLpit3LpitTrigOut1 = 61|0x20000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR2_IN61 input. */ + kXBAR2_InputLpit3LpitTrigOut2 = 62|0x20000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR2_IN62 input. */ + kXBAR2_InputLpit3LpitTrigOut3 = 63|0x20000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR2_IN63 input. */ + kXBAR2_InputEdma2DmaTriggerOut0 = 64|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN64 input. */ + kXBAR2_InputEdma2DmaTriggerOut1 = 65|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN65 input. */ + kXBAR2_InputEdma2DmaTriggerOut2 = 66|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN66 input. */ + kXBAR2_InputEdma2DmaTriggerOut3 = 67|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN67 input. */ + kXBAR2_InputEdma2DmaTriggerOut4 = 68|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN68 input. */ + kXBAR2_InputEdma2DmaTriggerOut5 = 69|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN69 input. */ + kXBAR2_InputEdma2DmaTriggerOut6 = 70|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN70 input. */ + kXBAR2_InputEdma2DmaTriggerOut7 = 71|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN71 input. */ + kXBAR2_InputEdma1DmaTriggerOut0 = 72|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN72 input. */ + kXBAR2_InputEdma1DmaTriggerOut1 = 73|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN73 input. */ + kXBAR2_InputEdma1DmaTriggerOut2 = 74|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN74 input. */ + kXBAR2_InputEdma1DmaTriggerOut3 = 75|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN75 input. */ + kXBAR2_InputEdma1DmaTriggerOut4 = 76|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN76 input. */ + kXBAR2_InputEdma1DmaTriggerOut5 = 77|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN77 input. */ + kXBAR2_InputEdma1DmaTriggerOut6 = 78|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN78 input. */ + kXBAR2_InputEdma1DmaTriggerOut7 = 79|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN79 input. */ + kXBAR2_InputEdma3DmaTriggerOut0 = 80|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN80 input. */ + kXBAR2_InputEdma3DmaTriggerOut1 = 81|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN81 input. */ + kXBAR2_InputEdma3DmaTriggerOut2 = 82|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN82 input. */ + kXBAR2_InputEdma3DmaTriggerOut3 = 83|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN83 input. */ + kXBAR2_InputEdma3DmaTriggerOut4 = 84|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN84 input. */ + kXBAR2_InputEdma3DmaTriggerOut5 = 85|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN85 input. */ + kXBAR2_InputEdma3DmaTriggerOut6 = 86|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN86 input. */ + kXBAR2_InputEdma3DmaTriggerOut7 = 87|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN87 input. */ + kXBAR2_InputEdma4DmaTriggerOut0 = 88|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN88 input. */ + kXBAR2_InputEdma4DmaTriggerOut1 = 89|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN89 input. */ + kXBAR2_InputEdma4DmaTriggerOut2 = 90|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN90 input. */ + kXBAR2_InputEdma4DmaTriggerOut3 = 91|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN91 input. */ + kXBAR2_InputEdma4DmaTriggerOut4 = 92|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN92 input. */ + kXBAR2_InputEdma4DmaTriggerOut5 = 93|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN93 input. */ + kXBAR2_InputEdma4DmaTriggerOut6 = 94|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN94 input. */ + kXBAR2_InputEdma4DmaTriggerOut7 = 95|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN95 input. */ + kXBAR2_InputAdc1IpiIntEoc = 96|0x20000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR2_IN96 input. */ + kXBAR2_InputAdc1IpiIntWd = 97|0x20000U, /**< ADC1_IPI_INT_WD output assigned to XBAR2_IN97 input. */ + kXBAR2_InputTpm1LptpmChTrigger0 = 98|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN98 input. */ + kXBAR2_InputTpm1LptpmChTrigger1 = 99|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN99 input. */ + kXBAR2_InputTpm1LptpmChTrigger2 = 100|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN100 input. */ + kXBAR2_InputTpm1LptpmChTrigger3 = 101|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN101 input. */ + kXBAR2_InputTpm1LptpmTrigger = 102|0x20000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR2_IN102 input. */ + kXBAR2_InputTpm2LptpmChTrigger0 = 103|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN103 input. */ + kXBAR2_InputTpm2LptpmChTrigger1 = 104|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN104 input. */ + kXBAR2_InputTpm2LptpmChTrigger2 = 105|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN105 input. */ + kXBAR2_InputTpm2LptpmChTrigger3 = 106|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN106 input. */ + kXBAR2_InputTpm2LptpmTrigger = 107|0x20000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR2_IN107 input. */ + kXBAR2_InputTpm3LptpmChTrigger0 = 108|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN108 input. */ + kXBAR2_InputTpm3LptpmChTrigger1 = 109|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN109 input. */ + kXBAR2_InputTpm3LptpmChTrigger2 = 110|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN110 input. */ + kXBAR2_InputTpm3LptpmChTrigger3 = 111|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN111 input. */ + kXBAR2_InputTpm3LptpmTrigger = 112|0x20000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR2_IN112 input. */ + kXBAR2_InputTpm4LptpmChTrigger0 = 113|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN113 input. */ + kXBAR2_InputTpm4LptpmChTrigger1 = 114|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN114 input. */ + kXBAR2_InputTpm4LptpmChTrigger2 = 115|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN115 input. */ + kXBAR2_InputTpm4LptpmChTrigger3 = 116|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN116 input. */ + kXBAR2_InputTpm4LptpmTrigger = 117|0x20000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR2_IN117 input. */ + kXBAR2_InputTpm5LptpmChTrigger0 = 118|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN118 input. */ + kXBAR2_InputTpm5LptpmChTrigger1 = 119|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN119 input. */ + kXBAR2_InputTpm5LptpmChTrigger2 = 120|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN120 input. */ + kXBAR2_InputTpm5LptpmChTrigger3 = 121|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN121 input. */ + kXBAR2_InputTpm5LptpmTrigger = 122|0x20000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR2_IN122 input. */ + kXBAR2_InputTpm6LptpmChTrigger0 = 123|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN123 input. */ + kXBAR2_InputTpm6LptpmChTrigger1 = 124|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN124 input. */ + kXBAR2_InputTpm6LptpmChTrigger2 = 125|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN125 input. */ + kXBAR2_InputTpm6LptpmChTrigger3 = 126|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN126 input. */ + kXBAR2_InputTpm6LptpmTrigger = 127|0x20000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR2_IN127 input. */ + kXBAR2_InputLptmr1LptimerTriggerDelay = 128|0x20000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN128 input. */ + kXBAR2_InputLptmr2LptimerTriggerDelay = 129|0x20000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN129 input. */ + kXBAR2_InputLogicLow2 = 130|0x20000U, /**< LOGIC_LOW2 output assigned to XBAR2_IN130 input. */ + kXBAR2_InputNetcTmr11588Pp1 = 131|0x20000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR2_IN131 input. */ + kXBAR2_InputNetcTmr11588Pp2 = 132|0x20000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR2_IN132 input. */ + kXBAR2_InputNetcTmr11588Pp3 = 133|0x20000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR2_IN133 input. */ + kXBAR2_InputNetcTmr11588Alarm1 = 134|0x20000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR2_IN134 input. */ + kXBAR2_InputNetcTmr11588Alarm2 = 135|0x20000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR2_IN135 input. */ + kXBAR2_InputNetcTmr21588Pp1 = 136|0x20000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR2_IN136 input. */ + kXBAR2_InputNetcTmr21588Pp2 = 137|0x20000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR2_IN137 input. */ + kXBAR2_InputNetcTmr21588Pp3 = 138|0x20000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR2_IN138 input. */ + kXBAR2_InputNetcTmr21588Alarm1 = 139|0x20000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR2_IN139 input. */ + kXBAR2_InputNetcTmr21588Alarm2 = 140|0x20000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR2_IN140 input. */ + kXBAR2_InputNetcTmr31588Pp1 = 141|0x20000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR2_IN141 input. */ + kXBAR2_InputNetcTmr31588Pp2 = 142|0x20000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR2_IN142 input. */ + kXBAR2_InputNetcTmr31588Pp3 = 143|0x20000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR2_IN143 input. */ + kXBAR2_InputNetcTmr31588Alarm1 = 144|0x20000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR2_IN144 input. */ + kXBAR2_InputNetcTmr31588Alarm2 = 145|0x20000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR2_IN145 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak0 = 146|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR2_IN146 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak1 = 147|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR2_IN147 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak2 = 148|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR2_IN148 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak3 = 149|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR2_IN149 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak0 = 150|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR2_IN150 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak1 = 151|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR2_IN151 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak2 = 152|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR2_IN152 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak3 = 153|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR2_IN153 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak0 = 154|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR2_IN154 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak1 = 155|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR2_IN155 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak2 = 156|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR2_IN156 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak3 = 157|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR2_IN157 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak0 = 158|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR2_IN158 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak1 = 159|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR2_IN159 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak2 = 160|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR2_IN160 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak3 = 161|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR2_IN161 input. */ + kXBAR2_InputSinc1PulseTrg0 = 162|0x20000U, /**< SINC1_PULSE_TRG0 output assigned to XBAR2_IN162 input. */ + kXBAR2_InputSinc1PulseTrg1 = 163|0x20000U, /**< SINC1_PULSE_TRG1 output assigned to XBAR2_IN163 input. */ + kXBAR2_InputSinc1PulseTrg2 = 164|0x20000U, /**< SINC1_PULSE_TRG2 output assigned to XBAR2_IN164 input. */ + kXBAR2_InputSinc1PulseTrg3 = 165|0x20000U, /**< SINC1_PULSE_TRG3 output assigned to XBAR2_IN165 input. */ + kXBAR2_InputSinc3PulseTrg0 = 166|0x20000U, /**< SINC3_PULSE_TRG0 output assigned to XBAR2_IN166 input. */ + kXBAR2_InputSinc3PulseTrg1 = 167|0x20000U, /**< SINC3_PULSE_TRG1 output assigned to XBAR2_IN167 input. */ + kXBAR2_InputSinc3PulseTrg2 = 168|0x20000U, /**< SINC3_PULSE_TRG2 output assigned to XBAR2_IN168 input. */ + kXBAR2_InputSinc3PulseTrg3 = 169|0x20000U, /**< SINC3_PULSE_TRG3 output assigned to XBAR2_IN169 input. */ + kXBAR2_InputEcatSyncOut0 = 170|0x20000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR2_IN170 input. */ + kXBAR2_InputEcatSyncOut1 = 171|0x20000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR2_IN171 input. */ + kXBAR2_InputFccuVfccuReactionsOut11 = 172|0x20000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR2_IN172 input. */ + kXBAR2_InputGpt1IppDoCmpout1 = 173|0x20000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR2_IN173 input. */ + kXBAR2_InputGpt1IppDoCmpout2 = 174|0x20000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR2_IN174 input. */ + kXBAR2_InputGpt1IppDoCmpout3 = 175|0x20000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR2_IN175 input. */ + kXBAR2_InputGpt2IppDoCmpout1 = 176|0x20000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR2_IN176 input. */ + kXBAR2_InputGpt2IppDoCmpout2 = 177|0x20000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR2_IN177 input. */ + kXBAR2_InputGpt2IppDoCmpout3 = 178|0x20000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR2_IN178 input. */ + kXBAR2_InputGpt3IppDoCmpout1 = 179|0x20000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR2_IN179 input. */ + kXBAR2_InputGpt3IppDoCmpout2 = 180|0x20000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR2_IN180 input. */ + kXBAR2_InputGpt3IppDoCmpout3 = 181|0x20000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR2_IN181 input. */ + kXBAR2_InputGpt4IppDoCmpout1 = 182|0x20000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR2_IN182 input. */ + kXBAR2_InputGpt4IppDoCmpout2 = 183|0x20000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR2_IN183 input. */ + kXBAR2_InputGpt4IppDoCmpout3 = 184|0x20000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR2_IN184 input. */ + kXBAR2_InputFlexio1FlexioTriggerOut0 = 185|0x20000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN185 input. */ + kXBAR2_InputFlexio2FlexioTriggerOut0 = 186|0x20000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN186 input. */ + kXBAR2_InputFlexio3FlexioTriggerOut0 = 187|0x20000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN187 input. */ + kXBAR2_InputFlexio4FlexioTriggerOut0 = 188|0x20000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN188 input. */ + kXBAR2_InputGpio1IpiIntRgpio0 = 189|0x20000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR2_IN189 input. */ + kXBAR2_InputGpio2IpiIntRgpio0 = 190|0x20000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR2_IN190 input. */ + kXBAR2_InputGpio3IpiIntRgpio0 = 191|0x20000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR2_IN191 input. */ + kXBAR2_InputGpio4IpiIntRgpio0 = 192|0x20000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR2_IN192 input. */ + kXBAR2_InputGpio5IpiIntRgpio0 = 193|0x20000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR2_IN193 input. */ + kXBAR2_InputGpio6IpiIntRgpio0 = 194|0x20000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR2_IN194 input. */ + kXBAR2_InputGpio7IpiIntRgpio0 = 195|0x20000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR2_IN195 input. */ + kXBAR2_InputCm33Txev = 196|0x20000U, /**< CM33_TXEV output assigned to XBAR2_IN196 input. */ + kXBAR2_InputCm33SyncTxev = 197|0x20000U, /**< CM33_SYNC_TXEV output assigned to XBAR2_IN197 input. */ + kXBAR2_InputEndat21SiN = 198|0x20000U, /**< ENDAT2_1_SI_N output assigned to XBAR2_IN198 input. */ + kXBAR2_InputEndat21TimerN = 199|0x20000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR2_IN199 input. */ + kXBAR2_InputEndat22SiN = 200|0x20000U, /**< ENDAT2_2_SI_N output assigned to XBAR2_IN200 input. */ + kXBAR2_InputEndat22TimerN = 201|0x20000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR2_IN201 input. */ + kXBAR2_InputBissEot = 202|0x20000U, /**< BISS_EOT output assigned to XBAR2_IN202 input. */ + kXBAR2_InputEnc1PosMatch0 = 203|0x20000U, /**< ENC1_POS_MATCH0 output assigned to XBAR2_IN203 input. */ + kXBAR2_InputEnc1PosMatch1 = 204|0x20000U, /**< ENC1_POS_MATCH1 output assigned to XBAR2_IN204 input. */ + kXBAR2_InputEnc1PosMatch2 = 205|0x20000U, /**< ENC1_POS_MATCH2 output assigned to XBAR2_IN205 input. */ + kXBAR2_InputEnc1PosMatch3 = 206|0x20000U, /**< ENC1_POS_MATCH3 output assigned to XBAR2_IN206 input. */ + kXBAR2_InputEnc1CompFlg0 = 207|0x20000U, /**< ENC1_COMP_FLG0 output assigned to XBAR2_IN207 input. */ + kXBAR2_InputEnc1CompFlg1 = 208|0x20000U, /**< ENC1_COMP_FLG1 output assigned to XBAR2_IN208 input. */ + kXBAR2_InputEnc1CompFlg2 = 209|0x20000U, /**< ENC1_COMP_FLG2 output assigned to XBAR2_IN209 input. */ + kXBAR2_InputEnc1CompFlg3 = 210|0x20000U, /**< ENC1_COMP_FLG3 output assigned to XBAR2_IN210 input. */ + kXBAR2_InputEnc1CntDn = 211|0x20000U, /**< ENC1_CNT_DN output assigned to XBAR2_IN211 input. */ + kXBAR2_InputEnc1CntUp = 212|0x20000U, /**< ENC1_CNT_UP output assigned to XBAR2_IN212 input. */ + kXBAR2_InputEnc1Dir = 213|0x20000U, /**< ENC1_DIR output assigned to XBAR2_IN213 input. */ + kXBAR2_InputEnc3PosMatch0 = 214|0x20000U, /**< ENC3_POS_MATCH0 output assigned to XBAR2_IN214 input. */ + kXBAR2_InputEnc3PosMatch1 = 215|0x20000U, /**< ENC3_POS_MATCH1 output assigned to XBAR2_IN215 input. */ + kXBAR2_InputEnc3PosMatch2 = 216|0x20000U, /**< ENC3_POS_MATCH2 output assigned to XBAR2_IN216 input. */ + kXBAR2_InputEnc3PosMatch3 = 217|0x20000U, /**< ENC3_POS_MATCH3 output assigned to XBAR2_IN217 input. */ + kXBAR2_InputEnc3CompFlg0 = 218|0x20000U, /**< ENC3_COMP_FLG0 output assigned to XBAR2_IN218 input. */ + kXBAR2_InputEnc3CompFlg1 = 219|0x20000U, /**< ENC3_COMP_FLG1 output assigned to XBAR2_IN219 input. */ + kXBAR2_InputEnc3CompFlg2 = 220|0x20000U, /**< ENC3_COMP_FLG2 output assigned to XBAR2_IN220 input. */ + kXBAR2_InputEnc3CompFlg3 = 221|0x20000U, /**< ENC3_COMP_FLG3 output assigned to XBAR2_IN221 input. */ + kXBAR2_InputEnc3CntDn = 222|0x20000U, /**< ENC3_CNT_DN output assigned to XBAR2_IN222 input. */ + kXBAR2_InputEnc3CntUp = 223|0x20000U, /**< ENC3_CNT_UP output assigned to XBAR2_IN223 input. */ + kXBAR2_InputEnc3Dir = 224|0x20000U, /**< ENC3_DIR output assigned to XBAR2_IN224 input. */ + kXBAR2_InputHiperface1FastPosRcvdEvt = 225|0x20000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR2_IN225 input. */ + kXBAR2_InputHiperface2FastPosRcvdEvt = 226|0x20000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR2_IN226 input. */ + kXBAR3_InputLogicLow = 0|0x30000U, /**< LOGIC_LOW output assigned to XBAR3_IN0 input. */ + kXBAR3_InputLogicHigh = 1|0x30000U, /**< LOGIC_HIGH output assigned to XBAR3_IN1 input. */ + kXBAR3_InputLogicLow1 = 2|0x30000U, /**< LOGIC_LOW1 output assigned to XBAR3_IN2 input. */ + kXBAR3_InputLogicHigh1 = 3|0x30000U, /**< LOGIC_HIGH1 output assigned to XBAR3_IN3 input. */ + kXBAR3_InputQtimer1Timer0 = 4|0x30000U, /**< QTIMER1_TIMER0 output assigned to XBAR3_IN4 input. */ + kXBAR3_InputQtimer1Timer1 = 5|0x30000U, /**< QTIMER1_TIMER1 output assigned to XBAR3_IN5 input. */ + kXBAR3_InputQtimer1Timer2 = 6|0x30000U, /**< QTIMER1_TIMER2 output assigned to XBAR3_IN6 input. */ + kXBAR3_InputQtimer1Timer3 = 7|0x30000U, /**< QTIMER1_TIMER3 output assigned to XBAR3_IN7 input. */ + kXBAR3_InputQtimer2Timer0 = 8|0x30000U, /**< QTIMER2_TIMER0 output assigned to XBAR3_IN8 input. */ + kXBAR3_InputQtimer2Timer1 = 9|0x30000U, /**< QTIMER2_TIMER1 output assigned to XBAR3_IN9 input. */ + kXBAR3_InputQtimer2Timer2 = 10|0x30000U, /**< QTIMER2_TIMER2 output assigned to XBAR3_IN10 input. */ + kXBAR3_InputQtimer2Timer3 = 11|0x30000U, /**< QTIMER2_TIMER3 output assigned to XBAR3_IN11 input. */ + kXBAR3_InputQtimer3Timer0 = 12|0x30000U, /**< QTIMER3_TIMER0 output assigned to XBAR3_IN12 input. */ + kXBAR3_InputQtimer3Timer1 = 13|0x30000U, /**< QTIMER3_TIMER1 output assigned to XBAR3_IN13 input. */ + kXBAR3_InputQtimer3Timer2 = 14|0x30000U, /**< QTIMER3_TIMER2 output assigned to XBAR3_IN14 input. */ + kXBAR3_InputQtimer3Timer3 = 15|0x30000U, /**< QTIMER3_TIMER3 output assigned to XBAR3_IN15 input. */ + kXBAR3_InputQtimer4Timer0 = 16|0x30000U, /**< QTIMER4_TIMER0 output assigned to XBAR3_IN16 input. */ + kXBAR3_InputQtimer4Timer1 = 17|0x30000U, /**< QTIMER4_TIMER1 output assigned to XBAR3_IN17 input. */ + kXBAR3_InputQtimer4Timer2 = 18|0x30000U, /**< QTIMER4_TIMER2 output assigned to XBAR3_IN18 input. */ + kXBAR3_InputQtimer4Timer3 = 19|0x30000U, /**< QTIMER4_TIMER3 output assigned to XBAR3_IN19 input. */ + kXBAR3_InputQtimer5Timer0 = 20|0x30000U, /**< QTIMER5_TIMER0 output assigned to XBAR3_IN20 input. */ + kXBAR3_InputQtimer5Timer1 = 21|0x30000U, /**< QTIMER5_TIMER1 output assigned to XBAR3_IN21 input. */ + kXBAR3_InputQtimer5Timer2 = 22|0x30000U, /**< QTIMER5_TIMER2 output assigned to XBAR3_IN22 input. */ + kXBAR3_InputQtimer5Timer3 = 23|0x30000U, /**< QTIMER5_TIMER3 output assigned to XBAR3_IN23 input. */ + kXBAR3_InputQtimer6Timer0 = 24|0x30000U, /**< QTIMER6_TIMER0 output assigned to XBAR3_IN24 input. */ + kXBAR3_InputQtimer6Timer1 = 25|0x30000U, /**< QTIMER6_TIMER1 output assigned to XBAR3_IN25 input. */ + kXBAR3_InputQtimer6Timer2 = 26|0x30000U, /**< QTIMER6_TIMER2 output assigned to XBAR3_IN26 input. */ + kXBAR3_InputQtimer6Timer3 = 27|0x30000U, /**< QTIMER6_TIMER3 output assigned to XBAR3_IN27 input. */ + kXBAR3_InputQtimer7Timer0 = 28|0x30000U, /**< QTIMER7_TIMER0 output assigned to XBAR3_IN28 input. */ + kXBAR3_InputQtimer7Timer1 = 29|0x30000U, /**< QTIMER7_TIMER1 output assigned to XBAR3_IN29 input. */ + kXBAR3_InputQtimer7Timer2 = 30|0x30000U, /**< QTIMER7_TIMER2 output assigned to XBAR3_IN30 input. */ + kXBAR3_InputQtimer7Timer3 = 31|0x30000U, /**< QTIMER7_TIMER3 output assigned to XBAR3_IN31 input. */ + kXBAR3_InputQtimer8Timer0 = 32|0x30000U, /**< QTIMER8_TIMER0 output assigned to XBAR3_IN32 input. */ + kXBAR3_InputQtimer8Timer1 = 33|0x30000U, /**< QTIMER8_TIMER1 output assigned to XBAR3_IN33 input. */ + kXBAR3_InputQtimer8Timer2 = 34|0x30000U, /**< QTIMER8_TIMER2 output assigned to XBAR3_IN34 input. */ + kXBAR3_InputQtimer8Timer3 = 35|0x30000U, /**< QTIMER8_TIMER3 output assigned to XBAR3_IN35 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger0 = 36|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR3_IN36 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger1 = 37|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR3_IN37 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger2 = 38|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR3_IN38 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger3 = 39|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR3_IN39 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger0 = 40|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR3_IN40 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger1 = 41|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR3_IN41 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger2 = 42|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR3_IN42 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger3 = 43|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR3_IN43 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger0 = 44|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR3_IN44 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger1 = 45|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR3_IN45 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger2 = 46|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR3_IN46 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger3 = 47|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR3_IN47 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger0 = 48|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR3_IN48 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger1 = 49|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR3_IN49 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger2 = 50|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR3_IN50 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger3 = 51|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR3_IN51 input. */ + kXBAR3_InputLpit1LpitTrigOut0 = 52|0x30000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR3_IN52 input. */ + kXBAR3_InputLpit1LpitTrigOut1 = 53|0x30000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR3_IN53 input. */ + kXBAR3_InputLpit1LpitTrigOut2 = 54|0x30000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR3_IN54 input. */ + kXBAR3_InputLpit1LpitTrigOut3 = 55|0x30000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR3_IN55 input. */ + kXBAR3_InputLpit2LpitTrigOut0 = 56|0x30000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR3_IN56 input. */ + kXBAR3_InputLpit2LpitTrigOut1 = 57|0x30000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR3_IN57 input. */ + kXBAR3_InputLpit2LpitTrigOut2 = 58|0x30000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR3_IN58 input. */ + kXBAR3_InputLpit2LpitTrigOut3 = 59|0x30000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR3_IN59 input. */ + kXBAR3_InputLpit3LpitTrigOut0 = 60|0x30000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR3_IN60 input. */ + kXBAR3_InputLpit3LpitTrigOut1 = 61|0x30000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR3_IN61 input. */ + kXBAR3_InputLpit3LpitTrigOut2 = 62|0x30000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR3_IN62 input. */ + kXBAR3_InputLpit3LpitTrigOut3 = 63|0x30000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR3_IN63 input. */ + kXBAR3_InputEdma2DmaTriggerOut0 = 64|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN64 input. */ + kXBAR3_InputEdma2DmaTriggerOut1 = 65|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN65 input. */ + kXBAR3_InputEdma2DmaTriggerOut2 = 66|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN66 input. */ + kXBAR3_InputEdma2DmaTriggerOut3 = 67|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN67 input. */ + kXBAR3_InputEdma2DmaTriggerOut4 = 68|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN68 input. */ + kXBAR3_InputEdma2DmaTriggerOut5 = 69|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN69 input. */ + kXBAR3_InputEdma2DmaTriggerOut6 = 70|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN70 input. */ + kXBAR3_InputEdma2DmaTriggerOut7 = 71|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN71 input. */ + kXBAR3_InputEdma1DmaTriggerOut0 = 72|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN72 input. */ + kXBAR3_InputEdma1DmaTriggerOut1 = 73|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN73 input. */ + kXBAR3_InputEdma1DmaTriggerOut2 = 74|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN74 input. */ + kXBAR3_InputEdma1DmaTriggerOut3 = 75|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN75 input. */ + kXBAR3_InputEdma1DmaTriggerOut4 = 76|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN76 input. */ + kXBAR3_InputEdma1DmaTriggerOut5 = 77|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN77 input. */ + kXBAR3_InputEdma1DmaTriggerOut6 = 78|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN78 input. */ + kXBAR3_InputEdma1DmaTriggerOut7 = 79|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN79 input. */ + kXBAR3_InputEdma3DmaTriggerOut0 = 80|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN80 input. */ + kXBAR3_InputEdma3DmaTriggerOut1 = 81|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN81 input. */ + kXBAR3_InputEdma3DmaTriggerOut2 = 82|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN82 input. */ + kXBAR3_InputEdma3DmaTriggerOut3 = 83|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN83 input. */ + kXBAR3_InputEdma3DmaTriggerOut4 = 84|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN84 input. */ + kXBAR3_InputEdma3DmaTriggerOut5 = 85|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN85 input. */ + kXBAR3_InputEdma3DmaTriggerOut6 = 86|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN86 input. */ + kXBAR3_InputEdma3DmaTriggerOut7 = 87|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN87 input. */ + kXBAR3_InputEdma4DmaTriggerOut0 = 88|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN88 input. */ + kXBAR3_InputEdma4DmaTriggerOut1 = 89|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN89 input. */ + kXBAR3_InputEdma4DmaTriggerOut2 = 90|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN90 input. */ + kXBAR3_InputEdma4DmaTriggerOut3 = 91|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN91 input. */ + kXBAR3_InputEdma4DmaTriggerOut4 = 92|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN92 input. */ + kXBAR3_InputEdma4DmaTriggerOut5 = 93|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN93 input. */ + kXBAR3_InputEdma4DmaTriggerOut6 = 94|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN94 input. */ + kXBAR3_InputEdma4DmaTriggerOut7 = 95|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN95 input. */ + kXBAR3_InputAdc1IpiIntEoc = 96|0x30000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR3_IN96 input. */ + kXBAR3_InputAdc1IpiIntWd = 97|0x30000U, /**< ADC1_IPI_INT_WD output assigned to XBAR3_IN97 input. */ + kXBAR3_InputTpm1LptpmChTrigger0 = 98|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN98 input. */ + kXBAR3_InputTpm1LptpmChTrigger1 = 99|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN99 input. */ + kXBAR3_InputTpm1LptpmChTrigger2 = 100|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN100 input. */ + kXBAR3_InputTpm1LptpmChTrigger3 = 101|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN101 input. */ + kXBAR3_InputTpm1LptpmTrigger = 102|0x30000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR3_IN102 input. */ + kXBAR3_InputTpm2LptpmChTrigger0 = 103|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN103 input. */ + kXBAR3_InputTpm2LptpmChTrigger1 = 104|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN104 input. */ + kXBAR3_InputTpm2LptpmChTrigger2 = 105|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN105 input. */ + kXBAR3_InputTpm2LptpmChTrigger3 = 106|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN106 input. */ + kXBAR3_InputTpm2LptpmTrigger = 107|0x30000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR3_IN107 input. */ + kXBAR3_InputTpm3LptpmChTrigger0 = 108|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN108 input. */ + kXBAR3_InputTpm3LptpmChTrigger1 = 109|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN109 input. */ + kXBAR3_InputTpm3LptpmChTrigger2 = 110|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN110 input. */ + kXBAR3_InputTpm3LptpmChTrigger3 = 111|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN111 input. */ + kXBAR3_InputTpm3LptpmTrigger = 112|0x30000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR3_IN112 input. */ + kXBAR3_InputTpm4LptpmChTrigger0 = 113|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN113 input. */ + kXBAR3_InputTpm4LptpmChTrigger1 = 114|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN114 input. */ + kXBAR3_InputTpm4LptpmChTrigger2 = 115|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN115 input. */ + kXBAR3_InputTpm4LptpmChTrigger3 = 116|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN116 input. */ + kXBAR3_InputTpm4LptpmTrigger = 117|0x30000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR3_IN117 input. */ + kXBAR3_InputTpm5LptpmChTrigger0 = 118|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN118 input. */ + kXBAR3_InputTpm5LptpmChTrigger1 = 119|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN119 input. */ + kXBAR3_InputTpm5LptpmChTrigger2 = 120|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN120 input. */ + kXBAR3_InputTpm5LptpmChTrigger3 = 121|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN121 input. */ + kXBAR3_InputTpm5LptpmTrigger = 122|0x30000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR3_IN122 input. */ + kXBAR3_InputTpm6LptpmChTrigger0 = 123|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN123 input. */ + kXBAR3_InputTpm6LptpmChTrigger1 = 124|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN124 input. */ + kXBAR3_InputTpm6LptpmChTrigger2 = 125|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN125 input. */ + kXBAR3_InputTpm6LptpmChTrigger3 = 126|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN126 input. */ + kXBAR3_InputTpm6LptpmTrigger = 127|0x30000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR3_IN127 input. */ + kXBAR3_InputLptmr1LptimerTriggerDelay = 128|0x30000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN128 input. */ + kXBAR3_InputLptmr2LptimerTriggerDelay = 129|0x30000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN129 input. */ + kXBAR3_InputLogicLow2 = 130|0x30000U, /**< LOGIC_LOW2 output assigned to XBAR3_IN130 input. */ + kXBAR3_InputNetcTmr11588Pp1 = 131|0x30000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR3_IN131 input. */ + kXBAR3_InputNetcTmr11588Pp2 = 132|0x30000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR3_IN132 input. */ + kXBAR3_InputNetcTmr11588Pp3 = 133|0x30000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR3_IN133 input. */ + kXBAR3_InputNetcTmr11588Alarm1 = 134|0x30000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR3_IN134 input. */ + kXBAR3_InputNetcTmr11588Alarm2 = 135|0x30000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR3_IN135 input. */ + kXBAR3_InputNetcTmr21588Pp1 = 136|0x30000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR3_IN136 input. */ + kXBAR3_InputNetcTmr21588Pp2 = 137|0x30000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR3_IN137 input. */ + kXBAR3_InputNetcTmr21588Pp3 = 138|0x30000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR3_IN138 input. */ + kXBAR3_InputNetcTmr21588Alarm1 = 139|0x30000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR3_IN139 input. */ + kXBAR3_InputNetcTmr21588Alarm2 = 140|0x30000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR3_IN140 input. */ + kXBAR3_InputNetcTmr31588Pp1 = 141|0x30000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR3_IN141 input. */ + kXBAR3_InputNetcTmr31588Pp2 = 142|0x30000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR3_IN142 input. */ + kXBAR3_InputNetcTmr31588Pp3 = 143|0x30000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR3_IN143 input. */ + kXBAR3_InputNetcTmr31588Alarm1 = 144|0x30000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR3_IN144 input. */ + kXBAR3_InputNetcTmr31588Alarm2 = 145|0x30000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR3_IN145 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak0 = 146|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR3_IN146 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak1 = 147|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR3_IN147 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak2 = 148|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR3_IN148 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak3 = 149|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR3_IN149 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak0 = 150|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR3_IN150 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak1 = 151|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR3_IN151 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak2 = 152|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR3_IN152 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak3 = 153|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR3_IN153 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak0 = 154|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR3_IN154 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak1 = 155|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR3_IN155 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak2 = 156|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR3_IN156 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak3 = 157|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR3_IN157 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak0 = 158|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR3_IN158 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak1 = 159|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR3_IN159 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak2 = 160|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR3_IN160 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak3 = 161|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR3_IN161 input. */ + kXBAR3_InputSinc2PulseTrg0 = 162|0x30000U, /**< SINC2_PULSE_TRG0 output assigned to XBAR3_IN162 input. */ + kXBAR3_InputSinc2PulseTrg1 = 163|0x30000U, /**< SINC2_PULSE_TRG1 output assigned to XBAR3_IN163 input. */ + kXBAR3_InputSinc2PulseTrg2 = 164|0x30000U, /**< SINC2_PULSE_TRG2 output assigned to XBAR3_IN164 input. */ + kXBAR3_InputSinc2PulseTrg3 = 165|0x30000U, /**< SINC2_PULSE_TRG3 output assigned to XBAR3_IN165 input. */ + kXBAR3_InputSinc4PulseTrg0 = 166|0x30000U, /**< SINC4_PULSE_TRG0 output assigned to XBAR3_IN166 input. */ + kXBAR3_InputSinc4PulseTrg1 = 167|0x30000U, /**< SINC4_PULSE_TRG1 output assigned to XBAR3_IN167 input. */ + kXBAR3_InputSinc4PulseTrg2 = 168|0x30000U, /**< SINC4_PULSE_TRG2 output assigned to XBAR3_IN168 input. */ + kXBAR3_InputSinc4PulseTrg3 = 169|0x30000U, /**< SINC4_PULSE_TRG3 output assigned to XBAR3_IN169 input. */ + kXBAR3_InputEcatSyncOut0 = 170|0x30000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR3_IN170 input. */ + kXBAR3_InputEcatSyncOut1 = 171|0x30000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR3_IN171 input. */ + kXBAR3_InputFccuVfccuReactionsOut11 = 172|0x30000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR3_IN172 input. */ + kXBAR3_InputGpt1IppDoCmpout1 = 173|0x30000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR3_IN173 input. */ + kXBAR3_InputGpt1IppDoCmpout2 = 174|0x30000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR3_IN174 input. */ + kXBAR3_InputGpt1IppDoCmpout3 = 175|0x30000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR3_IN175 input. */ + kXBAR3_InputGpt2IppDoCmpout1 = 176|0x30000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR3_IN176 input. */ + kXBAR3_InputGpt2IppDoCmpout2 = 177|0x30000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR3_IN177 input. */ + kXBAR3_InputGpt2IppDoCmpout3 = 178|0x30000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR3_IN178 input. */ + kXBAR3_InputGpt3IppDoCmpout1 = 179|0x30000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR3_IN179 input. */ + kXBAR3_InputGpt3IppDoCmpout2 = 180|0x30000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR3_IN180 input. */ + kXBAR3_InputGpt3IppDoCmpout3 = 181|0x30000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR3_IN181 input. */ + kXBAR3_InputGpt4IppDoCmpout1 = 182|0x30000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR3_IN182 input. */ + kXBAR3_InputGpt4IppDoCmpout2 = 183|0x30000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR3_IN183 input. */ + kXBAR3_InputGpt4IppDoCmpout3 = 184|0x30000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR3_IN184 input. */ + kXBAR3_InputFlexio1FlexioTriggerOut0 = 185|0x30000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN185 input. */ + kXBAR3_InputFlexio2FlexioTriggerOut0 = 186|0x30000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN186 input. */ + kXBAR3_InputFlexio3FlexioTriggerOut0 = 187|0x30000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN187 input. */ + kXBAR3_InputFlexio4FlexioTriggerOut0 = 188|0x30000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN188 input. */ + kXBAR3_InputGpio1IpiIntRgpio0 = 189|0x30000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR3_IN189 input. */ + kXBAR3_InputGpio2IpiIntRgpio0 = 190|0x30000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR3_IN190 input. */ + kXBAR3_InputGpio3IpiIntRgpio0 = 191|0x30000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR3_IN191 input. */ + kXBAR3_InputGpio4IpiIntRgpio0 = 192|0x30000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR3_IN192 input. */ + kXBAR3_InputGpio5IpiIntRgpio0 = 193|0x30000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR3_IN193 input. */ + kXBAR3_InputGpio6IpiIntRgpio0 = 194|0x30000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR3_IN194 input. */ + kXBAR3_InputGpio7IpiIntRgpio0 = 195|0x30000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR3_IN195 input. */ + kXBAR3_InputCm33Txev = 196|0x30000U, /**< CM33_TXEV output assigned to XBAR3_IN196 input. */ + kXBAR3_InputCm33SyncTxev = 197|0x30000U, /**< CM33_SYNC_TXEV output assigned to XBAR3_IN197 input. */ + kXBAR3_InputEndat21SiN = 198|0x30000U, /**< ENDAT2_1_SI_N output assigned to XBAR3_IN198 input. */ + kXBAR3_InputEndat21TimerN = 199|0x30000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR3_IN199 input. */ + kXBAR3_InputEndat22SiN = 200|0x30000U, /**< ENDAT2_2_SI_N output assigned to XBAR3_IN200 input. */ + kXBAR3_InputEndat22TimerN = 201|0x30000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR3_IN201 input. */ + kXBAR3_InputBissEot = 202|0x30000U, /**< BISS_EOT output assigned to XBAR3_IN202 input. */ + kXBAR3_InputEnc2PosMatch0 = 203|0x30000U, /**< ENC2_POS_MATCH0 output assigned to XBAR3_IN203 input. */ + kXBAR3_InputEnc2PosMatch1 = 204|0x30000U, /**< ENC2_POS_MATCH1 output assigned to XBAR3_IN204 input. */ + kXBAR3_InputEnc2PosMatch2 = 205|0x30000U, /**< ENC2_POS_MATCH2 output assigned to XBAR3_IN205 input. */ + kXBAR3_InputEnc2PosMatch3 = 206|0x30000U, /**< ENC2_POS_MATCH3 output assigned to XBAR3_IN206 input. */ + kXBAR3_InputEnc2CompFlg0 = 207|0x30000U, /**< ENC2_COMP_FLG0 output assigned to XBAR3_IN207 input. */ + kXBAR3_InputEnc2CompFlg1 = 208|0x30000U, /**< ENC2_COMP_FLG1 output assigned to XBAR3_IN208 input. */ + kXBAR3_InputEnc2CompFlg2 = 209|0x30000U, /**< ENC2_COMP_FLG2 output assigned to XBAR3_IN209 input. */ + kXBAR3_InputEnc2CompFlg3 = 210|0x30000U, /**< ENC2_COMP_FLG3 output assigned to XBAR3_IN210 input. */ + kXBAR3_InputEnc2CntDn = 211|0x30000U, /**< ENC2_CNT_DN output assigned to XBAR3_IN211 input. */ + kXBAR3_InputEnc2CntUp = 212|0x30000U, /**< ENC2_CNT_UP output assigned to XBAR3_IN212 input. */ + kXBAR3_InputEnc2Dir = 213|0x30000U, /**< ENC2_DIR output assigned to XBAR3_IN213 input. */ + kXBAR3_InputEnc4PosMatch0 = 214|0x30000U, /**< ENC4_POS_MATCH0 output assigned to XBAR3_IN214 input. */ + kXBAR3_InputEnc4PosMatch1 = 215|0x30000U, /**< ENC4_POS_MATCH1 output assigned to XBAR3_IN215 input. */ + kXBAR3_InputEnc4PosMatch2 = 216|0x30000U, /**< ENC4_POS_MATCH2 output assigned to XBAR3_IN216 input. */ + kXBAR3_InputEnc4PosMatch3 = 217|0x30000U, /**< ENC4_POS_MATCH3 output assigned to XBAR3_IN217 input. */ + kXBAR3_InputEnc4CompFlg0 = 218|0x30000U, /**< ENC4_COMP_FLG0 output assigned to XBAR3_IN218 input. */ + kXBAR3_InputEnc4CompFlg1 = 219|0x30000U, /**< ENC4_COMP_FLG1 output assigned to XBAR3_IN219 input. */ + kXBAR3_InputEnc4CompFlg2 = 220|0x30000U, /**< ENC4_COMP_FLG2 output assigned to XBAR3_IN220 input. */ + kXBAR3_InputEnc4CompFlg3 = 221|0x30000U, /**< ENC4_COMP_FLG3 output assigned to XBAR3_IN221 input. */ + kXBAR3_InputEnc4CntDn = 222|0x30000U, /**< ENC4_CNT_DN output assigned to XBAR3_IN222 input. */ + kXBAR3_InputEnc4CntUp = 223|0x30000U, /**< ENC4_CNT_UP output assigned to XBAR3_IN223 input. */ + kXBAR3_InputEnc4Dir = 224|0x30000U, /**< ENC4_DIR output assigned to XBAR3_IN224 input. */ + kXBAR3_InputHiperface1FastPosRcvdEvt = 225|0x30000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR3_IN225 input. */ + kXBAR3_InputHiperface2FastPosRcvdEvt = 226|0x30000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR3_IN226 input. */ +} xbar_input_signal_t; + +typedef enum _xbar_output_signal +{ + kXBAR1_OutputEdma4IpdReq76 = 0|0x10000U, /**< XBAR1_OUT0 output assigned to EDMA4_IPD_REQ76 */ + kXBAR1_OutputEdma4IpdReq77 = 1|0x10000U, /**< XBAR1_OUT1 output assigned to EDMA4_IPD_REQ77 */ + kXBAR1_OutputEdma4IpdReq78 = 2|0x10000U, /**< XBAR1_OUT2 output assigned to EDMA4_IPD_REQ78 */ + kXBAR1_OutputEdma4IpdReq79 = 3|0x10000U, /**< XBAR1_OUT3 output assigned to EDMA4_IPD_REQ79 */ + kXBAR1_OutputIomuxXbarOut04 = 4|0x10000U, /**< XBAR1_OUT4 output assigned to IOMUX_XBAR_OUT04 */ + kXBAR1_OutputIomuxXbarOut05 = 5|0x10000U, /**< XBAR1_OUT5 output assigned to IOMUX_XBAR_OUT05 */ + kXBAR1_OutputIomuxXbarOut06 = 6|0x10000U, /**< XBAR1_OUT6 output assigned to IOMUX_XBAR_OUT06 */ + kXBAR1_OutputIomuxXbarOut07 = 7|0x10000U, /**< XBAR1_OUT7 output assigned to IOMUX_XBAR_OUT07 */ + kXBAR1_OutputIomuxXbarOut08 = 8|0x10000U, /**< XBAR1_OUT8 output assigned to IOMUX_XBAR_OUT08 */ + kXBAR1_OutputIomuxXbarOut09 = 9|0x10000U, /**< XBAR1_OUT9 output assigned to IOMUX_XBAR_OUT09 */ + kXBAR1_OutputIomuxXbarOut10 = 10|0x10000U, /**< XBAR1_OUT10 output assigned to IOMUX_XBAR_OUT10 */ + kXBAR1_OutputIomuxXbarOut11 = 11|0x10000U, /**< XBAR1_OUT11 output assigned to IOMUX_XBAR_OUT11 */ + kXBAR1_OutputIomuxXbarOut12 = 12|0x10000U, /**< XBAR1_OUT12 output assigned to IOMUX_XBAR_OUT12 */ + kXBAR1_OutputIomuxXbarOut13 = 13|0x10000U, /**< XBAR1_OUT13 output assigned to IOMUX_XBAR_OUT13 */ + kXBAR1_OutputIomuxXbarOut14 = 14|0x10000U, /**< XBAR1_OUT14 output assigned to IOMUX_XBAR_OUT14 */ + kXBAR1_OutputIomuxXbarOut15 = 15|0x10000U, /**< XBAR1_OUT15 output assigned to IOMUX_XBAR_OUT15 */ + kXBAR1_OutputIomuxXbarOut16 = 16|0x10000U, /**< XBAR1_OUT16 output assigned to IOMUX_XBAR_OUT16 */ + kXBAR1_OutputIomuxXbarOut17 = 17|0x10000U, /**< XBAR1_OUT17 output assigned to IOMUX_XBAR_OUT17 */ + kXBAR1_OutputIomuxXbarOut18 = 18|0x10000U, /**< XBAR1_OUT18 output assigned to IOMUX_XBAR_OUT18 */ + kXBAR1_OutputIomuxXbarOut19 = 19|0x10000U, /**< XBAR1_OUT19 output assigned to IOMUX_XBAR_OUT19 */ + kXBAR1_OutputIomuxXbarOut20 = 20|0x10000U, /**< XBAR1_OUT20 output assigned to IOMUX_XBAR_OUT20 */ + kXBAR1_OutputIomuxXbarOut21 = 21|0x10000U, /**< XBAR1_OUT21 output assigned to IOMUX_XBAR_OUT21 */ + kXBAR1_OutputIomuxXbarOut22 = 22|0x10000U, /**< XBAR1_OUT22 output assigned to IOMUX_XBAR_OUT22 */ + kXBAR1_OutputIomuxXbarOut23 = 23|0x10000U, /**< XBAR1_OUT23 output assigned to IOMUX_XBAR_OUT23 */ + kXBAR1_OutputIomuxXbarOut24 = 24|0x10000U, /**< XBAR1_OUT24 output assigned to IOMUX_XBAR_OUT24 */ + kXBAR1_OutputIomuxXbarOut25 = 25|0x10000U, /**< XBAR1_OUT25 output assigned to IOMUX_XBAR_OUT25 */ + kXBAR1_OutputIomuxXbarOut26 = 26|0x10000U, /**< XBAR1_OUT26 output assigned to IOMUX_XBAR_OUT26 */ + kXBAR1_OutputIomuxXbarOut27 = 27|0x10000U, /**< XBAR1_OUT27 output assigned to IOMUX_XBAR_OUT27 */ + kXBAR1_OutputIomuxXbarOut28 = 28|0x10000U, /**< XBAR1_OUT28 output assigned to IOMUX_XBAR_OUT28 */ + kXBAR1_OutputIomuxXbarOut29 = 29|0x10000U, /**< XBAR1_OUT29 output assigned to IOMUX_XBAR_OUT29 */ + kXBAR1_OutputIomuxXbarOut30 = 30|0x10000U, /**< XBAR1_OUT30 output assigned to IOMUX_XBAR_OUT30 */ + kXBAR1_OutputIomuxXbarOut31 = 31|0x10000U, /**< XBAR1_OUT31 output assigned to IOMUX_XBAR_OUT31 */ + kXBAR1_OutputIomuxXbarOut32 = 32|0x10000U, /**< XBAR1_OUT32 output assigned to IOMUX_XBAR_OUT32 */ + kXBAR1_OutputIomuxXbarOut33 = 33|0x10000U, /**< XBAR1_OUT33 output assigned to IOMUX_XBAR_OUT33 */ + kXBAR1_OutputIomuxXbarOut34 = 34|0x10000U, /**< XBAR1_OUT34 output assigned to IOMUX_XBAR_OUT34 */ + kXBAR1_OutputIomuxXbarOut35 = 35|0x10000U, /**< XBAR1_OUT35 output assigned to IOMUX_XBAR_OUT35 */ + kXBAR1_OutputIomuxXbarOut36 = 36|0x10000U, /**< XBAR1_OUT36 output assigned to IOMUX_XBAR_OUT36 */ + kXBAR1_OutputIomuxXbarOut37 = 37|0x10000U, /**< XBAR1_OUT37 output assigned to IOMUX_XBAR_OUT37 */ + kXBAR1_OutputIomuxXbarOut38 = 38|0x10000U, /**< XBAR1_OUT38 output assigned to IOMUX_XBAR_OUT38 */ + kXBAR1_OutputIomuxXbarOut39 = 39|0x10000U, /**< XBAR1_OUT39 output assigned to IOMUX_XBAR_OUT39 */ + kXBAR1_OutputIomuxXbarOut40 = 40|0x10000U, /**< XBAR1_OUT40 output assigned to IOMUX_XBAR_OUT40 */ + kXBAR1_OutputTriggerSyncAsyncIn0 = 41|0x10000U, /**< XBAR1_OUT41 output assigned to TRIGGER_SYNC_ASYNC_IN0 */ + kXBAR1_OutputTriggerSyncAsyncIn1 = 42|0x10000U, /**< XBAR1_OUT42 output assigned to TRIGGER_SYNC_ASYNC_IN1 */ + kXBAR1_OutputTriggerSyncAsyncIn2 = 43|0x10000U, /**< XBAR1_OUT43 output assigned to TRIGGER_SYNC_ASYNC_IN2 */ + kXBAR1_OutputTriggerSyncAsyncIn3 = 44|0x10000U, /**< XBAR1_OUT44 output assigned to TRIGGER_SYNC_ASYNC_IN3 */ + kXBAR1_OutputTriggerSyncAsyncIn4 = 45|0x10000U, /**< XBAR1_OUT45 output assigned to TRIGGER_SYNC_ASYNC_IN4 */ + kXBAR1_OutputTriggerSyncAsyncIn5 = 46|0x10000U, /**< XBAR1_OUT46 output assigned to TRIGGER_SYNC_ASYNC_IN5 */ + kXBAR1_OutputTriggerSyncAsyncIn6 = 47|0x10000U, /**< XBAR1_OUT47 output assigned to TRIGGER_SYNC_ASYNC_IN6 */ + kXBAR1_OutputTriggerSyncAsyncIn7 = 48|0x10000U, /**< XBAR1_OUT48 output assigned to TRIGGER_SYNC_ASYNC_IN7 */ + kXBAR1_OutputFlexpwm1Exta0 = 49|0x10000U, /**< XBAR1_OUT49 output assigned to FLEXPWM1_EXTA0 */ + kXBAR1_OutputFlexpwm1Exta1 = 50|0x10000U, /**< XBAR1_OUT50 output assigned to FLEXPWM1_EXTA1 */ + kXBAR1_OutputFlexpwm1Exta2 = 51|0x10000U, /**< XBAR1_OUT51 output assigned to FLEXPWM1_EXTA2 */ + kXBAR1_OutputFlexpwm1Exta3 = 52|0x10000U, /**< XBAR1_OUT52 output assigned to FLEXPWM1_EXTA3 */ + kXBAR1_OutputFlexpwm1ExtSync0 = 53|0x10000U, /**< XBAR1_OUT53 output assigned to FLEXPWM1_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm1ExtSync1 = 54|0x10000U, /**< XBAR1_OUT54 output assigned to FLEXPWM1_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm1ExtSync2 = 55|0x10000U, /**< XBAR1_OUT55 output assigned to FLEXPWM1_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm1ExtSync3 = 56|0x10000U, /**< XBAR1_OUT56 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm1ExtClk = 57|0x10000U, /**< XBAR1_OUT57 output assigned to FLEXPWM1_EXT_CLK */ + kXBAR1_OutputFlexpwm1IppIndFault0 = 58|0x10000U, /**< XBAR1_OUT58 output assigned to FLEXPWM1_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm1IppIndFault1 = 59|0x10000U, /**< XBAR1_OUT59 output assigned to FLEXPWM1_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm1IppIndFault2 = 60|0x10000U, /**< XBAR1_OUT60 output assigned to FLEXPWM1_IPP_IND_FAULT2 */ + kXBAR1_OutputFlexpwm1IppIndFault3 = 61|0x10000U, /**< XBAR1_OUT61 output assigned to FLEXPWM1_IPP_IND_FAULT3 */ + kXBAR1_OutputFlexpwm1ExtForce = 62|0x10000U, /**< XBAR1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */ + kXBAR1_OutputFlexpwm2Exta0 = 63|0x10000U, /**< XBAR1_OUT63 output assigned to FLEXPWM2_EXTA0 */ + kXBAR1_OutputFlexpwm2Exta1 = 64|0x10000U, /**< XBAR1_OUT64 output assigned to FLEXPWM2_EXTA1 */ + kXBAR1_OutputFlexpwm2Exta2 = 65|0x10000U, /**< XBAR1_OUT65 output assigned to FLEXPWM2_EXTA2 */ + kXBAR1_OutputFlexpwm2Exta3 = 66|0x10000U, /**< XBAR1_OUT66 output assigned to FLEXPWM2_EXTA3 */ + kXBAR1_OutputFlexpwm2ExtSync0 = 67|0x10000U, /**< XBAR1_OUT67 output assigned to FLEXPWM2_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm2ExtSync1 = 68|0x10000U, /**< XBAR1_OUT68 output assigned to FLEXPWM2_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm2ExtSync2 = 69|0x10000U, /**< XBAR1_OUT69 output assigned to FLEXPWM2_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm2ExtSync3 = 70|0x10000U, /**< XBAR1_OUT70 output assigned to FLEXPWM2_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm2ExtClk = 71|0x10000U, /**< XBAR1_OUT71 output assigned to FLEXPWM2_EXT_CLK */ + kXBAR1_OutputFlexpwm2IppIndFault0 = 72|0x10000U, /**< XBAR1_OUT72 output assigned to FLEXPWM2_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm2IppIndFault1 = 73|0x10000U, /**< XBAR1_OUT73 output assigned to FLEXPWM2_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm2ExtForce = 74|0x10000U, /**< XBAR1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */ + kXBAR1_OutputFlexpwm3Exta0 = 75|0x10000U, /**< XBAR1_OUT75 output assigned to FLEXPWM3_EXTA0 */ + kXBAR1_OutputFlexpwm3Exta1 = 76|0x10000U, /**< XBAR1_OUT76 output assigned to FLEXPWM3_EXTA1 */ + kXBAR1_OutputFlexpwm3Exta2 = 77|0x10000U, /**< XBAR1_OUT77 output assigned to FLEXPWM3_EXTA2 */ + kXBAR1_OutputFlexpwm3Exta3 = 78|0x10000U, /**< XBAR1_OUT78 output assigned to FLEXPWM3_EXTA3 */ + kXBAR1_OutputFlexpwm3ExtClk = 79|0x10000U, /**< XBAR1_OUT79 output assigned to FLEXPWM3_EXT_CLK */ + kXBAR1_OutputFlexpwm3ExtSync0 = 80|0x10000U, /**< XBAR1_OUT80 output assigned to FLEXPWM3_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm3ExtSync1 = 81|0x10000U, /**< XBAR1_OUT81 output assigned to FLEXPWM3_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm3ExtSync2 = 82|0x10000U, /**< XBAR1_OUT82 output assigned to FLEXPWM3_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm3ExtSync3 = 83|0x10000U, /**< XBAR1_OUT83 output assigned to FLEXPWM3_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm3IppIndFault0 = 84|0x10000U, /**< XBAR1_OUT84 output assigned to FLEXPWM3_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm3IppIndFault1 = 85|0x10000U, /**< XBAR1_OUT85 output assigned to FLEXPWM3_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm3ExtForce = 86|0x10000U, /**< XBAR1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */ + kXBAR1_OutputFlexpwm4ExtSync0 = 87|0x10000U, /**< XBAR1_OUT87 output assigned to FLEXPWM4_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm4ExtSync1 = 88|0x10000U, /**< XBAR1_OUT88 output assigned to FLEXPWM4_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm4ExtSync2 = 89|0x10000U, /**< XBAR1_OUT89 output assigned to FLEXPWM4_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm4ExtSync3 = 90|0x10000U, /**< XBAR1_OUT90 output assigned to FLEXPWM4_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm4IppIndFault0 = 91|0x10000U, /**< XBAR1_OUT91 output assigned to FLEXPWM4_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm4IppIndFault1 = 92|0x10000U, /**< XBAR1_OUT92 output assigned to FLEXPWM4_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm4ExtForce = 93|0x10000U, /**< XBAR1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */ + kXBAR1_OutputEnc1PhaseAInput = 94|0x10000U, /**< XBAR1_OUT94 output assigned to ENC1_PHASE_A_INPUT */ + kXBAR1_OutputEnc1PhaseBInput = 95|0x10000U, /**< XBAR1_OUT95 output assigned to ENC1_PHASE_B_INPUT */ + kXBAR1_OutputEnc1Index = 96|0x10000U, /**< XBAR1_OUT96 output assigned to ENC1_INDEX */ + kXBAR1_OutputEnc1Home = 97|0x10000U, /**< XBAR1_OUT97 output assigned to ENC1_HOME */ + kXBAR1_OutputEnc1Trigger = 98|0x10000U, /**< XBAR1_OUT98 output assigned to ENC1_TRIGGER */ + kXBAR1_OutputEnc2PhaseAInput = 99|0x10000U, /**< XBAR1_OUT99 output assigned to ENC2_PHASE_A_INPUT */ + kXBAR1_OutputEnc2PhaseBInput = 100|0x10000U, /**< XBAR1_OUT100 output assigned to ENC2_PHASE_B_INPUT */ + kXBAR1_OutputEnc2Index = 101|0x10000U, /**< XBAR1_OUT101 output assigned to ENC2_INDEX */ + kXBAR1_OutputEnc2Home = 102|0x10000U, /**< XBAR1_OUT102 output assigned to ENC2_HOME */ + kXBAR1_OutputEnc2Trigger = 103|0x10000U, /**< XBAR1_OUT103 output assigned to ENC2_TRIGGER */ + kXBAR1_OutputEnc3PhaseAInput = 104|0x10000U, /**< XBAR1_OUT104 output assigned to ENC3_PHASE_A_INPUT */ + kXBAR1_OutputEnc3PhaseBInput = 105|0x10000U, /**< XBAR1_OUT105 output assigned to ENC3_PHASE_B_INPUT */ + kXBAR1_OutputEnc3Index = 106|0x10000U, /**< XBAR1_OUT106 output assigned to ENC3_INDEX */ + kXBAR1_OutputEnc3Home = 107|0x10000U, /**< XBAR1_OUT107 output assigned to ENC3_HOME */ + kXBAR1_OutputEnc3Trigger = 108|0x10000U, /**< XBAR1_OUT108 output assigned to ENC3_TRIGGER */ + kXBAR1_OutputEnc4PhaseAInput = 109|0x10000U, /**< XBAR1_OUT109 output assigned to ENC4_PHASE_A_INPUT */ + kXBAR1_OutputEnc4PhaseBInput = 110|0x10000U, /**< XBAR1_OUT110 output assigned to ENC4_PHASE_B_INPUT */ + kXBAR1_OutputEnc4Index = 111|0x10000U, /**< XBAR1_OUT111 output assigned to ENC4_INDEX */ + kXBAR1_OutputEnc4Home = 112|0x10000U, /**< XBAR1_OUT112 output assigned to ENC4_HOME */ + kXBAR1_OutputEnc4Trigger = 113|0x10000U, /**< XBAR1_OUT113 output assigned to ENC4_TRIGGER */ + kXBAR1_OutputQtimer1Tmr0Input = 114|0x10000U, /**< XBAR1_OUT114 output assigned to QTIMER1_TMR0_INPUT */ + kXBAR1_OutputQtimer1Tmr1Input = 115|0x10000U, /**< XBAR1_OUT115 output assigned to QTIMER1_TMR1_INPUT */ + kXBAR1_OutputQtimer1Tmr2Input = 116|0x10000U, /**< XBAR1_OUT116 output assigned to QTIMER1_TMR2_INPUT */ + kXBAR1_OutputQtimer1Tmr3Input = 117|0x10000U, /**< XBAR1_OUT117 output assigned to QTIMER1_TMR3_INPUT */ + kXBAR1_OutputQtimer2Tmr0Input = 118|0x10000U, /**< XBAR1_OUT118 output assigned to QTIMER2_TMR0_INPUT */ + kXBAR1_OutputQtimer2Tmr1Input = 119|0x10000U, /**< XBAR1_OUT119 output assigned to QTIMER2_TMR1_INPUT */ + kXBAR1_OutputQtimer2Tmr2Input = 120|0x10000U, /**< XBAR1_OUT120 output assigned to QTIMER2_TMR2_INPUT */ + kXBAR1_OutputQtimer2Tmr3Input = 121|0x10000U, /**< XBAR1_OUT121 output assigned to QTIMER2_TMR3_INPUT */ + kXBAR1_OutputQtimer3Tmr0Input = 122|0x10000U, /**< XBAR1_OUT122 output assigned to QTIMER3_TMR0_INPUT */ + kXBAR1_OutputQtimer3Tmr1Input = 123|0x10000U, /**< XBAR1_OUT123 output assigned to QTIMER3_TMR1_INPUT */ + kXBAR1_OutputQtimer3Tmr2Input = 124|0x10000U, /**< XBAR1_OUT124 output assigned to QTIMER3_TMR2_INPUT */ + kXBAR1_OutputQtimer3Tmr3Input = 125|0x10000U, /**< XBAR1_OUT125 output assigned to QTIMER3_TMR3_INPUT */ + kXBAR1_OutputQtimer4Tmr0Input = 126|0x10000U, /**< XBAR1_OUT126 output assigned to QTIMER4_TMR0_INPUT */ + kXBAR1_OutputQtimer4Tmr1Input = 127|0x10000U, /**< XBAR1_OUT127 output assigned to QTIMER4_TMR1_INPUT */ + kXBAR1_OutputQtimer4Tmr2Input = 128|0x10000U, /**< XBAR1_OUT128 output assigned to QTIMER4_TMR2_INPUT */ + kXBAR1_OutputQtimer4Tmr3Input = 129|0x10000U, /**< XBAR1_OUT129 output assigned to QTIMER4_TMR3_INPUT */ + kXBAR1_OutputQtimer5Tmr0Input = 130|0x10000U, /**< XBAR1_OUT130 output assigned to QTIMER5_TMR0_INPUT */ + kXBAR1_OutputQtimer5Tmr1Input = 131|0x10000U, /**< XBAR1_OUT131 output assigned to QTIMER5_TMR1_INPUT */ + kXBAR1_OutputQtimer5Tmr2Input = 132|0x10000U, /**< XBAR1_OUT132 output assigned to QTIMER5_TMR2_INPUT */ + kXBAR1_OutputQtimer5Tmr3Input = 133|0x10000U, /**< XBAR1_OUT133 output assigned to QTIMER5_TMR3_INPUT */ + kXBAR1_OutputQtimer6Tmr0Input = 134|0x10000U, /**< XBAR1_OUT134 output assigned to QTIMER6_TMR0_INPUT */ + kXBAR1_OutputQtimer6Tmr1Input = 135|0x10000U, /**< XBAR1_OUT135 output assigned to QTIMER6_TMR1_INPUT */ + kXBAR1_OutputQtimer6Tmr2Input = 136|0x10000U, /**< XBAR1_OUT136 output assigned to QTIMER6_TMR2_INPUT */ + kXBAR1_OutputQtimer6Tmr3Input = 137|0x10000U, /**< XBAR1_OUT137 output assigned to QTIMER6_TMR3_INPUT */ + kXBAR1_OutputQtimer7Tmr0Input = 138|0x10000U, /**< XBAR1_OUT138 output assigned to QTIMER7_TMR0_INPUT */ + kXBAR1_OutputQtimer7Tmr1Input = 139|0x10000U, /**< XBAR1_OUT139 output assigned to QTIMER7_TMR1_INPUT */ + kXBAR1_OutputQtimer7Tmr2Input = 140|0x10000U, /**< XBAR1_OUT140 output assigned to QTIMER7_TMR2_INPUT */ + kXBAR1_OutputQtimer7Tmr3Input = 141|0x10000U, /**< XBAR1_OUT141 output assigned to QTIMER7_TMR3_INPUT */ + kXBAR1_OutputQtimer8Tmr0Input = 142|0x10000U, /**< XBAR1_OUT142 output assigned to QTIMER8_TMR0_INPUT */ + kXBAR1_OutputQtimer8Tmr1Input = 143|0x10000U, /**< XBAR1_OUT143 output assigned to QTIMER8_TMR1_INPUT */ + kXBAR1_OutputQtimer8Tmr2Input = 144|0x10000U, /**< XBAR1_OUT144 output assigned to QTIMER8_TMR2_INPUT */ + kXBAR1_OutputQtimer8Tmr3Input = 145|0x10000U, /**< XBAR1_OUT145 output assigned to QTIMER8_TMR3_INPUT */ + kXBAR1_OutputEwmEwmIn = 146|0x10000U, /**< XBAR1_OUT146 output assigned to EWM_EWM_IN */ + kXBAR1_OutputAnamixGlueTrgmuxInjectionTrg = 147|0x10000U, /**< XBAR1_OUT147 output assigned to ANAMIX_GLUE_TRGMUX_INJECTION_TRG */ + kXBAR1_OutputAnamixGlueTrgmuxStartTrg = 148|0x10000U, /**< XBAR1_OUT148 output assigned to ANAMIX_GLUE_TRGMUX_START_TRG */ + kXBAR1_OutputSinc1ExtTrigger0 = 149|0x10000U, /**< XBAR1_OUT149 output assigned to SINC1_EXT_TRIGGER0 */ + kXBAR1_OutputSinc1ExtTrigger1 = 150|0x10000U, /**< XBAR1_OUT150 output assigned to SINC1_EXT_TRIGGER1 */ + kXBAR1_OutputSinc1ExtTrigger2 = 151|0x10000U, /**< XBAR1_OUT151 output assigned to SINC1_EXT_TRIGGER2 */ + kXBAR1_OutputSinc1ExtTrigger3 = 152|0x10000U, /**< XBAR1_OUT152 output assigned to SINC1_EXT_TRIGGER3 */ + kXBAR1_OutputFlexio1FlexioTriggerIn0 = 153|0x10000U, /**< XBAR1_OUT153 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio1FlexioTriggerIn1 = 154|0x10000U, /**< XBAR1_OUT154 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio2FlexioTriggerIn0 = 155|0x10000U, /**< XBAR1_OUT155 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio2FlexioTriggerIn1 = 156|0x10000U, /**< XBAR1_OUT156 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio3FlexioTriggerIn0 = 157|0x10000U, /**< XBAR1_OUT157 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio3FlexioTriggerIn1 = 158|0x10000U, /**< XBAR1_OUT158 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio4FlexioTriggerIn0 = 159|0x10000U, /**< XBAR1_OUT159 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio4FlexioTriggerIn1 = 160|0x10000U, /**< XBAR1_OUT160 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputLpi2c1Lpi2cTrgInput = 161|0x10000U, /**< XBAR1_OUT161 output assigned to LPI2C1_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c2Lpi2cTrgInput = 162|0x10000U, /**< XBAR1_OUT162 output assigned to LPI2C2_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c3Lpi2cTrgInput = 163|0x10000U, /**< XBAR1_OUT163 output assigned to LPI2C3_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c4Lpi2cTrgInput = 164|0x10000U, /**< XBAR1_OUT164 output assigned to LPI2C4_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c5Lpi2cTrgInput = 165|0x10000U, /**< XBAR1_OUT165 output assigned to LPI2C5_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c6Lpi2cTrgInput = 166|0x10000U, /**< XBAR1_OUT166 output assigned to LPI2C6_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c7Lpi2cTrgInput = 167|0x10000U, /**< XBAR1_OUT167 output assigned to LPI2C7_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c8Lpi2cTrgInput = 168|0x10000U, /**< XBAR1_OUT168 output assigned to LPI2C8_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpspi1LpspiTrgInput = 169|0x10000U, /**< XBAR1_OUT169 output assigned to LPSPI1_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi2LpspiTrgInput = 170|0x10000U, /**< XBAR1_OUT170 output assigned to LPSPI2_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi3LpspiTrgInput = 171|0x10000U, /**< XBAR1_OUT171 output assigned to LPSPI3_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi4LpspiTrgInput = 172|0x10000U, /**< XBAR1_OUT172 output assigned to LPSPI4_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi5LpspiTrgInput = 173|0x10000U, /**< XBAR1_OUT173 output assigned to LPSPI5_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi6LpspiTrgInput = 174|0x10000U, /**< XBAR1_OUT174 output assigned to LPSPI6_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi7LpspiTrgInput = 175|0x10000U, /**< XBAR1_OUT175 output assigned to LPSPI7_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi8LpspiTrgInput = 176|0x10000U, /**< XBAR1_OUT176 output assigned to LPSPI8_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpuart1LpuartTrgInput = 177|0x10000U, /**< XBAR1_OUT177 output assigned to LPUART1_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart2LpuartTrgInput = 178|0x10000U, /**< XBAR1_OUT178 output assigned to LPUART2_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart3LpuartTrgInput = 179|0x10000U, /**< XBAR1_OUT179 output assigned to LPUART3_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart4LpuartTrgInput = 180|0x10000U, /**< XBAR1_OUT180 output assigned to LPUART4_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart5LpuartTrgInput = 181|0x10000U, /**< XBAR1_OUT181 output assigned to LPUART5_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart6LpuartTrgInput = 182|0x10000U, /**< XBAR1_OUT182 output assigned to LPUART6_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart7LpuartTrgInput = 183|0x10000U, /**< XBAR1_OUT183 output assigned to LPUART7_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart8LpuartTrgInput = 184|0x10000U, /**< XBAR1_OUT184 output assigned to LPUART8_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart9LpuartTrgInput = 185|0x10000U, /**< XBAR1_OUT185 output assigned to LPUART9_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart10LpuartTrgInput = 186|0x10000U, /**< XBAR1_OUT186 output assigned to LPUART10_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart11LpuartTrgInput = 187|0x10000U, /**< XBAR1_OUT187 output assigned to LPUART11_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart12LpuartTrgInput = 188|0x10000U, /**< XBAR1_OUT188 output assigned to LPUART12_LPUART_TRG_INPUT */ + kXBAR1_OutputLpit1LpitExtTrigIn0 = 189|0x10000U, /**< XBAR1_OUT189 output assigned to LPIT1_LPIT_EXT_TRIG_IN0 */ + kXBAR1_OutputLpit1LpitExtTrigIn1 = 190|0x10000U, /**< XBAR1_OUT190 output assigned to LPIT1_LPIT_EXT_TRIG_IN1 */ + kXBAR1_OutputLpit1LpitExtTrigIn2 = 191|0x10000U, /**< XBAR1_OUT191 output assigned to LPIT1_LPIT_EXT_TRIG_IN2 */ + kXBAR1_OutputLpit1LpitExtTrigIn3 = 192|0x10000U, /**< XBAR1_OUT192 output assigned to LPIT1_LPIT_EXT_TRIG_IN3 */ + kXBAR1_OutputTpm1LptpmTriggerIn0 = 193|0x10000U, /**< XBAR1_OUT193 output assigned to TPM1_LPTPM_TRIGGER_IN0 */ + kXBAR1_OutputTpm1LptpmTriggerIn1 = 194|0x10000U, /**< XBAR1_OUT194 output assigned to TPM1_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm2LptpmTriggerIn1 = 195|0x10000U, /**< XBAR1_OUT195 output assigned to TPM2_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm3LptpmTriggerIn1 = 196|0x10000U, /**< XBAR1_OUT196 output assigned to TPM3_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm1LptpmTriggerIn2 = 197|0x10000U, /**< XBAR1_OUT197 output assigned to TPM1_LPTPM_TRIGGER_IN2 */ + kXBAR1_OutputTpm1LptpmTriggerIn3 = 198|0x10000U, /**< XBAR1_OUT198 output assigned to TPM1_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm2LptpmTriggerIn3 = 199|0x10000U, /**< XBAR1_OUT199 output assigned to TPM2_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm3LptpmTriggerIn3 = 200|0x10000U, /**< XBAR1_OUT200 output assigned to TPM3_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm4LptpmTriggerIn0 = 201|0x10000U, /**< XBAR1_OUT201 output assigned to TPM4_LPTPM_TRIGGER_IN0 */ + kXBAR1_OutputTpm4LptpmTriggerIn1 = 202|0x10000U, /**< XBAR1_OUT202 output assigned to TPM4_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm5LptpmTriggerIn1 = 203|0x10000U, /**< XBAR1_OUT203 output assigned to TPM5_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm6LptpmTriggerIn1 = 204|0x10000U, /**< XBAR1_OUT204 output assigned to TPM6_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm4LptpmTriggerIn2 = 205|0x10000U, /**< XBAR1_OUT205 output assigned to TPM4_LPTPM_TRIGGER_IN2 */ + kXBAR1_OutputTpm4LptpmTriggerIn3 = 206|0x10000U, /**< XBAR1_OUT206 output assigned to TPM4_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm5LptpmTriggerIn3 = 207|0x10000U, /**< XBAR1_OUT207 output assigned to TPM5_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm6LptpmTriggerIn3 = 208|0x10000U, /**< XBAR1_OUT208 output assigned to TPM6_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputNetcTmr11588Trig1 = 209|0x10000U, /**< XBAR1_OUT209 output assigned to NETC_TMR1_1588_TRIG1 */ + kXBAR1_OutputNetcTmr11588Trig2 = 210|0x10000U, /**< XBAR1_OUT210 output assigned to NETC_TMR1_1588_TRIG2 */ + kXBAR1_OutputNetcTmr21588Trig1 = 211|0x10000U, /**< XBAR1_OUT211 output assigned to NETC_TMR2_1588_TRIG1 */ + kXBAR1_OutputNetcTmr21588Trig2 = 212|0x10000U, /**< XBAR1_OUT212 output assigned to NETC_TMR2_1588_TRIG2 */ + kXBAR1_OutputNetcTmr31588Trig1 = 213|0x10000U, /**< XBAR1_OUT213 output assigned to NETC_TMR3_1588_TRIG1 */ + kXBAR1_OutputNetcTmr31588Trig2 = 214|0x10000U, /**< XBAR1_OUT214 output assigned to NETC_TMR3_1588_TRIG2 */ + kXBAR1_OutputEnc1Icap1 = 215|0x10000U, /**< XBAR1_OUT215 output assigned to ENC1_ICAP1 */ + kXBAR1_OutputEnc1Icap2 = 216|0x10000U, /**< XBAR1_OUT216 output assigned to ENC1_ICAP2 */ + kXBAR1_OutputEnc1Icap3 = 217|0x10000U, /**< XBAR1_OUT217 output assigned to ENC1_ICAP3 */ + kXBAR1_OutputEnc2Icap1 = 218|0x10000U, /**< XBAR1_OUT218 output assigned to ENC2_ICAP1 */ + kXBAR1_OutputEnc2Icap2 = 219|0x10000U, /**< XBAR1_OUT219 output assigned to ENC2_ICAP2 */ + kXBAR1_OutputEnc2Icap3 = 220|0x10000U, /**< XBAR1_OUT220 output assigned to ENC2_ICAP3 */ + kXBAR1_OutputEnc3Icap1 = 221|0x10000U, /**< XBAR1_OUT221 output assigned to ENC3_ICAP1 */ + kXBAR1_OutputEnc3Icap2 = 222|0x10000U, /**< XBAR1_OUT222 output assigned to ENC3_ICAP2 */ + kXBAR1_OutputEnc3Icap3 = 223|0x10000U, /**< XBAR1_OUT223 output assigned to ENC3_ICAP3 */ + kXBAR1_OutputEnc4Icap1 = 224|0x10000U, /**< XBAR1_OUT224 output assigned to ENC4_ICAP1 */ + kXBAR1_OutputEnc4Icap2 = 225|0x10000U, /**< XBAR1_OUT225 output assigned to ENC4_ICAP2 */ + kXBAR1_OutputEnc4Icap3 = 226|0x10000U, /**< XBAR1_OUT226 output assigned to ENC4_ICAP3 */ + kXBAR1_OutputEcatLatchIn0 = 227|0x10000U, /**< XBAR1_OUT227 output assigned to ECAT_LATCH_IN0 */ + kXBAR1_OutputEcatLatchIn1 = 228|0x10000U, /**< XBAR1_OUT228 output assigned to ECAT_LATCH_IN1 */ + kXBAR1_OutputSafetyClkMonDutClk = 229|0x10000U, /**< XBAR1_OUT229 output assigned to SAFETY_CLK_MON_DUT_CLK */ + kXBAR1_OutputEndat21StrN = 230|0x10000U, /**< XBAR1_OUT230 output assigned to ENDAT2_1_STR_N */ + kXBAR1_OutputEndat21Ir6N = 231|0x10000U, /**< XBAR1_OUT231 output assigned to ENDAT2_1_IR6_N */ + kXBAR1_OutputEndat21Ir7N = 232|0x10000U, /**< XBAR1_OUT232 output assigned to ENDAT2_1_IR7_N */ + kXBAR1_OutputEndat22StrN = 233|0x10000U, /**< XBAR1_OUT233 output assigned to ENDAT2_2_STR_N */ + kXBAR1_OutputEndat22Ir6N = 234|0x10000U, /**< XBAR1_OUT234 output assigned to ENDAT2_2_IR6_N */ + kXBAR1_OutputEndat22Ir7N = 235|0x10000U, /**< XBAR1_OUT235 output assigned to ENDAT2_2_IR7_N */ + kXBAR1_OutputEndat3HwStrobe = 236|0x10000U, /**< XBAR1_OUT236 output assigned to ENDAT3_HW_STROBE */ + kXBAR1_OutputBissGetsens = 237|0x10000U, /**< XBAR1_OUT237 output assigned to BISS_GETSENS */ + kXBAR1_OutputSinc3ExtTrigger2 = 238|0x10000U, /**< XBAR1_OUT238 output assigned to SINC3_EXT_TRIGGER2 */ + kXBAR1_OutputSinc3ExtTrigger3 = 239|0x10000U, /**< XBAR1_OUT239 output assigned to SINC3_EXT_TRIGGER3 */ + kXBAR1_OutputHiperface1SyncXbar = 240|0x10000U, /**< XBAR1_OUT240 output assigned to HIPERFACE1_SYNC_XBAR */ + kXBAR1_OutputHiperface2SyncXbar = 241|0x10000U, /**< XBAR1_OUT241 output assigned to HIPERFACE2_SYNC_XBAR */ + kXBAR1_OutputTriggerSyncAsyncIn8 = 242|0x10000U, /**< XBAR1_OUT242 output assigned to TRIGGER_SYNC_ASYNC_IN8 */ + kXBAR1_OutputTriggerSyncAsyncIn9 = 243|0x10000U, /**< XBAR1_OUT243 output assigned to TRIGGER_SYNC_ASYNC_IN9 */ + kXBAR1_OutputTriggerSyncAsyncIn10 = 244|0x10000U, /**< XBAR1_OUT244 output assigned to TRIGGER_SYNC_ASYNC_IN10 */ + kXBAR1_OutputTriggerSyncAsyncIn11 = 245|0x10000U, /**< XBAR1_OUT245 output assigned to TRIGGER_SYNC_ASYNC_IN11 */ + kXBAR1_OutputTriggerSyncAsyncIn12 = 246|0x10000U, /**< XBAR1_OUT246 output assigned to TRIGGER_SYNC_ASYNC_IN12 */ + kXBAR1_OutputTriggerSyncAsyncIn13 = 247|0x10000U, /**< XBAR1_OUT247 output assigned to TRIGGER_SYNC_ASYNC_IN13 */ + kXBAR1_OutputTriggerSyncAsyncIn14 = 248|0x10000U, /**< XBAR1_OUT248 output assigned to TRIGGER_SYNC_ASYNC_IN14 */ + kXBAR1_OutputTriggerSyncAsyncIn15 = 249|0x10000U, /**< XBAR1_OUT249 output assigned to TRIGGER_SYNC_ASYNC_IN15 */ + kXBAR1_OutputSinc2ExtTrigger0 = 250|0x10000U, /**< XBAR1_OUT250 output assigned to SINC2_EXT_TRIGGER0 */ + kXBAR1_OutputSinc2ExtTrigger1 = 251|0x10000U, /**< XBAR1_OUT251 output assigned to SINC2_EXT_TRIGGER1 */ + kXBAR1_OutputSinc2ExtTrigger2 = 252|0x10000U, /**< XBAR1_OUT252 output assigned to SINC2_EXT_TRIGGER2 */ + kXBAR1_OutputSinc2ExtTrigger3 = 253|0x10000U, /**< XBAR1_OUT253 output assigned to SINC2_EXT_TRIGGER3 */ + kXBAR1_OutputSinc3ExtTrigger0 = 254|0x10000U, /**< XBAR1_OUT254 output assigned to SINC3_EXT_TRIGGER0 */ + kXBAR1_OutputSinc3ExtTrigger1 = 255|0x10000U, /**< XBAR1_OUT255 output assigned to SINC3_EXT_TRIGGER1 */ + kXBAR2_OutputAoi1In00 = 0|0x20000U, /**< XBAR2_OUT0 output assigned to AOI1_IN00 */ + kXBAR2_OutputAoi1In01 = 1|0x20000U, /**< XBAR2_OUT1 output assigned to AOI1_IN01 */ + kXBAR2_OutputAoi1In02 = 2|0x20000U, /**< XBAR2_OUT2 output assigned to AOI1_IN02 */ + kXBAR2_OutputAoi1In03 = 3|0x20000U, /**< XBAR2_OUT3 output assigned to AOI1_IN03 */ + kXBAR2_OutputAoi1In04 = 4|0x20000U, /**< XBAR2_OUT4 output assigned to AOI1_IN04 */ + kXBAR2_OutputAoi1In05 = 5|0x20000U, /**< XBAR2_OUT5 output assigned to AOI1_IN05 */ + kXBAR2_OutputAoi1In06 = 6|0x20000U, /**< XBAR2_OUT6 output assigned to AOI1_IN06 */ + kXBAR2_OutputAoi1In07 = 7|0x20000U, /**< XBAR2_OUT7 output assigned to AOI1_IN07 */ + kXBAR2_OutputAoi1In08 = 8|0x20000U, /**< XBAR2_OUT8 output assigned to AOI1_IN08 */ + kXBAR2_OutputAoi1In09 = 9|0x20000U, /**< XBAR2_OUT9 output assigned to AOI1_IN09 */ + kXBAR2_OutputAoi1In10 = 10|0x20000U, /**< XBAR2_OUT10 output assigned to AOI1_IN10 */ + kXBAR2_OutputAoi1In11 = 11|0x20000U, /**< XBAR2_OUT11 output assigned to AOI1_IN11 */ + kXBAR2_OutputAoi1In12 = 12|0x20000U, /**< XBAR2_OUT12 output assigned to AOI1_IN12 */ + kXBAR2_OutputAoi1In13 = 13|0x20000U, /**< XBAR2_OUT13 output assigned to AOI1_IN13 */ + kXBAR2_OutputAoi1In14 = 14|0x20000U, /**< XBAR2_OUT14 output assigned to AOI1_IN14 */ + kXBAR2_OutputAoi1In15 = 15|0x20000U, /**< XBAR2_OUT15 output assigned to AOI1_IN15 */ + kXBAR2_OutputAoi3In00 = 16|0x20000U, /**< XBAR2_OUT16 output assigned to AOI3_IN00 */ + kXBAR2_OutputAoi3In01 = 17|0x20000U, /**< XBAR2_OUT17 output assigned to AOI3_IN01 */ + kXBAR2_OutputAoi3In02 = 18|0x20000U, /**< XBAR2_OUT18 output assigned to AOI3_IN02 */ + kXBAR2_OutputAoi3In03 = 19|0x20000U, /**< XBAR2_OUT19 output assigned to AOI3_IN03 */ + kXBAR2_OutputAoi3In04 = 20|0x20000U, /**< XBAR2_OUT20 output assigned to AOI3_IN04 */ + kXBAR2_OutputAoi3In05 = 21|0x20000U, /**< XBAR2_OUT21 output assigned to AOI3_IN05 */ + kXBAR2_OutputAoi3In06 = 22|0x20000U, /**< XBAR2_OUT22 output assigned to AOI3_IN06 */ + kXBAR2_OutputAoi3In07 = 23|0x20000U, /**< XBAR2_OUT23 output assigned to AOI3_IN07 */ + kXBAR2_OutputAoi3In08 = 24|0x20000U, /**< XBAR2_OUT24 output assigned to AOI3_IN08 */ + kXBAR2_OutputAoi3In09 = 25|0x20000U, /**< XBAR2_OUT25 output assigned to AOI3_IN09 */ + kXBAR2_OutputAoi3In10 = 26|0x20000U, /**< XBAR2_OUT26 output assigned to AOI3_IN10 */ + kXBAR2_OutputAoi3In11 = 27|0x20000U, /**< XBAR2_OUT27 output assigned to AOI3_IN11 */ + kXBAR2_OutputAoi3In12 = 28|0x20000U, /**< XBAR2_OUT28 output assigned to AOI3_IN12 */ + kXBAR2_OutputAoi3In13 = 29|0x20000U, /**< XBAR2_OUT29 output assigned to AOI3_IN13 */ + kXBAR2_OutputAoi3In14 = 30|0x20000U, /**< XBAR2_OUT30 output assigned to AOI3_IN14 */ + kXBAR2_OutputAoi3In15 = 31|0x20000U, /**< XBAR2_OUT31 output assigned to AOI3_IN15 */ + kXBAR3_OutputAoi2In00 = 0|0x30000U, /**< XBAR3_OUT0 output assigned to AOI2_IN00 */ + kXBAR3_OutputAoi2In01 = 1|0x30000U, /**< XBAR3_OUT1 output assigned to AOI2_IN01 */ + kXBAR3_OutputAoi2In02 = 2|0x30000U, /**< XBAR3_OUT2 output assigned to AOI2_IN02 */ + kXBAR3_OutputAoi2In03 = 3|0x30000U, /**< XBAR3_OUT3 output assigned to AOI2_IN03 */ + kXBAR3_OutputAoi2In04 = 4|0x30000U, /**< XBAR3_OUT4 output assigned to AOI2_IN04 */ + kXBAR3_OutputAoi2In05 = 5|0x30000U, /**< XBAR3_OUT5 output assigned to AOI2_IN05 */ + kXBAR3_OutputAoi2In06 = 6|0x30000U, /**< XBAR3_OUT6 output assigned to AOI2_IN06 */ + kXBAR3_OutputAoi2In07 = 7|0x30000U, /**< XBAR3_OUT7 output assigned to AOI2_IN07 */ + kXBAR3_OutputAoi2In08 = 8|0x30000U, /**< XBAR3_OUT8 output assigned to AOI2_IN08 */ + kXBAR3_OutputAoi2In09 = 9|0x30000U, /**< XBAR3_OUT9 output assigned to AOI2_IN09 */ + kXBAR3_OutputAoi2In10 = 10|0x30000U, /**< XBAR3_OUT10 output assigned to AOI2_IN10 */ + kXBAR3_OutputAoi2In11 = 11|0x30000U, /**< XBAR3_OUT11 output assigned to AOI2_IN11 */ + kXBAR3_OutputAoi2In12 = 12|0x30000U, /**< XBAR3_OUT12 output assigned to AOI2_IN12 */ + kXBAR3_OutputAoi2In13 = 13|0x30000U, /**< XBAR3_OUT13 output assigned to AOI2_IN13 */ + kXBAR3_OutputAoi2In14 = 14|0x30000U, /**< XBAR3_OUT14 output assigned to AOI2_IN14 */ + kXBAR3_OutputAoi2In15 = 15|0x30000U, /**< XBAR3_OUT15 output assigned to AOI2_IN15 */ + kXBAR3_OutputAoi4In00 = 16|0x30000U, /**< XBAR3_OUT16 output assigned to AOI4_IN00 */ + kXBAR3_OutputAoi4In01 = 17|0x30000U, /**< XBAR3_OUT17 output assigned to AOI4_IN01 */ + kXBAR3_OutputAoi4In02 = 18|0x30000U, /**< XBAR3_OUT18 output assigned to AOI4_IN02 */ + kXBAR3_OutputAoi4In03 = 19|0x30000U, /**< XBAR3_OUT19 output assigned to AOI4_IN03 */ + kXBAR3_OutputAoi4In04 = 20|0x30000U, /**< XBAR3_OUT20 output assigned to AOI4_IN04 */ + kXBAR3_OutputAoi4In05 = 21|0x30000U, /**< XBAR3_OUT21 output assigned to AOI4_IN05 */ + kXBAR3_OutputAoi4In06 = 22|0x30000U, /**< XBAR3_OUT22 output assigned to AOI4_IN06 */ + kXBAR3_OutputAoi4In07 = 23|0x30000U, /**< XBAR3_OUT23 output assigned to AOI4_IN07 */ + kXBAR3_OutputAoi4In08 = 24|0x30000U, /**< XBAR3_OUT24 output assigned to AOI4_IN08 */ + kXBAR3_OutputAoi4In09 = 25|0x30000U, /**< XBAR3_OUT25 output assigned to AOI4_IN09 */ + kXBAR3_OutputAoi4In10 = 26|0x30000U, /**< XBAR3_OUT26 output assigned to AOI4_IN10 */ + kXBAR3_OutputAoi4In11 = 27|0x30000U, /**< XBAR3_OUT27 output assigned to AOI4_IN11 */ + kXBAR3_OutputAoi4In12 = 28|0x30000U, /**< XBAR3_OUT28 output assigned to AOI4_IN12 */ + kXBAR3_OutputAoi4In13 = 29|0x30000U, /**< XBAR3_OUT29 output assigned to AOI4_IN13 */ + kXBAR3_OutputAoi4In14 = 30|0x30000U, /**< XBAR3_OUT30 output assigned to AOI4_IN14 */ + kXBAR3_OutputAoi4In15 = 31|0x30000U, /**< XBAR3_OUT31 output assigned to AOI4_IN15 */ +} xbar_output_signal_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ADC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ADC base address */ @@ -2187,6 +3279,35 @@ typedef enum IRQn { #define DCIF_BASE_PTRS { DCIF } #endif +/* DDRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DDRC base address */ + #define DDRC_BASE (0x5E080000u) + /** Peripheral DDRC base address */ + #define DDRC_BASE_NS (0x4E080000u) + /** Peripheral DDRC base pointer */ + #define DDRC ((DDRC_Type *)DDRC_BASE) + /** Peripheral DDRC base pointer */ + #define DDRC_NS ((DDRC_Type *)DDRC_BASE_NS) + /** Array initializer of DDRC peripheral base addresses */ + #define DDRC_BASE_ADDRS { DDRC_BASE } + /** Array initializer of DDRC peripheral base pointers */ + #define DDRC_BASE_PTRS { DDRC } + /** Array initializer of DDRC peripheral base addresses */ + #define DDRC_BASE_ADDRS_NS { DDRC_BASE_NS } + /** Array initializer of DDRC peripheral base pointers */ + #define DDRC_BASE_PTRS_NS { DDRC_NS } +#else + /** Peripheral DDRC base address */ + #define DDRC_BASE (0x4E080000u) + /** Peripheral DDRC base pointer */ + #define DDRC ((DDRC_Type *)DDRC_BASE) + /** Array initializer of DDRC peripheral base addresses */ + #define DDRC_BASE_ADDRS { DDRC_BASE } + /** Array initializer of DDRC peripheral base pointers */ + #define DDRC_BASE_PTRS { DDRC } +#endif + /* DDR_BLK_CTRL_DDRMIX - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral BLK_CTRL_DDRMIX base address */ @@ -2257,35 +3378,6 @@ typedef enum IRQn { #define DDR_CMU_BASE_PTRS { DDRC__CMU_1, DDRC__CMU_2 } #endif -/* DDR_DDRC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral DDRC base address */ - #define DDRC_BASE (0x5E080000u) - /** Peripheral DDRC base address */ - #define DDRC_BASE_NS (0x4E080000u) - /** Peripheral DDRC base pointer */ - #define DDRC ((DDR_DDRC_Type *)DDRC_BASE) - /** Peripheral DDRC base pointer */ - #define DDRC_NS ((DDR_DDRC_Type *)DDRC_BASE_NS) - /** Array initializer of DDR_DDRC peripheral base addresses */ - #define DDR_DDRC_BASE_ADDRS { DDRC_BASE } - /** Array initializer of DDR_DDRC peripheral base pointers */ - #define DDR_DDRC_BASE_PTRS { DDRC } - /** Array initializer of DDR_DDRC peripheral base addresses */ - #define DDR_DDRC_BASE_ADDRS_NS { DDRC_BASE_NS } - /** Array initializer of DDR_DDRC peripheral base pointers */ - #define DDR_DDRC_BASE_PTRS_NS { DDRC_NS } -#else - /** Peripheral DDRC base address */ - #define DDRC_BASE (0x4E080000u) - /** Peripheral DDRC base pointer */ - #define DDRC ((DDR_DDRC_Type *)DDRC_BASE) - /** Array initializer of DDR_DDRC peripheral base addresses */ - #define DDR_DDRC_BASE_ADDRS { DDRC_BASE } - /** Array initializer of DDR_DDRC peripheral base pointers */ - #define DDR_DDRC_BASE_PTRS { DDRC } -#endif - /* DDR_LSTCU - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral DDRC__LSTCU base address */ @@ -3571,23 +4663,59 @@ typedef enum IRQn { #define GPT1 ((GPT_Type *)GPT1_BASE) /** Peripheral GPT1 base pointer */ #define GPT1_NS ((GPT_Type *)GPT1_BASE_NS) + /** Peripheral GPT2 base address */ + #define GPT2_BASE (0x528A0000u) + /** Peripheral GPT2 base address */ + #define GPT2_BASE_NS (0x428A0000u) + /** Peripheral GPT2 base pointer */ + #define GPT2 ((GPT_Type *)GPT2_BASE) + /** Peripheral GPT2 base pointer */ + #define GPT2_NS ((GPT_Type *)GPT2_BASE_NS) + /** Peripheral GPT3 base address */ + #define GPT3_BASE (0x528B0000u) + /** Peripheral GPT3 base address */ + #define GPT3_BASE_NS (0x428B0000u) + /** Peripheral GPT3 base pointer */ + #define GPT3 ((GPT_Type *)GPT3_BASE) + /** Peripheral GPT3 base pointer */ + #define GPT3_NS ((GPT_Type *)GPT3_BASE_NS) + /** Peripheral GPT4 base address */ + #define GPT4_BASE (0x528C0000u) + /** Peripheral GPT4 base address */ + #define GPT4_BASE_NS (0x428C0000u) + /** Peripheral GPT4 base pointer */ + #define GPT4 ((GPT_Type *)GPT4_BASE) + /** Peripheral GPT4 base pointer */ + #define GPT4_NS ((GPT_Type *)GPT4_BASE_NS) /** Array initializer of GPT peripheral base addresses */ - #define GPT_BASE_ADDRS { GPT1_BASE } + #define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE } /** Array initializer of GPT peripheral base pointers */ - #define GPT_BASE_PTRS { GPT1 } + #define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4 } /** Array initializer of GPT peripheral base addresses */ - #define GPT_BASE_ADDRS_NS { GPT1_BASE_NS } + #define GPT_BASE_ADDRS_NS { 0u, GPT1_BASE_NS, GPT2_BASE_NS, GPT3_BASE_NS, GPT4_BASE_NS } /** Array initializer of GPT peripheral base pointers */ - #define GPT_BASE_PTRS_NS { GPT1_NS } + #define GPT_BASE_PTRS_NS { (GPT_Type *)0u, GPT1_NS, GPT2_NS, GPT3_NS, GPT4_NS } #else /** Peripheral GPT1 base address */ #define GPT1_BASE (0x446F0000u) /** Peripheral GPT1 base pointer */ #define GPT1 ((GPT_Type *)GPT1_BASE) + /** Peripheral GPT2 base address */ + #define GPT2_BASE (0x428A0000u) + /** Peripheral GPT2 base pointer */ + #define GPT2 ((GPT_Type *)GPT2_BASE) + /** Peripheral GPT3 base address */ + #define GPT3_BASE (0x428B0000u) + /** Peripheral GPT3 base pointer */ + #define GPT3 ((GPT_Type *)GPT3_BASE) + /** Peripheral GPT4 base address */ + #define GPT4_BASE (0x428C0000u) + /** Peripheral GPT4 base pointer */ + #define GPT4 ((GPT_Type *)GPT4_BASE) /** Array initializer of GPT peripheral base addresses */ - #define GPT_BASE_ADDRS { GPT1_BASE } + #define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE } /** Array initializer of GPT peripheral base pointers */ - #define GPT_BASE_PTRS { GPT1 } + #define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4 } #endif /* HIPERFACE - Peripheral instance base addresses */ @@ -3728,6 +4856,14 @@ typedef enum IRQn { #define SAI1 ((I2S_Type *)SAI1_BASE) /** Peripheral SAI1 base pointer */ #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Peripheral SAI2 base address */ + #define SAI2_BASE (0x52650000u) + /** Peripheral SAI2 base address */ + #define SAI2_BASE_NS (0x42650000u) + /** Peripheral SAI2 base pointer */ + #define SAI2 ((I2S_Type *)SAI2_BASE) + /** Peripheral SAI2 base pointer */ + #define SAI2_NS ((I2S_Type *)SAI2_BASE_NS) /** Peripheral SAI3 base address */ #define SAI3_BASE (0x52660000u) /** Peripheral SAI3 base address */ @@ -3745,18 +4881,22 @@ typedef enum IRQn { /** Peripheral SAI4 base pointer */ #define SAI4_NS ((I2S_Type *)SAI4_BASE_NS) /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { 0u, SAI1_BASE, 0u, SAI3_BASE, SAI4_BASE } + #define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE } /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, (I2S_Type *)0u, SAI3, SAI4 } + #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 } /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { 0u, SAI1_BASE_NS, 0u, SAI3_BASE_NS, SAI4_BASE_NS } + #define I2S_BASE_ADDRS_NS { 0u, SAI1_BASE_NS, SAI2_BASE_NS, SAI3_BASE_NS, SAI4_BASE_NS } /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { (I2S_Type *)0u, SAI1_NS, (I2S_Type *)0u, SAI3_NS, SAI4_NS } + #define I2S_BASE_PTRS_NS { (I2S_Type *)0u, SAI1_NS, SAI2_NS, SAI3_NS, SAI4_NS } #else /** Peripheral SAI1 base address */ #define SAI1_BASE (0x443B0000u) /** Peripheral SAI1 base pointer */ #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI2 base address */ + #define SAI2_BASE (0x42650000u) + /** Peripheral SAI2 base pointer */ + #define SAI2 ((I2S_Type *)SAI2_BASE) /** Peripheral SAI3 base address */ #define SAI3_BASE (0x42660000u) /** Peripheral SAI3 base pointer */ @@ -3766,13 +4906,13 @@ typedef enum IRQn { /** Peripheral SAI4 base pointer */ #define SAI4 ((I2S_Type *)SAI4_BASE) /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { 0u, SAI1_BASE, 0u, SAI3_BASE, SAI4_BASE } + #define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE } /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, (I2S_Type *)0u, SAI3, SAI4 } + #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 } #endif /** Interrupt vectors for the I2S peripheral type */ -#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, NotAvail_IRQn, SAI3_IRQn, SAI4_IRQn } -#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, NotAvail_IRQn, SAI3_IRQn, SAI4_IRQn } +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn } /* I3C - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -10062,13 +11202,13 @@ typedef enum IRQn { /** Peripheral TMR8 base pointer */ #define TMR8_NS ((TMR_Type *)TMR8_BASE_NS) /** Array initializer of TMR peripheral base addresses */ - #define TMR_BASE_ADDRS { TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } + #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } /** Array initializer of TMR peripheral base pointers */ - #define TMR_BASE_PTRS { TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } + #define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } /** Array initializer of TMR peripheral base addresses */ - #define TMR_BASE_ADDRS_NS { TMR1_BASE_NS, TMR2_BASE_NS, TMR3_BASE_NS, TMR4_BASE_NS, TMR5_BASE_NS, TMR6_BASE_NS, TMR7_BASE_NS, TMR8_BASE_NS } + #define TMR_BASE_ADDRS_NS { 0u, TMR1_BASE_NS, TMR2_BASE_NS, TMR3_BASE_NS, TMR4_BASE_NS, TMR5_BASE_NS, TMR6_BASE_NS, TMR7_BASE_NS, TMR8_BASE_NS } /** Array initializer of TMR peripheral base pointers */ - #define TMR_BASE_PTRS_NS { TMR1_NS, TMR2_NS, TMR3_NS, TMR4_NS, TMR5_NS, TMR6_NS, TMR7_NS, TMR8_NS } + #define TMR_BASE_PTRS_NS { (TMR_Type *)0u, TMR1_NS, TMR2_NS, TMR3_NS, TMR4_NS, TMR5_NS, TMR6_NS, TMR7_NS, TMR8_NS } #else /** Peripheral TMR1 base address */ #define TMR1_BASE (0x428D0000u) @@ -10103,9 +11243,9 @@ typedef enum IRQn { /** Peripheral TMR8 base pointer */ #define TMR8 ((TMR_Type *)TMR8_BASE) /** Array initializer of TMR peripheral base addresses */ - #define TMR_BASE_ADDRS { TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } + #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } /** Array initializer of TMR peripheral base pointers */ - #define TMR_BASE_PTRS { TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } + #define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } #endif /* TMR_GLOBAL - Peripheral instance base addresses */ @@ -10725,88 +11865,6 @@ typedef enum IRQn { #define WAKEUP_ERM_BASE_PTRS { WAKEUP__ERM } #endif -/* WAKEUP_GPT - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral GPT2 base address */ - #define GPT2_BASE (0x528A0000u) - /** Peripheral GPT2 base address */ - #define GPT2_BASE_NS (0x428A0000u) - /** Peripheral GPT2 base pointer */ - #define GPT2 ((WAKEUP_GPT_Type *)GPT2_BASE) - /** Peripheral GPT2 base pointer */ - #define GPT2_NS ((WAKEUP_GPT_Type *)GPT2_BASE_NS) - /** Peripheral GPT3 base address */ - #define GPT3_BASE (0x528B0000u) - /** Peripheral GPT3 base address */ - #define GPT3_BASE_NS (0x428B0000u) - /** Peripheral GPT3 base pointer */ - #define GPT3 ((WAKEUP_GPT_Type *)GPT3_BASE) - /** Peripheral GPT3 base pointer */ - #define GPT3_NS ((WAKEUP_GPT_Type *)GPT3_BASE_NS) - /** Peripheral GPT4 base address */ - #define GPT4_BASE (0x528C0000u) - /** Peripheral GPT4 base address */ - #define GPT4_BASE_NS (0x428C0000u) - /** Peripheral GPT4 base pointer */ - #define GPT4 ((WAKEUP_GPT_Type *)GPT4_BASE) - /** Peripheral GPT4 base pointer */ - #define GPT4_NS ((WAKEUP_GPT_Type *)GPT4_BASE_NS) - /** Array initializer of WAKEUP_GPT peripheral base addresses */ - #define WAKEUP_GPT_BASE_ADDRS { 0u, 0u, GPT2_BASE, GPT3_BASE, GPT4_BASE } - /** Array initializer of WAKEUP_GPT peripheral base pointers */ - #define WAKEUP_GPT_BASE_PTRS { (WAKEUP_GPT_Type *)0u, (WAKEUP_GPT_Type *)0u, GPT2, GPT3, GPT4 } - /** Array initializer of WAKEUP_GPT peripheral base addresses */ - #define WAKEUP_GPT_BASE_ADDRS_NS { 0u, 0u, GPT2_BASE_NS, GPT3_BASE_NS, GPT4_BASE_NS } - /** Array initializer of WAKEUP_GPT peripheral base pointers */ - #define WAKEUP_GPT_BASE_PTRS_NS { (WAKEUP_GPT_Type *)0u, (WAKEUP_GPT_Type *)0u, GPT2_NS, GPT3_NS, GPT4_NS } -#else - /** Peripheral GPT2 base address */ - #define GPT2_BASE (0x428A0000u) - /** Peripheral GPT2 base pointer */ - #define GPT2 ((WAKEUP_GPT_Type *)GPT2_BASE) - /** Peripheral GPT3 base address */ - #define GPT3_BASE (0x428B0000u) - /** Peripheral GPT3 base pointer */ - #define GPT3 ((WAKEUP_GPT_Type *)GPT3_BASE) - /** Peripheral GPT4 base address */ - #define GPT4_BASE (0x428C0000u) - /** Peripheral GPT4 base pointer */ - #define GPT4 ((WAKEUP_GPT_Type *)GPT4_BASE) - /** Array initializer of WAKEUP_GPT peripheral base addresses */ - #define WAKEUP_GPT_BASE_ADDRS { 0u, 0u, GPT2_BASE, GPT3_BASE, GPT4_BASE } - /** Array initializer of WAKEUP_GPT peripheral base pointers */ - #define WAKEUP_GPT_BASE_PTRS { (WAKEUP_GPT_Type *)0u, (WAKEUP_GPT_Type *)0u, GPT2, GPT3, GPT4 } -#endif - -/* WAKEUP_SAI - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral WAKEUP__SAI2 base address */ - #define WAKEUP__SAI2_BASE (0x52650000u) - /** Peripheral WAKEUP__SAI2 base address */ - #define WAKEUP__SAI2_BASE_NS (0x42650000u) - /** Peripheral WAKEUP__SAI2 base pointer */ - #define WAKEUP__SAI2 ((WAKEUP_SAI_Type *)WAKEUP__SAI2_BASE) - /** Peripheral WAKEUP__SAI2 base pointer */ - #define WAKEUP__SAI2_NS ((WAKEUP_SAI_Type *)WAKEUP__SAI2_BASE_NS) - /** Array initializer of WAKEUP_SAI peripheral base addresses */ - #define WAKEUP_SAI_BASE_ADDRS { WAKEUP__SAI2_BASE } - /** Array initializer of WAKEUP_SAI peripheral base pointers */ - #define WAKEUP_SAI_BASE_PTRS { WAKEUP__SAI2 } - /** Array initializer of WAKEUP_SAI peripheral base addresses */ - #define WAKEUP_SAI_BASE_ADDRS_NS { WAKEUP__SAI2_BASE_NS } - /** Array initializer of WAKEUP_SAI peripheral base pointers */ - #define WAKEUP_SAI_BASE_PTRS_NS { WAKEUP__SAI2_NS } -#else - /** Peripheral WAKEUP__SAI2 base address */ - #define WAKEUP__SAI2_BASE (0x42650000u) - /** Peripheral WAKEUP__SAI2 base pointer */ - #define WAKEUP__SAI2 ((WAKEUP_SAI_Type *)WAKEUP__SAI2_BASE) - /** Array initializer of WAKEUP_SAI peripheral base addresses */ - #define WAKEUP_SAI_BASE_ADDRS { WAKEUP__SAI2_BASE } - /** Array initializer of WAKEUP_SAI peripheral base pointers */ - #define WAKEUP_SAI_BASE_PTRS { WAKEUP__SAI2 } -#endif - /* WAKEUP_TCW - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral WAKEUP__TCW base address */ @@ -11545,3 +12603,4 @@ typedef enum #endif /* MIMX94398_CM33_CORE1_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1_features.h index 5c61693b1..ed15509f6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2023-11-01 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -53,8 +53,8 @@ #define FSL_FEATURE_SOC_AXBS_COUNT (2) /* @brief BBNSM availability on the SoC. */ #define FSL_FEATURE_SOC_BBNSM_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (1) +/* @brief DDRC availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_COUNT (1) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (4) /* @brief EIM availability on the SoC. */ @@ -74,7 +74,7 @@ /* @brief I3C availability on the SoC. */ #define FSL_FEATURE_SOC_I3C_COUNT (2) /* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (3) +#define FSL_FEATURE_SOC_I2S_COUNT (4) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ @@ -134,6 +134,8 @@ #define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) /* @brief Self-test threshold counts of ADC. */ #define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) +/* @brief Has external trigger or not. */ +#define FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER (1) /* AOI module features */ @@ -231,6 +233,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* TMPSNS module features */ @@ -400,8 +406,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -430,6 +434,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* RGPIO module features */ @@ -459,14 +465,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -565,8 +571,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -609,6 +613,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -771,6 +779,18 @@ #define FSL_FEATURE_NETC_HAS_NO_XGMII (1) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (1) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (1) /* @brief NXP Switch port group support. */ @@ -863,18 +883,18 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ + (((x) == SAI2) ? (128) : \ (((x) == SAI3) ? (128) : \ - (((x) == SAI4) ? (128) : (-1)))) + (((x) == SAI4) ? (128) : (-1))))) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ (((x) == SAI1) ? (2) : \ + (((x) == SAI2) ? (1) : \ (((x) == SAI3) ? (1) : \ - (((x) == SAI4) ? (1) : (-1)))) + (((x) == SAI4) ? (1) : (-1))))) /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ @@ -899,14 +919,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0.h index 443ad99ea..8834faabe 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0.h @@ -30,8 +30,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: iMX943RM rev1 draftK -** Version: rev. 1.0, 2023-11-01 -** Build: b250115 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX94398_cm7_core0 @@ -66,14 +66,17 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX94398_cm7_core0.h - * @version 1.0 - * @date 2023-11-01 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX94398_cm7_core0 * * CMSIS Peripheral Access Layer for MIMX94398_cm7_core0 @@ -121,9 +124,9 @@ #include "PERI_CCMSRCGPC_TCU.h" #include "PERI_CORTEXA_TCU.h" #include "PERI_DCIF.h" +#include "PERI_DDRC.h" #include "PERI_DDR_BLK_CTRL_DDRMIX.h" #include "PERI_DDR_CMU.h" -#include "PERI_DDR_DDRC.h" #include "PERI_DDR_LSTCU.h" #include "PERI_DDR_TCU.h" #include "PERI_DISPLAY_BLK_CTRL_DISPLAYMIX.h" @@ -314,8 +317,6 @@ #include "PERI_WAKEUP_DMA_CRC.h" #include "PERI_WAKEUP_EIM.h" #include "PERI_WAKEUP_ERM.h" -#include "PERI_WAKEUP_GPT.h" -#include "PERI_WAKEUP_SAI.h" #include "PERI_WAKEUP_TCW.h" #include "PERI_WAKEUP_TRDC_MGR_MEGA.h" #include "PERI_WAKEUP_USDHC.h" diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0_COMMON.h index d1fbcd386..f1b5e55c2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0_COMMON.h @@ -30,8 +30,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: iMX943RM rev1 draftK -** Version: rev. 1.0, 2023-11-01 -** Build: b250217 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX94398_cm7_core0 @@ -66,14 +66,17 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX94398_cm7_core0_COMMON.h - * @version 1.0 - * @date 2023-11-01 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX94398_cm7_core0 * * CMSIS Peripheral Access Layer for MIMX94398_cm7_core0 @@ -84,7 +87,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -1225,6 +1228,1095 @@ typedef enum IRQn { /* CPU specific feature definitions */ #include "MIMX94398_cm7_core0_features.h" +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +typedef enum _xbar_input_signal +{ + kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ + kXBAR1_InputLogicHigh = 1|0x10000U, /**< LOGIC_HIGH output assigned to XBAR1_IN1 input. */ + kXBAR1_InputLogicLow1 = 2|0x10000U, /**< LOGIC_LOW1 output assigned to XBAR1_IN2 input. */ + kXBAR1_InputLogicHigh1 = 3|0x10000U, /**< LOGIC_HIGH1 output assigned to XBAR1_IN3 input. */ + kXBAR1_InputIomuxXbarIn04 = 4|0x10000U, /**< IOMUX_XBAR_IN04 output assigned to XBAR1_IN4 input. */ + kXBAR1_InputIomuxXbarIn05 = 5|0x10000U, /**< IOMUX_XBAR_IN05 output assigned to XBAR1_IN5 input. */ + kXBAR1_InputIomuxXbarIn06 = 6|0x10000U, /**< IOMUX_XBAR_IN06 output assigned to XBAR1_IN6 input. */ + kXBAR1_InputIomuxXbarIn07 = 7|0x10000U, /**< IOMUX_XBAR_IN07 output assigned to XBAR1_IN7 input. */ + kXBAR1_InputIomuxXbarIn08 = 8|0x10000U, /**< IOMUX_XBAR_IN08 output assigned to XBAR1_IN8 input. */ + kXBAR1_InputIomuxXbarIn09 = 9|0x10000U, /**< IOMUX_XBAR_IN09 output assigned to XBAR1_IN9 input. */ + kXBAR1_InputIomuxXbarIn10 = 10|0x10000U, /**< IOMUX_XBAR_IN10 output assigned to XBAR1_IN10 input. */ + kXBAR1_InputIomuxXbarIn11 = 11|0x10000U, /**< IOMUX_XBAR_IN11 output assigned to XBAR1_IN11 input. */ + kXBAR1_InputIomuxXbarIn12 = 12|0x10000U, /**< IOMUX_XBAR_IN12 output assigned to XBAR1_IN12 input. */ + kXBAR1_InputIomuxXbarIn13 = 13|0x10000U, /**< IOMUX_XBAR_IN13 output assigned to XBAR1_IN13 input. */ + kXBAR1_InputIomuxXbarIn14 = 14|0x10000U, /**< IOMUX_XBAR_IN14 output assigned to XBAR1_IN14 input. */ + kXBAR1_InputIomuxXbarIn15 = 15|0x10000U, /**< IOMUX_XBAR_IN15 output assigned to XBAR1_IN15 input. */ + kXBAR1_InputIomuxXbarIn16 = 16|0x10000U, /**< IOMUX_XBAR_IN16 output assigned to XBAR1_IN16 input. */ + kXBAR1_InputIomuxXbarIn17 = 17|0x10000U, /**< IOMUX_XBAR_IN17 output assigned to XBAR1_IN17 input. */ + kXBAR1_InputIomuxXbarIn18 = 18|0x10000U, /**< IOMUX_XBAR_IN18 output assigned to XBAR1_IN18 input. */ + kXBAR1_InputIomuxXbarIn19 = 19|0x10000U, /**< IOMUX_XBAR_IN19 output assigned to XBAR1_IN19 input. */ + kXBAR1_InputIomuxXbarIn20 = 20|0x10000U, /**< IOMUX_XBAR_IN20 output assigned to XBAR1_IN20 input. */ + kXBAR1_InputIomuxXbarIn21 = 21|0x10000U, /**< IOMUX_XBAR_IN21 output assigned to XBAR1_IN21 input. */ + kXBAR1_InputIomuxXbarIn22 = 22|0x10000U, /**< IOMUX_XBAR_IN22 output assigned to XBAR1_IN22 input. */ + kXBAR1_InputIomuxXbarIn23 = 23|0x10000U, /**< IOMUX_XBAR_IN23 output assigned to XBAR1_IN23 input. */ + kXBAR1_InputIomuxXbarIn24 = 24|0x10000U, /**< IOMUX_XBAR_IN24 output assigned to XBAR1_IN24 input. */ + kXBAR1_InputIomuxXbarIn25 = 25|0x10000U, /**< IOMUX_XBAR_IN25 output assigned to XBAR1_IN25 input. */ + kXBAR1_InputIomuxXbarIn26 = 26|0x10000U, /**< IOMUX_XBAR_IN26 output assigned to XBAR1_IN26 input. */ + kXBAR1_InputIomuxXbarIn27 = 27|0x10000U, /**< IOMUX_XBAR_IN27 output assigned to XBAR1_IN27 input. */ + kXBAR1_InputIomuxXbarIn28 = 28|0x10000U, /**< IOMUX_XBAR_IN28 output assigned to XBAR1_IN28 input. */ + kXBAR1_InputIomuxXbarIn29 = 29|0x10000U, /**< IOMUX_XBAR_IN29 output assigned to XBAR1_IN29 input. */ + kXBAR1_InputIomuxXbarIn30 = 30|0x10000U, /**< IOMUX_XBAR_IN30 output assigned to XBAR1_IN30 input. */ + kXBAR1_InputIomuxXbarIn31 = 31|0x10000U, /**< IOMUX_XBAR_IN31 output assigned to XBAR1_IN31 input. */ + kXBAR1_InputIomuxXbarIn32 = 32|0x10000U, /**< IOMUX_XBAR_IN32 output assigned to XBAR1_IN32 input. */ + kXBAR1_InputIomuxXbarIn33 = 33|0x10000U, /**< IOMUX_XBAR_IN33 output assigned to XBAR1_IN33 input. */ + kXBAR1_InputIomuxXbarIn34 = 34|0x10000U, /**< IOMUX_XBAR_IN34 output assigned to XBAR1_IN34 input. */ + kXBAR1_InputIomuxXbarIn35 = 35|0x10000U, /**< IOMUX_XBAR_IN35 output assigned to XBAR1_IN35 input. */ + kXBAR1_InputIomuxXbarIn36 = 36|0x10000U, /**< IOMUX_XBAR_IN36 output assigned to XBAR1_IN36 input. */ + kXBAR1_InputIomuxXbarIn37 = 37|0x10000U, /**< IOMUX_XBAR_IN37 output assigned to XBAR1_IN37 input. */ + kXBAR1_InputIomuxXbarIn38 = 38|0x10000U, /**< IOMUX_XBAR_IN38 output assigned to XBAR1_IN38 input. */ + kXBAR1_InputIomuxXbarIn39 = 39|0x10000U, /**< IOMUX_XBAR_IN39 output assigned to XBAR1_IN39 input. */ + kXBAR1_InputIomuxXbarIn40 = 40|0x10000U, /**< IOMUX_XBAR_IN40 output assigned to XBAR1_IN40 input. */ + kXBAR1_InputIomuxXbarIn41 = 41|0x10000U, /**< IOMUX_XBAR_IN41 output assigned to XBAR1_IN41 input. */ + kXBAR1_InputIomuxXbarIn42 = 42|0x10000U, /**< IOMUX_XBAR_IN42 output assigned to XBAR1_IN42 input. */ + kXBAR1_InputIomuxXbarIn43 = 43|0x10000U, /**< IOMUX_XBAR_IN43 output assigned to XBAR1_IN43 input. */ + kXBAR1_InputIomuxXbarIn44 = 44|0x10000U, /**< IOMUX_XBAR_IN44 output assigned to XBAR1_IN44 input. */ + kXBAR1_InputIomuxXbarIn45 = 45|0x10000U, /**< IOMUX_XBAR_IN45 output assigned to XBAR1_IN45 input. */ + kXBAR1_InputIomuxXbarIn46 = 46|0x10000U, /**< IOMUX_XBAR_IN46 output assigned to XBAR1_IN46 input. */ + kXBAR1_InputIomuxXbarIn47 = 47|0x10000U, /**< IOMUX_XBAR_IN47 output assigned to XBAR1_IN47 input. */ + kXBAR1_InputIomuxXbarIn48 = 48|0x10000U, /**< IOMUX_XBAR_IN48 output assigned to XBAR1_IN48 input. */ + kXBAR1_InputQtimer1Timer0 = 49|0x10000U, /**< QTIMER1_TIMER0 output assigned to XBAR1_IN49 input. */ + kXBAR1_InputQtimer1Timer1 = 50|0x10000U, /**< QTIMER1_TIMER1 output assigned to XBAR1_IN50 input. */ + kXBAR1_InputQtimer1Timer2 = 51|0x10000U, /**< QTIMER1_TIMER2 output assigned to XBAR1_IN51 input. */ + kXBAR1_InputQtimer1Timer3 = 52|0x10000U, /**< QTIMER1_TIMER3 output assigned to XBAR1_IN52 input. */ + kXBAR1_InputQtimer2Timer0 = 53|0x10000U, /**< QTIMER2_TIMER0 output assigned to XBAR1_IN53 input. */ + kXBAR1_InputQtimer2Timer1 = 54|0x10000U, /**< QTIMER2_TIMER1 output assigned to XBAR1_IN54 input. */ + kXBAR1_InputQtimer2Timer2 = 55|0x10000U, /**< QTIMER2_TIMER2 output assigned to XBAR1_IN55 input. */ + kXBAR1_InputQtimer2Timer3 = 56|0x10000U, /**< QTIMER2_TIMER3 output assigned to XBAR1_IN56 input. */ + kXBAR1_InputQtimer3Timer0 = 57|0x10000U, /**< QTIMER3_TIMER0 output assigned to XBAR1_IN57 input. */ + kXBAR1_InputQtimer3Timer1 = 58|0x10000U, /**< QTIMER3_TIMER1 output assigned to XBAR1_IN58 input. */ + kXBAR1_InputQtimer3Timer2 = 59|0x10000U, /**< QTIMER3_TIMER2 output assigned to XBAR1_IN59 input. */ + kXBAR1_InputQtimer3Timer3 = 60|0x10000U, /**< QTIMER3_TIMER3 output assigned to XBAR1_IN60 input. */ + kXBAR1_InputQtimer4Timer0 = 61|0x10000U, /**< QTIMER4_TIMER0 output assigned to XBAR1_IN61 input. */ + kXBAR1_InputQtimer4Timer1 = 62|0x10000U, /**< QTIMER4_TIMER1 output assigned to XBAR1_IN62 input. */ + kXBAR1_InputQtimer4Timer2 = 63|0x10000U, /**< QTIMER4_TIMER2 output assigned to XBAR1_IN63 input. */ + kXBAR1_InputQtimer4Timer3 = 64|0x10000U, /**< QTIMER4_TIMER3 output assigned to XBAR1_IN64 input. */ + kXBAR1_InputQtimer5Timer0 = 65|0x10000U, /**< QTIMER5_TIMER0 output assigned to XBAR1_IN65 input. */ + kXBAR1_InputQtimer5Timer1 = 66|0x10000U, /**< QTIMER5_TIMER1 output assigned to XBAR1_IN66 input. */ + kXBAR1_InputQtimer5Timer2 = 67|0x10000U, /**< QTIMER5_TIMER2 output assigned to XBAR1_IN67 input. */ + kXBAR1_InputQtimer5Timer3 = 68|0x10000U, /**< QTIMER5_TIMER3 output assigned to XBAR1_IN68 input. */ + kXBAR1_InputQtimer6Timer0 = 69|0x10000U, /**< QTIMER6_TIMER0 output assigned to XBAR1_IN69 input. */ + kXBAR1_InputQtimer6Timer1 = 70|0x10000U, /**< QTIMER6_TIMER1 output assigned to XBAR1_IN70 input. */ + kXBAR1_InputQtimer6Timer2 = 71|0x10000U, /**< QTIMER6_TIMER2 output assigned to XBAR1_IN71 input. */ + kXBAR1_InputQtimer6Timer3 = 72|0x10000U, /**< QTIMER6_TIMER3 output assigned to XBAR1_IN72 input. */ + kXBAR1_InputQtimer7Timer0 = 73|0x10000U, /**< QTIMER7_TIMER0 output assigned to XBAR1_IN73 input. */ + kXBAR1_InputQtimer7Timer1 = 74|0x10000U, /**< QTIMER7_TIMER1 output assigned to XBAR1_IN74 input. */ + kXBAR1_InputQtimer7Timer2 = 75|0x10000U, /**< QTIMER7_TIMER2 output assigned to XBAR1_IN75 input. */ + kXBAR1_InputQtimer7Timer3 = 76|0x10000U, /**< QTIMER7_TIMER3 output assigned to XBAR1_IN76 input. */ + kXBAR1_InputQtimer8Timer0 = 77|0x10000U, /**< QTIMER8_TIMER0 output assigned to XBAR1_IN77 input. */ + kXBAR1_InputQtimer8Timer1 = 78|0x10000U, /**< QTIMER8_TIMER1 output assigned to XBAR1_IN78 input. */ + kXBAR1_InputQtimer8Timer2 = 79|0x10000U, /**< QTIMER8_TIMER2 output assigned to XBAR1_IN79 input. */ + kXBAR1_InputQtimer8Timer3 = 80|0x10000U, /**< QTIMER8_TIMER3 output assigned to XBAR1_IN80 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger0 = 81|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR1_IN81 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger0 = 82|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER0 output assigned to XBAR1_IN82 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger1 = 83|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR1_IN83 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger1 = 84|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER1 output assigned to XBAR1_IN84 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger2 = 85|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR1_IN85 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger2 = 86|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER2 output assigned to XBAR1_IN86 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger3 = 87|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR1_IN87 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger3 = 88|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER3 output assigned to XBAR1_IN88 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger0 = 89|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR1_IN89 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger0 = 90|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER0 output assigned to XBAR1_IN90 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger1 = 91|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR1_IN91 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger1 = 92|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER1 output assigned to XBAR1_IN92 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger2 = 93|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR1_IN93 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger2 = 94|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER2 output assigned to XBAR1_IN94 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger3 = 95|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR1_IN95 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger3 = 96|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER3 output assigned to XBAR1_IN96 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger0 = 97|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR1_IN97 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger0 = 98|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER0 output assigned to XBAR1_IN98 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger1 = 99|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR1_IN99 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger1 = 100|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER1 output assigned to XBAR1_IN100 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger2 = 101|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR1_IN101 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger2 = 102|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER2 output assigned to XBAR1_IN102 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger3 = 103|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR1_IN103 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger3 = 104|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER3 output assigned to XBAR1_IN104 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger0 = 105|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR1_IN105 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger0 = 106|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER0 output assigned to XBAR1_IN106 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger1 = 107|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR1_IN107 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger1 = 108|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER1 output assigned to XBAR1_IN108 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger2 = 109|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR1_IN109 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger2 = 110|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER2 output assigned to XBAR1_IN110 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger3 = 111|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR1_IN111 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger3 = 112|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER3 output assigned to XBAR1_IN112 input. */ + kXBAR1_InputLpit1LpitTrigOut0 = 113|0x10000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR1_IN113 input. */ + kXBAR1_InputLpit1LpitTrigOut1 = 114|0x10000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR1_IN114 input. */ + kXBAR1_InputLpit1LpitTrigOut2 = 115|0x10000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR1_IN115 input. */ + kXBAR1_InputLpit1LpitTrigOut3 = 116|0x10000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR1_IN116 input. */ + kXBAR1_InputLpit2LpitTrigOut0 = 117|0x10000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR1_IN117 input. */ + kXBAR1_InputLpit2LpitTrigOut1 = 118|0x10000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR1_IN118 input. */ + kXBAR1_InputLpit2LpitTrigOut2 = 119|0x10000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR1_IN119 input. */ + kXBAR1_InputLpit2LpitTrigOut3 = 120|0x10000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR1_IN120 input. */ + kXBAR1_InputLpit3LpitTrigOut0 = 121|0x10000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR1_IN121 input. */ + kXBAR1_InputLpit3LpitTrigOut1 = 122|0x10000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR1_IN122 input. */ + kXBAR1_InputLpit3LpitTrigOut2 = 123|0x10000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR1_IN123 input. */ + kXBAR1_InputLpit3LpitTrigOut3 = 124|0x10000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR1_IN124 input. */ + kXBAR1_InputTriggerSyncSyncOut0 = 125|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT0 output assigned to XBAR1_IN125 input. */ + kXBAR1_InputTriggerSyncSyncOut1 = 126|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT1 output assigned to XBAR1_IN126 input. */ + kXBAR1_InputTriggerSyncSyncOut2 = 127|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT2 output assigned to XBAR1_IN127 input. */ + kXBAR1_InputTriggerSyncSyncOut3 = 128|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT3 output assigned to XBAR1_IN128 input. */ + kXBAR1_InputEdma2DmaTriggerOut0 = 129|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN129 input. */ + kXBAR1_InputEdma2DmaTriggerOut1 = 130|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN130 input. */ + kXBAR1_InputEdma2DmaTriggerOut2 = 131|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN131 input. */ + kXBAR1_InputEdma2DmaTriggerOut3 = 132|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN132 input. */ + kXBAR1_InputEdma2DmaTriggerOut4 = 133|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN133 input. */ + kXBAR1_InputEdma2DmaTriggerOut5 = 134|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN134 input. */ + kXBAR1_InputEdma2DmaTriggerOut6 = 135|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN135 input. */ + kXBAR1_InputEdma2DmaTriggerOut7 = 136|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN136 input. */ + kXBAR1_InputEdma1DmaTriggerOut0 = 137|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN137 input. */ + kXBAR1_InputEdma1DmaTriggerOut1 = 138|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN138 input. */ + kXBAR1_InputEdma1DmaTriggerOut2 = 139|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN139 input. */ + kXBAR1_InputEdma1DmaTriggerOut3 = 140|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN140 input. */ + kXBAR1_InputEdma1DmaTriggerOut4 = 141|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN141 input. */ + kXBAR1_InputEdma1DmaTriggerOut5 = 142|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN142 input. */ + kXBAR1_InputEdma1DmaTriggerOut6 = 143|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN143 input. */ + kXBAR1_InputEdma1DmaTriggerOut7 = 144|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN144 input. */ + kXBAR1_InputEdma3DmaTriggerOut0 = 145|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN145 input. */ + kXBAR1_InputEdma3DmaTriggerOut1 = 146|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN146 input. */ + kXBAR1_InputEdma3DmaTriggerOut2 = 147|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN147 input. */ + kXBAR1_InputEdma3DmaTriggerOut3 = 148|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN148 input. */ + kXBAR1_InputEdma3DmaTriggerOut4 = 149|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN149 input. */ + kXBAR1_InputEdma3DmaTriggerOut5 = 150|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN150 input. */ + kXBAR1_InputEdma3DmaTriggerOut6 = 151|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN151 input. */ + kXBAR1_InputEdma3DmaTriggerOut7 = 152|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN152 input. */ + kXBAR1_InputEdma4DmaTriggerOut0 = 153|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN153 input. */ + kXBAR1_InputEdma4DmaTriggerOut1 = 154|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN154 input. */ + kXBAR1_InputEdma4DmaTriggerOut2 = 155|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN155 input. */ + kXBAR1_InputEdma4DmaTriggerOut3 = 156|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN156 input. */ + kXBAR1_InputEdma4DmaTriggerOut4 = 157|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN157 input. */ + kXBAR1_InputEdma4DmaTriggerOut5 = 158|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN158 input. */ + kXBAR1_InputEdma4DmaTriggerOut6 = 159|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN159 input. */ + kXBAR1_InputEdma4DmaTriggerOut7 = 160|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN160 input. */ + kXBAR1_InputAdc1IpiIntEoc = 161|0x10000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR1_IN161 input. */ + kXBAR1_InputAdc1IpiIntWd = 162|0x10000U, /**< ADC1_IPI_INT_WD output assigned to XBAR1_IN162 input. */ + kXBAR1_InputTpm1LptpmChTrigger0 = 163|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN163 input. */ + kXBAR1_InputTpm1LptpmChTrigger1 = 164|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN164 input. */ + kXBAR1_InputTpm1LptpmChTrigger2 = 165|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN165 input. */ + kXBAR1_InputTpm1LptpmChTrigger3 = 166|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN166 input. */ + kXBAR1_InputTpm1LptpmTrigger = 167|0x10000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR1_IN167 input. */ + kXBAR1_InputTpm2LptpmChTrigger0 = 168|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN168 input. */ + kXBAR1_InputTpm2LptpmChTrigger1 = 169|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN169 input. */ + kXBAR1_InputTpm2LptpmChTrigger2 = 170|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN170 input. */ + kXBAR1_InputTpm2LptpmChTrigger3 = 171|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN171 input. */ + kXBAR1_InputTpm2LptpmTrigger = 172|0x10000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR1_IN172 input. */ + kXBAR1_InputTpm3LptpmChTrigger0 = 173|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN173 input. */ + kXBAR1_InputTpm3LptpmChTrigger1 = 174|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN174 input. */ + kXBAR1_InputTpm3LptpmChTrigger2 = 175|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN175 input. */ + kXBAR1_InputTpm3LptpmChTrigger3 = 176|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN176 input. */ + kXBAR1_InputTpm3LptpmTrigger = 177|0x10000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR1_IN177 input. */ + kXBAR1_InputTpm4LptpmChTrigger0 = 178|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN178 input. */ + kXBAR1_InputTpm4LptpmChTrigger1 = 179|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN179 input. */ + kXBAR1_InputTpm4LptpmChTrigger2 = 180|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN180 input. */ + kXBAR1_InputTpm4LptpmChTrigger3 = 181|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN181 input. */ + kXBAR1_InputTpm4LptpmTrigger = 182|0x10000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR1_IN182 input. */ + kXBAR1_InputTpm5LptpmChTrigger0 = 183|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN183 input. */ + kXBAR1_InputTpm5LptpmChTrigger1 = 184|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN184 input. */ + kXBAR1_InputTpm5LptpmChTrigger2 = 185|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN185 input. */ + kXBAR1_InputTpm5LptpmChTrigger3 = 186|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN186 input. */ + kXBAR1_InputTpm5LptpmTrigger = 187|0x10000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR1_IN187 input. */ + kXBAR1_InputTpm6LptpmChTrigger0 = 188|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN188 input. */ + kXBAR1_InputTpm6LptpmChTrigger1 = 189|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN189 input. */ + kXBAR1_InputTpm6LptpmChTrigger2 = 190|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN190 input. */ + kXBAR1_InputTpm6LptpmChTrigger3 = 191|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN191 input. */ + kXBAR1_InputTpm6LptpmTrigger = 192|0x10000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR1_IN192 input. */ + kXBAR1_InputLptmr1LptimerTriggerDelay = 193|0x10000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN193 input. */ + kXBAR1_InputLptmr2LptimerTriggerDelay = 194|0x10000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN194 input. */ + kXBAR1_InputLogicLow2 = 195|0x10000U, /**< LOGIC_LOW2 output assigned to XBAR1_IN195 input. */ + kXBAR1_InputNetcTmr11588Pp1 = 196|0x10000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR1_IN196 input. */ + kXBAR1_InputNetcTmr11588Pp2 = 197|0x10000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR1_IN197 input. */ + kXBAR1_InputNetcTmr11588Pp3 = 198|0x10000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR1_IN198 input. */ + kXBAR1_InputNetcTmr11588Alarm1 = 199|0x10000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR1_IN199 input. */ + kXBAR1_InputNetcTmr11588Alarm2 = 200|0x10000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR1_IN200 input. */ + kXBAR1_InputNetcTmr21588Pp1 = 201|0x10000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR1_IN201 input. */ + kXBAR1_InputNetcTmr21588Pp2 = 202|0x10000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR1_IN202 input. */ + kXBAR1_InputNetcTmr21588Pp3 = 203|0x10000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR1_IN203 input. */ + kXBAR1_InputNetcTmr21588Alarm1 = 204|0x10000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR1_IN204 input. */ + kXBAR1_InputNetcTmr21588Alarm2 = 205|0x10000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR1_IN205 input. */ + kXBAR1_InputNetcTmr31588Pp1 = 206|0x10000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR1_IN206 input. */ + kXBAR1_InputNetcTmr31588Pp2 = 207|0x10000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR1_IN207 input. */ + kXBAR1_InputNetcTmr31588Pp3 = 208|0x10000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR1_IN208 input. */ + kXBAR1_InputNetcTmr31588Alarm1 = 209|0x10000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR1_IN209 input. */ + kXBAR1_InputNetcTmr31588Alarm2 = 210|0x10000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR1_IN210 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak0 = 211|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR1_IN211 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak1 = 212|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR1_IN212 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak2 = 213|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR1_IN213 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak3 = 214|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR1_IN214 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak0 = 215|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR1_IN215 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak1 = 216|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR1_IN216 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak2 = 217|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR1_IN217 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak3 = 218|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR1_IN218 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak0 = 219|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR1_IN219 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak1 = 220|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR1_IN220 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak2 = 221|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR1_IN221 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak3 = 222|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR1_IN222 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak0 = 223|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR1_IN223 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak1 = 224|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR1_IN224 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak2 = 225|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR1_IN225 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak3 = 226|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR1_IN226 input. */ + kXBAR1_InputAoi1AoiOut0 = 227|0x10000U, /**< AOI1_AOI_OUT0 output assigned to XBAR1_IN227 input. */ + kXBAR1_InputAoi1AoiOut1 = 228|0x10000U, /**< AOI1_AOI_OUT1 output assigned to XBAR1_IN228 input. */ + kXBAR1_InputAoi1AoiOut2 = 229|0x10000U, /**< AOI1_AOI_OUT2 output assigned to XBAR1_IN229 input. */ + kXBAR1_InputAoi1AoiOut3 = 230|0x10000U, /**< AOI1_AOI_OUT3 output assigned to XBAR1_IN230 input. */ + kXBAR1_InputAoi2AoiOut0 = 231|0x10000U, /**< AOI2_AOI_OUT0 output assigned to XBAR1_IN231 input. */ + kXBAR1_InputAoi2AoiOut1 = 232|0x10000U, /**< AOI2_AOI_OUT1 output assigned to XBAR1_IN232 input. */ + kXBAR1_InputAoi2AoiOut2 = 233|0x10000U, /**< AOI2_AOI_OUT2 output assigned to XBAR1_IN233 input. */ + kXBAR1_InputAoi2AoiOut3 = 234|0x10000U, /**< AOI2_AOI_OUT3 output assigned to XBAR1_IN234 input. */ + kXBAR1_InputTriggerSyncSyncOut4 = 235|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT4 output assigned to XBAR1_IN235 input. */ + kXBAR1_InputTriggerSyncSyncOut5 = 236|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT5 output assigned to XBAR1_IN236 input. */ + kXBAR1_InputTriggerSyncSyncOut6 = 237|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT6 output assigned to XBAR1_IN237 input. */ + kXBAR1_InputTriggerSyncSyncOut7 = 238|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT7 output assigned to XBAR1_IN238 input. */ + kXBAR1_InputAoi3AoiOut0 = 239|0x10000U, /**< AOI3_AOI_OUT0 output assigned to XBAR1_IN239 input. */ + kXBAR1_InputAoi3AoiOut1 = 240|0x10000U, /**< AOI3_AOI_OUT1 output assigned to XBAR1_IN240 input. */ + kXBAR1_InputAoi3AoiOut2 = 241|0x10000U, /**< AOI3_AOI_OUT2 output assigned to XBAR1_IN241 input. */ + kXBAR1_InputAoi3AoiOut3 = 242|0x10000U, /**< AOI3_AOI_OUT3 output assigned to XBAR1_IN242 input. */ + kXBAR1_InputAoi4AoiOut0 = 243|0x10000U, /**< AOI4_AOI_OUT0 output assigned to XBAR1_IN243 input. */ + kXBAR1_InputAoi4AoiOut1 = 244|0x10000U, /**< AOI4_AOI_OUT1 output assigned to XBAR1_IN244 input. */ + kXBAR1_InputAoi4AoiOut2 = 245|0x10000U, /**< AOI4_AOI_OUT2 output assigned to XBAR1_IN245 input. */ + kXBAR1_InputAoi4AoiOut3 = 246|0x10000U, /**< AOI4_AOI_OUT3 output assigned to XBAR1_IN246 input. */ + kXBAR1_InputEcatSyncOut0 = 247|0x10000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR1_IN247 input. */ + kXBAR1_InputEcatSyncOut1 = 248|0x10000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR1_IN248 input. */ + kXBAR1_InputFccuVfccuReactionsOut11 = 249|0x10000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR1_IN249 input. */ + kXBAR1_InputGpt1IppDoCmpout1 = 250|0x10000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR1_IN250 input. */ + kXBAR1_InputGpt1IppDoCmpout2 = 251|0x10000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR1_IN251 input. */ + kXBAR1_InputGpt1IppDoCmpout3 = 252|0x10000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR1_IN252 input. */ + kXBAR1_InputGpt2IppDoCmpout1 = 253|0x10000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR1_IN253 input. */ + kXBAR1_InputGpt2IppDoCmpout2 = 254|0x10000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR1_IN254 input. */ + kXBAR1_InputGpt2IppDoCmpout3 = 255|0x10000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR1_IN255 input. */ + kXBAR1_InputGpt3IppDoCmpout1 = 256|0x10000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR1_IN256 input. */ + kXBAR1_InputGpt3IppDoCmpout2 = 257|0x10000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR1_IN257 input. */ + kXBAR1_InputGpt3IppDoCmpout3 = 258|0x10000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR1_IN258 input. */ + kXBAR1_InputGpt4IppDoCmpout1 = 259|0x10000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR1_IN259 input. */ + kXBAR1_InputGpt4IppDoCmpout2 = 260|0x10000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR1_IN260 input. */ + kXBAR1_InputGpt4IppDoCmpout3 = 261|0x10000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR1_IN261 input. */ + kXBAR1_InputFlexio1FlexioTriggerOut0 = 262|0x10000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN262 input. */ + kXBAR1_InputFlexio2FlexioTriggerOut0 = 263|0x10000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN263 input. */ + kXBAR1_InputFlexio3FlexioTriggerOut0 = 264|0x10000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN264 input. */ + kXBAR1_InputFlexio4FlexioTriggerOut0 = 265|0x10000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN265 input. */ + kXBAR1_InputGpio1IpiIntRgpio0 = 266|0x10000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR1_IN266 input. */ + kXBAR1_InputGpio2IpiIntRgpio0 = 267|0x10000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR1_IN267 input. */ + kXBAR1_InputGpio3IpiIntRgpio0 = 268|0x10000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR1_IN268 input. */ + kXBAR1_InputGpio4IpiIntRgpio0 = 269|0x10000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR1_IN269 input. */ + kXBAR1_InputGpio5IpiIntRgpio0 = 270|0x10000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR1_IN270 input. */ + kXBAR1_InputGpio6IpiIntRgpio0 = 271|0x10000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR1_IN271 input. */ + kXBAR1_InputGpio7IpiIntRgpio0 = 272|0x10000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR1_IN272 input. */ + kXBAR1_InputCm33Txev = 273|0x10000U, /**< CM33_TXEV output assigned to XBAR1_IN273 input. */ + kXBAR1_InputCm33SyncTxev = 274|0x10000U, /**< CM33_SYNC_TXEV output assigned to XBAR1_IN274 input. */ + kXBAR1_InputEndat21SiN = 275|0x10000U, /**< ENDAT2_1_SI_N output assigned to XBAR1_IN275 input. */ + kXBAR1_InputEndat21TimerN = 276|0x10000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR1_IN276 input. */ + kXBAR1_InputEndat22SiN = 277|0x10000U, /**< ENDAT2_2_SI_N output assigned to XBAR1_IN277 input. */ + kXBAR1_InputEndat22TimerN = 278|0x10000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR1_IN278 input. */ + kXBAR1_InputBissEot = 279|0x10000U, /**< BISS_EOT output assigned to XBAR1_IN279 input. */ + kXBAR1_InputTriggerSyncSyncOut8 = 280|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT8 output assigned to XBAR1_IN280 input. */ + kXBAR1_InputTriggerSyncSyncOut9 = 281|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT9 output assigned to XBAR1_IN281 input. */ + kXBAR1_InputTriggerSyncSyncOut10 = 282|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT10 output assigned to XBAR1_IN282 input. */ + kXBAR1_InputTriggerSyncSyncOut11 = 283|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT11 output assigned to XBAR1_IN283 input. */ + kXBAR1_InputTriggerSyncSyncOut12 = 284|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT12 output assigned to XBAR1_IN284 input. */ + kXBAR1_InputTriggerSyncSyncOut13 = 285|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT13 output assigned to XBAR1_IN285 input. */ + kXBAR1_InputTriggerSyncSyncOut14 = 286|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT14 output assigned to XBAR1_IN286 input. */ + kXBAR1_InputTriggerSyncSyncOut15 = 287|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT15 output assigned to XBAR1_IN287 input. */ + kXBAR1_InputEcatResetOut = 288|0x10000U, /**< ECAT_RESET_OUT output assigned to XBAR1_IN288 input. */ + kXBAR1_InputHiperface1FastPosRcvdEvt = 289|0x10000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR1_IN289 input. */ + kXBAR1_InputHiperface2FastPosRcvdEvt = 290|0x10000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR1_IN290 input. */ + kXBAR2_InputLogicLow = 0|0x20000U, /**< LOGIC_LOW output assigned to XBAR2_IN0 input. */ + kXBAR2_InputLogicHigh = 1|0x20000U, /**< LOGIC_HIGH output assigned to XBAR2_IN1 input. */ + kXBAR2_InputLogicLow1 = 2|0x20000U, /**< LOGIC_LOW1 output assigned to XBAR2_IN2 input. */ + kXBAR2_InputLogicHigh1 = 3|0x20000U, /**< LOGIC_HIGH1 output assigned to XBAR2_IN3 input. */ + kXBAR2_InputQtimer1Timer0 = 4|0x20000U, /**< QTIMER1_TIMER0 output assigned to XBAR2_IN4 input. */ + kXBAR2_InputQtimer1Timer1 = 5|0x20000U, /**< QTIMER1_TIMER1 output assigned to XBAR2_IN5 input. */ + kXBAR2_InputQtimer1Timer2 = 6|0x20000U, /**< QTIMER1_TIMER2 output assigned to XBAR2_IN6 input. */ + kXBAR2_InputQtimer1Timer3 = 7|0x20000U, /**< QTIMER1_TIMER3 output assigned to XBAR2_IN7 input. */ + kXBAR2_InputQtimer2Timer0 = 8|0x20000U, /**< QTIMER2_TIMER0 output assigned to XBAR2_IN8 input. */ + kXBAR2_InputQtimer2Timer1 = 9|0x20000U, /**< QTIMER2_TIMER1 output assigned to XBAR2_IN9 input. */ + kXBAR2_InputQtimer2Timer2 = 10|0x20000U, /**< QTIMER2_TIMER2 output assigned to XBAR2_IN10 input. */ + kXBAR2_InputQtimer2Timer3 = 11|0x20000U, /**< QTIMER2_TIMER3 output assigned to XBAR2_IN11 input. */ + kXBAR2_InputQtimer3Timer0 = 12|0x20000U, /**< QTIMER3_TIMER0 output assigned to XBAR2_IN12 input. */ + kXBAR2_InputQtimer3Timer1 = 13|0x20000U, /**< QTIMER3_TIMER1 output assigned to XBAR2_IN13 input. */ + kXBAR2_InputQtimer3Timer2 = 14|0x20000U, /**< QTIMER3_TIMER2 output assigned to XBAR2_IN14 input. */ + kXBAR2_InputQtimer3Timer3 = 15|0x20000U, /**< QTIMER3_TIMER3 output assigned to XBAR2_IN15 input. */ + kXBAR2_InputQtimer4Timer0 = 16|0x20000U, /**< QTIMER4_TIMER0 output assigned to XBAR2_IN16 input. */ + kXBAR2_InputQtimer4Timer1 = 17|0x20000U, /**< QTIMER4_TIMER1 output assigned to XBAR2_IN17 input. */ + kXBAR2_InputQtimer4Timer2 = 18|0x20000U, /**< QTIMER4_TIMER2 output assigned to XBAR2_IN18 input. */ + kXBAR2_InputQtimer4Timer3 = 19|0x20000U, /**< QTIMER4_TIMER3 output assigned to XBAR2_IN19 input. */ + kXBAR2_InputQtimer5Timer0 = 20|0x20000U, /**< QTIMER5_TIMER0 output assigned to XBAR2_IN20 input. */ + kXBAR2_InputQtimer5Timer1 = 21|0x20000U, /**< QTIMER5_TIMER1 output assigned to XBAR2_IN21 input. */ + kXBAR2_InputQtimer5Timer2 = 22|0x20000U, /**< QTIMER5_TIMER2 output assigned to XBAR2_IN22 input. */ + kXBAR2_InputQtimer5Timer3 = 23|0x20000U, /**< QTIMER5_TIMER3 output assigned to XBAR2_IN23 input. */ + kXBAR2_InputQtimer6Timer0 = 24|0x20000U, /**< QTIMER6_TIMER0 output assigned to XBAR2_IN24 input. */ + kXBAR2_InputQtimer6Timer1 = 25|0x20000U, /**< QTIMER6_TIMER1 output assigned to XBAR2_IN25 input. */ + kXBAR2_InputQtimer6Timer2 = 26|0x20000U, /**< QTIMER6_TIMER2 output assigned to XBAR2_IN26 input. */ + kXBAR2_InputQtimer6Timer3 = 27|0x20000U, /**< QTIMER6_TIMER3 output assigned to XBAR2_IN27 input. */ + kXBAR2_InputQtimer7Timer0 = 28|0x20000U, /**< QTIMER7_TIMER0 output assigned to XBAR2_IN28 input. */ + kXBAR2_InputQtimer7Timer1 = 29|0x20000U, /**< QTIMER7_TIMER1 output assigned to XBAR2_IN29 input. */ + kXBAR2_InputQtimer7Timer2 = 30|0x20000U, /**< QTIMER7_TIMER2 output assigned to XBAR2_IN30 input. */ + kXBAR2_InputQtimer7Timer3 = 31|0x20000U, /**< QTIMER7_TIMER3 output assigned to XBAR2_IN31 input. */ + kXBAR2_InputQtimer8Timer0 = 32|0x20000U, /**< QTIMER8_TIMER0 output assigned to XBAR2_IN32 input. */ + kXBAR2_InputQtimer8Timer1 = 33|0x20000U, /**< QTIMER8_TIMER1 output assigned to XBAR2_IN33 input. */ + kXBAR2_InputQtimer8Timer2 = 34|0x20000U, /**< QTIMER8_TIMER2 output assigned to XBAR2_IN34 input. */ + kXBAR2_InputQtimer8Timer3 = 35|0x20000U, /**< QTIMER8_TIMER3 output assigned to XBAR2_IN35 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger0 = 36|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR2_IN36 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger1 = 37|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR2_IN37 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger2 = 38|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR2_IN38 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger3 = 39|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR2_IN39 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger0 = 40|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR2_IN40 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger1 = 41|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR2_IN41 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger2 = 42|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR2_IN42 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger3 = 43|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR2_IN43 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger0 = 44|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR2_IN44 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger1 = 45|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR2_IN45 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger2 = 46|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR2_IN46 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger3 = 47|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR2_IN47 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger0 = 48|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR2_IN48 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger1 = 49|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR2_IN49 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger2 = 50|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR2_IN50 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger3 = 51|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR2_IN51 input. */ + kXBAR2_InputLpit1LpitTrigOut0 = 52|0x20000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR2_IN52 input. */ + kXBAR2_InputLpit1LpitTrigOut1 = 53|0x20000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR2_IN53 input. */ + kXBAR2_InputLpit1LpitTrigOut2 = 54|0x20000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR2_IN54 input. */ + kXBAR2_InputLpit1LpitTrigOut3 = 55|0x20000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR2_IN55 input. */ + kXBAR2_InputLpit2LpitTrigOut0 = 56|0x20000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR2_IN56 input. */ + kXBAR2_InputLpit2LpitTrigOut1 = 57|0x20000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR2_IN57 input. */ + kXBAR2_InputLpit2LpitTrigOut2 = 58|0x20000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR2_IN58 input. */ + kXBAR2_InputLpit2LpitTrigOut3 = 59|0x20000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR2_IN59 input. */ + kXBAR2_InputLpit3LpitTrigOut0 = 60|0x20000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR2_IN60 input. */ + kXBAR2_InputLpit3LpitTrigOut1 = 61|0x20000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR2_IN61 input. */ + kXBAR2_InputLpit3LpitTrigOut2 = 62|0x20000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR2_IN62 input. */ + kXBAR2_InputLpit3LpitTrigOut3 = 63|0x20000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR2_IN63 input. */ + kXBAR2_InputEdma2DmaTriggerOut0 = 64|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN64 input. */ + kXBAR2_InputEdma2DmaTriggerOut1 = 65|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN65 input. */ + kXBAR2_InputEdma2DmaTriggerOut2 = 66|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN66 input. */ + kXBAR2_InputEdma2DmaTriggerOut3 = 67|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN67 input. */ + kXBAR2_InputEdma2DmaTriggerOut4 = 68|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN68 input. */ + kXBAR2_InputEdma2DmaTriggerOut5 = 69|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN69 input. */ + kXBAR2_InputEdma2DmaTriggerOut6 = 70|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN70 input. */ + kXBAR2_InputEdma2DmaTriggerOut7 = 71|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN71 input. */ + kXBAR2_InputEdma1DmaTriggerOut0 = 72|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN72 input. */ + kXBAR2_InputEdma1DmaTriggerOut1 = 73|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN73 input. */ + kXBAR2_InputEdma1DmaTriggerOut2 = 74|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN74 input. */ + kXBAR2_InputEdma1DmaTriggerOut3 = 75|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN75 input. */ + kXBAR2_InputEdma1DmaTriggerOut4 = 76|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN76 input. */ + kXBAR2_InputEdma1DmaTriggerOut5 = 77|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN77 input. */ + kXBAR2_InputEdma1DmaTriggerOut6 = 78|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN78 input. */ + kXBAR2_InputEdma1DmaTriggerOut7 = 79|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN79 input. */ + kXBAR2_InputEdma3DmaTriggerOut0 = 80|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN80 input. */ + kXBAR2_InputEdma3DmaTriggerOut1 = 81|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN81 input. */ + kXBAR2_InputEdma3DmaTriggerOut2 = 82|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN82 input. */ + kXBAR2_InputEdma3DmaTriggerOut3 = 83|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN83 input. */ + kXBAR2_InputEdma3DmaTriggerOut4 = 84|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN84 input. */ + kXBAR2_InputEdma3DmaTriggerOut5 = 85|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN85 input. */ + kXBAR2_InputEdma3DmaTriggerOut6 = 86|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN86 input. */ + kXBAR2_InputEdma3DmaTriggerOut7 = 87|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN87 input. */ + kXBAR2_InputEdma4DmaTriggerOut0 = 88|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN88 input. */ + kXBAR2_InputEdma4DmaTriggerOut1 = 89|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN89 input. */ + kXBAR2_InputEdma4DmaTriggerOut2 = 90|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN90 input. */ + kXBAR2_InputEdma4DmaTriggerOut3 = 91|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN91 input. */ + kXBAR2_InputEdma4DmaTriggerOut4 = 92|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN92 input. */ + kXBAR2_InputEdma4DmaTriggerOut5 = 93|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN93 input. */ + kXBAR2_InputEdma4DmaTriggerOut6 = 94|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN94 input. */ + kXBAR2_InputEdma4DmaTriggerOut7 = 95|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN95 input. */ + kXBAR2_InputAdc1IpiIntEoc = 96|0x20000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR2_IN96 input. */ + kXBAR2_InputAdc1IpiIntWd = 97|0x20000U, /**< ADC1_IPI_INT_WD output assigned to XBAR2_IN97 input. */ + kXBAR2_InputTpm1LptpmChTrigger0 = 98|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN98 input. */ + kXBAR2_InputTpm1LptpmChTrigger1 = 99|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN99 input. */ + kXBAR2_InputTpm1LptpmChTrigger2 = 100|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN100 input. */ + kXBAR2_InputTpm1LptpmChTrigger3 = 101|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN101 input. */ + kXBAR2_InputTpm1LptpmTrigger = 102|0x20000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR2_IN102 input. */ + kXBAR2_InputTpm2LptpmChTrigger0 = 103|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN103 input. */ + kXBAR2_InputTpm2LptpmChTrigger1 = 104|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN104 input. */ + kXBAR2_InputTpm2LptpmChTrigger2 = 105|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN105 input. */ + kXBAR2_InputTpm2LptpmChTrigger3 = 106|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN106 input. */ + kXBAR2_InputTpm2LptpmTrigger = 107|0x20000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR2_IN107 input. */ + kXBAR2_InputTpm3LptpmChTrigger0 = 108|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN108 input. */ + kXBAR2_InputTpm3LptpmChTrigger1 = 109|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN109 input. */ + kXBAR2_InputTpm3LptpmChTrigger2 = 110|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN110 input. */ + kXBAR2_InputTpm3LptpmChTrigger3 = 111|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN111 input. */ + kXBAR2_InputTpm3LptpmTrigger = 112|0x20000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR2_IN112 input. */ + kXBAR2_InputTpm4LptpmChTrigger0 = 113|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN113 input. */ + kXBAR2_InputTpm4LptpmChTrigger1 = 114|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN114 input. */ + kXBAR2_InputTpm4LptpmChTrigger2 = 115|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN115 input. */ + kXBAR2_InputTpm4LptpmChTrigger3 = 116|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN116 input. */ + kXBAR2_InputTpm4LptpmTrigger = 117|0x20000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR2_IN117 input. */ + kXBAR2_InputTpm5LptpmChTrigger0 = 118|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN118 input. */ + kXBAR2_InputTpm5LptpmChTrigger1 = 119|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN119 input. */ + kXBAR2_InputTpm5LptpmChTrigger2 = 120|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN120 input. */ + kXBAR2_InputTpm5LptpmChTrigger3 = 121|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN121 input. */ + kXBAR2_InputTpm5LptpmTrigger = 122|0x20000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR2_IN122 input. */ + kXBAR2_InputTpm6LptpmChTrigger0 = 123|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN123 input. */ + kXBAR2_InputTpm6LptpmChTrigger1 = 124|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN124 input. */ + kXBAR2_InputTpm6LptpmChTrigger2 = 125|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN125 input. */ + kXBAR2_InputTpm6LptpmChTrigger3 = 126|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN126 input. */ + kXBAR2_InputTpm6LptpmTrigger = 127|0x20000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR2_IN127 input. */ + kXBAR2_InputLptmr1LptimerTriggerDelay = 128|0x20000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN128 input. */ + kXBAR2_InputLptmr2LptimerTriggerDelay = 129|0x20000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN129 input. */ + kXBAR2_InputLogicLow2 = 130|0x20000U, /**< LOGIC_LOW2 output assigned to XBAR2_IN130 input. */ + kXBAR2_InputNetcTmr11588Pp1 = 131|0x20000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR2_IN131 input. */ + kXBAR2_InputNetcTmr11588Pp2 = 132|0x20000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR2_IN132 input. */ + kXBAR2_InputNetcTmr11588Pp3 = 133|0x20000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR2_IN133 input. */ + kXBAR2_InputNetcTmr11588Alarm1 = 134|0x20000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR2_IN134 input. */ + kXBAR2_InputNetcTmr11588Alarm2 = 135|0x20000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR2_IN135 input. */ + kXBAR2_InputNetcTmr21588Pp1 = 136|0x20000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR2_IN136 input. */ + kXBAR2_InputNetcTmr21588Pp2 = 137|0x20000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR2_IN137 input. */ + kXBAR2_InputNetcTmr21588Pp3 = 138|0x20000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR2_IN138 input. */ + kXBAR2_InputNetcTmr21588Alarm1 = 139|0x20000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR2_IN139 input. */ + kXBAR2_InputNetcTmr21588Alarm2 = 140|0x20000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR2_IN140 input. */ + kXBAR2_InputNetcTmr31588Pp1 = 141|0x20000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR2_IN141 input. */ + kXBAR2_InputNetcTmr31588Pp2 = 142|0x20000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR2_IN142 input. */ + kXBAR2_InputNetcTmr31588Pp3 = 143|0x20000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR2_IN143 input. */ + kXBAR2_InputNetcTmr31588Alarm1 = 144|0x20000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR2_IN144 input. */ + kXBAR2_InputNetcTmr31588Alarm2 = 145|0x20000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR2_IN145 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak0 = 146|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR2_IN146 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak1 = 147|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR2_IN147 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak2 = 148|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR2_IN148 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak3 = 149|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR2_IN149 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak0 = 150|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR2_IN150 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak1 = 151|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR2_IN151 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak2 = 152|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR2_IN152 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak3 = 153|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR2_IN153 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak0 = 154|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR2_IN154 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak1 = 155|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR2_IN155 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak2 = 156|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR2_IN156 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak3 = 157|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR2_IN157 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak0 = 158|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR2_IN158 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak1 = 159|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR2_IN159 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak2 = 160|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR2_IN160 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak3 = 161|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR2_IN161 input. */ + kXBAR2_InputSinc1PulseTrg0 = 162|0x20000U, /**< SINC1_PULSE_TRG0 output assigned to XBAR2_IN162 input. */ + kXBAR2_InputSinc1PulseTrg1 = 163|0x20000U, /**< SINC1_PULSE_TRG1 output assigned to XBAR2_IN163 input. */ + kXBAR2_InputSinc1PulseTrg2 = 164|0x20000U, /**< SINC1_PULSE_TRG2 output assigned to XBAR2_IN164 input. */ + kXBAR2_InputSinc1PulseTrg3 = 165|0x20000U, /**< SINC1_PULSE_TRG3 output assigned to XBAR2_IN165 input. */ + kXBAR2_InputSinc3PulseTrg0 = 166|0x20000U, /**< SINC3_PULSE_TRG0 output assigned to XBAR2_IN166 input. */ + kXBAR2_InputSinc3PulseTrg1 = 167|0x20000U, /**< SINC3_PULSE_TRG1 output assigned to XBAR2_IN167 input. */ + kXBAR2_InputSinc3PulseTrg2 = 168|0x20000U, /**< SINC3_PULSE_TRG2 output assigned to XBAR2_IN168 input. */ + kXBAR2_InputSinc3PulseTrg3 = 169|0x20000U, /**< SINC3_PULSE_TRG3 output assigned to XBAR2_IN169 input. */ + kXBAR2_InputEcatSyncOut0 = 170|0x20000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR2_IN170 input. */ + kXBAR2_InputEcatSyncOut1 = 171|0x20000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR2_IN171 input. */ + kXBAR2_InputFccuVfccuReactionsOut11 = 172|0x20000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR2_IN172 input. */ + kXBAR2_InputGpt1IppDoCmpout1 = 173|0x20000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR2_IN173 input. */ + kXBAR2_InputGpt1IppDoCmpout2 = 174|0x20000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR2_IN174 input. */ + kXBAR2_InputGpt1IppDoCmpout3 = 175|0x20000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR2_IN175 input. */ + kXBAR2_InputGpt2IppDoCmpout1 = 176|0x20000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR2_IN176 input. */ + kXBAR2_InputGpt2IppDoCmpout2 = 177|0x20000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR2_IN177 input. */ + kXBAR2_InputGpt2IppDoCmpout3 = 178|0x20000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR2_IN178 input. */ + kXBAR2_InputGpt3IppDoCmpout1 = 179|0x20000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR2_IN179 input. */ + kXBAR2_InputGpt3IppDoCmpout2 = 180|0x20000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR2_IN180 input. */ + kXBAR2_InputGpt3IppDoCmpout3 = 181|0x20000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR2_IN181 input. */ + kXBAR2_InputGpt4IppDoCmpout1 = 182|0x20000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR2_IN182 input. */ + kXBAR2_InputGpt4IppDoCmpout2 = 183|0x20000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR2_IN183 input. */ + kXBAR2_InputGpt4IppDoCmpout3 = 184|0x20000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR2_IN184 input. */ + kXBAR2_InputFlexio1FlexioTriggerOut0 = 185|0x20000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN185 input. */ + kXBAR2_InputFlexio2FlexioTriggerOut0 = 186|0x20000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN186 input. */ + kXBAR2_InputFlexio3FlexioTriggerOut0 = 187|0x20000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN187 input. */ + kXBAR2_InputFlexio4FlexioTriggerOut0 = 188|0x20000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN188 input. */ + kXBAR2_InputGpio1IpiIntRgpio0 = 189|0x20000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR2_IN189 input. */ + kXBAR2_InputGpio2IpiIntRgpio0 = 190|0x20000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR2_IN190 input. */ + kXBAR2_InputGpio3IpiIntRgpio0 = 191|0x20000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR2_IN191 input. */ + kXBAR2_InputGpio4IpiIntRgpio0 = 192|0x20000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR2_IN192 input. */ + kXBAR2_InputGpio5IpiIntRgpio0 = 193|0x20000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR2_IN193 input. */ + kXBAR2_InputGpio6IpiIntRgpio0 = 194|0x20000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR2_IN194 input. */ + kXBAR2_InputGpio7IpiIntRgpio0 = 195|0x20000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR2_IN195 input. */ + kXBAR2_InputCm33Txev = 196|0x20000U, /**< CM33_TXEV output assigned to XBAR2_IN196 input. */ + kXBAR2_InputCm33SyncTxev = 197|0x20000U, /**< CM33_SYNC_TXEV output assigned to XBAR2_IN197 input. */ + kXBAR2_InputEndat21SiN = 198|0x20000U, /**< ENDAT2_1_SI_N output assigned to XBAR2_IN198 input. */ + kXBAR2_InputEndat21TimerN = 199|0x20000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR2_IN199 input. */ + kXBAR2_InputEndat22SiN = 200|0x20000U, /**< ENDAT2_2_SI_N output assigned to XBAR2_IN200 input. */ + kXBAR2_InputEndat22TimerN = 201|0x20000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR2_IN201 input. */ + kXBAR2_InputBissEot = 202|0x20000U, /**< BISS_EOT output assigned to XBAR2_IN202 input. */ + kXBAR2_InputEnc1PosMatch0 = 203|0x20000U, /**< ENC1_POS_MATCH0 output assigned to XBAR2_IN203 input. */ + kXBAR2_InputEnc1PosMatch1 = 204|0x20000U, /**< ENC1_POS_MATCH1 output assigned to XBAR2_IN204 input. */ + kXBAR2_InputEnc1PosMatch2 = 205|0x20000U, /**< ENC1_POS_MATCH2 output assigned to XBAR2_IN205 input. */ + kXBAR2_InputEnc1PosMatch3 = 206|0x20000U, /**< ENC1_POS_MATCH3 output assigned to XBAR2_IN206 input. */ + kXBAR2_InputEnc1CompFlg0 = 207|0x20000U, /**< ENC1_COMP_FLG0 output assigned to XBAR2_IN207 input. */ + kXBAR2_InputEnc1CompFlg1 = 208|0x20000U, /**< ENC1_COMP_FLG1 output assigned to XBAR2_IN208 input. */ + kXBAR2_InputEnc1CompFlg2 = 209|0x20000U, /**< ENC1_COMP_FLG2 output assigned to XBAR2_IN209 input. */ + kXBAR2_InputEnc1CompFlg3 = 210|0x20000U, /**< ENC1_COMP_FLG3 output assigned to XBAR2_IN210 input. */ + kXBAR2_InputEnc1CntDn = 211|0x20000U, /**< ENC1_CNT_DN output assigned to XBAR2_IN211 input. */ + kXBAR2_InputEnc1CntUp = 212|0x20000U, /**< ENC1_CNT_UP output assigned to XBAR2_IN212 input. */ + kXBAR2_InputEnc1Dir = 213|0x20000U, /**< ENC1_DIR output assigned to XBAR2_IN213 input. */ + kXBAR2_InputEnc3PosMatch0 = 214|0x20000U, /**< ENC3_POS_MATCH0 output assigned to XBAR2_IN214 input. */ + kXBAR2_InputEnc3PosMatch1 = 215|0x20000U, /**< ENC3_POS_MATCH1 output assigned to XBAR2_IN215 input. */ + kXBAR2_InputEnc3PosMatch2 = 216|0x20000U, /**< ENC3_POS_MATCH2 output assigned to XBAR2_IN216 input. */ + kXBAR2_InputEnc3PosMatch3 = 217|0x20000U, /**< ENC3_POS_MATCH3 output assigned to XBAR2_IN217 input. */ + kXBAR2_InputEnc3CompFlg0 = 218|0x20000U, /**< ENC3_COMP_FLG0 output assigned to XBAR2_IN218 input. */ + kXBAR2_InputEnc3CompFlg1 = 219|0x20000U, /**< ENC3_COMP_FLG1 output assigned to XBAR2_IN219 input. */ + kXBAR2_InputEnc3CompFlg2 = 220|0x20000U, /**< ENC3_COMP_FLG2 output assigned to XBAR2_IN220 input. */ + kXBAR2_InputEnc3CompFlg3 = 221|0x20000U, /**< ENC3_COMP_FLG3 output assigned to XBAR2_IN221 input. */ + kXBAR2_InputEnc3CntDn = 222|0x20000U, /**< ENC3_CNT_DN output assigned to XBAR2_IN222 input. */ + kXBAR2_InputEnc3CntUp = 223|0x20000U, /**< ENC3_CNT_UP output assigned to XBAR2_IN223 input. */ + kXBAR2_InputEnc3Dir = 224|0x20000U, /**< ENC3_DIR output assigned to XBAR2_IN224 input. */ + kXBAR2_InputHiperface1FastPosRcvdEvt = 225|0x20000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR2_IN225 input. */ + kXBAR2_InputHiperface2FastPosRcvdEvt = 226|0x20000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR2_IN226 input. */ + kXBAR3_InputLogicLow = 0|0x30000U, /**< LOGIC_LOW output assigned to XBAR3_IN0 input. */ + kXBAR3_InputLogicHigh = 1|0x30000U, /**< LOGIC_HIGH output assigned to XBAR3_IN1 input. */ + kXBAR3_InputLogicLow1 = 2|0x30000U, /**< LOGIC_LOW1 output assigned to XBAR3_IN2 input. */ + kXBAR3_InputLogicHigh1 = 3|0x30000U, /**< LOGIC_HIGH1 output assigned to XBAR3_IN3 input. */ + kXBAR3_InputQtimer1Timer0 = 4|0x30000U, /**< QTIMER1_TIMER0 output assigned to XBAR3_IN4 input. */ + kXBAR3_InputQtimer1Timer1 = 5|0x30000U, /**< QTIMER1_TIMER1 output assigned to XBAR3_IN5 input. */ + kXBAR3_InputQtimer1Timer2 = 6|0x30000U, /**< QTIMER1_TIMER2 output assigned to XBAR3_IN6 input. */ + kXBAR3_InputQtimer1Timer3 = 7|0x30000U, /**< QTIMER1_TIMER3 output assigned to XBAR3_IN7 input. */ + kXBAR3_InputQtimer2Timer0 = 8|0x30000U, /**< QTIMER2_TIMER0 output assigned to XBAR3_IN8 input. */ + kXBAR3_InputQtimer2Timer1 = 9|0x30000U, /**< QTIMER2_TIMER1 output assigned to XBAR3_IN9 input. */ + kXBAR3_InputQtimer2Timer2 = 10|0x30000U, /**< QTIMER2_TIMER2 output assigned to XBAR3_IN10 input. */ + kXBAR3_InputQtimer2Timer3 = 11|0x30000U, /**< QTIMER2_TIMER3 output assigned to XBAR3_IN11 input. */ + kXBAR3_InputQtimer3Timer0 = 12|0x30000U, /**< QTIMER3_TIMER0 output assigned to XBAR3_IN12 input. */ + kXBAR3_InputQtimer3Timer1 = 13|0x30000U, /**< QTIMER3_TIMER1 output assigned to XBAR3_IN13 input. */ + kXBAR3_InputQtimer3Timer2 = 14|0x30000U, /**< QTIMER3_TIMER2 output assigned to XBAR3_IN14 input. */ + kXBAR3_InputQtimer3Timer3 = 15|0x30000U, /**< QTIMER3_TIMER3 output assigned to XBAR3_IN15 input. */ + kXBAR3_InputQtimer4Timer0 = 16|0x30000U, /**< QTIMER4_TIMER0 output assigned to XBAR3_IN16 input. */ + kXBAR3_InputQtimer4Timer1 = 17|0x30000U, /**< QTIMER4_TIMER1 output assigned to XBAR3_IN17 input. */ + kXBAR3_InputQtimer4Timer2 = 18|0x30000U, /**< QTIMER4_TIMER2 output assigned to XBAR3_IN18 input. */ + kXBAR3_InputQtimer4Timer3 = 19|0x30000U, /**< QTIMER4_TIMER3 output assigned to XBAR3_IN19 input. */ + kXBAR3_InputQtimer5Timer0 = 20|0x30000U, /**< QTIMER5_TIMER0 output assigned to XBAR3_IN20 input. */ + kXBAR3_InputQtimer5Timer1 = 21|0x30000U, /**< QTIMER5_TIMER1 output assigned to XBAR3_IN21 input. */ + kXBAR3_InputQtimer5Timer2 = 22|0x30000U, /**< QTIMER5_TIMER2 output assigned to XBAR3_IN22 input. */ + kXBAR3_InputQtimer5Timer3 = 23|0x30000U, /**< QTIMER5_TIMER3 output assigned to XBAR3_IN23 input. */ + kXBAR3_InputQtimer6Timer0 = 24|0x30000U, /**< QTIMER6_TIMER0 output assigned to XBAR3_IN24 input. */ + kXBAR3_InputQtimer6Timer1 = 25|0x30000U, /**< QTIMER6_TIMER1 output assigned to XBAR3_IN25 input. */ + kXBAR3_InputQtimer6Timer2 = 26|0x30000U, /**< QTIMER6_TIMER2 output assigned to XBAR3_IN26 input. */ + kXBAR3_InputQtimer6Timer3 = 27|0x30000U, /**< QTIMER6_TIMER3 output assigned to XBAR3_IN27 input. */ + kXBAR3_InputQtimer7Timer0 = 28|0x30000U, /**< QTIMER7_TIMER0 output assigned to XBAR3_IN28 input. */ + kXBAR3_InputQtimer7Timer1 = 29|0x30000U, /**< QTIMER7_TIMER1 output assigned to XBAR3_IN29 input. */ + kXBAR3_InputQtimer7Timer2 = 30|0x30000U, /**< QTIMER7_TIMER2 output assigned to XBAR3_IN30 input. */ + kXBAR3_InputQtimer7Timer3 = 31|0x30000U, /**< QTIMER7_TIMER3 output assigned to XBAR3_IN31 input. */ + kXBAR3_InputQtimer8Timer0 = 32|0x30000U, /**< QTIMER8_TIMER0 output assigned to XBAR3_IN32 input. */ + kXBAR3_InputQtimer8Timer1 = 33|0x30000U, /**< QTIMER8_TIMER1 output assigned to XBAR3_IN33 input. */ + kXBAR3_InputQtimer8Timer2 = 34|0x30000U, /**< QTIMER8_TIMER2 output assigned to XBAR3_IN34 input. */ + kXBAR3_InputQtimer8Timer3 = 35|0x30000U, /**< QTIMER8_TIMER3 output assigned to XBAR3_IN35 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger0 = 36|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR3_IN36 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger1 = 37|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR3_IN37 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger2 = 38|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR3_IN38 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger3 = 39|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR3_IN39 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger0 = 40|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR3_IN40 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger1 = 41|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR3_IN41 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger2 = 42|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR3_IN42 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger3 = 43|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR3_IN43 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger0 = 44|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR3_IN44 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger1 = 45|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR3_IN45 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger2 = 46|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR3_IN46 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger3 = 47|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR3_IN47 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger0 = 48|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR3_IN48 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger1 = 49|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR3_IN49 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger2 = 50|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR3_IN50 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger3 = 51|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR3_IN51 input. */ + kXBAR3_InputLpit1LpitTrigOut0 = 52|0x30000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR3_IN52 input. */ + kXBAR3_InputLpit1LpitTrigOut1 = 53|0x30000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR3_IN53 input. */ + kXBAR3_InputLpit1LpitTrigOut2 = 54|0x30000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR3_IN54 input. */ + kXBAR3_InputLpit1LpitTrigOut3 = 55|0x30000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR3_IN55 input. */ + kXBAR3_InputLpit2LpitTrigOut0 = 56|0x30000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR3_IN56 input. */ + kXBAR3_InputLpit2LpitTrigOut1 = 57|0x30000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR3_IN57 input. */ + kXBAR3_InputLpit2LpitTrigOut2 = 58|0x30000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR3_IN58 input. */ + kXBAR3_InputLpit2LpitTrigOut3 = 59|0x30000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR3_IN59 input. */ + kXBAR3_InputLpit3LpitTrigOut0 = 60|0x30000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR3_IN60 input. */ + kXBAR3_InputLpit3LpitTrigOut1 = 61|0x30000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR3_IN61 input. */ + kXBAR3_InputLpit3LpitTrigOut2 = 62|0x30000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR3_IN62 input. */ + kXBAR3_InputLpit3LpitTrigOut3 = 63|0x30000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR3_IN63 input. */ + kXBAR3_InputEdma2DmaTriggerOut0 = 64|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN64 input. */ + kXBAR3_InputEdma2DmaTriggerOut1 = 65|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN65 input. */ + kXBAR3_InputEdma2DmaTriggerOut2 = 66|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN66 input. */ + kXBAR3_InputEdma2DmaTriggerOut3 = 67|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN67 input. */ + kXBAR3_InputEdma2DmaTriggerOut4 = 68|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN68 input. */ + kXBAR3_InputEdma2DmaTriggerOut5 = 69|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN69 input. */ + kXBAR3_InputEdma2DmaTriggerOut6 = 70|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN70 input. */ + kXBAR3_InputEdma2DmaTriggerOut7 = 71|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN71 input. */ + kXBAR3_InputEdma1DmaTriggerOut0 = 72|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN72 input. */ + kXBAR3_InputEdma1DmaTriggerOut1 = 73|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN73 input. */ + kXBAR3_InputEdma1DmaTriggerOut2 = 74|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN74 input. */ + kXBAR3_InputEdma1DmaTriggerOut3 = 75|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN75 input. */ + kXBAR3_InputEdma1DmaTriggerOut4 = 76|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN76 input. */ + kXBAR3_InputEdma1DmaTriggerOut5 = 77|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN77 input. */ + kXBAR3_InputEdma1DmaTriggerOut6 = 78|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN78 input. */ + kXBAR3_InputEdma1DmaTriggerOut7 = 79|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN79 input. */ + kXBAR3_InputEdma3DmaTriggerOut0 = 80|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN80 input. */ + kXBAR3_InputEdma3DmaTriggerOut1 = 81|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN81 input. */ + kXBAR3_InputEdma3DmaTriggerOut2 = 82|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN82 input. */ + kXBAR3_InputEdma3DmaTriggerOut3 = 83|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN83 input. */ + kXBAR3_InputEdma3DmaTriggerOut4 = 84|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN84 input. */ + kXBAR3_InputEdma3DmaTriggerOut5 = 85|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN85 input. */ + kXBAR3_InputEdma3DmaTriggerOut6 = 86|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN86 input. */ + kXBAR3_InputEdma3DmaTriggerOut7 = 87|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN87 input. */ + kXBAR3_InputEdma4DmaTriggerOut0 = 88|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN88 input. */ + kXBAR3_InputEdma4DmaTriggerOut1 = 89|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN89 input. */ + kXBAR3_InputEdma4DmaTriggerOut2 = 90|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN90 input. */ + kXBAR3_InputEdma4DmaTriggerOut3 = 91|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN91 input. */ + kXBAR3_InputEdma4DmaTriggerOut4 = 92|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN92 input. */ + kXBAR3_InputEdma4DmaTriggerOut5 = 93|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN93 input. */ + kXBAR3_InputEdma4DmaTriggerOut6 = 94|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN94 input. */ + kXBAR3_InputEdma4DmaTriggerOut7 = 95|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN95 input. */ + kXBAR3_InputAdc1IpiIntEoc = 96|0x30000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR3_IN96 input. */ + kXBAR3_InputAdc1IpiIntWd = 97|0x30000U, /**< ADC1_IPI_INT_WD output assigned to XBAR3_IN97 input. */ + kXBAR3_InputTpm1LptpmChTrigger0 = 98|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN98 input. */ + kXBAR3_InputTpm1LptpmChTrigger1 = 99|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN99 input. */ + kXBAR3_InputTpm1LptpmChTrigger2 = 100|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN100 input. */ + kXBAR3_InputTpm1LptpmChTrigger3 = 101|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN101 input. */ + kXBAR3_InputTpm1LptpmTrigger = 102|0x30000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR3_IN102 input. */ + kXBAR3_InputTpm2LptpmChTrigger0 = 103|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN103 input. */ + kXBAR3_InputTpm2LptpmChTrigger1 = 104|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN104 input. */ + kXBAR3_InputTpm2LptpmChTrigger2 = 105|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN105 input. */ + kXBAR3_InputTpm2LptpmChTrigger3 = 106|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN106 input. */ + kXBAR3_InputTpm2LptpmTrigger = 107|0x30000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR3_IN107 input. */ + kXBAR3_InputTpm3LptpmChTrigger0 = 108|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN108 input. */ + kXBAR3_InputTpm3LptpmChTrigger1 = 109|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN109 input. */ + kXBAR3_InputTpm3LptpmChTrigger2 = 110|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN110 input. */ + kXBAR3_InputTpm3LptpmChTrigger3 = 111|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN111 input. */ + kXBAR3_InputTpm3LptpmTrigger = 112|0x30000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR3_IN112 input. */ + kXBAR3_InputTpm4LptpmChTrigger0 = 113|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN113 input. */ + kXBAR3_InputTpm4LptpmChTrigger1 = 114|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN114 input. */ + kXBAR3_InputTpm4LptpmChTrigger2 = 115|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN115 input. */ + kXBAR3_InputTpm4LptpmChTrigger3 = 116|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN116 input. */ + kXBAR3_InputTpm4LptpmTrigger = 117|0x30000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR3_IN117 input. */ + kXBAR3_InputTpm5LptpmChTrigger0 = 118|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN118 input. */ + kXBAR3_InputTpm5LptpmChTrigger1 = 119|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN119 input. */ + kXBAR3_InputTpm5LptpmChTrigger2 = 120|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN120 input. */ + kXBAR3_InputTpm5LptpmChTrigger3 = 121|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN121 input. */ + kXBAR3_InputTpm5LptpmTrigger = 122|0x30000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR3_IN122 input. */ + kXBAR3_InputTpm6LptpmChTrigger0 = 123|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN123 input. */ + kXBAR3_InputTpm6LptpmChTrigger1 = 124|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN124 input. */ + kXBAR3_InputTpm6LptpmChTrigger2 = 125|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN125 input. */ + kXBAR3_InputTpm6LptpmChTrigger3 = 126|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN126 input. */ + kXBAR3_InputTpm6LptpmTrigger = 127|0x30000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR3_IN127 input. */ + kXBAR3_InputLptmr1LptimerTriggerDelay = 128|0x30000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN128 input. */ + kXBAR3_InputLptmr2LptimerTriggerDelay = 129|0x30000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN129 input. */ + kXBAR3_InputLogicLow2 = 130|0x30000U, /**< LOGIC_LOW2 output assigned to XBAR3_IN130 input. */ + kXBAR3_InputNetcTmr11588Pp1 = 131|0x30000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR3_IN131 input. */ + kXBAR3_InputNetcTmr11588Pp2 = 132|0x30000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR3_IN132 input. */ + kXBAR3_InputNetcTmr11588Pp3 = 133|0x30000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR3_IN133 input. */ + kXBAR3_InputNetcTmr11588Alarm1 = 134|0x30000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR3_IN134 input. */ + kXBAR3_InputNetcTmr11588Alarm2 = 135|0x30000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR3_IN135 input. */ + kXBAR3_InputNetcTmr21588Pp1 = 136|0x30000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR3_IN136 input. */ + kXBAR3_InputNetcTmr21588Pp2 = 137|0x30000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR3_IN137 input. */ + kXBAR3_InputNetcTmr21588Pp3 = 138|0x30000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR3_IN138 input. */ + kXBAR3_InputNetcTmr21588Alarm1 = 139|0x30000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR3_IN139 input. */ + kXBAR3_InputNetcTmr21588Alarm2 = 140|0x30000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR3_IN140 input. */ + kXBAR3_InputNetcTmr31588Pp1 = 141|0x30000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR3_IN141 input. */ + kXBAR3_InputNetcTmr31588Pp2 = 142|0x30000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR3_IN142 input. */ + kXBAR3_InputNetcTmr31588Pp3 = 143|0x30000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR3_IN143 input. */ + kXBAR3_InputNetcTmr31588Alarm1 = 144|0x30000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR3_IN144 input. */ + kXBAR3_InputNetcTmr31588Alarm2 = 145|0x30000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR3_IN145 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak0 = 146|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR3_IN146 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak1 = 147|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR3_IN147 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak2 = 148|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR3_IN148 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak3 = 149|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR3_IN149 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak0 = 150|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR3_IN150 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak1 = 151|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR3_IN151 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak2 = 152|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR3_IN152 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak3 = 153|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR3_IN153 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak0 = 154|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR3_IN154 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak1 = 155|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR3_IN155 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak2 = 156|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR3_IN156 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak3 = 157|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR3_IN157 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak0 = 158|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR3_IN158 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak1 = 159|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR3_IN159 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak2 = 160|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR3_IN160 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak3 = 161|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR3_IN161 input. */ + kXBAR3_InputSinc2PulseTrg0 = 162|0x30000U, /**< SINC2_PULSE_TRG0 output assigned to XBAR3_IN162 input. */ + kXBAR3_InputSinc2PulseTrg1 = 163|0x30000U, /**< SINC2_PULSE_TRG1 output assigned to XBAR3_IN163 input. */ + kXBAR3_InputSinc2PulseTrg2 = 164|0x30000U, /**< SINC2_PULSE_TRG2 output assigned to XBAR3_IN164 input. */ + kXBAR3_InputSinc2PulseTrg3 = 165|0x30000U, /**< SINC2_PULSE_TRG3 output assigned to XBAR3_IN165 input. */ + kXBAR3_InputSinc4PulseTrg0 = 166|0x30000U, /**< SINC4_PULSE_TRG0 output assigned to XBAR3_IN166 input. */ + kXBAR3_InputSinc4PulseTrg1 = 167|0x30000U, /**< SINC4_PULSE_TRG1 output assigned to XBAR3_IN167 input. */ + kXBAR3_InputSinc4PulseTrg2 = 168|0x30000U, /**< SINC4_PULSE_TRG2 output assigned to XBAR3_IN168 input. */ + kXBAR3_InputSinc4PulseTrg3 = 169|0x30000U, /**< SINC4_PULSE_TRG3 output assigned to XBAR3_IN169 input. */ + kXBAR3_InputEcatSyncOut0 = 170|0x30000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR3_IN170 input. */ + kXBAR3_InputEcatSyncOut1 = 171|0x30000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR3_IN171 input. */ + kXBAR3_InputFccuVfccuReactionsOut11 = 172|0x30000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR3_IN172 input. */ + kXBAR3_InputGpt1IppDoCmpout1 = 173|0x30000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR3_IN173 input. */ + kXBAR3_InputGpt1IppDoCmpout2 = 174|0x30000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR3_IN174 input. */ + kXBAR3_InputGpt1IppDoCmpout3 = 175|0x30000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR3_IN175 input. */ + kXBAR3_InputGpt2IppDoCmpout1 = 176|0x30000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR3_IN176 input. */ + kXBAR3_InputGpt2IppDoCmpout2 = 177|0x30000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR3_IN177 input. */ + kXBAR3_InputGpt2IppDoCmpout3 = 178|0x30000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR3_IN178 input. */ + kXBAR3_InputGpt3IppDoCmpout1 = 179|0x30000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR3_IN179 input. */ + kXBAR3_InputGpt3IppDoCmpout2 = 180|0x30000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR3_IN180 input. */ + kXBAR3_InputGpt3IppDoCmpout3 = 181|0x30000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR3_IN181 input. */ + kXBAR3_InputGpt4IppDoCmpout1 = 182|0x30000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR3_IN182 input. */ + kXBAR3_InputGpt4IppDoCmpout2 = 183|0x30000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR3_IN183 input. */ + kXBAR3_InputGpt4IppDoCmpout3 = 184|0x30000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR3_IN184 input. */ + kXBAR3_InputFlexio1FlexioTriggerOut0 = 185|0x30000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN185 input. */ + kXBAR3_InputFlexio2FlexioTriggerOut0 = 186|0x30000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN186 input. */ + kXBAR3_InputFlexio3FlexioTriggerOut0 = 187|0x30000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN187 input. */ + kXBAR3_InputFlexio4FlexioTriggerOut0 = 188|0x30000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN188 input. */ + kXBAR3_InputGpio1IpiIntRgpio0 = 189|0x30000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR3_IN189 input. */ + kXBAR3_InputGpio2IpiIntRgpio0 = 190|0x30000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR3_IN190 input. */ + kXBAR3_InputGpio3IpiIntRgpio0 = 191|0x30000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR3_IN191 input. */ + kXBAR3_InputGpio4IpiIntRgpio0 = 192|0x30000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR3_IN192 input. */ + kXBAR3_InputGpio5IpiIntRgpio0 = 193|0x30000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR3_IN193 input. */ + kXBAR3_InputGpio6IpiIntRgpio0 = 194|0x30000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR3_IN194 input. */ + kXBAR3_InputGpio7IpiIntRgpio0 = 195|0x30000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR3_IN195 input. */ + kXBAR3_InputCm33Txev = 196|0x30000U, /**< CM33_TXEV output assigned to XBAR3_IN196 input. */ + kXBAR3_InputCm33SyncTxev = 197|0x30000U, /**< CM33_SYNC_TXEV output assigned to XBAR3_IN197 input. */ + kXBAR3_InputEndat21SiN = 198|0x30000U, /**< ENDAT2_1_SI_N output assigned to XBAR3_IN198 input. */ + kXBAR3_InputEndat21TimerN = 199|0x30000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR3_IN199 input. */ + kXBAR3_InputEndat22SiN = 200|0x30000U, /**< ENDAT2_2_SI_N output assigned to XBAR3_IN200 input. */ + kXBAR3_InputEndat22TimerN = 201|0x30000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR3_IN201 input. */ + kXBAR3_InputBissEot = 202|0x30000U, /**< BISS_EOT output assigned to XBAR3_IN202 input. */ + kXBAR3_InputEnc2PosMatch0 = 203|0x30000U, /**< ENC2_POS_MATCH0 output assigned to XBAR3_IN203 input. */ + kXBAR3_InputEnc2PosMatch1 = 204|0x30000U, /**< ENC2_POS_MATCH1 output assigned to XBAR3_IN204 input. */ + kXBAR3_InputEnc2PosMatch2 = 205|0x30000U, /**< ENC2_POS_MATCH2 output assigned to XBAR3_IN205 input. */ + kXBAR3_InputEnc2PosMatch3 = 206|0x30000U, /**< ENC2_POS_MATCH3 output assigned to XBAR3_IN206 input. */ + kXBAR3_InputEnc2CompFlg0 = 207|0x30000U, /**< ENC2_COMP_FLG0 output assigned to XBAR3_IN207 input. */ + kXBAR3_InputEnc2CompFlg1 = 208|0x30000U, /**< ENC2_COMP_FLG1 output assigned to XBAR3_IN208 input. */ + kXBAR3_InputEnc2CompFlg2 = 209|0x30000U, /**< ENC2_COMP_FLG2 output assigned to XBAR3_IN209 input. */ + kXBAR3_InputEnc2CompFlg3 = 210|0x30000U, /**< ENC2_COMP_FLG3 output assigned to XBAR3_IN210 input. */ + kXBAR3_InputEnc2CntDn = 211|0x30000U, /**< ENC2_CNT_DN output assigned to XBAR3_IN211 input. */ + kXBAR3_InputEnc2CntUp = 212|0x30000U, /**< ENC2_CNT_UP output assigned to XBAR3_IN212 input. */ + kXBAR3_InputEnc2Dir = 213|0x30000U, /**< ENC2_DIR output assigned to XBAR3_IN213 input. */ + kXBAR3_InputEnc4PosMatch0 = 214|0x30000U, /**< ENC4_POS_MATCH0 output assigned to XBAR3_IN214 input. */ + kXBAR3_InputEnc4PosMatch1 = 215|0x30000U, /**< ENC4_POS_MATCH1 output assigned to XBAR3_IN215 input. */ + kXBAR3_InputEnc4PosMatch2 = 216|0x30000U, /**< ENC4_POS_MATCH2 output assigned to XBAR3_IN216 input. */ + kXBAR3_InputEnc4PosMatch3 = 217|0x30000U, /**< ENC4_POS_MATCH3 output assigned to XBAR3_IN217 input. */ + kXBAR3_InputEnc4CompFlg0 = 218|0x30000U, /**< ENC4_COMP_FLG0 output assigned to XBAR3_IN218 input. */ + kXBAR3_InputEnc4CompFlg1 = 219|0x30000U, /**< ENC4_COMP_FLG1 output assigned to XBAR3_IN219 input. */ + kXBAR3_InputEnc4CompFlg2 = 220|0x30000U, /**< ENC4_COMP_FLG2 output assigned to XBAR3_IN220 input. */ + kXBAR3_InputEnc4CompFlg3 = 221|0x30000U, /**< ENC4_COMP_FLG3 output assigned to XBAR3_IN221 input. */ + kXBAR3_InputEnc4CntDn = 222|0x30000U, /**< ENC4_CNT_DN output assigned to XBAR3_IN222 input. */ + kXBAR3_InputEnc4CntUp = 223|0x30000U, /**< ENC4_CNT_UP output assigned to XBAR3_IN223 input. */ + kXBAR3_InputEnc4Dir = 224|0x30000U, /**< ENC4_DIR output assigned to XBAR3_IN224 input. */ + kXBAR3_InputHiperface1FastPosRcvdEvt = 225|0x30000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR3_IN225 input. */ + kXBAR3_InputHiperface2FastPosRcvdEvt = 226|0x30000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR3_IN226 input. */ +} xbar_input_signal_t; + +typedef enum _xbar_output_signal +{ + kXBAR1_OutputEdma4IpdReq76 = 0|0x10000U, /**< XBAR1_OUT0 output assigned to EDMA4_IPD_REQ76 */ + kXBAR1_OutputEdma4IpdReq77 = 1|0x10000U, /**< XBAR1_OUT1 output assigned to EDMA4_IPD_REQ77 */ + kXBAR1_OutputEdma4IpdReq78 = 2|0x10000U, /**< XBAR1_OUT2 output assigned to EDMA4_IPD_REQ78 */ + kXBAR1_OutputEdma4IpdReq79 = 3|0x10000U, /**< XBAR1_OUT3 output assigned to EDMA4_IPD_REQ79 */ + kXBAR1_OutputIomuxXbarOut04 = 4|0x10000U, /**< XBAR1_OUT4 output assigned to IOMUX_XBAR_OUT04 */ + kXBAR1_OutputIomuxXbarOut05 = 5|0x10000U, /**< XBAR1_OUT5 output assigned to IOMUX_XBAR_OUT05 */ + kXBAR1_OutputIomuxXbarOut06 = 6|0x10000U, /**< XBAR1_OUT6 output assigned to IOMUX_XBAR_OUT06 */ + kXBAR1_OutputIomuxXbarOut07 = 7|0x10000U, /**< XBAR1_OUT7 output assigned to IOMUX_XBAR_OUT07 */ + kXBAR1_OutputIomuxXbarOut08 = 8|0x10000U, /**< XBAR1_OUT8 output assigned to IOMUX_XBAR_OUT08 */ + kXBAR1_OutputIomuxXbarOut09 = 9|0x10000U, /**< XBAR1_OUT9 output assigned to IOMUX_XBAR_OUT09 */ + kXBAR1_OutputIomuxXbarOut10 = 10|0x10000U, /**< XBAR1_OUT10 output assigned to IOMUX_XBAR_OUT10 */ + kXBAR1_OutputIomuxXbarOut11 = 11|0x10000U, /**< XBAR1_OUT11 output assigned to IOMUX_XBAR_OUT11 */ + kXBAR1_OutputIomuxXbarOut12 = 12|0x10000U, /**< XBAR1_OUT12 output assigned to IOMUX_XBAR_OUT12 */ + kXBAR1_OutputIomuxXbarOut13 = 13|0x10000U, /**< XBAR1_OUT13 output assigned to IOMUX_XBAR_OUT13 */ + kXBAR1_OutputIomuxXbarOut14 = 14|0x10000U, /**< XBAR1_OUT14 output assigned to IOMUX_XBAR_OUT14 */ + kXBAR1_OutputIomuxXbarOut15 = 15|0x10000U, /**< XBAR1_OUT15 output assigned to IOMUX_XBAR_OUT15 */ + kXBAR1_OutputIomuxXbarOut16 = 16|0x10000U, /**< XBAR1_OUT16 output assigned to IOMUX_XBAR_OUT16 */ + kXBAR1_OutputIomuxXbarOut17 = 17|0x10000U, /**< XBAR1_OUT17 output assigned to IOMUX_XBAR_OUT17 */ + kXBAR1_OutputIomuxXbarOut18 = 18|0x10000U, /**< XBAR1_OUT18 output assigned to IOMUX_XBAR_OUT18 */ + kXBAR1_OutputIomuxXbarOut19 = 19|0x10000U, /**< XBAR1_OUT19 output assigned to IOMUX_XBAR_OUT19 */ + kXBAR1_OutputIomuxXbarOut20 = 20|0x10000U, /**< XBAR1_OUT20 output assigned to IOMUX_XBAR_OUT20 */ + kXBAR1_OutputIomuxXbarOut21 = 21|0x10000U, /**< XBAR1_OUT21 output assigned to IOMUX_XBAR_OUT21 */ + kXBAR1_OutputIomuxXbarOut22 = 22|0x10000U, /**< XBAR1_OUT22 output assigned to IOMUX_XBAR_OUT22 */ + kXBAR1_OutputIomuxXbarOut23 = 23|0x10000U, /**< XBAR1_OUT23 output assigned to IOMUX_XBAR_OUT23 */ + kXBAR1_OutputIomuxXbarOut24 = 24|0x10000U, /**< XBAR1_OUT24 output assigned to IOMUX_XBAR_OUT24 */ + kXBAR1_OutputIomuxXbarOut25 = 25|0x10000U, /**< XBAR1_OUT25 output assigned to IOMUX_XBAR_OUT25 */ + kXBAR1_OutputIomuxXbarOut26 = 26|0x10000U, /**< XBAR1_OUT26 output assigned to IOMUX_XBAR_OUT26 */ + kXBAR1_OutputIomuxXbarOut27 = 27|0x10000U, /**< XBAR1_OUT27 output assigned to IOMUX_XBAR_OUT27 */ + kXBAR1_OutputIomuxXbarOut28 = 28|0x10000U, /**< XBAR1_OUT28 output assigned to IOMUX_XBAR_OUT28 */ + kXBAR1_OutputIomuxXbarOut29 = 29|0x10000U, /**< XBAR1_OUT29 output assigned to IOMUX_XBAR_OUT29 */ + kXBAR1_OutputIomuxXbarOut30 = 30|0x10000U, /**< XBAR1_OUT30 output assigned to IOMUX_XBAR_OUT30 */ + kXBAR1_OutputIomuxXbarOut31 = 31|0x10000U, /**< XBAR1_OUT31 output assigned to IOMUX_XBAR_OUT31 */ + kXBAR1_OutputIomuxXbarOut32 = 32|0x10000U, /**< XBAR1_OUT32 output assigned to IOMUX_XBAR_OUT32 */ + kXBAR1_OutputIomuxXbarOut33 = 33|0x10000U, /**< XBAR1_OUT33 output assigned to IOMUX_XBAR_OUT33 */ + kXBAR1_OutputIomuxXbarOut34 = 34|0x10000U, /**< XBAR1_OUT34 output assigned to IOMUX_XBAR_OUT34 */ + kXBAR1_OutputIomuxXbarOut35 = 35|0x10000U, /**< XBAR1_OUT35 output assigned to IOMUX_XBAR_OUT35 */ + kXBAR1_OutputIomuxXbarOut36 = 36|0x10000U, /**< XBAR1_OUT36 output assigned to IOMUX_XBAR_OUT36 */ + kXBAR1_OutputIomuxXbarOut37 = 37|0x10000U, /**< XBAR1_OUT37 output assigned to IOMUX_XBAR_OUT37 */ + kXBAR1_OutputIomuxXbarOut38 = 38|0x10000U, /**< XBAR1_OUT38 output assigned to IOMUX_XBAR_OUT38 */ + kXBAR1_OutputIomuxXbarOut39 = 39|0x10000U, /**< XBAR1_OUT39 output assigned to IOMUX_XBAR_OUT39 */ + kXBAR1_OutputIomuxXbarOut40 = 40|0x10000U, /**< XBAR1_OUT40 output assigned to IOMUX_XBAR_OUT40 */ + kXBAR1_OutputTriggerSyncAsyncIn0 = 41|0x10000U, /**< XBAR1_OUT41 output assigned to TRIGGER_SYNC_ASYNC_IN0 */ + kXBAR1_OutputTriggerSyncAsyncIn1 = 42|0x10000U, /**< XBAR1_OUT42 output assigned to TRIGGER_SYNC_ASYNC_IN1 */ + kXBAR1_OutputTriggerSyncAsyncIn2 = 43|0x10000U, /**< XBAR1_OUT43 output assigned to TRIGGER_SYNC_ASYNC_IN2 */ + kXBAR1_OutputTriggerSyncAsyncIn3 = 44|0x10000U, /**< XBAR1_OUT44 output assigned to TRIGGER_SYNC_ASYNC_IN3 */ + kXBAR1_OutputTriggerSyncAsyncIn4 = 45|0x10000U, /**< XBAR1_OUT45 output assigned to TRIGGER_SYNC_ASYNC_IN4 */ + kXBAR1_OutputTriggerSyncAsyncIn5 = 46|0x10000U, /**< XBAR1_OUT46 output assigned to TRIGGER_SYNC_ASYNC_IN5 */ + kXBAR1_OutputTriggerSyncAsyncIn6 = 47|0x10000U, /**< XBAR1_OUT47 output assigned to TRIGGER_SYNC_ASYNC_IN6 */ + kXBAR1_OutputTriggerSyncAsyncIn7 = 48|0x10000U, /**< XBAR1_OUT48 output assigned to TRIGGER_SYNC_ASYNC_IN7 */ + kXBAR1_OutputFlexpwm1Exta0 = 49|0x10000U, /**< XBAR1_OUT49 output assigned to FLEXPWM1_EXTA0 */ + kXBAR1_OutputFlexpwm1Exta1 = 50|0x10000U, /**< XBAR1_OUT50 output assigned to FLEXPWM1_EXTA1 */ + kXBAR1_OutputFlexpwm1Exta2 = 51|0x10000U, /**< XBAR1_OUT51 output assigned to FLEXPWM1_EXTA2 */ + kXBAR1_OutputFlexpwm1Exta3 = 52|0x10000U, /**< XBAR1_OUT52 output assigned to FLEXPWM1_EXTA3 */ + kXBAR1_OutputFlexpwm1ExtSync0 = 53|0x10000U, /**< XBAR1_OUT53 output assigned to FLEXPWM1_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm1ExtSync1 = 54|0x10000U, /**< XBAR1_OUT54 output assigned to FLEXPWM1_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm1ExtSync2 = 55|0x10000U, /**< XBAR1_OUT55 output assigned to FLEXPWM1_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm1ExtSync3 = 56|0x10000U, /**< XBAR1_OUT56 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm1ExtClk = 57|0x10000U, /**< XBAR1_OUT57 output assigned to FLEXPWM1_EXT_CLK */ + kXBAR1_OutputFlexpwm1IppIndFault0 = 58|0x10000U, /**< XBAR1_OUT58 output assigned to FLEXPWM1_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm1IppIndFault1 = 59|0x10000U, /**< XBAR1_OUT59 output assigned to FLEXPWM1_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm1IppIndFault2 = 60|0x10000U, /**< XBAR1_OUT60 output assigned to FLEXPWM1_IPP_IND_FAULT2 */ + kXBAR1_OutputFlexpwm1IppIndFault3 = 61|0x10000U, /**< XBAR1_OUT61 output assigned to FLEXPWM1_IPP_IND_FAULT3 */ + kXBAR1_OutputFlexpwm1ExtForce = 62|0x10000U, /**< XBAR1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */ + kXBAR1_OutputFlexpwm2Exta0 = 63|0x10000U, /**< XBAR1_OUT63 output assigned to FLEXPWM2_EXTA0 */ + kXBAR1_OutputFlexpwm2Exta1 = 64|0x10000U, /**< XBAR1_OUT64 output assigned to FLEXPWM2_EXTA1 */ + kXBAR1_OutputFlexpwm2Exta2 = 65|0x10000U, /**< XBAR1_OUT65 output assigned to FLEXPWM2_EXTA2 */ + kXBAR1_OutputFlexpwm2Exta3 = 66|0x10000U, /**< XBAR1_OUT66 output assigned to FLEXPWM2_EXTA3 */ + kXBAR1_OutputFlexpwm2ExtSync0 = 67|0x10000U, /**< XBAR1_OUT67 output assigned to FLEXPWM2_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm2ExtSync1 = 68|0x10000U, /**< XBAR1_OUT68 output assigned to FLEXPWM2_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm2ExtSync2 = 69|0x10000U, /**< XBAR1_OUT69 output assigned to FLEXPWM2_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm2ExtSync3 = 70|0x10000U, /**< XBAR1_OUT70 output assigned to FLEXPWM2_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm2ExtClk = 71|0x10000U, /**< XBAR1_OUT71 output assigned to FLEXPWM2_EXT_CLK */ + kXBAR1_OutputFlexpwm2IppIndFault0 = 72|0x10000U, /**< XBAR1_OUT72 output assigned to FLEXPWM2_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm2IppIndFault1 = 73|0x10000U, /**< XBAR1_OUT73 output assigned to FLEXPWM2_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm2ExtForce = 74|0x10000U, /**< XBAR1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */ + kXBAR1_OutputFlexpwm3Exta0 = 75|0x10000U, /**< XBAR1_OUT75 output assigned to FLEXPWM3_EXTA0 */ + kXBAR1_OutputFlexpwm3Exta1 = 76|0x10000U, /**< XBAR1_OUT76 output assigned to FLEXPWM3_EXTA1 */ + kXBAR1_OutputFlexpwm3Exta2 = 77|0x10000U, /**< XBAR1_OUT77 output assigned to FLEXPWM3_EXTA2 */ + kXBAR1_OutputFlexpwm3Exta3 = 78|0x10000U, /**< XBAR1_OUT78 output assigned to FLEXPWM3_EXTA3 */ + kXBAR1_OutputFlexpwm3ExtClk = 79|0x10000U, /**< XBAR1_OUT79 output assigned to FLEXPWM3_EXT_CLK */ + kXBAR1_OutputFlexpwm3ExtSync0 = 80|0x10000U, /**< XBAR1_OUT80 output assigned to FLEXPWM3_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm3ExtSync1 = 81|0x10000U, /**< XBAR1_OUT81 output assigned to FLEXPWM3_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm3ExtSync2 = 82|0x10000U, /**< XBAR1_OUT82 output assigned to FLEXPWM3_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm3ExtSync3 = 83|0x10000U, /**< XBAR1_OUT83 output assigned to FLEXPWM3_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm3IppIndFault0 = 84|0x10000U, /**< XBAR1_OUT84 output assigned to FLEXPWM3_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm3IppIndFault1 = 85|0x10000U, /**< XBAR1_OUT85 output assigned to FLEXPWM3_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm3ExtForce = 86|0x10000U, /**< XBAR1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */ + kXBAR1_OutputFlexpwm4ExtSync0 = 87|0x10000U, /**< XBAR1_OUT87 output assigned to FLEXPWM4_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm4ExtSync1 = 88|0x10000U, /**< XBAR1_OUT88 output assigned to FLEXPWM4_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm4ExtSync2 = 89|0x10000U, /**< XBAR1_OUT89 output assigned to FLEXPWM4_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm4ExtSync3 = 90|0x10000U, /**< XBAR1_OUT90 output assigned to FLEXPWM4_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm4IppIndFault0 = 91|0x10000U, /**< XBAR1_OUT91 output assigned to FLEXPWM4_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm4IppIndFault1 = 92|0x10000U, /**< XBAR1_OUT92 output assigned to FLEXPWM4_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm4ExtForce = 93|0x10000U, /**< XBAR1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */ + kXBAR1_OutputEnc1PhaseAInput = 94|0x10000U, /**< XBAR1_OUT94 output assigned to ENC1_PHASE_A_INPUT */ + kXBAR1_OutputEnc1PhaseBInput = 95|0x10000U, /**< XBAR1_OUT95 output assigned to ENC1_PHASE_B_INPUT */ + kXBAR1_OutputEnc1Index = 96|0x10000U, /**< XBAR1_OUT96 output assigned to ENC1_INDEX */ + kXBAR1_OutputEnc1Home = 97|0x10000U, /**< XBAR1_OUT97 output assigned to ENC1_HOME */ + kXBAR1_OutputEnc1Trigger = 98|0x10000U, /**< XBAR1_OUT98 output assigned to ENC1_TRIGGER */ + kXBAR1_OutputEnc2PhaseAInput = 99|0x10000U, /**< XBAR1_OUT99 output assigned to ENC2_PHASE_A_INPUT */ + kXBAR1_OutputEnc2PhaseBInput = 100|0x10000U, /**< XBAR1_OUT100 output assigned to ENC2_PHASE_B_INPUT */ + kXBAR1_OutputEnc2Index = 101|0x10000U, /**< XBAR1_OUT101 output assigned to ENC2_INDEX */ + kXBAR1_OutputEnc2Home = 102|0x10000U, /**< XBAR1_OUT102 output assigned to ENC2_HOME */ + kXBAR1_OutputEnc2Trigger = 103|0x10000U, /**< XBAR1_OUT103 output assigned to ENC2_TRIGGER */ + kXBAR1_OutputEnc3PhaseAInput = 104|0x10000U, /**< XBAR1_OUT104 output assigned to ENC3_PHASE_A_INPUT */ + kXBAR1_OutputEnc3PhaseBInput = 105|0x10000U, /**< XBAR1_OUT105 output assigned to ENC3_PHASE_B_INPUT */ + kXBAR1_OutputEnc3Index = 106|0x10000U, /**< XBAR1_OUT106 output assigned to ENC3_INDEX */ + kXBAR1_OutputEnc3Home = 107|0x10000U, /**< XBAR1_OUT107 output assigned to ENC3_HOME */ + kXBAR1_OutputEnc3Trigger = 108|0x10000U, /**< XBAR1_OUT108 output assigned to ENC3_TRIGGER */ + kXBAR1_OutputEnc4PhaseAInput = 109|0x10000U, /**< XBAR1_OUT109 output assigned to ENC4_PHASE_A_INPUT */ + kXBAR1_OutputEnc4PhaseBInput = 110|0x10000U, /**< XBAR1_OUT110 output assigned to ENC4_PHASE_B_INPUT */ + kXBAR1_OutputEnc4Index = 111|0x10000U, /**< XBAR1_OUT111 output assigned to ENC4_INDEX */ + kXBAR1_OutputEnc4Home = 112|0x10000U, /**< XBAR1_OUT112 output assigned to ENC4_HOME */ + kXBAR1_OutputEnc4Trigger = 113|0x10000U, /**< XBAR1_OUT113 output assigned to ENC4_TRIGGER */ + kXBAR1_OutputQtimer1Tmr0Input = 114|0x10000U, /**< XBAR1_OUT114 output assigned to QTIMER1_TMR0_INPUT */ + kXBAR1_OutputQtimer1Tmr1Input = 115|0x10000U, /**< XBAR1_OUT115 output assigned to QTIMER1_TMR1_INPUT */ + kXBAR1_OutputQtimer1Tmr2Input = 116|0x10000U, /**< XBAR1_OUT116 output assigned to QTIMER1_TMR2_INPUT */ + kXBAR1_OutputQtimer1Tmr3Input = 117|0x10000U, /**< XBAR1_OUT117 output assigned to QTIMER1_TMR3_INPUT */ + kXBAR1_OutputQtimer2Tmr0Input = 118|0x10000U, /**< XBAR1_OUT118 output assigned to QTIMER2_TMR0_INPUT */ + kXBAR1_OutputQtimer2Tmr1Input = 119|0x10000U, /**< XBAR1_OUT119 output assigned to QTIMER2_TMR1_INPUT */ + kXBAR1_OutputQtimer2Tmr2Input = 120|0x10000U, /**< XBAR1_OUT120 output assigned to QTIMER2_TMR2_INPUT */ + kXBAR1_OutputQtimer2Tmr3Input = 121|0x10000U, /**< XBAR1_OUT121 output assigned to QTIMER2_TMR3_INPUT */ + kXBAR1_OutputQtimer3Tmr0Input = 122|0x10000U, /**< XBAR1_OUT122 output assigned to QTIMER3_TMR0_INPUT */ + kXBAR1_OutputQtimer3Tmr1Input = 123|0x10000U, /**< XBAR1_OUT123 output assigned to QTIMER3_TMR1_INPUT */ + kXBAR1_OutputQtimer3Tmr2Input = 124|0x10000U, /**< XBAR1_OUT124 output assigned to QTIMER3_TMR2_INPUT */ + kXBAR1_OutputQtimer3Tmr3Input = 125|0x10000U, /**< XBAR1_OUT125 output assigned to QTIMER3_TMR3_INPUT */ + kXBAR1_OutputQtimer4Tmr0Input = 126|0x10000U, /**< XBAR1_OUT126 output assigned to QTIMER4_TMR0_INPUT */ + kXBAR1_OutputQtimer4Tmr1Input = 127|0x10000U, /**< XBAR1_OUT127 output assigned to QTIMER4_TMR1_INPUT */ + kXBAR1_OutputQtimer4Tmr2Input = 128|0x10000U, /**< XBAR1_OUT128 output assigned to QTIMER4_TMR2_INPUT */ + kXBAR1_OutputQtimer4Tmr3Input = 129|0x10000U, /**< XBAR1_OUT129 output assigned to QTIMER4_TMR3_INPUT */ + kXBAR1_OutputQtimer5Tmr0Input = 130|0x10000U, /**< XBAR1_OUT130 output assigned to QTIMER5_TMR0_INPUT */ + kXBAR1_OutputQtimer5Tmr1Input = 131|0x10000U, /**< XBAR1_OUT131 output assigned to QTIMER5_TMR1_INPUT */ + kXBAR1_OutputQtimer5Tmr2Input = 132|0x10000U, /**< XBAR1_OUT132 output assigned to QTIMER5_TMR2_INPUT */ + kXBAR1_OutputQtimer5Tmr3Input = 133|0x10000U, /**< XBAR1_OUT133 output assigned to QTIMER5_TMR3_INPUT */ + kXBAR1_OutputQtimer6Tmr0Input = 134|0x10000U, /**< XBAR1_OUT134 output assigned to QTIMER6_TMR0_INPUT */ + kXBAR1_OutputQtimer6Tmr1Input = 135|0x10000U, /**< XBAR1_OUT135 output assigned to QTIMER6_TMR1_INPUT */ + kXBAR1_OutputQtimer6Tmr2Input = 136|0x10000U, /**< XBAR1_OUT136 output assigned to QTIMER6_TMR2_INPUT */ + kXBAR1_OutputQtimer6Tmr3Input = 137|0x10000U, /**< XBAR1_OUT137 output assigned to QTIMER6_TMR3_INPUT */ + kXBAR1_OutputQtimer7Tmr0Input = 138|0x10000U, /**< XBAR1_OUT138 output assigned to QTIMER7_TMR0_INPUT */ + kXBAR1_OutputQtimer7Tmr1Input = 139|0x10000U, /**< XBAR1_OUT139 output assigned to QTIMER7_TMR1_INPUT */ + kXBAR1_OutputQtimer7Tmr2Input = 140|0x10000U, /**< XBAR1_OUT140 output assigned to QTIMER7_TMR2_INPUT */ + kXBAR1_OutputQtimer7Tmr3Input = 141|0x10000U, /**< XBAR1_OUT141 output assigned to QTIMER7_TMR3_INPUT */ + kXBAR1_OutputQtimer8Tmr0Input = 142|0x10000U, /**< XBAR1_OUT142 output assigned to QTIMER8_TMR0_INPUT */ + kXBAR1_OutputQtimer8Tmr1Input = 143|0x10000U, /**< XBAR1_OUT143 output assigned to QTIMER8_TMR1_INPUT */ + kXBAR1_OutputQtimer8Tmr2Input = 144|0x10000U, /**< XBAR1_OUT144 output assigned to QTIMER8_TMR2_INPUT */ + kXBAR1_OutputQtimer8Tmr3Input = 145|0x10000U, /**< XBAR1_OUT145 output assigned to QTIMER8_TMR3_INPUT */ + kXBAR1_OutputEwmEwmIn = 146|0x10000U, /**< XBAR1_OUT146 output assigned to EWM_EWM_IN */ + kXBAR1_OutputAnamixGlueTrgmuxInjectionTrg = 147|0x10000U, /**< XBAR1_OUT147 output assigned to ANAMIX_GLUE_TRGMUX_INJECTION_TRG */ + kXBAR1_OutputAnamixGlueTrgmuxStartTrg = 148|0x10000U, /**< XBAR1_OUT148 output assigned to ANAMIX_GLUE_TRGMUX_START_TRG */ + kXBAR1_OutputSinc1ExtTrigger0 = 149|0x10000U, /**< XBAR1_OUT149 output assigned to SINC1_EXT_TRIGGER0 */ + kXBAR1_OutputSinc1ExtTrigger1 = 150|0x10000U, /**< XBAR1_OUT150 output assigned to SINC1_EXT_TRIGGER1 */ + kXBAR1_OutputSinc1ExtTrigger2 = 151|0x10000U, /**< XBAR1_OUT151 output assigned to SINC1_EXT_TRIGGER2 */ + kXBAR1_OutputSinc1ExtTrigger3 = 152|0x10000U, /**< XBAR1_OUT152 output assigned to SINC1_EXT_TRIGGER3 */ + kXBAR1_OutputFlexio1FlexioTriggerIn0 = 153|0x10000U, /**< XBAR1_OUT153 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio1FlexioTriggerIn1 = 154|0x10000U, /**< XBAR1_OUT154 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio2FlexioTriggerIn0 = 155|0x10000U, /**< XBAR1_OUT155 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio2FlexioTriggerIn1 = 156|0x10000U, /**< XBAR1_OUT156 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio3FlexioTriggerIn0 = 157|0x10000U, /**< XBAR1_OUT157 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio3FlexioTriggerIn1 = 158|0x10000U, /**< XBAR1_OUT158 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio4FlexioTriggerIn0 = 159|0x10000U, /**< XBAR1_OUT159 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio4FlexioTriggerIn1 = 160|0x10000U, /**< XBAR1_OUT160 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputLpi2c1Lpi2cTrgInput = 161|0x10000U, /**< XBAR1_OUT161 output assigned to LPI2C1_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c2Lpi2cTrgInput = 162|0x10000U, /**< XBAR1_OUT162 output assigned to LPI2C2_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c3Lpi2cTrgInput = 163|0x10000U, /**< XBAR1_OUT163 output assigned to LPI2C3_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c4Lpi2cTrgInput = 164|0x10000U, /**< XBAR1_OUT164 output assigned to LPI2C4_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c5Lpi2cTrgInput = 165|0x10000U, /**< XBAR1_OUT165 output assigned to LPI2C5_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c6Lpi2cTrgInput = 166|0x10000U, /**< XBAR1_OUT166 output assigned to LPI2C6_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c7Lpi2cTrgInput = 167|0x10000U, /**< XBAR1_OUT167 output assigned to LPI2C7_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c8Lpi2cTrgInput = 168|0x10000U, /**< XBAR1_OUT168 output assigned to LPI2C8_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpspi1LpspiTrgInput = 169|0x10000U, /**< XBAR1_OUT169 output assigned to LPSPI1_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi2LpspiTrgInput = 170|0x10000U, /**< XBAR1_OUT170 output assigned to LPSPI2_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi3LpspiTrgInput = 171|0x10000U, /**< XBAR1_OUT171 output assigned to LPSPI3_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi4LpspiTrgInput = 172|0x10000U, /**< XBAR1_OUT172 output assigned to LPSPI4_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi5LpspiTrgInput = 173|0x10000U, /**< XBAR1_OUT173 output assigned to LPSPI5_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi6LpspiTrgInput = 174|0x10000U, /**< XBAR1_OUT174 output assigned to LPSPI6_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi7LpspiTrgInput = 175|0x10000U, /**< XBAR1_OUT175 output assigned to LPSPI7_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi8LpspiTrgInput = 176|0x10000U, /**< XBAR1_OUT176 output assigned to LPSPI8_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpuart1LpuartTrgInput = 177|0x10000U, /**< XBAR1_OUT177 output assigned to LPUART1_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart2LpuartTrgInput = 178|0x10000U, /**< XBAR1_OUT178 output assigned to LPUART2_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart3LpuartTrgInput = 179|0x10000U, /**< XBAR1_OUT179 output assigned to LPUART3_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart4LpuartTrgInput = 180|0x10000U, /**< XBAR1_OUT180 output assigned to LPUART4_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart5LpuartTrgInput = 181|0x10000U, /**< XBAR1_OUT181 output assigned to LPUART5_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart6LpuartTrgInput = 182|0x10000U, /**< XBAR1_OUT182 output assigned to LPUART6_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart7LpuartTrgInput = 183|0x10000U, /**< XBAR1_OUT183 output assigned to LPUART7_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart8LpuartTrgInput = 184|0x10000U, /**< XBAR1_OUT184 output assigned to LPUART8_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart9LpuartTrgInput = 185|0x10000U, /**< XBAR1_OUT185 output assigned to LPUART9_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart10LpuartTrgInput = 186|0x10000U, /**< XBAR1_OUT186 output assigned to LPUART10_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart11LpuartTrgInput = 187|0x10000U, /**< XBAR1_OUT187 output assigned to LPUART11_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart12LpuartTrgInput = 188|0x10000U, /**< XBAR1_OUT188 output assigned to LPUART12_LPUART_TRG_INPUT */ + kXBAR1_OutputLpit1LpitExtTrigIn0 = 189|0x10000U, /**< XBAR1_OUT189 output assigned to LPIT1_LPIT_EXT_TRIG_IN0 */ + kXBAR1_OutputLpit1LpitExtTrigIn1 = 190|0x10000U, /**< XBAR1_OUT190 output assigned to LPIT1_LPIT_EXT_TRIG_IN1 */ + kXBAR1_OutputLpit1LpitExtTrigIn2 = 191|0x10000U, /**< XBAR1_OUT191 output assigned to LPIT1_LPIT_EXT_TRIG_IN2 */ + kXBAR1_OutputLpit1LpitExtTrigIn3 = 192|0x10000U, /**< XBAR1_OUT192 output assigned to LPIT1_LPIT_EXT_TRIG_IN3 */ + kXBAR1_OutputTpm1LptpmTriggerIn0 = 193|0x10000U, /**< XBAR1_OUT193 output assigned to TPM1_LPTPM_TRIGGER_IN0 */ + kXBAR1_OutputTpm1LptpmTriggerIn1 = 194|0x10000U, /**< XBAR1_OUT194 output assigned to TPM1_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm2LptpmTriggerIn1 = 195|0x10000U, /**< XBAR1_OUT195 output assigned to TPM2_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm3LptpmTriggerIn1 = 196|0x10000U, /**< XBAR1_OUT196 output assigned to TPM3_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm1LptpmTriggerIn2 = 197|0x10000U, /**< XBAR1_OUT197 output assigned to TPM1_LPTPM_TRIGGER_IN2 */ + kXBAR1_OutputTpm1LptpmTriggerIn3 = 198|0x10000U, /**< XBAR1_OUT198 output assigned to TPM1_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm2LptpmTriggerIn3 = 199|0x10000U, /**< XBAR1_OUT199 output assigned to TPM2_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm3LptpmTriggerIn3 = 200|0x10000U, /**< XBAR1_OUT200 output assigned to TPM3_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm4LptpmTriggerIn0 = 201|0x10000U, /**< XBAR1_OUT201 output assigned to TPM4_LPTPM_TRIGGER_IN0 */ + kXBAR1_OutputTpm4LptpmTriggerIn1 = 202|0x10000U, /**< XBAR1_OUT202 output assigned to TPM4_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm5LptpmTriggerIn1 = 203|0x10000U, /**< XBAR1_OUT203 output assigned to TPM5_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm6LptpmTriggerIn1 = 204|0x10000U, /**< XBAR1_OUT204 output assigned to TPM6_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm4LptpmTriggerIn2 = 205|0x10000U, /**< XBAR1_OUT205 output assigned to TPM4_LPTPM_TRIGGER_IN2 */ + kXBAR1_OutputTpm4LptpmTriggerIn3 = 206|0x10000U, /**< XBAR1_OUT206 output assigned to TPM4_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm5LptpmTriggerIn3 = 207|0x10000U, /**< XBAR1_OUT207 output assigned to TPM5_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm6LptpmTriggerIn3 = 208|0x10000U, /**< XBAR1_OUT208 output assigned to TPM6_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputNetcTmr11588Trig1 = 209|0x10000U, /**< XBAR1_OUT209 output assigned to NETC_TMR1_1588_TRIG1 */ + kXBAR1_OutputNetcTmr11588Trig2 = 210|0x10000U, /**< XBAR1_OUT210 output assigned to NETC_TMR1_1588_TRIG2 */ + kXBAR1_OutputNetcTmr21588Trig1 = 211|0x10000U, /**< XBAR1_OUT211 output assigned to NETC_TMR2_1588_TRIG1 */ + kXBAR1_OutputNetcTmr21588Trig2 = 212|0x10000U, /**< XBAR1_OUT212 output assigned to NETC_TMR2_1588_TRIG2 */ + kXBAR1_OutputNetcTmr31588Trig1 = 213|0x10000U, /**< XBAR1_OUT213 output assigned to NETC_TMR3_1588_TRIG1 */ + kXBAR1_OutputNetcTmr31588Trig2 = 214|0x10000U, /**< XBAR1_OUT214 output assigned to NETC_TMR3_1588_TRIG2 */ + kXBAR1_OutputEnc1Icap1 = 215|0x10000U, /**< XBAR1_OUT215 output assigned to ENC1_ICAP1 */ + kXBAR1_OutputEnc1Icap2 = 216|0x10000U, /**< XBAR1_OUT216 output assigned to ENC1_ICAP2 */ + kXBAR1_OutputEnc1Icap3 = 217|0x10000U, /**< XBAR1_OUT217 output assigned to ENC1_ICAP3 */ + kXBAR1_OutputEnc2Icap1 = 218|0x10000U, /**< XBAR1_OUT218 output assigned to ENC2_ICAP1 */ + kXBAR1_OutputEnc2Icap2 = 219|0x10000U, /**< XBAR1_OUT219 output assigned to ENC2_ICAP2 */ + kXBAR1_OutputEnc2Icap3 = 220|0x10000U, /**< XBAR1_OUT220 output assigned to ENC2_ICAP3 */ + kXBAR1_OutputEnc3Icap1 = 221|0x10000U, /**< XBAR1_OUT221 output assigned to ENC3_ICAP1 */ + kXBAR1_OutputEnc3Icap2 = 222|0x10000U, /**< XBAR1_OUT222 output assigned to ENC3_ICAP2 */ + kXBAR1_OutputEnc3Icap3 = 223|0x10000U, /**< XBAR1_OUT223 output assigned to ENC3_ICAP3 */ + kXBAR1_OutputEnc4Icap1 = 224|0x10000U, /**< XBAR1_OUT224 output assigned to ENC4_ICAP1 */ + kXBAR1_OutputEnc4Icap2 = 225|0x10000U, /**< XBAR1_OUT225 output assigned to ENC4_ICAP2 */ + kXBAR1_OutputEnc4Icap3 = 226|0x10000U, /**< XBAR1_OUT226 output assigned to ENC4_ICAP3 */ + kXBAR1_OutputEcatLatchIn0 = 227|0x10000U, /**< XBAR1_OUT227 output assigned to ECAT_LATCH_IN0 */ + kXBAR1_OutputEcatLatchIn1 = 228|0x10000U, /**< XBAR1_OUT228 output assigned to ECAT_LATCH_IN1 */ + kXBAR1_OutputSafetyClkMonDutClk = 229|0x10000U, /**< XBAR1_OUT229 output assigned to SAFETY_CLK_MON_DUT_CLK */ + kXBAR1_OutputEndat21StrN = 230|0x10000U, /**< XBAR1_OUT230 output assigned to ENDAT2_1_STR_N */ + kXBAR1_OutputEndat21Ir6N = 231|0x10000U, /**< XBAR1_OUT231 output assigned to ENDAT2_1_IR6_N */ + kXBAR1_OutputEndat21Ir7N = 232|0x10000U, /**< XBAR1_OUT232 output assigned to ENDAT2_1_IR7_N */ + kXBAR1_OutputEndat22StrN = 233|0x10000U, /**< XBAR1_OUT233 output assigned to ENDAT2_2_STR_N */ + kXBAR1_OutputEndat22Ir6N = 234|0x10000U, /**< XBAR1_OUT234 output assigned to ENDAT2_2_IR6_N */ + kXBAR1_OutputEndat22Ir7N = 235|0x10000U, /**< XBAR1_OUT235 output assigned to ENDAT2_2_IR7_N */ + kXBAR1_OutputEndat3HwStrobe = 236|0x10000U, /**< XBAR1_OUT236 output assigned to ENDAT3_HW_STROBE */ + kXBAR1_OutputBissGetsens = 237|0x10000U, /**< XBAR1_OUT237 output assigned to BISS_GETSENS */ + kXBAR1_OutputSinc3ExtTrigger2 = 238|0x10000U, /**< XBAR1_OUT238 output assigned to SINC3_EXT_TRIGGER2 */ + kXBAR1_OutputSinc3ExtTrigger3 = 239|0x10000U, /**< XBAR1_OUT239 output assigned to SINC3_EXT_TRIGGER3 */ + kXBAR1_OutputHiperface1SyncXbar = 240|0x10000U, /**< XBAR1_OUT240 output assigned to HIPERFACE1_SYNC_XBAR */ + kXBAR1_OutputHiperface2SyncXbar = 241|0x10000U, /**< XBAR1_OUT241 output assigned to HIPERFACE2_SYNC_XBAR */ + kXBAR1_OutputTriggerSyncAsyncIn8 = 242|0x10000U, /**< XBAR1_OUT242 output assigned to TRIGGER_SYNC_ASYNC_IN8 */ + kXBAR1_OutputTriggerSyncAsyncIn9 = 243|0x10000U, /**< XBAR1_OUT243 output assigned to TRIGGER_SYNC_ASYNC_IN9 */ + kXBAR1_OutputTriggerSyncAsyncIn10 = 244|0x10000U, /**< XBAR1_OUT244 output assigned to TRIGGER_SYNC_ASYNC_IN10 */ + kXBAR1_OutputTriggerSyncAsyncIn11 = 245|0x10000U, /**< XBAR1_OUT245 output assigned to TRIGGER_SYNC_ASYNC_IN11 */ + kXBAR1_OutputTriggerSyncAsyncIn12 = 246|0x10000U, /**< XBAR1_OUT246 output assigned to TRIGGER_SYNC_ASYNC_IN12 */ + kXBAR1_OutputTriggerSyncAsyncIn13 = 247|0x10000U, /**< XBAR1_OUT247 output assigned to TRIGGER_SYNC_ASYNC_IN13 */ + kXBAR1_OutputTriggerSyncAsyncIn14 = 248|0x10000U, /**< XBAR1_OUT248 output assigned to TRIGGER_SYNC_ASYNC_IN14 */ + kXBAR1_OutputTriggerSyncAsyncIn15 = 249|0x10000U, /**< XBAR1_OUT249 output assigned to TRIGGER_SYNC_ASYNC_IN15 */ + kXBAR1_OutputSinc2ExtTrigger0 = 250|0x10000U, /**< XBAR1_OUT250 output assigned to SINC2_EXT_TRIGGER0 */ + kXBAR1_OutputSinc2ExtTrigger1 = 251|0x10000U, /**< XBAR1_OUT251 output assigned to SINC2_EXT_TRIGGER1 */ + kXBAR1_OutputSinc2ExtTrigger2 = 252|0x10000U, /**< XBAR1_OUT252 output assigned to SINC2_EXT_TRIGGER2 */ + kXBAR1_OutputSinc2ExtTrigger3 = 253|0x10000U, /**< XBAR1_OUT253 output assigned to SINC2_EXT_TRIGGER3 */ + kXBAR1_OutputSinc3ExtTrigger0 = 254|0x10000U, /**< XBAR1_OUT254 output assigned to SINC3_EXT_TRIGGER0 */ + kXBAR1_OutputSinc3ExtTrigger1 = 255|0x10000U, /**< XBAR1_OUT255 output assigned to SINC3_EXT_TRIGGER1 */ + kXBAR2_OutputAoi1In00 = 0|0x20000U, /**< XBAR2_OUT0 output assigned to AOI1_IN00 */ + kXBAR2_OutputAoi1In01 = 1|0x20000U, /**< XBAR2_OUT1 output assigned to AOI1_IN01 */ + kXBAR2_OutputAoi1In02 = 2|0x20000U, /**< XBAR2_OUT2 output assigned to AOI1_IN02 */ + kXBAR2_OutputAoi1In03 = 3|0x20000U, /**< XBAR2_OUT3 output assigned to AOI1_IN03 */ + kXBAR2_OutputAoi1In04 = 4|0x20000U, /**< XBAR2_OUT4 output assigned to AOI1_IN04 */ + kXBAR2_OutputAoi1In05 = 5|0x20000U, /**< XBAR2_OUT5 output assigned to AOI1_IN05 */ + kXBAR2_OutputAoi1In06 = 6|0x20000U, /**< XBAR2_OUT6 output assigned to AOI1_IN06 */ + kXBAR2_OutputAoi1In07 = 7|0x20000U, /**< XBAR2_OUT7 output assigned to AOI1_IN07 */ + kXBAR2_OutputAoi1In08 = 8|0x20000U, /**< XBAR2_OUT8 output assigned to AOI1_IN08 */ + kXBAR2_OutputAoi1In09 = 9|0x20000U, /**< XBAR2_OUT9 output assigned to AOI1_IN09 */ + kXBAR2_OutputAoi1In10 = 10|0x20000U, /**< XBAR2_OUT10 output assigned to AOI1_IN10 */ + kXBAR2_OutputAoi1In11 = 11|0x20000U, /**< XBAR2_OUT11 output assigned to AOI1_IN11 */ + kXBAR2_OutputAoi1In12 = 12|0x20000U, /**< XBAR2_OUT12 output assigned to AOI1_IN12 */ + kXBAR2_OutputAoi1In13 = 13|0x20000U, /**< XBAR2_OUT13 output assigned to AOI1_IN13 */ + kXBAR2_OutputAoi1In14 = 14|0x20000U, /**< XBAR2_OUT14 output assigned to AOI1_IN14 */ + kXBAR2_OutputAoi1In15 = 15|0x20000U, /**< XBAR2_OUT15 output assigned to AOI1_IN15 */ + kXBAR2_OutputAoi3In00 = 16|0x20000U, /**< XBAR2_OUT16 output assigned to AOI3_IN00 */ + kXBAR2_OutputAoi3In01 = 17|0x20000U, /**< XBAR2_OUT17 output assigned to AOI3_IN01 */ + kXBAR2_OutputAoi3In02 = 18|0x20000U, /**< XBAR2_OUT18 output assigned to AOI3_IN02 */ + kXBAR2_OutputAoi3In03 = 19|0x20000U, /**< XBAR2_OUT19 output assigned to AOI3_IN03 */ + kXBAR2_OutputAoi3In04 = 20|0x20000U, /**< XBAR2_OUT20 output assigned to AOI3_IN04 */ + kXBAR2_OutputAoi3In05 = 21|0x20000U, /**< XBAR2_OUT21 output assigned to AOI3_IN05 */ + kXBAR2_OutputAoi3In06 = 22|0x20000U, /**< XBAR2_OUT22 output assigned to AOI3_IN06 */ + kXBAR2_OutputAoi3In07 = 23|0x20000U, /**< XBAR2_OUT23 output assigned to AOI3_IN07 */ + kXBAR2_OutputAoi3In08 = 24|0x20000U, /**< XBAR2_OUT24 output assigned to AOI3_IN08 */ + kXBAR2_OutputAoi3In09 = 25|0x20000U, /**< XBAR2_OUT25 output assigned to AOI3_IN09 */ + kXBAR2_OutputAoi3In10 = 26|0x20000U, /**< XBAR2_OUT26 output assigned to AOI3_IN10 */ + kXBAR2_OutputAoi3In11 = 27|0x20000U, /**< XBAR2_OUT27 output assigned to AOI3_IN11 */ + kXBAR2_OutputAoi3In12 = 28|0x20000U, /**< XBAR2_OUT28 output assigned to AOI3_IN12 */ + kXBAR2_OutputAoi3In13 = 29|0x20000U, /**< XBAR2_OUT29 output assigned to AOI3_IN13 */ + kXBAR2_OutputAoi3In14 = 30|0x20000U, /**< XBAR2_OUT30 output assigned to AOI3_IN14 */ + kXBAR2_OutputAoi3In15 = 31|0x20000U, /**< XBAR2_OUT31 output assigned to AOI3_IN15 */ + kXBAR3_OutputAoi2In00 = 0|0x30000U, /**< XBAR3_OUT0 output assigned to AOI2_IN00 */ + kXBAR3_OutputAoi2In01 = 1|0x30000U, /**< XBAR3_OUT1 output assigned to AOI2_IN01 */ + kXBAR3_OutputAoi2In02 = 2|0x30000U, /**< XBAR3_OUT2 output assigned to AOI2_IN02 */ + kXBAR3_OutputAoi2In03 = 3|0x30000U, /**< XBAR3_OUT3 output assigned to AOI2_IN03 */ + kXBAR3_OutputAoi2In04 = 4|0x30000U, /**< XBAR3_OUT4 output assigned to AOI2_IN04 */ + kXBAR3_OutputAoi2In05 = 5|0x30000U, /**< XBAR3_OUT5 output assigned to AOI2_IN05 */ + kXBAR3_OutputAoi2In06 = 6|0x30000U, /**< XBAR3_OUT6 output assigned to AOI2_IN06 */ + kXBAR3_OutputAoi2In07 = 7|0x30000U, /**< XBAR3_OUT7 output assigned to AOI2_IN07 */ + kXBAR3_OutputAoi2In08 = 8|0x30000U, /**< XBAR3_OUT8 output assigned to AOI2_IN08 */ + kXBAR3_OutputAoi2In09 = 9|0x30000U, /**< XBAR3_OUT9 output assigned to AOI2_IN09 */ + kXBAR3_OutputAoi2In10 = 10|0x30000U, /**< XBAR3_OUT10 output assigned to AOI2_IN10 */ + kXBAR3_OutputAoi2In11 = 11|0x30000U, /**< XBAR3_OUT11 output assigned to AOI2_IN11 */ + kXBAR3_OutputAoi2In12 = 12|0x30000U, /**< XBAR3_OUT12 output assigned to AOI2_IN12 */ + kXBAR3_OutputAoi2In13 = 13|0x30000U, /**< XBAR3_OUT13 output assigned to AOI2_IN13 */ + kXBAR3_OutputAoi2In14 = 14|0x30000U, /**< XBAR3_OUT14 output assigned to AOI2_IN14 */ + kXBAR3_OutputAoi2In15 = 15|0x30000U, /**< XBAR3_OUT15 output assigned to AOI2_IN15 */ + kXBAR3_OutputAoi4In00 = 16|0x30000U, /**< XBAR3_OUT16 output assigned to AOI4_IN00 */ + kXBAR3_OutputAoi4In01 = 17|0x30000U, /**< XBAR3_OUT17 output assigned to AOI4_IN01 */ + kXBAR3_OutputAoi4In02 = 18|0x30000U, /**< XBAR3_OUT18 output assigned to AOI4_IN02 */ + kXBAR3_OutputAoi4In03 = 19|0x30000U, /**< XBAR3_OUT19 output assigned to AOI4_IN03 */ + kXBAR3_OutputAoi4In04 = 20|0x30000U, /**< XBAR3_OUT20 output assigned to AOI4_IN04 */ + kXBAR3_OutputAoi4In05 = 21|0x30000U, /**< XBAR3_OUT21 output assigned to AOI4_IN05 */ + kXBAR3_OutputAoi4In06 = 22|0x30000U, /**< XBAR3_OUT22 output assigned to AOI4_IN06 */ + kXBAR3_OutputAoi4In07 = 23|0x30000U, /**< XBAR3_OUT23 output assigned to AOI4_IN07 */ + kXBAR3_OutputAoi4In08 = 24|0x30000U, /**< XBAR3_OUT24 output assigned to AOI4_IN08 */ + kXBAR3_OutputAoi4In09 = 25|0x30000U, /**< XBAR3_OUT25 output assigned to AOI4_IN09 */ + kXBAR3_OutputAoi4In10 = 26|0x30000U, /**< XBAR3_OUT26 output assigned to AOI4_IN10 */ + kXBAR3_OutputAoi4In11 = 27|0x30000U, /**< XBAR3_OUT27 output assigned to AOI4_IN11 */ + kXBAR3_OutputAoi4In12 = 28|0x30000U, /**< XBAR3_OUT28 output assigned to AOI4_IN12 */ + kXBAR3_OutputAoi4In13 = 29|0x30000U, /**< XBAR3_OUT29 output assigned to AOI4_IN13 */ + kXBAR3_OutputAoi4In14 = 30|0x30000U, /**< XBAR3_OUT30 output assigned to AOI4_IN14 */ + kXBAR3_OutputAoi4In15 = 31|0x30000U, /**< XBAR3_OUT31 output assigned to AOI4_IN15 */ +} xbar_output_signal_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ADC - Peripheral instance base addresses */ /** Peripheral ADC base address */ #define ADC_BASE (0x44530000u) @@ -1656,6 +2748,16 @@ typedef enum IRQn { /** Array initializer of DCIF peripheral base pointers */ #define DCIF_BASE_PTRS { DCIF } +/* DDRC - Peripheral instance base addresses */ +/** Peripheral DDRC base address */ +#define DDRC_BASE (0x4E080000u) +/** Peripheral DDRC base pointer */ +#define DDRC ((DDRC_Type *)DDRC_BASE) +/** Array initializer of DDRC peripheral base addresses */ +#define DDRC_BASE_ADDRS { DDRC_BASE } +/** Array initializer of DDRC peripheral base pointers */ +#define DDRC_BASE_PTRS { DDRC } + /* DDR_BLK_CTRL_DDRMIX - Peripheral instance base addresses */ /** Peripheral BLK_CTRL_DDRMIX base address */ #define BLK_CTRL_DDRMIX_BASE (0x4E010000u) @@ -1680,16 +2782,6 @@ typedef enum IRQn { /** Array initializer of DDR_CMU peripheral base pointers */ #define DDR_CMU_BASE_PTRS { DDRC__CMU_1, DDRC__CMU_2 } -/* DDR_DDRC - Peripheral instance base addresses */ -/** Peripheral DDRC base address */ -#define DDRC_BASE (0x4E080000u) -/** Peripheral DDRC base pointer */ -#define DDRC ((DDR_DDRC_Type *)DDRC_BASE) -/** Array initializer of DDR_DDRC peripheral base addresses */ -#define DDR_DDRC_BASE_ADDRS { DDRC_BASE } -/** Array initializer of DDR_DDRC peripheral base pointers */ -#define DDR_DDRC_BASE_PTRS { DDRC } - /* DDR_LSTCU - Peripheral instance base addresses */ /** Peripheral DDRC__LSTCU base address */ #define DDRC__LSTCU_BASE (0x4E050000u) @@ -2131,10 +3223,22 @@ typedef enum IRQn { #define GPT1_BASE (0x446F0000u) /** Peripheral GPT1 base pointer */ #define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x428A0000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Peripheral GPT3 base address */ +#define GPT3_BASE (0x428B0000u) +/** Peripheral GPT3 base pointer */ +#define GPT3 ((GPT_Type *)GPT3_BASE) +/** Peripheral GPT4 base address */ +#define GPT4_BASE (0x428C0000u) +/** Peripheral GPT4 base pointer */ +#define GPT4 ((GPT_Type *)GPT4_BASE) /** Array initializer of GPT peripheral base addresses */ -#define GPT_BASE_ADDRS { GPT1_BASE } +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE } /** Array initializer of GPT peripheral base pointers */ -#define GPT_BASE_PTRS { GPT1 } +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4 } /* HIPERFACE - Peripheral instance base addresses */ /** Peripheral HIPERFACE1 base address */ @@ -2185,6 +3289,10 @@ typedef enum IRQn { #define SAI1_BASE (0x443B0000u) /** Peripheral SAI1 base pointer */ #define SAI1 ((I2S_Type *)SAI1_BASE) +/** Peripheral SAI2 base address */ +#define SAI2_BASE (0x42650000u) +/** Peripheral SAI2 base pointer */ +#define SAI2 ((I2S_Type *)SAI2_BASE) /** Peripheral SAI3 base address */ #define SAI3_BASE (0x42660000u) /** Peripheral SAI3 base pointer */ @@ -2194,12 +3302,12 @@ typedef enum IRQn { /** Peripheral SAI4 base pointer */ #define SAI4 ((I2S_Type *)SAI4_BASE) /** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { 0u, SAI1_BASE, 0u, SAI3_BASE, SAI4_BASE } +#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE } /** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, (I2S_Type *)0u, SAI3, SAI4 } +#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 } /** Interrupt vectors for the I2S peripheral type */ -#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, NotAvail_IRQn, SAI3_IRQn, SAI4_IRQn } -#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, NotAvail_IRQn, SAI3_IRQn, SAI4_IRQn } +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn } /* I3C - Peripheral instance base addresses */ /** Peripheral I3C1 base address */ @@ -4365,9 +5473,9 @@ typedef enum IRQn { /** Peripheral TMR8 base pointer */ #define TMR8 ((TMR_Type *)TMR8_BASE) /** Array initializer of TMR peripheral base addresses */ -#define TMR_BASE_ADDRS { TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } +#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } /** Array initializer of TMR peripheral base pointers */ -#define TMR_BASE_PTRS { TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } +#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } /* TMR_GLOBAL - Peripheral instance base addresses */ /** Peripheral NETC__ECAM_PCI_EMDIO0_BAR_0__TMR1_GLOBAL base address */ @@ -4581,34 +5689,6 @@ typedef enum IRQn { /** Array initializer of WAKEUP_ERM peripheral base pointers */ #define WAKEUP_ERM_BASE_PTRS { WAKEUP__ERM } -/* WAKEUP_GPT - Peripheral instance base addresses */ -/** Peripheral GPT2 base address */ -#define GPT2_BASE (0x428A0000u) -/** Peripheral GPT2 base pointer */ -#define GPT2 ((WAKEUP_GPT_Type *)GPT2_BASE) -/** Peripheral GPT3 base address */ -#define GPT3_BASE (0x428B0000u) -/** Peripheral GPT3 base pointer */ -#define GPT3 ((WAKEUP_GPT_Type *)GPT3_BASE) -/** Peripheral GPT4 base address */ -#define GPT4_BASE (0x428C0000u) -/** Peripheral GPT4 base pointer */ -#define GPT4 ((WAKEUP_GPT_Type *)GPT4_BASE) -/** Array initializer of WAKEUP_GPT peripheral base addresses */ -#define WAKEUP_GPT_BASE_ADDRS { 0u, 0u, GPT2_BASE, GPT3_BASE, GPT4_BASE } -/** Array initializer of WAKEUP_GPT peripheral base pointers */ -#define WAKEUP_GPT_BASE_PTRS { (WAKEUP_GPT_Type *)0u, (WAKEUP_GPT_Type *)0u, GPT2, GPT3, GPT4 } - -/* WAKEUP_SAI - Peripheral instance base addresses */ -/** Peripheral WAKEUP__SAI2 base address */ -#define WAKEUP__SAI2_BASE (0x42650000u) -/** Peripheral WAKEUP__SAI2 base pointer */ -#define WAKEUP__SAI2 ((WAKEUP_SAI_Type *)WAKEUP__SAI2_BASE) -/** Array initializer of WAKEUP_SAI peripheral base addresses */ -#define WAKEUP_SAI_BASE_ADDRS { WAKEUP__SAI2_BASE } -/** Array initializer of WAKEUP_SAI peripheral base pointers */ -#define WAKEUP_SAI_BASE_PTRS { WAKEUP__SAI2 } - /* WAKEUP_TCW - Peripheral instance base addresses */ /** Peripheral WAKEUP__TCW base address */ #define WAKEUP__TCW_BASE (0x42620000u) @@ -4903,3 +5983,4 @@ typedef enum #endif /* MIMX94398_CM7_CORE0_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0_features.h index 521542ff3..7d19bbb66 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2023-11-01 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -53,8 +53,8 @@ #define FSL_FEATURE_SOC_AXBS_COUNT (2) /* @brief BBNSM availability on the SoC. */ #define FSL_FEATURE_SOC_BBNSM_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (1) +/* @brief DDRC availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_COUNT (1) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (4) /* @brief EIM availability on the SoC. */ @@ -74,7 +74,7 @@ /* @brief I3C availability on the SoC. */ #define FSL_FEATURE_SOC_I3C_COUNT (2) /* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (3) +#define FSL_FEATURE_SOC_I2S_COUNT (4) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ @@ -132,6 +132,8 @@ #define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) /* @brief Self-test threshold counts of ADC. */ #define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) +/* @brief Has external trigger or not. */ +#define FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER (1) /* AOI module features */ @@ -229,6 +231,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* TMPSNS module features */ @@ -398,8 +404,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -428,6 +432,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* RGPIO module features */ @@ -457,14 +463,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -563,8 +569,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -607,6 +611,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -762,6 +770,18 @@ #define FSL_FEATURE_NETC_HAS_NO_XGMII (1) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (1) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (1) /* @brief NXP Switch port group support. */ @@ -854,18 +874,18 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ + (((x) == SAI2) ? (128) : \ (((x) == SAI3) ? (128) : \ - (((x) == SAI4) ? (128) : (-1)))) + (((x) == SAI4) ? (128) : (-1))))) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ (((x) == SAI1) ? (2) : \ + (((x) == SAI2) ? (1) : \ (((x) == SAI3) ? (1) : \ - (((x) == SAI4) ? (1) : (-1)))) + (((x) == SAI4) ? (1) : (-1))))) /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ @@ -890,14 +910,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1.h index f833442b3..94f3a5a5d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1.h @@ -30,8 +30,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: iMX943RM rev1 draftK -** Version: rev. 1.0, 2023-11-01 -** Build: b250115 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX94398_cm7_core1 @@ -66,14 +66,17 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX94398_cm7_core1.h - * @version 1.0 - * @date 2023-11-01 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX94398_cm7_core1 * * CMSIS Peripheral Access Layer for MIMX94398_cm7_core1 @@ -121,9 +124,9 @@ #include "PERI_CCMSRCGPC_TCU.h" #include "PERI_CORTEXA_TCU.h" #include "PERI_DCIF.h" +#include "PERI_DDRC.h" #include "PERI_DDR_BLK_CTRL_DDRMIX.h" #include "PERI_DDR_CMU.h" -#include "PERI_DDR_DDRC.h" #include "PERI_DDR_LSTCU.h" #include "PERI_DDR_TCU.h" #include "PERI_DISPLAY_BLK_CTRL_DISPLAYMIX.h" @@ -314,8 +317,6 @@ #include "PERI_WAKEUP_DMA_CRC.h" #include "PERI_WAKEUP_EIM.h" #include "PERI_WAKEUP_ERM.h" -#include "PERI_WAKEUP_GPT.h" -#include "PERI_WAKEUP_SAI.h" #include "PERI_WAKEUP_TCW.h" #include "PERI_WAKEUP_TRDC_MGR_MEGA.h" #include "PERI_WAKEUP_USDHC.h" diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1_COMMON.h index 7457ad4a6..10be12ecf 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1_COMMON.h @@ -30,8 +30,8 @@ ** Keil ARM C/C++ Compiler ** ** Reference manual: iMX943RM rev1 draftK -** Version: rev. 1.0, 2023-11-01 -** Build: b250217 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX94398_cm7_core1 @@ -66,14 +66,17 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! * @file MIMX94398_cm7_core1_COMMON.h - * @version 1.0 - * @date 2023-11-01 + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MIMX94398_cm7_core1 * * CMSIS Peripheral Access Layer for MIMX94398_cm7_core1 @@ -84,7 +87,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -1225,6 +1228,1095 @@ typedef enum IRQn { /* CPU specific feature definitions */ #include "MIMX94398_cm7_core1_features.h" +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +typedef enum _xbar_input_signal +{ + kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ + kXBAR1_InputLogicHigh = 1|0x10000U, /**< LOGIC_HIGH output assigned to XBAR1_IN1 input. */ + kXBAR1_InputLogicLow1 = 2|0x10000U, /**< LOGIC_LOW1 output assigned to XBAR1_IN2 input. */ + kXBAR1_InputLogicHigh1 = 3|0x10000U, /**< LOGIC_HIGH1 output assigned to XBAR1_IN3 input. */ + kXBAR1_InputIomuxXbarIn04 = 4|0x10000U, /**< IOMUX_XBAR_IN04 output assigned to XBAR1_IN4 input. */ + kXBAR1_InputIomuxXbarIn05 = 5|0x10000U, /**< IOMUX_XBAR_IN05 output assigned to XBAR1_IN5 input. */ + kXBAR1_InputIomuxXbarIn06 = 6|0x10000U, /**< IOMUX_XBAR_IN06 output assigned to XBAR1_IN6 input. */ + kXBAR1_InputIomuxXbarIn07 = 7|0x10000U, /**< IOMUX_XBAR_IN07 output assigned to XBAR1_IN7 input. */ + kXBAR1_InputIomuxXbarIn08 = 8|0x10000U, /**< IOMUX_XBAR_IN08 output assigned to XBAR1_IN8 input. */ + kXBAR1_InputIomuxXbarIn09 = 9|0x10000U, /**< IOMUX_XBAR_IN09 output assigned to XBAR1_IN9 input. */ + kXBAR1_InputIomuxXbarIn10 = 10|0x10000U, /**< IOMUX_XBAR_IN10 output assigned to XBAR1_IN10 input. */ + kXBAR1_InputIomuxXbarIn11 = 11|0x10000U, /**< IOMUX_XBAR_IN11 output assigned to XBAR1_IN11 input. */ + kXBAR1_InputIomuxXbarIn12 = 12|0x10000U, /**< IOMUX_XBAR_IN12 output assigned to XBAR1_IN12 input. */ + kXBAR1_InputIomuxXbarIn13 = 13|0x10000U, /**< IOMUX_XBAR_IN13 output assigned to XBAR1_IN13 input. */ + kXBAR1_InputIomuxXbarIn14 = 14|0x10000U, /**< IOMUX_XBAR_IN14 output assigned to XBAR1_IN14 input. */ + kXBAR1_InputIomuxXbarIn15 = 15|0x10000U, /**< IOMUX_XBAR_IN15 output assigned to XBAR1_IN15 input. */ + kXBAR1_InputIomuxXbarIn16 = 16|0x10000U, /**< IOMUX_XBAR_IN16 output assigned to XBAR1_IN16 input. */ + kXBAR1_InputIomuxXbarIn17 = 17|0x10000U, /**< IOMUX_XBAR_IN17 output assigned to XBAR1_IN17 input. */ + kXBAR1_InputIomuxXbarIn18 = 18|0x10000U, /**< IOMUX_XBAR_IN18 output assigned to XBAR1_IN18 input. */ + kXBAR1_InputIomuxXbarIn19 = 19|0x10000U, /**< IOMUX_XBAR_IN19 output assigned to XBAR1_IN19 input. */ + kXBAR1_InputIomuxXbarIn20 = 20|0x10000U, /**< IOMUX_XBAR_IN20 output assigned to XBAR1_IN20 input. */ + kXBAR1_InputIomuxXbarIn21 = 21|0x10000U, /**< IOMUX_XBAR_IN21 output assigned to XBAR1_IN21 input. */ + kXBAR1_InputIomuxXbarIn22 = 22|0x10000U, /**< IOMUX_XBAR_IN22 output assigned to XBAR1_IN22 input. */ + kXBAR1_InputIomuxXbarIn23 = 23|0x10000U, /**< IOMUX_XBAR_IN23 output assigned to XBAR1_IN23 input. */ + kXBAR1_InputIomuxXbarIn24 = 24|0x10000U, /**< IOMUX_XBAR_IN24 output assigned to XBAR1_IN24 input. */ + kXBAR1_InputIomuxXbarIn25 = 25|0x10000U, /**< IOMUX_XBAR_IN25 output assigned to XBAR1_IN25 input. */ + kXBAR1_InputIomuxXbarIn26 = 26|0x10000U, /**< IOMUX_XBAR_IN26 output assigned to XBAR1_IN26 input. */ + kXBAR1_InputIomuxXbarIn27 = 27|0x10000U, /**< IOMUX_XBAR_IN27 output assigned to XBAR1_IN27 input. */ + kXBAR1_InputIomuxXbarIn28 = 28|0x10000U, /**< IOMUX_XBAR_IN28 output assigned to XBAR1_IN28 input. */ + kXBAR1_InputIomuxXbarIn29 = 29|0x10000U, /**< IOMUX_XBAR_IN29 output assigned to XBAR1_IN29 input. */ + kXBAR1_InputIomuxXbarIn30 = 30|0x10000U, /**< IOMUX_XBAR_IN30 output assigned to XBAR1_IN30 input. */ + kXBAR1_InputIomuxXbarIn31 = 31|0x10000U, /**< IOMUX_XBAR_IN31 output assigned to XBAR1_IN31 input. */ + kXBAR1_InputIomuxXbarIn32 = 32|0x10000U, /**< IOMUX_XBAR_IN32 output assigned to XBAR1_IN32 input. */ + kXBAR1_InputIomuxXbarIn33 = 33|0x10000U, /**< IOMUX_XBAR_IN33 output assigned to XBAR1_IN33 input. */ + kXBAR1_InputIomuxXbarIn34 = 34|0x10000U, /**< IOMUX_XBAR_IN34 output assigned to XBAR1_IN34 input. */ + kXBAR1_InputIomuxXbarIn35 = 35|0x10000U, /**< IOMUX_XBAR_IN35 output assigned to XBAR1_IN35 input. */ + kXBAR1_InputIomuxXbarIn36 = 36|0x10000U, /**< IOMUX_XBAR_IN36 output assigned to XBAR1_IN36 input. */ + kXBAR1_InputIomuxXbarIn37 = 37|0x10000U, /**< IOMUX_XBAR_IN37 output assigned to XBAR1_IN37 input. */ + kXBAR1_InputIomuxXbarIn38 = 38|0x10000U, /**< IOMUX_XBAR_IN38 output assigned to XBAR1_IN38 input. */ + kXBAR1_InputIomuxXbarIn39 = 39|0x10000U, /**< IOMUX_XBAR_IN39 output assigned to XBAR1_IN39 input. */ + kXBAR1_InputIomuxXbarIn40 = 40|0x10000U, /**< IOMUX_XBAR_IN40 output assigned to XBAR1_IN40 input. */ + kXBAR1_InputIomuxXbarIn41 = 41|0x10000U, /**< IOMUX_XBAR_IN41 output assigned to XBAR1_IN41 input. */ + kXBAR1_InputIomuxXbarIn42 = 42|0x10000U, /**< IOMUX_XBAR_IN42 output assigned to XBAR1_IN42 input. */ + kXBAR1_InputIomuxXbarIn43 = 43|0x10000U, /**< IOMUX_XBAR_IN43 output assigned to XBAR1_IN43 input. */ + kXBAR1_InputIomuxXbarIn44 = 44|0x10000U, /**< IOMUX_XBAR_IN44 output assigned to XBAR1_IN44 input. */ + kXBAR1_InputIomuxXbarIn45 = 45|0x10000U, /**< IOMUX_XBAR_IN45 output assigned to XBAR1_IN45 input. */ + kXBAR1_InputIomuxXbarIn46 = 46|0x10000U, /**< IOMUX_XBAR_IN46 output assigned to XBAR1_IN46 input. */ + kXBAR1_InputIomuxXbarIn47 = 47|0x10000U, /**< IOMUX_XBAR_IN47 output assigned to XBAR1_IN47 input. */ + kXBAR1_InputIomuxXbarIn48 = 48|0x10000U, /**< IOMUX_XBAR_IN48 output assigned to XBAR1_IN48 input. */ + kXBAR1_InputQtimer1Timer0 = 49|0x10000U, /**< QTIMER1_TIMER0 output assigned to XBAR1_IN49 input. */ + kXBAR1_InputQtimer1Timer1 = 50|0x10000U, /**< QTIMER1_TIMER1 output assigned to XBAR1_IN50 input. */ + kXBAR1_InputQtimer1Timer2 = 51|0x10000U, /**< QTIMER1_TIMER2 output assigned to XBAR1_IN51 input. */ + kXBAR1_InputQtimer1Timer3 = 52|0x10000U, /**< QTIMER1_TIMER3 output assigned to XBAR1_IN52 input. */ + kXBAR1_InputQtimer2Timer0 = 53|0x10000U, /**< QTIMER2_TIMER0 output assigned to XBAR1_IN53 input. */ + kXBAR1_InputQtimer2Timer1 = 54|0x10000U, /**< QTIMER2_TIMER1 output assigned to XBAR1_IN54 input. */ + kXBAR1_InputQtimer2Timer2 = 55|0x10000U, /**< QTIMER2_TIMER2 output assigned to XBAR1_IN55 input. */ + kXBAR1_InputQtimer2Timer3 = 56|0x10000U, /**< QTIMER2_TIMER3 output assigned to XBAR1_IN56 input. */ + kXBAR1_InputQtimer3Timer0 = 57|0x10000U, /**< QTIMER3_TIMER0 output assigned to XBAR1_IN57 input. */ + kXBAR1_InputQtimer3Timer1 = 58|0x10000U, /**< QTIMER3_TIMER1 output assigned to XBAR1_IN58 input. */ + kXBAR1_InputQtimer3Timer2 = 59|0x10000U, /**< QTIMER3_TIMER2 output assigned to XBAR1_IN59 input. */ + kXBAR1_InputQtimer3Timer3 = 60|0x10000U, /**< QTIMER3_TIMER3 output assigned to XBAR1_IN60 input. */ + kXBAR1_InputQtimer4Timer0 = 61|0x10000U, /**< QTIMER4_TIMER0 output assigned to XBAR1_IN61 input. */ + kXBAR1_InputQtimer4Timer1 = 62|0x10000U, /**< QTIMER4_TIMER1 output assigned to XBAR1_IN62 input. */ + kXBAR1_InputQtimer4Timer2 = 63|0x10000U, /**< QTIMER4_TIMER2 output assigned to XBAR1_IN63 input. */ + kXBAR1_InputQtimer4Timer3 = 64|0x10000U, /**< QTIMER4_TIMER3 output assigned to XBAR1_IN64 input. */ + kXBAR1_InputQtimer5Timer0 = 65|0x10000U, /**< QTIMER5_TIMER0 output assigned to XBAR1_IN65 input. */ + kXBAR1_InputQtimer5Timer1 = 66|0x10000U, /**< QTIMER5_TIMER1 output assigned to XBAR1_IN66 input. */ + kXBAR1_InputQtimer5Timer2 = 67|0x10000U, /**< QTIMER5_TIMER2 output assigned to XBAR1_IN67 input. */ + kXBAR1_InputQtimer5Timer3 = 68|0x10000U, /**< QTIMER5_TIMER3 output assigned to XBAR1_IN68 input. */ + kXBAR1_InputQtimer6Timer0 = 69|0x10000U, /**< QTIMER6_TIMER0 output assigned to XBAR1_IN69 input. */ + kXBAR1_InputQtimer6Timer1 = 70|0x10000U, /**< QTIMER6_TIMER1 output assigned to XBAR1_IN70 input. */ + kXBAR1_InputQtimer6Timer2 = 71|0x10000U, /**< QTIMER6_TIMER2 output assigned to XBAR1_IN71 input. */ + kXBAR1_InputQtimer6Timer3 = 72|0x10000U, /**< QTIMER6_TIMER3 output assigned to XBAR1_IN72 input. */ + kXBAR1_InputQtimer7Timer0 = 73|0x10000U, /**< QTIMER7_TIMER0 output assigned to XBAR1_IN73 input. */ + kXBAR1_InputQtimer7Timer1 = 74|0x10000U, /**< QTIMER7_TIMER1 output assigned to XBAR1_IN74 input. */ + kXBAR1_InputQtimer7Timer2 = 75|0x10000U, /**< QTIMER7_TIMER2 output assigned to XBAR1_IN75 input. */ + kXBAR1_InputQtimer7Timer3 = 76|0x10000U, /**< QTIMER7_TIMER3 output assigned to XBAR1_IN76 input. */ + kXBAR1_InputQtimer8Timer0 = 77|0x10000U, /**< QTIMER8_TIMER0 output assigned to XBAR1_IN77 input. */ + kXBAR1_InputQtimer8Timer1 = 78|0x10000U, /**< QTIMER8_TIMER1 output assigned to XBAR1_IN78 input. */ + kXBAR1_InputQtimer8Timer2 = 79|0x10000U, /**< QTIMER8_TIMER2 output assigned to XBAR1_IN79 input. */ + kXBAR1_InputQtimer8Timer3 = 80|0x10000U, /**< QTIMER8_TIMER3 output assigned to XBAR1_IN80 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger0 = 81|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR1_IN81 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger0 = 82|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER0 output assigned to XBAR1_IN82 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger1 = 83|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR1_IN83 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger1 = 84|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER1 output assigned to XBAR1_IN84 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger2 = 85|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR1_IN85 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger2 = 86|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER2 output assigned to XBAR1_IN86 input. */ + kXBAR1_InputFlexpwm1Mux0Trigger3 = 87|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR1_IN87 input. */ + kXBAR1_InputFlexpwm1Mux1Trigger3 = 88|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER3 output assigned to XBAR1_IN88 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger0 = 89|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR1_IN89 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger0 = 90|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER0 output assigned to XBAR1_IN90 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger1 = 91|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR1_IN91 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger1 = 92|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER1 output assigned to XBAR1_IN92 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger2 = 93|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR1_IN93 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger2 = 94|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER2 output assigned to XBAR1_IN94 input. */ + kXBAR1_InputFlexpwm2Mux0Trigger3 = 95|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR1_IN95 input. */ + kXBAR1_InputFlexpwm2Mux1Trigger3 = 96|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER3 output assigned to XBAR1_IN96 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger0 = 97|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR1_IN97 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger0 = 98|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER0 output assigned to XBAR1_IN98 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger1 = 99|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR1_IN99 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger1 = 100|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER1 output assigned to XBAR1_IN100 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger2 = 101|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR1_IN101 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger2 = 102|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER2 output assigned to XBAR1_IN102 input. */ + kXBAR1_InputFlexpwm3Mux0Trigger3 = 103|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR1_IN103 input. */ + kXBAR1_InputFlexpwm3Mux1Trigger3 = 104|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER3 output assigned to XBAR1_IN104 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger0 = 105|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR1_IN105 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger0 = 106|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER0 output assigned to XBAR1_IN106 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger1 = 107|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR1_IN107 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger1 = 108|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER1 output assigned to XBAR1_IN108 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger2 = 109|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR1_IN109 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger2 = 110|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER2 output assigned to XBAR1_IN110 input. */ + kXBAR1_InputFlexpwm4Mux0Trigger3 = 111|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR1_IN111 input. */ + kXBAR1_InputFlexpwm4Mux1Trigger3 = 112|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER3 output assigned to XBAR1_IN112 input. */ + kXBAR1_InputLpit1LpitTrigOut0 = 113|0x10000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR1_IN113 input. */ + kXBAR1_InputLpit1LpitTrigOut1 = 114|0x10000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR1_IN114 input. */ + kXBAR1_InputLpit1LpitTrigOut2 = 115|0x10000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR1_IN115 input. */ + kXBAR1_InputLpit1LpitTrigOut3 = 116|0x10000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR1_IN116 input. */ + kXBAR1_InputLpit2LpitTrigOut0 = 117|0x10000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR1_IN117 input. */ + kXBAR1_InputLpit2LpitTrigOut1 = 118|0x10000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR1_IN118 input. */ + kXBAR1_InputLpit2LpitTrigOut2 = 119|0x10000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR1_IN119 input. */ + kXBAR1_InputLpit2LpitTrigOut3 = 120|0x10000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR1_IN120 input. */ + kXBAR1_InputLpit3LpitTrigOut0 = 121|0x10000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR1_IN121 input. */ + kXBAR1_InputLpit3LpitTrigOut1 = 122|0x10000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR1_IN122 input. */ + kXBAR1_InputLpit3LpitTrigOut2 = 123|0x10000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR1_IN123 input. */ + kXBAR1_InputLpit3LpitTrigOut3 = 124|0x10000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR1_IN124 input. */ + kXBAR1_InputTriggerSyncSyncOut0 = 125|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT0 output assigned to XBAR1_IN125 input. */ + kXBAR1_InputTriggerSyncSyncOut1 = 126|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT1 output assigned to XBAR1_IN126 input. */ + kXBAR1_InputTriggerSyncSyncOut2 = 127|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT2 output assigned to XBAR1_IN127 input. */ + kXBAR1_InputTriggerSyncSyncOut3 = 128|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT3 output assigned to XBAR1_IN128 input. */ + kXBAR1_InputEdma2DmaTriggerOut0 = 129|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN129 input. */ + kXBAR1_InputEdma2DmaTriggerOut1 = 130|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN130 input. */ + kXBAR1_InputEdma2DmaTriggerOut2 = 131|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN131 input. */ + kXBAR1_InputEdma2DmaTriggerOut3 = 132|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN132 input. */ + kXBAR1_InputEdma2DmaTriggerOut4 = 133|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN133 input. */ + kXBAR1_InputEdma2DmaTriggerOut5 = 134|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN134 input. */ + kXBAR1_InputEdma2DmaTriggerOut6 = 135|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN135 input. */ + kXBAR1_InputEdma2DmaTriggerOut7 = 136|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN136 input. */ + kXBAR1_InputEdma1DmaTriggerOut0 = 137|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN137 input. */ + kXBAR1_InputEdma1DmaTriggerOut1 = 138|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN138 input. */ + kXBAR1_InputEdma1DmaTriggerOut2 = 139|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN139 input. */ + kXBAR1_InputEdma1DmaTriggerOut3 = 140|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN140 input. */ + kXBAR1_InputEdma1DmaTriggerOut4 = 141|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN141 input. */ + kXBAR1_InputEdma1DmaTriggerOut5 = 142|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN142 input. */ + kXBAR1_InputEdma1DmaTriggerOut6 = 143|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN143 input. */ + kXBAR1_InputEdma1DmaTriggerOut7 = 144|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN144 input. */ + kXBAR1_InputEdma3DmaTriggerOut0 = 145|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN145 input. */ + kXBAR1_InputEdma3DmaTriggerOut1 = 146|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN146 input. */ + kXBAR1_InputEdma3DmaTriggerOut2 = 147|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN147 input. */ + kXBAR1_InputEdma3DmaTriggerOut3 = 148|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN148 input. */ + kXBAR1_InputEdma3DmaTriggerOut4 = 149|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN149 input. */ + kXBAR1_InputEdma3DmaTriggerOut5 = 150|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN150 input. */ + kXBAR1_InputEdma3DmaTriggerOut6 = 151|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN151 input. */ + kXBAR1_InputEdma3DmaTriggerOut7 = 152|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN152 input. */ + kXBAR1_InputEdma4DmaTriggerOut0 = 153|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN153 input. */ + kXBAR1_InputEdma4DmaTriggerOut1 = 154|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN154 input. */ + kXBAR1_InputEdma4DmaTriggerOut2 = 155|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN155 input. */ + kXBAR1_InputEdma4DmaTriggerOut3 = 156|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN156 input. */ + kXBAR1_InputEdma4DmaTriggerOut4 = 157|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN157 input. */ + kXBAR1_InputEdma4DmaTriggerOut5 = 158|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN158 input. */ + kXBAR1_InputEdma4DmaTriggerOut6 = 159|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN159 input. */ + kXBAR1_InputEdma4DmaTriggerOut7 = 160|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN160 input. */ + kXBAR1_InputAdc1IpiIntEoc = 161|0x10000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR1_IN161 input. */ + kXBAR1_InputAdc1IpiIntWd = 162|0x10000U, /**< ADC1_IPI_INT_WD output assigned to XBAR1_IN162 input. */ + kXBAR1_InputTpm1LptpmChTrigger0 = 163|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN163 input. */ + kXBAR1_InputTpm1LptpmChTrigger1 = 164|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN164 input. */ + kXBAR1_InputTpm1LptpmChTrigger2 = 165|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN165 input. */ + kXBAR1_InputTpm1LptpmChTrigger3 = 166|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN166 input. */ + kXBAR1_InputTpm1LptpmTrigger = 167|0x10000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR1_IN167 input. */ + kXBAR1_InputTpm2LptpmChTrigger0 = 168|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN168 input. */ + kXBAR1_InputTpm2LptpmChTrigger1 = 169|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN169 input. */ + kXBAR1_InputTpm2LptpmChTrigger2 = 170|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN170 input. */ + kXBAR1_InputTpm2LptpmChTrigger3 = 171|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN171 input. */ + kXBAR1_InputTpm2LptpmTrigger = 172|0x10000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR1_IN172 input. */ + kXBAR1_InputTpm3LptpmChTrigger0 = 173|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN173 input. */ + kXBAR1_InputTpm3LptpmChTrigger1 = 174|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN174 input. */ + kXBAR1_InputTpm3LptpmChTrigger2 = 175|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN175 input. */ + kXBAR1_InputTpm3LptpmChTrigger3 = 176|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN176 input. */ + kXBAR1_InputTpm3LptpmTrigger = 177|0x10000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR1_IN177 input. */ + kXBAR1_InputTpm4LptpmChTrigger0 = 178|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN178 input. */ + kXBAR1_InputTpm4LptpmChTrigger1 = 179|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN179 input. */ + kXBAR1_InputTpm4LptpmChTrigger2 = 180|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN180 input. */ + kXBAR1_InputTpm4LptpmChTrigger3 = 181|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN181 input. */ + kXBAR1_InputTpm4LptpmTrigger = 182|0x10000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR1_IN182 input. */ + kXBAR1_InputTpm5LptpmChTrigger0 = 183|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN183 input. */ + kXBAR1_InputTpm5LptpmChTrigger1 = 184|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN184 input. */ + kXBAR1_InputTpm5LptpmChTrigger2 = 185|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN185 input. */ + kXBAR1_InputTpm5LptpmChTrigger3 = 186|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN186 input. */ + kXBAR1_InputTpm5LptpmTrigger = 187|0x10000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR1_IN187 input. */ + kXBAR1_InputTpm6LptpmChTrigger0 = 188|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN188 input. */ + kXBAR1_InputTpm6LptpmChTrigger1 = 189|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN189 input. */ + kXBAR1_InputTpm6LptpmChTrigger2 = 190|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN190 input. */ + kXBAR1_InputTpm6LptpmChTrigger3 = 191|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN191 input. */ + kXBAR1_InputTpm6LptpmTrigger = 192|0x10000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR1_IN192 input. */ + kXBAR1_InputLptmr1LptimerTriggerDelay = 193|0x10000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN193 input. */ + kXBAR1_InputLptmr2LptimerTriggerDelay = 194|0x10000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN194 input. */ + kXBAR1_InputLogicLow2 = 195|0x10000U, /**< LOGIC_LOW2 output assigned to XBAR1_IN195 input. */ + kXBAR1_InputNetcTmr11588Pp1 = 196|0x10000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR1_IN196 input. */ + kXBAR1_InputNetcTmr11588Pp2 = 197|0x10000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR1_IN197 input. */ + kXBAR1_InputNetcTmr11588Pp3 = 198|0x10000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR1_IN198 input. */ + kXBAR1_InputNetcTmr11588Alarm1 = 199|0x10000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR1_IN199 input. */ + kXBAR1_InputNetcTmr11588Alarm2 = 200|0x10000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR1_IN200 input. */ + kXBAR1_InputNetcTmr21588Pp1 = 201|0x10000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR1_IN201 input. */ + kXBAR1_InputNetcTmr21588Pp2 = 202|0x10000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR1_IN202 input. */ + kXBAR1_InputNetcTmr21588Pp3 = 203|0x10000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR1_IN203 input. */ + kXBAR1_InputNetcTmr21588Alarm1 = 204|0x10000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR1_IN204 input. */ + kXBAR1_InputNetcTmr21588Alarm2 = 205|0x10000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR1_IN205 input. */ + kXBAR1_InputNetcTmr31588Pp1 = 206|0x10000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR1_IN206 input. */ + kXBAR1_InputNetcTmr31588Pp2 = 207|0x10000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR1_IN207 input. */ + kXBAR1_InputNetcTmr31588Pp3 = 208|0x10000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR1_IN208 input. */ + kXBAR1_InputNetcTmr31588Alarm1 = 209|0x10000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR1_IN209 input. */ + kXBAR1_InputNetcTmr31588Alarm2 = 210|0x10000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR1_IN210 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak0 = 211|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR1_IN211 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak1 = 212|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR1_IN212 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak2 = 213|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR1_IN213 input. */ + kXBAR1_InputSincFilterGlue1IppDoBreak3 = 214|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR1_IN214 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak0 = 215|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR1_IN215 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak1 = 216|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR1_IN216 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak2 = 217|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR1_IN217 input. */ + kXBAR1_InputSincFilterGlue2IppDoBreak3 = 218|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR1_IN218 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak0 = 219|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR1_IN219 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak1 = 220|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR1_IN220 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak2 = 221|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR1_IN221 input. */ + kXBAR1_InputSincFilterGlue3IppDoBreak3 = 222|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR1_IN222 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak0 = 223|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR1_IN223 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak1 = 224|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR1_IN224 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak2 = 225|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR1_IN225 input. */ + kXBAR1_InputSincFilterGlue4IppDoBreak3 = 226|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR1_IN226 input. */ + kXBAR1_InputAoi1AoiOut0 = 227|0x10000U, /**< AOI1_AOI_OUT0 output assigned to XBAR1_IN227 input. */ + kXBAR1_InputAoi1AoiOut1 = 228|0x10000U, /**< AOI1_AOI_OUT1 output assigned to XBAR1_IN228 input. */ + kXBAR1_InputAoi1AoiOut2 = 229|0x10000U, /**< AOI1_AOI_OUT2 output assigned to XBAR1_IN229 input. */ + kXBAR1_InputAoi1AoiOut3 = 230|0x10000U, /**< AOI1_AOI_OUT3 output assigned to XBAR1_IN230 input. */ + kXBAR1_InputAoi2AoiOut0 = 231|0x10000U, /**< AOI2_AOI_OUT0 output assigned to XBAR1_IN231 input. */ + kXBAR1_InputAoi2AoiOut1 = 232|0x10000U, /**< AOI2_AOI_OUT1 output assigned to XBAR1_IN232 input. */ + kXBAR1_InputAoi2AoiOut2 = 233|0x10000U, /**< AOI2_AOI_OUT2 output assigned to XBAR1_IN233 input. */ + kXBAR1_InputAoi2AoiOut3 = 234|0x10000U, /**< AOI2_AOI_OUT3 output assigned to XBAR1_IN234 input. */ + kXBAR1_InputTriggerSyncSyncOut4 = 235|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT4 output assigned to XBAR1_IN235 input. */ + kXBAR1_InputTriggerSyncSyncOut5 = 236|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT5 output assigned to XBAR1_IN236 input. */ + kXBAR1_InputTriggerSyncSyncOut6 = 237|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT6 output assigned to XBAR1_IN237 input. */ + kXBAR1_InputTriggerSyncSyncOut7 = 238|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT7 output assigned to XBAR1_IN238 input. */ + kXBAR1_InputAoi3AoiOut0 = 239|0x10000U, /**< AOI3_AOI_OUT0 output assigned to XBAR1_IN239 input. */ + kXBAR1_InputAoi3AoiOut1 = 240|0x10000U, /**< AOI3_AOI_OUT1 output assigned to XBAR1_IN240 input. */ + kXBAR1_InputAoi3AoiOut2 = 241|0x10000U, /**< AOI3_AOI_OUT2 output assigned to XBAR1_IN241 input. */ + kXBAR1_InputAoi3AoiOut3 = 242|0x10000U, /**< AOI3_AOI_OUT3 output assigned to XBAR1_IN242 input. */ + kXBAR1_InputAoi4AoiOut0 = 243|0x10000U, /**< AOI4_AOI_OUT0 output assigned to XBAR1_IN243 input. */ + kXBAR1_InputAoi4AoiOut1 = 244|0x10000U, /**< AOI4_AOI_OUT1 output assigned to XBAR1_IN244 input. */ + kXBAR1_InputAoi4AoiOut2 = 245|0x10000U, /**< AOI4_AOI_OUT2 output assigned to XBAR1_IN245 input. */ + kXBAR1_InputAoi4AoiOut3 = 246|0x10000U, /**< AOI4_AOI_OUT3 output assigned to XBAR1_IN246 input. */ + kXBAR1_InputEcatSyncOut0 = 247|0x10000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR1_IN247 input. */ + kXBAR1_InputEcatSyncOut1 = 248|0x10000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR1_IN248 input. */ + kXBAR1_InputFccuVfccuReactionsOut11 = 249|0x10000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR1_IN249 input. */ + kXBAR1_InputGpt1IppDoCmpout1 = 250|0x10000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR1_IN250 input. */ + kXBAR1_InputGpt1IppDoCmpout2 = 251|0x10000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR1_IN251 input. */ + kXBAR1_InputGpt1IppDoCmpout3 = 252|0x10000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR1_IN252 input. */ + kXBAR1_InputGpt2IppDoCmpout1 = 253|0x10000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR1_IN253 input. */ + kXBAR1_InputGpt2IppDoCmpout2 = 254|0x10000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR1_IN254 input. */ + kXBAR1_InputGpt2IppDoCmpout3 = 255|0x10000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR1_IN255 input. */ + kXBAR1_InputGpt3IppDoCmpout1 = 256|0x10000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR1_IN256 input. */ + kXBAR1_InputGpt3IppDoCmpout2 = 257|0x10000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR1_IN257 input. */ + kXBAR1_InputGpt3IppDoCmpout3 = 258|0x10000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR1_IN258 input. */ + kXBAR1_InputGpt4IppDoCmpout1 = 259|0x10000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR1_IN259 input. */ + kXBAR1_InputGpt4IppDoCmpout2 = 260|0x10000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR1_IN260 input. */ + kXBAR1_InputGpt4IppDoCmpout3 = 261|0x10000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR1_IN261 input. */ + kXBAR1_InputFlexio1FlexioTriggerOut0 = 262|0x10000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN262 input. */ + kXBAR1_InputFlexio2FlexioTriggerOut0 = 263|0x10000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN263 input. */ + kXBAR1_InputFlexio3FlexioTriggerOut0 = 264|0x10000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN264 input. */ + kXBAR1_InputFlexio4FlexioTriggerOut0 = 265|0x10000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN265 input. */ + kXBAR1_InputGpio1IpiIntRgpio0 = 266|0x10000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR1_IN266 input. */ + kXBAR1_InputGpio2IpiIntRgpio0 = 267|0x10000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR1_IN267 input. */ + kXBAR1_InputGpio3IpiIntRgpio0 = 268|0x10000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR1_IN268 input. */ + kXBAR1_InputGpio4IpiIntRgpio0 = 269|0x10000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR1_IN269 input. */ + kXBAR1_InputGpio5IpiIntRgpio0 = 270|0x10000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR1_IN270 input. */ + kXBAR1_InputGpio6IpiIntRgpio0 = 271|0x10000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR1_IN271 input. */ + kXBAR1_InputGpio7IpiIntRgpio0 = 272|0x10000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR1_IN272 input. */ + kXBAR1_InputCm33Txev = 273|0x10000U, /**< CM33_TXEV output assigned to XBAR1_IN273 input. */ + kXBAR1_InputCm33SyncTxev = 274|0x10000U, /**< CM33_SYNC_TXEV output assigned to XBAR1_IN274 input. */ + kXBAR1_InputEndat21SiN = 275|0x10000U, /**< ENDAT2_1_SI_N output assigned to XBAR1_IN275 input. */ + kXBAR1_InputEndat21TimerN = 276|0x10000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR1_IN276 input. */ + kXBAR1_InputEndat22SiN = 277|0x10000U, /**< ENDAT2_2_SI_N output assigned to XBAR1_IN277 input. */ + kXBAR1_InputEndat22TimerN = 278|0x10000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR1_IN278 input. */ + kXBAR1_InputBissEot = 279|0x10000U, /**< BISS_EOT output assigned to XBAR1_IN279 input. */ + kXBAR1_InputTriggerSyncSyncOut8 = 280|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT8 output assigned to XBAR1_IN280 input. */ + kXBAR1_InputTriggerSyncSyncOut9 = 281|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT9 output assigned to XBAR1_IN281 input. */ + kXBAR1_InputTriggerSyncSyncOut10 = 282|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT10 output assigned to XBAR1_IN282 input. */ + kXBAR1_InputTriggerSyncSyncOut11 = 283|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT11 output assigned to XBAR1_IN283 input. */ + kXBAR1_InputTriggerSyncSyncOut12 = 284|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT12 output assigned to XBAR1_IN284 input. */ + kXBAR1_InputTriggerSyncSyncOut13 = 285|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT13 output assigned to XBAR1_IN285 input. */ + kXBAR1_InputTriggerSyncSyncOut14 = 286|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT14 output assigned to XBAR1_IN286 input. */ + kXBAR1_InputTriggerSyncSyncOut15 = 287|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT15 output assigned to XBAR1_IN287 input. */ + kXBAR1_InputEcatResetOut = 288|0x10000U, /**< ECAT_RESET_OUT output assigned to XBAR1_IN288 input. */ + kXBAR1_InputHiperface1FastPosRcvdEvt = 289|0x10000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR1_IN289 input. */ + kXBAR1_InputHiperface2FastPosRcvdEvt = 290|0x10000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR1_IN290 input. */ + kXBAR2_InputLogicLow = 0|0x20000U, /**< LOGIC_LOW output assigned to XBAR2_IN0 input. */ + kXBAR2_InputLogicHigh = 1|0x20000U, /**< LOGIC_HIGH output assigned to XBAR2_IN1 input. */ + kXBAR2_InputLogicLow1 = 2|0x20000U, /**< LOGIC_LOW1 output assigned to XBAR2_IN2 input. */ + kXBAR2_InputLogicHigh1 = 3|0x20000U, /**< LOGIC_HIGH1 output assigned to XBAR2_IN3 input. */ + kXBAR2_InputQtimer1Timer0 = 4|0x20000U, /**< QTIMER1_TIMER0 output assigned to XBAR2_IN4 input. */ + kXBAR2_InputQtimer1Timer1 = 5|0x20000U, /**< QTIMER1_TIMER1 output assigned to XBAR2_IN5 input. */ + kXBAR2_InputQtimer1Timer2 = 6|0x20000U, /**< QTIMER1_TIMER2 output assigned to XBAR2_IN6 input. */ + kXBAR2_InputQtimer1Timer3 = 7|0x20000U, /**< QTIMER1_TIMER3 output assigned to XBAR2_IN7 input. */ + kXBAR2_InputQtimer2Timer0 = 8|0x20000U, /**< QTIMER2_TIMER0 output assigned to XBAR2_IN8 input. */ + kXBAR2_InputQtimer2Timer1 = 9|0x20000U, /**< QTIMER2_TIMER1 output assigned to XBAR2_IN9 input. */ + kXBAR2_InputQtimer2Timer2 = 10|0x20000U, /**< QTIMER2_TIMER2 output assigned to XBAR2_IN10 input. */ + kXBAR2_InputQtimer2Timer3 = 11|0x20000U, /**< QTIMER2_TIMER3 output assigned to XBAR2_IN11 input. */ + kXBAR2_InputQtimer3Timer0 = 12|0x20000U, /**< QTIMER3_TIMER0 output assigned to XBAR2_IN12 input. */ + kXBAR2_InputQtimer3Timer1 = 13|0x20000U, /**< QTIMER3_TIMER1 output assigned to XBAR2_IN13 input. */ + kXBAR2_InputQtimer3Timer2 = 14|0x20000U, /**< QTIMER3_TIMER2 output assigned to XBAR2_IN14 input. */ + kXBAR2_InputQtimer3Timer3 = 15|0x20000U, /**< QTIMER3_TIMER3 output assigned to XBAR2_IN15 input. */ + kXBAR2_InputQtimer4Timer0 = 16|0x20000U, /**< QTIMER4_TIMER0 output assigned to XBAR2_IN16 input. */ + kXBAR2_InputQtimer4Timer1 = 17|0x20000U, /**< QTIMER4_TIMER1 output assigned to XBAR2_IN17 input. */ + kXBAR2_InputQtimer4Timer2 = 18|0x20000U, /**< QTIMER4_TIMER2 output assigned to XBAR2_IN18 input. */ + kXBAR2_InputQtimer4Timer3 = 19|0x20000U, /**< QTIMER4_TIMER3 output assigned to XBAR2_IN19 input. */ + kXBAR2_InputQtimer5Timer0 = 20|0x20000U, /**< QTIMER5_TIMER0 output assigned to XBAR2_IN20 input. */ + kXBAR2_InputQtimer5Timer1 = 21|0x20000U, /**< QTIMER5_TIMER1 output assigned to XBAR2_IN21 input. */ + kXBAR2_InputQtimer5Timer2 = 22|0x20000U, /**< QTIMER5_TIMER2 output assigned to XBAR2_IN22 input. */ + kXBAR2_InputQtimer5Timer3 = 23|0x20000U, /**< QTIMER5_TIMER3 output assigned to XBAR2_IN23 input. */ + kXBAR2_InputQtimer6Timer0 = 24|0x20000U, /**< QTIMER6_TIMER0 output assigned to XBAR2_IN24 input. */ + kXBAR2_InputQtimer6Timer1 = 25|0x20000U, /**< QTIMER6_TIMER1 output assigned to XBAR2_IN25 input. */ + kXBAR2_InputQtimer6Timer2 = 26|0x20000U, /**< QTIMER6_TIMER2 output assigned to XBAR2_IN26 input. */ + kXBAR2_InputQtimer6Timer3 = 27|0x20000U, /**< QTIMER6_TIMER3 output assigned to XBAR2_IN27 input. */ + kXBAR2_InputQtimer7Timer0 = 28|0x20000U, /**< QTIMER7_TIMER0 output assigned to XBAR2_IN28 input. */ + kXBAR2_InputQtimer7Timer1 = 29|0x20000U, /**< QTIMER7_TIMER1 output assigned to XBAR2_IN29 input. */ + kXBAR2_InputQtimer7Timer2 = 30|0x20000U, /**< QTIMER7_TIMER2 output assigned to XBAR2_IN30 input. */ + kXBAR2_InputQtimer7Timer3 = 31|0x20000U, /**< QTIMER7_TIMER3 output assigned to XBAR2_IN31 input. */ + kXBAR2_InputQtimer8Timer0 = 32|0x20000U, /**< QTIMER8_TIMER0 output assigned to XBAR2_IN32 input. */ + kXBAR2_InputQtimer8Timer1 = 33|0x20000U, /**< QTIMER8_TIMER1 output assigned to XBAR2_IN33 input. */ + kXBAR2_InputQtimer8Timer2 = 34|0x20000U, /**< QTIMER8_TIMER2 output assigned to XBAR2_IN34 input. */ + kXBAR2_InputQtimer8Timer3 = 35|0x20000U, /**< QTIMER8_TIMER3 output assigned to XBAR2_IN35 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger0 = 36|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR2_IN36 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger1 = 37|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR2_IN37 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger2 = 38|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR2_IN38 input. */ + kXBAR2_InputFlexpwm1Mux0Trigger3 = 39|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR2_IN39 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger0 = 40|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR2_IN40 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger1 = 41|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR2_IN41 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger2 = 42|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR2_IN42 input. */ + kXBAR2_InputFlexpwm2Mux0Trigger3 = 43|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR2_IN43 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger0 = 44|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR2_IN44 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger1 = 45|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR2_IN45 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger2 = 46|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR2_IN46 input. */ + kXBAR2_InputFlexpwm3Mux0Trigger3 = 47|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR2_IN47 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger0 = 48|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR2_IN48 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger1 = 49|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR2_IN49 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger2 = 50|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR2_IN50 input. */ + kXBAR2_InputFlexpwm4Mux0Trigger3 = 51|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR2_IN51 input. */ + kXBAR2_InputLpit1LpitTrigOut0 = 52|0x20000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR2_IN52 input. */ + kXBAR2_InputLpit1LpitTrigOut1 = 53|0x20000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR2_IN53 input. */ + kXBAR2_InputLpit1LpitTrigOut2 = 54|0x20000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR2_IN54 input. */ + kXBAR2_InputLpit1LpitTrigOut3 = 55|0x20000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR2_IN55 input. */ + kXBAR2_InputLpit2LpitTrigOut0 = 56|0x20000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR2_IN56 input. */ + kXBAR2_InputLpit2LpitTrigOut1 = 57|0x20000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR2_IN57 input. */ + kXBAR2_InputLpit2LpitTrigOut2 = 58|0x20000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR2_IN58 input. */ + kXBAR2_InputLpit2LpitTrigOut3 = 59|0x20000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR2_IN59 input. */ + kXBAR2_InputLpit3LpitTrigOut0 = 60|0x20000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR2_IN60 input. */ + kXBAR2_InputLpit3LpitTrigOut1 = 61|0x20000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR2_IN61 input. */ + kXBAR2_InputLpit3LpitTrigOut2 = 62|0x20000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR2_IN62 input. */ + kXBAR2_InputLpit3LpitTrigOut3 = 63|0x20000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR2_IN63 input. */ + kXBAR2_InputEdma2DmaTriggerOut0 = 64|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN64 input. */ + kXBAR2_InputEdma2DmaTriggerOut1 = 65|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN65 input. */ + kXBAR2_InputEdma2DmaTriggerOut2 = 66|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN66 input. */ + kXBAR2_InputEdma2DmaTriggerOut3 = 67|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN67 input. */ + kXBAR2_InputEdma2DmaTriggerOut4 = 68|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN68 input. */ + kXBAR2_InputEdma2DmaTriggerOut5 = 69|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN69 input. */ + kXBAR2_InputEdma2DmaTriggerOut6 = 70|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN70 input. */ + kXBAR2_InputEdma2DmaTriggerOut7 = 71|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN71 input. */ + kXBAR2_InputEdma1DmaTriggerOut0 = 72|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN72 input. */ + kXBAR2_InputEdma1DmaTriggerOut1 = 73|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN73 input. */ + kXBAR2_InputEdma1DmaTriggerOut2 = 74|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN74 input. */ + kXBAR2_InputEdma1DmaTriggerOut3 = 75|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN75 input. */ + kXBAR2_InputEdma1DmaTriggerOut4 = 76|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN76 input. */ + kXBAR2_InputEdma1DmaTriggerOut5 = 77|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN77 input. */ + kXBAR2_InputEdma1DmaTriggerOut6 = 78|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN78 input. */ + kXBAR2_InputEdma1DmaTriggerOut7 = 79|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN79 input. */ + kXBAR2_InputEdma3DmaTriggerOut0 = 80|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN80 input. */ + kXBAR2_InputEdma3DmaTriggerOut1 = 81|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN81 input. */ + kXBAR2_InputEdma3DmaTriggerOut2 = 82|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN82 input. */ + kXBAR2_InputEdma3DmaTriggerOut3 = 83|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN83 input. */ + kXBAR2_InputEdma3DmaTriggerOut4 = 84|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN84 input. */ + kXBAR2_InputEdma3DmaTriggerOut5 = 85|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN85 input. */ + kXBAR2_InputEdma3DmaTriggerOut6 = 86|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN86 input. */ + kXBAR2_InputEdma3DmaTriggerOut7 = 87|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN87 input. */ + kXBAR2_InputEdma4DmaTriggerOut0 = 88|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN88 input. */ + kXBAR2_InputEdma4DmaTriggerOut1 = 89|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN89 input. */ + kXBAR2_InputEdma4DmaTriggerOut2 = 90|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN90 input. */ + kXBAR2_InputEdma4DmaTriggerOut3 = 91|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN91 input. */ + kXBAR2_InputEdma4DmaTriggerOut4 = 92|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN92 input. */ + kXBAR2_InputEdma4DmaTriggerOut5 = 93|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN93 input. */ + kXBAR2_InputEdma4DmaTriggerOut6 = 94|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN94 input. */ + kXBAR2_InputEdma4DmaTriggerOut7 = 95|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN95 input. */ + kXBAR2_InputAdc1IpiIntEoc = 96|0x20000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR2_IN96 input. */ + kXBAR2_InputAdc1IpiIntWd = 97|0x20000U, /**< ADC1_IPI_INT_WD output assigned to XBAR2_IN97 input. */ + kXBAR2_InputTpm1LptpmChTrigger0 = 98|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN98 input. */ + kXBAR2_InputTpm1LptpmChTrigger1 = 99|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN99 input. */ + kXBAR2_InputTpm1LptpmChTrigger2 = 100|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN100 input. */ + kXBAR2_InputTpm1LptpmChTrigger3 = 101|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN101 input. */ + kXBAR2_InputTpm1LptpmTrigger = 102|0x20000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR2_IN102 input. */ + kXBAR2_InputTpm2LptpmChTrigger0 = 103|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN103 input. */ + kXBAR2_InputTpm2LptpmChTrigger1 = 104|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN104 input. */ + kXBAR2_InputTpm2LptpmChTrigger2 = 105|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN105 input. */ + kXBAR2_InputTpm2LptpmChTrigger3 = 106|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN106 input. */ + kXBAR2_InputTpm2LptpmTrigger = 107|0x20000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR2_IN107 input. */ + kXBAR2_InputTpm3LptpmChTrigger0 = 108|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN108 input. */ + kXBAR2_InputTpm3LptpmChTrigger1 = 109|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN109 input. */ + kXBAR2_InputTpm3LptpmChTrigger2 = 110|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN110 input. */ + kXBAR2_InputTpm3LptpmChTrigger3 = 111|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN111 input. */ + kXBAR2_InputTpm3LptpmTrigger = 112|0x20000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR2_IN112 input. */ + kXBAR2_InputTpm4LptpmChTrigger0 = 113|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN113 input. */ + kXBAR2_InputTpm4LptpmChTrigger1 = 114|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN114 input. */ + kXBAR2_InputTpm4LptpmChTrigger2 = 115|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN115 input. */ + kXBAR2_InputTpm4LptpmChTrigger3 = 116|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN116 input. */ + kXBAR2_InputTpm4LptpmTrigger = 117|0x20000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR2_IN117 input. */ + kXBAR2_InputTpm5LptpmChTrigger0 = 118|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN118 input. */ + kXBAR2_InputTpm5LptpmChTrigger1 = 119|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN119 input. */ + kXBAR2_InputTpm5LptpmChTrigger2 = 120|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN120 input. */ + kXBAR2_InputTpm5LptpmChTrigger3 = 121|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN121 input. */ + kXBAR2_InputTpm5LptpmTrigger = 122|0x20000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR2_IN122 input. */ + kXBAR2_InputTpm6LptpmChTrigger0 = 123|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN123 input. */ + kXBAR2_InputTpm6LptpmChTrigger1 = 124|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN124 input. */ + kXBAR2_InputTpm6LptpmChTrigger2 = 125|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN125 input. */ + kXBAR2_InputTpm6LptpmChTrigger3 = 126|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN126 input. */ + kXBAR2_InputTpm6LptpmTrigger = 127|0x20000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR2_IN127 input. */ + kXBAR2_InputLptmr1LptimerTriggerDelay = 128|0x20000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN128 input. */ + kXBAR2_InputLptmr2LptimerTriggerDelay = 129|0x20000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN129 input. */ + kXBAR2_InputLogicLow2 = 130|0x20000U, /**< LOGIC_LOW2 output assigned to XBAR2_IN130 input. */ + kXBAR2_InputNetcTmr11588Pp1 = 131|0x20000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR2_IN131 input. */ + kXBAR2_InputNetcTmr11588Pp2 = 132|0x20000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR2_IN132 input. */ + kXBAR2_InputNetcTmr11588Pp3 = 133|0x20000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR2_IN133 input. */ + kXBAR2_InputNetcTmr11588Alarm1 = 134|0x20000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR2_IN134 input. */ + kXBAR2_InputNetcTmr11588Alarm2 = 135|0x20000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR2_IN135 input. */ + kXBAR2_InputNetcTmr21588Pp1 = 136|0x20000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR2_IN136 input. */ + kXBAR2_InputNetcTmr21588Pp2 = 137|0x20000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR2_IN137 input. */ + kXBAR2_InputNetcTmr21588Pp3 = 138|0x20000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR2_IN138 input. */ + kXBAR2_InputNetcTmr21588Alarm1 = 139|0x20000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR2_IN139 input. */ + kXBAR2_InputNetcTmr21588Alarm2 = 140|0x20000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR2_IN140 input. */ + kXBAR2_InputNetcTmr31588Pp1 = 141|0x20000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR2_IN141 input. */ + kXBAR2_InputNetcTmr31588Pp2 = 142|0x20000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR2_IN142 input. */ + kXBAR2_InputNetcTmr31588Pp3 = 143|0x20000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR2_IN143 input. */ + kXBAR2_InputNetcTmr31588Alarm1 = 144|0x20000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR2_IN144 input. */ + kXBAR2_InputNetcTmr31588Alarm2 = 145|0x20000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR2_IN145 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak0 = 146|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR2_IN146 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak1 = 147|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR2_IN147 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak2 = 148|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR2_IN148 input. */ + kXBAR2_InputSincFilterGlue1IppDoBreak3 = 149|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR2_IN149 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak0 = 150|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR2_IN150 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak1 = 151|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR2_IN151 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak2 = 152|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR2_IN152 input. */ + kXBAR2_InputSincFilterGlue2IppDoBreak3 = 153|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR2_IN153 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak0 = 154|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR2_IN154 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak1 = 155|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR2_IN155 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak2 = 156|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR2_IN156 input. */ + kXBAR2_InputSincFilterGlue3IppDoBreak3 = 157|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR2_IN157 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak0 = 158|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR2_IN158 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak1 = 159|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR2_IN159 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak2 = 160|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR2_IN160 input. */ + kXBAR2_InputSincFilterGlue4IppDoBreak3 = 161|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR2_IN161 input. */ + kXBAR2_InputSinc1PulseTrg0 = 162|0x20000U, /**< SINC1_PULSE_TRG0 output assigned to XBAR2_IN162 input. */ + kXBAR2_InputSinc1PulseTrg1 = 163|0x20000U, /**< SINC1_PULSE_TRG1 output assigned to XBAR2_IN163 input. */ + kXBAR2_InputSinc1PulseTrg2 = 164|0x20000U, /**< SINC1_PULSE_TRG2 output assigned to XBAR2_IN164 input. */ + kXBAR2_InputSinc1PulseTrg3 = 165|0x20000U, /**< SINC1_PULSE_TRG3 output assigned to XBAR2_IN165 input. */ + kXBAR2_InputSinc3PulseTrg0 = 166|0x20000U, /**< SINC3_PULSE_TRG0 output assigned to XBAR2_IN166 input. */ + kXBAR2_InputSinc3PulseTrg1 = 167|0x20000U, /**< SINC3_PULSE_TRG1 output assigned to XBAR2_IN167 input. */ + kXBAR2_InputSinc3PulseTrg2 = 168|0x20000U, /**< SINC3_PULSE_TRG2 output assigned to XBAR2_IN168 input. */ + kXBAR2_InputSinc3PulseTrg3 = 169|0x20000U, /**< SINC3_PULSE_TRG3 output assigned to XBAR2_IN169 input. */ + kXBAR2_InputEcatSyncOut0 = 170|0x20000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR2_IN170 input. */ + kXBAR2_InputEcatSyncOut1 = 171|0x20000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR2_IN171 input. */ + kXBAR2_InputFccuVfccuReactionsOut11 = 172|0x20000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR2_IN172 input. */ + kXBAR2_InputGpt1IppDoCmpout1 = 173|0x20000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR2_IN173 input. */ + kXBAR2_InputGpt1IppDoCmpout2 = 174|0x20000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR2_IN174 input. */ + kXBAR2_InputGpt1IppDoCmpout3 = 175|0x20000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR2_IN175 input. */ + kXBAR2_InputGpt2IppDoCmpout1 = 176|0x20000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR2_IN176 input. */ + kXBAR2_InputGpt2IppDoCmpout2 = 177|0x20000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR2_IN177 input. */ + kXBAR2_InputGpt2IppDoCmpout3 = 178|0x20000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR2_IN178 input. */ + kXBAR2_InputGpt3IppDoCmpout1 = 179|0x20000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR2_IN179 input. */ + kXBAR2_InputGpt3IppDoCmpout2 = 180|0x20000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR2_IN180 input. */ + kXBAR2_InputGpt3IppDoCmpout3 = 181|0x20000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR2_IN181 input. */ + kXBAR2_InputGpt4IppDoCmpout1 = 182|0x20000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR2_IN182 input. */ + kXBAR2_InputGpt4IppDoCmpout2 = 183|0x20000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR2_IN183 input. */ + kXBAR2_InputGpt4IppDoCmpout3 = 184|0x20000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR2_IN184 input. */ + kXBAR2_InputFlexio1FlexioTriggerOut0 = 185|0x20000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN185 input. */ + kXBAR2_InputFlexio2FlexioTriggerOut0 = 186|0x20000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN186 input. */ + kXBAR2_InputFlexio3FlexioTriggerOut0 = 187|0x20000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN187 input. */ + kXBAR2_InputFlexio4FlexioTriggerOut0 = 188|0x20000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN188 input. */ + kXBAR2_InputGpio1IpiIntRgpio0 = 189|0x20000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR2_IN189 input. */ + kXBAR2_InputGpio2IpiIntRgpio0 = 190|0x20000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR2_IN190 input. */ + kXBAR2_InputGpio3IpiIntRgpio0 = 191|0x20000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR2_IN191 input. */ + kXBAR2_InputGpio4IpiIntRgpio0 = 192|0x20000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR2_IN192 input. */ + kXBAR2_InputGpio5IpiIntRgpio0 = 193|0x20000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR2_IN193 input. */ + kXBAR2_InputGpio6IpiIntRgpio0 = 194|0x20000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR2_IN194 input. */ + kXBAR2_InputGpio7IpiIntRgpio0 = 195|0x20000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR2_IN195 input. */ + kXBAR2_InputCm33Txev = 196|0x20000U, /**< CM33_TXEV output assigned to XBAR2_IN196 input. */ + kXBAR2_InputCm33SyncTxev = 197|0x20000U, /**< CM33_SYNC_TXEV output assigned to XBAR2_IN197 input. */ + kXBAR2_InputEndat21SiN = 198|0x20000U, /**< ENDAT2_1_SI_N output assigned to XBAR2_IN198 input. */ + kXBAR2_InputEndat21TimerN = 199|0x20000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR2_IN199 input. */ + kXBAR2_InputEndat22SiN = 200|0x20000U, /**< ENDAT2_2_SI_N output assigned to XBAR2_IN200 input. */ + kXBAR2_InputEndat22TimerN = 201|0x20000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR2_IN201 input. */ + kXBAR2_InputBissEot = 202|0x20000U, /**< BISS_EOT output assigned to XBAR2_IN202 input. */ + kXBAR2_InputEnc1PosMatch0 = 203|0x20000U, /**< ENC1_POS_MATCH0 output assigned to XBAR2_IN203 input. */ + kXBAR2_InputEnc1PosMatch1 = 204|0x20000U, /**< ENC1_POS_MATCH1 output assigned to XBAR2_IN204 input. */ + kXBAR2_InputEnc1PosMatch2 = 205|0x20000U, /**< ENC1_POS_MATCH2 output assigned to XBAR2_IN205 input. */ + kXBAR2_InputEnc1PosMatch3 = 206|0x20000U, /**< ENC1_POS_MATCH3 output assigned to XBAR2_IN206 input. */ + kXBAR2_InputEnc1CompFlg0 = 207|0x20000U, /**< ENC1_COMP_FLG0 output assigned to XBAR2_IN207 input. */ + kXBAR2_InputEnc1CompFlg1 = 208|0x20000U, /**< ENC1_COMP_FLG1 output assigned to XBAR2_IN208 input. */ + kXBAR2_InputEnc1CompFlg2 = 209|0x20000U, /**< ENC1_COMP_FLG2 output assigned to XBAR2_IN209 input. */ + kXBAR2_InputEnc1CompFlg3 = 210|0x20000U, /**< ENC1_COMP_FLG3 output assigned to XBAR2_IN210 input. */ + kXBAR2_InputEnc1CntDn = 211|0x20000U, /**< ENC1_CNT_DN output assigned to XBAR2_IN211 input. */ + kXBAR2_InputEnc1CntUp = 212|0x20000U, /**< ENC1_CNT_UP output assigned to XBAR2_IN212 input. */ + kXBAR2_InputEnc1Dir = 213|0x20000U, /**< ENC1_DIR output assigned to XBAR2_IN213 input. */ + kXBAR2_InputEnc3PosMatch0 = 214|0x20000U, /**< ENC3_POS_MATCH0 output assigned to XBAR2_IN214 input. */ + kXBAR2_InputEnc3PosMatch1 = 215|0x20000U, /**< ENC3_POS_MATCH1 output assigned to XBAR2_IN215 input. */ + kXBAR2_InputEnc3PosMatch2 = 216|0x20000U, /**< ENC3_POS_MATCH2 output assigned to XBAR2_IN216 input. */ + kXBAR2_InputEnc3PosMatch3 = 217|0x20000U, /**< ENC3_POS_MATCH3 output assigned to XBAR2_IN217 input. */ + kXBAR2_InputEnc3CompFlg0 = 218|0x20000U, /**< ENC3_COMP_FLG0 output assigned to XBAR2_IN218 input. */ + kXBAR2_InputEnc3CompFlg1 = 219|0x20000U, /**< ENC3_COMP_FLG1 output assigned to XBAR2_IN219 input. */ + kXBAR2_InputEnc3CompFlg2 = 220|0x20000U, /**< ENC3_COMP_FLG2 output assigned to XBAR2_IN220 input. */ + kXBAR2_InputEnc3CompFlg3 = 221|0x20000U, /**< ENC3_COMP_FLG3 output assigned to XBAR2_IN221 input. */ + kXBAR2_InputEnc3CntDn = 222|0x20000U, /**< ENC3_CNT_DN output assigned to XBAR2_IN222 input. */ + kXBAR2_InputEnc3CntUp = 223|0x20000U, /**< ENC3_CNT_UP output assigned to XBAR2_IN223 input. */ + kXBAR2_InputEnc3Dir = 224|0x20000U, /**< ENC3_DIR output assigned to XBAR2_IN224 input. */ + kXBAR2_InputHiperface1FastPosRcvdEvt = 225|0x20000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR2_IN225 input. */ + kXBAR2_InputHiperface2FastPosRcvdEvt = 226|0x20000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR2_IN226 input. */ + kXBAR3_InputLogicLow = 0|0x30000U, /**< LOGIC_LOW output assigned to XBAR3_IN0 input. */ + kXBAR3_InputLogicHigh = 1|0x30000U, /**< LOGIC_HIGH output assigned to XBAR3_IN1 input. */ + kXBAR3_InputLogicLow1 = 2|0x30000U, /**< LOGIC_LOW1 output assigned to XBAR3_IN2 input. */ + kXBAR3_InputLogicHigh1 = 3|0x30000U, /**< LOGIC_HIGH1 output assigned to XBAR3_IN3 input. */ + kXBAR3_InputQtimer1Timer0 = 4|0x30000U, /**< QTIMER1_TIMER0 output assigned to XBAR3_IN4 input. */ + kXBAR3_InputQtimer1Timer1 = 5|0x30000U, /**< QTIMER1_TIMER1 output assigned to XBAR3_IN5 input. */ + kXBAR3_InputQtimer1Timer2 = 6|0x30000U, /**< QTIMER1_TIMER2 output assigned to XBAR3_IN6 input. */ + kXBAR3_InputQtimer1Timer3 = 7|0x30000U, /**< QTIMER1_TIMER3 output assigned to XBAR3_IN7 input. */ + kXBAR3_InputQtimer2Timer0 = 8|0x30000U, /**< QTIMER2_TIMER0 output assigned to XBAR3_IN8 input. */ + kXBAR3_InputQtimer2Timer1 = 9|0x30000U, /**< QTIMER2_TIMER1 output assigned to XBAR3_IN9 input. */ + kXBAR3_InputQtimer2Timer2 = 10|0x30000U, /**< QTIMER2_TIMER2 output assigned to XBAR3_IN10 input. */ + kXBAR3_InputQtimer2Timer3 = 11|0x30000U, /**< QTIMER2_TIMER3 output assigned to XBAR3_IN11 input. */ + kXBAR3_InputQtimer3Timer0 = 12|0x30000U, /**< QTIMER3_TIMER0 output assigned to XBAR3_IN12 input. */ + kXBAR3_InputQtimer3Timer1 = 13|0x30000U, /**< QTIMER3_TIMER1 output assigned to XBAR3_IN13 input. */ + kXBAR3_InputQtimer3Timer2 = 14|0x30000U, /**< QTIMER3_TIMER2 output assigned to XBAR3_IN14 input. */ + kXBAR3_InputQtimer3Timer3 = 15|0x30000U, /**< QTIMER3_TIMER3 output assigned to XBAR3_IN15 input. */ + kXBAR3_InputQtimer4Timer0 = 16|0x30000U, /**< QTIMER4_TIMER0 output assigned to XBAR3_IN16 input. */ + kXBAR3_InputQtimer4Timer1 = 17|0x30000U, /**< QTIMER4_TIMER1 output assigned to XBAR3_IN17 input. */ + kXBAR3_InputQtimer4Timer2 = 18|0x30000U, /**< QTIMER4_TIMER2 output assigned to XBAR3_IN18 input. */ + kXBAR3_InputQtimer4Timer3 = 19|0x30000U, /**< QTIMER4_TIMER3 output assigned to XBAR3_IN19 input. */ + kXBAR3_InputQtimer5Timer0 = 20|0x30000U, /**< QTIMER5_TIMER0 output assigned to XBAR3_IN20 input. */ + kXBAR3_InputQtimer5Timer1 = 21|0x30000U, /**< QTIMER5_TIMER1 output assigned to XBAR3_IN21 input. */ + kXBAR3_InputQtimer5Timer2 = 22|0x30000U, /**< QTIMER5_TIMER2 output assigned to XBAR3_IN22 input. */ + kXBAR3_InputQtimer5Timer3 = 23|0x30000U, /**< QTIMER5_TIMER3 output assigned to XBAR3_IN23 input. */ + kXBAR3_InputQtimer6Timer0 = 24|0x30000U, /**< QTIMER6_TIMER0 output assigned to XBAR3_IN24 input. */ + kXBAR3_InputQtimer6Timer1 = 25|0x30000U, /**< QTIMER6_TIMER1 output assigned to XBAR3_IN25 input. */ + kXBAR3_InputQtimer6Timer2 = 26|0x30000U, /**< QTIMER6_TIMER2 output assigned to XBAR3_IN26 input. */ + kXBAR3_InputQtimer6Timer3 = 27|0x30000U, /**< QTIMER6_TIMER3 output assigned to XBAR3_IN27 input. */ + kXBAR3_InputQtimer7Timer0 = 28|0x30000U, /**< QTIMER7_TIMER0 output assigned to XBAR3_IN28 input. */ + kXBAR3_InputQtimer7Timer1 = 29|0x30000U, /**< QTIMER7_TIMER1 output assigned to XBAR3_IN29 input. */ + kXBAR3_InputQtimer7Timer2 = 30|0x30000U, /**< QTIMER7_TIMER2 output assigned to XBAR3_IN30 input. */ + kXBAR3_InputQtimer7Timer3 = 31|0x30000U, /**< QTIMER7_TIMER3 output assigned to XBAR3_IN31 input. */ + kXBAR3_InputQtimer8Timer0 = 32|0x30000U, /**< QTIMER8_TIMER0 output assigned to XBAR3_IN32 input. */ + kXBAR3_InputQtimer8Timer1 = 33|0x30000U, /**< QTIMER8_TIMER1 output assigned to XBAR3_IN33 input. */ + kXBAR3_InputQtimer8Timer2 = 34|0x30000U, /**< QTIMER8_TIMER2 output assigned to XBAR3_IN34 input. */ + kXBAR3_InputQtimer8Timer3 = 35|0x30000U, /**< QTIMER8_TIMER3 output assigned to XBAR3_IN35 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger0 = 36|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR3_IN36 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger1 = 37|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR3_IN37 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger2 = 38|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR3_IN38 input. */ + kXBAR3_InputFlexpwm1Mux0Trigger3 = 39|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR3_IN39 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger0 = 40|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR3_IN40 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger1 = 41|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR3_IN41 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger2 = 42|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR3_IN42 input. */ + kXBAR3_InputFlexpwm2Mux0Trigger3 = 43|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR3_IN43 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger0 = 44|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR3_IN44 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger1 = 45|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR3_IN45 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger2 = 46|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR3_IN46 input. */ + kXBAR3_InputFlexpwm3Mux0Trigger3 = 47|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR3_IN47 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger0 = 48|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR3_IN48 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger1 = 49|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR3_IN49 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger2 = 50|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR3_IN50 input. */ + kXBAR3_InputFlexpwm4Mux0Trigger3 = 51|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR3_IN51 input. */ + kXBAR3_InputLpit1LpitTrigOut0 = 52|0x30000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR3_IN52 input. */ + kXBAR3_InputLpit1LpitTrigOut1 = 53|0x30000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR3_IN53 input. */ + kXBAR3_InputLpit1LpitTrigOut2 = 54|0x30000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR3_IN54 input. */ + kXBAR3_InputLpit1LpitTrigOut3 = 55|0x30000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR3_IN55 input. */ + kXBAR3_InputLpit2LpitTrigOut0 = 56|0x30000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR3_IN56 input. */ + kXBAR3_InputLpit2LpitTrigOut1 = 57|0x30000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR3_IN57 input. */ + kXBAR3_InputLpit2LpitTrigOut2 = 58|0x30000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR3_IN58 input. */ + kXBAR3_InputLpit2LpitTrigOut3 = 59|0x30000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR3_IN59 input. */ + kXBAR3_InputLpit3LpitTrigOut0 = 60|0x30000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR3_IN60 input. */ + kXBAR3_InputLpit3LpitTrigOut1 = 61|0x30000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR3_IN61 input. */ + kXBAR3_InputLpit3LpitTrigOut2 = 62|0x30000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR3_IN62 input. */ + kXBAR3_InputLpit3LpitTrigOut3 = 63|0x30000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR3_IN63 input. */ + kXBAR3_InputEdma2DmaTriggerOut0 = 64|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN64 input. */ + kXBAR3_InputEdma2DmaTriggerOut1 = 65|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN65 input. */ + kXBAR3_InputEdma2DmaTriggerOut2 = 66|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN66 input. */ + kXBAR3_InputEdma2DmaTriggerOut3 = 67|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN67 input. */ + kXBAR3_InputEdma2DmaTriggerOut4 = 68|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN68 input. */ + kXBAR3_InputEdma2DmaTriggerOut5 = 69|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN69 input. */ + kXBAR3_InputEdma2DmaTriggerOut6 = 70|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN70 input. */ + kXBAR3_InputEdma2DmaTriggerOut7 = 71|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN71 input. */ + kXBAR3_InputEdma1DmaTriggerOut0 = 72|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN72 input. */ + kXBAR3_InputEdma1DmaTriggerOut1 = 73|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN73 input. */ + kXBAR3_InputEdma1DmaTriggerOut2 = 74|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN74 input. */ + kXBAR3_InputEdma1DmaTriggerOut3 = 75|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN75 input. */ + kXBAR3_InputEdma1DmaTriggerOut4 = 76|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN76 input. */ + kXBAR3_InputEdma1DmaTriggerOut5 = 77|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN77 input. */ + kXBAR3_InputEdma1DmaTriggerOut6 = 78|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN78 input. */ + kXBAR3_InputEdma1DmaTriggerOut7 = 79|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN79 input. */ + kXBAR3_InputEdma3DmaTriggerOut0 = 80|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN80 input. */ + kXBAR3_InputEdma3DmaTriggerOut1 = 81|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN81 input. */ + kXBAR3_InputEdma3DmaTriggerOut2 = 82|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN82 input. */ + kXBAR3_InputEdma3DmaTriggerOut3 = 83|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN83 input. */ + kXBAR3_InputEdma3DmaTriggerOut4 = 84|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN84 input. */ + kXBAR3_InputEdma3DmaTriggerOut5 = 85|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN85 input. */ + kXBAR3_InputEdma3DmaTriggerOut6 = 86|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN86 input. */ + kXBAR3_InputEdma3DmaTriggerOut7 = 87|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN87 input. */ + kXBAR3_InputEdma4DmaTriggerOut0 = 88|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN88 input. */ + kXBAR3_InputEdma4DmaTriggerOut1 = 89|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN89 input. */ + kXBAR3_InputEdma4DmaTriggerOut2 = 90|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN90 input. */ + kXBAR3_InputEdma4DmaTriggerOut3 = 91|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN91 input. */ + kXBAR3_InputEdma4DmaTriggerOut4 = 92|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN92 input. */ + kXBAR3_InputEdma4DmaTriggerOut5 = 93|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN93 input. */ + kXBAR3_InputEdma4DmaTriggerOut6 = 94|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN94 input. */ + kXBAR3_InputEdma4DmaTriggerOut7 = 95|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN95 input. */ + kXBAR3_InputAdc1IpiIntEoc = 96|0x30000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR3_IN96 input. */ + kXBAR3_InputAdc1IpiIntWd = 97|0x30000U, /**< ADC1_IPI_INT_WD output assigned to XBAR3_IN97 input. */ + kXBAR3_InputTpm1LptpmChTrigger0 = 98|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN98 input. */ + kXBAR3_InputTpm1LptpmChTrigger1 = 99|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN99 input. */ + kXBAR3_InputTpm1LptpmChTrigger2 = 100|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN100 input. */ + kXBAR3_InputTpm1LptpmChTrigger3 = 101|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN101 input. */ + kXBAR3_InputTpm1LptpmTrigger = 102|0x30000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR3_IN102 input. */ + kXBAR3_InputTpm2LptpmChTrigger0 = 103|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN103 input. */ + kXBAR3_InputTpm2LptpmChTrigger1 = 104|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN104 input. */ + kXBAR3_InputTpm2LptpmChTrigger2 = 105|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN105 input. */ + kXBAR3_InputTpm2LptpmChTrigger3 = 106|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN106 input. */ + kXBAR3_InputTpm2LptpmTrigger = 107|0x30000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR3_IN107 input. */ + kXBAR3_InputTpm3LptpmChTrigger0 = 108|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN108 input. */ + kXBAR3_InputTpm3LptpmChTrigger1 = 109|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN109 input. */ + kXBAR3_InputTpm3LptpmChTrigger2 = 110|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN110 input. */ + kXBAR3_InputTpm3LptpmChTrigger3 = 111|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN111 input. */ + kXBAR3_InputTpm3LptpmTrigger = 112|0x30000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR3_IN112 input. */ + kXBAR3_InputTpm4LptpmChTrigger0 = 113|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN113 input. */ + kXBAR3_InputTpm4LptpmChTrigger1 = 114|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN114 input. */ + kXBAR3_InputTpm4LptpmChTrigger2 = 115|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN115 input. */ + kXBAR3_InputTpm4LptpmChTrigger3 = 116|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN116 input. */ + kXBAR3_InputTpm4LptpmTrigger = 117|0x30000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR3_IN117 input. */ + kXBAR3_InputTpm5LptpmChTrigger0 = 118|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN118 input. */ + kXBAR3_InputTpm5LptpmChTrigger1 = 119|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN119 input. */ + kXBAR3_InputTpm5LptpmChTrigger2 = 120|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN120 input. */ + kXBAR3_InputTpm5LptpmChTrigger3 = 121|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN121 input. */ + kXBAR3_InputTpm5LptpmTrigger = 122|0x30000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR3_IN122 input. */ + kXBAR3_InputTpm6LptpmChTrigger0 = 123|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN123 input. */ + kXBAR3_InputTpm6LptpmChTrigger1 = 124|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN124 input. */ + kXBAR3_InputTpm6LptpmChTrigger2 = 125|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN125 input. */ + kXBAR3_InputTpm6LptpmChTrigger3 = 126|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN126 input. */ + kXBAR3_InputTpm6LptpmTrigger = 127|0x30000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR3_IN127 input. */ + kXBAR3_InputLptmr1LptimerTriggerDelay = 128|0x30000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN128 input. */ + kXBAR3_InputLptmr2LptimerTriggerDelay = 129|0x30000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN129 input. */ + kXBAR3_InputLogicLow2 = 130|0x30000U, /**< LOGIC_LOW2 output assigned to XBAR3_IN130 input. */ + kXBAR3_InputNetcTmr11588Pp1 = 131|0x30000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR3_IN131 input. */ + kXBAR3_InputNetcTmr11588Pp2 = 132|0x30000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR3_IN132 input. */ + kXBAR3_InputNetcTmr11588Pp3 = 133|0x30000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR3_IN133 input. */ + kXBAR3_InputNetcTmr11588Alarm1 = 134|0x30000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR3_IN134 input. */ + kXBAR3_InputNetcTmr11588Alarm2 = 135|0x30000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR3_IN135 input. */ + kXBAR3_InputNetcTmr21588Pp1 = 136|0x30000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR3_IN136 input. */ + kXBAR3_InputNetcTmr21588Pp2 = 137|0x30000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR3_IN137 input. */ + kXBAR3_InputNetcTmr21588Pp3 = 138|0x30000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR3_IN138 input. */ + kXBAR3_InputNetcTmr21588Alarm1 = 139|0x30000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR3_IN139 input. */ + kXBAR3_InputNetcTmr21588Alarm2 = 140|0x30000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR3_IN140 input. */ + kXBAR3_InputNetcTmr31588Pp1 = 141|0x30000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR3_IN141 input. */ + kXBAR3_InputNetcTmr31588Pp2 = 142|0x30000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR3_IN142 input. */ + kXBAR3_InputNetcTmr31588Pp3 = 143|0x30000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR3_IN143 input. */ + kXBAR3_InputNetcTmr31588Alarm1 = 144|0x30000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR3_IN144 input. */ + kXBAR3_InputNetcTmr31588Alarm2 = 145|0x30000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR3_IN145 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak0 = 146|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR3_IN146 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak1 = 147|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR3_IN147 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak2 = 148|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR3_IN148 input. */ + kXBAR3_InputSincFilterGlue1IppDoBreak3 = 149|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR3_IN149 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak0 = 150|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR3_IN150 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak1 = 151|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR3_IN151 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak2 = 152|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR3_IN152 input. */ + kXBAR3_InputSincFilterGlue2IppDoBreak3 = 153|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR3_IN153 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak0 = 154|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR3_IN154 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak1 = 155|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR3_IN155 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak2 = 156|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR3_IN156 input. */ + kXBAR3_InputSincFilterGlue3IppDoBreak3 = 157|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR3_IN157 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak0 = 158|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR3_IN158 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak1 = 159|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR3_IN159 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak2 = 160|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR3_IN160 input. */ + kXBAR3_InputSincFilterGlue4IppDoBreak3 = 161|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR3_IN161 input. */ + kXBAR3_InputSinc2PulseTrg0 = 162|0x30000U, /**< SINC2_PULSE_TRG0 output assigned to XBAR3_IN162 input. */ + kXBAR3_InputSinc2PulseTrg1 = 163|0x30000U, /**< SINC2_PULSE_TRG1 output assigned to XBAR3_IN163 input. */ + kXBAR3_InputSinc2PulseTrg2 = 164|0x30000U, /**< SINC2_PULSE_TRG2 output assigned to XBAR3_IN164 input. */ + kXBAR3_InputSinc2PulseTrg3 = 165|0x30000U, /**< SINC2_PULSE_TRG3 output assigned to XBAR3_IN165 input. */ + kXBAR3_InputSinc4PulseTrg0 = 166|0x30000U, /**< SINC4_PULSE_TRG0 output assigned to XBAR3_IN166 input. */ + kXBAR3_InputSinc4PulseTrg1 = 167|0x30000U, /**< SINC4_PULSE_TRG1 output assigned to XBAR3_IN167 input. */ + kXBAR3_InputSinc4PulseTrg2 = 168|0x30000U, /**< SINC4_PULSE_TRG2 output assigned to XBAR3_IN168 input. */ + kXBAR3_InputSinc4PulseTrg3 = 169|0x30000U, /**< SINC4_PULSE_TRG3 output assigned to XBAR3_IN169 input. */ + kXBAR3_InputEcatSyncOut0 = 170|0x30000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR3_IN170 input. */ + kXBAR3_InputEcatSyncOut1 = 171|0x30000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR3_IN171 input. */ + kXBAR3_InputFccuVfccuReactionsOut11 = 172|0x30000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR3_IN172 input. */ + kXBAR3_InputGpt1IppDoCmpout1 = 173|0x30000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR3_IN173 input. */ + kXBAR3_InputGpt1IppDoCmpout2 = 174|0x30000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR3_IN174 input. */ + kXBAR3_InputGpt1IppDoCmpout3 = 175|0x30000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR3_IN175 input. */ + kXBAR3_InputGpt2IppDoCmpout1 = 176|0x30000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR3_IN176 input. */ + kXBAR3_InputGpt2IppDoCmpout2 = 177|0x30000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR3_IN177 input. */ + kXBAR3_InputGpt2IppDoCmpout3 = 178|0x30000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR3_IN178 input. */ + kXBAR3_InputGpt3IppDoCmpout1 = 179|0x30000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR3_IN179 input. */ + kXBAR3_InputGpt3IppDoCmpout2 = 180|0x30000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR3_IN180 input. */ + kXBAR3_InputGpt3IppDoCmpout3 = 181|0x30000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR3_IN181 input. */ + kXBAR3_InputGpt4IppDoCmpout1 = 182|0x30000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR3_IN182 input. */ + kXBAR3_InputGpt4IppDoCmpout2 = 183|0x30000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR3_IN183 input. */ + kXBAR3_InputGpt4IppDoCmpout3 = 184|0x30000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR3_IN184 input. */ + kXBAR3_InputFlexio1FlexioTriggerOut0 = 185|0x30000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN185 input. */ + kXBAR3_InputFlexio2FlexioTriggerOut0 = 186|0x30000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN186 input. */ + kXBAR3_InputFlexio3FlexioTriggerOut0 = 187|0x30000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN187 input. */ + kXBAR3_InputFlexio4FlexioTriggerOut0 = 188|0x30000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN188 input. */ + kXBAR3_InputGpio1IpiIntRgpio0 = 189|0x30000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR3_IN189 input. */ + kXBAR3_InputGpio2IpiIntRgpio0 = 190|0x30000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR3_IN190 input. */ + kXBAR3_InputGpio3IpiIntRgpio0 = 191|0x30000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR3_IN191 input. */ + kXBAR3_InputGpio4IpiIntRgpio0 = 192|0x30000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR3_IN192 input. */ + kXBAR3_InputGpio5IpiIntRgpio0 = 193|0x30000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR3_IN193 input. */ + kXBAR3_InputGpio6IpiIntRgpio0 = 194|0x30000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR3_IN194 input. */ + kXBAR3_InputGpio7IpiIntRgpio0 = 195|0x30000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR3_IN195 input. */ + kXBAR3_InputCm33Txev = 196|0x30000U, /**< CM33_TXEV output assigned to XBAR3_IN196 input. */ + kXBAR3_InputCm33SyncTxev = 197|0x30000U, /**< CM33_SYNC_TXEV output assigned to XBAR3_IN197 input. */ + kXBAR3_InputEndat21SiN = 198|0x30000U, /**< ENDAT2_1_SI_N output assigned to XBAR3_IN198 input. */ + kXBAR3_InputEndat21TimerN = 199|0x30000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR3_IN199 input. */ + kXBAR3_InputEndat22SiN = 200|0x30000U, /**< ENDAT2_2_SI_N output assigned to XBAR3_IN200 input. */ + kXBAR3_InputEndat22TimerN = 201|0x30000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR3_IN201 input. */ + kXBAR3_InputBissEot = 202|0x30000U, /**< BISS_EOT output assigned to XBAR3_IN202 input. */ + kXBAR3_InputEnc2PosMatch0 = 203|0x30000U, /**< ENC2_POS_MATCH0 output assigned to XBAR3_IN203 input. */ + kXBAR3_InputEnc2PosMatch1 = 204|0x30000U, /**< ENC2_POS_MATCH1 output assigned to XBAR3_IN204 input. */ + kXBAR3_InputEnc2PosMatch2 = 205|0x30000U, /**< ENC2_POS_MATCH2 output assigned to XBAR3_IN205 input. */ + kXBAR3_InputEnc2PosMatch3 = 206|0x30000U, /**< ENC2_POS_MATCH3 output assigned to XBAR3_IN206 input. */ + kXBAR3_InputEnc2CompFlg0 = 207|0x30000U, /**< ENC2_COMP_FLG0 output assigned to XBAR3_IN207 input. */ + kXBAR3_InputEnc2CompFlg1 = 208|0x30000U, /**< ENC2_COMP_FLG1 output assigned to XBAR3_IN208 input. */ + kXBAR3_InputEnc2CompFlg2 = 209|0x30000U, /**< ENC2_COMP_FLG2 output assigned to XBAR3_IN209 input. */ + kXBAR3_InputEnc2CompFlg3 = 210|0x30000U, /**< ENC2_COMP_FLG3 output assigned to XBAR3_IN210 input. */ + kXBAR3_InputEnc2CntDn = 211|0x30000U, /**< ENC2_CNT_DN output assigned to XBAR3_IN211 input. */ + kXBAR3_InputEnc2CntUp = 212|0x30000U, /**< ENC2_CNT_UP output assigned to XBAR3_IN212 input. */ + kXBAR3_InputEnc2Dir = 213|0x30000U, /**< ENC2_DIR output assigned to XBAR3_IN213 input. */ + kXBAR3_InputEnc4PosMatch0 = 214|0x30000U, /**< ENC4_POS_MATCH0 output assigned to XBAR3_IN214 input. */ + kXBAR3_InputEnc4PosMatch1 = 215|0x30000U, /**< ENC4_POS_MATCH1 output assigned to XBAR3_IN215 input. */ + kXBAR3_InputEnc4PosMatch2 = 216|0x30000U, /**< ENC4_POS_MATCH2 output assigned to XBAR3_IN216 input. */ + kXBAR3_InputEnc4PosMatch3 = 217|0x30000U, /**< ENC4_POS_MATCH3 output assigned to XBAR3_IN217 input. */ + kXBAR3_InputEnc4CompFlg0 = 218|0x30000U, /**< ENC4_COMP_FLG0 output assigned to XBAR3_IN218 input. */ + kXBAR3_InputEnc4CompFlg1 = 219|0x30000U, /**< ENC4_COMP_FLG1 output assigned to XBAR3_IN219 input. */ + kXBAR3_InputEnc4CompFlg2 = 220|0x30000U, /**< ENC4_COMP_FLG2 output assigned to XBAR3_IN220 input. */ + kXBAR3_InputEnc4CompFlg3 = 221|0x30000U, /**< ENC4_COMP_FLG3 output assigned to XBAR3_IN221 input. */ + kXBAR3_InputEnc4CntDn = 222|0x30000U, /**< ENC4_CNT_DN output assigned to XBAR3_IN222 input. */ + kXBAR3_InputEnc4CntUp = 223|0x30000U, /**< ENC4_CNT_UP output assigned to XBAR3_IN223 input. */ + kXBAR3_InputEnc4Dir = 224|0x30000U, /**< ENC4_DIR output assigned to XBAR3_IN224 input. */ + kXBAR3_InputHiperface1FastPosRcvdEvt = 225|0x30000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR3_IN225 input. */ + kXBAR3_InputHiperface2FastPosRcvdEvt = 226|0x30000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR3_IN226 input. */ +} xbar_input_signal_t; + +typedef enum _xbar_output_signal +{ + kXBAR1_OutputEdma4IpdReq76 = 0|0x10000U, /**< XBAR1_OUT0 output assigned to EDMA4_IPD_REQ76 */ + kXBAR1_OutputEdma4IpdReq77 = 1|0x10000U, /**< XBAR1_OUT1 output assigned to EDMA4_IPD_REQ77 */ + kXBAR1_OutputEdma4IpdReq78 = 2|0x10000U, /**< XBAR1_OUT2 output assigned to EDMA4_IPD_REQ78 */ + kXBAR1_OutputEdma4IpdReq79 = 3|0x10000U, /**< XBAR1_OUT3 output assigned to EDMA4_IPD_REQ79 */ + kXBAR1_OutputIomuxXbarOut04 = 4|0x10000U, /**< XBAR1_OUT4 output assigned to IOMUX_XBAR_OUT04 */ + kXBAR1_OutputIomuxXbarOut05 = 5|0x10000U, /**< XBAR1_OUT5 output assigned to IOMUX_XBAR_OUT05 */ + kXBAR1_OutputIomuxXbarOut06 = 6|0x10000U, /**< XBAR1_OUT6 output assigned to IOMUX_XBAR_OUT06 */ + kXBAR1_OutputIomuxXbarOut07 = 7|0x10000U, /**< XBAR1_OUT7 output assigned to IOMUX_XBAR_OUT07 */ + kXBAR1_OutputIomuxXbarOut08 = 8|0x10000U, /**< XBAR1_OUT8 output assigned to IOMUX_XBAR_OUT08 */ + kXBAR1_OutputIomuxXbarOut09 = 9|0x10000U, /**< XBAR1_OUT9 output assigned to IOMUX_XBAR_OUT09 */ + kXBAR1_OutputIomuxXbarOut10 = 10|0x10000U, /**< XBAR1_OUT10 output assigned to IOMUX_XBAR_OUT10 */ + kXBAR1_OutputIomuxXbarOut11 = 11|0x10000U, /**< XBAR1_OUT11 output assigned to IOMUX_XBAR_OUT11 */ + kXBAR1_OutputIomuxXbarOut12 = 12|0x10000U, /**< XBAR1_OUT12 output assigned to IOMUX_XBAR_OUT12 */ + kXBAR1_OutputIomuxXbarOut13 = 13|0x10000U, /**< XBAR1_OUT13 output assigned to IOMUX_XBAR_OUT13 */ + kXBAR1_OutputIomuxXbarOut14 = 14|0x10000U, /**< XBAR1_OUT14 output assigned to IOMUX_XBAR_OUT14 */ + kXBAR1_OutputIomuxXbarOut15 = 15|0x10000U, /**< XBAR1_OUT15 output assigned to IOMUX_XBAR_OUT15 */ + kXBAR1_OutputIomuxXbarOut16 = 16|0x10000U, /**< XBAR1_OUT16 output assigned to IOMUX_XBAR_OUT16 */ + kXBAR1_OutputIomuxXbarOut17 = 17|0x10000U, /**< XBAR1_OUT17 output assigned to IOMUX_XBAR_OUT17 */ + kXBAR1_OutputIomuxXbarOut18 = 18|0x10000U, /**< XBAR1_OUT18 output assigned to IOMUX_XBAR_OUT18 */ + kXBAR1_OutputIomuxXbarOut19 = 19|0x10000U, /**< XBAR1_OUT19 output assigned to IOMUX_XBAR_OUT19 */ + kXBAR1_OutputIomuxXbarOut20 = 20|0x10000U, /**< XBAR1_OUT20 output assigned to IOMUX_XBAR_OUT20 */ + kXBAR1_OutputIomuxXbarOut21 = 21|0x10000U, /**< XBAR1_OUT21 output assigned to IOMUX_XBAR_OUT21 */ + kXBAR1_OutputIomuxXbarOut22 = 22|0x10000U, /**< XBAR1_OUT22 output assigned to IOMUX_XBAR_OUT22 */ + kXBAR1_OutputIomuxXbarOut23 = 23|0x10000U, /**< XBAR1_OUT23 output assigned to IOMUX_XBAR_OUT23 */ + kXBAR1_OutputIomuxXbarOut24 = 24|0x10000U, /**< XBAR1_OUT24 output assigned to IOMUX_XBAR_OUT24 */ + kXBAR1_OutputIomuxXbarOut25 = 25|0x10000U, /**< XBAR1_OUT25 output assigned to IOMUX_XBAR_OUT25 */ + kXBAR1_OutputIomuxXbarOut26 = 26|0x10000U, /**< XBAR1_OUT26 output assigned to IOMUX_XBAR_OUT26 */ + kXBAR1_OutputIomuxXbarOut27 = 27|0x10000U, /**< XBAR1_OUT27 output assigned to IOMUX_XBAR_OUT27 */ + kXBAR1_OutputIomuxXbarOut28 = 28|0x10000U, /**< XBAR1_OUT28 output assigned to IOMUX_XBAR_OUT28 */ + kXBAR1_OutputIomuxXbarOut29 = 29|0x10000U, /**< XBAR1_OUT29 output assigned to IOMUX_XBAR_OUT29 */ + kXBAR1_OutputIomuxXbarOut30 = 30|0x10000U, /**< XBAR1_OUT30 output assigned to IOMUX_XBAR_OUT30 */ + kXBAR1_OutputIomuxXbarOut31 = 31|0x10000U, /**< XBAR1_OUT31 output assigned to IOMUX_XBAR_OUT31 */ + kXBAR1_OutputIomuxXbarOut32 = 32|0x10000U, /**< XBAR1_OUT32 output assigned to IOMUX_XBAR_OUT32 */ + kXBAR1_OutputIomuxXbarOut33 = 33|0x10000U, /**< XBAR1_OUT33 output assigned to IOMUX_XBAR_OUT33 */ + kXBAR1_OutputIomuxXbarOut34 = 34|0x10000U, /**< XBAR1_OUT34 output assigned to IOMUX_XBAR_OUT34 */ + kXBAR1_OutputIomuxXbarOut35 = 35|0x10000U, /**< XBAR1_OUT35 output assigned to IOMUX_XBAR_OUT35 */ + kXBAR1_OutputIomuxXbarOut36 = 36|0x10000U, /**< XBAR1_OUT36 output assigned to IOMUX_XBAR_OUT36 */ + kXBAR1_OutputIomuxXbarOut37 = 37|0x10000U, /**< XBAR1_OUT37 output assigned to IOMUX_XBAR_OUT37 */ + kXBAR1_OutputIomuxXbarOut38 = 38|0x10000U, /**< XBAR1_OUT38 output assigned to IOMUX_XBAR_OUT38 */ + kXBAR1_OutputIomuxXbarOut39 = 39|0x10000U, /**< XBAR1_OUT39 output assigned to IOMUX_XBAR_OUT39 */ + kXBAR1_OutputIomuxXbarOut40 = 40|0x10000U, /**< XBAR1_OUT40 output assigned to IOMUX_XBAR_OUT40 */ + kXBAR1_OutputTriggerSyncAsyncIn0 = 41|0x10000U, /**< XBAR1_OUT41 output assigned to TRIGGER_SYNC_ASYNC_IN0 */ + kXBAR1_OutputTriggerSyncAsyncIn1 = 42|0x10000U, /**< XBAR1_OUT42 output assigned to TRIGGER_SYNC_ASYNC_IN1 */ + kXBAR1_OutputTriggerSyncAsyncIn2 = 43|0x10000U, /**< XBAR1_OUT43 output assigned to TRIGGER_SYNC_ASYNC_IN2 */ + kXBAR1_OutputTriggerSyncAsyncIn3 = 44|0x10000U, /**< XBAR1_OUT44 output assigned to TRIGGER_SYNC_ASYNC_IN3 */ + kXBAR1_OutputTriggerSyncAsyncIn4 = 45|0x10000U, /**< XBAR1_OUT45 output assigned to TRIGGER_SYNC_ASYNC_IN4 */ + kXBAR1_OutputTriggerSyncAsyncIn5 = 46|0x10000U, /**< XBAR1_OUT46 output assigned to TRIGGER_SYNC_ASYNC_IN5 */ + kXBAR1_OutputTriggerSyncAsyncIn6 = 47|0x10000U, /**< XBAR1_OUT47 output assigned to TRIGGER_SYNC_ASYNC_IN6 */ + kXBAR1_OutputTriggerSyncAsyncIn7 = 48|0x10000U, /**< XBAR1_OUT48 output assigned to TRIGGER_SYNC_ASYNC_IN7 */ + kXBAR1_OutputFlexpwm1Exta0 = 49|0x10000U, /**< XBAR1_OUT49 output assigned to FLEXPWM1_EXTA0 */ + kXBAR1_OutputFlexpwm1Exta1 = 50|0x10000U, /**< XBAR1_OUT50 output assigned to FLEXPWM1_EXTA1 */ + kXBAR1_OutputFlexpwm1Exta2 = 51|0x10000U, /**< XBAR1_OUT51 output assigned to FLEXPWM1_EXTA2 */ + kXBAR1_OutputFlexpwm1Exta3 = 52|0x10000U, /**< XBAR1_OUT52 output assigned to FLEXPWM1_EXTA3 */ + kXBAR1_OutputFlexpwm1ExtSync0 = 53|0x10000U, /**< XBAR1_OUT53 output assigned to FLEXPWM1_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm1ExtSync1 = 54|0x10000U, /**< XBAR1_OUT54 output assigned to FLEXPWM1_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm1ExtSync2 = 55|0x10000U, /**< XBAR1_OUT55 output assigned to FLEXPWM1_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm1ExtSync3 = 56|0x10000U, /**< XBAR1_OUT56 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm1ExtClk = 57|0x10000U, /**< XBAR1_OUT57 output assigned to FLEXPWM1_EXT_CLK */ + kXBAR1_OutputFlexpwm1IppIndFault0 = 58|0x10000U, /**< XBAR1_OUT58 output assigned to FLEXPWM1_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm1IppIndFault1 = 59|0x10000U, /**< XBAR1_OUT59 output assigned to FLEXPWM1_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm1IppIndFault2 = 60|0x10000U, /**< XBAR1_OUT60 output assigned to FLEXPWM1_IPP_IND_FAULT2 */ + kXBAR1_OutputFlexpwm1IppIndFault3 = 61|0x10000U, /**< XBAR1_OUT61 output assigned to FLEXPWM1_IPP_IND_FAULT3 */ + kXBAR1_OutputFlexpwm1ExtForce = 62|0x10000U, /**< XBAR1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */ + kXBAR1_OutputFlexpwm2Exta0 = 63|0x10000U, /**< XBAR1_OUT63 output assigned to FLEXPWM2_EXTA0 */ + kXBAR1_OutputFlexpwm2Exta1 = 64|0x10000U, /**< XBAR1_OUT64 output assigned to FLEXPWM2_EXTA1 */ + kXBAR1_OutputFlexpwm2Exta2 = 65|0x10000U, /**< XBAR1_OUT65 output assigned to FLEXPWM2_EXTA2 */ + kXBAR1_OutputFlexpwm2Exta3 = 66|0x10000U, /**< XBAR1_OUT66 output assigned to FLEXPWM2_EXTA3 */ + kXBAR1_OutputFlexpwm2ExtSync0 = 67|0x10000U, /**< XBAR1_OUT67 output assigned to FLEXPWM2_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm2ExtSync1 = 68|0x10000U, /**< XBAR1_OUT68 output assigned to FLEXPWM2_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm2ExtSync2 = 69|0x10000U, /**< XBAR1_OUT69 output assigned to FLEXPWM2_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm2ExtSync3 = 70|0x10000U, /**< XBAR1_OUT70 output assigned to FLEXPWM2_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm2ExtClk = 71|0x10000U, /**< XBAR1_OUT71 output assigned to FLEXPWM2_EXT_CLK */ + kXBAR1_OutputFlexpwm2IppIndFault0 = 72|0x10000U, /**< XBAR1_OUT72 output assigned to FLEXPWM2_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm2IppIndFault1 = 73|0x10000U, /**< XBAR1_OUT73 output assigned to FLEXPWM2_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm2ExtForce = 74|0x10000U, /**< XBAR1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */ + kXBAR1_OutputFlexpwm3Exta0 = 75|0x10000U, /**< XBAR1_OUT75 output assigned to FLEXPWM3_EXTA0 */ + kXBAR1_OutputFlexpwm3Exta1 = 76|0x10000U, /**< XBAR1_OUT76 output assigned to FLEXPWM3_EXTA1 */ + kXBAR1_OutputFlexpwm3Exta2 = 77|0x10000U, /**< XBAR1_OUT77 output assigned to FLEXPWM3_EXTA2 */ + kXBAR1_OutputFlexpwm3Exta3 = 78|0x10000U, /**< XBAR1_OUT78 output assigned to FLEXPWM3_EXTA3 */ + kXBAR1_OutputFlexpwm3ExtClk = 79|0x10000U, /**< XBAR1_OUT79 output assigned to FLEXPWM3_EXT_CLK */ + kXBAR1_OutputFlexpwm3ExtSync0 = 80|0x10000U, /**< XBAR1_OUT80 output assigned to FLEXPWM3_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm3ExtSync1 = 81|0x10000U, /**< XBAR1_OUT81 output assigned to FLEXPWM3_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm3ExtSync2 = 82|0x10000U, /**< XBAR1_OUT82 output assigned to FLEXPWM3_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm3ExtSync3 = 83|0x10000U, /**< XBAR1_OUT83 output assigned to FLEXPWM3_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm3IppIndFault0 = 84|0x10000U, /**< XBAR1_OUT84 output assigned to FLEXPWM3_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm3IppIndFault1 = 85|0x10000U, /**< XBAR1_OUT85 output assigned to FLEXPWM3_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm3ExtForce = 86|0x10000U, /**< XBAR1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */ + kXBAR1_OutputFlexpwm4ExtSync0 = 87|0x10000U, /**< XBAR1_OUT87 output assigned to FLEXPWM4_EXT_SYNC0 */ + kXBAR1_OutputFlexpwm4ExtSync1 = 88|0x10000U, /**< XBAR1_OUT88 output assigned to FLEXPWM4_EXT_SYNC1 */ + kXBAR1_OutputFlexpwm4ExtSync2 = 89|0x10000U, /**< XBAR1_OUT89 output assigned to FLEXPWM4_EXT_SYNC2 */ + kXBAR1_OutputFlexpwm4ExtSync3 = 90|0x10000U, /**< XBAR1_OUT90 output assigned to FLEXPWM4_EXT_SYNC3 */ + kXBAR1_OutputFlexpwm4IppIndFault0 = 91|0x10000U, /**< XBAR1_OUT91 output assigned to FLEXPWM4_IPP_IND_FAULT0 */ + kXBAR1_OutputFlexpwm4IppIndFault1 = 92|0x10000U, /**< XBAR1_OUT92 output assigned to FLEXPWM4_IPP_IND_FAULT1 */ + kXBAR1_OutputFlexpwm4ExtForce = 93|0x10000U, /**< XBAR1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */ + kXBAR1_OutputEnc1PhaseAInput = 94|0x10000U, /**< XBAR1_OUT94 output assigned to ENC1_PHASE_A_INPUT */ + kXBAR1_OutputEnc1PhaseBInput = 95|0x10000U, /**< XBAR1_OUT95 output assigned to ENC1_PHASE_B_INPUT */ + kXBAR1_OutputEnc1Index = 96|0x10000U, /**< XBAR1_OUT96 output assigned to ENC1_INDEX */ + kXBAR1_OutputEnc1Home = 97|0x10000U, /**< XBAR1_OUT97 output assigned to ENC1_HOME */ + kXBAR1_OutputEnc1Trigger = 98|0x10000U, /**< XBAR1_OUT98 output assigned to ENC1_TRIGGER */ + kXBAR1_OutputEnc2PhaseAInput = 99|0x10000U, /**< XBAR1_OUT99 output assigned to ENC2_PHASE_A_INPUT */ + kXBAR1_OutputEnc2PhaseBInput = 100|0x10000U, /**< XBAR1_OUT100 output assigned to ENC2_PHASE_B_INPUT */ + kXBAR1_OutputEnc2Index = 101|0x10000U, /**< XBAR1_OUT101 output assigned to ENC2_INDEX */ + kXBAR1_OutputEnc2Home = 102|0x10000U, /**< XBAR1_OUT102 output assigned to ENC2_HOME */ + kXBAR1_OutputEnc2Trigger = 103|0x10000U, /**< XBAR1_OUT103 output assigned to ENC2_TRIGGER */ + kXBAR1_OutputEnc3PhaseAInput = 104|0x10000U, /**< XBAR1_OUT104 output assigned to ENC3_PHASE_A_INPUT */ + kXBAR1_OutputEnc3PhaseBInput = 105|0x10000U, /**< XBAR1_OUT105 output assigned to ENC3_PHASE_B_INPUT */ + kXBAR1_OutputEnc3Index = 106|0x10000U, /**< XBAR1_OUT106 output assigned to ENC3_INDEX */ + kXBAR1_OutputEnc3Home = 107|0x10000U, /**< XBAR1_OUT107 output assigned to ENC3_HOME */ + kXBAR1_OutputEnc3Trigger = 108|0x10000U, /**< XBAR1_OUT108 output assigned to ENC3_TRIGGER */ + kXBAR1_OutputEnc4PhaseAInput = 109|0x10000U, /**< XBAR1_OUT109 output assigned to ENC4_PHASE_A_INPUT */ + kXBAR1_OutputEnc4PhaseBInput = 110|0x10000U, /**< XBAR1_OUT110 output assigned to ENC4_PHASE_B_INPUT */ + kXBAR1_OutputEnc4Index = 111|0x10000U, /**< XBAR1_OUT111 output assigned to ENC4_INDEX */ + kXBAR1_OutputEnc4Home = 112|0x10000U, /**< XBAR1_OUT112 output assigned to ENC4_HOME */ + kXBAR1_OutputEnc4Trigger = 113|0x10000U, /**< XBAR1_OUT113 output assigned to ENC4_TRIGGER */ + kXBAR1_OutputQtimer1Tmr0Input = 114|0x10000U, /**< XBAR1_OUT114 output assigned to QTIMER1_TMR0_INPUT */ + kXBAR1_OutputQtimer1Tmr1Input = 115|0x10000U, /**< XBAR1_OUT115 output assigned to QTIMER1_TMR1_INPUT */ + kXBAR1_OutputQtimer1Tmr2Input = 116|0x10000U, /**< XBAR1_OUT116 output assigned to QTIMER1_TMR2_INPUT */ + kXBAR1_OutputQtimer1Tmr3Input = 117|0x10000U, /**< XBAR1_OUT117 output assigned to QTIMER1_TMR3_INPUT */ + kXBAR1_OutputQtimer2Tmr0Input = 118|0x10000U, /**< XBAR1_OUT118 output assigned to QTIMER2_TMR0_INPUT */ + kXBAR1_OutputQtimer2Tmr1Input = 119|0x10000U, /**< XBAR1_OUT119 output assigned to QTIMER2_TMR1_INPUT */ + kXBAR1_OutputQtimer2Tmr2Input = 120|0x10000U, /**< XBAR1_OUT120 output assigned to QTIMER2_TMR2_INPUT */ + kXBAR1_OutputQtimer2Tmr3Input = 121|0x10000U, /**< XBAR1_OUT121 output assigned to QTIMER2_TMR3_INPUT */ + kXBAR1_OutputQtimer3Tmr0Input = 122|0x10000U, /**< XBAR1_OUT122 output assigned to QTIMER3_TMR0_INPUT */ + kXBAR1_OutputQtimer3Tmr1Input = 123|0x10000U, /**< XBAR1_OUT123 output assigned to QTIMER3_TMR1_INPUT */ + kXBAR1_OutputQtimer3Tmr2Input = 124|0x10000U, /**< XBAR1_OUT124 output assigned to QTIMER3_TMR2_INPUT */ + kXBAR1_OutputQtimer3Tmr3Input = 125|0x10000U, /**< XBAR1_OUT125 output assigned to QTIMER3_TMR3_INPUT */ + kXBAR1_OutputQtimer4Tmr0Input = 126|0x10000U, /**< XBAR1_OUT126 output assigned to QTIMER4_TMR0_INPUT */ + kXBAR1_OutputQtimer4Tmr1Input = 127|0x10000U, /**< XBAR1_OUT127 output assigned to QTIMER4_TMR1_INPUT */ + kXBAR1_OutputQtimer4Tmr2Input = 128|0x10000U, /**< XBAR1_OUT128 output assigned to QTIMER4_TMR2_INPUT */ + kXBAR1_OutputQtimer4Tmr3Input = 129|0x10000U, /**< XBAR1_OUT129 output assigned to QTIMER4_TMR3_INPUT */ + kXBAR1_OutputQtimer5Tmr0Input = 130|0x10000U, /**< XBAR1_OUT130 output assigned to QTIMER5_TMR0_INPUT */ + kXBAR1_OutputQtimer5Tmr1Input = 131|0x10000U, /**< XBAR1_OUT131 output assigned to QTIMER5_TMR1_INPUT */ + kXBAR1_OutputQtimer5Tmr2Input = 132|0x10000U, /**< XBAR1_OUT132 output assigned to QTIMER5_TMR2_INPUT */ + kXBAR1_OutputQtimer5Tmr3Input = 133|0x10000U, /**< XBAR1_OUT133 output assigned to QTIMER5_TMR3_INPUT */ + kXBAR1_OutputQtimer6Tmr0Input = 134|0x10000U, /**< XBAR1_OUT134 output assigned to QTIMER6_TMR0_INPUT */ + kXBAR1_OutputQtimer6Tmr1Input = 135|0x10000U, /**< XBAR1_OUT135 output assigned to QTIMER6_TMR1_INPUT */ + kXBAR1_OutputQtimer6Tmr2Input = 136|0x10000U, /**< XBAR1_OUT136 output assigned to QTIMER6_TMR2_INPUT */ + kXBAR1_OutputQtimer6Tmr3Input = 137|0x10000U, /**< XBAR1_OUT137 output assigned to QTIMER6_TMR3_INPUT */ + kXBAR1_OutputQtimer7Tmr0Input = 138|0x10000U, /**< XBAR1_OUT138 output assigned to QTIMER7_TMR0_INPUT */ + kXBAR1_OutputQtimer7Tmr1Input = 139|0x10000U, /**< XBAR1_OUT139 output assigned to QTIMER7_TMR1_INPUT */ + kXBAR1_OutputQtimer7Tmr2Input = 140|0x10000U, /**< XBAR1_OUT140 output assigned to QTIMER7_TMR2_INPUT */ + kXBAR1_OutputQtimer7Tmr3Input = 141|0x10000U, /**< XBAR1_OUT141 output assigned to QTIMER7_TMR3_INPUT */ + kXBAR1_OutputQtimer8Tmr0Input = 142|0x10000U, /**< XBAR1_OUT142 output assigned to QTIMER8_TMR0_INPUT */ + kXBAR1_OutputQtimer8Tmr1Input = 143|0x10000U, /**< XBAR1_OUT143 output assigned to QTIMER8_TMR1_INPUT */ + kXBAR1_OutputQtimer8Tmr2Input = 144|0x10000U, /**< XBAR1_OUT144 output assigned to QTIMER8_TMR2_INPUT */ + kXBAR1_OutputQtimer8Tmr3Input = 145|0x10000U, /**< XBAR1_OUT145 output assigned to QTIMER8_TMR3_INPUT */ + kXBAR1_OutputEwmEwmIn = 146|0x10000U, /**< XBAR1_OUT146 output assigned to EWM_EWM_IN */ + kXBAR1_OutputAnamixGlueTrgmuxInjectionTrg = 147|0x10000U, /**< XBAR1_OUT147 output assigned to ANAMIX_GLUE_TRGMUX_INJECTION_TRG */ + kXBAR1_OutputAnamixGlueTrgmuxStartTrg = 148|0x10000U, /**< XBAR1_OUT148 output assigned to ANAMIX_GLUE_TRGMUX_START_TRG */ + kXBAR1_OutputSinc1ExtTrigger0 = 149|0x10000U, /**< XBAR1_OUT149 output assigned to SINC1_EXT_TRIGGER0 */ + kXBAR1_OutputSinc1ExtTrigger1 = 150|0x10000U, /**< XBAR1_OUT150 output assigned to SINC1_EXT_TRIGGER1 */ + kXBAR1_OutputSinc1ExtTrigger2 = 151|0x10000U, /**< XBAR1_OUT151 output assigned to SINC1_EXT_TRIGGER2 */ + kXBAR1_OutputSinc1ExtTrigger3 = 152|0x10000U, /**< XBAR1_OUT152 output assigned to SINC1_EXT_TRIGGER3 */ + kXBAR1_OutputFlexio1FlexioTriggerIn0 = 153|0x10000U, /**< XBAR1_OUT153 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio1FlexioTriggerIn1 = 154|0x10000U, /**< XBAR1_OUT154 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio2FlexioTriggerIn0 = 155|0x10000U, /**< XBAR1_OUT155 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio2FlexioTriggerIn1 = 156|0x10000U, /**< XBAR1_OUT156 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio3FlexioTriggerIn0 = 157|0x10000U, /**< XBAR1_OUT157 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio3FlexioTriggerIn1 = 158|0x10000U, /**< XBAR1_OUT158 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputFlexio4FlexioTriggerIn0 = 159|0x10000U, /**< XBAR1_OUT159 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN0 */ + kXBAR1_OutputFlexio4FlexioTriggerIn1 = 160|0x10000U, /**< XBAR1_OUT160 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN1 */ + kXBAR1_OutputLpi2c1Lpi2cTrgInput = 161|0x10000U, /**< XBAR1_OUT161 output assigned to LPI2C1_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c2Lpi2cTrgInput = 162|0x10000U, /**< XBAR1_OUT162 output assigned to LPI2C2_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c3Lpi2cTrgInput = 163|0x10000U, /**< XBAR1_OUT163 output assigned to LPI2C3_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c4Lpi2cTrgInput = 164|0x10000U, /**< XBAR1_OUT164 output assigned to LPI2C4_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c5Lpi2cTrgInput = 165|0x10000U, /**< XBAR1_OUT165 output assigned to LPI2C5_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c6Lpi2cTrgInput = 166|0x10000U, /**< XBAR1_OUT166 output assigned to LPI2C6_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c7Lpi2cTrgInput = 167|0x10000U, /**< XBAR1_OUT167 output assigned to LPI2C7_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpi2c8Lpi2cTrgInput = 168|0x10000U, /**< XBAR1_OUT168 output assigned to LPI2C8_LPI2C_TRG_INPUT */ + kXBAR1_OutputLpspi1LpspiTrgInput = 169|0x10000U, /**< XBAR1_OUT169 output assigned to LPSPI1_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi2LpspiTrgInput = 170|0x10000U, /**< XBAR1_OUT170 output assigned to LPSPI2_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi3LpspiTrgInput = 171|0x10000U, /**< XBAR1_OUT171 output assigned to LPSPI3_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi4LpspiTrgInput = 172|0x10000U, /**< XBAR1_OUT172 output assigned to LPSPI4_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi5LpspiTrgInput = 173|0x10000U, /**< XBAR1_OUT173 output assigned to LPSPI5_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi6LpspiTrgInput = 174|0x10000U, /**< XBAR1_OUT174 output assigned to LPSPI6_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi7LpspiTrgInput = 175|0x10000U, /**< XBAR1_OUT175 output assigned to LPSPI7_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpspi8LpspiTrgInput = 176|0x10000U, /**< XBAR1_OUT176 output assigned to LPSPI8_LPSPI_TRG_INPUT */ + kXBAR1_OutputLpuart1LpuartTrgInput = 177|0x10000U, /**< XBAR1_OUT177 output assigned to LPUART1_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart2LpuartTrgInput = 178|0x10000U, /**< XBAR1_OUT178 output assigned to LPUART2_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart3LpuartTrgInput = 179|0x10000U, /**< XBAR1_OUT179 output assigned to LPUART3_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart4LpuartTrgInput = 180|0x10000U, /**< XBAR1_OUT180 output assigned to LPUART4_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart5LpuartTrgInput = 181|0x10000U, /**< XBAR1_OUT181 output assigned to LPUART5_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart6LpuartTrgInput = 182|0x10000U, /**< XBAR1_OUT182 output assigned to LPUART6_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart7LpuartTrgInput = 183|0x10000U, /**< XBAR1_OUT183 output assigned to LPUART7_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart8LpuartTrgInput = 184|0x10000U, /**< XBAR1_OUT184 output assigned to LPUART8_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart9LpuartTrgInput = 185|0x10000U, /**< XBAR1_OUT185 output assigned to LPUART9_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart10LpuartTrgInput = 186|0x10000U, /**< XBAR1_OUT186 output assigned to LPUART10_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart11LpuartTrgInput = 187|0x10000U, /**< XBAR1_OUT187 output assigned to LPUART11_LPUART_TRG_INPUT */ + kXBAR1_OutputLpuart12LpuartTrgInput = 188|0x10000U, /**< XBAR1_OUT188 output assigned to LPUART12_LPUART_TRG_INPUT */ + kXBAR1_OutputLpit1LpitExtTrigIn0 = 189|0x10000U, /**< XBAR1_OUT189 output assigned to LPIT1_LPIT_EXT_TRIG_IN0 */ + kXBAR1_OutputLpit1LpitExtTrigIn1 = 190|0x10000U, /**< XBAR1_OUT190 output assigned to LPIT1_LPIT_EXT_TRIG_IN1 */ + kXBAR1_OutputLpit1LpitExtTrigIn2 = 191|0x10000U, /**< XBAR1_OUT191 output assigned to LPIT1_LPIT_EXT_TRIG_IN2 */ + kXBAR1_OutputLpit1LpitExtTrigIn3 = 192|0x10000U, /**< XBAR1_OUT192 output assigned to LPIT1_LPIT_EXT_TRIG_IN3 */ + kXBAR1_OutputTpm1LptpmTriggerIn0 = 193|0x10000U, /**< XBAR1_OUT193 output assigned to TPM1_LPTPM_TRIGGER_IN0 */ + kXBAR1_OutputTpm1LptpmTriggerIn1 = 194|0x10000U, /**< XBAR1_OUT194 output assigned to TPM1_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm2LptpmTriggerIn1 = 195|0x10000U, /**< XBAR1_OUT195 output assigned to TPM2_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm3LptpmTriggerIn1 = 196|0x10000U, /**< XBAR1_OUT196 output assigned to TPM3_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm1LptpmTriggerIn2 = 197|0x10000U, /**< XBAR1_OUT197 output assigned to TPM1_LPTPM_TRIGGER_IN2 */ + kXBAR1_OutputTpm1LptpmTriggerIn3 = 198|0x10000U, /**< XBAR1_OUT198 output assigned to TPM1_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm2LptpmTriggerIn3 = 199|0x10000U, /**< XBAR1_OUT199 output assigned to TPM2_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm3LptpmTriggerIn3 = 200|0x10000U, /**< XBAR1_OUT200 output assigned to TPM3_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm4LptpmTriggerIn0 = 201|0x10000U, /**< XBAR1_OUT201 output assigned to TPM4_LPTPM_TRIGGER_IN0 */ + kXBAR1_OutputTpm4LptpmTriggerIn1 = 202|0x10000U, /**< XBAR1_OUT202 output assigned to TPM4_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm5LptpmTriggerIn1 = 203|0x10000U, /**< XBAR1_OUT203 output assigned to TPM5_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm6LptpmTriggerIn1 = 204|0x10000U, /**< XBAR1_OUT204 output assigned to TPM6_LPTPM_TRIGGER_IN1 */ + kXBAR1_OutputTpm4LptpmTriggerIn2 = 205|0x10000U, /**< XBAR1_OUT205 output assigned to TPM4_LPTPM_TRIGGER_IN2 */ + kXBAR1_OutputTpm4LptpmTriggerIn3 = 206|0x10000U, /**< XBAR1_OUT206 output assigned to TPM4_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm5LptpmTriggerIn3 = 207|0x10000U, /**< XBAR1_OUT207 output assigned to TPM5_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputTpm6LptpmTriggerIn3 = 208|0x10000U, /**< XBAR1_OUT208 output assigned to TPM6_LPTPM_TRIGGER_IN3 */ + kXBAR1_OutputNetcTmr11588Trig1 = 209|0x10000U, /**< XBAR1_OUT209 output assigned to NETC_TMR1_1588_TRIG1 */ + kXBAR1_OutputNetcTmr11588Trig2 = 210|0x10000U, /**< XBAR1_OUT210 output assigned to NETC_TMR1_1588_TRIG2 */ + kXBAR1_OutputNetcTmr21588Trig1 = 211|0x10000U, /**< XBAR1_OUT211 output assigned to NETC_TMR2_1588_TRIG1 */ + kXBAR1_OutputNetcTmr21588Trig2 = 212|0x10000U, /**< XBAR1_OUT212 output assigned to NETC_TMR2_1588_TRIG2 */ + kXBAR1_OutputNetcTmr31588Trig1 = 213|0x10000U, /**< XBAR1_OUT213 output assigned to NETC_TMR3_1588_TRIG1 */ + kXBAR1_OutputNetcTmr31588Trig2 = 214|0x10000U, /**< XBAR1_OUT214 output assigned to NETC_TMR3_1588_TRIG2 */ + kXBAR1_OutputEnc1Icap1 = 215|0x10000U, /**< XBAR1_OUT215 output assigned to ENC1_ICAP1 */ + kXBAR1_OutputEnc1Icap2 = 216|0x10000U, /**< XBAR1_OUT216 output assigned to ENC1_ICAP2 */ + kXBAR1_OutputEnc1Icap3 = 217|0x10000U, /**< XBAR1_OUT217 output assigned to ENC1_ICAP3 */ + kXBAR1_OutputEnc2Icap1 = 218|0x10000U, /**< XBAR1_OUT218 output assigned to ENC2_ICAP1 */ + kXBAR1_OutputEnc2Icap2 = 219|0x10000U, /**< XBAR1_OUT219 output assigned to ENC2_ICAP2 */ + kXBAR1_OutputEnc2Icap3 = 220|0x10000U, /**< XBAR1_OUT220 output assigned to ENC2_ICAP3 */ + kXBAR1_OutputEnc3Icap1 = 221|0x10000U, /**< XBAR1_OUT221 output assigned to ENC3_ICAP1 */ + kXBAR1_OutputEnc3Icap2 = 222|0x10000U, /**< XBAR1_OUT222 output assigned to ENC3_ICAP2 */ + kXBAR1_OutputEnc3Icap3 = 223|0x10000U, /**< XBAR1_OUT223 output assigned to ENC3_ICAP3 */ + kXBAR1_OutputEnc4Icap1 = 224|0x10000U, /**< XBAR1_OUT224 output assigned to ENC4_ICAP1 */ + kXBAR1_OutputEnc4Icap2 = 225|0x10000U, /**< XBAR1_OUT225 output assigned to ENC4_ICAP2 */ + kXBAR1_OutputEnc4Icap3 = 226|0x10000U, /**< XBAR1_OUT226 output assigned to ENC4_ICAP3 */ + kXBAR1_OutputEcatLatchIn0 = 227|0x10000U, /**< XBAR1_OUT227 output assigned to ECAT_LATCH_IN0 */ + kXBAR1_OutputEcatLatchIn1 = 228|0x10000U, /**< XBAR1_OUT228 output assigned to ECAT_LATCH_IN1 */ + kXBAR1_OutputSafetyClkMonDutClk = 229|0x10000U, /**< XBAR1_OUT229 output assigned to SAFETY_CLK_MON_DUT_CLK */ + kXBAR1_OutputEndat21StrN = 230|0x10000U, /**< XBAR1_OUT230 output assigned to ENDAT2_1_STR_N */ + kXBAR1_OutputEndat21Ir6N = 231|0x10000U, /**< XBAR1_OUT231 output assigned to ENDAT2_1_IR6_N */ + kXBAR1_OutputEndat21Ir7N = 232|0x10000U, /**< XBAR1_OUT232 output assigned to ENDAT2_1_IR7_N */ + kXBAR1_OutputEndat22StrN = 233|0x10000U, /**< XBAR1_OUT233 output assigned to ENDAT2_2_STR_N */ + kXBAR1_OutputEndat22Ir6N = 234|0x10000U, /**< XBAR1_OUT234 output assigned to ENDAT2_2_IR6_N */ + kXBAR1_OutputEndat22Ir7N = 235|0x10000U, /**< XBAR1_OUT235 output assigned to ENDAT2_2_IR7_N */ + kXBAR1_OutputEndat3HwStrobe = 236|0x10000U, /**< XBAR1_OUT236 output assigned to ENDAT3_HW_STROBE */ + kXBAR1_OutputBissGetsens = 237|0x10000U, /**< XBAR1_OUT237 output assigned to BISS_GETSENS */ + kXBAR1_OutputSinc3ExtTrigger2 = 238|0x10000U, /**< XBAR1_OUT238 output assigned to SINC3_EXT_TRIGGER2 */ + kXBAR1_OutputSinc3ExtTrigger3 = 239|0x10000U, /**< XBAR1_OUT239 output assigned to SINC3_EXT_TRIGGER3 */ + kXBAR1_OutputHiperface1SyncXbar = 240|0x10000U, /**< XBAR1_OUT240 output assigned to HIPERFACE1_SYNC_XBAR */ + kXBAR1_OutputHiperface2SyncXbar = 241|0x10000U, /**< XBAR1_OUT241 output assigned to HIPERFACE2_SYNC_XBAR */ + kXBAR1_OutputTriggerSyncAsyncIn8 = 242|0x10000U, /**< XBAR1_OUT242 output assigned to TRIGGER_SYNC_ASYNC_IN8 */ + kXBAR1_OutputTriggerSyncAsyncIn9 = 243|0x10000U, /**< XBAR1_OUT243 output assigned to TRIGGER_SYNC_ASYNC_IN9 */ + kXBAR1_OutputTriggerSyncAsyncIn10 = 244|0x10000U, /**< XBAR1_OUT244 output assigned to TRIGGER_SYNC_ASYNC_IN10 */ + kXBAR1_OutputTriggerSyncAsyncIn11 = 245|0x10000U, /**< XBAR1_OUT245 output assigned to TRIGGER_SYNC_ASYNC_IN11 */ + kXBAR1_OutputTriggerSyncAsyncIn12 = 246|0x10000U, /**< XBAR1_OUT246 output assigned to TRIGGER_SYNC_ASYNC_IN12 */ + kXBAR1_OutputTriggerSyncAsyncIn13 = 247|0x10000U, /**< XBAR1_OUT247 output assigned to TRIGGER_SYNC_ASYNC_IN13 */ + kXBAR1_OutputTriggerSyncAsyncIn14 = 248|0x10000U, /**< XBAR1_OUT248 output assigned to TRIGGER_SYNC_ASYNC_IN14 */ + kXBAR1_OutputTriggerSyncAsyncIn15 = 249|0x10000U, /**< XBAR1_OUT249 output assigned to TRIGGER_SYNC_ASYNC_IN15 */ + kXBAR1_OutputSinc2ExtTrigger0 = 250|0x10000U, /**< XBAR1_OUT250 output assigned to SINC2_EXT_TRIGGER0 */ + kXBAR1_OutputSinc2ExtTrigger1 = 251|0x10000U, /**< XBAR1_OUT251 output assigned to SINC2_EXT_TRIGGER1 */ + kXBAR1_OutputSinc2ExtTrigger2 = 252|0x10000U, /**< XBAR1_OUT252 output assigned to SINC2_EXT_TRIGGER2 */ + kXBAR1_OutputSinc2ExtTrigger3 = 253|0x10000U, /**< XBAR1_OUT253 output assigned to SINC2_EXT_TRIGGER3 */ + kXBAR1_OutputSinc3ExtTrigger0 = 254|0x10000U, /**< XBAR1_OUT254 output assigned to SINC3_EXT_TRIGGER0 */ + kXBAR1_OutputSinc3ExtTrigger1 = 255|0x10000U, /**< XBAR1_OUT255 output assigned to SINC3_EXT_TRIGGER1 */ + kXBAR2_OutputAoi1In00 = 0|0x20000U, /**< XBAR2_OUT0 output assigned to AOI1_IN00 */ + kXBAR2_OutputAoi1In01 = 1|0x20000U, /**< XBAR2_OUT1 output assigned to AOI1_IN01 */ + kXBAR2_OutputAoi1In02 = 2|0x20000U, /**< XBAR2_OUT2 output assigned to AOI1_IN02 */ + kXBAR2_OutputAoi1In03 = 3|0x20000U, /**< XBAR2_OUT3 output assigned to AOI1_IN03 */ + kXBAR2_OutputAoi1In04 = 4|0x20000U, /**< XBAR2_OUT4 output assigned to AOI1_IN04 */ + kXBAR2_OutputAoi1In05 = 5|0x20000U, /**< XBAR2_OUT5 output assigned to AOI1_IN05 */ + kXBAR2_OutputAoi1In06 = 6|0x20000U, /**< XBAR2_OUT6 output assigned to AOI1_IN06 */ + kXBAR2_OutputAoi1In07 = 7|0x20000U, /**< XBAR2_OUT7 output assigned to AOI1_IN07 */ + kXBAR2_OutputAoi1In08 = 8|0x20000U, /**< XBAR2_OUT8 output assigned to AOI1_IN08 */ + kXBAR2_OutputAoi1In09 = 9|0x20000U, /**< XBAR2_OUT9 output assigned to AOI1_IN09 */ + kXBAR2_OutputAoi1In10 = 10|0x20000U, /**< XBAR2_OUT10 output assigned to AOI1_IN10 */ + kXBAR2_OutputAoi1In11 = 11|0x20000U, /**< XBAR2_OUT11 output assigned to AOI1_IN11 */ + kXBAR2_OutputAoi1In12 = 12|0x20000U, /**< XBAR2_OUT12 output assigned to AOI1_IN12 */ + kXBAR2_OutputAoi1In13 = 13|0x20000U, /**< XBAR2_OUT13 output assigned to AOI1_IN13 */ + kXBAR2_OutputAoi1In14 = 14|0x20000U, /**< XBAR2_OUT14 output assigned to AOI1_IN14 */ + kXBAR2_OutputAoi1In15 = 15|0x20000U, /**< XBAR2_OUT15 output assigned to AOI1_IN15 */ + kXBAR2_OutputAoi3In00 = 16|0x20000U, /**< XBAR2_OUT16 output assigned to AOI3_IN00 */ + kXBAR2_OutputAoi3In01 = 17|0x20000U, /**< XBAR2_OUT17 output assigned to AOI3_IN01 */ + kXBAR2_OutputAoi3In02 = 18|0x20000U, /**< XBAR2_OUT18 output assigned to AOI3_IN02 */ + kXBAR2_OutputAoi3In03 = 19|0x20000U, /**< XBAR2_OUT19 output assigned to AOI3_IN03 */ + kXBAR2_OutputAoi3In04 = 20|0x20000U, /**< XBAR2_OUT20 output assigned to AOI3_IN04 */ + kXBAR2_OutputAoi3In05 = 21|0x20000U, /**< XBAR2_OUT21 output assigned to AOI3_IN05 */ + kXBAR2_OutputAoi3In06 = 22|0x20000U, /**< XBAR2_OUT22 output assigned to AOI3_IN06 */ + kXBAR2_OutputAoi3In07 = 23|0x20000U, /**< XBAR2_OUT23 output assigned to AOI3_IN07 */ + kXBAR2_OutputAoi3In08 = 24|0x20000U, /**< XBAR2_OUT24 output assigned to AOI3_IN08 */ + kXBAR2_OutputAoi3In09 = 25|0x20000U, /**< XBAR2_OUT25 output assigned to AOI3_IN09 */ + kXBAR2_OutputAoi3In10 = 26|0x20000U, /**< XBAR2_OUT26 output assigned to AOI3_IN10 */ + kXBAR2_OutputAoi3In11 = 27|0x20000U, /**< XBAR2_OUT27 output assigned to AOI3_IN11 */ + kXBAR2_OutputAoi3In12 = 28|0x20000U, /**< XBAR2_OUT28 output assigned to AOI3_IN12 */ + kXBAR2_OutputAoi3In13 = 29|0x20000U, /**< XBAR2_OUT29 output assigned to AOI3_IN13 */ + kXBAR2_OutputAoi3In14 = 30|0x20000U, /**< XBAR2_OUT30 output assigned to AOI3_IN14 */ + kXBAR2_OutputAoi3In15 = 31|0x20000U, /**< XBAR2_OUT31 output assigned to AOI3_IN15 */ + kXBAR3_OutputAoi2In00 = 0|0x30000U, /**< XBAR3_OUT0 output assigned to AOI2_IN00 */ + kXBAR3_OutputAoi2In01 = 1|0x30000U, /**< XBAR3_OUT1 output assigned to AOI2_IN01 */ + kXBAR3_OutputAoi2In02 = 2|0x30000U, /**< XBAR3_OUT2 output assigned to AOI2_IN02 */ + kXBAR3_OutputAoi2In03 = 3|0x30000U, /**< XBAR3_OUT3 output assigned to AOI2_IN03 */ + kXBAR3_OutputAoi2In04 = 4|0x30000U, /**< XBAR3_OUT4 output assigned to AOI2_IN04 */ + kXBAR3_OutputAoi2In05 = 5|0x30000U, /**< XBAR3_OUT5 output assigned to AOI2_IN05 */ + kXBAR3_OutputAoi2In06 = 6|0x30000U, /**< XBAR3_OUT6 output assigned to AOI2_IN06 */ + kXBAR3_OutputAoi2In07 = 7|0x30000U, /**< XBAR3_OUT7 output assigned to AOI2_IN07 */ + kXBAR3_OutputAoi2In08 = 8|0x30000U, /**< XBAR3_OUT8 output assigned to AOI2_IN08 */ + kXBAR3_OutputAoi2In09 = 9|0x30000U, /**< XBAR3_OUT9 output assigned to AOI2_IN09 */ + kXBAR3_OutputAoi2In10 = 10|0x30000U, /**< XBAR3_OUT10 output assigned to AOI2_IN10 */ + kXBAR3_OutputAoi2In11 = 11|0x30000U, /**< XBAR3_OUT11 output assigned to AOI2_IN11 */ + kXBAR3_OutputAoi2In12 = 12|0x30000U, /**< XBAR3_OUT12 output assigned to AOI2_IN12 */ + kXBAR3_OutputAoi2In13 = 13|0x30000U, /**< XBAR3_OUT13 output assigned to AOI2_IN13 */ + kXBAR3_OutputAoi2In14 = 14|0x30000U, /**< XBAR3_OUT14 output assigned to AOI2_IN14 */ + kXBAR3_OutputAoi2In15 = 15|0x30000U, /**< XBAR3_OUT15 output assigned to AOI2_IN15 */ + kXBAR3_OutputAoi4In00 = 16|0x30000U, /**< XBAR3_OUT16 output assigned to AOI4_IN00 */ + kXBAR3_OutputAoi4In01 = 17|0x30000U, /**< XBAR3_OUT17 output assigned to AOI4_IN01 */ + kXBAR3_OutputAoi4In02 = 18|0x30000U, /**< XBAR3_OUT18 output assigned to AOI4_IN02 */ + kXBAR3_OutputAoi4In03 = 19|0x30000U, /**< XBAR3_OUT19 output assigned to AOI4_IN03 */ + kXBAR3_OutputAoi4In04 = 20|0x30000U, /**< XBAR3_OUT20 output assigned to AOI4_IN04 */ + kXBAR3_OutputAoi4In05 = 21|0x30000U, /**< XBAR3_OUT21 output assigned to AOI4_IN05 */ + kXBAR3_OutputAoi4In06 = 22|0x30000U, /**< XBAR3_OUT22 output assigned to AOI4_IN06 */ + kXBAR3_OutputAoi4In07 = 23|0x30000U, /**< XBAR3_OUT23 output assigned to AOI4_IN07 */ + kXBAR3_OutputAoi4In08 = 24|0x30000U, /**< XBAR3_OUT24 output assigned to AOI4_IN08 */ + kXBAR3_OutputAoi4In09 = 25|0x30000U, /**< XBAR3_OUT25 output assigned to AOI4_IN09 */ + kXBAR3_OutputAoi4In10 = 26|0x30000U, /**< XBAR3_OUT26 output assigned to AOI4_IN10 */ + kXBAR3_OutputAoi4In11 = 27|0x30000U, /**< XBAR3_OUT27 output assigned to AOI4_IN11 */ + kXBAR3_OutputAoi4In12 = 28|0x30000U, /**< XBAR3_OUT28 output assigned to AOI4_IN12 */ + kXBAR3_OutputAoi4In13 = 29|0x30000U, /**< XBAR3_OUT29 output assigned to AOI4_IN13 */ + kXBAR3_OutputAoi4In14 = 30|0x30000U, /**< XBAR3_OUT30 output assigned to AOI4_IN14 */ + kXBAR3_OutputAoi4In15 = 31|0x30000U, /**< XBAR3_OUT31 output assigned to AOI4_IN15 */ +} xbar_output_signal_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ADC - Peripheral instance base addresses */ /** Peripheral ADC base address */ #define ADC_BASE (0x44530000u) @@ -1656,6 +2748,16 @@ typedef enum IRQn { /** Array initializer of DCIF peripheral base pointers */ #define DCIF_BASE_PTRS { DCIF } +/* DDRC - Peripheral instance base addresses */ +/** Peripheral DDRC base address */ +#define DDRC_BASE (0x4E080000u) +/** Peripheral DDRC base pointer */ +#define DDRC ((DDRC_Type *)DDRC_BASE) +/** Array initializer of DDRC peripheral base addresses */ +#define DDRC_BASE_ADDRS { DDRC_BASE } +/** Array initializer of DDRC peripheral base pointers */ +#define DDRC_BASE_PTRS { DDRC } + /* DDR_BLK_CTRL_DDRMIX - Peripheral instance base addresses */ /** Peripheral BLK_CTRL_DDRMIX base address */ #define BLK_CTRL_DDRMIX_BASE (0x4E010000u) @@ -1680,16 +2782,6 @@ typedef enum IRQn { /** Array initializer of DDR_CMU peripheral base pointers */ #define DDR_CMU_BASE_PTRS { DDRC__CMU_1, DDRC__CMU_2 } -/* DDR_DDRC - Peripheral instance base addresses */ -/** Peripheral DDRC base address */ -#define DDRC_BASE (0x4E080000u) -/** Peripheral DDRC base pointer */ -#define DDRC ((DDR_DDRC_Type *)DDRC_BASE) -/** Array initializer of DDR_DDRC peripheral base addresses */ -#define DDR_DDRC_BASE_ADDRS { DDRC_BASE } -/** Array initializer of DDR_DDRC peripheral base pointers */ -#define DDR_DDRC_BASE_PTRS { DDRC } - /* DDR_LSTCU - Peripheral instance base addresses */ /** Peripheral DDRC__LSTCU base address */ #define DDRC__LSTCU_BASE (0x4E050000u) @@ -2131,10 +3223,22 @@ typedef enum IRQn { #define GPT1_BASE (0x446F0000u) /** Peripheral GPT1 base pointer */ #define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x428A0000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Peripheral GPT3 base address */ +#define GPT3_BASE (0x428B0000u) +/** Peripheral GPT3 base pointer */ +#define GPT3 ((GPT_Type *)GPT3_BASE) +/** Peripheral GPT4 base address */ +#define GPT4_BASE (0x428C0000u) +/** Peripheral GPT4 base pointer */ +#define GPT4 ((GPT_Type *)GPT4_BASE) /** Array initializer of GPT peripheral base addresses */ -#define GPT_BASE_ADDRS { GPT1_BASE } +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE } /** Array initializer of GPT peripheral base pointers */ -#define GPT_BASE_PTRS { GPT1 } +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4 } /* HIPERFACE - Peripheral instance base addresses */ /** Peripheral HIPERFACE1 base address */ @@ -2185,6 +3289,10 @@ typedef enum IRQn { #define SAI1_BASE (0x443B0000u) /** Peripheral SAI1 base pointer */ #define SAI1 ((I2S_Type *)SAI1_BASE) +/** Peripheral SAI2 base address */ +#define SAI2_BASE (0x42650000u) +/** Peripheral SAI2 base pointer */ +#define SAI2 ((I2S_Type *)SAI2_BASE) /** Peripheral SAI3 base address */ #define SAI3_BASE (0x42660000u) /** Peripheral SAI3 base pointer */ @@ -2194,12 +3302,12 @@ typedef enum IRQn { /** Peripheral SAI4 base pointer */ #define SAI4 ((I2S_Type *)SAI4_BASE) /** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { 0u, SAI1_BASE, 0u, SAI3_BASE, SAI4_BASE } +#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE } /** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, (I2S_Type *)0u, SAI3, SAI4 } +#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 } /** Interrupt vectors for the I2S peripheral type */ -#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, NotAvail_IRQn, SAI3_IRQn, SAI4_IRQn } -#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, NotAvail_IRQn, SAI3_IRQn, SAI4_IRQn } +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn } /* I3C - Peripheral instance base addresses */ /** Peripheral I3C1 base address */ @@ -4365,9 +5473,9 @@ typedef enum IRQn { /** Peripheral TMR8 base pointer */ #define TMR8 ((TMR_Type *)TMR8_BASE) /** Array initializer of TMR peripheral base addresses */ -#define TMR_BASE_ADDRS { TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } +#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE, TMR5_BASE, TMR6_BASE, TMR7_BASE, TMR8_BASE } /** Array initializer of TMR peripheral base pointers */ -#define TMR_BASE_PTRS { TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } +#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8 } /* TMR_GLOBAL - Peripheral instance base addresses */ /** Peripheral NETC__ECAM_PCI_EMDIO0_BAR_0__TMR1_GLOBAL base address */ @@ -4581,34 +5689,6 @@ typedef enum IRQn { /** Array initializer of WAKEUP_ERM peripheral base pointers */ #define WAKEUP_ERM_BASE_PTRS { WAKEUP__ERM } -/* WAKEUP_GPT - Peripheral instance base addresses */ -/** Peripheral GPT2 base address */ -#define GPT2_BASE (0x428A0000u) -/** Peripheral GPT2 base pointer */ -#define GPT2 ((WAKEUP_GPT_Type *)GPT2_BASE) -/** Peripheral GPT3 base address */ -#define GPT3_BASE (0x428B0000u) -/** Peripheral GPT3 base pointer */ -#define GPT3 ((WAKEUP_GPT_Type *)GPT3_BASE) -/** Peripheral GPT4 base address */ -#define GPT4_BASE (0x428C0000u) -/** Peripheral GPT4 base pointer */ -#define GPT4 ((WAKEUP_GPT_Type *)GPT4_BASE) -/** Array initializer of WAKEUP_GPT peripheral base addresses */ -#define WAKEUP_GPT_BASE_ADDRS { 0u, 0u, GPT2_BASE, GPT3_BASE, GPT4_BASE } -/** Array initializer of WAKEUP_GPT peripheral base pointers */ -#define WAKEUP_GPT_BASE_PTRS { (WAKEUP_GPT_Type *)0u, (WAKEUP_GPT_Type *)0u, GPT2, GPT3, GPT4 } - -/* WAKEUP_SAI - Peripheral instance base addresses */ -/** Peripheral WAKEUP__SAI2 base address */ -#define WAKEUP__SAI2_BASE (0x42650000u) -/** Peripheral WAKEUP__SAI2 base pointer */ -#define WAKEUP__SAI2 ((WAKEUP_SAI_Type *)WAKEUP__SAI2_BASE) -/** Array initializer of WAKEUP_SAI peripheral base addresses */ -#define WAKEUP_SAI_BASE_ADDRS { WAKEUP__SAI2_BASE } -/** Array initializer of WAKEUP_SAI peripheral base pointers */ -#define WAKEUP_SAI_BASE_PTRS { WAKEUP__SAI2 } - /* WAKEUP_TCW - Peripheral instance base addresses */ /** Peripheral WAKEUP__TCW base address */ #define WAKEUP__TCW_BASE (0x42620000u) @@ -4903,3 +5983,4 @@ typedef enum #endif /* MIMX94398_CM7_CORE1_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1_features.h index 7a09ab607..3b328a1d0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_cm7_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2023-11-01 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -53,8 +53,8 @@ #define FSL_FEATURE_SOC_AXBS_COUNT (2) /* @brief BBNSM availability on the SoC. */ #define FSL_FEATURE_SOC_BBNSM_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (1) +/* @brief DDRC availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_COUNT (1) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (4) /* @brief EIM availability on the SoC. */ @@ -74,7 +74,7 @@ /* @brief I3C availability on the SoC. */ #define FSL_FEATURE_SOC_I3C_COUNT (2) /* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (3) +#define FSL_FEATURE_SOC_I2S_COUNT (4) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ @@ -132,6 +132,8 @@ #define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) /* @brief Self-test threshold counts of ADC. */ #define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) +/* @brief Has external trigger or not. */ +#define FSL_FEATURE_ADC_HAS_EXTERNAL_TRIGGER (1) /* AOI module features */ @@ -229,6 +231,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* TMPSNS module features */ @@ -398,8 +404,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -428,6 +432,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* RGPIO module features */ @@ -457,14 +463,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -563,8 +569,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -607,6 +611,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -762,6 +770,18 @@ #define FSL_FEATURE_NETC_HAS_NO_XGMII (1) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (1) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (1) /* @brief NXP Switch port group support. */ @@ -854,18 +874,18 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ + (((x) == SAI2) ? (128) : \ (((x) == SAI3) ? (128) : \ - (((x) == SAI4) ? (128) : (-1)))) + (((x) == SAI4) ? (128) : (-1))))) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ (((x) == SAI1) ? (2) : \ + (((x) == SAI2) ? (1) : \ (((x) == SAI3) ? (1) : \ - (((x) == SAI4) ? (1) : (-1)))) + (((x) == SAI4) ? (1) : (-1))))) /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ @@ -890,14 +910,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/drivers/fsl_clock.h index a867ad55f..775fd9a6a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/drivers/fsl_clock.h @@ -1606,7 +1606,9 @@ typedef enum _clock_gate_value */ #define TMR_CLOCKS \ { \ - kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \ + kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \ } diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm33_core1.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm33_core1.c index 449ea5ea5..5cc7b861f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm33_core1.c @@ -81,6 +81,9 @@ #include "scmi.h" #include "scmi_internal.h" #include "smt.h" +#if SCMI_LMM_POWER_CHANGE_PROCESSED +#include "app_srtm.h" +#endif #define NETC_OCRAM_START_ADDR (0x20800000U) #define NETC_OCRAM_END_ADDR (0x2097FFFFU) @@ -200,6 +203,7 @@ void SystemPlatformInit(void) /* Configure MU */ MU_Init(base); EnableIRQ(irq); + NVIC_SetPriority(irq, SCMI_MU_IRQ_PRIORITY); MU_EnableInterrupts(base, kMU_GenInt1InterruptEnable); MU_EnableInterrupts(base, kMU_GenInt2InterruptEnable); @@ -312,7 +316,10 @@ void SystemPlatformHandler(void) if (SCMI_LmmEvent(SCMI_NOTIFY, NULL, &eventLm, ¬ifyFlags) == SCMI_ERR_SUCCESS) { - PRINTF("\nSCMI LMM notification: LM %u, flags=0x%08X\r\n", eventLm, notifyFlags); +#if SCMI_LMM_POWER_CHANGE_PROCESSED + /* Handle peer acore power changes notification to assure right communication. */ + APP_SRTM_HandleLmmPowerChange(eventLm, notifyFlags); +#endif } } else if (protocolId == SCMI_PROTOCOL_BBM) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm33_core1.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm33_core1.h index d6473da19..6e3272046 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm33_core1.h @@ -157,10 +157,41 @@ #define SYSTEM_POWER_PLATFORM_MIX_SLICE_IDX_NPU 17U #define SYSTEM_POWER_PLATFORM_MIX_SLICE_IDX_WAKEUP 18U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_AON 0U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_M7_1 1U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_A55C0 2U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_A55C1 3U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_A55C2 4U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_A55C3 5U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_A55P 6U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_A55L3 7U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_DDR 8U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_DISPLAY 9U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_M7_0 10U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_HSIO 11U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_NETC 12U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_NOC1 13U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_NOC2 14U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_NPU 15U +#define SYSTEM_POWER_PLATFORM_MEM_SLICE_IDX_WAKEUP 16U + #ifndef SYSTEM_PLATFORM_RTC_NOTIFY #define SYSTEM_PLATFORM_RTC_NOTIFY 0 #endif +#ifndef SCMI_LMM_POWER_CHANGE_PROCESSED +#define SCMI_LMM_POWER_CHANGE_PROCESSED (0) +#endif + +/* SCMI lmm protocol cpu id */ +#define SYSTEM_LMID_SM (0U) +#define SYSTEM_LMID_M33S (1U) +#define SYSTEM_LMID_M70 (2U) +#define SYSTEM_LMID_M71 (3U) +#define SYSTEM_LMID_A55 (4U) + +#define SCMI_MU_IRQ_PRIORITY (3U) + #ifdef __cplusplus extern "C" { #endif diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core0.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core0.c index 3215e67c7..f1a793f93 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core0.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core0.c @@ -80,6 +80,9 @@ #include "scmi.h" #include "scmi_internal.h" #include "smt.h" +#if SCMI_LMM_POWER_CHANGE_PROCESSED +#include "app_srtm.h" +#endif /* ---------------------------------------------------------------------------- -- Core clock @@ -183,6 +186,7 @@ void SystemPlatformInit(void) /* Configure MU */ MU_Init(base); EnableIRQ(irq); + NVIC_SetPriority(irq, SCMI_MU_IRQ_PRIORITY); MU_EnableInterrupts(base, kMU_GenInt1InterruptEnable); MU_EnableInterrupts(base, kMU_GenInt2InterruptEnable); @@ -294,7 +298,10 @@ void SystemPlatformHandler(void) if (SCMI_LmmEvent(SCMI_NOTIFY, NULL, &eventLm, ¬ifyFlags) == SCMI_ERR_SUCCESS) { - PRINTF("\nSCMI LMM notification: LM %u, flags=0x%08X\r\n", eventLm, notifyFlags); +#if SCMI_LMM_POWER_CHANGE_PROCESSED + /* Handle peer acore power changes notification to assure right communication. */ + APP_SRTM_HandleLmmPowerChange(eventLm, notifyFlags); +#endif } } else if (protocolId == SCMI_PROTOCOL_BBM) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core0.h index ecda2049c..99df86c9e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core0.h @@ -130,6 +130,19 @@ #define SYSTEM_PLATFORM_RTC_NOTIFY 0 #endif +#ifndef SCMI_LMM_POWER_CHANGE_PROCESSED +#define SCMI_LMM_POWER_CHANGE_PROCESSED (0) +#endif + +/* SCMI lmm protocol cpu id */ +#define SYSTEM_LMID_SM (0U) +#define SYSTEM_LMID_M33S (1U) +#define SYSTEM_LMID_M70 (2U) +#define SYSTEM_LMID_M71 (3U) +#define SYSTEM_LMID_A55 (4U) + +#define SCMI_MU_IRQ_PRIORITY (3U) + #ifdef __cplusplus extern "C" { #endif diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core1.c b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core1.c index d67bf1d71..cf20af290 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core1.c +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core1.c @@ -80,6 +80,9 @@ #include "scmi.h" #include "scmi_internal.h" #include "smt.h" +#if SCMI_LMM_POWER_CHANGE_PROCESSED +#include "app_srtm.h" +#endif /* ---------------------------------------------------------------------------- -- Core clock @@ -183,6 +186,7 @@ void SystemPlatformInit(void) /* Configure MU */ MU_Init(base); EnableIRQ(irq); + NVIC_SetPriority(irq, SCMI_MU_IRQ_PRIORITY); MU_EnableInterrupts(base, kMU_GenInt1InterruptEnable); MU_EnableInterrupts(base, kMU_GenInt2InterruptEnable); @@ -294,7 +298,10 @@ void SystemPlatformHandler(void) if (SCMI_LmmEvent(SCMI_NOTIFY, NULL, &eventLm, ¬ifyFlags) == SCMI_ERR_SUCCESS) { - PRINTF("\nSCMI LMM notification: LM %u, flags=0x%08X\r\n", eventLm, notifyFlags); +#if SCMI_LMM_POWER_CHANGE_PROCESSED + /* Handle peer acore power changes notification to assure right communication. */ + APP_SRTM_HandleLmmPowerChange(eventLm, notifyFlags); +#endif } } else if (protocolId == SCMI_PROTOCOL_BBM) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core1.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core1.h index 21f207f27..f7a323c9e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core1.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/system_MIMX94398_cm7_core1.h @@ -134,6 +134,19 @@ extern "C" { #define SYSTEM_PLATFORM_RTC_NOTIFY 0 #endif +#ifndef SCMI_LMM_POWER_CHANGE_PROCESSED +#define SCMI_LMM_POWER_CHANGE_PROCESSED (0) +#endif + +/* SCMI lmm protocol cpu id */ +#define SYSTEM_LMID_SM (0U) +#define SYSTEM_LMID_M33S (1U) +#define SYSTEM_LMID_M70 (2U) +#define SYSTEM_LMID_M71 (3U) +#define SYSTEM_LMID_A55 (4U) + +#define SCMI_MU_IRQ_PRIORITY (3U) + /** * @brief System clock frequency (core clock) * diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_AGDET.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_AGDET.h index a2d64c9d2..2609cac5d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_AGDET.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_AGDET.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANALOG_AGDET @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ANALOG_AGDET.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ANALOG_AGDET.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ANALOG_AGDET * * CMSIS Peripheral Access Layer for ANALOG_AGDET */ -#if !defined(ANALOG_AGDET_H_) -#define ANALOG_AGDET_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ANALOG_AGDET_H_) +#define PERI_ANALOG_AGDET_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -480,5 +483,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ANALOG_AGDET_H_ */ +#endif /* PERI_ANALOG_AGDET_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_CMU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_CMU.h index 56b589c1a..70ba71552 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_CMU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_CMU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANALOG_CMU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ANALOG_CMU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ANALOG_CMU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ANALOG_CMU * * CMSIS Peripheral Access Layer for ANALOG_CMU */ -#if !defined(ANALOG_CMU_H_) -#define ANALOG_CMU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ANALOG_CMU_H_) +#define PERI_ANALOG_CMU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -365,5 +368,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ANALOG_CMU_H_ */ +#endif /* PERI_ANALOG_CMU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_PMRO.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_PMRO.h index 2f8f58d64..33faf4ad5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_PMRO.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_PMRO.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANALOG_PMRO @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ANALOG_PMRO.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ANALOG_PMRO.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ANALOG_PMRO * * CMSIS Peripheral Access Layer for ANALOG_PMRO */ -#if !defined(ANALOG_PMRO_H_) -#define ANALOG_PMRO_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ANALOG_PMRO_H_) +#define PERI_ANALOG_PMRO_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -306,5 +309,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ANALOG_PMRO_H_ */ +#endif /* PERI_ANALOG_PMRO_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_SFA.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_SFA.h index 181d85798..8f6bdac90 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_SFA.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_SFA.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANALOG_SFA @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ANALOG_SFA.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ANALOG_SFA.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ANALOG_SFA * * CMSIS Peripheral Access Layer for ANALOG_SFA */ -#if !defined(ANALOG_SFA_H_) -#define ANALOG_SFA_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ANALOG_SFA_H_) +#define PERI_ANALOG_SFA_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -467,5 +470,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ANALOG_SFA_H_ */ +#endif /* PERI_ANALOG_SFA_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_TCU.h index b8450b205..87e68c336 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANALOG_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ANALOG_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ANALOG_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ANALOG_TCU * * CMSIS Peripheral Access Layer for ANALOG_TCU */ -#if !defined(ANALOG_TCU_H_) -#define ANALOG_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ANALOG_TCU_H_) +#define PERI_ANALOG_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -436,5 +439,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ANALOG_TCU_H_ */ +#endif /* PERI_ANALOG_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_VDET.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_VDET.h index 89b155d65..820c3b626 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_VDET.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ANALOG_VDET.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANALOG_VDET @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ANALOG_VDET.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ANALOG_VDET.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ANALOG_VDET * * CMSIS Peripheral Access Layer for ANALOG_VDET */ -#if !defined(ANALOG_VDET_H_) -#define ANALOG_VDET_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ANALOG_VDET_H_) +#define PERI_ANALOG_VDET_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -293,5 +296,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ANALOG_VDET_H_ */ +#endif /* PERI_ANALOG_VDET_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AOI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AOI.h index 27112d939..599a3506a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AOI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AOI.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AOI @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AOI.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AOI.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AOI * * CMSIS Peripheral Access Layer for AOI */ -#if !defined(AOI_H_) -#define AOI_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AOI_H_) +#define PERI_AOI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -453,5 +456,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AOI_H_ */ +#endif /* PERI_AOI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CMU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CMU.h index 1c4aa892b..3c460746a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CMU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CMU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_CMU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_CMU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_CMU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_CMU * * CMSIS Peripheral Access Layer for AON_CMU */ -#if !defined(AON_CMU_H_) -#define AON_CMU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_CMU_H_) +#define PERI_AON_CMU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -365,5 +368,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_CMU_H_ */ +#endif /* PERI_AON_CMU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CRC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CRC.h index fdd875854..9a0ca2e0e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CRC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CRC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_CRC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_CRC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_CRC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_CRC * * CMSIS Peripheral Access Layer for AON_CRC */ -#if !defined(AON_CRC_H_) -#define AON_CRC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_CRC_H_) +#define PERI_AON_CRC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_CRC_H_ */ +#endif /* PERI_AON_CRC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CSTCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CSTCU.h index 553df4eab..09f6b0818 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CSTCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_CSTCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_CSTCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_CSTCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_CSTCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_CSTCU * * CMSIS Peripheral Access Layer for AON_CSTCU */ -#if !defined(AON_CSTCU_H_) -#define AON_CSTCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_CSTCU_H_) +#define PERI_AON_CSTCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -273,8 +276,8 @@ typedef struct { #define AON_CSTCU_RUNSWREG_RUNSW_MASK (0x1U) #define AON_CSTCU_RUNSWREG_RUNSW_SHIFT (0U) /*! RUNSW - Run Software - * 0b0..No self-test run in progress * 0b0..No effect + * 0b0..No self-test run in progress * 0b1..Self-test in progress * 0b1..Starts self-test */ @@ -283,8 +286,8 @@ typedef struct { #define AON_CSTCU_RUNSWREG_SW_ABORT_MASK (0x10U) #define AON_CSTCU_RUNSWREG_SW_ABORT_SHIFT (4U) /*! SW_ABORT - Software Abort - * 0b0..No self-test abort request * 0b0..No effect + * 0b0..No self-test abort request * 0b1..Aborts self-test */ #define AON_CSTCU_RUNSWREG_SW_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_RUNSWREG_SW_ABORT_SHIFT)) & AON_CSTCU_RUNSWREG_SW_ABORT_MASK) @@ -320,10 +323,10 @@ typedef struct { #define AON_CSTCU_IF_STEND_IF_MASK (0x1U) #define AON_CSTCU_IF_STEND_IF_SHIFT (0U) /*! STEND_IF - Self-Test End Interrupt Flag - * 0b0..No pending interrupt * 0b0..No effect - * 0b1..Pending interrupt + * 0b0..No pending interrupt * 0b1..Clear the flag + * 0b1..Pending interrupt */ #define AON_CSTCU_IF_STEND_IF(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_IF_STEND_IF_SHIFT)) & AON_CSTCU_IF_STEND_IF_MASK) /*! @} */ @@ -711,5 +714,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_CSTCU_H_ */ +#endif /* PERI_AON_CSTCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_EIM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_EIM.h index 5a260b699..fc19150f1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_EIM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_EIM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_EIM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_EIM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_EIM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_EIM * * CMSIS Peripheral Access Layer for AON_EIM */ -#if !defined(AON_EIM_H_) -#define AON_EIM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_EIM_H_) +#define PERI_AON_EIM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -707,5 +710,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_EIM_H_ */ +#endif /* PERI_AON_EIM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_ERM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_ERM.h index f4f9451e5..0bf24883f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_ERM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_ERM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_ERM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_ERM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_ERM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_ERM * * CMSIS Peripheral Access Layer for AON_ERM */ -#if !defined(AON_ERM_H_) -#define AON_ERM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_ERM_H_) +#define PERI_AON_ERM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -923,5 +926,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_ERM_H_ */ +#endif /* PERI_AON_ERM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_FCCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_FCCU.h index d023f8e4f..290d934f2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_FCCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_FCCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_FCCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_FCCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_FCCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_FCCU * * CMSIS Peripheral Access Layer for AON_FCCU */ -#if !defined(AON_FCCU_H_) -#define AON_FCCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_FCCU_H_) +#define PERI_AON_FCCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2808,320 +2811,320 @@ typedef struct { #define AON_FCCU_FHFLTS0_0_STAT0_MASK (0x1U) #define AON_FCCU_FHFLTS0_0_STAT0_SHIFT (0U) /*! STAT0 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT0_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT0_MASK) #define AON_FCCU_FHFLTS0_0_STAT1_MASK (0x2U) #define AON_FCCU_FHFLTS0_0_STAT1_SHIFT (1U) /*! STAT1 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT1_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT1_MASK) #define AON_FCCU_FHFLTS0_0_STAT2_MASK (0x4U) #define AON_FCCU_FHFLTS0_0_STAT2_SHIFT (2U) /*! STAT2 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT2_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT2_MASK) #define AON_FCCU_FHFLTS0_0_STAT3_MASK (0x8U) #define AON_FCCU_FHFLTS0_0_STAT3_SHIFT (3U) /*! STAT3 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT3_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT3_MASK) #define AON_FCCU_FHFLTS0_0_STAT4_MASK (0x10U) #define AON_FCCU_FHFLTS0_0_STAT4_SHIFT (4U) /*! STAT4 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT4_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT4_MASK) #define AON_FCCU_FHFLTS0_0_STAT5_MASK (0x20U) #define AON_FCCU_FHFLTS0_0_STAT5_SHIFT (5U) /*! STAT5 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT5_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT5_MASK) #define AON_FCCU_FHFLTS0_0_STAT6_MASK (0x40U) #define AON_FCCU_FHFLTS0_0_STAT6_SHIFT (6U) /*! STAT6 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT6_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT6_MASK) #define AON_FCCU_FHFLTS0_0_STAT7_MASK (0x80U) #define AON_FCCU_FHFLTS0_0_STAT7_SHIFT (7U) /*! STAT7 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT7(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT7_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT7_MASK) #define AON_FCCU_FHFLTS0_0_STAT8_MASK (0x100U) #define AON_FCCU_FHFLTS0_0_STAT8_SHIFT (8U) /*! STAT8 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT8(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT8_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT8_MASK) #define AON_FCCU_FHFLTS0_0_STAT9_MASK (0x200U) #define AON_FCCU_FHFLTS0_0_STAT9_SHIFT (9U) /*! STAT9 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT9(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT9_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT9_MASK) #define AON_FCCU_FHFLTS0_0_STAT10_MASK (0x400U) #define AON_FCCU_FHFLTS0_0_STAT10_SHIFT (10U) /*! STAT10 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT10(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT10_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT10_MASK) #define AON_FCCU_FHFLTS0_0_STAT11_MASK (0x800U) #define AON_FCCU_FHFLTS0_0_STAT11_SHIFT (11U) /*! STAT11 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT11(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT11_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT11_MASK) #define AON_FCCU_FHFLTS0_0_STAT12_MASK (0x1000U) #define AON_FCCU_FHFLTS0_0_STAT12_SHIFT (12U) /*! STAT12 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT12(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT12_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT12_MASK) #define AON_FCCU_FHFLTS0_0_STAT13_MASK (0x2000U) #define AON_FCCU_FHFLTS0_0_STAT13_SHIFT (13U) /*! STAT13 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT13(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT13_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT13_MASK) #define AON_FCCU_FHFLTS0_0_STAT14_MASK (0x4000U) #define AON_FCCU_FHFLTS0_0_STAT14_SHIFT (14U) /*! STAT14 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT14(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT14_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT14_MASK) #define AON_FCCU_FHFLTS0_0_STAT15_MASK (0x8000U) #define AON_FCCU_FHFLTS0_0_STAT15_SHIFT (15U) /*! STAT15 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT15(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT15_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT15_MASK) #define AON_FCCU_FHFLTS0_0_STAT16_MASK (0x10000U) #define AON_FCCU_FHFLTS0_0_STAT16_SHIFT (16U) /*! STAT16 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT16(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT16_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT16_MASK) #define AON_FCCU_FHFLTS0_0_STAT17_MASK (0x20000U) #define AON_FCCU_FHFLTS0_0_STAT17_SHIFT (17U) /*! STAT17 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT17(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT17_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT17_MASK) #define AON_FCCU_FHFLTS0_0_STAT18_MASK (0x40000U) #define AON_FCCU_FHFLTS0_0_STAT18_SHIFT (18U) /*! STAT18 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT18(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT18_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT18_MASK) #define AON_FCCU_FHFLTS0_0_STAT19_MASK (0x80000U) #define AON_FCCU_FHFLTS0_0_STAT19_SHIFT (19U) /*! STAT19 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT19(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT19_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT19_MASK) #define AON_FCCU_FHFLTS0_0_STAT20_MASK (0x100000U) #define AON_FCCU_FHFLTS0_0_STAT20_SHIFT (20U) /*! STAT20 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT20(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT20_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT20_MASK) #define AON_FCCU_FHFLTS0_0_STAT21_MASK (0x200000U) #define AON_FCCU_FHFLTS0_0_STAT21_SHIFT (21U) /*! STAT21 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT21(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT21_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT21_MASK) #define AON_FCCU_FHFLTS0_0_STAT22_MASK (0x400000U) #define AON_FCCU_FHFLTS0_0_STAT22_SHIFT (22U) /*! STAT22 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT22(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT22_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT22_MASK) #define AON_FCCU_FHFLTS0_0_STAT23_MASK (0x800000U) #define AON_FCCU_FHFLTS0_0_STAT23_SHIFT (23U) /*! STAT23 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT23(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT23_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT23_MASK) #define AON_FCCU_FHFLTS0_0_STAT24_MASK (0x1000000U) #define AON_FCCU_FHFLTS0_0_STAT24_SHIFT (24U) /*! STAT24 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT24(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT24_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT24_MASK) #define AON_FCCU_FHFLTS0_0_STAT25_MASK (0x2000000U) #define AON_FCCU_FHFLTS0_0_STAT25_SHIFT (25U) /*! STAT25 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT25(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT25_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT25_MASK) #define AON_FCCU_FHFLTS0_0_STAT26_MASK (0x4000000U) #define AON_FCCU_FHFLTS0_0_STAT26_SHIFT (26U) /*! STAT26 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT26(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT26_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT26_MASK) #define AON_FCCU_FHFLTS0_0_STAT27_MASK (0x8000000U) #define AON_FCCU_FHFLTS0_0_STAT27_SHIFT (27U) /*! STAT27 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT27(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT27_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT27_MASK) #define AON_FCCU_FHFLTS0_0_STAT28_MASK (0x10000000U) #define AON_FCCU_FHFLTS0_0_STAT28_SHIFT (28U) /*! STAT28 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT28(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT28_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT28_MASK) #define AON_FCCU_FHFLTS0_0_STAT29_MASK (0x20000000U) #define AON_FCCU_FHFLTS0_0_STAT29_SHIFT (29U) /*! STAT29 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT29(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT29_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT29_MASK) #define AON_FCCU_FHFLTS0_0_STAT30_MASK (0x40000000U) #define AON_FCCU_FHFLTS0_0_STAT30_SHIFT (30U) /*! STAT30 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT30(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT30_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT30_MASK) #define AON_FCCU_FHFLTS0_0_STAT31_MASK (0x80000000U) #define AON_FCCU_FHFLTS0_0_STAT31_SHIFT (31U) /*! STAT31 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_0_STAT31(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT31_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT31_MASK) /*! @} */ @@ -3132,320 +3135,320 @@ typedef struct { #define AON_FCCU_FHFLTS0_1_STAT32_MASK (0x1U) #define AON_FCCU_FHFLTS0_1_STAT32_SHIFT (0U) /*! STAT32 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT32(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT32_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT32_MASK) #define AON_FCCU_FHFLTS0_1_STAT33_MASK (0x2U) #define AON_FCCU_FHFLTS0_1_STAT33_SHIFT (1U) /*! STAT33 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT33(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT33_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT33_MASK) #define AON_FCCU_FHFLTS0_1_STAT34_MASK (0x4U) #define AON_FCCU_FHFLTS0_1_STAT34_SHIFT (2U) /*! STAT34 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT34(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT34_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT34_MASK) #define AON_FCCU_FHFLTS0_1_STAT35_MASK (0x8U) #define AON_FCCU_FHFLTS0_1_STAT35_SHIFT (3U) /*! STAT35 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT35(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT35_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT35_MASK) #define AON_FCCU_FHFLTS0_1_STAT36_MASK (0x10U) #define AON_FCCU_FHFLTS0_1_STAT36_SHIFT (4U) /*! STAT36 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT36(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT36_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT36_MASK) #define AON_FCCU_FHFLTS0_1_STAT37_MASK (0x20U) #define AON_FCCU_FHFLTS0_1_STAT37_SHIFT (5U) /*! STAT37 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT37(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT37_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT37_MASK) #define AON_FCCU_FHFLTS0_1_STAT38_MASK (0x40U) #define AON_FCCU_FHFLTS0_1_STAT38_SHIFT (6U) /*! STAT38 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT38(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT38_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT38_MASK) #define AON_FCCU_FHFLTS0_1_STAT39_MASK (0x80U) #define AON_FCCU_FHFLTS0_1_STAT39_SHIFT (7U) /*! STAT39 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT39(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT39_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT39_MASK) #define AON_FCCU_FHFLTS0_1_STAT40_MASK (0x100U) #define AON_FCCU_FHFLTS0_1_STAT40_SHIFT (8U) /*! STAT40 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT40(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT40_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT40_MASK) #define AON_FCCU_FHFLTS0_1_STAT41_MASK (0x200U) #define AON_FCCU_FHFLTS0_1_STAT41_SHIFT (9U) /*! STAT41 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT41(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT41_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT41_MASK) #define AON_FCCU_FHFLTS0_1_STAT42_MASK (0x400U) #define AON_FCCU_FHFLTS0_1_STAT42_SHIFT (10U) /*! STAT42 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT42(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT42_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT42_MASK) #define AON_FCCU_FHFLTS0_1_STAT43_MASK (0x800U) #define AON_FCCU_FHFLTS0_1_STAT43_SHIFT (11U) /*! STAT43 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT43(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT43_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT43_MASK) #define AON_FCCU_FHFLTS0_1_STAT44_MASK (0x1000U) #define AON_FCCU_FHFLTS0_1_STAT44_SHIFT (12U) /*! STAT44 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT44(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT44_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT44_MASK) #define AON_FCCU_FHFLTS0_1_STAT45_MASK (0x2000U) #define AON_FCCU_FHFLTS0_1_STAT45_SHIFT (13U) /*! STAT45 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT45(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT45_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT45_MASK) #define AON_FCCU_FHFLTS0_1_STAT46_MASK (0x4000U) #define AON_FCCU_FHFLTS0_1_STAT46_SHIFT (14U) /*! STAT46 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT46(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT46_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT46_MASK) #define AON_FCCU_FHFLTS0_1_STAT47_MASK (0x8000U) #define AON_FCCU_FHFLTS0_1_STAT47_SHIFT (15U) /*! STAT47 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT47(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT47_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT47_MASK) #define AON_FCCU_FHFLTS0_1_STAT48_MASK (0x10000U) #define AON_FCCU_FHFLTS0_1_STAT48_SHIFT (16U) /*! STAT48 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT48(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT48_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT48_MASK) #define AON_FCCU_FHFLTS0_1_STAT49_MASK (0x20000U) #define AON_FCCU_FHFLTS0_1_STAT49_SHIFT (17U) /*! STAT49 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT49(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT49_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT49_MASK) #define AON_FCCU_FHFLTS0_1_STAT50_MASK (0x40000U) #define AON_FCCU_FHFLTS0_1_STAT50_SHIFT (18U) /*! STAT50 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT50(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT50_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT50_MASK) #define AON_FCCU_FHFLTS0_1_STAT51_MASK (0x80000U) #define AON_FCCU_FHFLTS0_1_STAT51_SHIFT (19U) /*! STAT51 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT51(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT51_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT51_MASK) #define AON_FCCU_FHFLTS0_1_STAT52_MASK (0x100000U) #define AON_FCCU_FHFLTS0_1_STAT52_SHIFT (20U) /*! STAT52 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT52(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT52_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT52_MASK) #define AON_FCCU_FHFLTS0_1_STAT53_MASK (0x200000U) #define AON_FCCU_FHFLTS0_1_STAT53_SHIFT (21U) /*! STAT53 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT53(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT53_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT53_MASK) #define AON_FCCU_FHFLTS0_1_STAT54_MASK (0x400000U) #define AON_FCCU_FHFLTS0_1_STAT54_SHIFT (22U) /*! STAT54 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT54(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT54_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT54_MASK) #define AON_FCCU_FHFLTS0_1_STAT55_MASK (0x800000U) #define AON_FCCU_FHFLTS0_1_STAT55_SHIFT (23U) /*! STAT55 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT55(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT55_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT55_MASK) #define AON_FCCU_FHFLTS0_1_STAT56_MASK (0x1000000U) #define AON_FCCU_FHFLTS0_1_STAT56_SHIFT (24U) /*! STAT56 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT56(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT56_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT56_MASK) #define AON_FCCU_FHFLTS0_1_STAT57_MASK (0x2000000U) #define AON_FCCU_FHFLTS0_1_STAT57_SHIFT (25U) /*! STAT57 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT57(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT57_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT57_MASK) #define AON_FCCU_FHFLTS0_1_STAT58_MASK (0x4000000U) #define AON_FCCU_FHFLTS0_1_STAT58_SHIFT (26U) /*! STAT58 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT58(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT58_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT58_MASK) #define AON_FCCU_FHFLTS0_1_STAT59_MASK (0x8000000U) #define AON_FCCU_FHFLTS0_1_STAT59_SHIFT (27U) /*! STAT59 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT59(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT59_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT59_MASK) #define AON_FCCU_FHFLTS0_1_STAT60_MASK (0x10000000U) #define AON_FCCU_FHFLTS0_1_STAT60_SHIFT (28U) /*! STAT60 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT60(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT60_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT60_MASK) #define AON_FCCU_FHFLTS0_1_STAT61_MASK (0x20000000U) #define AON_FCCU_FHFLTS0_1_STAT61_SHIFT (29U) /*! STAT61 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT61(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT61_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT61_MASK) #define AON_FCCU_FHFLTS0_1_STAT62_MASK (0x40000000U) #define AON_FCCU_FHFLTS0_1_STAT62_SHIFT (30U) /*! STAT62 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT62(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT62_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT62_MASK) #define AON_FCCU_FHFLTS0_1_STAT63_MASK (0x80000000U) #define AON_FCCU_FHFLTS0_1_STAT63_SHIFT (31U) /*! STAT63 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_1_STAT63(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT63_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT63_MASK) /*! @} */ @@ -3456,320 +3459,320 @@ typedef struct { #define AON_FCCU_FHFLTS0_2_STAT64_MASK (0x1U) #define AON_FCCU_FHFLTS0_2_STAT64_SHIFT (0U) /*! STAT64 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT64(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT64_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT64_MASK) #define AON_FCCU_FHFLTS0_2_STAT65_MASK (0x2U) #define AON_FCCU_FHFLTS0_2_STAT65_SHIFT (1U) /*! STAT65 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT65(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT65_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT65_MASK) #define AON_FCCU_FHFLTS0_2_STAT66_MASK (0x4U) #define AON_FCCU_FHFLTS0_2_STAT66_SHIFT (2U) /*! STAT66 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT66(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT66_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT66_MASK) #define AON_FCCU_FHFLTS0_2_STAT67_MASK (0x8U) #define AON_FCCU_FHFLTS0_2_STAT67_SHIFT (3U) /*! STAT67 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT67(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT67_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT67_MASK) #define AON_FCCU_FHFLTS0_2_STAT68_MASK (0x10U) #define AON_FCCU_FHFLTS0_2_STAT68_SHIFT (4U) /*! STAT68 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT68(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT68_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT68_MASK) #define AON_FCCU_FHFLTS0_2_STAT69_MASK (0x20U) #define AON_FCCU_FHFLTS0_2_STAT69_SHIFT (5U) /*! STAT69 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT69(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT69_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT69_MASK) #define AON_FCCU_FHFLTS0_2_STAT70_MASK (0x40U) #define AON_FCCU_FHFLTS0_2_STAT70_SHIFT (6U) /*! STAT70 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT70(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT70_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT70_MASK) #define AON_FCCU_FHFLTS0_2_STAT71_MASK (0x80U) #define AON_FCCU_FHFLTS0_2_STAT71_SHIFT (7U) /*! STAT71 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT71(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT71_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT71_MASK) #define AON_FCCU_FHFLTS0_2_STAT72_MASK (0x100U) #define AON_FCCU_FHFLTS0_2_STAT72_SHIFT (8U) /*! STAT72 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT72(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT72_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT72_MASK) #define AON_FCCU_FHFLTS0_2_STAT73_MASK (0x200U) #define AON_FCCU_FHFLTS0_2_STAT73_SHIFT (9U) /*! STAT73 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT73(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT73_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT73_MASK) #define AON_FCCU_FHFLTS0_2_STAT74_MASK (0x400U) #define AON_FCCU_FHFLTS0_2_STAT74_SHIFT (10U) /*! STAT74 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT74(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT74_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT74_MASK) #define AON_FCCU_FHFLTS0_2_STAT75_MASK (0x800U) #define AON_FCCU_FHFLTS0_2_STAT75_SHIFT (11U) /*! STAT75 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT75(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT75_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT75_MASK) #define AON_FCCU_FHFLTS0_2_STAT76_MASK (0x1000U) #define AON_FCCU_FHFLTS0_2_STAT76_SHIFT (12U) /*! STAT76 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT76(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT76_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT76_MASK) #define AON_FCCU_FHFLTS0_2_STAT77_MASK (0x2000U) #define AON_FCCU_FHFLTS0_2_STAT77_SHIFT (13U) /*! STAT77 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT77(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT77_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT77_MASK) #define AON_FCCU_FHFLTS0_2_STAT78_MASK (0x4000U) #define AON_FCCU_FHFLTS0_2_STAT78_SHIFT (14U) /*! STAT78 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT78(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT78_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT78_MASK) #define AON_FCCU_FHFLTS0_2_STAT79_MASK (0x8000U) #define AON_FCCU_FHFLTS0_2_STAT79_SHIFT (15U) /*! STAT79 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT79(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT79_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT79_MASK) #define AON_FCCU_FHFLTS0_2_STAT80_MASK (0x10000U) #define AON_FCCU_FHFLTS0_2_STAT80_SHIFT (16U) /*! STAT80 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT80(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT80_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT80_MASK) #define AON_FCCU_FHFLTS0_2_STAT81_MASK (0x20000U) #define AON_FCCU_FHFLTS0_2_STAT81_SHIFT (17U) /*! STAT81 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT81(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT81_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT81_MASK) #define AON_FCCU_FHFLTS0_2_STAT82_MASK (0x40000U) #define AON_FCCU_FHFLTS0_2_STAT82_SHIFT (18U) /*! STAT82 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT82(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT82_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT82_MASK) #define AON_FCCU_FHFLTS0_2_STAT83_MASK (0x80000U) #define AON_FCCU_FHFLTS0_2_STAT83_SHIFT (19U) /*! STAT83 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT83(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT83_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT83_MASK) #define AON_FCCU_FHFLTS0_2_STAT84_MASK (0x100000U) #define AON_FCCU_FHFLTS0_2_STAT84_SHIFT (20U) /*! STAT84 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT84(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT84_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT84_MASK) #define AON_FCCU_FHFLTS0_2_STAT85_MASK (0x200000U) #define AON_FCCU_FHFLTS0_2_STAT85_SHIFT (21U) /*! STAT85 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT85(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT85_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT85_MASK) #define AON_FCCU_FHFLTS0_2_STAT86_MASK (0x400000U) #define AON_FCCU_FHFLTS0_2_STAT86_SHIFT (22U) /*! STAT86 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT86(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT86_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT86_MASK) #define AON_FCCU_FHFLTS0_2_STAT87_MASK (0x800000U) #define AON_FCCU_FHFLTS0_2_STAT87_SHIFT (23U) /*! STAT87 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT87(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT87_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT87_MASK) #define AON_FCCU_FHFLTS0_2_STAT88_MASK (0x1000000U) #define AON_FCCU_FHFLTS0_2_STAT88_SHIFT (24U) /*! STAT88 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT88(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT88_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT88_MASK) #define AON_FCCU_FHFLTS0_2_STAT89_MASK (0x2000000U) #define AON_FCCU_FHFLTS0_2_STAT89_SHIFT (25U) /*! STAT89 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT89(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT89_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT89_MASK) #define AON_FCCU_FHFLTS0_2_STAT90_MASK (0x4000000U) #define AON_FCCU_FHFLTS0_2_STAT90_SHIFT (26U) /*! STAT90 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT90(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT90_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT90_MASK) #define AON_FCCU_FHFLTS0_2_STAT91_MASK (0x8000000U) #define AON_FCCU_FHFLTS0_2_STAT91_SHIFT (27U) /*! STAT91 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT91(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT91_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT91_MASK) #define AON_FCCU_FHFLTS0_2_STAT92_MASK (0x10000000U) #define AON_FCCU_FHFLTS0_2_STAT92_SHIFT (28U) /*! STAT92 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT92(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT92_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT92_MASK) #define AON_FCCU_FHFLTS0_2_STAT93_MASK (0x20000000U) #define AON_FCCU_FHFLTS0_2_STAT93_SHIFT (29U) /*! STAT93 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT93(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT93_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT93_MASK) #define AON_FCCU_FHFLTS0_2_STAT94_MASK (0x40000000U) #define AON_FCCU_FHFLTS0_2_STAT94_SHIFT (30U) /*! STAT94 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT94(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT94_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT94_MASK) #define AON_FCCU_FHFLTS0_2_STAT95_MASK (0x80000000U) #define AON_FCCU_FHFLTS0_2_STAT95_SHIFT (31U) /*! STAT95 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_2_STAT95(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT95_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT95_MASK) /*! @} */ @@ -3780,320 +3783,320 @@ typedef struct { #define AON_FCCU_FHFLTS0_3_STAT96_MASK (0x1U) #define AON_FCCU_FHFLTS0_3_STAT96_SHIFT (0U) /*! STAT96 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT96(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT96_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT96_MASK) #define AON_FCCU_FHFLTS0_3_STAT97_MASK (0x2U) #define AON_FCCU_FHFLTS0_3_STAT97_SHIFT (1U) /*! STAT97 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT97(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT97_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT97_MASK) #define AON_FCCU_FHFLTS0_3_STAT98_MASK (0x4U) #define AON_FCCU_FHFLTS0_3_STAT98_SHIFT (2U) /*! STAT98 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT98(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT98_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT98_MASK) #define AON_FCCU_FHFLTS0_3_STAT99_MASK (0x8U) #define AON_FCCU_FHFLTS0_3_STAT99_SHIFT (3U) /*! STAT99 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT99(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT99_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT99_MASK) #define AON_FCCU_FHFLTS0_3_STAT100_MASK (0x10U) #define AON_FCCU_FHFLTS0_3_STAT100_SHIFT (4U) /*! STAT100 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT100(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT100_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT100_MASK) #define AON_FCCU_FHFLTS0_3_STAT101_MASK (0x20U) #define AON_FCCU_FHFLTS0_3_STAT101_SHIFT (5U) /*! STAT101 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT101(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT101_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT101_MASK) #define AON_FCCU_FHFLTS0_3_STAT102_MASK (0x40U) #define AON_FCCU_FHFLTS0_3_STAT102_SHIFT (6U) /*! STAT102 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT102(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT102_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT102_MASK) #define AON_FCCU_FHFLTS0_3_STAT103_MASK (0x80U) #define AON_FCCU_FHFLTS0_3_STAT103_SHIFT (7U) /*! STAT103 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT103(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT103_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT103_MASK) #define AON_FCCU_FHFLTS0_3_STAT104_MASK (0x100U) #define AON_FCCU_FHFLTS0_3_STAT104_SHIFT (8U) /*! STAT104 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT104(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT104_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT104_MASK) #define AON_FCCU_FHFLTS0_3_STAT105_MASK (0x200U) #define AON_FCCU_FHFLTS0_3_STAT105_SHIFT (9U) /*! STAT105 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT105(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT105_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT105_MASK) #define AON_FCCU_FHFLTS0_3_STAT106_MASK (0x400U) #define AON_FCCU_FHFLTS0_3_STAT106_SHIFT (10U) /*! STAT106 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT106(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT106_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT106_MASK) #define AON_FCCU_FHFLTS0_3_STAT107_MASK (0x800U) #define AON_FCCU_FHFLTS0_3_STAT107_SHIFT (11U) /*! STAT107 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT107(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT107_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT107_MASK) #define AON_FCCU_FHFLTS0_3_STAT108_MASK (0x1000U) #define AON_FCCU_FHFLTS0_3_STAT108_SHIFT (12U) /*! STAT108 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT108(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT108_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT108_MASK) #define AON_FCCU_FHFLTS0_3_STAT109_MASK (0x2000U) #define AON_FCCU_FHFLTS0_3_STAT109_SHIFT (13U) /*! STAT109 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT109(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT109_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT109_MASK) #define AON_FCCU_FHFLTS0_3_STAT110_MASK (0x4000U) #define AON_FCCU_FHFLTS0_3_STAT110_SHIFT (14U) /*! STAT110 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT110(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT110_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT110_MASK) #define AON_FCCU_FHFLTS0_3_STAT111_MASK (0x8000U) #define AON_FCCU_FHFLTS0_3_STAT111_SHIFT (15U) /*! STAT111 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT111(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT111_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT111_MASK) #define AON_FCCU_FHFLTS0_3_STAT112_MASK (0x10000U) #define AON_FCCU_FHFLTS0_3_STAT112_SHIFT (16U) /*! STAT112 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT112(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT112_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT112_MASK) #define AON_FCCU_FHFLTS0_3_STAT113_MASK (0x20000U) #define AON_FCCU_FHFLTS0_3_STAT113_SHIFT (17U) /*! STAT113 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT113(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT113_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT113_MASK) #define AON_FCCU_FHFLTS0_3_STAT114_MASK (0x40000U) #define AON_FCCU_FHFLTS0_3_STAT114_SHIFT (18U) /*! STAT114 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT114(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT114_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT114_MASK) #define AON_FCCU_FHFLTS0_3_STAT115_MASK (0x80000U) #define AON_FCCU_FHFLTS0_3_STAT115_SHIFT (19U) /*! STAT115 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT115(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT115_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT115_MASK) #define AON_FCCU_FHFLTS0_3_STAT116_MASK (0x100000U) #define AON_FCCU_FHFLTS0_3_STAT116_SHIFT (20U) /*! STAT116 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT116(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT116_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT116_MASK) #define AON_FCCU_FHFLTS0_3_STAT117_MASK (0x200000U) #define AON_FCCU_FHFLTS0_3_STAT117_SHIFT (21U) /*! STAT117 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT117(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT117_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT117_MASK) #define AON_FCCU_FHFLTS0_3_STAT118_MASK (0x400000U) #define AON_FCCU_FHFLTS0_3_STAT118_SHIFT (22U) /*! STAT118 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT118(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT118_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT118_MASK) #define AON_FCCU_FHFLTS0_3_STAT119_MASK (0x800000U) #define AON_FCCU_FHFLTS0_3_STAT119_SHIFT (23U) /*! STAT119 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT119(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT119_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT119_MASK) #define AON_FCCU_FHFLTS0_3_STAT120_MASK (0x1000000U) #define AON_FCCU_FHFLTS0_3_STAT120_SHIFT (24U) /*! STAT120 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT120(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT120_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT120_MASK) #define AON_FCCU_FHFLTS0_3_STAT121_MASK (0x2000000U) #define AON_FCCU_FHFLTS0_3_STAT121_SHIFT (25U) /*! STAT121 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT121(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT121_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT121_MASK) #define AON_FCCU_FHFLTS0_3_STAT122_MASK (0x4000000U) #define AON_FCCU_FHFLTS0_3_STAT122_SHIFT (26U) /*! STAT122 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT122(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT122_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT122_MASK) #define AON_FCCU_FHFLTS0_3_STAT123_MASK (0x8000000U) #define AON_FCCU_FHFLTS0_3_STAT123_SHIFT (27U) /*! STAT123 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT123(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT123_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT123_MASK) #define AON_FCCU_FHFLTS0_3_STAT124_MASK (0x10000000U) #define AON_FCCU_FHFLTS0_3_STAT124_SHIFT (28U) /*! STAT124 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT124(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT124_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT124_MASK) #define AON_FCCU_FHFLTS0_3_STAT125_MASK (0x20000000U) #define AON_FCCU_FHFLTS0_3_STAT125_SHIFT (29U) /*! STAT125 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT125(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT125_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT125_MASK) #define AON_FCCU_FHFLTS0_3_STAT126_MASK (0x40000000U) #define AON_FCCU_FHFLTS0_3_STAT126_SHIFT (30U) /*! STAT126 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT126(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT126_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT126_MASK) #define AON_FCCU_FHFLTS0_3_STAT127_MASK (0x80000000U) #define AON_FCCU_FHFLTS0_3_STAT127_SHIFT (31U) /*! STAT127 - Fault Status - * 0b0..Not latched * 0b0..No effect - * 0b1..Latched + * 0b0..Not latched * 0b1..Deasserts (clear) + * 0b1..Latched */ #define AON_FCCU_FHFLTS0_3_STAT127(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_3_STAT127_SHIFT)) & AON_FCCU_FHFLTS0_3_STAT127_MASK) /*! @} */ @@ -6756,5 +6759,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_FCCU_H_ */ +#endif /* PERI_AON_FCCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_INTM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_INTM.h index 39038c130..a8995f3b7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_INTM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_INTM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_INTM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_INTM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_INTM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_INTM * * CMSIS Peripheral Access Layer for AON_INTM */ -#if !defined(AON_INTM_H_) -#define AON_INTM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_INTM_H_) +#define PERI_AON_INTM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -355,5 +358,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_INTM_H_ */ +#endif /* PERI_AON_INTM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_LSTCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_LSTCU.h index 534a4398f..f720cdf34 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_LSTCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_LSTCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_LSTCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_LSTCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_LSTCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_LSTCU * * CMSIS Peripheral Access Layer for AON_LSTCU */ -#if !defined(AON_LSTCU_H_) -#define AON_LSTCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_LSTCU_H_) +#define PERI_AON_LSTCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -433,5 +436,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_LSTCU_H_ */ +#endif /* PERI_AON_LSTCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_MCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_MCM.h index 1d3d20551..5942d8738 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_MCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_MCM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_MCM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_MCM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_MCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_MCM * * CMSIS Peripheral Access Layer for AON_MCM */ -#if !defined(AON_MCM_H_) -#define AON_MCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_MCM_H_) +#define PERI_AON_MCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -538,5 +541,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_MCM_H_ */ +#endif /* PERI_AON_MCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_SYSPM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_SYSPM.h index 0a3db7d1f..052ba1876 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_SYSPM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_SYSPM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_SYSPM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_SYSPM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_SYSPM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_SYSPM * * CMSIS Peripheral Access Layer for AON_SYSPM */ -#if !defined(AON_SYSPM_H_) -#define AON_SYSPM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_SYSPM_H_) +#define PERI_AON_SYSPM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -431,5 +434,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_SYSPM_H_ */ +#endif /* PERI_AON_SYSPM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_TCU.h index 95a7c20b0..a2f453e24 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_TCU * * CMSIS Peripheral Access Layer for AON_TCU */ -#if !defined(AON_TCU_H_) -#define AON_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_TCU_H_) +#define PERI_AON_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -463,5 +466,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_TCU_H_ */ +#endif /* PERI_AON_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_TRDC_MGR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_TRDC_MGR.h index c4b1827ee..f6abef9b0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_TRDC_MGR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AON_TRDC_MGR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AON_TRDC_MGR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AON_TRDC_MGR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AON_TRDC_MGR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AON_TRDC_MGR * * CMSIS Peripheral Access Layer for AON_TRDC_MGR */ -#if !defined(AON_TRDC_MGR_H_) -#define AON_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AON_TRDC_MGR_H_) +#define PERI_AON_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -123654,5 +123657,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AON_TRDC_MGR_H_ */ +#endif /* PERI_AON_TRDC_MGR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ARDB.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ARDB.h index a2091fe97..72a7a7d4a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ARDB.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ARDB.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ARDB @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ARDB.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ARDB.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ARDB * * CMSIS Peripheral Access Layer for ARDB */ -#if !defined(ARDB_H_) -#define ARDB_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ARDB_H_) +#define PERI_ARDB_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -285,5 +288,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ARDB_H_ */ +#endif /* PERI_ARDB_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ATU_USB2.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ATU_USB2.h index 104ea092e..ef4a7d689 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ATU_USB2.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ATU_USB2.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ATU_USB2 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ATU_USB2.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ATU_USB2.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ATU_USB2 * * CMSIS Peripheral Access Layer for ATU_USB2 */ -#if !defined(ATU_USB2_H_) -#define ATU_USB2_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ATU_USB2_H_) +#define PERI_ATU_USB2_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -806,5 +809,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ATU_USB2_H_ */ +#endif /* PERI_ATU_USB2_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AXBS.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AXBS.h index ce04b0656..5caaf2ee4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AXBS.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_AXBS.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AXBS @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file AXBS.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_AXBS.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for AXBS * * CMSIS Peripheral Access Layer for AXBS */ -#if !defined(AXBS_H_) -#define AXBS_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_AXBS_H_) +#define PERI_AXBS_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -682,5 +685,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* AXBS_H_ */ +#endif /* PERI_AXBS_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBNSM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBNSM.h index aa214ff52..081328a77 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBNSM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBNSM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BBNSM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BBNSM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_BBNSM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BBNSM * * CMSIS Peripheral Access Layer for BBNSM */ -#if !defined(BBNSM_H_) -#define BBNSM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BBNSM_H_) +#define PERI_BBNSM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -698,5 +701,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BBNSM_H_ */ +#endif /* PERI_BBNSM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBSM_BLK_CTRL_BBSMMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBSM_BLK_CTRL_BBSMMIX.h index a279390bd..f8df72538 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBSM_BLK_CTRL_BBSMMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBSM_BLK_CTRL_BBSMMIX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BBSM_BLK_CTRL_BBSMMIX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BBSM_BLK_CTRL_BBSMMIX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_BBSM_BLK_CTRL_BBSMMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BBSM_BLK_CTRL_BBSMMIX * * CMSIS Peripheral Access Layer for BBSM_BLK_CTRL_BBSMMIX */ -#if !defined(BBSM_BLK_CTRL_BBSMMIX_H_) -#define BBSM_BLK_CTRL_BBSMMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BBSM_BLK_CTRL_BBSMMIX_H_) +#define PERI_BBSM_BLK_CTRL_BBSMMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -310,5 +313,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BBSM_BLK_CTRL_BBSMMIX_H_ */ +#endif /* PERI_BBSM_BLK_CTRL_BBSMMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBSM_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBSM_TCU.h index c2f1d4db3..7345c0eb6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBSM_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BBSM_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BBSM_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BBSM_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_BBSM_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BBSM_TCU * * CMSIS Peripheral Access Layer for BBSM_TCU */ -#if !defined(BBSM_TCU_H_) -#define BBSM_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BBSM_TCU_H_) +#define PERI_BBSM_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -330,5 +333,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BBSM_TCU_H_ */ +#endif /* PERI_BBSM_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BISS.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BISS.h index 1b4eccdfa..d24d7c711 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BISS.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BISS.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BISS @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BISS.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_BISS.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BISS * * CMSIS Peripheral Access Layer for BISS */ -#if !defined(BISS_H_) -#define BISS_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BISS_H_) +#define PERI_BISS_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -963,5 +966,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BISS_H_ */ +#endif /* PERI_BISS_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_NETCMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_NETCMIX.h index 5afcf0ca3..010d6f73f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_NETCMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_NETCMIX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_NETCMIX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BLK_CTRL_NETCMIX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_BLK_CTRL_NETCMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BLK_CTRL_NETCMIX * * CMSIS Peripheral Access Layer for BLK_CTRL_NETCMIX */ -#if !defined(BLK_CTRL_NETCMIX_H_) -#define BLK_CTRL_NETCMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BLK_CTRL_NETCMIX_H_) +#define PERI_BLK_CTRL_NETCMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1640,5 +1643,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BLK_CTRL_NETCMIX_H_ */ +#endif /* PERI_BLK_CTRL_NETCMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_NS_AONMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_NS_AONMIX.h index 8a415bb6d..8c1bfc107 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_NS_AONMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_NS_AONMIX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_NS_AONMIX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BLK_CTRL_NS_AONMIX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_BLK_CTRL_NS_AONMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BLK_CTRL_NS_AONMIX * * CMSIS Peripheral Access Layer for BLK_CTRL_NS_AONMIX */ -#if !defined(BLK_CTRL_NS_AONMIX_H_) -#define BLK_CTRL_NS_AONMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BLK_CTRL_NS_AONMIX_H_) +#define PERI_BLK_CTRL_NS_AONMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -3214,5 +3217,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BLK_CTRL_NS_AONMIX_H_ */ +#endif /* PERI_BLK_CTRL_NS_AONMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_S_AONMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_S_AONMIX.h index b26c0a8d8..2db8db36a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_S_AONMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_S_AONMIX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_S_AONMIX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BLK_CTRL_S_AONMIX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_BLK_CTRL_S_AONMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BLK_CTRL_S_AONMIX * * CMSIS Peripheral Access Layer for BLK_CTRL_S_AONMIX */ -#if !defined(BLK_CTRL_S_AONMIX_H_) -#define BLK_CTRL_S_AONMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BLK_CTRL_S_AONMIX_H_) +#define PERI_BLK_CTRL_S_AONMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2182,5 +2185,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BLK_CTRL_S_AONMIX_H_ */ +#endif /* PERI_BLK_CTRL_S_AONMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_WAKEUPMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_WAKEUPMIX.h index 263e1daed..3d4c0daa8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_WAKEUPMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_BLK_CTRL_WAKEUPMIX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_WAKEUPMIX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file BLK_CTRL_WAKEUPMIX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_BLK_CTRL_WAKEUPMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for BLK_CTRL_WAKEUPMIX * * CMSIS Peripheral Access Layer for BLK_CTRL_WAKEUPMIX */ -#if !defined(BLK_CTRL_WAKEUPMIX_H_) -#define BLK_CTRL_WAKEUPMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_BLK_CTRL_WAKEUPMIX_H_) +#define PERI_BLK_CTRL_WAKEUPMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -7547,5 +7550,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* BLK_CTRL_WAKEUPMIX_H_ */ +#endif /* PERI_BLK_CTRL_WAKEUPMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CACHE_ECC_MCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CACHE_ECC_MCM.h index 4aa2e9c86..aac1d51a8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CACHE_ECC_MCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CACHE_ECC_MCM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CACHE_ECC_MCM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CACHE_ECC_MCM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_CACHE_ECC_MCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CACHE_ECC_MCM * * CMSIS Peripheral Access Layer for CACHE_ECC_MCM */ -#if !defined(CACHE_ECC_MCM_H_) -#define CACHE_ECC_MCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CACHE_ECC_MCM_H_) +#define PERI_CACHE_ECC_MCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -290,80 +293,80 @@ typedef struct { #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_MASK (0x100U) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_SHIFT (8U) /*! CODE_CACHE_ECC_ERRM_INT - Code Cache Access Multibit ECC Error Interrupt Status - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_MASK (0x200U) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_SHIFT (9U) /*! CODE_CACHE_ECC_ERRS_INT - Code Cache Access Single-Bit ECC Error Interrupt Status - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_MASK (0x400U) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_SHIFT (10U) /*! CODE_CACHE_ECC_ERRM_OVER_INT - Code Cache Access Multiple Multibit ECC Error Interrupt Status - * 0b0..Not more than one error * 0b0..No effect - * 0b1..Multiple errors + * 0b0..Not more than one error * 0b1..Clear the flag + * 0b1..Multiple errors */ #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_MASK (0x800U) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_SHIFT (11U) /*! CODE_CACHE_ECC_ERRS_OVER_INT - Code Cache Access Multiple Single-Bit ECC Error Interrupt Status - * 0b0..Not more than one error * 0b0..No effect - * 0b1..Multiple errors + * 0b0..Not more than one error * 0b1..Clear the flag + * 0b1..Multiple errors */ #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_MASK (0x1000U) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_SHIFT (12U) /*! SYSTEM_CACHE_ECC_ERRM_INT - System Cache Access Multibit ECC Error Interrupt Status - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_MASK (0x2000U) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_SHIFT (13U) /*! SYSTEM_CACHE_ECC_ERRS_INT - System Cache Access Single-Bit ECC Error Interrupt Status - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_MASK (0x4000U) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_SHIFT (14U) /*! SYSTEM_CACHE_ECC_ERRM_OVER_INT - System Cache Access Multiple Multibit ECC Error Interrupt Status - * 0b0..Not more than one error * 0b0..No effect - * 0b1..Multiple errors + * 0b0..Not more than one error * 0b1..Clear the flag + * 0b1..Multiple errors */ #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_MASK (0x8000U) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_SHIFT (15U) /*! SYSTEM_CACHE_ECC_ERRS_OVER_INT - System Cache Access Multiple Single-Bit ECC Error Interrupt Status - * 0b0..Not more than one error * 0b0..No effect - * 0b1..Multiple errors + * 0b0..Not more than one error * 0b1..Clear the flag + * 0b1..Multiple errors */ #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_MASK) /*! @} */ @@ -1082,5 +1085,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CACHE_ECC_MCM_H_ */ +#endif /* PERI_CACHE_ECC_MCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAMERA_ATU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAMERA_ATU.h index 42945bc9d..b62e12a52 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAMERA_ATU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAMERA_ATU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAMERA_ATU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CAMERA_ATU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_CAMERA_ATU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CAMERA_ATU * * CMSIS Peripheral Access Layer for CAMERA_ATU */ -#if !defined(CAMERA_ATU_H_) -#define CAMERA_ATU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CAMERA_ATU_H_) +#define PERI_CAMERA_ATU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -806,5 +809,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CAMERA_ATU_H_ */ +#endif /* PERI_CAMERA_ATU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAMIX_BLK_CTRL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAMIX_BLK_CTRL.h index 08c1681d7..80ad0560e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAMIX_BLK_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAMIX_BLK_CTRL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAMIX_BLK_CTRL @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CAMIX_BLK_CTRL.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_CAMIX_BLK_CTRL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CAMIX_BLK_CTRL * * CMSIS Peripheral Access Layer for CAMIX_BLK_CTRL */ -#if !defined(CAMIX_BLK_CTRL_H_) -#define CAMIX_BLK_CTRL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CAMIX_BLK_CTRL_H_) +#define PERI_CAMIX_BLK_CTRL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -773,5 +776,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CAMIX_BLK_CTRL_H_ */ +#endif /* PERI_CAMIX_BLK_CTRL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAN.h index 7c42ec267..d47013a8c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CAN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CAN.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_CAN.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CAN * * CMSIS Peripheral Access Layer for CAN */ -#if !defined(CAN_H_) -#define CAN_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CAN_H_) +#define PERI_CAN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2391,5 +2394,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CAN_H_ */ +#endif /* PERI_CAN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CCM.h index 9e948d391..707c56a81 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CCM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CCM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_CCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CCM * * CMSIS Peripheral Access Layer for CCM */ -#if !defined(CCM_H_) -#define CCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CCM_H_) +#define PERI_CCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2182,5 +2185,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CCM_H_ */ +#endif /* PERI_CCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CCMSRCGPC_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CCMSRCGPC_TCU.h index af9455b83..2e774ad62 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CCMSRCGPC_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CCMSRCGPC_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCMSRCGPC_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CCMSRCGPC_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_CCMSRCGPC_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CCMSRCGPC_TCU * * CMSIS Peripheral Access Layer for CCMSRCGPC_TCU */ -#if !defined(CCMSRCGPC_TCU_H_) -#define CCMSRCGPC_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CCMSRCGPC_TCU_H_) +#define PERI_CCMSRCGPC_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -346,5 +349,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CCMSRCGPC_TCU_H_ */ +#endif /* PERI_CCMSRCGPC_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CORTEXA_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CORTEXA_TCU.h index 2fb891dbb..efeaddc57 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CORTEXA_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_CORTEXA_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CORTEXA_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file CORTEXA_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_CORTEXA_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for CORTEXA_TCU * * CMSIS Peripheral Access Layer for CORTEXA_TCU */ -#if !defined(CORTEXA_TCU_H_) -#define CORTEXA_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_CORTEXA_TCU_H_) +#define PERI_CORTEXA_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -346,5 +349,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* CORTEXA_TCU_H_ */ +#endif /* PERI_CORTEXA_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DCIF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DCIF.h index 7520a0082..c769d53be 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DCIF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DCIF.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCIF @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DCIF.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DCIF.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DCIF * * CMSIS Peripheral Access Layer for DCIF */ -#if !defined(DCIF_H_) -#define DCIF_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DCIF_H_) +#define PERI_DCIF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2307,5 +2310,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DCIF_H_ */ +#endif /* PERI_DCIF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDRC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDRC.h new file mode 100644 index 000000000..e03c848e7 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDRC.h @@ -0,0 +1,4492 @@ +/* +** ################################################################### +** Processors: MIMX94398AVKE_ca55 +** MIMX94398AVKE_cm33_core0 +** MIMX94398AVKE_cm33_core1 +** MIMX94398AVKE_cm7_core0 +** MIMX94398AVKE_cm7_core1 +** MIMX94398AVKJ_ca55 +** MIMX94398AVKJ_cm33_core0 +** MIMX94398AVKJ_cm33_core1 +** MIMX94398AVKJ_cm7_core0 +** MIMX94398AVKJ_cm7_core1 +** MIMX94398AVKM_ca55 +** MIMX94398AVKM_cm33_core0 +** MIMX94398AVKM_cm33_core1 +** MIMX94398AVKM_cm7_core0 +** MIMX94398AVKM_cm7_core1 +** MIMX94398AVME_ca55 +** MIMX94398AVME_cm33_core0 +** MIMX94398AVME_cm33_core1 +** MIMX94398AVME_cm7_core0 +** MIMX94398AVME_cm7_core1 +** MIMX94398AVMJ_ca55 +** MIMX94398AVMJ_cm33_core0 +** MIMX94398AVMJ_cm33_core1 +** MIMX94398AVMJ_cm7_core0 +** MIMX94398AVMJ_cm7_core1 +** MIMX94398AVMM_ca55 +** MIMX94398AVMM_cm33_core0 +** MIMX94398AVMM_cm33_core1 +** MIMX94398AVMM_cm7_core0 +** MIMX94398AVMM_cm7_core1 +** MIMX94398CVKE_ca55 +** MIMX94398CVKE_cm33_core0 +** MIMX94398CVKE_cm33_core1 +** MIMX94398CVKE_cm7_core0 +** MIMX94398CVKE_cm7_core1 +** MIMX94398CVKJ_ca55 +** MIMX94398CVKJ_cm33_core0 +** MIMX94398CVKJ_cm33_core1 +** MIMX94398CVKJ_cm7_core0 +** MIMX94398CVKJ_cm7_core1 +** MIMX94398CVKM_ca55 +** MIMX94398CVKM_cm33_core0 +** MIMX94398CVKM_cm33_core1 +** MIMX94398CVKM_cm7_core0 +** MIMX94398CVKM_cm7_core1 +** MIMX94398CVME_ca55 +** MIMX94398CVME_cm33_core0 +** MIMX94398CVME_cm33_core1 +** MIMX94398CVME_cm7_core0 +** MIMX94398CVME_cm7_core1 +** MIMX94398CVMJ_ca55 +** MIMX94398CVMJ_cm33_core0 +** MIMX94398CVMJ_cm33_core1 +** MIMX94398CVMJ_cm7_core0 +** MIMX94398CVMJ_cm7_core1 +** MIMX94398CVMM_ca55 +** MIMX94398CVMM_cm33_core0 +** MIMX94398CVMM_cm33_core1 +** MIMX94398CVMM_cm7_core0 +** MIMX94398CVMM_cm7_core1 +** MIMX94398DVKE_ca55 +** MIMX94398DVKE_cm33_core0 +** MIMX94398DVKE_cm33_core1 +** MIMX94398DVKE_cm7_core0 +** MIMX94398DVKE_cm7_core1 +** MIMX94398DVKJ_ca55 +** MIMX94398DVKJ_cm33_core0 +** MIMX94398DVKJ_cm33_core1 +** MIMX94398DVKJ_cm7_core0 +** MIMX94398DVKJ_cm7_core1 +** MIMX94398DVKM_ca55 +** MIMX94398DVKM_cm33_core0 +** MIMX94398DVKM_cm33_core1 +** MIMX94398DVKM_cm7_core0 +** MIMX94398DVKM_cm7_core1 +** MIMX94398DVME_ca55 +** MIMX94398DVME_cm33_core0 +** MIMX94398DVME_cm33_core1 +** MIMX94398DVME_cm7_core0 +** MIMX94398DVME_cm7_core1 +** MIMX94398DVMJ_ca55 +** MIMX94398DVMJ_cm33_core0 +** MIMX94398DVMJ_cm33_core1 +** MIMX94398DVMJ_cm7_core0 +** MIMX94398DVMJ_cm7_core1 +** MIMX94398DVMM_ca55 +** MIMX94398DVMM_cm33_core0 +** MIMX94398DVMM_cm33_core1 +** MIMX94398DVMM_cm7_core0 +** MIMX94398DVMM_cm7_core1 +** MIMX94398XVKE_ca55 +** MIMX94398XVKE_cm33_core0 +** MIMX94398XVKE_cm33_core1 +** MIMX94398XVKE_cm7_core0 +** MIMX94398XVKE_cm7_core1 +** MIMX94398XVKJ_ca55 +** MIMX94398XVKJ_cm33_core0 +** MIMX94398XVKJ_cm33_core1 +** MIMX94398XVKJ_cm7_core0 +** MIMX94398XVKJ_cm7_core1 +** MIMX94398XVKM_ca55 +** MIMX94398XVKM_cm33_core0 +** MIMX94398XVKM_cm33_core1 +** MIMX94398XVKM_cm7_core0 +** MIMX94398XVKM_cm7_core1 +** MIMX94398XVME_ca55 +** MIMX94398XVME_cm33_core0 +** MIMX94398XVME_cm33_core1 +** MIMX94398XVME_cm7_core0 +** MIMX94398XVME_cm7_core1 +** MIMX94398XVMJ_ca55 +** MIMX94398XVMJ_cm33_core0 +** MIMX94398XVMJ_cm33_core1 +** MIMX94398XVMJ_cm7_core0 +** MIMX94398XVMJ_cm7_core1 +** MIMX94398XVMM_ca55 +** MIMX94398XVMM_cm33_core0 +** MIMX94398XVMM_cm33_core1 +** MIMX94398XVMM_cm7_core0 +** MIMX94398XVMM_cm7_core1 +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 +** +** Abstract: +** CMSIS Peripheral Access Layer for DDRC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-11-01) +** Initial version. +** core name and core alias name +** +---------------------------------------------------------------------+ +** | core name | core alias name | +** +---------------------------------------------------------------------+ +** | cm33_core0 | m33, cm33 | +** +---------------------------------------------------------------------+ +** | cm33_core1 | m33_2, cm33_2, cm33_sync, netcmix_cm33 | +** +---------------------------------------------------------------------+ +** | cm7_core0 | m7, cm7 | +** +---------------------------------------------------------------------+ +** | cm7_core1 | m7_2, cm7_2 | +** +---------------------------------------------------------------------+ +** | ca55_core0 | a55, ca55, a55_0, ca55_0 | +** +---------------------------------------------------------------------+ +** | ca55_core1 | a55, ca55, a55_1, ca55_1 | +** +---------------------------------------------------------------------+ +** | ca55_core2 | a55, ca55, a55_2, ca55_2 | +** +---------------------------------------------------------------------+ +** | ca55_core3 | a55, ca55, a55_3, ca55_3 | +** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_DDRC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for DDRC + * + * CMSIS Peripheral Access Layer for DDRC + */ + +#if !defined(PERI_DDRC_H_) +#define PERI_DDRC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) +#include "MIMX94398_ca55_COMMON.h" +#elif (defined(CPU_MIMX94398AVKE_cm33_core0) || defined(CPU_MIMX94398AVKJ_cm33_core0) || defined(CPU_MIMX94398AVKM_cm33_core0) || defined(CPU_MIMX94398AVME_cm33_core0) || defined(CPU_MIMX94398AVMJ_cm33_core0) || defined(CPU_MIMX94398AVMM_cm33_core0) || defined(CPU_MIMX94398CVKE_cm33_core0) || defined(CPU_MIMX94398CVKJ_cm33_core0) || defined(CPU_MIMX94398CVKM_cm33_core0) || defined(CPU_MIMX94398CVME_cm33_core0) || defined(CPU_MIMX94398CVMJ_cm33_core0) || defined(CPU_MIMX94398CVMM_cm33_core0) || defined(CPU_MIMX94398DVKE_cm33_core0) || defined(CPU_MIMX94398DVKJ_cm33_core0) || defined(CPU_MIMX94398DVKM_cm33_core0) || defined(CPU_MIMX94398DVME_cm33_core0) || defined(CPU_MIMX94398DVMJ_cm33_core0) || defined(CPU_MIMX94398DVMM_cm33_core0) || defined(CPU_MIMX94398XVKE_cm33_core0) || defined(CPU_MIMX94398XVKJ_cm33_core0) || defined(CPU_MIMX94398XVKM_cm33_core0) || defined(CPU_MIMX94398XVME_cm33_core0) || defined(CPU_MIMX94398XVMJ_cm33_core0) || defined(CPU_MIMX94398XVMM_cm33_core0)) +#include "MIMX94398_cm33_core0_COMMON.h" +#elif (defined(CPU_MIMX94398AVKE_cm33_core1) || defined(CPU_MIMX94398AVKJ_cm33_core1) || defined(CPU_MIMX94398AVKM_cm33_core1) || defined(CPU_MIMX94398AVME_cm33_core1) || defined(CPU_MIMX94398AVMJ_cm33_core1) || defined(CPU_MIMX94398AVMM_cm33_core1) || defined(CPU_MIMX94398CVKE_cm33_core1) || defined(CPU_MIMX94398CVKJ_cm33_core1) || defined(CPU_MIMX94398CVKM_cm33_core1) || defined(CPU_MIMX94398CVME_cm33_core1) || defined(CPU_MIMX94398CVMJ_cm33_core1) || defined(CPU_MIMX94398CVMM_cm33_core1) || defined(CPU_MIMX94398DVKE_cm33_core1) || defined(CPU_MIMX94398DVKJ_cm33_core1) || defined(CPU_MIMX94398DVKM_cm33_core1) || defined(CPU_MIMX94398DVME_cm33_core1) || defined(CPU_MIMX94398DVMJ_cm33_core1) || defined(CPU_MIMX94398DVMM_cm33_core1) || defined(CPU_MIMX94398XVKE_cm33_core1) || defined(CPU_MIMX94398XVKJ_cm33_core1) || defined(CPU_MIMX94398XVKM_cm33_core1) || defined(CPU_MIMX94398XVME_cm33_core1) || defined(CPU_MIMX94398XVMJ_cm33_core1) || defined(CPU_MIMX94398XVMM_cm33_core1)) +#include "MIMX94398_cm33_core1_COMMON.h" +#elif (defined(CPU_MIMX94398AVKE_cm7_core0) || defined(CPU_MIMX94398AVKJ_cm7_core0) || defined(CPU_MIMX94398AVKM_cm7_core0) || defined(CPU_MIMX94398AVME_cm7_core0) || defined(CPU_MIMX94398AVMJ_cm7_core0) || defined(CPU_MIMX94398AVMM_cm7_core0) || defined(CPU_MIMX94398CVKE_cm7_core0) || defined(CPU_MIMX94398CVKJ_cm7_core0) || defined(CPU_MIMX94398CVKM_cm7_core0) || defined(CPU_MIMX94398CVME_cm7_core0) || defined(CPU_MIMX94398CVMJ_cm7_core0) || defined(CPU_MIMX94398CVMM_cm7_core0) || defined(CPU_MIMX94398DVKE_cm7_core0) || defined(CPU_MIMX94398DVKJ_cm7_core0) || defined(CPU_MIMX94398DVKM_cm7_core0) || defined(CPU_MIMX94398DVME_cm7_core0) || defined(CPU_MIMX94398DVMJ_cm7_core0) || defined(CPU_MIMX94398DVMM_cm7_core0) || defined(CPU_MIMX94398XVKE_cm7_core0) || defined(CPU_MIMX94398XVKJ_cm7_core0) || defined(CPU_MIMX94398XVKM_cm7_core0) || defined(CPU_MIMX94398XVME_cm7_core0) || defined(CPU_MIMX94398XVMJ_cm7_core0) || defined(CPU_MIMX94398XVMM_cm7_core0)) +#include "MIMX94398_cm7_core0_COMMON.h" +#elif (defined(CPU_MIMX94398AVKE_cm7_core1) || defined(CPU_MIMX94398AVKJ_cm7_core1) || defined(CPU_MIMX94398AVKM_cm7_core1) || defined(CPU_MIMX94398AVME_cm7_core1) || defined(CPU_MIMX94398AVMJ_cm7_core1) || defined(CPU_MIMX94398AVMM_cm7_core1) || defined(CPU_MIMX94398CVKE_cm7_core1) || defined(CPU_MIMX94398CVKJ_cm7_core1) || defined(CPU_MIMX94398CVKM_cm7_core1) || defined(CPU_MIMX94398CVME_cm7_core1) || defined(CPU_MIMX94398CVMJ_cm7_core1) || defined(CPU_MIMX94398CVMM_cm7_core1) || defined(CPU_MIMX94398DVKE_cm7_core1) || defined(CPU_MIMX94398DVKJ_cm7_core1) || defined(CPU_MIMX94398DVKM_cm7_core1) || defined(CPU_MIMX94398DVME_cm7_core1) || defined(CPU_MIMX94398DVMJ_cm7_core1) || defined(CPU_MIMX94398DVMM_cm7_core1) || defined(CPU_MIMX94398XVKE_cm7_core1) || defined(CPU_MIMX94398XVKJ_cm7_core1) || defined(CPU_MIMX94398XVKM_cm7_core1) || defined(CPU_MIMX94398XVME_cm7_core1) || defined(CPU_MIMX94398XVMJ_cm7_core1) || defined(CPU_MIMX94398XVMM_cm7_core1)) +#include "MIMX94398_cm7_core1_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- DDRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer + * @{ + */ + +/** DDRC - Size of Registers Arrays */ +#define DDRC_CS_BNDS_COUNT 2u +#define DDRC_CS_CONFIG_COUNT 2u +#define DDRC_DDR_MTP_COUNT 10u + +/** DDRC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x8 */ + __IO uint32_t CS_BNDS; /**< Rank 0 Memory Bounds..Rank 1 Memory Bounds, array offset: 0x0, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } CS_BNDS[DDRC_CS_BNDS_COUNT]; + __IO uint32_t REMAP_EXT_0; /**< Remap Extended Region 0 Configuration, offset: 0x10 */ + __IO uint32_t REMAP_EXT_1; /**< Remap Extended Region 1 Configuration, offset: 0x14 */ + __IO uint32_t REMAP_EXT_2; /**< Remap Extended Region 2 Configuration, offset: 0x18 */ + __IO uint32_t REMAP_EXT_3; /**< Remap Extended Region 3 Configuration, offset: 0x1C */ + __IO uint32_t REMAP_0A; /**< Remap Region 0A Configuration, offset: 0x20 */ + __IO uint32_t REMAP_0B; /**< Remap Region 0B Configuration, offset: 0x24 */ + __IO uint32_t REMAP_1A; /**< Remap Region 1A Configuration, offset: 0x28 */ + __IO uint32_t REMAP_1B; /**< Remap Region 1B Configuration, offset: 0x2C */ + __IO uint32_t REMAP_2A; /**< Remap Region 2A Configuration, offset: 0x30 */ + __IO uint32_t REMAP_2B; /**< Remap Region 2B Configuration, offset: 0x34 */ + __IO uint32_t REMAP_3A; /**< Remap Region 3A Configuration, offset: 0x38 */ + __IO uint32_t REMAP_3B; /**< Remap Region 3B Configuration, offset: 0x3C */ + __IO uint32_t DDR_ADDR_DEC_0; /**< DDRC Address Decode 0, offset: 0x40 */ + __IO uint32_t DDR_ADDR_DEC_1; /**< DDRC Address Decode 1, offset: 0x44 */ + __IO uint32_t DDR_ADDR_DEC_2; /**< DDRC Address Decode 2, offset: 0x48 */ + __IO uint32_t DDR_ADDR_DEC_3; /**< DDRC Address Decode 3, offset: 0x4C */ + __IO uint32_t DDR_ADDR_DEC_4; /**< DDRC Address Decode 4, offset: 0x50 */ + __IO uint32_t DDR_ADDR_DEC_5; /**< DDRC Address Decode 5, offset: 0x54 */ + __IO uint32_t DDR_ADDR_DEC_6; /**< DDRC Address Decode 6, offset: 0x58 */ + __IO uint32_t DDR_ADDR_DEC_7; /**< DDRC Address Decode 7, offset: 0x5C */ + __IO uint32_t DDR_ADDR_DEC_8; /**< DDRC Address Decode 8, offset: 0x60 */ + __IO uint32_t DDR_ADDR_DEC_9; /**< DDRC Address Decode 9, offset: 0x64 */ + uint8_t RESERVED_0[24]; + __IO uint32_t CS_CONFIG[DDRC_CS_CONFIG_COUNT]; /**< Rank 0 Configuration..Rank 1 Configuration, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_1[120]; + __IO uint32_t TIMING_CFG_3; /**< DDR SDRAM Timing Configuration 3, offset: 0x100 */ + __IO uint32_t TIMING_CFG_0; /**< DDR SDRAM Timing Configuration 0, offset: 0x104 */ + __IO uint32_t TIMING_CFG_1; /**< DDR SDRAM Timing Configuration 1, offset: 0x108 */ + __IO uint32_t TIMING_CFG_2; /**< DDR SDRAM Timing Configuration 2, offset: 0x10C */ + __IO uint32_t DDR_SDRAM_CFG; /**< DDR SDRAM Control Configuration, offset: 0x110 */ + __IO uint32_t DDR_SDRAM_CFG_2; /**< DDR SDRAM Control Configuration 2, offset: 0x114 */ + uint8_t RESERVED_2[8]; + __IO uint32_t DDR_SDRAM_MD_CNTL; /**< DDR SDRAM Mode Control, offset: 0x120 */ + __IO uint32_t DDR_SDRAM_INTERVAL; /**< DDR SDRAM Interval Configuration, offset: 0x124 */ + __IO uint32_t DDR_DATA_INIT; /**< DDR SDRAM Data Initialization, offset: 0x128 */ + uint8_t RESERVED_3[52]; + __IO uint32_t TIMING_CFG_4; /**< DDR SDRAM Timing Configuration 4, offset: 0x160 */ + uint8_t RESERVED_4[8]; + __IO uint32_t TIMING_CFG_7; /**< DDR SDRAM Timing Configuration 7, offset: 0x16C */ + __IO uint32_t DDR_ZQ_CNTL; /**< DDR SDRAM ZQ Calibration Control, offset: 0x170 */ + uint8_t RESERVED_5[8]; + __IO uint32_t DDR_SR_CNTR; /**< DDR SDRAM Self-Refresh Counter, offset: 0x17C */ + uint8_t RESERVED_6[208]; + __IO uint32_t TIMING_CFG_8; /**< DDR SDRAM Timing Configuration 8, offset: 0x250 */ + __IO uint32_t TIMING_CFG_9; /**< DDR SDRAM timing configuration 9, offset: 0x254 */ + __IO uint32_t TIMING_CFG_10; /**< DDR SDRAM Timing Configuration 10, offset: 0x258 */ + __IO uint32_t TIMING_CFG_11; /**< DDR SDRAM Timing Configuration 11, offset: 0x25C */ + __IO uint32_t DDR_SDRAM_CFG_3; /**< DDR SDRAM Control Configuration 3, offset: 0x260 */ + uint8_t RESERVED_7[4]; + __IO uint32_t DDR_SDRAM_CFG_5; /**< DDR SDRAM Control Configuration 5, offset: 0x268 */ + __IO uint32_t DDR_SDRAM_CFG_6; /**< DDR SDRAM Control Configuration 6, offset: 0x26C */ + __IO uint32_t DDR_SDRAM_MD_CNTL2; /**< DDR SDRAM mode control 2, offset: 0x270 */ + uint8_t RESERVED_8[24]; + __I uint32_t DDR_SDRAM_MPR4; /**< DDR SDRAM multi-purpose register 4, offset: 0x28C */ + __IO uint32_t DDR_SDRAM_MPR5; /**< DDR SDRAM multi-purpose register 5, offset: 0x290 */ + uint8_t RESERVED_9[44]; + __I uint32_t DDR_SDRAM_REF_RATE; /**< DDR Refresh Rate, offset: 0x2C0 */ + uint8_t RESERVED_10[60]; + __IO uint32_t TIMING_CFG_12; /**< DDR SDRAM Timing Configuration 12, offset: 0x300 */ + __IO uint32_t TIMING_CFG_13; /**< DDR SDRAM Timing Configuration 13, offset: 0x304 */ + __IO uint32_t TIMING_CFG_14; /**< DDR SDRAM Timing Configuration 14, offset: 0x308 */ + __IO uint32_t TIMING_CFG_15; /**< DDR SDRAM Timing Configuration 15, offset: 0x30C */ + __IO uint32_t TIMING_CFG_16; /**< DDR SDRAM Timing Configuration 16, offset: 0x310 */ + __IO uint32_t TIMING_CFG_17; /**< DDR SDRAM Timing Configuration 17, offset: 0x314 */ + uint8_t RESERVED_11[1256]; + __IO uint32_t TX_CFG_1; /**< Transaction Configuration Register 1, offset: 0x800 */ + __IO uint32_t TX_CFG_2; /**< Transaction Configuration Register 2, offset: 0x804 */ + uint8_t RESERVED_12[796]; + __IO uint32_t DDRDSR_2; /**< DDR SDRAM Debug Status 2, offset: 0xB24 */ + uint8_t RESERVED_13[208]; + __I uint32_t DDR_IP_REV1; /**< DDRC Revision 1, offset: 0xBF8 */ + uint8_t RESERVED_14[260]; + __IO uint32_t DDR_MTCR; /**< DDR SDRAM Memory Test Control, offset: 0xD00 */ + uint8_t RESERVED_15[28]; + __IO uint32_t DDR_MTP[DDRC_DDR_MTP_COUNT]; /**< DDR SDRAM Memory Test Pattern n, array offset: 0xD20, array step: 0x4 */ + uint8_t RESERVED_16[24]; + __IO uint32_t DDR_MT_ST_EXT_ADDR; /**< DDR SDRAM Memory Test Start Extended Address, offset: 0xD60 */ + __IO uint32_t DDR_MT_ST_ADDR; /**< DDR SDRAM Memory Test Start Address, offset: 0xD64 */ + __IO uint32_t DDR_MT_END_EXT_ADDR; /**< DDR SDRAM Memory Test End Extended Address, offset: 0xD68 */ + __IO uint32_t DDR_MT_END_ADDR; /**< DDR SDRAM Memory Test End Address, offset: 0xD6C */ + uint8_t RESERVED_17[656]; + __IO uint32_t ERR_EN; /**< Error Enable, offset: 0x1000 */ + uint8_t RESERVED_18[252]; + __IO uint32_t DATA_ERR_INJECT_HI; /**< Memory Data Path Error Injection Mask High, offset: 0x1100 */ + __IO uint32_t DATA_ERR_INJECT_LO; /**< Memory Data Path Error Injection Mask Low, offset: 0x1104 */ + __IO uint32_t ERR_INJECT; /**< Memory Data Path Error Injection Mask ECC, offset: 0x1108 */ + __IO uint32_t ADDR_ERR_INJ; /**< Address Error Inject, offset: 0x110C */ + __IO uint32_t EXT_ADDR_ERR_INJ; /**< Extended Address Error Inject, offset: 0x1110 */ + uint8_t RESERVED_19[4]; + __IO uint32_t CAPTURE_EXT_DATA_HI; /**< Memory Extended Data Path Read Capture High, offset: 0x1118 */ + __IO uint32_t CAPTURE_EXT_DATA_LO; /**< Memory Extended Data Path Read Capture Low, offset: 0x111C */ + __IO uint32_t CAPTURE_DATA_HI; /**< Memory Data Path Read Capture High, offset: 0x1120 */ + __IO uint32_t CAPTURE_DATA_LO; /**< Memory Data Path Read Capture Low, offset: 0x1124 */ + __IO uint32_t CAPTURE_ECC; /**< Memory Data Path Read Capture ECC, offset: 0x1128 */ + uint8_t RESERVED_20[20]; + __IO uint32_t ERR_DETECT; /**< Memory Error Detect, offset: 0x1140 */ + __IO uint32_t ERR_DISABLE; /**< Memory Error Disable, offset: 0x1144 */ + __IO uint32_t ERR_INT_EN; /**< Memory Error Interrupt Enable, offset: 0x1148 */ + __IO uint32_t CAPTURE_ATTRIBUTES; /**< Memory Error Attributes Capture, offset: 0x114C */ + __IO uint32_t CAPTURE_ADDRESS; /**< Memory Error Address Capture, offset: 0x1150 */ + __IO uint32_t CAPTURE_EXT_ADDRESS; /**< Memory Error Extended Address Capture, offset: 0x1154 */ + __IO uint32_t ERR_SBE; /**< Single-Bit ECC Memory Error Management, offset: 0x1158 */ + uint8_t RESERVED_21[180]; + __IO uint32_t REG_CRC_GRP_1; /**< Register CRC Code For Group 1, offset: 0x1210 */ + __IO uint32_t REG_CRC_GRP_2; /**< Register CRC Code For Group 2, offset: 0x1214 */ + uint8_t RESERVED_22[8]; + __IO uint32_t ECC_EXT_REG_0; /**< ECC Extended Region 0 Configuration, offset: 0x1220 */ + __IO uint32_t ECC_EXT_REG_1; /**< ECC Extended Region 1 Configuration, offset: 0x1224 */ + __IO uint32_t ECC_EXT_REG_2; /**< ECC Extended Region 2 Configuration, offset: 0x1228 */ + __IO uint32_t ECC_EXT_REG_3; /**< ECC Extended Region 3 Configuration, offset: 0x122C */ + __IO uint32_t ECC_EXT_REG_4; /**< ECC Extended Region 4 Configuration, offset: 0x1230 */ + __IO uint32_t ECC_EXT_REG_5; /**< ECC Extended Region 5 Configuration, offset: 0x1234 */ + __IO uint32_t ECC_EXT_REG_6; /**< ECC Extended Region 6 Configuration, offset: 0x1238 */ + __IO uint32_t ECC_EXT_REG_7; /**< ECC Extended Region 7 Configuration, offset: 0x123C */ + __IO uint32_t ECC_REG_0; /**< ECC Region 0 Configuration, offset: 0x1240 */ + __IO uint32_t ECC_REG_1; /**< ECC Region 1 Configuration, offset: 0x1244 */ + __IO uint32_t ECC_REG_2; /**< ECC Region 2 Configuration, offset: 0x1248 */ + __IO uint32_t ECC_REG_3; /**< ECC Region 3 Configuration, offset: 0x124C */ + __IO uint32_t ECC_REG_4; /**< ECC Region 4 Configuration, offset: 0x1250 */ + __IO uint32_t ECC_REG_5; /**< ECC Region 5 Configuration, offset: 0x1254 */ + __IO uint32_t ECC_REG_6; /**< ECC Region 6 Configuration, offset: 0x1258 */ + __IO uint32_t ECC_REG_7; /**< ECC Region 7 Configuration, offset: 0x125C */ + uint8_t RESERVED_23[64416]; + __IO uint32_t PMGC0; /**< Performance Monitor Global Control, offset: 0x10E00 */ + uint8_t RESERVED_24[12]; + __IO uint32_t PMLCA0; /**< Performance Monitor Local Control A0, offset: 0x10E10 */ + __IO uint32_t PMLCB0; /**< Performance Monitor Local Control B0, offset: 0x10E14 */ + __IO uint32_t PMC0A; /**< PMC 0a, offset: 0x10E18 */ + __IO uint32_t PMC0B; /**< PMC 0b, offset: 0x10E1C */ + __IO uint32_t PMLCA1; /**< Performance Monitor Local Control A, offset: 0x10E20 */ + __IO uint32_t PMLCB1; /**< Performance Monitor Local Control B, offset: 0x10E24 */ + __IO uint32_t PMC1; /**< Performance Monitor Counter, offset: 0x10E28 */ + uint8_t RESERVED_25[4]; + __IO uint32_t PMLCA2; /**< Performance Monitor Local Control A, offset: 0x10E30 */ + __IO uint32_t PMLCB2; /**< Performance Monitor Local Control B, offset: 0x10E34 */ + __IO uint32_t PMC2; /**< Performance Monitor Counter, offset: 0x10E38 */ + uint8_t RESERVED_26[4]; + __IO uint32_t PMLCA3; /**< Performance Monitor Local Control A, offset: 0x10E40 */ + __IO uint32_t PMLCB3; /**< Performance Monitor Local Control B, offset: 0x10E44 */ + __IO uint32_t PMC3; /**< Performance Monitor Counter, offset: 0x10E48 */ + uint8_t RESERVED_27[4]; + __IO uint32_t PMLCA4; /**< Performance Monitor Local Control A, offset: 0x10E50 */ + __IO uint32_t PMLCB4; /**< Performance Monitor Local Control B, offset: 0x10E54 */ + __IO uint32_t PMC4; /**< Performance Monitor Counter, offset: 0x10E58 */ + uint8_t RESERVED_28[4]; + __IO uint32_t PMLCA5; /**< Performance Monitor Local Control A, offset: 0x10E60 */ + __IO uint32_t PMLCB5; /**< Performance Monitor Local Control B, offset: 0x10E64 */ + __IO uint32_t PMC5; /**< Performance Monitor Counter, offset: 0x10E68 */ + uint8_t RESERVED_29[4]; + __IO uint32_t PMLCA6; /**< Performance Monitor Local Control A, offset: 0x10E70 */ + __IO uint32_t PMLCB6; /**< Performance Monitor Local Control B, offset: 0x10E74 */ + __IO uint32_t PMC6; /**< Performance Monitor Counter, offset: 0x10E78 */ + uint8_t RESERVED_30[4]; + __IO uint32_t PMLCA7; /**< Performance Monitor Local Control A, offset: 0x10E80 */ + __IO uint32_t PMLCB7; /**< Performance Monitor Local Control B, offset: 0x10E84 */ + __IO uint32_t PMC7; /**< Performance Monitor Counter, offset: 0x10E88 */ + uint8_t RESERVED_31[4]; + __IO uint32_t PMLCA8; /**< Performance Monitor Local Control A, offset: 0x10E90 */ + __IO uint32_t PMLCB8; /**< Performance Monitor Local Control B, offset: 0x10E94 */ + __IO uint32_t PMC8; /**< Performance Monitor Counter, offset: 0x10E98 */ + uint8_t RESERVED_32[4]; + __IO uint32_t PMLCA9; /**< Performance Monitor Local Control A, offset: 0x10EA0 */ + __IO uint32_t PMLCB9; /**< Performance Monitor Local Control B, offset: 0x10EA4 */ + __IO uint32_t PMC9; /**< Performance Monitor Counter, offset: 0x10EA8 */ + uint8_t RESERVED_33[4]; + __IO uint32_t PMLCA10; /**< Performance Monitor Local Control A, offset: 0x10EB0 */ + __IO uint32_t PMLCB10; /**< Performance Monitor Local Control B, offset: 0x10EB4 */ + __IO uint32_t PMC10; /**< Performance Monitor Counter, offset: 0x10EB8 */ +} DDRC_Type; + +/* ---------------------------------------------------------------------------- + -- DDRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Register_Masks DDRC Register Masks + * @{ + */ + +/*! @name CS_BNDS - Rank 0 Memory Bounds..Rank 1 Memory Bounds */ +/*! @{ */ + +#define DDRC_CS_BNDS_EA_MASK (0xFFFFU) +#define DDRC_CS_BNDS_EA_SHIFT (0U) +/*! EA - Ending Address */ +#define DDRC_CS_BNDS_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_BNDS_EA_SHIFT)) & DDRC_CS_BNDS_EA_MASK) + +#define DDRC_CS_BNDS_SA_MASK (0xFFFF0000U) +#define DDRC_CS_BNDS_SA_SHIFT (16U) +/*! SA - Starting Address */ +#define DDRC_CS_BNDS_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_BNDS_SA_SHIFT)) & DDRC_CS_BNDS_SA_MASK) +/*! @} */ + +/*! @name REMAP_EXT_0 - Remap Extended Region 0 Configuration */ +/*! @{ */ + +#define DDRC_REMAP_EXT_0_EXT_REG_0_EA_MASK (0xFFU) +#define DDRC_REMAP_EXT_0_EXT_REG_0_EA_SHIFT (0U) +/*! EXT_REG_0_EA - Region 0 Extended Ending Address */ +#define DDRC_REMAP_EXT_0_EXT_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_0_EXT_REG_0_EA_SHIFT)) & DDRC_REMAP_EXT_0_EXT_REG_0_EA_MASK) + +#define DDRC_REMAP_EXT_0_EXT_REG_0_SA_MASK (0xFF00U) +#define DDRC_REMAP_EXT_0_EXT_REG_0_SA_SHIFT (8U) +/*! EXT_REG_0_SA - Region 0 Extended Starting Address */ +#define DDRC_REMAP_EXT_0_EXT_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_0_EXT_REG_0_SA_SHIFT)) & DDRC_REMAP_EXT_0_EXT_REG_0_SA_MASK) + +#define DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR_MASK (0xFF0000U) +#define DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR_SHIFT (16U) +/*! REG_0_EXT_REMAP_ADDR - Region 0 Extended Remap Starting Address */ +#define DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR_SHIFT)) & DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR_MASK) +/*! @} */ + +/*! @name REMAP_EXT_1 - Remap Extended Region 1 Configuration */ +/*! @{ */ + +#define DDRC_REMAP_EXT_1_EXT_REG_1_EA_MASK (0xFFU) +#define DDRC_REMAP_EXT_1_EXT_REG_1_EA_SHIFT (0U) +/*! EXT_REG_1_EA - Region 1 Extended Ending Address */ +#define DDRC_REMAP_EXT_1_EXT_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_1_EXT_REG_1_EA_SHIFT)) & DDRC_REMAP_EXT_1_EXT_REG_1_EA_MASK) + +#define DDRC_REMAP_EXT_1_EXT_REG_1_SA_MASK (0xFF00U) +#define DDRC_REMAP_EXT_1_EXT_REG_1_SA_SHIFT (8U) +/*! EXT_REG_1_SA - Region 1 Extended Starting Address */ +#define DDRC_REMAP_EXT_1_EXT_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_1_EXT_REG_1_SA_SHIFT)) & DDRC_REMAP_EXT_1_EXT_REG_1_SA_MASK) + +#define DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR_MASK (0xFF0000U) +#define DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR_SHIFT (16U) +/*! REG_1_EXT_REMAP_ADDR - Region 1 Extended Remap Starting Address */ +#define DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR_SHIFT)) & DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR_MASK) +/*! @} */ + +/*! @name REMAP_EXT_2 - Remap Extended Region 2 Configuration */ +/*! @{ */ + +#define DDRC_REMAP_EXT_2_EXT_REG_2_EA_MASK (0xFFU) +#define DDRC_REMAP_EXT_2_EXT_REG_2_EA_SHIFT (0U) +/*! EXT_REG_2_EA - Region 2 Extended Ending Address */ +#define DDRC_REMAP_EXT_2_EXT_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_2_EXT_REG_2_EA_SHIFT)) & DDRC_REMAP_EXT_2_EXT_REG_2_EA_MASK) + +#define DDRC_REMAP_EXT_2_EXT_REG_2_SA_MASK (0xFF00U) +#define DDRC_REMAP_EXT_2_EXT_REG_2_SA_SHIFT (8U) +/*! EXT_REG_2_SA - Region 2 Extended Starting Address */ +#define DDRC_REMAP_EXT_2_EXT_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_2_EXT_REG_2_SA_SHIFT)) & DDRC_REMAP_EXT_2_EXT_REG_2_SA_MASK) + +#define DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR_MASK (0xFF0000U) +#define DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR_SHIFT (16U) +/*! REG_2_EXT_REMAP_ADDR - Region 2 Extended Remap Starting Address */ +#define DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR_SHIFT)) & DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR_MASK) +/*! @} */ + +/*! @name REMAP_EXT_3 - Remap Extended Region 3 Configuration */ +/*! @{ */ + +#define DDRC_REMAP_EXT_3_EXT_REG_3_EA_MASK (0xFFU) +#define DDRC_REMAP_EXT_3_EXT_REG_3_EA_SHIFT (0U) +/*! EXT_REG_3_EA - Region 3 Extended Ending Address */ +#define DDRC_REMAP_EXT_3_EXT_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_3_EXT_REG_3_EA_SHIFT)) & DDRC_REMAP_EXT_3_EXT_REG_3_EA_MASK) + +#define DDRC_REMAP_EXT_3_EXT_REG_3_SA_MASK (0xFF00U) +#define DDRC_REMAP_EXT_3_EXT_REG_3_SA_SHIFT (8U) +/*! EXT_REG_3_SA - Region 3 Extended Starting Address */ +#define DDRC_REMAP_EXT_3_EXT_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_3_EXT_REG_3_SA_SHIFT)) & DDRC_REMAP_EXT_3_EXT_REG_3_SA_MASK) + +#define DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR_MASK (0xFF0000U) +#define DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR_SHIFT (16U) +/*! REG_3_EXT_REMAP_ADDR - Region 3 Extended Remap Starting Address */ +#define DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR_SHIFT)) & DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR_MASK) +/*! @} */ + +/*! @name REMAP_0A - Remap Region 0A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT (0U) +/*! REG_0_REMAP_ADDR - Region 0 Remap Starting Address */ +#define DDRC_REMAP_0A_REG_0_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT)) & DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK) + +#define DDRC_REMAP_0A_REG_0_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT (31U) +/*! REG_0_REMAP_EN - Region 0 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_0A_REG_0_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT)) & DDRC_REMAP_0A_REG_0_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_0B - Remap Region 0B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_0B_REG_0_EA_MASK (0xFFFU) +#define DDRC_REMAP_0B_REG_0_EA_SHIFT (0U) +/*! REG_0_EA - Region 0 Ending Address */ +#define DDRC_REMAP_0B_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0B_REG_0_EA_SHIFT)) & DDRC_REMAP_0B_REG_0_EA_MASK) + +#define DDRC_REMAP_0B_REG_0_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_0B_REG_0_SA_SHIFT (16U) +/*! REG_0_SA - Region 0 Starting Address */ +#define DDRC_REMAP_0B_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0B_REG_0_SA_SHIFT)) & DDRC_REMAP_0B_REG_0_SA_MASK) +/*! @} */ + +/*! @name REMAP_1A - Remap Region 1A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT (0U) +/*! REG_1_REMAP_ADDR - Region 1 Remap Starting Address */ +#define DDRC_REMAP_1A_REG_1_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT)) & DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK) + +#define DDRC_REMAP_1A_REG_1_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT (31U) +/*! REG_1_REMAP_EN - Region 1 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_1A_REG_1_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT)) & DDRC_REMAP_1A_REG_1_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_1B - Remap Region 1B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_1B_REG_1_EA_MASK (0xFFFU) +#define DDRC_REMAP_1B_REG_1_EA_SHIFT (0U) +/*! REG_1_EA - Region 1 Ending Address */ +#define DDRC_REMAP_1B_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1B_REG_1_EA_SHIFT)) & DDRC_REMAP_1B_REG_1_EA_MASK) + +#define DDRC_REMAP_1B_REG_1_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_1B_REG_1_SA_SHIFT (16U) +/*! REG_1_SA - Region 1 Starting Address */ +#define DDRC_REMAP_1B_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1B_REG_1_SA_SHIFT)) & DDRC_REMAP_1B_REG_1_SA_MASK) +/*! @} */ + +/*! @name REMAP_2A - Remap Region 2A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT (0U) +/*! REG_2_REMAP_ADDR - Region 2 Remap Starting Address */ +#define DDRC_REMAP_2A_REG_2_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT)) & DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK) + +#define DDRC_REMAP_2A_REG_2_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT (31U) +/*! REG_2_REMAP_EN - Region 2 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_2A_REG_2_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT)) & DDRC_REMAP_2A_REG_2_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_2B - Remap Region 2B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_2B_REG_2_EA_MASK (0xFFFU) +#define DDRC_REMAP_2B_REG_2_EA_SHIFT (0U) +/*! REG_2_EA - Region 2 Ending Address */ +#define DDRC_REMAP_2B_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2B_REG_2_EA_SHIFT)) & DDRC_REMAP_2B_REG_2_EA_MASK) + +#define DDRC_REMAP_2B_REG_2_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_2B_REG_2_SA_SHIFT (16U) +/*! REG_2_SA - Region 2 Starting Address */ +#define DDRC_REMAP_2B_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2B_REG_2_SA_SHIFT)) & DDRC_REMAP_2B_REG_2_SA_MASK) +/*! @} */ + +/*! @name REMAP_3A - Remap Region 3A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT (0U) +/*! REG_3_REMAP_ADDR - Region 3 Remap Starting Address */ +#define DDRC_REMAP_3A_REG_3_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT)) & DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK) + +#define DDRC_REMAP_3A_REG_3_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT (31U) +/*! REG_3_REMAP_EN - Region 3 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_3A_REG_3_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT)) & DDRC_REMAP_3A_REG_3_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_3B - Remap Region 3B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_3B_REG_3_EA_MASK (0xFFFU) +#define DDRC_REMAP_3B_REG_3_EA_SHIFT (0U) +/*! REG_3_EA - Region 3 Ending Address */ +#define DDRC_REMAP_3B_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3B_REG_3_EA_SHIFT)) & DDRC_REMAP_3B_REG_3_EA_MASK) + +#define DDRC_REMAP_3B_REG_3_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_3B_REG_3_SA_SHIFT (16U) +/*! REG_3_SA - Region 3 Starting Address */ +#define DDRC_REMAP_3B_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3B_REG_3_SA_SHIFT)) & DDRC_REMAP_3B_REG_3_SA_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_0 - DDRC Address Decode 0 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT (2U) +/*! ROW14_OVRD - Row 14 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT (10U) +/*! ROW15_OVRD - Row 15 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT (18U) +/*! ROW16_OVRD - Row 16 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT (26U) +/*! ROW17_OVRD - Row 17 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_1 - DDRC Address Decode 1 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT (2U) +/*! ROW10_OVRD - Row 10 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT (10U) +/*! ROW11_OVRD - Row 11 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT (18U) +/*! ROW12_OVRD - Row 12 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT (26U) +/*! ROW13_OVRD - Row 13 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_2 - DDRC Address Decode 2 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT (2U) +/*! ROW6_OVRD - Row 6 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT (10U) +/*! ROW7_OVRD - Row 7 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT (18U) +/*! ROW8_OVRD - Row 8 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT (26U) +/*! ROW9_OVRD - Row 9 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_3 - DDRC Address Decode 3 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT (2U) +/*! ROW2_OVRD - Row 2 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT (10U) +/*! ROW3_OVRD - Row 3 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT (18U) +/*! ROW4_OVRD - Row 4 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT (26U) +/*! ROW5_OVRD - Row 5 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_4 - DDRC Address Decode 4 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT (2U) +/*! COL9_OVRD - Col 9 Override */ +#define DDRC_DDR_ADDR_DEC_4_COL9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT (10U) +/*! COL10_OVRD - Col 10 Override */ +#define DDRC_DDR_ADDR_DEC_4_COL10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT (18U) +/*! ROW0_OVRD - Row 0 Override */ +#define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT (26U) +/*! ROW1_OVRD - Row 1 Override */ +#define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_5 - DDRC Address Decode 5 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT (2U) +/*! COL5_OVRD - Col 5 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT (10U) +/*! COL6_OVRD - Col 6 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT (18U) +/*! COL7_OVRD - Col 7 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT (26U) +/*! COL8_OVRD - Col 8 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_6 - DDRC Address Decode 6 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT (2U) +/*! COL1_OVRD - Col 1 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT (10U) +/*! COL2_OVRD - Col 2 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT (18U) +/*! COL3_OVRD - Col 3 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT (26U) +/*! COL4_OVRD - Col 4 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_7 - DDRC Address Decode 7 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT (2U) +/*! CID1_OVRD - CID 1 Override */ +#define DDRC_DDR_ADDR_DEC_7_CID1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT (10U) +/*! BA0_OVRD - Bank 0 Override */ +#define DDRC_DDR_ADDR_DEC_7_BA0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT (18U) +/*! BA1_OVRD - Bank 1 Override */ +#define DDRC_DDR_ADDR_DEC_7_BA1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT (26U) +/*! COL0_OVRD - Col 0 Override */ +#define DDRC_DDR_ADDR_DEC_7_COL0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_8 - DDRC Address Decode 8 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT (2U) +/*! BG1_OVRD - Bank Group 1 Override */ +#define DDRC_DDR_ADDR_DEC_8_BG1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT (10U) +/*! CS0_OVRD - Interleaved Rank 0 Override */ +#define DDRC_DDR_ADDR_DEC_8_CS0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT (18U) +/*! CS1_OVRD - Interleaved Rank 1 Override */ +#define DDRC_DDR_ADDR_DEC_8_CS1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT (26U) +/*! CID0_OVRD - CID 0 Override */ +#define DDRC_DDR_ADDR_DEC_8_CID0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_9 - DDRC Address Decode 9 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK (0x1U) +#define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT (0U) +/*! ADDR_DEC_OVRD - Address Decode Override */ +#define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT (26U) +/*! BG0_OVRD - Bank Group 0 Override */ +#define DDRC_DDR_ADDR_DEC_9_BG0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK) +/*! @} */ + +/*! @name CS_CONFIG - Rank 0 Configuration..Rank 1 Configuration */ +/*! @{ */ + +#define DDRC_CS_CONFIG_COL_BITS_CS_MASK (0x7U) +#define DDRC_CS_CONFIG_COL_BITS_CS_SHIFT (0U) +/*! COL_BITS_CS - Column Bits + * 0b000..8 + * 0b001..9 + * 0b010..10 + * 0b011..11 + * 0b111..7 + */ +#define DDRC_CS_CONFIG_COL_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_COL_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_COL_BITS_CS_MASK) + +#define DDRC_CS_CONFIG_BG_BITS_CS_MASK (0x30U) +#define DDRC_CS_CONFIG_BG_BITS_CS_SHIFT (4U) +/*! BG_BITS_CS - Bank Group Bits + * 0b00..0 + * 0b01..Must be set to 1 to enable the 3rd bank address bit for LPDDR4, memories. + * 0b10..Reserved for LPDDR4 ,2 BG bits for LPDDR5 + * 0b11..Reserved + */ +#define DDRC_CS_CONFIG_BG_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_BG_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_BG_BITS_CS_MASK) + +#define DDRC_CS_CONFIG_ROW_BITS_CS_MASK (0x700U) +#define DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT (8U) +/*! ROW_BITS_CS - Row Bits + * 0b000..12 + * 0b001..13 + * 0b010..14 + * 0b011..15 + * 0b100..16 + * 0b101..17 + * 0b110..18 + */ +#define DDRC_CS_CONFIG_ROW_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_ROW_BITS_CS_MASK) + +#define DDRC_CS_CONFIG_AP_EN_MASK (0x800000U) +#define DDRC_CS_CONFIG_AP_EN_SHIFT (23U) +/*! AP_EN - Auto-Precharge Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_CS_CONFIG_AP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_AP_EN_SHIFT)) & DDRC_CS_CONFIG_AP_EN_MASK) + +#define DDRC_CS_CONFIG_CS_EN_MASK (0x80000000U) +#define DDRC_CS_CONFIG_CS_EN_SHIFT (31U) +/*! CS_EN - Rank Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_CS_CONFIG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_CS_EN_SHIFT)) & DDRC_CS_CONFIG_CS_EN_MASK) +/*! @} */ + +/*! @name TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_3_EXT_WRTORD_MASK (0x1U) +#define DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT (0U) +/*! EXT_WRTORD - Extended Write-To-Read Time */ +#define DDRC_TIMING_CFG_3_EXT_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WRTORD_MASK) + +#define DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK (0x2U) +#define DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT (1U) +/*! EXT_ACTTOACT - Extended Activate-To-Activate Time */ +#define DDRC_TIMING_CFG_3_EXT_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK) + +#define DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK (0x8U) +#define DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT (3U) +/*! EXT_FOUR_ACT - Extended Four Activate */ +#define DDRC_TIMING_CFG_3_EXT_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK) + +#define DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK (0x30U) +#define DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT (4U) +/*! EXT_CKE_PLS - Extended MCKE Pulse */ +#define DDRC_TIMING_CFG_3_EXT_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT)) & DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK) + +#define DDRC_TIMING_CFG_3_EXT_WRREC_MASK (0x700U) +#define DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT (8U) +/*! EXT_WRREC - Extended Write Recovery + * 0b111.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_3_EXT_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WRREC_MASK) + +#define DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK (0x800U) +#define DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT (11U) +/*! EXT_WR_LAT_2 - Extended Write Latency 2 */ +#define DDRC_TIMING_CFG_3_EXT_WR_LAT_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK) + +#define DDRC_TIMING_CFG_3_EXT_CASLAT_MASK (0x7000U) +#define DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT (12U) +/*! EXT_CASLAT - Extended CAS Latency */ +#define DDRC_TIMING_CFG_3_EXT_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_CASLAT_MASK) + +#define DDRC_TIMING_CFG_3_EXT_REFREC_MASK (0x3F0000U) +#define DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT (16U) +/*! EXT_REFREC - Extended Refresh Recovery */ +#define DDRC_TIMING_CFG_3_EXT_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT)) & DDRC_TIMING_CFG_3_EXT_REFREC_MASK) + +#define DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK (0xC00000U) +#define DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT (22U) +/*! EXT_ACTTORW - Extended Activate To Read Or Write Time */ +#define DDRC_TIMING_CFG_3_EXT_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK) + +#define DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK (0x7000000U) +#define DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT (24U) +/*! EXT_ACTTOPRE - Extended Activate-To-Precharge Time */ +#define DDRC_TIMING_CFG_3_EXT_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK) + +#define DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK (0x30000000U) +#define DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT (28U) +/*! EXT_PRETOACT - Extended Precharge-To-Activate Time */ +#define DDRC_TIMING_CFG_3_EXT_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_0_MRS_CYC_MASK (0x3FU) +#define DDRC_TIMING_CFG_0_MRS_CYC_SHIFT (0U) +/*! MRS_CYC - MRW Cycle Time + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_0_MRS_CYC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_MRS_CYC_SHIFT)) & DDRC_TIMING_CFG_0_MRS_CYC_MASK) + +#define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK (0x1000U) +#define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT (12U) +/*! EXT_ACT_PD_EXIT - Extended Active Power-Down Exit */ +#define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK (0xC000U) +#define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT (14U) +/*! EXT_PRE_PD_EXIT - Extended Precharge Power-Down Exit */ +#define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK (0xF0000U) +#define DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT (16U) +/*! PRE_PD_EXIT - Precharge Power-Down Exit + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_0_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK (0xF00000U) +#define DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT (20U) +/*! ACT_PD_EXIT - Active Powerdown Exit + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_0_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_WWT_MASK (0x3000000U) +#define DDRC_TIMING_CFG_0_WWT_SHIFT (24U) +/*! WWT - Write-To-Write Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WWT_SHIFT)) & DDRC_TIMING_CFG_0_WWT_MASK) + +#define DDRC_TIMING_CFG_0_RRT_MASK (0xC000000U) +#define DDRC_TIMING_CFG_0_RRT_SHIFT (26U) +/*! RRT - Read-To-Read Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_RRT_SHIFT)) & DDRC_TIMING_CFG_0_RRT_MASK) + +#define DDRC_TIMING_CFG_0_WRT_MASK (0x30000000U) +#define DDRC_TIMING_CFG_0_WRT_SHIFT (28U) +/*! WRT - Write-To-Read Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WRT_SHIFT)) & DDRC_TIMING_CFG_0_WRT_MASK) + +#define DDRC_TIMING_CFG_0_RWT_MASK (0xC0000000U) +#define DDRC_TIMING_CFG_0_RWT_SHIFT (30U) +/*! RWT - Read-To-Write Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_RWT_SHIFT)) & DDRC_TIMING_CFG_0_RWT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_1_WRTORD_MASK (0xFU) +#define DDRC_TIMING_CFG_1_WRTORD_SHIFT (0U) +/*! WRTORD - Write-To-Read Interval + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_WRTORD_SHIFT)) & DDRC_TIMING_CFG_1_WRTORD_MASK) + +#define DDRC_TIMING_CFG_1_ACTTOACT_MASK (0xF0U) +#define DDRC_TIMING_CFG_1_ACTTOACT_SHIFT (4U) +/*! ACTTOACT - Activate-To-Activate Interval + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTOACT_SHIFT)) & DDRC_TIMING_CFG_1_ACTTOACT_MASK) + +#define DDRC_TIMING_CFG_1_WRREC_MASK (0xF00U) +#define DDRC_TIMING_CFG_1_WRREC_SHIFT (8U) +/*! WRREC - Write Recovery */ +#define DDRC_TIMING_CFG_1_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_WRREC_SHIFT)) & DDRC_TIMING_CFG_1_WRREC_MASK) + +#define DDRC_TIMING_CFG_1_REFREC_MASK (0xF000U) +#define DDRC_TIMING_CFG_1_REFREC_SHIFT (12U) +/*! REFREC - Refresh Recovery */ +#define DDRC_TIMING_CFG_1_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_REFREC_SHIFT)) & DDRC_TIMING_CFG_1_REFREC_MASK) + +#define DDRC_TIMING_CFG_1_CASLAT_MASK (0xE0000U) +#define DDRC_TIMING_CFG_1_CASLAT_SHIFT (17U) +/*! CASLAT - CAS Latency */ +#define DDRC_TIMING_CFG_1_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_CASLAT_SHIFT)) & DDRC_TIMING_CFG_1_CASLAT_MASK) + +#define DDRC_TIMING_CFG_1_ACTTORW_MASK (0xF00000U) +#define DDRC_TIMING_CFG_1_ACTTORW_SHIFT (20U) +/*! ACTTORW - Activate To Read Or Write + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTORW_SHIFT)) & DDRC_TIMING_CFG_1_ACTTORW_MASK) + +#define DDRC_TIMING_CFG_1_ACTTOPRE_MASK (0xF000000U) +#define DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT (24U) +/*! ACTTOPRE - Activate-To-Precharge Time */ +#define DDRC_TIMING_CFG_1_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT)) & DDRC_TIMING_CFG_1_ACTTOPRE_MASK) + +#define DDRC_TIMING_CFG_1_PRETOACT_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_1_PRETOACT_SHIFT (28U) +/*! PRETOACT - Precharge-To-Activate Time + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_PRETOACT_SHIFT)) & DDRC_TIMING_CFG_1_PRETOACT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_2_FOUR_ACT_MASK (0x3FU) +#define DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT (0U) +/*! FOUR_ACT - Four Activate */ +#define DDRC_TIMING_CFG_2_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT)) & DDRC_TIMING_CFG_2_FOUR_ACT_MASK) + +#define DDRC_TIMING_CFG_2_CKE_PLS_MASK (0x1C0U) +#define DDRC_TIMING_CFG_2_CKE_PLS_SHIFT (6U) +/*! CKE_PLS - MCKE Pulse */ +#define DDRC_TIMING_CFG_2_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_CKE_PLS_SHIFT)) & DDRC_TIMING_CFG_2_CKE_PLS_MASK) + +#define DDRC_TIMING_CFG_2_RD_TO_PRE_MASK (0x3E000U) +#define DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT (13U) +/*! RD_TO_PRE - Read-To-Precharge Time + * 0b00000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_2_RD_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT)) & DDRC_TIMING_CFG_2_RD_TO_PRE_MASK) + +#define DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK (0x40000U) +#define DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT (18U) +/*! EXT_WR_LAT - Extended Write Latency */ +#define DDRC_TIMING_CFG_2_EXT_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT)) & DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK) + +#define DDRC_TIMING_CFG_2_WR_LAT_MASK (0x780000U) +#define DDRC_TIMING_CFG_2_WR_LAT_SHIFT (19U) +/*! WR_LAT - Write Latency */ +#define DDRC_TIMING_CFG_2_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_WR_LAT_SHIFT)) & DDRC_TIMING_CFG_2_WR_LAT_MASK) + +#define DDRC_TIMING_CFG_2_DERATE_VAL_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT (28U) +/*! DERATE_VAL - Derate Value */ +#define DDRC_TIMING_CFG_2_DERATE_VAL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT)) & DDRC_TIMING_CFG_2_DERATE_VAL_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_BI_MASK (0x1U) +#define DDRC_DDR_SDRAM_CFG_BI_SHIFT (0U) +/*! BI - Bypass Initialization + * 0b0..Reserved; do not use + * 0b1..Initialization routine is bypassed + */ +#define DDRC_DDR_SDRAM_CFG_BI(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_BI_SHIFT)) & DDRC_DDR_SDRAM_CFG_BI_MASK) + +#define DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK (0x2U) +#define DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT (1U) +/*! MEM_HALT - DDRC Halt + * 0b0..Accepts new transactions + * 0b1..Completes any remaining transactions and remains halted until you write 0 to this field + */ +#define DDRC_DDR_SDRAM_CFG_MEM_HALT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT)) & DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK) + +#define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK (0x7F00U) +#define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT (8U) +/*! BA_INTLV_CTL - Rank Interleaving Control + * 0b0000000..No external ranks are interleaved. + * 0b1000000..External ranks 0 and 1 are interleaved. + */ +#define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT)) & DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK) + +#define DDRC_DDR_SDRAM_CFG_DC_EN_MASK (0x10000U) +#define DDRC_DDR_SDRAM_CFG_DC_EN_SHIFT (16U) +/*! DC_EN - Dual Channel Enable + * 0b0..Dual independent 16-bit channels are not used + * 0b1..Dual independent 16-bit channels are used + */ +#define DDRC_DDR_SDRAM_CFG_DC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DC_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_DC_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_DBW_MASK (0x180000U) +#define DDRC_DDR_SDRAM_CFG_DBW_SHIFT (19U) +/*! DBW - DDR SDRAM Data Bus Width + * 0b01..32 bits + * 0b10..16 bits + */ +#define DDRC_DDR_SDRAM_CFG_DBW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DBW_SHIFT)) & DDRC_DDR_SDRAM_CFG_DBW_MASK) + +#define DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK (0x200000U) +#define DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT (21U) +/*! DYN_PWR - Dynamic Power Management + * 0b0..No + * 0b1..Yes + */ +#define DDRC_DDR_SDRAM_CFG_DYN_PWR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT)) & DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK) + +#define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK (0x7000000U) +#define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT (24U) +/*! SDRAM_TYPE - DDR SDRAM Type + * 0b001..LPDDR5 SDRAM + * 0b100..LPDDR4, SDRAM + */ +#define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT)) & DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK) + +#define DDRC_DDR_SDRAM_CFG_SREN_MASK (0x40000000U) +#define DDRC_DDR_SDRAM_CFG_SREN_SHIFT (30U) +/*! SREN - Self-Refresh Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_SREN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_SREN_SHIFT)) & DDRC_DDR_SDRAM_CFG_SREN_MASK) + +#define DDRC_DDR_SDRAM_CFG_MEM_EN_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT (31U) +/*! MEM_EN - DDRC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_MEM_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_MEM_EN_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_2 - DDR SDRAM Control Configuration 2 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK (0x10U) +#define DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT (4U) +/*! D_INIT - DDR SDRAM Data Initialization + * 0b0..No data initialization in progress, and none scheduled + * 0b1..DDRC to initialize the DDR SDRAM after DDRC is enabled + */ +#define DDRC_DDR_SDRAM_CFG_2_D_INIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK (0xF000U) +#define DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT (12U) +/*! NUM_PR - Number Of Posted Refreshes + * 0b0000, 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0100..4 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + */ +#define DDRC_DDR_SDRAM_CFG_2_NUM_PR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_BYTE_MODE_MASK (0x200000U) +#define DDRC_DDR_SDRAM_CFG_2_BYTE_MODE_SHIFT (21U) +/*! BYTE_MODE - Byte Mode. */ +#define DDRC_DDR_SDRAM_CFG_2_BYTE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_BYTE_MODE_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_BYTE_MODE_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK (0xF000000U) +#define DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT (24U) +/*! MCK_DIS - MCK Disable */ +#define DDRC_DDR_SDRAM_CFG_2_MCK_DIS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT (31U) +/*! FRC_SR - Force Self-Refresh + * 0b0..Normal mode + * 0b1..Self-Refresh mode + */ +#define DDRC_DDR_SDRAM_CFG_2_FRC_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_MD_CNTL - DDR SDRAM Mode Control */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK (0x3FFFFU) +#define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT (0U) +/*! MD_VALUE - Mode Register Value */ +#define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK (0x300000U) +#define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT (20U) +/*! CKE_CNTL - Clock Enable Control + * 0b00..Not forced + * 0b01..Forced to a lower value + * 0b10..Forced to a higher value + * 0b11..Force a powerdown exit command. You may only use this decoding when using LPDDR5 DDR SDRAM. If using + * this setting before DDR_SDRAM_CFG[MEM_EN] is set, then you must first set DDR_SDRAM_CFG[BI] to allow the + * powerdown exit command to be issued. + */ +#define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_START_OSC_MASK (0x400000U) +#define DDRC_DDR_SDRAM_MD_CNTL_START_OSC_SHIFT (22U) +/*! START_OSC - Start Oscillator + * 0b0..No + * 0b1..Yes + */ +#define DDRC_DDR_SDRAM_MD_CNTL_START_OSC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_START_OSC_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_START_OSC_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_START_OSC2_MASK (0x800000U) +#define DDRC_DDR_SDRAM_MD_CNTL_START_OSC2_SHIFT (23U) +/*! START_OSC2 - Start Oscillator 2 + * 0b0..No + * 0b1..Yes + */ +#define DDRC_DDR_SDRAM_MD_CNTL_START_OSC2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_START_OSC2_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_START_OSC2_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK (0xF000000U) +#define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT (24U) +/*! MD_SEL - Mode Register Select + * 0b0000..MR + * 0b0001..EMR + * 0b0010..EMR2 + * 0b0011..EMR3 + */ +#define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK (0x70000000U) +#define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT (28U) +/*! CS_SEL - Select Rank + * 0b000..0 + * 0b001..1 + * 0b100..0 and 1 + */ +#define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT (31U) +/*! MD_EN - Mode Enable + * 0b0..Does not need to be issued + * 0b1..Valid data contained in the register ready to be issued as an MRW command + */ +#define DDRC_DDR_SDRAM_MD_CNTL_MD_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_INTERVAL - DDR SDRAM Interval Configuration */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK (0x3FFFU) +#define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT (0U) +/*! BSTOPRE - Precharge Interval */ +#define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT)) & DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK) + +#define DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK (0xFFFF0000U) +#define DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT (16U) +/*! REFINT - Refresh Interval */ +#define DDRC_DDR_SDRAM_INTERVAL_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT)) & DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK) +/*! @} */ + +/*! @name DDR_DATA_INIT - DDR SDRAM Data Initialization */ +/*! @{ */ + +#define DDRC_DDR_DATA_INIT_INIT_VALUE_MASK (0xFFFFFFFFU) +#define DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT (0U) +/*! INIT_VALUE - Initialization Value */ +#define DDRC_DDR_DATA_INIT_INIT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT)) & DDRC_DDR_DATA_INIT_INIT_VALUE_MASK) +/*! @} */ + +/*! @name TIMING_CFG_4 - DDR SDRAM Timing Configuration 4 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_4_DLL_LOCK_MASK (0x3U) +#define DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT (0U) +/*! DLL_LOCK - DDR SDRAM DLL Lock Time + * 0b10..1024 clocks + * 0b11..2048 clocks + */ +#define DDRC_TIMING_CFG_4_DLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT)) & DDRC_TIMING_CFG_4_DLL_LOCK_MASK) + +#define DDRC_TIMING_CFG_4_EXT_REFINT_MASK (0x10U) +#define DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT (4U) +/*! EXT_REFINT - Extended Refresh Interval + * 0b0..0 + * 0b1..65,536 + */ +#define DDRC_TIMING_CFG_4_EXT_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_REFINT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_WWT_MASK (0x300U) +#define DDRC_TIMING_CFG_4_EXT_WWT_SHIFT (8U) +/*! EXT_WWT - Extended Write-To-Write Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_WWT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_WWT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_RRT_MASK (0xC00U) +#define DDRC_TIMING_CFG_4_EXT_RRT_SHIFT (10U) +/*! EXT_RRT - Extended Read-To-Read Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_RRT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_RRT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_WRT_MASK (0x3000U) +#define DDRC_TIMING_CFG_4_EXT_WRT_SHIFT (12U) +/*! EXT_WRT - Extended Write-To-Read Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_WRT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_WRT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_RWT_MASK (0xC000U) +#define DDRC_TIMING_CFG_4_EXT_RWT_SHIFT (14U) +/*! EXT_RWT - Extended Read-To-Write Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_RWT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_RWT_MASK) + +#define DDRC_TIMING_CFG_4_WWT_MASK (0xF0000U) +#define DDRC_TIMING_CFG_4_WWT_SHIFT (16U) +/*! WWT - Write-To-Write Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_WWT_SHIFT)) & DDRC_TIMING_CFG_4_WWT_MASK) + +#define DDRC_TIMING_CFG_4_RRT_MASK (0xF00000U) +#define DDRC_TIMING_CFG_4_RRT_SHIFT (20U) +/*! RRT - Read-To-Read Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_RRT_SHIFT)) & DDRC_TIMING_CFG_4_RRT_MASK) + +#define DDRC_TIMING_CFG_4_WRT_MASK (0xF000000U) +#define DDRC_TIMING_CFG_4_WRT_SHIFT (24U) +/*! WRT - Write-To-Read Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_WRT_SHIFT)) & DDRC_TIMING_CFG_4_WRT_MASK) + +#define DDRC_TIMING_CFG_4_RWT_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_4_RWT_SHIFT (28U) +/*! RWT - Read-To-Write Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_RWT_SHIFT)) & DDRC_TIMING_CFG_4_RWT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_7 - DDR SDRAM Timing Configuration 7 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_7_CKSRX_MASK (0xF00000U) +#define DDRC_TIMING_CFG_7_CKSRX_SHIFT (20U) +/*! CKSRX - Clock After Self-Refresh Exit + * 0b0000, 0b1010..15 for LPDDR4, 19 for LPDDR5 + * 0b0001..6 for LPDDR4, 10 for LPDDR5 + * 0b0010..7 for LPDDR4, 11 for LPDDR5 + * 0b0011..8 for LPDDR4, 12 for LPDDR5 + * 0b0100..9 for LPDDR4, 13 for LPDDR5 + * 0b0101..10 for LPDDR4, 14 for LPDDR5 + * 0b0110..11 for LPDDR4, 15 for LPDDR5 + * 0b0111..12 for LPDDR4, 16 for LPDDR5 + * 0b1000..13 for LPDDR4, 17 for LPDDR5 + * 0b1001..14 for LPDDR4, 18 for LPDDR5 + * 0b1011..16 for LPDDR4, 20 for LPDDR5 + * 0b1100..17 for LPDDR4, 21 for LPDDR5 + * 0b1101..18 for LPDDR4, 22 for LPDDR5 + * 0b1110..19 for LPDDR4, 23 for LPDDR5 + * 0b1111..116 for LPDDR4, 31 for LPDDR5 + */ +#define DDRC_TIMING_CFG_7_CKSRX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKSRX_SHIFT)) & DDRC_TIMING_CFG_7_CKSRX_MASK) + +#define DDRC_TIMING_CFG_7_CKSRE_MASK (0xF000000U) +#define DDRC_TIMING_CFG_7_CKSRE_SHIFT (24U) +/*! CKSRE - Clock After Self-Refresh Entry + * 0b0000, 0b1010..15 for LPDDR4, 20 for LPDDR5 + * 0b0001..6 for LPDDR4, 11 for LPDDR5 + * 0b0010..7 for LPDDR4, 12 for LPDDR5 + * 0b0011..8 for LPDDR4, 13 for LPDDR5 + * 0b0100..9 for LPDDR4, 14 for LPDDR5 + * 0b0101..10 for LPDDR4, 15 for LPDDR5 + * 0b0110..11 for LPDDR4, 16 for LPDDR5 + * 0b0111..12 for LPDDR4, 17 for LPDDR5 + * 0b1000..13 for LPDDR4, 18 for LPDDR5 + * 0b1001..14 for LPDDR4, 19 for LPDDR5 + * 0b1011..16 for LPDDR4, 21 for LPDDR5 + * 0b1100..17 for LPDDR4, 22 for LPDDR5 + * 0b1101..18 for LPDDR4, 23 for LPDDR5 + * 0b1110..19 for LPDDR4, 24 for LPDDR5 + * 0b1111..32 for LPDDR4, 31 for LPDDR5 + */ +#define DDRC_TIMING_CFG_7_CKSRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKSRE_SHIFT)) & DDRC_TIMING_CFG_7_CKSRE_MASK) + +#define DDRC_TIMING_CFG_7_CKE_RST_MASK (0x30000000U) +#define DDRC_TIMING_CFG_7_CKE_RST_SHIFT (28U) +/*! CKE_RST - MCKE Reset Time + * 0b00..200 + * 0b01..256 + * 0b10..512 + * 0b11..4096 + */ +#define DDRC_TIMING_CFG_7_CKE_RST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKE_RST_SHIFT)) & DDRC_TIMING_CFG_7_CKE_RST_MASK) +/*! @} */ + +/*! @name DDR_ZQ_CNTL - DDR SDRAM ZQ Calibration Control */ +/*! @{ */ + +#define DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK (0xFU) +#define DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT (0U) +/*! ZQCS_INT - ZQCS Interval + * 0b0000..32 + * 0b0001..64 + * 0b0010..128 + * 0b0011..256 + * 0b0100..512 + * 0b0101..1024 + * 0b0110..2048 + * 0b0111..4096 + * 0b1000..8192 + * 0b1001..16384 + * 0b1010..32768 + * 0b1111..ZQCS calibration disabled + */ +#define DDRC_DDR_ZQ_CNTL_ZQCS_INT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQCS_MASK (0xF00U) +#define DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT (8U) +/*! ZQCS - ZQ Calibration Short Time + * 0b0000..1 + * 0b0001..2 + * 0b0010..4 + * 0b0011..8 + * 0b0100..16 + * 0b0101..32 + * 0b0110..64 + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + */ +#define DDRC_DDR_ZQ_CNTL_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQCS_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQOPER_MASK (0xF0000U) +#define DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT (16U) +/*! ZQOPER - ZQ Calibration Operation Time + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + * 0b1011..2048 + * 0b1100..4096 + * 0b1101..8192 + * 0b1110..2200 cycles when using LPDDR4 DDR_SDRAM; 2416 cycles when using LPDDR5 DDR_SDRAM + */ +#define DDRC_DDR_ZQ_CNTL_ZQOPER(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQOPER_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQINIT_MASK (0xF000000U) +#define DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT (24U) +/*! ZQINIT - ZQ Calibration Initialization Time + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + * 0b1011..2048 + * 0b1100..4096 + * 0b1101..8192 + * 0b1110..2200 cycles when using LPDDR4 DDR_SDRAM; 2416 cycles when using LPDDR5 DDR_SDRAM + */ +#define DDRC_DDR_ZQ_CNTL_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQINIT_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK (0x80000000U) +#define DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT (31U) +/*! ZQ_EN - ZQ Calibration Enable + * 0b0..Not used + * 0b1..Used + */ +#define DDRC_DDR_ZQ_CNTL_ZQ_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK) +/*! @} */ + +/*! @name DDR_SR_CNTR - DDR SDRAM Self-Refresh Counter */ +/*! @{ */ + +#define DDRC_DDR_SR_CNTR_SR_IT_MASK (0xF0000U) +#define DDRC_DDR_SR_CNTR_SR_IT_SHIFT (16U) +/*! SR_IT - Self-Refresh Idle Threshold */ +#define DDRC_DDR_SR_CNTR_SR_IT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SR_CNTR_SR_IT_SHIFT)) & DDRC_DDR_SR_CNTR_SR_IT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_8 - DDR SDRAM Timing Configuration 8 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK (0x3FU) +#define DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT (0U) +/*! PRE_ALL_REC - Precharge All-To-Activate Interval */ +#define DDRC_TIMING_CFG_8_PRE_ALL_REC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT)) & DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK) + +#define DDRC_TIMING_CFG_8_EXT_WRTORD_BG_MASK (0x80U) +#define DDRC_TIMING_CFG_8_EXT_WRTORD_BG_SHIFT (7U) +/*! EXT_WRTORD_BG - Extended Write-To-Read Same Bank Group + * 0b0..0 + * 0b1..16 + */ +#define DDRC_TIMING_CFG_8_EXT_WRTORD_BG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_EXT_WRTORD_BG_SHIFT)) & DDRC_TIMING_CFG_8_EXT_WRTORD_BG_MASK) + +#define DDRC_TIMING_CFG_8_WRTORD_BG_MASK (0xF00U) +#define DDRC_TIMING_CFG_8_WRTORD_BG_SHIFT (8U) +/*! WRTORD_BG - Write-To-Read Same Bank Group */ +#define DDRC_TIMING_CFG_8_WRTORD_BG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_WRTORD_BG_SHIFT)) & DDRC_TIMING_CFG_8_WRTORD_BG_MASK) + +#define DDRC_TIMING_CFG_8_ACTTOACT_BG_MASK (0xF000U) +#define DDRC_TIMING_CFG_8_ACTTOACT_BG_SHIFT (12U) +/*! ACTTOACT_BG - Activate-To-Activate Same Bank Group */ +#define DDRC_TIMING_CFG_8_ACTTOACT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_ACTTOACT_BG_SHIFT)) & DDRC_TIMING_CFG_8_ACTTOACT_BG_MASK) + +#define DDRC_TIMING_CFG_8_WWT_BG_MASK (0xF0000U) +#define DDRC_TIMING_CFG_8_WWT_BG_SHIFT (16U) +/*! WWT_BG - Write-To-Write Turnaround For Same CS And Bank Group */ +#define DDRC_TIMING_CFG_8_WWT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_WWT_BG_SHIFT)) & DDRC_TIMING_CFG_8_WWT_BG_MASK) + +#define DDRC_TIMING_CFG_8_RRT_BG_MASK (0xF00000U) +#define DDRC_TIMING_CFG_8_RRT_BG_SHIFT (20U) +/*! RRT_BG - Read-To-Read Turnaround For Same Rank And Bank Group */ +#define DDRC_TIMING_CFG_8_RRT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_RRT_BG_SHIFT)) & DDRC_TIMING_CFG_8_RRT_BG_MASK) + +#define DDRC_TIMING_CFG_8_WRT_BG_MASK (0xF000000U) +#define DDRC_TIMING_CFG_8_WRT_BG_SHIFT (24U) +/*! WRT_BG - Write-To-Read Turnaround For Same Rank And Bank Group */ +#define DDRC_TIMING_CFG_8_WRT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_WRT_BG_SHIFT)) & DDRC_TIMING_CFG_8_WRT_BG_MASK) + +#define DDRC_TIMING_CFG_8_RWT_BG_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_8_RWT_BG_SHIFT (28U) +/*! RWT_BG - Read-To-Write Turnaround For Same Rank And Bank Group */ +#define DDRC_TIMING_CFG_8_RWT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_RWT_BG_SHIFT)) & DDRC_TIMING_CFG_8_RWT_BG_MASK) +/*! @} */ + +/*! @name TIMING_CFG_9 - DDR SDRAM timing configuration 9 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_9_REFTOREF_PB_MASK (0x3FFU) +#define DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT (0U) +/*! REFTOREF_PB - Refresh-to-refresh interval for per-bank refresh. + * 0b0000000000..disable PB refresh + * 0b0000000001..9 clocks + * 0b0000000010..10 clocks + * 0b1011111110..774 clocks + * 0b1011111111..775 clocks + */ +#define DDRC_TIMING_CFG_9_REFTOREF_PB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT)) & DDRC_TIMING_CFG_9_REFTOREF_PB_MASK) + +#define DDRC_TIMING_CFG_9_REFREC_PB_MASK (0x3FF0000U) +#define DDRC_TIMING_CFG_9_REFREC_PB_SHIFT (16U) +/*! REFREC_PB - Refresh Recovery Per-Bank Refresh + * 0b0000000000..8 clocks + * 0b0000000001..9 clocks + * 0b0000000010..10 clocks + * 0b1011111110..774 clocks + * 0b1011111111..775 clocks + */ +#define DDRC_TIMING_CFG_9_REFREC_PB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_9_REFREC_PB_SHIFT)) & DDRC_TIMING_CFG_9_REFREC_PB_MASK) +/*! @} */ + +/*! @name TIMING_CFG_10 - DDR SDRAM Timing Configuration 10 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_10_T_STAB_MASK (0x7FFFU) +#define DDRC_TIMING_CFG_10_T_STAB_SHIFT (0U) +/*! T_STAB - Stabilization Wait Time */ +#define DDRC_TIMING_CFG_10_T_STAB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_10_T_STAB_SHIFT)) & DDRC_TIMING_CFG_10_T_STAB_MASK) + +#define DDRC_TIMING_CFG_10_PBRTOACT_MASK (0xF800000U) +#define DDRC_TIMING_CFG_10_PBRTOACT_SHIFT (23U) +/*! PBRTOACT - Per-Bank Refresh to Activate */ +#define DDRC_TIMING_CFG_10_PBRTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_10_PBRTOACT_SHIFT)) & DDRC_TIMING_CFG_10_PBRTOACT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_11 - DDR SDRAM Timing Configuration 11 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_11_MWWT_MASK (0xFU) +#define DDRC_TIMING_CFG_11_MWWT_SHIFT (0U) +/*! MWWT - Masked Write-To-Write Turnaround (tCCDMW) */ +#define DDRC_TIMING_CFG_11_MWWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_MWWT_SHIFT)) & DDRC_TIMING_CFG_11_MWWT_MASK) + +#define DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK (0xF00U) +#define DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT (8U) +/*! PRE_TO_PRE - Precharge-To-Precharge Time + * 0b0000, 0b0100..4 + * 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + * 0b1001..9 + * 0b1010..10 + * 0b1011..11 + * 0b1100..12 + * 0b1101..13 + * 0b1110..14 + * 0b1111..15 + */ +#define DDRC_TIMING_CFG_11_PRE_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT)) & DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK) + +#define DDRC_TIMING_CFG_11_WCKEN_FS_MASK (0xF0000U) +#define DDRC_TIMING_CFG_11_WCKEN_FS_SHIFT (16U) +/*! WCKEN_FS - WCKEN FS Time + * 0b0000, 0b0010..2 + * 0b0001..1 + * 0b0011..3 + * 0b0100..4 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + * 0b1001..9 + * 0b1010..10 + * 0b1011..11 + * 0b1100..12 + * 0b1101..13 + * 0b1110..14 + * 0b1111..15 + */ +#define DDRC_TIMING_CFG_11_WCKEN_FS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_WCKEN_FS_SHIFT)) & DDRC_TIMING_CFG_11_WCKEN_FS_MASK) + +#define DDRC_TIMING_CFG_11_WCK_STOP_MASK (0xF00000U) +#define DDRC_TIMING_CFG_11_WCK_STOP_SHIFT (20U) +/*! WCK_STOP - WCK Stop Time + * 0b0000, 0b0111..7 + * 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0100..4 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + * 0b1001..9 + * 0b1010..10 + */ +#define DDRC_TIMING_CFG_11_WCK_STOP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_WCK_STOP_SHIFT)) & DDRC_TIMING_CFG_11_WCK_STOP_MASK) + +#define DDRC_TIMING_CFG_11_WS_OFF_MASK (0x7000000U) +#define DDRC_TIMING_CFG_11_WS_OFF_SHIFT (24U) +/*! WS_OFF - WS_OFF Wait Time + * 0b000..0 extra cycles added + * 0b001..1 + * 0b010..2 + * 0b011..3 + * 0b100..4 + */ +#define DDRC_TIMING_CFG_11_WS_OFF(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_WS_OFF_SHIFT)) & DDRC_TIMING_CFG_11_WS_OFF_MASK) + +#define DDRC_TIMING_CFG_11_WCKPRE_STATIC_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_11_WCKPRE_STATIC_SHIFT (28U) +/*! WCKPRE_STATIC - WCKPRE Static Time + * 0b0000, 0b0100..4 + * 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + * 0b1001..9 + * 0b1010..10 + * 0b1011..11 + * 0b1100..12 + * 0b1101..13 + * 0b1110..14 + * 0b1111..15 + */ +#define DDRC_TIMING_CFG_11_WCKPRE_STATIC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_WCKPRE_STATIC_SHIFT)) & DDRC_TIMING_CFG_11_WCKPRE_STATIC_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_3 - DDR SDRAM Control Configuration 3 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_3_DIS_MR13_MASK (0x1U) +#define DDRC_DDR_SDRAM_CFG_3_DIS_MR13_SHIFT (0U) +/*! DIS_MR13 - Disable MR13 Write for Self Refresh + * 0b0..Issues an MR13 (or MR16) command + * 0b1..Does not issue an MR13 (or MR16) command + */ +#define DDRC_DDR_SDRAM_CFG_3_DIS_MR13(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DIS_MR13_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DIS_MR13_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK (0x2U) +#define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT (1U) +/*! SR_FAST_WK_EN - Self Refresh Fast Wakeup Enable + * 0b0..Slow + * 0b1..Fast + */ +#define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_SR_PD_EN_MASK (0x10U) +#define DDRC_DDR_SDRAM_CFG_3_SR_PD_EN_SHIFT (4U) +/*! SR_PD_EN - Self Refresh Powerdown Enable + * 0b0..Issues a powerdown after self refresh entry. + * 0b1..Does not issue a powerdown after self refresh entry. + */ +#define DDRC_DDR_SDRAM_CFG_3_SR_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_SR_PD_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_SR_PD_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DIS_MR28_MASK (0x20U) +#define DDRC_DDR_SDRAM_CFG_3_DIS_MR28_SHIFT (5U) +/*! DIS_MR28 - Disable MR28 Write for Self Refresh + * 0b0..Issues an MR28 command + * 0b1..Does not issue an MR28 command + */ +#define DDRC_DDR_SDRAM_CFG_3_DIS_MR28(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DIS_MR28_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DIS_MR28_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK (0x80U) +#define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT (7U) +/*! DYN_REF_RATE_EN - Dynamic Refresh Rate Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK (0x800U) +#define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT (11U) +/*! DRAIN_FOR_SR - Drain Queues For Self-Refresh + * 0b0..Do not drain + * 0b1..Drain + */ +#define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK (0x7000U) +#define DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT (12U) +/*! DM_CFG - Data Mask Configuration + * 0b000..Normal data masks based on the settings defined in DDR_SDRAM_CFG[SDRAM_TYPE] + * 0b010..DBI + * 0b011..Neither data masks nor DBI + * 0b100..DBI with data masks + */ +#define DDRC_DDR_SDRAM_CFG_3_DM_CFG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN_MASK (0x10000U) +#define DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN_SHIFT (16U) +/*! CHB_SWP_EN - Channel B Swap Enable + * 0b0..Channel B is not byte swapped + * 0b1..Channel B is byte swapped + */ +#define DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN_MASK (0x20000U) +#define DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN_SHIFT (17U) +/*! CHA_SWP_EN - Channel A Swap Enable + * 0b0..Channel A is not byte swapped + * 0b1..Channel A is byte swapped + */ +#define DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_HP_EN_MASK (0x80000U) +#define DDRC_DDR_SDRAM_CFG_3_HP_EN_SHIFT (19U) +/*! HP_EN - High Performance Enable + * 0b0..High performance not enabled + * 0b1..High performance enabled + */ +#define DDRC_DDR_SDRAM_CFG_3_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_HP_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_HP_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT_MASK (0xF000000U) +#define DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT_SHIFT (24U) +/*! ECC_SCRUB_INT - ECC Scrubbing Interval */ +#define DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN_MASK (0x40000000U) +#define DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN_SHIFT (30U) +/*! ECC_FIX_EN - ECC Fixing Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT (31U) +/*! DDRC_RST - DDRC Reset + * 0b0..Operating normally + * 0b1..Undergoing reset + */ +#define DDRC_DDR_SDRAM_CFG_3_DDRC_RST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_5 - DDR SDRAM Control Configuration 5 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN_MASK (0x1U) +#define DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN_SHIFT (0U) +/*! LNK_ECC_EN - Link ECC enable. + * 0b0..Link ECC is disabled. + * 0b1..Link ECC is enabled. + */ +#define DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_5_DSLP_EN_MASK (0x2U) +#define DDRC_DDR_SDRAM_CFG_5_DSLP_EN_SHIFT (1U) +/*! DSLP_EN - Deep sleep enable. + * 0b0..Self-refresh requests do not cause the controller to enter Deep Sleep mode. + * 0b1..Self-refresh requests cause the controller to enter Deep Sleep mode. + */ +#define DDRC_DDR_SDRAM_CFG_5_DSLP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_5_DSLP_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_5_DSLP_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_5_MED_PRIO_MASK (0xF000000U) +#define DDRC_DDR_SDRAM_CFG_5_MED_PRIO_SHIFT (24U) +/*! MED_PRIO - Medium Priority Level. */ +#define DDRC_DDR_SDRAM_CFG_5_MED_PRIO(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_5_MED_PRIO_SHIFT)) & DDRC_DDR_SDRAM_CFG_5_MED_PRIO_MASK) + +#define DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO_MASK (0xF0000000U) +#define DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO_SHIFT (28U) +/*! HIGH_PRIO - High Priority Level. */ +#define DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO_SHIFT)) & DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_6 - DDR SDRAM Control Configuration 6 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_6_MR28_VAL_MASK (0x3FU) +#define DDRC_DDR_SDRAM_CFG_6_MR28_VAL_SHIFT (0U) +/*! MR28_VAL - MR28 Value. */ +#define DDRC_DDR_SDRAM_CFG_6_MR28_VAL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_6_MR28_VAL_SHIFT)) & DDRC_DDR_SDRAM_CFG_6_MR28_VAL_MASK) + +#define DDRC_DDR_SDRAM_CFG_6_RRO_MASK (0x40U) +#define DDRC_DDR_SDRAM_CFG_6_RRO_SHIFT (6U) +/*! RRO - Refresh rate option. */ +#define DDRC_DDR_SDRAM_CFG_6_RRO(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_6_RRO_SHIFT)) & DDRC_DDR_SDRAM_CFG_6_RRO_MASK) + +#define DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN_MASK (0x1000U) +#define DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN_SHIFT (12U) +/*! ADDR_SZL_EN - Address swizzle enable. + * 0b0..Do not enable address swizzling. + * 0b1..Will move bit 6 of the incoming address of the DDRC to the bit dedicated to BG1 (assuming 10-bit column + * address). Then, all bits from BG1 to bit 7 will be shifted right 1 bit. This will force 64-byte sequential + * transactions to use different bank groups. Note that when this bit is set, any addresses captured in the + * error capture registers will represent the address after this swizzle occurs. + */ +#define DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN_MASK (0x2000U) +#define DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN_SHIFT (13U) +/*! RD_SPLT_EN - Read split enable. + * 0b0..Read split feature is disabled. + * 0b1..64-byte reads (or reads that cross a 32-byte boundary) will be split into 2 transactions within the scheduling. + */ +#define DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_MD_CNTL2 - DDR SDRAM mode control 2 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_MD_CNTL2_MPRR_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_MD_CNTL2_MPRR_SHIFT (31U) +/*! MPRR - Multi-purpose register read. + * 0b0..A multi-purpose register read will not be issued. + * 0b1..A multi-purpose register read will be issued after DDR_SDRAM_MD_CNTL[MD_EN] is set. + */ +#define DDRC_DDR_SDRAM_MD_CNTL2_MPRR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL2_MPRR_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL2_MPRR_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_MPR4 - DDR SDRAM multi-purpose register 4 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_MPR4_MPR_READ_MASK (0xFFFFFFFFU) +#define DDRC_DDR_SDRAM_MPR4_MPR_READ_SHIFT (0U) +/*! MPR_READ - MPR Read Value. */ +#define DDRC_DDR_SDRAM_MPR4_MPR_READ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MPR4_MPR_READ_SHIFT)) & DDRC_DDR_SDRAM_MPR4_MPR_READ_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_MPR5 - DDR SDRAM multi-purpose register 5 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_MPR5_MPR_VLD_MASK (0x1U) +#define DDRC_DDR_SDRAM_MPR5_MPR_VLD_SHIFT (0U) +/*! MPR_VLD - MPR Valid. + * 0b0..The multi-purpose register read data registers are not valid. + * 0b1..The multi-purpose register read data registers are valid. + */ +#define DDRC_DDR_SDRAM_MPR5_MPR_VLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MPR5_MPR_VLD_SHIFT)) & DDRC_DDR_SDRAM_MPR5_MPR_VLD_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_REF_RATE - DDR Refresh Rate */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK (0xFFU) +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT (0U) +/*! REF_RATE_CS1 - Refresh Rate Rank 1 */ +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK) + +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK (0xFF00U) +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT (8U) +/*! REF_RATE_CS0 - Refresh Rate Rank 0 */ +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK) + +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB_MASK (0xFF0000U) +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB_SHIFT (16U) +/*! REF_RATE_CS1_CHB - Refresh Rate Rank 1 */ +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB_MASK) + +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB_MASK (0xFF000000U) +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB_SHIFT (24U) +/*! REF_RATE_CS0_CHB - Refresh Rate Rank 0 */ +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB_MASK) +/*! @} */ + +/*! @name TIMING_CFG_12 - DDR SDRAM Timing Configuration 12 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_12_CASLAT_HS_MASK (0x3FU) +#define DDRC_TIMING_CFG_12_CASLAT_HS_SHIFT (0U) +/*! CASLAT_HS - CAS Latency For Half Speed */ +#define DDRC_TIMING_CFG_12_CASLAT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_CASLAT_HS_SHIFT)) & DDRC_TIMING_CFG_12_CASLAT_HS_MASK) + +#define DDRC_TIMING_CFG_12_ACTTORW_HS_MASK (0x3F00U) +#define DDRC_TIMING_CFG_12_ACTTORW_HS_SHIFT (8U) +/*! ACTTORW_HS - Activate To Read Or Write For Half Speed + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_12_ACTTORW_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_ACTTORW_HS_SHIFT)) & DDRC_TIMING_CFG_12_ACTTORW_HS_MASK) + +#define DDRC_TIMING_CFG_12_ACTTOPRE_HS_MASK (0x7F0000U) +#define DDRC_TIMING_CFG_12_ACTTOPRE_HS_SHIFT (16U) +/*! ACTTOPRE_HS - Activate-To-Precharge Time For Half Speed */ +#define DDRC_TIMING_CFG_12_ACTTOPRE_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_ACTTOPRE_HS_SHIFT)) & DDRC_TIMING_CFG_12_ACTTOPRE_HS_MASK) + +#define DDRC_TIMING_CFG_12_PRETOACT_HS_MASK (0x3F000000U) +#define DDRC_TIMING_CFG_12_PRETOACT_HS_SHIFT (24U) +/*! PRETOACT_HS - Precharge-To-Activate Time For Half Speed + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_12_PRETOACT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_PRETOACT_HS_SHIFT)) & DDRC_TIMING_CFG_12_PRETOACT_HS_MASK) +/*! @} */ + +/*! @name TIMING_CFG_13 - DDR SDRAM Timing Configuration 13 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_13_ACTTOACT_HS_MASK (0x1FU) +#define DDRC_TIMING_CFG_13_ACTTOACT_HS_SHIFT (0U) +/*! ACTTOACT_HS - Activate-To-Activate Interval For Half Speed + * 0b00000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_13_ACTTOACT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_13_ACTTOACT_HS_SHIFT)) & DDRC_TIMING_CFG_13_ACTTOACT_HS_MASK) + +#define DDRC_TIMING_CFG_13_WRREC_HS_MASK (0x3F00U) +#define DDRC_TIMING_CFG_13_WRREC_HS_SHIFT (8U) +/*! WRREC_HS - Write Recovery For Half Speed + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_13_WRREC_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_13_WRREC_HS_SHIFT)) & DDRC_TIMING_CFG_13_WRREC_HS_MASK) + +#define DDRC_TIMING_CFG_13_REFREC_HS_MASK (0x3FF0000U) +#define DDRC_TIMING_CFG_13_REFREC_HS_SHIFT (16U) +/*! REFREC_HS - Refresh Recovery For Half Speed */ +#define DDRC_TIMING_CFG_13_REFREC_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_13_REFREC_HS_SHIFT)) & DDRC_TIMING_CFG_13_REFREC_HS_MASK) +/*! @} */ + +/*! @name TIMING_CFG_14 - DDR SDRAM Timing Configuration 14 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_14_REFINT_HS_MASK (0x1FFFFU) +#define DDRC_TIMING_CFG_14_REFINT_HS_SHIFT (0U) +/*! REFINT_HS - Refresh Interval For Half Speed */ +#define DDRC_TIMING_CFG_14_REFINT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_14_REFINT_HS_SHIFT)) & DDRC_TIMING_CFG_14_REFINT_HS_MASK) + +#define DDRC_TIMING_CFG_14_RD_TO_PRE_HS_MASK (0x7C0000U) +#define DDRC_TIMING_CFG_14_RD_TO_PRE_HS_SHIFT (18U) +/*! RD_TO_PRE_HS - Read-To-Precharge Time For Half Speed + * 0b00000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_14_RD_TO_PRE_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_14_RD_TO_PRE_HS_SHIFT)) & DDRC_TIMING_CFG_14_RD_TO_PRE_HS_MASK) + +#define DDRC_TIMING_CFG_14_WRLAT_HS_MASK (0x3F000000U) +#define DDRC_TIMING_CFG_14_WRLAT_HS_SHIFT (24U) +/*! WRLAT_HS - Write Latency For Half Speed */ +#define DDRC_TIMING_CFG_14_WRLAT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_14_WRLAT_HS_SHIFT)) & DDRC_TIMING_CFG_14_WRLAT_HS_MASK) +/*! @} */ + +/*! @name TIMING_CFG_15 - DDR SDRAM Timing Configuration 15 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_15_REFTOREF_PB_HS_MASK (0x3FFU) +#define DDRC_TIMING_CFG_15_REFTOREF_PB_HS_SHIFT (0U) +/*! REFTOREF_PB_HS - Refresh-to-refresh interval for per-bank refresh. + * 0b0000000000..8 clocks + * 0b0000000001..9 clocks + * 0b0000000010..10 clocks + * 0b1011111110..774 clocks + * 0b1011111111..775 clocks + */ +#define DDRC_TIMING_CFG_15_REFTOREF_PB_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_15_REFTOREF_PB_HS_SHIFT)) & DDRC_TIMING_CFG_15_REFTOREF_PB_HS_MASK) + +#define DDRC_TIMING_CFG_15_REFREC_PB_HS_MASK (0x3FF0000U) +#define DDRC_TIMING_CFG_15_REFREC_PB_HS_SHIFT (16U) +/*! REFREC_PB_HS - Refresh Recovery During Per-Bank Refresh. + * 0b0000000000..8 clocks + * 0b0000000001..9 clocks + * 0b0000000010..10 clocks + * 0b1011111110..774 clocks + * 0b1011111111..775 clocks + */ +#define DDRC_TIMING_CFG_15_REFREC_PB_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_15_REFREC_PB_HS_SHIFT)) & DDRC_TIMING_CFG_15_REFREC_PB_HS_MASK) +/*! @} */ + +/*! @name TIMING_CFG_16 - DDR SDRAM Timing Configuration 16 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_16_T_STAB_HS_MASK (0x7FFFU) +#define DDRC_TIMING_CFG_16_T_STAB_HS_SHIFT (0U) +/*! T_STAB_HS - Stabilization Wait Time at Half Speed */ +#define DDRC_TIMING_CFG_16_T_STAB_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_16_T_STAB_HS_SHIFT)) & DDRC_TIMING_CFG_16_T_STAB_HS_MASK) + +#define DDRC_TIMING_CFG_16_LNK_ECC_EN_HS_MASK (0x8000U) +#define DDRC_TIMING_CFG_16_LNK_ECC_EN_HS_SHIFT (15U) +/*! LNK_ECC_EN_HS - Link ECC Enable at Half Speed. + * 0b0..Link ECC is disabled. + * 0b1..Link ECC is enabled. + */ +#define DDRC_TIMING_CFG_16_LNK_ECC_EN_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_16_LNK_ECC_EN_HS_SHIFT)) & DDRC_TIMING_CFG_16_LNK_ECC_EN_HS_MASK) + +#define DDRC_TIMING_CFG_16_WCK_CNFGS_HS_MASK (0xFFFF0000U) +#define DDRC_TIMING_CFG_16_WCK_CNFGS_HS_SHIFT (16U) +/*! WCK_CNFGS_HS - WCK Configuration Settings at Half Speed */ +#define DDRC_TIMING_CFG_16_WCK_CNFGS_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_16_WCK_CNFGS_HS_SHIFT)) & DDRC_TIMING_CFG_16_WCK_CNFGS_HS_MASK) +/*! @} */ + +/*! @name TIMING_CFG_17 - DDR SDRAM Timing Configuration 17 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_17_ZQCS_INT_HS_MASK (0xFU) +#define DDRC_TIMING_CFG_17_ZQCS_INT_HS_SHIFT (0U) +/*! ZQCS_INT_HS - ZQCS Interval + * 0b0000..32 + * 0b0001..64 + * 0b0010..128 + * 0b0011..256 + * 0b0100..512 + * 0b0101..1024 + * 0b0110..2048 + * 0b0111..4096 + * 0b1000..8192 + * 0b1001..16384 + * 0b1010..32768 + * 0b1111..ZQCS calibration disabled + */ +#define DDRC_TIMING_CFG_17_ZQCS_INT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_17_ZQCS_INT_HS_SHIFT)) & DDRC_TIMING_CFG_17_ZQCS_INT_HS_MASK) + +#define DDRC_TIMING_CFG_17_ZQCS_HS_MASK (0xF00U) +#define DDRC_TIMING_CFG_17_ZQCS_HS_SHIFT (8U) +/*! ZQCS_HS - ZQ Calibration Short Time + * 0b0000..1 + * 0b0001..2 + * 0b0010..4 + * 0b0011..8 + * 0b0100..16 + * 0b0101..32 + * 0b0110..64 + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + */ +#define DDRC_TIMING_CFG_17_ZQCS_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_17_ZQCS_HS_SHIFT)) & DDRC_TIMING_CFG_17_ZQCS_HS_MASK) + +#define DDRC_TIMING_CFG_17_ZQOPER_HS_MASK (0xF0000U) +#define DDRC_TIMING_CFG_17_ZQOPER_HS_SHIFT (16U) +/*! ZQOPER_HS - ZQ Calibration Operation Time + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + * 0b1011..2048 + */ +#define DDRC_TIMING_CFG_17_ZQOPER_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_17_ZQOPER_HS_SHIFT)) & DDRC_TIMING_CFG_17_ZQOPER_HS_MASK) + +#define DDRC_TIMING_CFG_17_ZQINIT_HS_MASK (0xF000000U) +#define DDRC_TIMING_CFG_17_ZQINIT_HS_SHIFT (24U) +/*! ZQINIT_HS - ZQ Calibration Initialization Time + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + * 0b1011..2048 + */ +#define DDRC_TIMING_CFG_17_ZQINIT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_17_ZQINIT_HS_SHIFT)) & DDRC_TIMING_CFG_17_ZQINIT_HS_MASK) +/*! @} */ + +/*! @name TX_CFG_1 - Transaction Configuration Register 1 */ +/*! @{ */ + +#define DDRC_TX_CFG_1_WWATER_MASK (0xFU) +#define DDRC_TX_CFG_1_WWATER_SHIFT (0U) +/*! WWATER - Write Watermark. */ +#define DDRC_TX_CFG_1_WWATER(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_1_WWATER_SHIFT)) & DDRC_TX_CFG_1_WWATER_MASK) + +#define DDRC_TX_CFG_1_TS_DEPTH_MASK (0xF80U) +#define DDRC_TX_CFG_1_TS_DEPTH_SHIFT (7U) +/*! TS_DEPTH - Transaction Scheduler Depth */ +#define DDRC_TX_CFG_1_TS_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_1_TS_DEPTH_SHIFT)) & DDRC_TX_CFG_1_TS_DEPTH_MASK) + +#define DDRC_TX_CFG_1_HPR_MASK (0x200000U) +#define DDRC_TX_CFG_1_HPR_SHIFT (21U) +/*! HPR - High Priority Read. + * 0b0..New high priority read does not truncate a write run. + * 0b1..New high priority read can truncate a write run. + */ +#define DDRC_TX_CFG_1_HPR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_1_HPR_SHIFT)) & DDRC_TX_CFG_1_HPR_MASK) +/*! @} */ + +/*! @name TX_CFG_2 - Transaction Configuration Register 2 */ +/*! @{ */ + +#define DDRC_TX_CFG_2_WR_BONUS_MASK (0x1FU) +#define DDRC_TX_CFG_2_WR_BONUS_SHIFT (0U) +/*! WR_BONUS - Write Bandwidth Bonus Count. */ +#define DDRC_TX_CFG_2_WR_BONUS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_2_WR_BONUS_SHIFT)) & DDRC_TX_CFG_2_WR_BONUS_MASK) + +#define DDRC_TX_CFG_2_WR_CNT_MASK (0x1F00U) +#define DDRC_TX_CFG_2_WR_CNT_SHIFT (8U) +/*! WR_CNT - Write Bandwidth Count. */ +#define DDRC_TX_CFG_2_WR_CNT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_2_WR_CNT_SHIFT)) & DDRC_TX_CFG_2_WR_CNT_MASK) + +#define DDRC_TX_CFG_2_RD_BONUS_MASK (0x1F0000U) +#define DDRC_TX_CFG_2_RD_BONUS_SHIFT (16U) +/*! RD_BONUS - Read Bandwidth Bonus Count. */ +#define DDRC_TX_CFG_2_RD_BONUS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_2_RD_BONUS_SHIFT)) & DDRC_TX_CFG_2_RD_BONUS_MASK) + +#define DDRC_TX_CFG_2_RD_CNT_MASK (0x1F000000U) +#define DDRC_TX_CFG_2_RD_CNT_SHIFT (24U) +/*! RD_CNT - Read Bandwidth Count. */ +#define DDRC_TX_CFG_2_RD_CNT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_2_RD_CNT_SHIFT)) & DDRC_TX_CFG_2_RD_CNT_MASK) + +#define DDRC_TX_CFG_2_RD_EPA_DIS_MASK (0x40000000U) +#define DDRC_TX_CFG_2_RD_EPA_DIS_SHIFT (30U) +/*! RD_EPA_DIS - Read Precharge to Activate Disable. */ +#define DDRC_TX_CFG_2_RD_EPA_DIS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_2_RD_EPA_DIS_SHIFT)) & DDRC_TX_CFG_2_RD_EPA_DIS_MASK) + +#define DDRC_TX_CFG_2_WR_EPA_DIS_MASK (0x80000000U) +#define DDRC_TX_CFG_2_WR_EPA_DIS_SHIFT (31U) +/*! WR_EPA_DIS - Write Precharge to Activate Disable. */ +#define DDRC_TX_CFG_2_WR_EPA_DIS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_2_WR_EPA_DIS_SHIFT)) & DDRC_TX_CFG_2_WR_EPA_DIS_MASK) +/*! @} */ + +/*! @name DDRDSR_2 - DDR SDRAM Debug Status 2 */ +/*! @{ */ + +#define DDRC_DDRDSR_2_RPD_END_MASK (0x1U) +#define DDRC_DDRDSR_2_RPD_END_SHIFT (0U) +/*! RPD_END - Rapid Clear Of Memory End + * 0b0..Not complete + * 0b1..Complete + */ +#define DDRC_DDRDSR_2_RPD_END(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_RPD_END_SHIFT)) & DDRC_DDRDSR_2_RPD_END_MASK) + +#define DDRC_DDRDSR_2_RPD_ST_MASK (0x2U) +#define DDRC_DDRDSR_2_RPD_ST_SHIFT (1U) +/*! RPD_ST - Rapid Clear Of Memory Start + * 0b0..Not started + * 0b1..Started + */ +#define DDRC_DDRDSR_2_RPD_ST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_RPD_ST_SHIFT)) & DDRC_DDRDSR_2_RPD_ST_MASK) + +#define DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK (0x4U) +#define DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT (2U) +/*! PHY_INIT_CMPLT - DDR PHY Initialization Complete + * 0b0..Not complete + * 0b1..Complete + */ +#define DDRC_DDRDSR_2_PHY_INIT_CMPLT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT)) & DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK) + +#define DDRC_DDRDSR_2_NML_MASK (0x40000000U) +#define DDRC_DDRDSR_2_NML_SHIFT (30U) +/*! NML - No Modified Lines + * 0b0..Exist + * 0b1..Do not exist + */ +#define DDRC_DDRDSR_2_NML(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_NML_SHIFT)) & DDRC_DDRDSR_2_NML_MASK) + +#define DDRC_DDRDSR_2_IDLE_MASK (0x80000000U) +#define DDRC_DDRDSR_2_IDLE_SHIFT (31U) +/*! IDLE - Memory controller idle (read only). + * 0b0..Memory controller is busy. + * 0b1..Memory controller is idle. + */ +#define DDRC_DDRDSR_2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_IDLE_SHIFT)) & DDRC_DDRDSR_2_IDLE_MASK) +/*! @} */ + +/*! @name DDR_IP_REV1 - DDRC Revision 1 */ +/*! @{ */ + +#define DDRC_DDR_IP_REV1_IP_MN_MASK (0xFFU) +#define DDRC_DDR_IP_REV1_IP_MN_SHIFT (0U) +/*! IP_MN - Minor Revision */ +#define DDRC_DDR_IP_REV1_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_MN_SHIFT)) & DDRC_DDR_IP_REV1_IP_MN_MASK) + +#define DDRC_DDR_IP_REV1_IP_MJ_MASK (0xFF00U) +#define DDRC_DDR_IP_REV1_IP_MJ_SHIFT (8U) +/*! IP_MJ - Major Revision */ +#define DDRC_DDR_IP_REV1_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_MJ_SHIFT)) & DDRC_DDR_IP_REV1_IP_MJ_MASK) + +#define DDRC_DDR_IP_REV1_IP_ID_MASK (0xFFFF0000U) +#define DDRC_DDR_IP_REV1_IP_ID_SHIFT (16U) +/*! IP_ID - IP Block ID */ +#define DDRC_DDR_IP_REV1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_ID_SHIFT)) & DDRC_DDR_IP_REV1_IP_ID_MASK) +/*! @} */ + +/*! @name DDR_MTCR - DDR SDRAM Memory Test Control */ +/*! @{ */ + +#define DDRC_DDR_MTCR_MT_STAT_MASK (0x1U) +#define DDRC_DDR_MTCR_MT_STAT_SHIFT (0U) +/*! MT_STAT - Memory Test Status + * 0b0..No fail detected + * 0b1..Data miscompare detected + */ +#define DDRC_DDR_MTCR_MT_STAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_STAT_SHIFT)) & DDRC_DDR_MTCR_MT_STAT_MASK) + +#define DDRC_DDR_MTCR_MT_ADDR_EN_MASK (0x200U) +#define DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT (9U) +/*! MT_ADDR_EN - Memory Test Address Range Enable + * 0b0..Memory range that the CSn_BNDS registers define + * 0b1..Memory range that the DDR_MT_ST_EXT_ADDR, DDR_MT_ST_ADDR, DDR_MT_END_EXT_ADDR, and DDR_MT_END_ADDR registers define + */ +#define DDRC_DDR_MTCR_MT_ADDR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT)) & DDRC_DDR_MTCR_MT_ADDR_EN_MASK) + +#define DDRC_DDR_MTCR_MT_TRNARND_MASK (0xF0000U) +#define DDRC_DDR_MTCR_MT_TRNARND_SHIFT (16U) +/*! MT_TRNARND - Memory Test Turnaround + * 0b0000..Entire memory is written to before read transactions are issued. + * 0b0001..Total write and read streams are one transaction each. + * 0b0010..Total write and read streams are two transactions each. + * 0b0011..Total write and read streams are four transactions each. + */ +#define DDRC_DDR_MTCR_MT_TRNARND(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_TRNARND_SHIFT)) & DDRC_DDR_MTCR_MT_TRNARND_MASK) + +#define DDRC_DDR_MTCR_MT_TYP_MASK (0x3000000U) +#define DDRC_DDR_MTCR_MT_TYP_SHIFT (24U) +/*! MT_TYP - Memory Test Type + * 0b00..Both writes and reads + * 0b01..Only writes + * 0b10..Only reads + * 0b11..Reserved + */ +#define DDRC_DDR_MTCR_MT_TYP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_TYP_SHIFT)) & DDRC_DDR_MTCR_MT_TYP_MASK) + +#define DDRC_DDR_MTCR_MT_EN_MASK (0x80000000U) +#define DDRC_DDR_MTCR_MT_EN_SHIFT (31U) +/*! MT_EN - Memory Test Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_MTCR_MT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_EN_SHIFT)) & DDRC_DDR_MTCR_MT_EN_MASK) +/*! @} */ + +/*! @name DDR_MTP - DDR SDRAM Memory Test Pattern n */ +/*! @{ */ + +#define DDRC_DDR_MTP_DDR_PATT_MASK (0xFFFFFFFFU) +#define DDRC_DDR_MTP_DDR_PATT_SHIFT (0U) +/*! DDR_PATT - DDR SDRAM Pattern */ +#define DDRC_DDR_MTP_DDR_PATT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTP_DDR_PATT_SHIFT)) & DDRC_DDR_MTP_DDR_PATT_MASK) +/*! @} */ + +/*! @name DDR_MT_ST_EXT_ADDR - DDR SDRAM Memory Test Start Extended Address */ +/*! @{ */ + +#define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK (0xFFU) +#define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT (0U) +/*! MT_ST_EXT_ADDR - Memory Test Start Extended Address */ +#define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT)) & DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK) +/*! @} */ + +/*! @name DDR_MT_ST_ADDR - DDR SDRAM Memory Test Start Address */ +/*! @{ */ + +#define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK (0xFFFFFFFFU) +#define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT (0U) +/*! MT_ST_ADDR - Memory Test Start Address */ +#define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT)) & DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK) +/*! @} */ + +/*! @name DDR_MT_END_EXT_ADDR - DDR SDRAM Memory Test End Extended Address */ +/*! @{ */ + +#define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK (0xFFU) +#define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT (0U) +/*! MT_END_EXT_ADDR - Memory Test End Extended Address */ +#define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT)) & DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK) +/*! @} */ + +/*! @name DDR_MT_END_ADDR - DDR SDRAM Memory Test End Address */ +/*! @{ */ + +#define DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK (0xFFFFFFFFU) +#define DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT (0U) +/*! MT_END_ADDR - Memory Test End Address */ +#define DDRC_DDR_MT_END_ADDR_MT_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT)) & DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK) +/*! @} */ + +/*! @name ERR_EN - Error Enable */ +/*! @{ */ + +#define DDRC_ERR_EN_WTE_EN_MASK (0x1U) +#define DDRC_ERR_EN_WTE_EN_SHIFT (0U) +/*! WTE_EN - Write Tag Error Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_WTE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_WTE_EN_SHIFT)) & DDRC_ERR_EN_WTE_EN_MASK) + +#define DDRC_ERR_EN_RTE_EN_MASK (0x2U) +#define DDRC_ERR_EN_RTE_EN_SHIFT (1U) +/*! RTE_EN - Read Tag Error Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_RTE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_RTE_EN_SHIFT)) & DDRC_ERR_EN_RTE_EN_MASK) + +#define DDRC_ERR_EN_PAR_1_EN_MASK (0x20U) +#define DDRC_ERR_EN_PAR_1_EN_SHIFT (5U) +/*! PAR_1_EN - Parity Enable For Internal Errors + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_PAR_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_PAR_1_EN_SHIFT)) & DDRC_ERR_EN_PAR_1_EN_MASK) + +#define DDRC_ERR_EN_ECC_EN_RAM_2_MASK (0x40U) +#define DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT (6U) +/*! ECC_EN_RAM_2 - ECC Enable For On-Chip RAM 2 + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_ECC_EN_RAM_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT)) & DDRC_ERR_EN_ECC_EN_RAM_2_MASK) + +#define DDRC_ERR_EN_ECC_EN_RAM_1_MASK (0x80U) +#define DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT (7U) +/*! ECC_EN_RAM_1 - ECC Enable For On-Chip RAM 1 + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_ECC_EN_RAM_1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT)) & DDRC_ERR_EN_ECC_EN_RAM_1_MASK) + +#define DDRC_ERR_EN_CRC_2_EN_MASK (0x100U) +#define DDRC_ERR_EN_CRC_2_EN_SHIFT (8U) +/*! CRC_2_EN - CRC Enable For Group 2 Registers + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_CRC_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_CRC_2_EN_SHIFT)) & DDRC_ERR_EN_CRC_2_EN_MASK) + +#define DDRC_ERR_EN_CRC_1_EN_MASK (0x200U) +#define DDRC_ERR_EN_CRC_1_EN_SHIFT (9U) +/*! CRC_1_EN - CRC Enable For Group 1 Registers + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_CRC_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_CRC_1_EN_SHIFT)) & DDRC_ERR_EN_CRC_1_EN_MASK) + +#define DDRC_ERR_EN_INLINE_ECC_EN_MASK (0x40000000U) +#define DDRC_ERR_EN_INLINE_ECC_EN_SHIFT (30U) +/*! INLINE_ECC_EN - Inline ECC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_INLINE_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_INLINE_ECC_EN_SHIFT)) & DDRC_ERR_EN_INLINE_ECC_EN_MASK) + +#define DDRC_ERR_EN_ECC_EN_MASK (0x80000000U) +#define DDRC_ERR_EN_ECC_EN_SHIFT (31U) +/*! ECC_EN - ECC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_SHIFT)) & DDRC_ERR_EN_ECC_EN_MASK) +/*! @} */ + +/*! @name DATA_ERR_INJECT_HI - Memory Data Path Error Injection Mask High */ +/*! @{ */ + +#define DDRC_DATA_ERR_INJECT_HI_EIMH_MASK (0xFFFFFFFFU) +#define DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT (0U) +/*! EIMH - Error Injection Mask High Data Path */ +#define DDRC_DATA_ERR_INJECT_HI_EIMH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT)) & DDRC_DATA_ERR_INJECT_HI_EIMH_MASK) +/*! @} */ + +/*! @name DATA_ERR_INJECT_LO - Memory Data Path Error Injection Mask Low */ +/*! @{ */ + +#define DDRC_DATA_ERR_INJECT_LO_EIML_MASK (0xFFFFFFFFU) +#define DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT (0U) +/*! EIML - Error Injection Mask Low Data Bit */ +#define DDRC_DATA_ERR_INJECT_LO_EIML(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT)) & DDRC_DATA_ERR_INJECT_LO_EIML_MASK) +/*! @} */ + +/*! @name ERR_INJECT - Memory Data Path Error Injection Mask ECC */ +/*! @{ */ + +#define DDRC_ERR_INJECT_EEIM_MASK (0xFFU) +#define DDRC_ERR_INJECT_EEIM_SHIFT (0U) +/*! EEIM - ECC Error Injection Mask */ +#define DDRC_ERR_INJECT_EEIM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_EEIM_SHIFT)) & DDRC_ERR_INJECT_EEIM_MASK) + +#define DDRC_ERR_INJECT_EIEN_MASK (0x100U) +#define DDRC_ERR_INJECT_EIEN_SHIFT (8U) +/*! EIEN - Error Injection Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_INJECT_EIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_EIEN_SHIFT)) & DDRC_ERR_INJECT_EIEN_MASK) + +#define DDRC_ERR_INJECT_NUM_ECC_INJ_MASK (0xF000U) +#define DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT (12U) +/*! NUM_ECC_INJ - Number Of ECC Errors Injected + * 0b0000..ECC errors are injected until the error injection is disabled + * 0b0001..4 + * 0b0010..8 + * 0b0011..16 + * 0b0100..20 + * 0b0101..24 + * 0b0110..28 + * 0b0111..32 + * 0b1000..36 + * 0b1001..40 + * 0b1010..44 + * 0b1011..48 + * 0b1100..52 + * 0b1101..56 + * 0b1110..60 + * 0b1111..64 + */ +#define DDRC_ERR_INJECT_NUM_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT)) & DDRC_ERR_INJECT_NUM_ECC_INJ_MASK) + +#define DDRC_ERR_INJECT_PIEN_MASK (0x10000U) +#define DDRC_ERR_INJECT_PIEN_SHIFT (16U) +/*! PIEN - Parity Error Injection Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_INJECT_PIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_PIEN_SHIFT)) & DDRC_ERR_INJECT_PIEN_MASK) + +#define DDRC_ERR_INJECT_INTEIN_MASK (0x20000U) +#define DDRC_ERR_INJECT_INTEIN_SHIFT (17U) +/*! INTEIN - Internal Error Injection Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_INJECT_INTEIN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_INTEIN_SHIFT)) & DDRC_ERR_INJECT_INTEIN_MASK) + +#define DDRC_ERR_INJECT_INTIES_MASK (0x1C0000U) +#define DDRC_ERR_INJECT_INTIES_SHIFT (18U) +/*! INTIES - Internal Error Injection Source + * 0b000..Read tag + * 0b001..Write tag + * 0b010..Read tag timeout + * 0b011..Write tag timeout + * 0b100..Reserved + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define DDRC_ERR_INJECT_INTIES(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_INTIES_SHIFT)) & DDRC_ERR_INJECT_INTIES_MASK) + +#define DDRC_ERR_INJECT_ECC_INJ_SRC_MASK (0x600000U) +#define DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT (21U) +/*! ECC_INJ_SRC - ECC Injection Source + * 0b00..DDR SDRAM ECC using programmed data and ECC injection masks + * 0b01..On-chip RAM ECC 1 + * 0b10..On-chip RAM ECC 2 + * 0b11..DDR SDRAM ECC. This setting forces a 1 or 2-bit ECC syndrome error based on the value of FRC2B + */ +#define DDRC_ERR_INJECT_ECC_INJ_SRC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT)) & DDRC_ERR_INJECT_ECC_INJ_SRC_MASK) + +#define DDRC_ERR_INJECT_FRC2B_MASK (0x800000U) +#define DDRC_ERR_INJECT_FRC2B_SHIFT (23U) +/*! FRC2B - Force 2-Bit Error + * 0b0..SBE + * 0b1..2-bit error + */ +#define DDRC_ERR_INJECT_FRC2B(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_FRC2B_SHIFT)) & DDRC_ERR_INJECT_FRC2B_MASK) + +#define DDRC_ERR_INJECT_PAR_INJ_SRC_MASK (0x3000000U) +#define DDRC_ERR_INJECT_PAR_INJ_SRC_SHIFT (24U) +/*! PAR_INJ_SRC - Parity Error Injection Source + * 0b00..On-chip write buffer ECC + * 0b01..On-chip parity 1 + * 0b10..On-chip parity 2 + * 0b11..On-chip parity 3 + */ +#define DDRC_ERR_INJECT_PAR_INJ_SRC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_PAR_INJ_SRC_SHIFT)) & DDRC_ERR_INJECT_PAR_INJ_SRC_MASK) + +#define DDRC_ERR_INJECT_ADDR_TEN_MASK (0x80000000U) +#define DDRC_ERR_INJECT_ADDR_TEN_SHIFT (31U) +/*! ADDR_TEN - Address Trigger Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_INJECT_ADDR_TEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_ADDR_TEN_SHIFT)) & DDRC_ERR_INJECT_ADDR_TEN_MASK) +/*! @} */ + +/*! @name ADDR_ERR_INJ - Address Error Inject */ +/*! @{ */ + +#define DDRC_ADDR_ERR_INJ_ADDR_MASK (0xFFFFFFFFU) +#define DDRC_ADDR_ERR_INJ_ADDR_SHIFT (0U) +/*! ADDR - Address */ +#define DDRC_ADDR_ERR_INJ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDR_ERR_INJ_ADDR_SHIFT)) & DDRC_ADDR_ERR_INJ_ADDR_MASK) +/*! @} */ + +/*! @name EXT_ADDR_ERR_INJ - Extended Address Error Inject */ +/*! @{ */ + +#define DDRC_EXT_ADDR_ERR_INJ_EADDR_MASK (0xFFU) +#define DDRC_EXT_ADDR_ERR_INJ_EADDR_SHIFT (0U) +/*! EADDR - Extended Address */ +#define DDRC_EXT_ADDR_ERR_INJ_EADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_EXT_ADDR_ERR_INJ_EADDR_SHIFT)) & DDRC_EXT_ADDR_ERR_INJ_EADDR_MASK) +/*! @} */ + +/*! @name CAPTURE_EXT_DATA_HI - Memory Extended Data Path Read Capture High */ +/*! @{ */ + +#define DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT (0U) +/*! ECEHD - Error Capture Extended High Data Path */ +#define DDRC_CAPTURE_EXT_DATA_HI_ECEHD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT)) & DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK) +/*! @} */ + +/*! @name CAPTURE_EXT_DATA_LO - Memory Extended Data Path Read Capture Low */ +/*! @{ */ + +#define DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT (0U) +/*! ECELD - Error Capture Extended Low Data Path */ +#define DDRC_CAPTURE_EXT_DATA_LO_ECELD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT)) & DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK) +/*! @} */ + +/*! @name CAPTURE_DATA_HI - Memory Data Path Read Capture High */ +/*! @{ */ + +#define DDRC_CAPTURE_DATA_HI_ECHD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_DATA_HI_ECHD_SHIFT (0U) +/*! ECHD - Error Capture High Data Path */ +#define DDRC_CAPTURE_DATA_HI_ECHD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_DATA_HI_ECHD_SHIFT)) & DDRC_CAPTURE_DATA_HI_ECHD_MASK) +/*! @} */ + +/*! @name CAPTURE_DATA_LO - Memory Data Path Read Capture Low */ +/*! @{ */ + +#define DDRC_CAPTURE_DATA_LO_ECLD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_DATA_LO_ECLD_SHIFT (0U) +/*! ECLD - Error Capture Low Data Path */ +#define DDRC_CAPTURE_DATA_LO_ECLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_DATA_LO_ECLD_SHIFT)) & DDRC_CAPTURE_DATA_LO_ECLD_MASK) +/*! @} */ + +/*! @name CAPTURE_ECC - Memory Data Path Read Capture ECC */ +/*! @{ */ + +#define DDRC_CAPTURE_ECC_ECE_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_ECC_ECE_SHIFT (0U) +/*! ECE - Error Capture ECC */ +#define DDRC_CAPTURE_ECC_ECE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ECC_ECE_SHIFT)) & DDRC_CAPTURE_ECC_ECE_MASK) +/*! @} */ + +/*! @name ERR_DETECT - Memory Error Detect */ +/*! @{ */ + +#define DDRC_ERR_DETECT_MSE_MASK (0x1U) +#define DDRC_ERR_DETECT_MSE_SHIFT (0U) +/*! MSE - Memory-Select Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_MSE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MSE_SHIFT)) & DDRC_ERR_DETECT_MSE_MASK) + +#define DDRC_ERR_DETECT_SBE_MASK (0x4U) +#define DDRC_ERR_DETECT_SBE_SHIFT (2U) +/*! SBE - Single-Bit ECC Errors + * 0b0..Did not cross + * 0b1..Crossed + */ +#define DDRC_ERR_DETECT_SBE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SBE_SHIFT)) & DDRC_ERR_DETECT_SBE_MASK) + +#define DDRC_ERR_DETECT_MBE_MASK (0x8U) +#define DDRC_ERR_DETECT_MBE_SHIFT (3U) +/*! MBE - Multiple-Bit Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_MBE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MBE_SHIFT)) & DDRC_ERR_DETECT_MBE_MASK) + +#define DDRC_ERR_DETECT_ILLTXNE_MASK (0x10U) +#define DDRC_ERR_DETECT_ILLTXNE_SHIFT (4U) +/*! ILLTXNE - Illegal transaction error. + * 0b0..An illegal transaction has not been detected by the DDRC. + * 0b1..A illegal transaction has been detected by the DDRC. + */ +#define DDRC_ERR_DETECT_ILLTXNE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_ILLTXNE_SHIFT)) & DDRC_ERR_DETECT_ILLTXNE_MASK) + +#define DDRC_ERR_DETECT_REFRATEE_MASK (0x80U) +#define DDRC_ERR_DETECT_REFRATEE_SHIFT (7U) +/*! REFRATEE - Refresh rate error. + * 0b0..A refresh rate error has not been detected. + * 0b1..A refresh rate error has been detected. + */ +#define DDRC_ERR_DETECT_REFRATEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_REFRATEE_SHIFT)) & DDRC_ERR_DETECT_REFRATEE_MASK) + +#define DDRC_ERR_DETECT_LKSTP4E_MASK (0x800U) +#define DDRC_ERR_DETECT_LKSTP4E_SHIFT (11U) +/*! LKSTP4E - Lockstep 4 error. + * 0b0..A Lockstep 4 error has not been detected. + * 0b1..A Lockstep 4 error has been detected. + */ +#define DDRC_ERR_DETECT_LKSTP4E(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_LKSTP4E_SHIFT)) & DDRC_ERR_DETECT_LKSTP4E_MASK) + +#define DDRC_ERR_DETECT_SSBE_MASK (0x1000U) +#define DDRC_ERR_DETECT_SSBE_SHIFT (12U) +/*! SSBE - Scrubbed Single-Bit ECC Error + * 0b0..Did not cross + * 0b1..Crossed + */ +#define DDRC_ERR_DETECT_SSBE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SSBE_SHIFT)) & DDRC_ERR_DETECT_SSBE_MASK) + +#define DDRC_ERR_DETECT_LNKE_MASK (0x2000U) +#define DDRC_ERR_DETECT_LNKE_SHIFT (13U) +/*! LNKE - Link ECC Error + * 0b0..Did not cross + * 0b1..Crossed + */ +#define DDRC_ERR_DETECT_LNKE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_LNKE_SHIFT)) & DDRC_ERR_DETECT_LNKE_MASK) + +#define DDRC_ERR_DETECT_PHYE_MASK (0x10000U) +#define DDRC_ERR_DETECT_PHYE_SHIFT (16U) +/*! PHYE - PHY error. + * 0b0..A DDR PHY error has not been detected. + * 0b1..An error has been detected by the DDR PHY. + */ +#define DDRC_ERR_DETECT_PHYE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_PHYE_SHIFT)) & DDRC_ERR_DETECT_PHYE_MASK) + +#define DDRC_ERR_DETECT_IPE_MASK (0x80000U) +#define DDRC_ERR_DETECT_IPE_SHIFT (19U) +/*! IPE - Internal Parity Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_IPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_IPE_SHIFT)) & DDRC_ERR_DETECT_IPE_MASK) + +#define DDRC_ERR_DETECT_UPDTMTE_MASK (0x100000U) +#define DDRC_ERR_DETECT_UPDTMTE_SHIFT (20U) +/*! UPDTMTE - Update Timeout Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_UPDTMTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_UPDTMTE_SHIFT)) & DDRC_ERR_DETECT_UPDTMTE_MASK) + +#define DDRC_ERR_DETECT_CRCE_MASK (0x200000U) +#define DDRC_ERR_DETECT_CRCE_SHIFT (21U) +/*! CRCE - Configuration CRC Error + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_CRCE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_CRCE_SHIFT)) & DDRC_ERR_DETECT_CRCE_MASK) + +#define DDRC_ERR_DETECT_SMBE2_MASK (0x400000U) +#define DDRC_ERR_DETECT_SMBE2_SHIFT (22U) +/*! SMBE2 - SRAM Multi-Bit Error 2 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SMBE2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SMBE2_SHIFT)) & DDRC_ERR_DETECT_SMBE2_MASK) + +#define DDRC_ERR_DETECT_SMBE1_MASK (0x800000U) +#define DDRC_ERR_DETECT_SMBE1_SHIFT (23U) +/*! SMBE1 - SRAM Multi-Bit Error 1 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SMBE1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SMBE1_SHIFT)) & DDRC_ERR_DETECT_SMBE1_MASK) + +#define DDRC_ERR_DETECT_SSBE2_MASK (0x1000000U) +#define DDRC_ERR_DETECT_SSBE2_SHIFT (24U) +/*! SSBE2 - SRAM SBE 2 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SSBE2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SSBE2_SHIFT)) & DDRC_ERR_DETECT_SSBE2_MASK) + +#define DDRC_ERR_DETECT_SSBE1_MASK (0x2000000U) +#define DDRC_ERR_DETECT_SSBE1_SHIFT (25U) +/*! SSBE1 - SRAM SBE 1 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SSBE1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SSBE1_SHIFT)) & DDRC_ERR_DETECT_SSBE1_MASK) + +#define DDRC_ERR_DETECT_WTAGE_MASK (0x4000000U) +#define DDRC_ERR_DETECT_WTAGE_SHIFT (26U) +/*! WTAGE - Write Tag Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_WTAGE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_WTAGE_SHIFT)) & DDRC_ERR_DETECT_WTAGE_MASK) + +#define DDRC_ERR_DETECT_RTAGE_MASK (0x8000000U) +#define DDRC_ERR_DETECT_RTAGE_SHIFT (27U) +/*! RTAGE - Read Tag Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_RTAGE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_RTAGE_SHIFT)) & DDRC_ERR_DETECT_RTAGE_MASK) + +#define DDRC_ERR_DETECT_WTTE_MASK (0x10000000U) +#define DDRC_ERR_DETECT_WTTE_SHIFT (28U) +/*! WTTE - Write Tag Timeout Error + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_DETECT_WTTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_WTTE_SHIFT)) & DDRC_ERR_DETECT_WTTE_MASK) + +#define DDRC_ERR_DETECT_RTTE_MASK (0x20000000U) +#define DDRC_ERR_DETECT_RTTE_SHIFT (29U) +/*! RTTE - Read Tag Timeout Error + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_DETECT_RTTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_RTTE_SHIFT)) & DDRC_ERR_DETECT_RTTE_MASK) + +#define DDRC_ERR_DETECT_RTMTE_MASK (0x40000000U) +#define DDRC_ERR_DETECT_RTMTE_SHIFT (30U) +/*! RTMTE - Read Timeout Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_RTMTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_RTMTE_SHIFT)) & DDRC_ERR_DETECT_RTMTE_MASK) + +#define DDRC_ERR_DETECT_MME_MASK (0x80000000U) +#define DDRC_ERR_DETECT_MME_SHIFT (31U) +/*! MME - Multiple Memory Errors + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_MME(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MME_SHIFT)) & DDRC_ERR_DETECT_MME_MASK) +/*! @} */ + +/*! @name ERR_DISABLE - Memory Error Disable */ +/*! @{ */ + +#define DDRC_ERR_DISABLE_MSED_MASK (0x1U) +#define DDRC_ERR_DISABLE_MSED_SHIFT (0U) +/*! MSED - Memory-Select Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_MSED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_MSED_SHIFT)) & DDRC_ERR_DISABLE_MSED_MASK) + +#define DDRC_ERR_DISABLE_SBED_MASK (0x4U) +#define DDRC_ERR_DISABLE_SBED_SHIFT (2U) +/*! SBED - Single-Bit ECC Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_SBED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_SBED_SHIFT)) & DDRC_ERR_DISABLE_SBED_MASK) + +#define DDRC_ERR_DISABLE_MBED_MASK (0x8U) +#define DDRC_ERR_DISABLE_MBED_SHIFT (3U) +/*! MBED - Multiple-Bit ECC Error Disable + * 0b0..Detected + * 0b1..Not detected or reported + */ +#define DDRC_ERR_DISABLE_MBED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_MBED_SHIFT)) & DDRC_ERR_DISABLE_MBED_MASK) + +#define DDRC_ERR_DISABLE_ILLTXNED_MASK (0x10U) +#define DDRC_ERR_DISABLE_ILLTXNED_SHIFT (4U) +/*! ILLTXNED - Illegal Transaction Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_ILLTXNED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_ILLTXNED_SHIFT)) & DDRC_ERR_DISABLE_ILLTXNED_MASK) + +#define DDRC_ERR_DISABLE_REFRATEED_MASK (0x80U) +#define DDRC_ERR_DISABLE_REFRATEED_SHIFT (7U) +/*! REFRATEED - Refresh Rate Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_REFRATEED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_REFRATEED_SHIFT)) & DDRC_ERR_DISABLE_REFRATEED_MASK) + +#define DDRC_ERR_DISABLE_LNKED_MASK (0x100U) +#define DDRC_ERR_DISABLE_LNKED_SHIFT (8U) +/*! LNKED - Link ECC Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_LNKED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_LNKED_SHIFT)) & DDRC_ERR_DISABLE_LNKED_MASK) + +#define DDRC_ERR_DISABLE_SSBED_MASK (0x1000U) +#define DDRC_ERR_DISABLE_SSBED_SHIFT (12U) +/*! SSBED - Scrubbed Single-Bit ECC Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_SSBED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_SSBED_SHIFT)) & DDRC_ERR_DISABLE_SSBED_MASK) + +#define DDRC_ERR_DISABLE_PHYED_MASK (0x10000U) +#define DDRC_ERR_DISABLE_PHYED_SHIFT (16U) +/*! PHYED - PHY Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_PHYED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_PHYED_SHIFT)) & DDRC_ERR_DISABLE_PHYED_MASK) + +#define DDRC_ERR_DISABLE_UPDTMTED_MASK (0x100000U) +#define DDRC_ERR_DISABLE_UPDTMTED_SHIFT (20U) +/*! UPDTMTED - Update Timeout Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_UPDTMTED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_UPDTMTED_SHIFT)) & DDRC_ERR_DISABLE_UPDTMTED_MASK) +/*! @} */ + +/*! @name ERR_INT_EN - Memory Error Interrupt Enable */ +/*! @{ */ + +#define DDRC_ERR_INT_EN_MSEE_MASK (0x1U) +#define DDRC_ERR_INT_EN_MSEE_SHIFT (0U) +/*! MSEE - Memory-Select Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_MSEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_MSEE_SHIFT)) & DDRC_ERR_INT_EN_MSEE_MASK) + +#define DDRC_ERR_INT_EN_SBEE_MASK (0x4U) +#define DDRC_ERR_INT_EN_SBEE_SHIFT (2U) +/*! SBEE - Single-Bit ECC Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_SBEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_SBEE_SHIFT)) & DDRC_ERR_INT_EN_SBEE_MASK) + +#define DDRC_ERR_INT_EN_MBEE_MASK (0x8U) +#define DDRC_ERR_INT_EN_MBEE_SHIFT (3U) +/*! MBEE - Multiple-Bit ECC Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_MBEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_MBEE_SHIFT)) & DDRC_ERR_INT_EN_MBEE_MASK) + +#define DDRC_ERR_INT_EN_SSBE12E_MASK (0x10U) +#define DDRC_ERR_INT_EN_SSBE12E_SHIFT (4U) +/*! SSBE12E - SRAM Single-Bit Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_SSBE12E(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_SSBE12E_SHIFT)) & DDRC_ERR_INT_EN_SSBE12E_MASK) + +#define DDRC_ERR_INT_EN_REFRATEEE_MASK (0x80U) +#define DDRC_ERR_INT_EN_REFRATEEE_SHIFT (7U) +/*! REFRATEEE - Refresh Rate Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_REFRATEEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_REFRATEEE_SHIFT)) & DDRC_ERR_INT_EN_REFRATEEE_MASK) + +#define DDRC_ERR_INT_EN_ILLTXNEE_MASK (0x100U) +#define DDRC_ERR_INT_EN_ILLTXNEE_SHIFT (8U) +/*! ILLTXNEE - Illegal Transaction Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_ILLTXNEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_ILLTXNEE_SHIFT)) & DDRC_ERR_INT_EN_ILLTXNEE_MASK) + +#define DDRC_ERR_INT_EN_LNKEE_MASK (0x200U) +#define DDRC_ERR_INT_EN_LNKEE_SHIFT (9U) +/*! LNKEE - Link ECC Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_LNKEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_LNKEE_SHIFT)) & DDRC_ERR_INT_EN_LNKEE_MASK) + +#define DDRC_ERR_INT_EN_SSBEE_MASK (0x1000U) +#define DDRC_ERR_INT_EN_SSBEE_SHIFT (12U) +/*! SSBEE - Scrubbed Single-Bit ECC Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_SSBEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_SSBEE_SHIFT)) & DDRC_ERR_INT_EN_SSBEE_MASK) + +#define DDRC_ERR_INT_EN_PHYEE_MASK (0x10000U) +#define DDRC_ERR_INT_EN_PHYEE_SHIFT (16U) +/*! PHYEE - PHY error interrupt enable. + * 0b0..PHY errors cannot generate interrupts. + * 0b1..PHY errors generate interrupts. + */ +#define DDRC_ERR_INT_EN_PHYEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_PHYEE_SHIFT)) & DDRC_ERR_INT_EN_PHYEE_MASK) + +#define DDRC_ERR_INT_EN_UPDTMTEE_MASK (0x100000U) +#define DDRC_ERR_INT_EN_UPDTMTEE_SHIFT (20U) +/*! UPDTMTEE - Update Timeout Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_UPDTMTEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_UPDTMTEE_SHIFT)) & DDRC_ERR_INT_EN_UPDTMTEE_MASK) +/*! @} */ + +/*! @name CAPTURE_ATTRIBUTES - Memory Error Attributes Capture */ +/*! @{ */ + +#define DDRC_CAPTURE_ATTRIBUTES_VLD_MASK (0x1U) +#define DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define DDRC_CAPTURE_ATTRIBUTES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_VLD_MASK) + +#define DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK (0x3000U) +#define DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT (12U) +/*! TTYP - Error Transaction Type + * 0b00..Reserved + * 0b01..Write + * 0b10..Read + * 0b11..Read-modify-write + */ +#define DDRC_CAPTURE_ATTRIBUTES_TTYP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK) + +#define DDRC_CAPTURE_ATTRIBUTES_TSIZ_MASK (0x7000000U) +#define DDRC_CAPTURE_ATTRIBUTES_TSIZ_SHIFT (24U) +/*! TSIZ - Error Transaction Size + * 0b000..8 + * 0b001..1 + * 0b010..2 + * 0b011..3 + * 0b100..4 + * 0b101..5 + * 0b110..6 + * 0b111..7 + */ +#define DDRC_CAPTURE_ATTRIBUTES_TSIZ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_TSIZ_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_TSIZ_MASK) + +#define DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK (0x70000000U) +#define DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT (28U) +/*! BNUM - Data Beat Number */ +#define DDRC_CAPTURE_ATTRIBUTES_BNUM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK) +/*! @} */ + +/*! @name CAPTURE_ADDRESS - Memory Error Address Capture */ +/*! @{ */ + +#define DDRC_CAPTURE_ADDRESS_CADDR_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_ADDRESS_CADDR_SHIFT (0U) +/*! CADDR - Captured Address */ +#define DDRC_CAPTURE_ADDRESS_CADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ADDRESS_CADDR_SHIFT)) & DDRC_CAPTURE_ADDRESS_CADDR_MASK) +/*! @} */ + +/*! @name CAPTURE_EXT_ADDRESS - Memory Error Extended Address Capture */ +/*! @{ */ + +#define DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK (0xFFU) +#define DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT (0U) +/*! CEADDR - Captured Extended Address */ +#define DDRC_CAPTURE_EXT_ADDRESS_CEADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT)) & DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK) +/*! @} */ + +/*! @name ERR_SBE - Single-Bit ECC Memory Error Management */ +/*! @{ */ + +#define DDRC_ERR_SBE_SBEC_MASK (0xFFU) +#define DDRC_ERR_SBE_SBEC_SHIFT (0U) +/*! SBEC - SBE Counter */ +#define DDRC_ERR_SBE_SBEC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SBEC_SHIFT)) & DDRC_ERR_SBE_SBEC_MASK) + +#define DDRC_ERR_SBE_SSBEC_MASK (0xFF00U) +#define DDRC_ERR_SBE_SSBEC_SHIFT (8U) +/*! SSBEC - Scrubbed SBE Counter */ +#define DDRC_ERR_SBE_SSBEC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SSBEC_SHIFT)) & DDRC_ERR_SBE_SSBEC_MASK) + +#define DDRC_ERR_SBE_SBET_MASK (0xFF0000U) +#define DDRC_ERR_SBE_SBET_SHIFT (16U) +/*! SBET - SBE Threshold */ +#define DDRC_ERR_SBE_SBET(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SBET_SHIFT)) & DDRC_ERR_SBE_SBET_MASK) + +#define DDRC_ERR_SBE_SSBET_MASK (0xFF000000U) +#define DDRC_ERR_SBE_SSBET_SHIFT (24U) +/*! SSBET - Scrubbed SBE Threshold */ +#define DDRC_ERR_SBE_SSBET(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SSBET_SHIFT)) & DDRC_ERR_SBE_SSBET_MASK) +/*! @} */ + +/*! @name REG_CRC_GRP_1 - Register CRC Code For Group 1 */ +/*! @{ */ + +#define DDRC_REG_CRC_GRP_1_CRC_1_MASK (0xFFFFFFFFU) +#define DDRC_REG_CRC_GRP_1_CRC_1_SHIFT (0U) +/*! CRC_1 - Programmed CRC Code */ +#define DDRC_REG_CRC_GRP_1_CRC_1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REG_CRC_GRP_1_CRC_1_SHIFT)) & DDRC_REG_CRC_GRP_1_CRC_1_MASK) +/*! @} */ + +/*! @name REG_CRC_GRP_2 - Register CRC Code For Group 2 */ +/*! @{ */ + +#define DDRC_REG_CRC_GRP_2_CRC_2_MASK (0xFFFFFFFFU) +#define DDRC_REG_CRC_GRP_2_CRC_2_SHIFT (0U) +/*! CRC_2 - Programmed CRC Code */ +#define DDRC_REG_CRC_GRP_2_CRC_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REG_CRC_GRP_2_CRC_2_SHIFT)) & DDRC_REG_CRC_GRP_2_CRC_2_MASK) +/*! @} */ + +/*! @name ECC_EXT_REG_0 - ECC Extended Region 0 Configuration */ +/*! @{ */ + +#define DDRC_ECC_EXT_REG_0_EXT_REG_0_EA_MASK (0xFFU) +#define DDRC_ECC_EXT_REG_0_EXT_REG_0_EA_SHIFT (0U) +/*! EXT_REG_0_EA - Extended Region 0 End Address */ +#define DDRC_ECC_EXT_REG_0_EXT_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_0_EXT_REG_0_EA_SHIFT)) & DDRC_ECC_EXT_REG_0_EXT_REG_0_EA_MASK) + +#define DDRC_ECC_EXT_REG_0_EXT_REG_0_SA_MASK (0xFF0000U) +#define DDRC_ECC_EXT_REG_0_EXT_REG_0_SA_SHIFT (16U) +/*! EXT_REG_0_SA - Extended Region 0 Start Address */ +#define DDRC_ECC_EXT_REG_0_EXT_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_0_EXT_REG_0_SA_SHIFT)) & DDRC_ECC_EXT_REG_0_EXT_REG_0_SA_MASK) +/*! @} */ + +/*! @name ECC_EXT_REG_1 - ECC Extended Region 1 Configuration */ +/*! @{ */ + +#define DDRC_ECC_EXT_REG_1_EXT_REG_1_EA_MASK (0xFFU) +#define DDRC_ECC_EXT_REG_1_EXT_REG_1_EA_SHIFT (0U) +/*! EXT_REG_1_EA - Extended Region 1 End Address */ +#define DDRC_ECC_EXT_REG_1_EXT_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_1_EXT_REG_1_EA_SHIFT)) & DDRC_ECC_EXT_REG_1_EXT_REG_1_EA_MASK) + +#define DDRC_ECC_EXT_REG_1_EXT_REG_1_SA_MASK (0xFF0000U) +#define DDRC_ECC_EXT_REG_1_EXT_REG_1_SA_SHIFT (16U) +/*! EXT_REG_1_SA - Extended Region 1 Start Address */ +#define DDRC_ECC_EXT_REG_1_EXT_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_1_EXT_REG_1_SA_SHIFT)) & DDRC_ECC_EXT_REG_1_EXT_REG_1_SA_MASK) +/*! @} */ + +/*! @name ECC_EXT_REG_2 - ECC Extended Region 2 Configuration */ +/*! @{ */ + +#define DDRC_ECC_EXT_REG_2_EXT_REG_2_EA_MASK (0xFFU) +#define DDRC_ECC_EXT_REG_2_EXT_REG_2_EA_SHIFT (0U) +/*! EXT_REG_2_EA - Extended Region 2 End Address */ +#define DDRC_ECC_EXT_REG_2_EXT_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_2_EXT_REG_2_EA_SHIFT)) & DDRC_ECC_EXT_REG_2_EXT_REG_2_EA_MASK) + +#define DDRC_ECC_EXT_REG_2_EXT_REG_2_SA_MASK (0xFF0000U) +#define DDRC_ECC_EXT_REG_2_EXT_REG_2_SA_SHIFT (16U) +/*! EXT_REG_2_SA - Extended Region 2 Start Address */ +#define DDRC_ECC_EXT_REG_2_EXT_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_2_EXT_REG_2_SA_SHIFT)) & DDRC_ECC_EXT_REG_2_EXT_REG_2_SA_MASK) +/*! @} */ + +/*! @name ECC_EXT_REG_3 - ECC Extended Region 3 Configuration */ +/*! @{ */ + +#define DDRC_ECC_EXT_REG_3_EXT_REG_3_EA_MASK (0xFFU) +#define DDRC_ECC_EXT_REG_3_EXT_REG_3_EA_SHIFT (0U) +/*! EXT_REG_3_EA - Extended Region 3 End Address */ +#define DDRC_ECC_EXT_REG_3_EXT_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_3_EXT_REG_3_EA_SHIFT)) & DDRC_ECC_EXT_REG_3_EXT_REG_3_EA_MASK) + +#define DDRC_ECC_EXT_REG_3_EXT_REG_3_SA_MASK (0xFF0000U) +#define DDRC_ECC_EXT_REG_3_EXT_REG_3_SA_SHIFT (16U) +/*! EXT_REG_3_SA - Extended Region 3 Start Address */ +#define DDRC_ECC_EXT_REG_3_EXT_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_3_EXT_REG_3_SA_SHIFT)) & DDRC_ECC_EXT_REG_3_EXT_REG_3_SA_MASK) +/*! @} */ + +/*! @name ECC_EXT_REG_4 - ECC Extended Region 4 Configuration */ +/*! @{ */ + +#define DDRC_ECC_EXT_REG_4_EXT_REG_4_EA_MASK (0xFFU) +#define DDRC_ECC_EXT_REG_4_EXT_REG_4_EA_SHIFT (0U) +/*! EXT_REG_4_EA - Extended Region 4 End Address */ +#define DDRC_ECC_EXT_REG_4_EXT_REG_4_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_4_EXT_REG_4_EA_SHIFT)) & DDRC_ECC_EXT_REG_4_EXT_REG_4_EA_MASK) + +#define DDRC_ECC_EXT_REG_4_EXT_REG_4_SA_MASK (0xFF0000U) +#define DDRC_ECC_EXT_REG_4_EXT_REG_4_SA_SHIFT (16U) +/*! EXT_REG_4_SA - Extended Region 4 Start Address */ +#define DDRC_ECC_EXT_REG_4_EXT_REG_4_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_4_EXT_REG_4_SA_SHIFT)) & DDRC_ECC_EXT_REG_4_EXT_REG_4_SA_MASK) +/*! @} */ + +/*! @name ECC_EXT_REG_5 - ECC Extended Region 5 Configuration */ +/*! @{ */ + +#define DDRC_ECC_EXT_REG_5_EXT_REG_5_EA_MASK (0xFFU) +#define DDRC_ECC_EXT_REG_5_EXT_REG_5_EA_SHIFT (0U) +/*! EXT_REG_5_EA - Extended Region 5 End Address */ +#define DDRC_ECC_EXT_REG_5_EXT_REG_5_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_5_EXT_REG_5_EA_SHIFT)) & DDRC_ECC_EXT_REG_5_EXT_REG_5_EA_MASK) + +#define DDRC_ECC_EXT_REG_5_EXT_REG_5_SA_MASK (0xFF0000U) +#define DDRC_ECC_EXT_REG_5_EXT_REG_5_SA_SHIFT (16U) +/*! EXT_REG_5_SA - Extended Region 5 Start Address */ +#define DDRC_ECC_EXT_REG_5_EXT_REG_5_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_5_EXT_REG_5_SA_SHIFT)) & DDRC_ECC_EXT_REG_5_EXT_REG_5_SA_MASK) +/*! @} */ + +/*! @name ECC_EXT_REG_6 - ECC Extended Region 6 Configuration */ +/*! @{ */ + +#define DDRC_ECC_EXT_REG_6_EXT_REG_6_EA_MASK (0xFFU) +#define DDRC_ECC_EXT_REG_6_EXT_REG_6_EA_SHIFT (0U) +/*! EXT_REG_6_EA - Extended Region 6 End Address */ +#define DDRC_ECC_EXT_REG_6_EXT_REG_6_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_6_EXT_REG_6_EA_SHIFT)) & DDRC_ECC_EXT_REG_6_EXT_REG_6_EA_MASK) + +#define DDRC_ECC_EXT_REG_6_EXT_REG_6_SA_MASK (0xFF0000U) +#define DDRC_ECC_EXT_REG_6_EXT_REG_6_SA_SHIFT (16U) +/*! EXT_REG_6_SA - Extended Region 6 Start Address */ +#define DDRC_ECC_EXT_REG_6_EXT_REG_6_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_6_EXT_REG_6_SA_SHIFT)) & DDRC_ECC_EXT_REG_6_EXT_REG_6_SA_MASK) +/*! @} */ + +/*! @name ECC_EXT_REG_7 - ECC Extended Region 7 Configuration */ +/*! @{ */ + +#define DDRC_ECC_EXT_REG_7_EXT_REG_7_EA_MASK (0xFFU) +#define DDRC_ECC_EXT_REG_7_EXT_REG_7_EA_SHIFT (0U) +/*! EXT_REG_7_EA - Extended Region 7 End Address */ +#define DDRC_ECC_EXT_REG_7_EXT_REG_7_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_7_EXT_REG_7_EA_SHIFT)) & DDRC_ECC_EXT_REG_7_EXT_REG_7_EA_MASK) + +#define DDRC_ECC_EXT_REG_7_EXT_REG_7_SA_MASK (0xFF0000U) +#define DDRC_ECC_EXT_REG_7_EXT_REG_7_SA_SHIFT (16U) +/*! EXT_REG_7_SA - Extended Region 7 Start Address */ +#define DDRC_ECC_EXT_REG_7_EXT_REG_7_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_EXT_REG_7_EXT_REG_7_SA_SHIFT)) & DDRC_ECC_EXT_REG_7_EXT_REG_7_SA_MASK) +/*! @} */ + +/*! @name ECC_REG_0 - ECC Region 0 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_0_REG_0_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_0_REG_0_EA_SHIFT (0U) +/*! REG_0_EA - Region 0 End Address */ +#define DDRC_ECC_REG_0_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_EA_SHIFT)) & DDRC_ECC_REG_0_REG_0_EA_MASK) + +#define DDRC_ECC_REG_0_REG_0_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_0_REG_0_SA_SHIFT (16U) +/*! REG_0_SA - Region 0 Start Address */ +#define DDRC_ECC_REG_0_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_SA_SHIFT)) & DDRC_ECC_REG_0_REG_0_SA_MASK) + +#define DDRC_ECC_REG_0_REG_0_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_0_REG_0_EN_SHIFT (31U) +/*! REG_0_EN - Region 0 Enable + * 0b0..Does not use region 0 for ECC enablement + * 0b1..Protects addresses from region 0 with ECC + */ +#define DDRC_ECC_REG_0_REG_0_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_EN_SHIFT)) & DDRC_ECC_REG_0_REG_0_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_1 - ECC Region 1 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_1_REG_1_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_1_REG_1_EA_SHIFT (0U) +/*! REG_1_EA - Region 1 End Address */ +#define DDRC_ECC_REG_1_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_EA_SHIFT)) & DDRC_ECC_REG_1_REG_1_EA_MASK) + +#define DDRC_ECC_REG_1_REG_1_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_1_REG_1_SA_SHIFT (16U) +/*! REG_1_SA - Region 1 Start Address */ +#define DDRC_ECC_REG_1_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_SA_SHIFT)) & DDRC_ECC_REG_1_REG_1_SA_MASK) + +#define DDRC_ECC_REG_1_REG_1_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_1_REG_1_EN_SHIFT (31U) +/*! REG_1_EN - Region 1 Enable + * 0b0..Does not use region 1 for ECC enablement + * 0b1..Protects addresses from region 1 with ECC + */ +#define DDRC_ECC_REG_1_REG_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_EN_SHIFT)) & DDRC_ECC_REG_1_REG_1_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_2 - ECC Region 2 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_2_REG_2_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_2_REG_2_EA_SHIFT (0U) +/*! REG_2_EA - Region 2 End Address */ +#define DDRC_ECC_REG_2_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_EA_SHIFT)) & DDRC_ECC_REG_2_REG_2_EA_MASK) + +#define DDRC_ECC_REG_2_REG_2_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_2_REG_2_SA_SHIFT (16U) +/*! REG_2_SA - Region 2 Start Address */ +#define DDRC_ECC_REG_2_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_SA_SHIFT)) & DDRC_ECC_REG_2_REG_2_SA_MASK) + +#define DDRC_ECC_REG_2_REG_2_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_2_REG_2_EN_SHIFT (31U) +/*! REG_2_EN - Region 2 Enable + * 0b0..Does not use region 2 for ECC enablement + * 0b1..Protects addresses from region 2 with ECC + */ +#define DDRC_ECC_REG_2_REG_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_EN_SHIFT)) & DDRC_ECC_REG_2_REG_2_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_3 - ECC Region 3 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_3_REG_3_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_3_REG_3_EA_SHIFT (0U) +/*! REG_3_EA - Region 3 End Address */ +#define DDRC_ECC_REG_3_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_EA_SHIFT)) & DDRC_ECC_REG_3_REG_3_EA_MASK) + +#define DDRC_ECC_REG_3_REG_3_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_3_REG_3_SA_SHIFT (16U) +/*! REG_3_SA - Region 3 Start Address */ +#define DDRC_ECC_REG_3_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_SA_SHIFT)) & DDRC_ECC_REG_3_REG_3_SA_MASK) + +#define DDRC_ECC_REG_3_REG_3_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_3_REG_3_EN_SHIFT (31U) +/*! REG_3_EN - Region 3 Enable + * 0b0..Does not use region 3 for ECC enablement + * 0b1..Protects addresses from region 3 with ECC + */ +#define DDRC_ECC_REG_3_REG_3_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_EN_SHIFT)) & DDRC_ECC_REG_3_REG_3_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_4 - ECC Region 4 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_4_REG_4_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_4_REG_4_EA_SHIFT (0U) +/*! REG_4_EA - Region 4 End Address */ +#define DDRC_ECC_REG_4_REG_4_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_EA_SHIFT)) & DDRC_ECC_REG_4_REG_4_EA_MASK) + +#define DDRC_ECC_REG_4_REG_4_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_4_REG_4_SA_SHIFT (16U) +/*! REG_4_SA - Region 4 Start Address */ +#define DDRC_ECC_REG_4_REG_4_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_SA_SHIFT)) & DDRC_ECC_REG_4_REG_4_SA_MASK) + +#define DDRC_ECC_REG_4_REG_4_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_4_REG_4_EN_SHIFT (31U) +/*! REG_4_EN - Region 4 Enable + * 0b0..Does not use region 4 for ECC enablement + * 0b1..Protects addresses from region 4 with ECC + */ +#define DDRC_ECC_REG_4_REG_4_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_EN_SHIFT)) & DDRC_ECC_REG_4_REG_4_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_5 - ECC Region 5 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_5_REG_5_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_5_REG_5_EA_SHIFT (0U) +/*! REG_5_EA - Region 5 End Address */ +#define DDRC_ECC_REG_5_REG_5_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_EA_SHIFT)) & DDRC_ECC_REG_5_REG_5_EA_MASK) + +#define DDRC_ECC_REG_5_REG_5_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_5_REG_5_SA_SHIFT (16U) +/*! REG_5_SA - Region 5 Start Address */ +#define DDRC_ECC_REG_5_REG_5_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_SA_SHIFT)) & DDRC_ECC_REG_5_REG_5_SA_MASK) + +#define DDRC_ECC_REG_5_REG_5_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_5_REG_5_EN_SHIFT (31U) +/*! REG_5_EN - Region 5 Enable + * 0b0..Does not use region 5 for ECC enablement + * 0b1..Protects addresses from region 5 with ECC + */ +#define DDRC_ECC_REG_5_REG_5_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_EN_SHIFT)) & DDRC_ECC_REG_5_REG_5_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_6 - ECC Region 6 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_6_REG_6_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_6_REG_6_EA_SHIFT (0U) +/*! REG_6_EA - Region 6 End Address */ +#define DDRC_ECC_REG_6_REG_6_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_EA_SHIFT)) & DDRC_ECC_REG_6_REG_6_EA_MASK) + +#define DDRC_ECC_REG_6_REG_6_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_6_REG_6_SA_SHIFT (16U) +/*! REG_6_SA - Region 6 Start Address */ +#define DDRC_ECC_REG_6_REG_6_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_SA_SHIFT)) & DDRC_ECC_REG_6_REG_6_SA_MASK) + +#define DDRC_ECC_REG_6_REG_6_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_6_REG_6_EN_SHIFT (31U) +/*! REG_6_EN - Region 6 Enable + * 0b0..Does not use region 6 for ECC enablement + * 0b1..Protects addresses from region 6 with ECC + */ +#define DDRC_ECC_REG_6_REG_6_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_EN_SHIFT)) & DDRC_ECC_REG_6_REG_6_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_7 - ECC Region 7 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_7_REG_7_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_7_REG_7_EA_SHIFT (0U) +/*! REG_7_EA - Region 7 End Address */ +#define DDRC_ECC_REG_7_REG_7_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_EA_SHIFT)) & DDRC_ECC_REG_7_REG_7_EA_MASK) + +#define DDRC_ECC_REG_7_REG_7_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_7_REG_7_SA_SHIFT (16U) +/*! REG_7_SA - Region 7 Start Address */ +#define DDRC_ECC_REG_7_REG_7_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_SA_SHIFT)) & DDRC_ECC_REG_7_REG_7_SA_MASK) + +#define DDRC_ECC_REG_7_REG_7_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_7_REG_7_EN_SHIFT (31U) +/*! REG_7_EN - Region 7 Enable + * 0b0..Does not use region 7 for ECC enablement + * 0b1..Protects addresses from region 7 with ECC + */ +#define DDRC_ECC_REG_7_REG_7_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_EN_SHIFT)) & DDRC_ECC_REG_7_REG_7_EN_MASK) +/*! @} */ + +/*! @name PMGC0 - Performance Monitor Global Control */ +/*! @{ */ + +#define DDRC_PMGC0_FCECE_MASK (0x20000000U) +#define DDRC_PMGC0_FCECE_SHIFT (29U) +/*! FCECE - Freeze Counters On Enabled Condition Or Event + * 0b0..Enabled if PMLCAn[CE] = 1, until an event or condition occurs. + * 0b1..Enabled if PMLCAn[CE] = 1, until an event or condition occurs. At this point, if PMGC0[FAC] = 1, you must write 0 to it. + */ +#define DDRC_PMGC0_FCECE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_FCECE_SHIFT)) & DDRC_PMGC0_FCECE_MASK) + +#define DDRC_PMGC0_PMIE_MASK (0x40000000U) +#define DDRC_PMGC0_PMIE_SHIFT (30U) +/*! PMIE - Performance Monitor Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_PMGC0_PMIE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_PMIE_SHIFT)) & DDRC_PMGC0_PMIE_MASK) + +#define DDRC_PMGC0_FAC_MASK (0x80000000U) +#define DDRC_PMGC0_FAC_SHIFT (31U) +/*! FAC - Freeze All Counters + * 0b0..Incremented + * 0b1..Not incremented + */ +#define DDRC_PMGC0_FAC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_FAC_SHIFT)) & DDRC_PMGC0_FAC_MASK) +/*! @} */ + +/*! @name PMLCA0 - Performance Monitor Local Control A0 */ +/*! @{ */ + +#define DDRC_PMLCA0_CE_MASK (0x4000000U) +#define DDRC_PMLCA0_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions for PMC0n cannot occur (PMC0n cannot cause interrupts or freeze counters) + * 0b1..Counter overflow conditions occur when the most-significant bit of PMC0n is 1 + */ +#define DDRC_PMLCA0_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA0_CE_SHIFT)) & DDRC_PMLCA0_CE_MASK) + +#define DDRC_PMLCA0_FC_MASK (0x80000000U) +#define DDRC_PMLCA0_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA0_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA0_FC_SHIFT)) & DDRC_PMLCA0_FC_MASK) +/*! @} */ + +/*! @name PMLCB0 - Performance Monitor Local Control B0 */ +/*! @{ */ + +#define DDRC_PMLCB0_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB0_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB0_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB0_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB0_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB0_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB0_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGONCNTL_SHIFT)) & DDRC_PMLCB0_TRIGONCNTL_MASK) + +#define DDRC_PMLCB0_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB0_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB0_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB0_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB0_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB0_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB0_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGONSEL_SHIFT)) & DDRC_PMLCB0_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC0A - PMC 0a */ +/*! @{ */ + +#define DDRC_PMC0A_PMC0_MASK (0xFFFFFFFFU) +#define DDRC_PMC0A_PMC0_SHIFT (0U) +/*! PMC0 - Counter 0 */ +#define DDRC_PMC0A_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC0A_PMC0_SHIFT)) & DDRC_PMC0A_PMC0_MASK) +/*! @} */ + +/*! @name PMC0B - PMC 0b */ +/*! @{ */ + +#define DDRC_PMC0B_PMC0_MASK (0xFFFFFFFFU) +#define DDRC_PMC0B_PMC0_SHIFT (0U) +/*! PMC0 - Counter 0 */ +#define DDRC_PMC0B_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC0B_PMC0_SHIFT)) & DDRC_PMC0B_PMC0_MASK) +/*! @} */ + +/*! @name PMLCA1 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA1_BDIST_MASK (0x3FU) +#define DDRC_PMLCA1_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA1_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BDIST_SHIFT)) & DDRC_PMLCA1_BDIST_MASK) + +#define DDRC_PMLCA1_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA1_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA1_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BGRAN_SHIFT)) & DDRC_PMLCA1_BGRAN_MASK) + +#define DDRC_PMLCA1_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA1_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA1_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BSIZE_SHIFT)) & DDRC_PMLCA1_BSIZE_MASK) + +#define DDRC_PMLCA1_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA1_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA1_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_EVENT_SHIFT)) & DDRC_PMLCA1_EVENT_MASK) + +#define DDRC_PMLCA1_CE_MASK (0x4000000U) +#define DDRC_PMLCA1_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA1_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_CE_SHIFT)) & DDRC_PMLCA1_CE_MASK) + +#define DDRC_PMLCA1_FC_MASK (0x80000000U) +#define DDRC_PMLCA1_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA1_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_FC_SHIFT)) & DDRC_PMLCA1_FC_MASK) +/*! @} */ + +/*! @name PMLCB1 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB1_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB1_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB1_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_THRESHOLD_SHIFT)) & DDRC_PMLCB1_THRESHOLD_MASK) + +#define DDRC_PMLCB1_TBMULT_MASK (0x700U) +#define DDRC_PMLCB1_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB1_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TBMULT_SHIFT)) & DDRC_PMLCB1_TBMULT_MASK) + +#define DDRC_PMLCB1_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB1_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB1_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB1_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB1_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB1_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB1_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGONCNTL_SHIFT)) & DDRC_PMLCB1_TRIGONCNTL_MASK) + +#define DDRC_PMLCB1_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB1_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB1_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB1_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB1_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB1_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB1_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGONSEL_SHIFT)) & DDRC_PMLCB1_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC1 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC1_PMC1_MASK (0xFFFFFFFFU) +#define DDRC_PMC1_PMC1_SHIFT (0U) +/*! PMC1 - Event Count */ +#define DDRC_PMC1_PMC1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC1_PMC1_SHIFT)) & DDRC_PMC1_PMC1_MASK) +/*! @} */ + +/*! @name PMLCA2 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA2_BDIST_MASK (0x3FU) +#define DDRC_PMLCA2_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA2_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BDIST_SHIFT)) & DDRC_PMLCA2_BDIST_MASK) + +#define DDRC_PMLCA2_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA2_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA2_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BGRAN_SHIFT)) & DDRC_PMLCA2_BGRAN_MASK) + +#define DDRC_PMLCA2_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA2_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA2_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BSIZE_SHIFT)) & DDRC_PMLCA2_BSIZE_MASK) + +#define DDRC_PMLCA2_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA2_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA2_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_EVENT_SHIFT)) & DDRC_PMLCA2_EVENT_MASK) + +#define DDRC_PMLCA2_CE_MASK (0x4000000U) +#define DDRC_PMLCA2_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA2_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_CE_SHIFT)) & DDRC_PMLCA2_CE_MASK) + +#define DDRC_PMLCA2_FC_MASK (0x80000000U) +#define DDRC_PMLCA2_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA2_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_FC_SHIFT)) & DDRC_PMLCA2_FC_MASK) +/*! @} */ + +/*! @name PMLCB2 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB2_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB2_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB2_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_THRESHOLD_SHIFT)) & DDRC_PMLCB2_THRESHOLD_MASK) + +#define DDRC_PMLCB2_TBMULT_MASK (0x700U) +#define DDRC_PMLCB2_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB2_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TBMULT_SHIFT)) & DDRC_PMLCB2_TBMULT_MASK) + +#define DDRC_PMLCB2_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB2_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB2_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB2_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB2_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB2_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB2_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGONCNTL_SHIFT)) & DDRC_PMLCB2_TRIGONCNTL_MASK) + +#define DDRC_PMLCB2_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB2_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB2_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB2_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB2_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB2_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB2_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGONSEL_SHIFT)) & DDRC_PMLCB2_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC2 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC2_PMC2_MASK (0xFFFFFFFFU) +#define DDRC_PMC2_PMC2_SHIFT (0U) +/*! PMC2 - Event Count */ +#define DDRC_PMC2_PMC2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC2_PMC2_SHIFT)) & DDRC_PMC2_PMC2_MASK) +/*! @} */ + +/*! @name PMLCA3 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA3_BDIST_MASK (0x3FU) +#define DDRC_PMLCA3_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA3_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BDIST_SHIFT)) & DDRC_PMLCA3_BDIST_MASK) + +#define DDRC_PMLCA3_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA3_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA3_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BGRAN_SHIFT)) & DDRC_PMLCA3_BGRAN_MASK) + +#define DDRC_PMLCA3_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA3_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA3_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BSIZE_SHIFT)) & DDRC_PMLCA3_BSIZE_MASK) + +#define DDRC_PMLCA3_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA3_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA3_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_EVENT_SHIFT)) & DDRC_PMLCA3_EVENT_MASK) + +#define DDRC_PMLCA3_CE_MASK (0x4000000U) +#define DDRC_PMLCA3_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA3_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_CE_SHIFT)) & DDRC_PMLCA3_CE_MASK) + +#define DDRC_PMLCA3_FC_MASK (0x80000000U) +#define DDRC_PMLCA3_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA3_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_FC_SHIFT)) & DDRC_PMLCA3_FC_MASK) +/*! @} */ + +/*! @name PMLCB3 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB3_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB3_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB3_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_THRESHOLD_SHIFT)) & DDRC_PMLCB3_THRESHOLD_MASK) + +#define DDRC_PMLCB3_TBMULT_MASK (0x700U) +#define DDRC_PMLCB3_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB3_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TBMULT_SHIFT)) & DDRC_PMLCB3_TBMULT_MASK) + +#define DDRC_PMLCB3_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB3_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB3_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB3_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB3_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB3_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB3_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGONCNTL_SHIFT)) & DDRC_PMLCB3_TRIGONCNTL_MASK) + +#define DDRC_PMLCB3_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB3_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB3_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB3_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB3_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB3_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB3_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGONSEL_SHIFT)) & DDRC_PMLCB3_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC3 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC3_PMC3_MASK (0xFFFFFFFFU) +#define DDRC_PMC3_PMC3_SHIFT (0U) +/*! PMC3 - Event Count */ +#define DDRC_PMC3_PMC3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC3_PMC3_SHIFT)) & DDRC_PMC3_PMC3_MASK) +/*! @} */ + +/*! @name PMLCA4 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA4_BDIST_MASK (0x3FU) +#define DDRC_PMLCA4_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA4_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BDIST_SHIFT)) & DDRC_PMLCA4_BDIST_MASK) + +#define DDRC_PMLCA4_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA4_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA4_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BGRAN_SHIFT)) & DDRC_PMLCA4_BGRAN_MASK) + +#define DDRC_PMLCA4_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA4_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA4_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BSIZE_SHIFT)) & DDRC_PMLCA4_BSIZE_MASK) + +#define DDRC_PMLCA4_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA4_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA4_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_EVENT_SHIFT)) & DDRC_PMLCA4_EVENT_MASK) + +#define DDRC_PMLCA4_CE_MASK (0x4000000U) +#define DDRC_PMLCA4_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA4_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_CE_SHIFT)) & DDRC_PMLCA4_CE_MASK) + +#define DDRC_PMLCA4_FC_MASK (0x80000000U) +#define DDRC_PMLCA4_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA4_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_FC_SHIFT)) & DDRC_PMLCA4_FC_MASK) +/*! @} */ + +/*! @name PMLCB4 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB4_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB4_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB4_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_THRESHOLD_SHIFT)) & DDRC_PMLCB4_THRESHOLD_MASK) + +#define DDRC_PMLCB4_TBMULT_MASK (0x700U) +#define DDRC_PMLCB4_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB4_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TBMULT_SHIFT)) & DDRC_PMLCB4_TBMULT_MASK) + +#define DDRC_PMLCB4_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB4_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB4_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB4_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB4_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB4_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB4_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGONCNTL_SHIFT)) & DDRC_PMLCB4_TRIGONCNTL_MASK) + +#define DDRC_PMLCB4_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB4_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB4_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB4_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB4_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB4_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB4_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGONSEL_SHIFT)) & DDRC_PMLCB4_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC4 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC4_PMC4_MASK (0xFFFFFFFFU) +#define DDRC_PMC4_PMC4_SHIFT (0U) +/*! PMC4 - Event Count */ +#define DDRC_PMC4_PMC4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC4_PMC4_SHIFT)) & DDRC_PMC4_PMC4_MASK) +/*! @} */ + +/*! @name PMLCA5 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA5_BDIST_MASK (0x3FU) +#define DDRC_PMLCA5_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA5_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BDIST_SHIFT)) & DDRC_PMLCA5_BDIST_MASK) + +#define DDRC_PMLCA5_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA5_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA5_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BGRAN_SHIFT)) & DDRC_PMLCA5_BGRAN_MASK) + +#define DDRC_PMLCA5_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA5_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA5_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BSIZE_SHIFT)) & DDRC_PMLCA5_BSIZE_MASK) + +#define DDRC_PMLCA5_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA5_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA5_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_EVENT_SHIFT)) & DDRC_PMLCA5_EVENT_MASK) + +#define DDRC_PMLCA5_CE_MASK (0x4000000U) +#define DDRC_PMLCA5_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA5_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_CE_SHIFT)) & DDRC_PMLCA5_CE_MASK) + +#define DDRC_PMLCA5_FC_MASK (0x80000000U) +#define DDRC_PMLCA5_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA5_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_FC_SHIFT)) & DDRC_PMLCA5_FC_MASK) +/*! @} */ + +/*! @name PMLCB5 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB5_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB5_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB5_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_THRESHOLD_SHIFT)) & DDRC_PMLCB5_THRESHOLD_MASK) + +#define DDRC_PMLCB5_TBMULT_MASK (0x700U) +#define DDRC_PMLCB5_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB5_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TBMULT_SHIFT)) & DDRC_PMLCB5_TBMULT_MASK) + +#define DDRC_PMLCB5_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB5_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB5_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB5_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB5_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB5_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB5_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGONCNTL_SHIFT)) & DDRC_PMLCB5_TRIGONCNTL_MASK) + +#define DDRC_PMLCB5_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB5_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB5_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB5_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB5_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB5_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB5_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGONSEL_SHIFT)) & DDRC_PMLCB5_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC5 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC5_PMC5_MASK (0xFFFFFFFFU) +#define DDRC_PMC5_PMC5_SHIFT (0U) +/*! PMC5 - Event Count */ +#define DDRC_PMC5_PMC5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC5_PMC5_SHIFT)) & DDRC_PMC5_PMC5_MASK) +/*! @} */ + +/*! @name PMLCA6 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA6_BDIST_MASK (0x3FU) +#define DDRC_PMLCA6_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA6_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BDIST_SHIFT)) & DDRC_PMLCA6_BDIST_MASK) + +#define DDRC_PMLCA6_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA6_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA6_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BGRAN_SHIFT)) & DDRC_PMLCA6_BGRAN_MASK) + +#define DDRC_PMLCA6_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA6_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA6_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BSIZE_SHIFT)) & DDRC_PMLCA6_BSIZE_MASK) + +#define DDRC_PMLCA6_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA6_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA6_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_EVENT_SHIFT)) & DDRC_PMLCA6_EVENT_MASK) + +#define DDRC_PMLCA6_CE_MASK (0x4000000U) +#define DDRC_PMLCA6_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA6_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_CE_SHIFT)) & DDRC_PMLCA6_CE_MASK) + +#define DDRC_PMLCA6_FC_MASK (0x80000000U) +#define DDRC_PMLCA6_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA6_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_FC_SHIFT)) & DDRC_PMLCA6_FC_MASK) +/*! @} */ + +/*! @name PMLCB6 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB6_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB6_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB6_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_THRESHOLD_SHIFT)) & DDRC_PMLCB6_THRESHOLD_MASK) + +#define DDRC_PMLCB6_TBMULT_MASK (0x700U) +#define DDRC_PMLCB6_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB6_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TBMULT_SHIFT)) & DDRC_PMLCB6_TBMULT_MASK) + +#define DDRC_PMLCB6_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB6_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB6_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB6_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB6_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB6_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB6_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGONCNTL_SHIFT)) & DDRC_PMLCB6_TRIGONCNTL_MASK) + +#define DDRC_PMLCB6_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB6_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB6_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB6_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB6_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB6_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB6_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGONSEL_SHIFT)) & DDRC_PMLCB6_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC6 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC6_PMC6_MASK (0xFFFFFFFFU) +#define DDRC_PMC6_PMC6_SHIFT (0U) +/*! PMC6 - Event Count */ +#define DDRC_PMC6_PMC6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC6_PMC6_SHIFT)) & DDRC_PMC6_PMC6_MASK) +/*! @} */ + +/*! @name PMLCA7 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA7_BDIST_MASK (0x3FU) +#define DDRC_PMLCA7_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA7_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BDIST_SHIFT)) & DDRC_PMLCA7_BDIST_MASK) + +#define DDRC_PMLCA7_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA7_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA7_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BGRAN_SHIFT)) & DDRC_PMLCA7_BGRAN_MASK) + +#define DDRC_PMLCA7_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA7_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA7_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BSIZE_SHIFT)) & DDRC_PMLCA7_BSIZE_MASK) + +#define DDRC_PMLCA7_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA7_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA7_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_EVENT_SHIFT)) & DDRC_PMLCA7_EVENT_MASK) + +#define DDRC_PMLCA7_CE_MASK (0x4000000U) +#define DDRC_PMLCA7_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA7_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_CE_SHIFT)) & DDRC_PMLCA7_CE_MASK) + +#define DDRC_PMLCA7_FC_MASK (0x80000000U) +#define DDRC_PMLCA7_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA7_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_FC_SHIFT)) & DDRC_PMLCA7_FC_MASK) +/*! @} */ + +/*! @name PMLCB7 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB7_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB7_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB7_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_THRESHOLD_SHIFT)) & DDRC_PMLCB7_THRESHOLD_MASK) + +#define DDRC_PMLCB7_TBMULT_MASK (0x700U) +#define DDRC_PMLCB7_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB7_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TBMULT_SHIFT)) & DDRC_PMLCB7_TBMULT_MASK) + +#define DDRC_PMLCB7_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB7_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB7_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB7_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB7_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB7_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB7_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGONCNTL_SHIFT)) & DDRC_PMLCB7_TRIGONCNTL_MASK) + +#define DDRC_PMLCB7_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB7_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB7_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB7_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB7_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB7_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB7_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGONSEL_SHIFT)) & DDRC_PMLCB7_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC7 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC7_PMC7_MASK (0xFFFFFFFFU) +#define DDRC_PMC7_PMC7_SHIFT (0U) +/*! PMC7 - Event Count */ +#define DDRC_PMC7_PMC7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC7_PMC7_SHIFT)) & DDRC_PMC7_PMC7_MASK) +/*! @} */ + +/*! @name PMLCA8 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA8_BDIST_MASK (0x3FU) +#define DDRC_PMLCA8_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA8_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BDIST_SHIFT)) & DDRC_PMLCA8_BDIST_MASK) + +#define DDRC_PMLCA8_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA8_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA8_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BGRAN_SHIFT)) & DDRC_PMLCA8_BGRAN_MASK) + +#define DDRC_PMLCA8_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA8_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA8_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BSIZE_SHIFT)) & DDRC_PMLCA8_BSIZE_MASK) + +#define DDRC_PMLCA8_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA8_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA8_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_EVENT_SHIFT)) & DDRC_PMLCA8_EVENT_MASK) + +#define DDRC_PMLCA8_CE_MASK (0x4000000U) +#define DDRC_PMLCA8_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA8_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_CE_SHIFT)) & DDRC_PMLCA8_CE_MASK) + +#define DDRC_PMLCA8_FC_MASK (0x80000000U) +#define DDRC_PMLCA8_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA8_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_FC_SHIFT)) & DDRC_PMLCA8_FC_MASK) +/*! @} */ + +/*! @name PMLCB8 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB8_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB8_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB8_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_THRESHOLD_SHIFT)) & DDRC_PMLCB8_THRESHOLD_MASK) + +#define DDRC_PMLCB8_TBMULT_MASK (0x700U) +#define DDRC_PMLCB8_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB8_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TBMULT_SHIFT)) & DDRC_PMLCB8_TBMULT_MASK) + +#define DDRC_PMLCB8_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB8_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB8_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB8_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB8_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB8_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB8_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGONCNTL_SHIFT)) & DDRC_PMLCB8_TRIGONCNTL_MASK) + +#define DDRC_PMLCB8_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB8_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB8_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB8_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB8_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB8_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB8_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGONSEL_SHIFT)) & DDRC_PMLCB8_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC8 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC8_PMC8_MASK (0xFFFFFFFFU) +#define DDRC_PMC8_PMC8_SHIFT (0U) +/*! PMC8 - Event Count */ +#define DDRC_PMC8_PMC8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC8_PMC8_SHIFT)) & DDRC_PMC8_PMC8_MASK) +/*! @} */ + +/*! @name PMLCA9 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA9_BDIST_MASK (0x3FU) +#define DDRC_PMLCA9_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA9_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BDIST_SHIFT)) & DDRC_PMLCA9_BDIST_MASK) + +#define DDRC_PMLCA9_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA9_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA9_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BGRAN_SHIFT)) & DDRC_PMLCA9_BGRAN_MASK) + +#define DDRC_PMLCA9_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA9_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA9_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BSIZE_SHIFT)) & DDRC_PMLCA9_BSIZE_MASK) + +#define DDRC_PMLCA9_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA9_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA9_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_EVENT_SHIFT)) & DDRC_PMLCA9_EVENT_MASK) + +#define DDRC_PMLCA9_CE_MASK (0x4000000U) +#define DDRC_PMLCA9_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA9_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_CE_SHIFT)) & DDRC_PMLCA9_CE_MASK) + +#define DDRC_PMLCA9_FC_MASK (0x80000000U) +#define DDRC_PMLCA9_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA9_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_FC_SHIFT)) & DDRC_PMLCA9_FC_MASK) +/*! @} */ + +/*! @name PMLCB9 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB9_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB9_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB9_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_THRESHOLD_SHIFT)) & DDRC_PMLCB9_THRESHOLD_MASK) + +#define DDRC_PMLCB9_TBMULT_MASK (0x700U) +#define DDRC_PMLCB9_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB9_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TBMULT_SHIFT)) & DDRC_PMLCB9_TBMULT_MASK) + +#define DDRC_PMLCB9_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB9_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB9_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB9_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB9_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB9_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB9_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGONCNTL_SHIFT)) & DDRC_PMLCB9_TRIGONCNTL_MASK) + +#define DDRC_PMLCB9_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB9_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB9_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB9_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB9_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB9_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB9_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGONSEL_SHIFT)) & DDRC_PMLCB9_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC9 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC9_PMC9_MASK (0xFFFFFFFFU) +#define DDRC_PMC9_PMC9_SHIFT (0U) +/*! PMC9 - Event Count */ +#define DDRC_PMC9_PMC9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC9_PMC9_SHIFT)) & DDRC_PMC9_PMC9_MASK) +/*! @} */ + +/*! @name PMLCA10 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA10_BDIST_MASK (0x3FU) +#define DDRC_PMLCA10_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA10_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BDIST_SHIFT)) & DDRC_PMLCA10_BDIST_MASK) + +#define DDRC_PMLCA10_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA10_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA10_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BGRAN_SHIFT)) & DDRC_PMLCA10_BGRAN_MASK) + +#define DDRC_PMLCA10_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA10_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA10_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BSIZE_SHIFT)) & DDRC_PMLCA10_BSIZE_MASK) + +#define DDRC_PMLCA10_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA10_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA10_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_EVENT_SHIFT)) & DDRC_PMLCA10_EVENT_MASK) + +#define DDRC_PMLCA10_CE_MASK (0x4000000U) +#define DDRC_PMLCA10_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA10_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_CE_SHIFT)) & DDRC_PMLCA10_CE_MASK) + +#define DDRC_PMLCA10_FC_MASK (0x80000000U) +#define DDRC_PMLCA10_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA10_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_FC_SHIFT)) & DDRC_PMLCA10_FC_MASK) +/*! @} */ + +/*! @name PMLCB10 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB10_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB10_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB10_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_THRESHOLD_SHIFT)) & DDRC_PMLCB10_THRESHOLD_MASK) + +#define DDRC_PMLCB10_TBMULT_MASK (0x700U) +#define DDRC_PMLCB10_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB10_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TBMULT_SHIFT)) & DDRC_PMLCB10_TBMULT_MASK) + +#define DDRC_PMLCB10_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB10_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB10_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB10_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB10_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB10_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB10_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGONCNTL_SHIFT)) & DDRC_PMLCB10_TRIGONCNTL_MASK) + +#define DDRC_PMLCB10_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB10_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB10_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB10_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB10_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB10_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB10_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGONSEL_SHIFT)) & DDRC_PMLCB10_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC10 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC10_PMC10_MASK (0xFFFFFFFFU) +#define DDRC_PMC10_PMC10_SHIFT (0U) +/*! PMC10 - Event Count */ +#define DDRC_PMC10_PMC10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC10_PMC10_SHIFT)) & DDRC_PMC10_PMC10_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DDRC_Register_Masks */ + + +/*! + * @} + */ /* end of group DDRC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_DDRC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_BLK_CTRL_DDRMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_BLK_CTRL_DDRMIX.h index d10e8826e..0e158f57c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_BLK_CTRL_DDRMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_BLK_CTRL_DDRMIX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DDR_BLK_CTRL_DDRMIX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DDR_BLK_CTRL_DDRMIX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DDR_BLK_CTRL_DDRMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DDR_BLK_CTRL_DDRMIX * * CMSIS Peripheral Access Layer for DDR_BLK_CTRL_DDRMIX */ -#if !defined(DDR_BLK_CTRL_DDRMIX_H_) -#define DDR_BLK_CTRL_DDRMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DDR_BLK_CTRL_DDRMIX_H_) +#define PERI_DDR_BLK_CTRL_DDRMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -797,5 +800,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DDR_BLK_CTRL_DDRMIX_H_ */ +#endif /* PERI_DDR_BLK_CTRL_DDRMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_CMU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_CMU.h index 2723781d4..14051a688 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_CMU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_CMU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DDR_CMU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DDR_CMU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DDR_CMU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DDR_CMU * * CMSIS Peripheral Access Layer for DDR_CMU */ -#if !defined(DDR_CMU_H_) -#define DDR_CMU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DDR_CMU_H_) +#define PERI_DDR_CMU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -365,5 +368,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DDR_CMU_H_ */ +#endif /* PERI_DDR_CMU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_LSTCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_LSTCU.h index 6dae2a883..89aeaf66c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_LSTCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_LSTCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DDR_LSTCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DDR_LSTCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DDR_LSTCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DDR_LSTCU * * CMSIS Peripheral Access Layer for DDR_LSTCU */ -#if !defined(DDR_LSTCU_H_) -#define DDR_LSTCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DDR_LSTCU_H_) +#define PERI_DDR_LSTCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -399,5 +402,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DDR_LSTCU_H_ */ +#endif /* PERI_DDR_LSTCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_TCU.h index 37ac8b076..782998d4e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DDR_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DDR_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DDR_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DDR_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DDR_TCU * * CMSIS Peripheral Access Layer for DDR_TCU */ -#if !defined(DDR_TCU_H_) -#define DDR_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DDR_TCU_H_) +#define PERI_DDR_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -394,5 +397,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DDR_TCU_H_ */ +#endif /* PERI_DDR_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_BLK_CTRL_DISPLAYMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_BLK_CTRL_DISPLAYMIX.h index a7e04abf4..8f2ff2a96 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_BLK_CTRL_DISPLAYMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_BLK_CTRL_DISPLAYMIX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DISPLAY_BLK_CTRL_DISPLAYMIX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DISPLAY_BLK_CTRL_DISPLAYMIX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DISPLAY_BLK_CTRL_DISPLAYMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DISPLAY_BLK_CTRL_DISPLAYMIX * * CMSIS Peripheral Access Layer for DISPLAY_BLK_CTRL_DISPLAYMIX */ -#if !defined(DISPLAY_BLK_CTRL_DISPLAYMIX_H_) -#define DISPLAY_BLK_CTRL_DISPLAYMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DISPLAY_BLK_CTRL_DISPLAYMIX_H_) +#define PERI_DISPLAY_BLK_CTRL_DISPLAYMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -603,5 +606,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DISPLAY_BLK_CTRL_DISPLAYMIX_H_ */ +#endif /* PERI_DISPLAY_BLK_CTRL_DISPLAYMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_BLK_CTRL_LVDS.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_BLK_CTRL_LVDS.h index 451fe36fd..93c3d081f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_BLK_CTRL_LVDS.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_BLK_CTRL_LVDS.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DISPLAY_BLK_CTRL_LVDS @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DISPLAY_BLK_CTRL_LVDS.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DISPLAY_BLK_CTRL_LVDS.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DISPLAY_BLK_CTRL_LVDS * * CMSIS Peripheral Access Layer for DISPLAY_BLK_CTRL_LVDS */ -#if !defined(DISPLAY_BLK_CTRL_LVDS_H_) -#define DISPLAY_BLK_CTRL_LVDS_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DISPLAY_BLK_CTRL_LVDS_H_) +#define PERI_DISPLAY_BLK_CTRL_LVDS_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -460,5 +463,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DISPLAY_BLK_CTRL_LVDS_H_ */ +#endif /* PERI_DISPLAY_BLK_CTRL_LVDS_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_TCU.h index b0c86cade..e129a2672 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DISPLAY_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DISPLAY_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DISPLAY_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DISPLAY_TCU * * CMSIS Peripheral Access Layer for DISPLAY_TCU */ -#if !defined(DISPLAY_TCU_H_) -#define DISPLAY_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DISPLAY_TCU_H_) +#define PERI_DISPLAY_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -387,5 +390,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DISPLAY_TCU_H_ */ +#endif /* PERI_DISPLAY_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_TRDC_MGR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_TRDC_MGR.h index 951746ee5..597b2645a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_TRDC_MGR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DISPLAY_TRDC_MGR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DISPLAY_TRDC_MGR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DISPLAY_TRDC_MGR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DISPLAY_TRDC_MGR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DISPLAY_TRDC_MGR * * CMSIS Peripheral Access Layer for DISPLAY_TRDC_MGR */ -#if !defined(DISPLAY_TRDC_MGR_H_) -#define DISPLAY_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DISPLAY_TRDC_MGR_H_) +#define PERI_DISPLAY_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -135668,5 +135671,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DISPLAY_TRDC_MGR_H_ */ +#endif /* PERI_DISPLAY_TRDC_MGR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DMA.h index 5389009d3..fbf70d611 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DMA.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DMA.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DMA.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DMA * * CMSIS Peripheral Access Layer for DMA */ -#if !defined(DMA_H_) -#define DMA_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DMA_H_) +#define PERI_DMA_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1072,5 +1075,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DMA_H_ */ +#endif /* PERI_DMA_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DMA5.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DMA5.h index e3948ff62..9907c438c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DMA5.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DMA5.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA5 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DMA5.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DMA5.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DMA5 * * CMSIS Peripheral Access Layer for DMA5 */ -#if !defined(DMA5_H_) -#define DMA5_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DMA5_H_) +#define PERI_DMA5_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -681,10 +684,10 @@ typedef struct { #define DMA5_CH_CSR_DONE_MASK (0x40000000U) #define DMA5_CH_CSR_DONE_SHIFT (30U) /*! DONE - Channel Done Flag - * 0b0..Not done * 0b0..No effect - * 0b1..Done + * 0b0..Not done * 0b1..Clear the flag + * 0b1..Done */ #define DMA5_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_DONE_SHIFT)) & DMA5_CH_CSR_DONE_MASK) @@ -783,10 +786,10 @@ typedef struct { #define DMA5_CH_ES_ERR_MASK (0x80000000U) #define DMA5_CH_ES_ERR_SHIFT (31U) /*! ERR - Error in Channel Flag - * 0b0..Not occurred * 0b0..No effect - * 0b1..Occurred + * 0b0..Not occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define DMA5_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_ERR_SHIFT)) & DMA5_CH_ES_ERR_MASK) /*! @} */ @@ -1379,5 +1382,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DMA5_H_ */ +#endif /* PERI_DMA5_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DWC_USB3.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DWC_USB3.h index 9a7945b1f..f920cb283 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DWC_USB3.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DWC_USB3.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DWC_usb3 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file DWC_usb3.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_DWC_usb3.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for DWC_usb3 * * CMSIS Peripheral Access Layer for DWC_usb3 */ -#if !defined(DWC_usb3_H_) -#define DWC_usb3_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_DWC_USB3_H_) +#define PERI_DWC_USB3_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -244,7 +247,6 @@ typedef struct { __I uint32_t HCCPARAMS2; /**< Host Controller Capability Parameters 2, offset: 0x1C */ __IO uint32_t USBCMD; /**< USB Command, offset: 0x20 */ __IO uint32_t USBSTS; /**< USB Status, offset: 0x24 */ -#undef PAGESIZE __I uint32_t PAGESIZE; /**< Page Size, offset: 0x28 */ uint8_t RESERVED_0[8]; __IO uint32_t DNCTRL; /**< Device Notification, offset: 0x34 */ @@ -4520,5 +4522,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* DWC_usb3_H_ */ +#endif /* PERI_DWC_USB3_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ECAT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ECAT.h index 0a6e1b4e3..c6714c8e9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ECAT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ECAT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ECAT @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ECAT.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ECAT.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ECAT * * CMSIS Peripheral Access Layer for ECAT */ -#if !defined(ECAT_H_) -#define ECAT_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ECAT_H_) +#define PERI_ECAT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -4064,5 +4067,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ECAT_H_ */ +#endif /* PERI_ECAT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENDAT2P2.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENDAT2P2.h index bdda4cee0..3e10b1411 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENDAT2P2.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENDAT2P2.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENDAT2P2 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENDAT2P2.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENDAT2P2.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENDAT2P2 * * CMSIS Peripheral Access Layer for ENDAT2P2 */ -#if !defined(ENDAT2P2_H_) -#define ENDAT2P2_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENDAT2P2_H_) +#define PERI_ENDAT2P2_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -986,5 +989,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENDAT2P2_H_ */ +#endif /* PERI_ENDAT2P2_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENDAT3.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENDAT3.h index a11e64de7..522d49312 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENDAT3.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENDAT3.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENDAT3 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENDAT3.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENDAT3.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENDAT3 * * CMSIS Peripheral Access Layer for ENDAT3 */ -#if !defined(ENDAT3_H_) -#define ENDAT3_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENDAT3_H_) +#define PERI_ENDAT3_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1013,5 +1016,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENDAT3_H_ */ +#endif /* PERI_ENDAT3_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_COMMON.h index a48e28eb7..9a25bac6e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_COMMON.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_COMMON @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENETC_COMMON.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENETC_COMMON.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENETC_COMMON * * CMSIS Peripheral Access Layer for ENETC_COMMON */ -#if !defined(ENETC_COMMON_H_) -#define ENETC_COMMON_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENETC_COMMON_H_) +#define PERI_ENETC_COMMON_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1586,5 +1589,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENETC_COMMON_H_ */ +#endif /* PERI_ENETC_COMMON_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_GLOBAL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_GLOBAL.h index dd071de5d..4b883a1b9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_GLOBAL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_GLOBAL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_GLOBAL @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENETC_GLOBAL.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENETC_GLOBAL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENETC_GLOBAL * * CMSIS Peripheral Access Layer for ENETC_GLOBAL */ -#if !defined(ENETC_GLOBAL_H_) -#define ENETC_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENETC_GLOBAL_H_) +#define PERI_ENETC_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -784,5 +787,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENETC_GLOBAL_H_ */ +#endif /* PERI_ENETC_GLOBAL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PCI_TYPE0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PCI_TYPE0.h index 2024feccb..4c9b87b37 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PCI_TYPE0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PCI_TYPE0.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_PCI_TYPE0 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENETC_PCI_TYPE0.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENETC_PCI_TYPE0.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENETC_PCI_TYPE0 * * CMSIS Peripheral Access Layer for ENETC_PCI_TYPE0 */ -#if !defined(ENETC_PCI_TYPE0_H_) -#define ENETC_PCI_TYPE0_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENETC_PCI_TYPE0_H_) +#define PERI_ENETC_PCI_TYPE0_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1164,5 +1167,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENETC_PCI_TYPE0_H_ */ +#endif /* PERI_ENETC_PCI_TYPE0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PF_EMDIO.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PF_EMDIO.h index 697dd7e95..4757a543e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PF_EMDIO.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PF_EMDIO.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_PF_EMDIO @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENETC_PF_EMDIO.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENETC_PF_EMDIO.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENETC_PF_EMDIO * * CMSIS Peripheral Access Layer for ENETC_PF_EMDIO */ -#if !defined(ENETC_PF_EMDIO_H_) -#define ENETC_PF_EMDIO_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENETC_PF_EMDIO_H_) +#define PERI_ENETC_PF_EMDIO_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -571,5 +574,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENETC_PF_EMDIO_H_ */ +#endif /* PERI_ENETC_PF_EMDIO_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PF_TMR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PF_TMR.h index 0ee4f9ec9..292d555d5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PF_TMR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PF_TMR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_PF_TMR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENETC_PF_TMR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENETC_PF_TMR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENETC_PF_TMR * * CMSIS Peripheral Access Layer for ENETC_PF_TMR */ -#if !defined(ENETC_PF_TMR_H_) -#define ENETC_PF_TMR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENETC_PF_TMR_H_) +#define PERI_ENETC_PF_TMR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -905,5 +908,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENETC_PF_TMR_H_ */ +#endif /* PERI_ENETC_PF_TMR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PORT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PORT.h index 89a3141a9..b44b6a682 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PORT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_PORT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_PORT @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENETC_PORT.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENETC_PORT.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENETC_PORT * * CMSIS Peripheral Access Layer for ENETC_PORT */ -#if !defined(ENETC_PORT_H_) -#define ENETC_PORT_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENETC_PORT_H_) +#define PERI_ENETC_PORT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -986,5 +989,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENETC_PORT_H_ */ +#endif /* PERI_ENETC_PORT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_SI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_SI.h index ed6ce20b8..8e1efef58 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_SI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_SI.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_SI @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENETC_SI.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENETC_SI.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENETC_SI * * CMSIS Peripheral Access Layer for ENETC_SI */ -#if !defined(ENETC_SI_H_) -#define ENETC_SI_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENETC_SI_H_) +#define PERI_ENETC_SI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2615,5 +2618,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENETC_SI_H_ */ +#endif /* PERI_ENETC_SI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_VF_PCI_TYPE0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_VF_PCI_TYPE0.h index dcb61ac86..aeae63d42 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_VF_PCI_TYPE0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENETC_VF_PCI_TYPE0.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_VF_PCI_TYPE0 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENETC_VF_PCI_TYPE0.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENETC_VF_PCI_TYPE0.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENETC_VF_PCI_TYPE0 * * CMSIS Peripheral Access Layer for ENETC_VF_PCI_TYPE0 */ -#if !defined(ENETC_VF_PCI_TYPE0_H_) -#define ENETC_VF_PCI_TYPE0_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENETC_VF_PCI_TYPE0_H_) +#define PERI_ENETC_VF_PCI_TYPE0_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -841,5 +844,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENETC_VF_PCI_TYPE0_H_ */ +#endif /* PERI_ENETC_VF_PCI_TYPE0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENET_PHY_CTRL_EX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENET_PHY_CTRL_EX.h index a352643e4..2f961a4f8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENET_PHY_CTRL_EX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENET_PHY_CTRL_EX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET_PHY_CTRL_EX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENET_PHY_CTRL_EX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENET_PHY_CTRL_EX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENET_PHY_CTRL_EX * * CMSIS Peripheral Access Layer for ENET_PHY_CTRL_EX */ -#if !defined(ENET_PHY_CTRL_EX_H_) -#define ENET_PHY_CTRL_EX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENET_PHY_CTRL_EX_H_) +#define PERI_ENET_PHY_CTRL_EX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -715,5 +718,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENET_PHY_CTRL_EX_H_ */ +#endif /* PERI_ENET_PHY_CTRL_EX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENET_PHY_MAC_ADAPTER.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENET_PHY_MAC_ADAPTER.h index f215e767a..01b00e47f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENET_PHY_MAC_ADAPTER.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_ENET_PHY_MAC_ADAPTER.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET_PHY_MAC_ADAPTER @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ENET_PHY_MAC_ADAPTER.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ENET_PHY_MAC_ADAPTER.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ENET_PHY_MAC_ADAPTER * * CMSIS Peripheral Access Layer for ENET_PHY_MAC_ADAPTER */ -#if !defined(ENET_PHY_MAC_ADAPTER_H_) -#define ENET_PHY_MAC_ADAPTER_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_ENET_PHY_MAC_ADAPTER_H_) +#define PERI_ENET_PHY_MAC_ADAPTER_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -368,5 +371,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ENET_PHY_MAC_ADAPTER_H_ */ +#endif /* PERI_ENET_PHY_MAC_ADAPTER_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_EQDC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_EQDC.h index 7e28a4e6c..18320ae00 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_EQDC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_EQDC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for EQDC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file EQDC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_EQDC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for EQDC * * CMSIS Peripheral Access Layer for EQDC */ -#if !defined(EQDC_H_) -#define EQDC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_EQDC_H_) +#define PERI_EQDC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1136,5 +1139,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* EQDC_H_ */ +#endif /* PERI_EQDC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_EWM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_EWM.h index 42734ca22..8a3adf260 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_EWM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_EWM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for EWM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file EWM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_EWM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for EWM * * CMSIS Peripheral Access Layer for EWM */ -#if !defined(EWM_H_) -#define EWM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_EWM_H_) +#define PERI_EWM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* EWM_H_ */ +#endif /* PERI_EWM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_FLEXIO.h index 3666caa10..5aa29b3ce 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_FLEXIO.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file FLEXIO.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_FLEXIO.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for FLEXIO * * CMSIS Peripheral Access Layer for FLEXIO */ -#if !defined(FLEXIO_H_) -#define FLEXIO_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_FLEXIO_H_) +#define PERI_FLEXIO_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -424,8 +427,8 @@ typedef struct { /*! SSF - Shifter Status Flag * 0b00000000..Clear * 0b00000000..No effect - * 0b00000001..Set * 0b00000001..Clear the flag + * 0b00000001..Set */ #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) /*! @} */ @@ -438,8 +441,8 @@ typedef struct { /*! SEF - Shifter Error Flag * 0b00000000..Clear * 0b00000000..No effect - * 0b00000001..Set * 0b00000001..Clear the flag + * 0b00000001..Set */ #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) /*! @} */ @@ -452,8 +455,8 @@ typedef struct { /*! TSF - Timer Status Flag * 0b00000000..Clear * 0b00000000..No effect - * 0b00000001..Set * 0b00000001..Clear the flag + * 0b00000001..Set */ #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) /*! @} */ @@ -520,8 +523,8 @@ typedef struct { /*! ETSF - External Trigger Status Flag * 0b0000..Clear * 0b0000..No effect - * 0b0001..Set * 0b0001..Clear the flag + * 0b0001..Set */ #define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) /*! @} */ @@ -543,8 +546,8 @@ typedef struct { /*! PSF - Pin Status Flag * 0b0000000000000000..Clear * 0b0000000000000000..No effect - * 0b0000000000000001..Set * 0b0000000000000001..Clear the flag + * 0b0000000000000001..Set */ #define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) /*! @} */ @@ -1043,5 +1046,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* FLEXIO_H_ */ +#endif /* PERI_FLEXIO_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_FRO.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_FRO.h index c176df601..454c96911 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_FRO.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_FRO.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for FRO @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file FRO.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_FRO.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for FRO * * CMSIS Peripheral Access Layer for FRO */ -#if !defined(FRO_H_) -#define FRO_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_FRO_H_) +#define PERI_FRO_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -552,5 +555,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* FRO_H_ */ +#endif /* PERI_FRO_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GLITCHFILTER.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GLITCHFILTER.h index ff6b755ee..45d8fd3da 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GLITCHFILTER.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GLITCHFILTER.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for GLITCHFILTER @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file GLITCHFILTER.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_GLITCHFILTER.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for GLITCHFILTER * * CMSIS Peripheral Access Layer for GLITCHFILTER */ -#if !defined(GLITCHFILTER_H_) -#define GLITCHFILTER_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_GLITCHFILTER_H_) +#define PERI_GLITCHFILTER_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -468,5 +471,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* GLITCHFILTER_H_ */ +#endif /* PERI_GLITCHFILTER_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPC_CPU_CTRL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPC_CPU_CTRL.h index 4c64fa833..d901256f0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPC_CPU_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPC_CPU_CTRL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_CPU_CTRL @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file GPC_CPU_CTRL.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_GPC_CPU_CTRL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for GPC_CPU_CTRL * * CMSIS Peripheral Access Layer for GPC_CPU_CTRL */ -#if !defined(GPC_CPU_CTRL_H_) -#define GPC_CPU_CTRL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_GPC_CPU_CTRL_H_) +#define PERI_GPC_CPU_CTRL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -869,5 +872,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* GPC_CPU_CTRL_H_ */ +#endif /* PERI_GPC_CPU_CTRL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPC_GLOBAL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPC_GLOBAL.h index 3375ef7c9..d3565b506 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPC_GLOBAL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPC_GLOBAL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_GLOBAL @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file GPC_GLOBAL.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_GPC_GLOBAL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for GPC_GLOBAL * * CMSIS Peripheral Access Layer for GPC_GLOBAL */ -#if !defined(GPC_GLOBAL_H_) -#define GPC_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_GPC_GLOBAL_H_) +#define PERI_GPC_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -472,5 +475,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* GPC_GLOBAL_H_ */ +#endif /* PERI_GPC_GLOBAL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPT.h index 10778bbb9..b3d213ad0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_GPT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPT @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file GPT.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_GPT.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for GPT * * CMSIS Peripheral Access Layer for GPT */ -#if !defined(GPT_H_) -#define GPT_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_GPT_H_) +#define PERI_GPT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -606,5 +609,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* GPT_H_ */ +#endif /* PERI_GPT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HIPERFACE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HIPERFACE.h index a21466672..3005758e1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HIPERFACE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HIPERFACE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for HIPERFACE @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file HIPERFACE.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_HIPERFACE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for HIPERFACE * * CMSIS Peripheral Access Layer for HIPERFACE */ -#if !defined(HIPERFACE_H_) -#define HIPERFACE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_HIPERFACE_H_) +#define PERI_HIPERFACE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1807,5 +1810,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* HIPERFACE_H_ */ +#endif /* PERI_HIPERFACE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_BLK_CTRL_HSIOMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_BLK_CTRL_HSIOMIX.h index dee841fd4..d2ae84903 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_BLK_CTRL_HSIOMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_BLK_CTRL_HSIOMIX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for HSIO_BLK_CTRL_HSIOMIX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file HSIO_BLK_CTRL_HSIOMIX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_HSIO_BLK_CTRL_HSIOMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for HSIO_BLK_CTRL_HSIOMIX * * CMSIS Peripheral Access Layer for HSIO_BLK_CTRL_HSIOMIX */ -#if !defined(HSIO_BLK_CTRL_HSIOMIX_H_) -#define HSIO_BLK_CTRL_HSIOMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_HSIO_BLK_CTRL_HSIOMIX_H_) +#define PERI_HSIO_BLK_CTRL_HSIOMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1432,5 +1435,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* HSIO_BLK_CTRL_HSIOMIX_H_ */ +#endif /* PERI_HSIO_BLK_CTRL_HSIOMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_TCU.h index 7524d52d0..adf076b28 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for HSIO_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file HSIO_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_HSIO_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for HSIO_TCU * * CMSIS Peripheral Access Layer for HSIO_TCU */ -#if !defined(HSIO_TCU_H_) -#define HSIO_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_HSIO_TCU_H_) +#define PERI_HSIO_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -644,5 +647,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* HSIO_TCU_H_ */ +#endif /* PERI_HSIO_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_TRDC_MGR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_TRDC_MGR.h index 3f9d6b5b6..8daca22a0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_TRDC_MGR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_HSIO_TRDC_MGR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for HSIO_TRDC_MGR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file HSIO_TRDC_MGR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_HSIO_TRDC_MGR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for HSIO_TRDC_MGR * * CMSIS Peripheral Access Layer for HSIO_TRDC_MGR */ -#if !defined(HSIO_TRDC_MGR_H_) -#define HSIO_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_HSIO_TRDC_MGR_H_) +#define PERI_HSIO_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -91480,5 +91483,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* HSIO_TRDC_MGR_H_ */ +#endif /* PERI_HSIO_TRDC_MGR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_I2S.h index f624bc4f2..b2b985125 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_I2S.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file I2S.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_I2S.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for I2S * * CMSIS Peripheral Access Layer for I2S */ -#if !defined(I2S_H_) -#define I2S_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_I2S_H_) +#define PERI_I2S_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -399,30 +402,30 @@ typedef struct { #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) @@ -892,30 +895,30 @@ typedef struct { #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Receive overflow detected + * 0b0..No error * 0b1..Clear the flag + * 0b1..Receive overflow detected */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) @@ -1383,5 +1386,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* I2S_H_ */ +#endif /* PERI_I2S_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_I3C.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_I3C.h index b61770bb9..42ad5da83 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_I3C.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_I3C.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for I3C @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file I3C.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_I3C.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for I3C * * CMSIS Peripheral Access Layer for I3C */ -#if !defined(I3C_H_) -#define I3C_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_I3C_H_) +#define PERI_I3C_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -516,10 +519,10 @@ typedef struct { #define I3C_SSTATUS_START_MASK (0x100U) #define I3C_SSTATUS_START_SHIFT (8U) /*! START - Start Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) @@ -528,8 +531,8 @@ typedef struct { /*! MATCHED - Matched Flag * 0b0..Header not matched * 0b0..No effect - * 0b1..Header matched * 0b1..Clear the flag + * 0b1..Header matched */ #define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) @@ -538,8 +541,8 @@ typedef struct { /*! STOP - Stop Flag * 0b0..No Stopped state detected * 0b0..No effect - * 0b1..Stopped state detected * 0b1..Clear the flag + * 0b1..Stopped state detected */ #define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) @@ -564,8 +567,8 @@ typedef struct { /*! DACHG - Dynamic Address Change Flag * 0b0..No DA change detected * 0b0..No effect - * 0b1..DA change detected * 0b1..Clear the flag + * 0b1..DA change detected */ #define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) @@ -589,8 +592,8 @@ typedef struct { /*! HDRMATCH - High Data Rate Command Match Flag * 0b0..Did not match * 0b0..No effect - * 0b1..Matched the I3C dynamic address * 0b1..Clear the flag + * 0b1..Matched the I3C dynamic address */ #define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) @@ -607,10 +610,10 @@ typedef struct { #define I3C_SSTATUS_EVENT_MASK (0x40000U) #define I3C_SSTATUS_EVENT_SHIFT (18U) /*! EVENT - Event Flag - * 0b0..No event occurred * 0b0..No effect - * 0b1..IBI, CR, or HJ occurred + * 0b0..No event occurred * 0b1..Clear the flag + * 0b1..IBI, CR, or HJ occurred */ #define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) @@ -955,50 +958,50 @@ typedef struct { #define I3C_SERRWARN_ORUN_MASK (0x1U) #define I3C_SERRWARN_ORUN_SHIFT (0U) /*! ORUN - Overrun Error Flag - * 0b0..No overrun error * 0b0..No effect - * 0b1..Overrun error + * 0b0..No overrun error * 0b1..Clear the flag + * 0b1..Overrun error */ #define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) #define I3C_SERRWARN_URUN_MASK (0x2U) #define I3C_SERRWARN_URUN_SHIFT (1U) /*! URUN - Underrun Error Flag - * 0b0..No underrun error * 0b0..No effect - * 0b1..Underrun error + * 0b0..No underrun error * 0b1..Clear the flag + * 0b1..Underrun error */ #define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) #define I3C_SERRWARN_URUNNACK_MASK (0x4U) #define I3C_SERRWARN_URUNNACK_SHIFT (2U) /*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error Flag - * 0b0..No underrun; not acknowledged error * 0b0..No effect - * 0b1..Underrun; not acknowledged error + * 0b0..No underrun; not acknowledged error * 0b1..Clear the flag + * 0b1..Underrun; not acknowledged error */ #define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) #define I3C_SERRWARN_TERM_MASK (0x8U) #define I3C_SERRWARN_TERM_SHIFT (3U) /*! TERM - Terminated Error Flag - * 0b0..No terminated error * 0b0..No effect - * 0b1..Terminated error + * 0b0..No terminated error * 0b1..Clear the flag + * 0b1..Terminated error */ #define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) #define I3C_SERRWARN_INVSTART_MASK (0x10U) #define I3C_SERRWARN_INVSTART_SHIFT (4U) /*! INVSTART - Invalid Start Error Flag - * 0b0..No invalid start error * 0b0..No effect - * 0b1..Invalid start error + * 0b0..No invalid start error * 0b1..Clear the flag + * 0b1..Invalid start error */ #define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) @@ -1007,8 +1010,8 @@ typedef struct { /*! SPAR - SDR Parity Error Flag * 0b0..No SDR parity error * 0b0..No effect - * 0b1..SDR parity error * 0b1..Clear the flag + * 0b1..SDR parity error */ #define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) @@ -1017,8 +1020,8 @@ typedef struct { /*! HPAR - HDR Parity Error Flag * 0b0..No HDR parity error * 0b0..No effect - * 0b1..HDR parity error * 0b1..Clear the flag + * 0b1..HDR parity error */ #define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) @@ -1027,8 +1030,8 @@ typedef struct { /*! HCRC - HDR-DDR CRC Error Flag * 0b0..No HDR-DDR CRC error occurred * 0b0..No effect - * 0b1..HDR-DDR CRC error occurred * 0b1..Clear the flag + * 0b1..HDR-DDR CRC error occurred */ #define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) @@ -1037,28 +1040,28 @@ typedef struct { /*! S0S1 - TE0 or TE1 Error Flag * 0b0..No TE0 or TE1 error occurred * 0b0..No effect - * 0b1..TE0 or TE1 error occurred * 0b1..Clear the flag + * 0b1..TE0 or TE1 error occurred */ #define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) #define I3C_SERRWARN_OREAD_MASK (0x10000U) #define I3C_SERRWARN_OREAD_SHIFT (16U) /*! OREAD - Over-Read Error Flag - * 0b0..No over-read error * 0b0..No effect - * 0b1..Over-read error + * 0b0..No over-read error * 0b1..Clear the flag + * 0b1..Over-read error */ #define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) #define I3C_SERRWARN_OWRITE_MASK (0x20000U) #define I3C_SERRWARN_OWRITE_SHIFT (17U) /*! OWRITE - Over-Write Error Flag - * 0b0..No overwrite error * 0b0..No effect - * 0b1..Overwrite error + * 0b0..No overwrite error * 0b1..Clear the flag + * 0b1..Overwrite error */ #define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) /*! @} */ @@ -1735,30 +1738,30 @@ typedef struct { #define I3C_MSTATUS_SLVSTART_MASK (0x100U) #define I3C_MSTATUS_SLVSTART_SHIFT (8U) /*! SLVSTART - Target Start Flag - * 0b0..Target not requesting START * 0b0..No effect - * 0b1..Target requesting START + * 0b0..Target not requesting START * 0b1..Clear the flag + * 0b1..Target requesting START */ #define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) #define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) #define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - Controller Control Done Flag - * 0b0..Not done * 0b0..No effect - * 0b1..Done + * 0b0..Not done * 0b1..Clear the flag + * 0b1..Done */ #define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) #define I3C_MSTATUS_COMPLETE_MASK (0x400U) #define I3C_MSTATUS_COMPLETE_SHIFT (10U) /*! COMPLETE - Complete Flag - * 0b0..Not complete * 0b0..No effect - * 0b1..Complete + * 0b0..Not complete * 0b1..Clear the flag + * 0b1..Complete */ #define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) @@ -1783,8 +1786,8 @@ typedef struct { /*! IBIWON - In-Band Interrupt (IBI) Won Flag * 0b0..No IBI arbitration won * 0b0..No effect - * 0b1..IBI arbitration won * 0b1..Clear the flag + * 0b1..IBI arbitration won */ #define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) @@ -1799,10 +1802,10 @@ typedef struct { #define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) #define I3C_MSTATUS_NOWMASTER_SHIFT (19U) /*! NOWMASTER - Module is now Controller Flag - * 0b0..Not a controller * 0b0..No effect - * 0b1..Controller + * 0b0..Not a controller * 0b1..Clear the flag + * 0b1..Controller */ #define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) @@ -1930,8 +1933,8 @@ typedef struct { /*! SLVSTART - SLVSTART Interrupt Enable Clear Flag * 0b0..No effect * 0b0..No effect - * 0b1..Interrupt enable cleared * 0b1..Clear the flag + * 0b1..Interrupt enable cleared */ #define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) @@ -1940,8 +1943,8 @@ typedef struct { /*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear Flag * 0b0..No effect * 0b0..No effect - * 0b1..Interrupt enable cleared * 0b1..Clear the flag + * 0b1..Interrupt enable cleared */ #define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) @@ -1950,8 +1953,8 @@ typedef struct { /*! COMPLETE - COMPLETE Interrupt Enable Clear Flag * 0b0..No effect * 0b0..No effect - * 0b1..Interrupt enable cleared * 0b1..Clear the flag + * 0b1..Interrupt enable cleared */ #define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) @@ -1960,8 +1963,8 @@ typedef struct { /*! RXPEND - RXPEND Interrupt Enable Clear Flag * 0b0..No effect * 0b0..No effect - * 0b1..Interrupt enable cleared * 0b1..Clear the flag + * 0b1..Interrupt enable cleared */ #define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) @@ -1970,8 +1973,8 @@ typedef struct { /*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear Flag * 0b0..No effect * 0b0..No effect - * 0b1..Interrupt enable cleared * 0b1..Clear the flag + * 0b1..Interrupt enable cleared */ #define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) @@ -1980,8 +1983,8 @@ typedef struct { /*! IBIWON - IBIWON Interrupt Enable Clear Flag * 0b0..No effect * 0b0..No effect - * 0b1..Interrupt enable cleared * 0b1..Clear the flag + * 0b1..Interrupt enable cleared */ #define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) @@ -1990,8 +1993,8 @@ typedef struct { /*! ERRWARN - ERRWARN Interrupt Enable Clear Flag * 0b0..No effect * 0b0..No effect - * 0b1..Interrupt enable cleared * 0b1..Clear the flag + * 0b1..Interrupt enable cleared */ #define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) @@ -2000,8 +2003,8 @@ typedef struct { /*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear Flag * 0b0..No effect * 0b0..No effect - * 0b1..Interrupt enable cleared * 0b1..Clear the flag + * 0b1..Interrupt enable cleared */ #define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) /*! @} */ @@ -2077,110 +2080,110 @@ typedef struct { #define I3C_MERRWARN_URUN_MASK (0x2U) #define I3C_MERRWARN_URUN_SHIFT (1U) /*! URUN - Underrun Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) #define I3C_MERRWARN_NACK_MASK (0x4U) #define I3C_MERRWARN_NACK_SHIFT (2U) /*! NACK - Not Acknowledge Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) #define I3C_MERRWARN_WRABT_MASK (0x8U) #define I3C_MERRWARN_WRABT_SHIFT (3U) /*! WRABT - Write Abort Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) #define I3C_MERRWARN_TERM_MASK (0x10U) #define I3C_MERRWARN_TERM_SHIFT (4U) /*! TERM - Terminate Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) #define I3C_MERRWARN_HPAR_MASK (0x200U) #define I3C_MERRWARN_HPAR_SHIFT (9U) /*! HPAR - High Data Rate Parity Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) #define I3C_MERRWARN_HCRC_MASK (0x400U) #define I3C_MERRWARN_HCRC_SHIFT (10U) /*! HCRC - High Data Rate CRC Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) #define I3C_MERRWARN_OREAD_MASK (0x10000U) #define I3C_MERRWARN_OREAD_SHIFT (16U) /*! OREAD - Overread Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) #define I3C_MERRWARN_OWRITE_MASK (0x20000U) #define I3C_MERRWARN_OWRITE_SHIFT (17U) /*! OWRITE - Overwrite Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) #define I3C_MERRWARN_MSGERR_MASK (0x40000U) #define I3C_MERRWARN_MSGERR_SHIFT (18U) /*! MSGERR - Message Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) #define I3C_MERRWARN_INVREQ_MASK (0x80000U) #define I3C_MERRWARN_INVREQ_SHIFT (19U) /*! INVREQ - Invalid Request Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) #define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) #define I3C_MERRWARN_TIMEOUT_SHIFT (20U) /*! TIMEOUT - Timeout Error Flag - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) /*! @} */ @@ -2853,5 +2856,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* I3C_H_ */ +#endif /* PERI_I3C_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_IERB.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_IERB.h index 5ce092436..b73f58231 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_IERB.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_IERB.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ieprc_ierb @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ieprc_ierb.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ieprc_ierb.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ieprc_ierb * * CMSIS Peripheral Access Layer for ieprc_ierb */ -#if !defined(ieprc_ierb_H_) -#define ieprc_ierb_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_IEPRC_IERB_H_) +#define PERI_IEPRC_IERB_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -358,5 +361,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ieprc_ierb_H_ */ +#endif /* PERI_IEPRC_IERB_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_PCI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_PCI.h index 56917dbab..9a16e4d8f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_PCI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_PCI.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ieprc_pci @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ieprc_pci.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ieprc_pci.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ieprc_pci * * CMSIS Peripheral Access Layer for ieprc_pci */ -#if !defined(ieprc_pci_H_) -#define ieprc_pci_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_IEPRC_PCI_H_) +#define PERI_IEPRC_PCI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -619,5 +622,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ieprc_pci_H_ */ +#endif /* PERI_IEPRC_PCI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_PRB.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_PRB.h index 3c84c7445..ec1d916eb 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_PRB.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IEPRC_PRB.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ieprc_prb @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file ieprc_prb.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_ieprc_prb.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for ieprc_prb * * CMSIS Peripheral Access Layer for ieprc_prb */ -#if !defined(ieprc_prb_H_) -#define ieprc_prb_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_IEPRC_PRB_H_) +#define PERI_IEPRC_PRB_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -304,5 +307,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* ieprc_prb_H_ */ +#endif /* PERI_IEPRC_PRB_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IOMUXC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IOMUXC.h index ad9fe80b8..14db71b26 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IOMUXC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IOMUXC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file IOMUXC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_IOMUXC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for IOMUXC * * CMSIS Peripheral Access Layer for IOMUXC */ -#if !defined(IOMUXC_H_) -#define IOMUXC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_IOMUXC_H_) +#define PERI_IOMUXC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -483,5 +486,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* IOMUXC_H_ */ +#endif /* PERI_IOMUXC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IOMUXC_GPR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IOMUXC_GPR.h index 91cb51668..c3ecebd58 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IOMUXC_GPR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IOMUXC_GPR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_GPR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file IOMUXC_GPR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_IOMUXC_GPR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for IOMUXC_GPR * * CMSIS Peripheral Access Layer for IOMUXC_GPR */ -#if !defined(IOMUXC_GPR_H_) -#define IOMUXC_GPR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_IOMUXC_GPR_H_) +#define PERI_IOMUXC_GPR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -282,5 +285,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* IOMUXC_GPR_H_ */ +#endif /* PERI_IOMUXC_GPR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IRQSTEER.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IRQSTEER.h index 977fe7a4d..62c7c18ca 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IRQSTEER.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IRQSTEER.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IRQSTEER @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file IRQSTEER.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_IRQSTEER.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for IRQSTEER * * CMSIS Peripheral Access Layer for IRQSTEER */ -#if !defined(IRQSTEER_H_) -#define IRQSTEER_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_IRQSTEER_H_) +#define PERI_IRQSTEER_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* IRQSTEER_H_ */ +#endif /* PERI_IRQSTEER_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IRQSTEERA55.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IRQSTEERA55.h index 076969d5e..ee6a2fea0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IRQSTEERA55.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_IRQSTEERA55.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IRQSTEERA55 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file IRQSTEERA55.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_IRQSTEERA55.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for IRQSTEERA55 * * CMSIS Peripheral Access Layer for IRQSTEERA55 */ -#if !defined(IRQSTEERA55_H_) -#define IRQSTEERA55_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_IRQSTEERA55_H_) +#define PERI_IRQSTEERA55_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -334,5 +337,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* IRQSTEERA55_H_ */ +#endif /* PERI_IRQSTEERA55_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPI2C.h index f458a1907..58eb99fd6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPI2C.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPI2C.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_LPI2C.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPI2C * * CMSIS Peripheral Access Layer for LPI2C */ -#if !defined(LPI2C_H_) -#define LPI2C_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPI2C_H_) +#define PERI_LPI2C_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -401,8 +404,8 @@ typedef struct { /*! EPF - End Packet Flag * 0b0..No Stop or repeated Start generated * 0b0..No effect - * 0b1..Stop or repeated Start generated * 0b1..Clear the flag + * 0b1..Stop or repeated Start generated */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) @@ -411,18 +414,18 @@ typedef struct { /*! SDF - Stop Detect Flag * 0b0..No Stop condition generated * 0b0..No effect - * 0b1..Stop condition generated * 0b1..Clear the flag + * 0b1..Stop condition generated */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag - * 0b0..No unexpected NACK detected * 0b0..No effect - * 0b1..Unexpected NACK detected + * 0b0..No unexpected NACK detected * 0b1..Clear the flag + * 0b1..Unexpected NACK detected */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) @@ -431,8 +434,8 @@ typedef struct { /*! ALF - Arbitration Lost Flag * 0b0..Controller did not lose arbitration * 0b0..No effect - * 0b1..Controller lost arbitration * 0b1..Clear the flag + * 0b1..Controller lost arbitration */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) @@ -441,18 +444,18 @@ typedef struct { /*! FEF - FIFO Error Flag * 0b0..No FIFO error * 0b0..No effect - * 0b1..FIFO error * 0b1..Clear the flag + * 0b1..FIFO error */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag - * 0b0..Pin low timeout did not occur * 0b0..No effect - * 0b1..Pin low timeout occurred + * 0b0..Pin low timeout did not occur * 0b1..Clear the flag + * 0b1..Pin low timeout occurred */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) @@ -461,18 +464,18 @@ typedef struct { /*! DMF - Data Match Flag * 0b0..Matching data not received * 0b0..No effect - * 0b1..Matching data received * 0b1..Clear the flag + * 0b1..Matching data received */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_STF_MASK (0x8000U) #define LPI2C_MSR_STF_SHIFT (15U) /*! STF - Start Flag - * 0b0..Start condition not detected * 0b0..No effect - * 0b1..Start condition detected + * 0b0..Start condition not detected * 0b1..Clear the flag + * 0b1..Start condition detected */ #define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) @@ -1008,10 +1011,10 @@ typedef struct { #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) /*! RSF - Repeated Start Flag - * 0b0..No repeated Start detected * 0b0..No effect - * 0b1..Repeated Start detected + * 0b0..No repeated Start detected * 0b1..Clear the flag + * 0b1..Repeated Start detected */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) @@ -1020,8 +1023,8 @@ typedef struct { /*! SDF - Stop Detect Flag * 0b0..No Stop detected * 0b0..No effect - * 0b1..Stop detected * 0b1..Clear the flag + * 0b1..Stop detected */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) @@ -1040,8 +1043,8 @@ typedef struct { /*! FEF - FIFO Error Flag * 0b0..No FIFO error * 0b0..No effect - * 0b1..FIFO error * 0b1..Clear the flag + * 0b1..FIFO error */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) @@ -1596,5 +1599,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPI2C_H_ */ +#endif /* PERI_LPI2C_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPIT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPIT.h index b4efb76ee..af2a4dc7d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPIT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPIT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPIT @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPIT.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_LPIT.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPIT * * CMSIS Peripheral Access Layer for LPIT */ -#if !defined(LPIT_H_) -#define LPIT_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPIT_H_) +#define PERI_LPIT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -330,40 +333,40 @@ typedef struct { #define LPIT_MSR_TIF0_MASK (0x1U) #define LPIT_MSR_TIF0_SHIFT (0U) /*! TIF0 - Channel 0 Timer Interrupt Flag - * 0b0..Not timed out * 0b0..No effect - * 0b1..Timed out + * 0b0..Not timed out * 0b1..Clear the flag + * 0b1..Timed out */ #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) #define LPIT_MSR_TIF1_MASK (0x2U) #define LPIT_MSR_TIF1_SHIFT (1U) /*! TIF1 - Channel 1 Timer Interrupt Flag - * 0b0..Not timed out * 0b0..No effect - * 0b1..Timed out + * 0b0..Not timed out * 0b1..Clear the flag + * 0b1..Timed out */ #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) #define LPIT_MSR_TIF2_MASK (0x4U) #define LPIT_MSR_TIF2_SHIFT (2U) /*! TIF2 - Channel 2 Timer Interrupt Flag - * 0b0..Not timed out * 0b0..No effect - * 0b1..Timed out + * 0b0..Not timed out * 0b1..Clear the flag + * 0b1..Timed out */ #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) #define LPIT_MSR_TIF3_MASK (0x8U) #define LPIT_MSR_TIF3_SHIFT (3U) /*! TIF3 - Channel 3 Timer Interrupt Flag - * 0b0..Not timed out * 0b0..No effect - * 0b1..Timed out + * 0b0..Not timed out * 0b1..Clear the flag + * 0b1..Timed out */ #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) /*! @} */ @@ -610,5 +613,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPIT_H_ */ +#endif /* PERI_LPIT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPSPI.h index b2b934d74..b2e157671 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPSPI.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPSPI.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_LPSPI.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPSPI * * CMSIS Peripheral Access Layer for LPSPI */ -#if !defined(LPSPI_H_) -#define LPSPI_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPSPI_H_) +#define PERI_LPSPI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -384,60 +387,60 @@ typedef struct { #define LPSPI_SR_WCF_MASK (0x100U) #define LPSPI_SR_WCF_SHIFT (8U) /*! WCF - Word Complete Flag - * 0b0..Not complete * 0b0..No effect - * 0b1..Complete + * 0b0..Not complete * 0b1..Clear the flag + * 0b1..Complete */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) #define LPSPI_SR_FCF_MASK (0x200U) #define LPSPI_SR_FCF_SHIFT (9U) /*! FCF - Frame Complete Flag - * 0b0..Not complete * 0b0..No effect - * 0b1..Complete + * 0b0..Not complete * 0b1..Clear the flag + * 0b1..Complete */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) #define LPSPI_SR_TCF_MASK (0x400U) #define LPSPI_SR_TCF_SHIFT (10U) /*! TCF - Transfer Complete Flag - * 0b0..Not complete * 0b0..No effect - * 0b1..Complete + * 0b0..Not complete * 0b1..Clear the flag + * 0b1..Complete */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) #define LPSPI_SR_TEF_MASK (0x800U) #define LPSPI_SR_TEF_SHIFT (11U) /*! TEF - Transmit Error Flag - * 0b0..No underrun * 0b0..No effect - * 0b1..Underrun + * 0b0..No underrun * 0b1..Clear the flag + * 0b1..Underrun */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) #define LPSPI_SR_REF_MASK (0x1000U) #define LPSPI_SR_REF_SHIFT (12U) /*! REF - Receive Error Flag - * 0b0..No overflow * 0b0..No effect - * 0b1..Overflow + * 0b0..No overflow * 0b1..Clear the flag + * 0b1..Overflow */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) #define LPSPI_SR_DMF_MASK (0x2000U) #define LPSPI_SR_DMF_SHIFT (13U) /*! DMF - Data Match Flag - * 0b0..No match * 0b0..No effect - * 0b1..Match + * 0b0..No match * 0b1..Clear the flag + * 0b1..Match */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) @@ -980,5 +983,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPSPI_H_ */ +#endif /* PERI_LPSPI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPTMR.h index 696b70616..466ee8564 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPTMR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPTMR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPTMR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPTMR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_LPTMR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPTMR * * CMSIS Peripheral Access Layer for LPTMR */ -#if !defined(LPTMR_H_) -#define LPTMR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPTMR_H_) +#define PERI_LPTMR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -410,5 +413,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPTMR_H_ */ +#endif /* PERI_LPTMR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPUART.h index 949c98b3b..bf498d354 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_LPUART.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file LPUART.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_LPUART.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for LPUART * * CMSIS Peripheral Access Layer for LPUART */ -#if !defined(LPUART_H_) -#define LPUART_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_LPUART_H_) +#define PERI_LPUART_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -515,60 +518,60 @@ typedef struct { #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) /*! MA2F - Match 2 Flag - * 0b0..Not equal to MA2 * 0b0..No effect - * 0b1..Equal to MA2 + * 0b0..Not equal to MA2 * 0b1..Clear the flag + * 0b1..Equal to MA2 */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) #define LPUART_STAT_MA1F_MASK (0x8000U) #define LPUART_STAT_MA1F_SHIFT (15U) /*! MA1F - Match 1 Flag - * 0b0..Not equal to MA1 * 0b0..No effect - * 0b1..Equal to MA1 + * 0b0..Not equal to MA1 * 0b1..Clear the flag + * 0b1..Equal to MA1 */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) /*! PF - Parity Error Flag - * 0b0..No parity error detected * 0b0..No effect - * 0b1..Parity error detected + * 0b0..No parity error detected * 0b1..Clear the flag + * 0b1..Parity error detected */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) /*! FE - Framing Error Flag - * 0b0..No framing error detected (this does not guarantee that the framing is correct) * 0b0..No effect - * 0b1..Framing error detected + * 0b0..No framing error detected (this does not guarantee that the framing is correct) * 0b1..Clear the flag + * 0b1..Framing error detected */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) /*! NF - Noise Flag - * 0b0..No noise detected * 0b0..No effect - * 0b1..Noise detected + * 0b0..No noise detected * 0b1..Clear the flag + * 0b1..Noise detected */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) #define LPUART_STAT_OR_MASK (0x80000U) #define LPUART_STAT_OR_SHIFT (19U) /*! OR - Receiver Overrun Flag - * 0b0..No overrun * 0b0..No effect - * 0b1..Receive overrun (new LPUART data is lost) + * 0b0..No overrun * 0b1..Clear the flag + * 0b1..Receive overrun (new LPUART data is lost) */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) @@ -577,8 +580,8 @@ typedef struct { /*! IDLE - Idle Line Flag * 0b0..Idle line detected * 0b0..No effect - * 0b1..Idle line not detected * 0b1..Clear the flag + * 0b1..Idle line not detected */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) @@ -657,20 +660,20 @@ typedef struct { #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) #define LPUART_STAT_RXEDGIF_SHIFT (30U) /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag - * 0b0..Not occurred * 0b0..No effect - * 0b1..Occurred + * 0b0..Not occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) /*! LBKDIF - LIN Break Detect Interrupt Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) /*! @} */ @@ -1190,20 +1193,20 @@ typedef struct { #define LPUART_FIFO_RXUF_MASK (0x10000U) #define LPUART_FIFO_RXUF_SHIFT (16U) /*! RXUF - Receiver FIFO Underflow Flag - * 0b0..No underflow * 0b0..No effect - * 0b1..Underflow + * 0b0..No underflow * 0b1..Clear the flag + * 0b1..Underflow */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) #define LPUART_FIFO_TXOF_MASK (0x20000U) #define LPUART_FIFO_TXOF_SHIFT (17U) /*! TXOF - Transmitter FIFO Overflow Flag - * 0b0..No overflow * 0b0..No effect - * 0b1..Overflow + * 0b0..No overflow * 0b1..Clear the flag + * 0b1..Overflow */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) @@ -1469,10 +1472,10 @@ typedef struct { #define LPUART_TOSR_TOF_MASK (0xF00U) #define LPUART_TOSR_TOF_SHIFT (8U) /*! TOF - Timeout Flag - * 0b0000..Not occurred * 0b0000..No effect - * 0b0001..Occurred + * 0b0000..Not occurred * 0b0001..Clear the flag + * 0b0001..Occurred */ #define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) /*! @} */ @@ -1563,5 +1566,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* LPUART_H_ */ +#endif /* PERI_LPUART_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_A7_APB_MCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_A7_APB_MCM.h index 568ae8769..862d01d92 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_A7_APB_MCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_A7_APB_MCM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for M7_A7_APB_MCM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file M7_A7_APB_MCM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_M7_A7_APB_MCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for M7_A7_APB_MCM * * CMSIS Peripheral Access Layer for M7_A7_APB_MCM */ -#if !defined(M7_A7_APB_MCM_H_) -#define M7_A7_APB_MCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_M7_A7_APB_MCM_H_) +#define PERI_M7_A7_APB_MCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -689,5 +692,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* M7_A7_APB_MCM_H_ */ +#endif /* PERI_M7_A7_APB_MCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_A7_PPB_MCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_A7_PPB_MCM.h index d9c1edbc6..97b5758b7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_A7_PPB_MCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_A7_PPB_MCM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for M7_A7_PPB_MCM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file M7_A7_PPB_MCM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_M7_A7_PPB_MCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for M7_A7_PPB_MCM * * CMSIS Peripheral Access Layer for M7_A7_PPB_MCM */ -#if !defined(M7_A7_PPB_MCM_H_) -#define M7_A7_PPB_MCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_M7_A7_PPB_MCM_H_) +#define PERI_M7_A7_PPB_MCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -431,5 +434,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* M7_A7_PPB_MCM_H_ */ +#endif /* PERI_M7_A7_PPB_MCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_CMU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_CMU.h index 40f9928eb..69274ea33 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_CMU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_CMU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for M7_CMU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file M7_CMU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_M7_CMU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for M7_CMU * * CMSIS Peripheral Access Layer for M7_CMU */ -#if !defined(M7_CMU_H_) -#define M7_CMU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_M7_CMU_H_) +#define PERI_M7_CMU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -365,5 +368,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* M7_CMU_H_ */ +#endif /* PERI_M7_CMU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_EIM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_EIM.h index 1ccae1e39..38d4c528c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_EIM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_EIM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for M7_EIM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file M7_EIM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_M7_EIM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for M7_EIM * * CMSIS Peripheral Access Layer for M7_EIM */ -#if !defined(M7_EIM_H_) -#define M7_EIM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_M7_EIM_H_) +#define PERI_M7_EIM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -691,5 +694,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* M7_EIM_H_ */ +#endif /* PERI_M7_EIM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_ERM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_ERM.h index d72203a7b..1eda2bc71 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_ERM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_ERM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for M7_ERM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file M7_ERM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_M7_ERM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for M7_ERM * * CMSIS Peripheral Access Layer for M7_ERM */ -#if !defined(M7_ERM_H_) -#define M7_ERM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_M7_ERM_H_) +#define PERI_M7_ERM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -644,5 +647,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* M7_ERM_H_ */ +#endif /* PERI_M7_ERM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_LSTCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_LSTCU.h index 695cf8700..10b09e28c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_LSTCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_LSTCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for M7_LSTCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file M7_LSTCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_M7_LSTCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for M7_LSTCU * * CMSIS Peripheral Access Layer for M7_LSTCU */ -#if !defined(M7_LSTCU_H_) -#define M7_LSTCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_M7_LSTCU_H_) +#define PERI_M7_LSTCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -399,5 +402,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* M7_LSTCU_H_ */ +#endif /* PERI_M7_LSTCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_TCU.h index 045c42091..671a55234 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M7_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for M7_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file M7_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_M7_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for M7_TCU * * CMSIS Peripheral Access Layer for M7_TCU */ -#if !defined(M7_TCU_H_) -#define M7_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_M7_TCU_H_) +#define PERI_M7_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -346,5 +349,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* M7_TCU_H_ */ +#endif /* PERI_M7_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_MSGINTR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_MSGINTR.h index 6d03be6dd..8d7cc659a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_MSGINTR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_MSGINTR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MSGINTR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file MSGINTR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_MSGINTR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MSGINTR * * CMSIS Peripheral Access Layer for MSGINTR */ -#if !defined(MSGINTR_H_) -#define MSGINTR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_MSGINTR_H_) +#define PERI_MSGINTR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -302,5 +305,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* MSGINTR_H_ */ +#endif /* PERI_MSGINTR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_MU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_MU.h index 2aaa5af96..ccd1baec9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_MU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file MU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_MU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for MU * * CMSIS Peripheral Access Layer for MU */ -#if !defined(MU_H_) -#define MU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_MU_H_) +#define PERI_MU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -353,10 +356,10 @@ typedef struct { #define MU_SR_MURIP_MASK (0x2U) #define MU_SR_MURIP_SHIFT (1U) /*! MURIP - MU Reset Interrupt Pending Flag - * 0b0..Reset not issued * 0b0..No effect - * 0b1..Reset issued + * 0b0..Reset not issued * 0b1..Clear the flag + * 0b1..Reset issued */ #define MU_SR_MURIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK) @@ -777,40 +780,40 @@ typedef struct { #define MU_GSR_GIP0_MASK (0x1U) #define MU_GSR_GIP0_SHIFT (0U) /*! GIP0 - MUB General-Purpose Interrupt Request Pending - * 0b0..Not pending * 0b0..No effect - * 0b1..Pending + * 0b0..Not pending * 0b1..Clear the flag + * 0b1..Pending */ #define MU_GSR_GIP0(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP0_SHIFT)) & MU_GSR_GIP0_MASK) #define MU_GSR_GIP1_MASK (0x2U) #define MU_GSR_GIP1_SHIFT (1U) /*! GIP1 - MUB General-Purpose Interrupt Request Pending - * 0b0..Not pending * 0b0..No effect - * 0b1..Pending + * 0b0..Not pending * 0b1..Clear the flag + * 0b1..Pending */ #define MU_GSR_GIP1(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP1_SHIFT)) & MU_GSR_GIP1_MASK) #define MU_GSR_GIP2_MASK (0x4U) #define MU_GSR_GIP2_SHIFT (2U) /*! GIP2 - MUB General-Purpose Interrupt Request Pending - * 0b0..Not pending * 0b0..No effect - * 0b1..Pending + * 0b0..Not pending * 0b1..Clear the flag + * 0b1..Pending */ #define MU_GSR_GIP2(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP2_SHIFT)) & MU_GSR_GIP2_MASK) #define MU_GSR_GIP3_MASK (0x8U) #define MU_GSR_GIP3_SHIFT (3U) /*! GIP3 - MUB General-Purpose Interrupt Request Pending - * 0b0..Not pending * 0b0..No effect - * 0b1..Pending + * 0b0..Not pending * 0b1..Clear the flag + * 0b1..Pending */ #define MU_GSR_GIP3(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP3_SHIFT)) & MU_GSR_GIP3_MASK) /*! @} */ @@ -1011,5 +1014,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* MU_H_ */ +#endif /* PERI_MU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M_E_3_WR_I_MAIN_TRANSTATFILT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M_E_3_WR_I_MAIN_TRANSTATFILT.h index a2fb91a08..2d585e9d9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M_E_3_WR_I_MAIN_TRANSTATFILT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M_E_3_WR_I_MAIN_TRANSTATFILT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for m_e_3_wr_I_main_TranStatFilt @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file m_e_3_wr_I_main_TranStatFilt.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_m_e_3_wr_I_main_TranStatFilt.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for m_e_3_wr_I_main_TranStatFilt * * CMSIS Peripheral Access Layer for m_e_3_wr_I_main_TranStatFilt */ -#if !defined(m_e_3_wr_I_main_TranStatFilt_H_) -#define m_e_3_wr_I_main_TranStatFilt_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_M_E_3_WR_I_MAIN_TRANSTATFILT_H_) +#define PERI_M_E_3_WR_I_MAIN_TRANSTATFILT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* m_e_3_wr_I_main_TranStatFilt_H_ */ +#endif /* PERI_M_E_3_WR_I_MAIN_TRANSTATFILT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER.h index 7a90432f8..b70223bbd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for @@ -158,21 +158,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file m_e_9_rd_I_main_TransactionStatFilter.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_m_e_9_rd_I_main_TransactionStatFilter.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for m_e_9_rd_I_main_TransactionStatFilter * * CMSIS Peripheral Access Layer for m_e_9_rd_I_main_TransactionStatFilter */ -#if !defined(m_e_9_rd_I_main_TransactionStatFilter_H_) -#define m_e_9_rd_I_main_TransactionStatFilter_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER_H_) +#define PERI_M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -367,5 +370,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* m_e_9_rd_I_main_TransactionStatFilter_H_ */ +#endif /* PERI_M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NECTMIX_CM33_AIPS.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NECTMIX_CM33_AIPS.h index 2043af26e..90cfebbca 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NECTMIX_CM33_AIPS.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NECTMIX_CM33_AIPS.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NECTMIX_CM33_AIPS @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NECTMIX_CM33_AIPS.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NECTMIX_CM33_AIPS.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NECTMIX_CM33_AIPS * * CMSIS Peripheral Access Layer for NECTMIX_CM33_AIPS */ -#if !defined(NECTMIX_CM33_AIPS_H_) -#define NECTMIX_CM33_AIPS_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NECTMIX_CM33_AIPS_H_) +#define PERI_NECTMIX_CM33_AIPS_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -431,5 +434,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NECTMIX_CM33_AIPS_H_ */ +#endif /* PERI_NECTMIX_CM33_AIPS_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_CMU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_CMU.h index 8776a4418..a03ab5fa4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_CMU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_CMU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_CMU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_CMU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_CMU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_CMU * * CMSIS Peripheral Access Layer for NETC_CMU */ -#if !defined(NETC_CMU_H_) -#define NETC_CMU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_CMU_H_) +#define PERI_NETC_CMU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -365,5 +368,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_CMU_H_ */ +#endif /* PERI_NETC_CMU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_EIM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_EIM.h index 6482b1e37..da4519fc7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_EIM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_EIM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_EIM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_EIM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_EIM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_EIM * * CMSIS Peripheral Access Layer for NETC_EIM */ -#if !defined(NETC_EIM_H_) -#define NETC_EIM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_EIM_H_) +#define PERI_NETC_EIM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -794,5 +797,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_EIM_H_ */ +#endif /* PERI_NETC_EIM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ENETC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ENETC.h index 8145db8ee..fc6d6244d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ENETC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ENETC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_ENETC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_ENETC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_ENETC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_ENETC * * CMSIS Peripheral Access Layer for NETC_ENETC */ -#if !defined(NETC_ENETC_H_) -#define NETC_ENETC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_ENETC_H_) +#define PERI_NETC_ENETC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1396,5 +1399,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_ENETC_H_ */ +#endif /* PERI_NETC_ENETC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ERM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ERM.h index 1d9aee093..cd32223f0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ERM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ERM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_ERM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_ERM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_ERM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_ERM * * CMSIS Peripheral Access Layer for NETC_ERM */ -#if !defined(NETC_ERM_H_) -#define NETC_ERM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_ERM_H_) +#define PERI_NETC_ERM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1112,5 +1115,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_ERM_H_ */ +#endif /* PERI_NETC_ERM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ETH_LINK.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ETH_LINK.h index 998366a65..52cacae31 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ETH_LINK.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_ETH_LINK.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_ETH_LINK @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_ETH_LINK.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_ETH_LINK.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_ETH_LINK * * CMSIS Peripheral Access Layer for NETC_ETH_LINK */ -#if !defined(NETC_ETH_LINK_H_) -#define NETC_ETH_LINK_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_ETH_LINK_H_) +#define PERI_NETC_ETH_LINK_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2838,5 +2841,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_ETH_LINK_H_ */ +#endif /* PERI_NETC_ETH_LINK_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_IERB.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_IERB.h index 177ff08c3..89f8ae800 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_IERB.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_IERB.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_IERB @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_IERB.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_IERB.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_IERB * * CMSIS Peripheral Access Layer for NETC_IERB */ -#if !defined(NETC_IERB_H_) -#define NETC_IERB_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_IERB_H_) +#define PERI_NETC_IERB_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -3134,5 +3137,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_IERB_H_ */ +#endif /* PERI_NETC_IERB_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_LSTCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_LSTCU.h index 3526ef363..a30d75e11 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_LSTCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_LSTCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_LSTCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_LSTCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_LSTCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_LSTCU * * CMSIS Peripheral Access Layer for NETC_LSTCU */ -#if !defined(NETC_LSTCU_H_) -#define NETC_LSTCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_LSTCU_H_) +#define PERI_NETC_LSTCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -433,5 +436,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_LSTCU_H_ */ +#endif /* PERI_NETC_LSTCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_MAX_CORE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_MAX_CORE.h index bd44c3252..71912e4cb 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_MAX_CORE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_MAX_CORE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_MAX_CORE @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_MAX_CORE.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_MAX_CORE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_MAX_CORE * * CMSIS Peripheral Access Layer for NETC_MAX_CORE */ -#if !defined(NETC_MAX_CORE_H_) -#define NETC_MAX_CORE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_MAX_CORE_H_) +#define PERI_NETC_MAX_CORE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -4183,5 +4186,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_MAX_CORE_H_ */ +#endif /* PERI_NETC_MAX_CORE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_OCSRAM_MCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_OCSRAM_MCM.h index 73d48b8c0..4f9b05655 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_OCSRAM_MCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_OCSRAM_MCM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_OCSRAM_MCM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_OCSRAM_MCM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_OCSRAM_MCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_OCSRAM_MCM * * CMSIS Peripheral Access Layer for NETC_OCSRAM_MCM */ -#if !defined(NETC_OCSRAM_MCM_H_) -#define NETC_OCSRAM_MCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_OCSRAM_MCM_H_) +#define PERI_NETC_OCSRAM_MCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -772,5 +775,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_OCSRAM_MCM_H_ */ +#endif /* PERI_NETC_OCSRAM_MCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PORT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PORT.h index 02371c5a8..42b7b8a97 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PORT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PORT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_PORT @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_PORT.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_PORT.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_PORT * * CMSIS Peripheral Access Layer for NETC_PORT */ -#if !defined(NETC_PORT_H_) -#define NETC_PORT_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_PORT_H_) +#define PERI_NETC_PORT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1733,5 +1736,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_PORT_H_ */ +#endif /* PERI_NETC_PORT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PRIV.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PRIV.h index 555df2b41..aca18fcc1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PRIV.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PRIV.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_PRIV @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_PRIV.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_PRIV.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_PRIV * * CMSIS Peripheral Access Layer for NETC_PRIV */ -#if !defined(NETC_PRIV_H_) -#define NETC_PRIV_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_PRIV_H_) +#define PERI_NETC_PRIV_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -529,5 +532,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_PRIV_H_ */ +#endif /* PERI_NETC_PRIV_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PSEUDO_LINK.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PSEUDO_LINK.h index ded05bfd8..cf9f18285 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PSEUDO_LINK.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_PSEUDO_LINK.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_PSEUDO_LINK @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_PSEUDO_LINK.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_PSEUDO_LINK.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_PSEUDO_LINK * * CMSIS Peripheral Access Layer for NETC_PSEUDO_LINK */ -#if !defined(NETC_PSEUDO_LINK_H_) -#define NETC_PSEUDO_LINK_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_PSEUDO_LINK_H_) +#define PERI_NETC_PSEUDO_LINK_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -380,5 +383,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_PSEUDO_LINK_H_ */ +#endif /* PERI_NETC_PSEUDO_LINK_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_SW.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_SW.h index ed99d30be..388d7b402 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_SW.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_SW.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_SW @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_SW.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_SW.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_SW * * CMSIS Peripheral Access Layer for NETC_SW */ -#if !defined(NETC_SW_H_) -#define NETC_SW_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_SW_H_) +#define PERI_NETC_SW_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1430,5 +1433,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_SW_H_ */ +#endif /* PERI_NETC_SW_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_SW_ENETC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_SW_ENETC.h index 24eaf9cdc..e1820b01a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_SW_ENETC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_SW_ENETC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_SW_ENETC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_SW_ENETC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_SW_ENETC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_SW_ENETC * * CMSIS Peripheral Access Layer for NETC_SW_ENETC */ -#if !defined(NETC_SW_ENETC_H_) -#define NETC_SW_ENETC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_SW_ENETC_H_) +#define PERI_NETC_SW_ENETC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2678,5 +2681,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_SW_ENETC_H_ */ +#endif /* PERI_NETC_SW_ENETC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TCU.h index 05774316d..06946183b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_TCU * * CMSIS Peripheral Access Layer for NETC_TCU */ -#if !defined(NETC_TCU_H_) -#define NETC_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_TCU_H_) +#define PERI_NETC_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -466,5 +469,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_TCU_H_ */ +#endif /* PERI_NETC_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TCU_CM33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TCU_CM33.h index 3ec4d17b4..cb1789834 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TCU_CM33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TCU_CM33.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_TCU_CM33 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_TCU_CM33.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_TCU_CM33.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_TCU_CM33 * * CMSIS Peripheral Access Layer for NETC_TCU_CM33 */ -#if !defined(NETC_TCU_CM33_H_) -#define NETC_TCU_CM33_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_TCU_CM33_H_) +#define PERI_NETC_TCU_CM33_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -466,5 +469,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_TCU_CM33_H_ */ +#endif /* PERI_NETC_TCU_CM33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TMR_BASE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TMR_BASE.h index afb29039c..369799482 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TMR_BASE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TMR_BASE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_TMR_BASE @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_TMR_BASE.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_TMR_BASE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_TMR_BASE * * CMSIS Peripheral Access Layer for NETC_TMR_BASE */ -#if !defined(NETC_TMR_BASE_H_) -#define NETC_TMR_BASE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_TMR_BASE_H_) +#define PERI_NETC_TMR_BASE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -905,5 +908,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_TMR_BASE_H_ */ +#endif /* PERI_NETC_TMR_BASE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TRDC_MGR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TRDC_MGR.h index 58f5db34c..04364ef23 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TRDC_MGR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TRDC_MGR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_TRDC_MGR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_TRDC_MGR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_TRDC_MGR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_TRDC_MGR * * CMSIS Peripheral Access Layer for NETC_TRDC_MGR */ -#if !defined(NETC_TRDC_MGR_H_) -#define NETC_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_TRDC_MGR_H_) +#define PERI_NETC_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -39954,5 +39957,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_TRDC_MGR_H_ */ +#endif /* PERI_NETC_TRDC_MGR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TRDC_MGR_CM33.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TRDC_MGR_CM33.h index 7d160a4f6..c4e9f55cb 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TRDC_MGR_CM33.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NETC_TRDC_MGR_CM33.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_TRDC_MGR_CM33 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NETC_TRDC_MGR_CM33.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NETC_TRDC_MGR_CM33.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NETC_TRDC_MGR_CM33 * * CMSIS Peripheral Access Layer for NETC_TRDC_MGR_CM33 */ -#if !defined(NETC_TRDC_MGR_CM33_H_) -#define NETC_TRDC_MGR_CM33_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NETC_TRDC_MGR_CM33_H_) +#define PERI_NETC_TRDC_MGR_CM33_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -39583,5 +39586,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NETC_TRDC_MGR_CM33_H_ */ +#endif /* PERI_NETC_TRDC_MGR_CM33_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NEUTRON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NEUTRON.h index 419d53b0e..7d501a51d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NEUTRON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NEUTRON.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NEUTRON @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NEUTRON.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NEUTRON.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NEUTRON * * CMSIS Peripheral Access Layer for NEUTRON */ -#if !defined(NEUTRON_H_) -#define NEUTRON_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NEUTRON_H_) +#define PERI_NEUTRON_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1254,5 +1257,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NEUTRON_H_ */ +#endif /* PERI_NEUTRON_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NEUTRONS.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NEUTRONS.h index 5d7371040..eeb9e67ff 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NEUTRONS.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NEUTRONS.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for neutrons @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file neutrons.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_neutrons.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for neutrons * * CMSIS Peripheral Access Layer for neutrons */ -#if !defined(neutrons_H_) -#define neutrons_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NEUTRONS_H_) +#define PERI_NEUTRONS_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -987,50 +990,50 @@ typedef struct { #define neutrons_CONFIG_TTINT_MASK (0x100U) #define neutrons_CONFIG_TTINT_SHIFT (8U) /*! TTINT - TCM-to-TCM Channel Interrupt Status - * 0b0..No interrupt generated * 0b0..No effect - * 0b1..Interrupt generated + * 0b0..No interrupt generated * 0b1..Clear + * 0b1..Interrupt generated */ #define neutrons_CONFIG_TTINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_TTINT_SHIFT)) & neutrons_CONFIG_TTINT_MASK) #define neutrons_CONFIG_FINT_MASK (0x200U) #define neutrons_CONFIG_FINT_SHIFT (9U) /*! FINT - Fetch Channel Interrupt Status - * 0b0..No interrupt generated * 0b0..No effect - * 0b1..Interrupt generated + * 0b0..No interrupt generated * 0b1..Clear + * 0b1..Interrupt generated */ #define neutrons_CONFIG_FINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_FINT_SHIFT)) & neutrons_CONFIG_FINT_MASK) #define neutrons_CONFIG_PINT_MASK (0x400U) #define neutrons_CONFIG_PINT_SHIFT (10U) /*! PINT - Push Channel Interrupt Status - * 0b0..No interrupt generated * 0b0..No effect - * 0b1..Interrupt generated + * 0b0..No interrupt generated * 0b1..Clear + * 0b1..Interrupt generated */ #define neutrons_CONFIG_PINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_PINT_SHIFT)) & neutrons_CONFIG_PINT_MASK) #define neutrons_CONFIG_WINT_MASK (0x800U) #define neutrons_CONFIG_WINT_SHIFT (11U) /*! WINT - Data Mover Weight Channel Interrupt - * 0b0..No interrupt generated * 0b0..No effect - * 0b1..Interrupt generated + * 0b0..No interrupt generated * 0b1..Clear + * 0b1..Interrupt generated */ #define neutrons_CONFIG_WINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_WINT_SHIFT)) & neutrons_CONFIG_WINT_MASK) #define neutrons_CONFIG_EINT_MASK (0x1000U) #define neutrons_CONFIG_EINT_SHIFT (12U) /*! EINT - Data Mover Error Interrupt - * 0b0..No interrupt generated * 0b0..No effect - * 0b1..Interrupt generated + * 0b0..No interrupt generated * 0b1..Clear + * 0b1..Interrupt generated */ #define neutrons_CONFIG_EINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_EINT_SHIFT)) & neutrons_CONFIG_EINT_MASK) @@ -2582,5 +2585,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* neutrons_H_ */ +#endif /* PERI_NEUTRONS_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_ALWAYS_ON_MAIN_RESFAULTCNTR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_ALWAYS_ON_MAIN_RESFAULTCNTR.h index 805048edc..98fbe73c3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_ALWAYS_ON_MAIN_RESFAULTCNTR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_ALWAYS_ON_MAIN_RESFAULTCNTR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_always_on_main_ResFaultCntr @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_always_on_main_ResFaultCntr.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_always_on_main_ResFaultCntr.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_always_on_main_ResFaultCntr * * CMSIS Peripheral Access Layer for NOC_always_on_main_ResFaultCntr */ -#if !defined(NOC_always_on_main_ResFaultCntr_H_) -#define NOC_always_on_main_ResFaultCntr_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_ALWAYS_ON_MAIN_RESFAULTCNTR_H_) +#define PERI_NOC_ALWAYS_ON_MAIN_RESFAULTCNTR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -453,5 +456,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_always_on_main_ResFaultCntr_H_ */ +#endif /* PERI_NOC_ALWAYS_ON_MAIN_RESFAULTCNTR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_BLK_CTRL_NOCMIX.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_BLK_CTRL_NOCMIX.h index a8390147d..c3366de5f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_BLK_CTRL_NOCMIX.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_BLK_CTRL_NOCMIX.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_BLK_CTRL_NOCMIX @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_BLK_CTRL_NOCMIX.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_BLK_CTRL_NOCMIX.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_BLK_CTRL_NOCMIX * * CMSIS Peripheral Access Layer for NOC_BLK_CTRL_NOCMIX */ -#if !defined(NOC_BLK_CTRL_NOCMIX_H_) -#define NOC_BLK_CTRL_NOCMIX_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_BLK_CTRL_NOCMIX_H_) +#define PERI_NOC_BLK_CTRL_NOCMIX_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1499,5 +1502,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_BLK_CTRL_NOCMIX_H_ */ +#endif /* PERI_NOC_BLK_CTRL_NOCMIX_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_CMU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_CMU.h index 491bf0543..78ade89fc 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_CMU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_CMU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_CMU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_CMU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_CMU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_CMU * * CMSIS Peripheral Access Layer for NOC_CMU */ -#if !defined(NOC_CMU_H_) -#define NOC_CMU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_CMU_H_) +#define PERI_NOC_CMU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -365,5 +368,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_CMU_H_ */ +#endif /* PERI_NOC_CMU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_EIM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_EIM.h index 4dc8d0f12..5c87722bd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_EIM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_EIM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_EIM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_EIM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_EIM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_EIM * * CMSIS Peripheral Access Layer for NOC_EIM */ -#if !defined(NOC_EIM_H_) -#define NOC_EIM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_EIM_H_) +#define PERI_NOC_EIM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -348,5 +351,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_EIM_H_ */ +#endif /* PERI_NOC_EIM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICA.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICA.h index 95784673a..18e81c0a7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICA.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICA.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICA @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICA.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICA.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICA * * CMSIS Peripheral Access Layer for NOC_GICA */ -#if !defined(NOC_GICA_H_) -#define NOC_GICA_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICA_H_) +#define PERI_NOC_GICA_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -624,5 +627,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICA_H_ */ +#endif /* PERI_NOC_GICA_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICD.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICD.h index eb9d12fa6..337c43b59 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICD.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICD.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICD @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICD.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICD.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICD * * CMSIS Peripheral Access Layer for NOC_GICD */ -#if !defined(NOC_GICD_H_) -#define NOC_GICD_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICD_H_) +#define PERI_NOC_GICD_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -83004,5 +83007,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICD_H_ */ +#endif /* PERI_NOC_GICD_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICDA.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICDA.h index e652836fc..4e21dc571 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICDA.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICDA.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICDA @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICDA.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICDA.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICDA * * CMSIS Peripheral Access Layer for NOC_GICDA */ -#if !defined(NOC_GICDA_H_) -#define NOC_GICDA_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICDA_H_) +#define PERI_NOC_GICDA_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -83004,5 +83007,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICDA_H_ */ +#endif /* PERI_NOC_GICDA_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICP.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICP.h index 2c03bec6b..a6cb2b777 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICP.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICP.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICP @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICP.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICP.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICP * * CMSIS Peripheral Access Layer for NOC_GICP */ -#if !defined(NOC_GICP_H_) -#define NOC_GICP_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICP_H_) +#define PERI_NOC_GICP_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1181,5 +1184,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICP_H_ */ +#endif /* PERI_NOC_GICP_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI0.h index 8a39b10cc..f2c16431a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI0.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICRlpi0 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICRlpi0.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICRlpi0.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICRlpi0 * * CMSIS Peripheral Access Layer for NOC_GICRlpi0 */ -#if !defined(NOC_GICRlpi0_H_) -#define NOC_GICRlpi0_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICRLPI0_H_) +#define PERI_NOC_GICRLPI0_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1018,5 +1021,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICRlpi0_H_ */ +#endif /* PERI_NOC_GICRLPI0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI1.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI1.h index 32e071072..eea692026 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI1.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI1.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICRlpi1 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICRlpi1.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICRlpi1.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICRlpi1 * * CMSIS Peripheral Access Layer for NOC_GICRlpi1 */ -#if !defined(NOC_GICRlpi1_H_) -#define NOC_GICRlpi1_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICRLPI1_H_) +#define PERI_NOC_GICRLPI1_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1018,5 +1021,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICRlpi1_H_ */ +#endif /* PERI_NOC_GICRLPI1_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI2.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI2.h index 6253886d5..640fe15c1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI2.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI2.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICRlpi2 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICRlpi2.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICRlpi2.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICRlpi2 * * CMSIS Peripheral Access Layer for NOC_GICRlpi2 */ -#if !defined(NOC_GICRlpi2_H_) -#define NOC_GICRlpi2_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICRLPI2_H_) +#define PERI_NOC_GICRLPI2_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1018,5 +1021,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICRlpi2_H_ */ +#endif /* PERI_NOC_GICRLPI2_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI3.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI3.h index d3e2fe5e9..356194640 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI3.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRLPI3.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICRlpi3 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICRlpi3.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICRlpi3.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICRlpi3 * * CMSIS Peripheral Access Layer for NOC_GICRlpi3 */ -#if !defined(NOC_GICRlpi3_H_) -#define NOC_GICRlpi3_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICRLPI3_H_) +#define PERI_NOC_GICRLPI3_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1018,5 +1021,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICRlpi3_H_ */ +#endif /* PERI_NOC_GICRLPI3_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI0.h index 6e3af7aa7..92897a48f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI0.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICRsgi0 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICRsgi0.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICRsgi0.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICRsgi0 * * CMSIS Peripheral Access Layer for NOC_GICRsgi0 */ -#if !defined(NOC_GICRsgi0_H_) -#define NOC_GICRsgi0_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICRSGI0_H_) +#define PERI_NOC_GICRSGI0_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -4176,5 +4179,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICRsgi0_H_ */ +#endif /* PERI_NOC_GICRSGI0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI2.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI2.h index 971009a09..c6a1466d8 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI2.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI2.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICRsgi2 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICRsgi2.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICRsgi2.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICRsgi2 * * CMSIS Peripheral Access Layer for NOC_GICRsgi2 */ -#if !defined(NOC_GICRsgi2_H_) -#define NOC_GICRsgi2_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICRSGI2_H_) +#define PERI_NOC_GICRSGI2_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -4176,5 +4179,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICRsgi2_H_ */ +#endif /* PERI_NOC_GICRSGI2_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI3.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI3.h index e24417475..8265d3c6b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI3.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGI3.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICRsgi3 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICRsgi3.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICRsgi3.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICRsgi3 * * CMSIS Peripheral Access Layer for NOC_GICRsgi3 */ -#if !defined(NOC_GICRsgi3_H_) -#define NOC_GICRsgi3_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICRSGI3_H_) +#define PERI_NOC_GICRSGI3_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -4176,5 +4179,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICRsgi3_H_ */ +#endif /* PERI_NOC_GICRSGI3_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGIL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGIL.h index 420aa9b1a..101bc291b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGIL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICRSGIL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICRsgil @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICRsgil.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICRsgil.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICRsgil * * CMSIS Peripheral Access Layer for NOC_GICRsgil */ -#if !defined(NOC_GICRsgil_H_) -#define NOC_GICRsgil_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICRSGIL_H_) +#define PERI_NOC_GICRSGIL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -4176,5 +4179,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICRsgil_H_ */ +#endif /* PERI_NOC_GICRSGIL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICT.h index f59d04c91..3c77ecce1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GICT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GICT @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GICT.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GICT.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GICT * * CMSIS Peripheral Access Layer for NOC_GICT */ -#if !defined(NOC_GICT_H_) -#define NOC_GICT_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GICT_H_) +#define PERI_NOC_GICT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -8024,5 +8027,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GICT_H_ */ +#endif /* PERI_NOC_GICT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GITS0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GITS0.h index ce509b909..0290bd35b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GITS0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GITS0.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GITS0 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GITS0.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GITS0.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GITS0 * * CMSIS Peripheral Access Layer for NOC_GITS0 */ -#if !defined(NOC_GITS0_H_) -#define NOC_GITS0_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GITS0_H_) +#define PERI_NOC_GITS0_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1278,5 +1281,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GITS0_H_ */ +#endif /* PERI_NOC_GITS0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GITS0TRANSLATER.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GITS0TRANSLATER.h index 85d7dfe70..a18ca3b64 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GITS0TRANSLATER.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_GITS0TRANSLATER.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_GITS0translater @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_GITS0translater.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_GITS0translater.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_GITS0translater * * CMSIS Peripheral Access Layer for NOC_GITS0translater */ -#if !defined(NOC_GITS0translater_H_) -#define NOC_GITS0translater_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_GITS0TRANSLATER_H_) +#define PERI_NOC_GITS0TRANSLATER_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -288,5 +291,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_GITS0translater_H_ */ +#endif /* PERI_NOC_GITS0TRANSLATER_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_LCDIF_RD_I_MAIN_QOSG.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_LCDIF_RD_I_MAIN_QOSG.h index fea51ee05..24f2944c1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_LCDIF_RD_I_MAIN_QOSG.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_LCDIF_RD_I_MAIN_QOSG.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_I_LCDIF_rd_I_main_QosG @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_I_LCDIF_rd_I_main_QosG.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_I_LCDIF_rd_I_main_QosG.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_I_LCDIF_rd_I_main_QosG * * CMSIS Peripheral Access Layer for NOC_I_LCDIF_rd_I_main_QosG */ -#if !defined(NOC_I_LCDIF_rd_I_main_QosG_H_) -#define NOC_I_LCDIF_rd_I_main_QosG_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_I_LCDIF_RD_I_MAIN_QOSG_H_) +#define PERI_NOC_I_LCDIF_RD_I_MAIN_QOSG_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_I_LCDIF_rd_I_main_QosG_H_ */ +#endif /* PERI_NOC_I_LCDIF_RD_I_MAIN_QOSG_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_LCDIF_RD_I_MAIN_TRANSTATFLTR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_LCDIF_RD_I_MAIN_TRANSTATFLTR.h index 1d0088619..a73727f3d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_LCDIF_RD_I_MAIN_TRANSTATFLTR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_LCDIF_RD_I_MAIN_TRANSTATFLTR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_I_LCDIF_rd_I_main_TranStatFltr @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_I_LCDIF_rd_I_main_TranStatFltr.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_I_LCDIF_rd_I_main_TranStatFltr.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_I_LCDIF_rd_I_main_TranStatFltr * * CMSIS Peripheral Access Layer for NOC_I_LCDIF_rd_I_main_TranStatFltr */ -#if !defined(NOC_I_LCDIF_rd_I_main_TranStatFltr_H_) -#define NOC_I_LCDIF_rd_I_main_TranStatFltr_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_I_LCDIF_RD_I_MAIN_TRANSTATFLTR_H_) +#define PERI_NOC_I_LCDIF_RD_I_MAIN_TRANSTATFLTR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -358,5 +361,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_I_LCDIF_rd_I_main_TranStatFltr_H_ */ +#endif /* PERI_NOC_I_LCDIF_RD_I_MAIN_TRANSTATFLTR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_RD_I_MAIN_QOSG.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_RD_I_MAIN_QOSG.h index feb901d69..bd0907b1c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_RD_I_MAIN_QOSG.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_RD_I_MAIN_QOSG.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_I_PXP_rd_I_main_QosG @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_I_PXP_rd_I_main_QosG.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_I_PXP_rd_I_main_QosG.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_I_PXP_rd_I_main_QosG * * CMSIS Peripheral Access Layer for NOC_I_PXP_rd_I_main_QosG */ -#if !defined(NOC_I_PXP_rd_I_main_QosG_H_) -#define NOC_I_PXP_rd_I_main_QosG_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_I_PXP_RD_I_MAIN_QOSG_H_) +#define PERI_NOC_I_PXP_RD_I_MAIN_QOSG_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_I_PXP_rd_I_main_QosG_H_ */ +#endif /* PERI_NOC_I_PXP_RD_I_MAIN_QOSG_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_RD_I_MAIN_TRANSTATFLTR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_RD_I_MAIN_TRANSTATFLTR.h index 513b61f92..f506b3b34 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_RD_I_MAIN_TRANSTATFLTR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_RD_I_MAIN_TRANSTATFLTR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_I_PXP_rd_I_main_TranStatFltr @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_I_PXP_rd_I_main_TranStatFltr.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_I_PXP_rd_I_main_TranStatFltr.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_I_PXP_rd_I_main_TranStatFltr * * CMSIS Peripheral Access Layer for NOC_I_PXP_rd_I_main_TranStatFltr */ -#if !defined(NOC_I_PXP_rd_I_main_TranStatFltr_H_) -#define NOC_I_PXP_rd_I_main_TranStatFltr_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_I_PXP_RD_I_MAIN_TRANSTATFLTR_H_) +#define PERI_NOC_I_PXP_RD_I_MAIN_TRANSTATFLTR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -358,5 +361,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_I_PXP_rd_I_main_TranStatFltr_H_ */ +#endif /* PERI_NOC_I_PXP_RD_I_MAIN_TRANSTATFLTR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_WR_I_MAIN_QOSG.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_WR_I_MAIN_QOSG.h index c085a79e0..791faf343 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_WR_I_MAIN_QOSG.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_WR_I_MAIN_QOSG.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_I_PXP_wr_I_main_QosG @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_I_PXP_wr_I_main_QosG.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_I_PXP_wr_I_main_QosG.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_I_PXP_wr_I_main_QosG * * CMSIS Peripheral Access Layer for NOC_I_PXP_wr_I_main_QosG */ -#if !defined(NOC_I_PXP_wr_I_main_QosG_H_) -#define NOC_I_PXP_wr_I_main_QosG_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_I_PXP_WR_I_MAIN_QOSG_H_) +#define PERI_NOC_I_PXP_WR_I_MAIN_QOSG_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_I_PXP_wr_I_main_QosG_H_ */ +#endif /* PERI_NOC_I_PXP_WR_I_MAIN_QOSG_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_WR_I_MAIN_TRANSTATFLTR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_WR_I_MAIN_TRANSTATFLTR.h index f0943e037..fd8546ee5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_WR_I_MAIN_TRANSTATFLTR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_I_PXP_WR_I_MAIN_TRANSTATFLTR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_I_PXP_wr_I_main_TranStatFltr @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_I_PXP_wr_I_main_TranStatFltr.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_I_PXP_wr_I_main_TranStatFltr.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_I_PXP_wr_I_main_TranStatFltr * * CMSIS Peripheral Access Layer for NOC_I_PXP_wr_I_main_TranStatFltr */ -#if !defined(NOC_I_PXP_wr_I_main_TranStatFltr_H_) -#define NOC_I_PXP_wr_I_main_TranStatFltr_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_I_PXP_WR_I_MAIN_TRANSTATFLTR_H_) +#define PERI_NOC_I_PXP_WR_I_MAIN_TRANSTATFLTR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -358,5 +361,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_I_PXP_wr_I_main_TranStatFltr_H_ */ +#endif /* PERI_NOC_I_PXP_WR_I_MAIN_TRANSTATFLTR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_LSTCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_LSTCU.h index bb7042b05..ac468082b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_LSTCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_LSTCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_LSTCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_LSTCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_LSTCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_LSTCU * * CMSIS Peripheral Access Layer for NOC_LSTCU */ -#if !defined(NOC_LSTCU_H_) -#define NOC_LSTCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_LSTCU_H_) +#define PERI_NOC_LSTCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -399,5 +402,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_LSTCU_H_ */ +#endif /* PERI_NOC_LSTCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_RD_I_MAIN_TRANSTATFILT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_RD_I_MAIN_TRANSTATFILT.h index 855dade54..70be85590 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_RD_I_MAIN_TRANSTATFILT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_RD_I_MAIN_TRANSTATFILT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_0_rd_I_main_TranStatFilt @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_0_rd_I_main_TranStatFilt.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_0_rd_I_main_TranStatFilt.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_0_rd_I_main_TranStatFilt * * CMSIS Peripheral Access Layer for NOC_m_e_0_rd_I_main_TranStatFilt */ -#if !defined(NOC_m_e_0_rd_I_main_TranStatFilt_H_) -#define NOC_m_e_0_rd_I_main_TranStatFilt_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_0_RD_I_MAIN_TRANSTATFILT_H_) +#define PERI_NOC_M_E_0_RD_I_MAIN_TRANSTATFILT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_0_rd_I_main_TranStatFilt_H_ */ +#endif /* PERI_NOC_M_E_0_RD_I_MAIN_TRANSTATFILT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_RD_I_M_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_RD_I_M_QOSGEN.h index 3fea7465f..1fdc02bf6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_RD_I_M_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_RD_I_M_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_0_rd_I_m_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_0_rd_I_m_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_0_rd_I_m_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_0_rd_I_m_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_0_rd_I_m_QosGen */ -#if !defined(NOC_m_e_0_rd_I_m_QosGen_H_) -#define NOC_m_e_0_rd_I_m_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_0_RD_I_M_QOSGEN_H_) +#define PERI_NOC_M_E_0_RD_I_M_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_0_rd_I_m_QosGen_H_ */ +#endif /* PERI_NOC_M_E_0_RD_I_M_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_WR_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_WR_I_MAIN_QOSGEN.h index 2b44df574..87d90e078 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_WR_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_WR_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_0_wr_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_0_wr_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_0_wr_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_0_wr_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_0_wr_I_main_QosGen */ -#if !defined(NOC_m_e_0_wr_I_main_QosGen_H_) -#define NOC_m_e_0_wr_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_0_WR_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_0_WR_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_0_wr_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_0_WR_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_WR_I_MAIN_TRANSTATFILT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_WR_I_MAIN_TRANSTATFILT.h index b4f74bac9..e3bc3908e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_WR_I_MAIN_TRANSTATFILT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_0_WR_I_MAIN_TRANSTATFILT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_0_wr_I_main_TranStatFilt @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_0_wr_I_main_TranStatFilt.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_0_wr_I_main_TranStatFilt.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_0_wr_I_main_TranStatFilt * * CMSIS Peripheral Access Layer for NOC_m_e_0_wr_I_main_TranStatFilt */ -#if !defined(NOC_m_e_0_wr_I_main_TranStatFilt_H_) -#define NOC_m_e_0_wr_I_main_TranStatFilt_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_0_WR_I_MAIN_TRANSTATFILT_H_) +#define PERI_NOC_M_E_0_WR_I_MAIN_TRANSTATFILT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_0_wr_I_main_TranStatFilt_H_ */ +#endif /* PERI_NOC_M_E_0_WR_I_MAIN_TRANSTATFILT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1A_RD_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1A_RD_I_MAIN_QOSGEN.h index f0dcb53f9..becacd1f2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1A_RD_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1A_RD_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_1a_rd_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_1a_rd_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_1a_rd_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_1a_rd_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_1a_rd_I_main_QosGen */ -#if !defined(NOC_m_e_1a_rd_I_main_QosGen_H_) -#define NOC_m_e_1a_rd_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_1A_RD_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_1A_RD_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_1a_rd_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_1A_RD_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1A_WR_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1A_WR_I_MAIN_QOSGEN.h index 5d34fcabe..aa6937e88 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1A_WR_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1A_WR_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_1a_wr_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_1a_wr_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_1a_wr_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_1a_wr_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_1a_wr_I_main_QosGen */ -#if !defined(NOC_m_e_1a_wr_I_main_QosGen_H_) -#define NOC_m_e_1a_wr_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_1A_WR_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_1A_WR_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_1a_wr_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_1A_WR_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1B_RD_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1B_RD_I_MAIN_QOSGEN.h index fb60c5fce..24136a0f1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1B_RD_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1B_RD_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_1b_rd_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_1b_rd_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_1b_rd_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_1b_rd_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_1b_rd_I_main_QosGen */ -#if !defined(NOC_m_e_1b_rd_I_main_QosGen_H_) -#define NOC_m_e_1b_rd_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_1B_RD_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_1B_RD_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_1b_rd_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_1B_RD_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1B_WR_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1B_WR_I_MAIN_QOSGEN.h index 7f6ee8292..70efc56dd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1B_WR_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_1B_WR_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_1b_wr_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_1b_wr_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_1b_wr_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_1b_wr_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_1b_wr_I_main_QosGen */ -#if !defined(NOC_m_e_1b_wr_I_main_QosGen_H_) -#define NOC_m_e_1b_wr_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_1B_WR_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_1B_WR_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_1b_wr_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_1B_WR_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_RD_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_RD_I_MAIN_QOSGEN.h index 928408113..e46bb5e4f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_RD_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_RD_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_3_rd_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_3_rd_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_3_rd_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_3_rd_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_3_rd_I_main_QosGen */ -#if !defined(NOC_m_e_3_rd_I_main_QosGen_H_) -#define NOC_m_e_3_rd_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_3_RD_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_3_RD_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_3_rd_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_3_RD_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_RD_I_MAIN_TRANSTATFILT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_RD_I_MAIN_TRANSTATFILT.h index 7809f6cdd..06a39780f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_RD_I_MAIN_TRANSTATFILT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_RD_I_MAIN_TRANSTATFILT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_3_rd_I_main_TranStatFilt @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_3_rd_I_main_TranStatFilt.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_3_rd_I_main_TranStatFilt.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_3_rd_I_main_TranStatFilt * * CMSIS Peripheral Access Layer for NOC_m_e_3_rd_I_main_TranStatFilt */ -#if !defined(NOC_m_e_3_rd_I_main_TranStatFilt_H_) -#define NOC_m_e_3_rd_I_main_TranStatFilt_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_3_RD_I_MAIN_TRANSTATFILT_H_) +#define PERI_NOC_M_E_3_RD_I_MAIN_TRANSTATFILT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_3_rd_I_main_TranStatFilt_H_ */ +#endif /* PERI_NOC_M_E_3_RD_I_MAIN_TRANSTATFILT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_WR_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_WR_I_MAIN_QOSGEN.h index 213c3b68f..e4d5f5d63 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_WR_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_3_WR_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_3_wr_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_3_wr_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_3_wr_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_3_wr_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_3_wr_I_main_QosGen */ -#if !defined(NOC_m_e_3_wr_I_main_QosGen_H_) -#define NOC_m_e_3_wr_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_3_WR_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_3_WR_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_3_wr_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_3_WR_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_RD_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_RD_I_MAIN_QOSGEN.h index 7484ea158..b45b8b828 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_RD_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_RD_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_6_rd_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_6_rd_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_6_rd_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_6_rd_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_6_rd_I_main_QosGen */ -#if !defined(NOC_m_e_6_rd_I_main_QosGen_H_) -#define NOC_m_e_6_rd_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_6_RD_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_6_RD_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_6_rd_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_6_RD_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_RD_I_MAIN_TRANSTATFILT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_RD_I_MAIN_TRANSTATFILT.h index aa0f23cfa..6847200e0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_RD_I_MAIN_TRANSTATFILT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_RD_I_MAIN_TRANSTATFILT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_6_rd_I_main_TranStatFilt @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_6_rd_I_main_TranStatFilt.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_6_rd_I_main_TranStatFilt.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_6_rd_I_main_TranStatFilt * * CMSIS Peripheral Access Layer for NOC_m_e_6_rd_I_main_TranStatFilt */ -#if !defined(NOC_m_e_6_rd_I_main_TranStatFilt_H_) -#define NOC_m_e_6_rd_I_main_TranStatFilt_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_6_RD_I_MAIN_TRANSTATFILT_H_) +#define PERI_NOC_M_E_6_RD_I_MAIN_TRANSTATFILT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_6_rd_I_main_TranStatFilt_H_ */ +#endif /* PERI_NOC_M_E_6_RD_I_MAIN_TRANSTATFILT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_WR_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_WR_I_MAIN_QOSGEN.h index bf92473fe..3670611ca 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_WR_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_WR_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_6_wr_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_6_wr_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_6_wr_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_6_wr_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_6_wr_I_main_QosGen */ -#if !defined(NOC_m_e_6_wr_I_main_QosGen_H_) -#define NOC_m_e_6_wr_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_6_WR_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_6_WR_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_6_wr_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_6_WR_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_WR_I_MAIN_TRANSTATFILT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_WR_I_MAIN_TRANSTATFILT.h index cd34bf01b..97289916a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_WR_I_MAIN_TRANSTATFILT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_6_WR_I_MAIN_TRANSTATFILT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_6_wr_I_main_TranStatFilt @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_6_wr_I_main_TranStatFilt.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_6_wr_I_main_TranStatFilt.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_6_wr_I_main_TranStatFilt * * CMSIS Peripheral Access Layer for NOC_m_e_6_wr_I_main_TranStatFilt */ -#if !defined(NOC_m_e_6_wr_I_main_TranStatFilt_H_) -#define NOC_m_e_6_wr_I_main_TranStatFilt_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_6_WR_I_MAIN_TRANSTATFILT_H_) +#define PERI_NOC_M_E_6_WR_I_MAIN_TRANSTATFILT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_6_wr_I_main_TranStatFilt_H_ */ +#endif /* PERI_NOC_M_E_6_WR_I_MAIN_TRANSTATFILT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_RD_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_RD_I_MAIN_QOSGEN.h index c99c9a2a5..08e5d8002 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_RD_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_RD_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_7_rd_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_7_rd_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_7_rd_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_7_rd_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_7_rd_I_main_QosGen */ -#if !defined(NOC_m_e_7_rd_I_main_QosGen_H_) -#define NOC_m_e_7_rd_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_7_RD_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_7_RD_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_7_rd_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_7_RD_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_RD_I_MAIN_TRANSTATFILT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_RD_I_MAIN_TRANSTATFILT.h index 5c4a359da..c01f28b01 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_RD_I_MAIN_TRANSTATFILT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_RD_I_MAIN_TRANSTATFILT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_7_rd_I_main_TranStatFilt @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_7_rd_I_main_TranStatFilt.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_7_rd_I_main_TranStatFilt.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_7_rd_I_main_TranStatFilt * * CMSIS Peripheral Access Layer for NOC_m_e_7_rd_I_main_TranStatFilt */ -#if !defined(NOC_m_e_7_rd_I_main_TranStatFilt_H_) -#define NOC_m_e_7_rd_I_main_TranStatFilt_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_7_RD_I_MAIN_TRANSTATFILT_H_) +#define PERI_NOC_M_E_7_RD_I_MAIN_TRANSTATFILT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_7_rd_I_main_TranStatFilt_H_ */ +#endif /* PERI_NOC_M_E_7_RD_I_MAIN_TRANSTATFILT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_WR_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_WR_I_MAIN_QOSGEN.h index f497964a1..f8a5c4712 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_WR_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_WR_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_7_wr_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_7_wr_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_7_wr_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_7_wr_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_7_wr_I_main_QosGen */ -#if !defined(NOC_m_e_7_wr_I_main_QosGen_H_) -#define NOC_m_e_7_wr_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_7_WR_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_7_WR_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_7_wr_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_7_WR_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_WR_I_MAIN_TRANSTATFILT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_WR_I_MAIN_TRANSTATFILT.h index a02a73478..8efcbcb64 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_WR_I_MAIN_TRANSTATFILT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_7_WR_I_MAIN_TRANSTATFILT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_7_wr_I_main_TranStatFilt @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_7_wr_I_main_TranStatFilt.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_7_wr_I_main_TranStatFilt.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_7_wr_I_main_TranStatFilt * * CMSIS Peripheral Access Layer for NOC_m_e_7_wr_I_main_TranStatFilt */ -#if !defined(NOC_m_e_7_wr_I_main_TranStatFilt_H_) -#define NOC_m_e_7_wr_I_main_TranStatFilt_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_7_WR_I_MAIN_TRANSTATFILT_H_) +#define PERI_NOC_M_E_7_WR_I_MAIN_TRANSTATFILT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_7_wr_I_main_TranStatFilt_H_ */ +#endif /* PERI_NOC_M_E_7_WR_I_MAIN_TRANSTATFILT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_RD_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_RD_I_MAIN_QOSGEN.h index ab0c10eaf..4867b41c1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_RD_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_RD_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_9_rd_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_9_rd_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_9_rd_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_9_rd_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_9_rd_I_main_QosGen */ -#if !defined(NOC_m_e_9_rd_I_main_QosGen_H_) -#define NOC_m_e_9_rd_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_9_RD_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_9_RD_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_9_rd_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_9_RD_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_WR_I_MAIN_QOSGEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_WR_I_MAIN_QOSGEN.h index 54af9867b..3b034a4e3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_WR_I_MAIN_QOSGEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_WR_I_MAIN_QOSGEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_9_wr_I_main_QosGen @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_9_wr_I_main_QosGen.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_9_wr_I_main_QosGen.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_9_wr_I_main_QosGen * * CMSIS Peripheral Access Layer for NOC_m_e_9_wr_I_main_QosGen */ -#if !defined(NOC_m_e_9_wr_I_main_QosGen_H_) -#define NOC_m_e_9_wr_I_main_QosGen_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_9_WR_I_MAIN_QOSGEN_H_) +#define PERI_NOC_M_E_9_WR_I_MAIN_QOSGEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -359,5 +362,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_9_wr_I_main_QosGen_H_ */ +#endif /* PERI_NOC_M_E_9_WR_I_MAIN_QOSGEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_WR_I_MAIN_TRANSTATFILT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_WR_I_MAIN_TRANSTATFILT.h index 2bba90bf8..e6f261bae 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_WR_I_MAIN_TRANSTATFILT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_M_E_9_WR_I_MAIN_TRANSTATFILT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_m_e_9_wr_I_main_TranStatFilt @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_m_e_9_wr_I_main_TranStatFilt.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_m_e_9_wr_I_main_TranStatFilt.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_m_e_9_wr_I_main_TranStatFilt * * CMSIS Peripheral Access Layer for NOC_m_e_9_wr_I_main_TranStatFilt */ -#if !defined(NOC_m_e_9_wr_I_main_TranStatFilt_H_) -#define NOC_m_e_9_wr_I_main_TranStatFilt_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_M_E_9_WR_I_MAIN_TRANSTATFILT_H_) +#define PERI_NOC_M_E_9_WR_I_MAIN_TRANSTATFILT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -366,5 +369,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_m_e_9_wr_I_main_TranStatFilt_H_ */ +#endif /* PERI_NOC_M_E_9_WR_I_MAIN_TRANSTATFILT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_LCDIF_RD_MAIN_PROBE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_LCDIF_RD_MAIN_PROBE.h index eb76d5ad4..2371d67f5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_LCDIF_RD_MAIN_PROBE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_LCDIF_RD_MAIN_PROBE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_LCDIF_rd_main_Probe @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_LCDIF_rd_main_Probe.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_LCDIF_rd_main_Probe.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_LCDIF_rd_main_Probe * * CMSIS Peripheral Access Layer for NOC_Probe_LCDIF_rd_main_Probe */ -#if !defined(NOC_Probe_LCDIF_rd_main_Probe_H_) -#define NOC_Probe_LCDIF_rd_main_Probe_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_LCDIF_RD_MAIN_PROBE_H_) +#define PERI_NOC_PROBE_LCDIF_RD_MAIN_PROBE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -438,5 +441,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_LCDIF_rd_main_Probe_H_ */ +#endif /* PERI_NOC_PROBE_LCDIF_RD_MAIN_PROBE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_LCDIF_RD_MAIN_TRSTPROF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_LCDIF_RD_MAIN_TRSTPROF.h index 53263f95e..35b641341 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_LCDIF_RD_MAIN_TRSTPROF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_LCDIF_RD_MAIN_TRSTPROF.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_LCDIF_rd_main_TrStProf @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_LCDIF_rd_main_TrStProf.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_LCDIF_rd_main_TrStProf.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_LCDIF_rd_main_TrStProf * * CMSIS Peripheral Access Layer for NOC_Probe_LCDIF_rd_main_TrStProf */ -#if !defined(NOC_Probe_LCDIF_rd_main_TrStProf_H_) -#define NOC_Probe_LCDIF_rd_main_TrStProf_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_LCDIF_RD_MAIN_TRSTPROF_H_) +#define PERI_NOC_PROBE_LCDIF_RD_MAIN_TRSTPROF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -390,5 +393,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_LCDIF_rd_main_TrStProf_H_ */ +#endif /* PERI_NOC_PROBE_LCDIF_RD_MAIN_TRSTPROF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_0_MAIN_PROBE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_0_MAIN_PROBE.h index 2b260a817..a72567bb3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_0_MAIN_PROBE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_0_MAIN_PROBE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_0_main_Probe @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_0_main_Probe.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_0_main_Probe.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_0_main_Probe * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_0_main_Probe */ -#if !defined(NOC_Probe_m_e_0_main_Probe_H_) -#define NOC_Probe_m_e_0_main_Probe_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_0_MAIN_PROBE_H_) +#define PERI_NOC_PROBE_M_E_0_MAIN_PROBE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -438,5 +441,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_0_main_Probe_H_ */ +#endif /* PERI_NOC_PROBE_M_E_0_MAIN_PROBE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_0_MAIN_TRANSTATPROF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_0_MAIN_TRANSTATPROF.h index c5446e65f..6e5318e11 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_0_MAIN_TRANSTATPROF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_0_MAIN_TRANSTATPROF.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_0_main_TranStatProf @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_0_main_TranStatProf.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_0_main_TranStatProf.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_0_main_TranStatProf * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_0_main_TranStatProf */ -#if !defined(NOC_Probe_m_e_0_main_TranStatProf_H_) -#define NOC_Probe_m_e_0_main_TranStatProf_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_0_MAIN_TRANSTATPROF_H_) +#define PERI_NOC_PROBE_M_E_0_MAIN_TRANSTATPROF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -405,5 +408,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_0_main_TranStatProf_H_ */ +#endif /* PERI_NOC_PROBE_M_E_0_MAIN_TRANSTATPROF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_3_MAIN_PROBE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_3_MAIN_PROBE.h index 5da044e40..d588ea5e2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_3_MAIN_PROBE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_3_MAIN_PROBE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_3_main_Probe @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_3_main_Probe.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_3_main_Probe.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_3_main_Probe * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_3_main_Probe */ -#if !defined(NOC_Probe_m_e_3_main_Probe_H_) -#define NOC_Probe_m_e_3_main_Probe_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_3_MAIN_PROBE_H_) +#define PERI_NOC_PROBE_M_E_3_MAIN_PROBE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -438,5 +441,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_3_main_Probe_H_ */ +#endif /* PERI_NOC_PROBE_M_E_3_MAIN_PROBE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_3_MAIN_TRANSTATPROF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_3_MAIN_TRANSTATPROF.h index c8aca5896..ab2a67fda 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_3_MAIN_TRANSTATPROF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_3_MAIN_TRANSTATPROF.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_3_main_TranStatProf @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_3_main_TranStatProf.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_3_main_TranStatProf.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_3_main_TranStatProf * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_3_main_TranStatProf */ -#if !defined(NOC_Probe_m_e_3_main_TranStatProf_H_) -#define NOC_Probe_m_e_3_main_TranStatProf_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_3_MAIN_TRANSTATPROF_H_) +#define PERI_NOC_PROBE_M_E_3_MAIN_TRANSTATPROF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -405,5 +408,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_3_main_TranStatProf_H_ */ +#endif /* PERI_NOC_PROBE_M_E_3_MAIN_TRANSTATPROF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_6_MAIN_PROBE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_6_MAIN_PROBE.h index fc66b3f48..b8468066c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_6_MAIN_PROBE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_6_MAIN_PROBE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_6_main_Probe @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_6_main_Probe.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_6_main_Probe.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_6_main_Probe * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_6_main_Probe */ -#if !defined(NOC_Probe_m_e_6_main_Probe_H_) -#define NOC_Probe_m_e_6_main_Probe_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_6_MAIN_PROBE_H_) +#define PERI_NOC_PROBE_M_E_6_MAIN_PROBE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -438,5 +441,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_6_main_Probe_H_ */ +#endif /* PERI_NOC_PROBE_M_E_6_MAIN_PROBE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_6_MAIN_TRANSTATPROF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_6_MAIN_TRANSTATPROF.h index 496adcf5f..b7d694ff6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_6_MAIN_TRANSTATPROF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_6_MAIN_TRANSTATPROF.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_6_main_TranStatProf @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_6_main_TranStatProf.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_6_main_TranStatProf.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_6_main_TranStatProf * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_6_main_TranStatProf */ -#if !defined(NOC_Probe_m_e_6_main_TranStatProf_H_) -#define NOC_Probe_m_e_6_main_TranStatProf_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_6_MAIN_TRANSTATPROF_H_) +#define PERI_NOC_PROBE_M_E_6_MAIN_TRANSTATPROF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -405,5 +408,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_6_main_TranStatProf_H_ */ +#endif /* PERI_NOC_PROBE_M_E_6_MAIN_TRANSTATPROF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_7_MAIN_PROBE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_7_MAIN_PROBE.h index 9b1c68737..abe786737 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_7_MAIN_PROBE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_7_MAIN_PROBE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_7_main_Probe @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_7_main_Probe.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_7_main_Probe.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_7_main_Probe * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_7_main_Probe */ -#if !defined(NOC_Probe_m_e_7_main_Probe_H_) -#define NOC_Probe_m_e_7_main_Probe_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_7_MAIN_PROBE_H_) +#define PERI_NOC_PROBE_M_E_7_MAIN_PROBE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -438,5 +441,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_7_main_Probe_H_ */ +#endif /* PERI_NOC_PROBE_M_E_7_MAIN_PROBE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_7_MAIN_TRANSTATPROF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_7_MAIN_TRANSTATPROF.h index 302c87323..9d704387f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_7_MAIN_TRANSTATPROF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_7_MAIN_TRANSTATPROF.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_7_main_TranStatProf @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_7_main_TranStatProf.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_7_main_TranStatProf.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_7_main_TranStatProf * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_7_main_TranStatProf */ -#if !defined(NOC_Probe_m_e_7_main_TranStatProf_H_) -#define NOC_Probe_m_e_7_main_TranStatProf_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_7_MAIN_TRANSTATPROF_H_) +#define PERI_NOC_PROBE_M_E_7_MAIN_TRANSTATPROF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -405,5 +408,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_7_main_TranStatProf_H_ */ +#endif /* PERI_NOC_PROBE_M_E_7_MAIN_TRANSTATPROF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_9_MAIN_PROBE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_9_MAIN_PROBE.h index 3c9465aef..2dfbafe1c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_9_MAIN_PROBE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_9_MAIN_PROBE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_9_main_Probe @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_9_main_Probe.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_9_main_Probe.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_9_main_Probe * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_9_main_Probe */ -#if !defined(NOC_Probe_m_e_9_main_Probe_H_) -#define NOC_Probe_m_e_9_main_Probe_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_9_MAIN_PROBE_H_) +#define PERI_NOC_PROBE_M_E_9_MAIN_PROBE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -438,5 +441,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_9_main_Probe_H_ */ +#endif /* PERI_NOC_PROBE_M_E_9_MAIN_PROBE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_9_MAIN_TRANSTATPROF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_9_MAIN_TRANSTATPROF.h index 1c40300d7..15b967b24 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_9_MAIN_TRANSTATPROF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_M_E_9_MAIN_TRANSTATPROF.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_m_e_9_main_TranStatProf @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_m_e_9_main_TranStatProf.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_m_e_9_main_TranStatProf.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_m_e_9_main_TranStatProf * * CMSIS Peripheral Access Layer for NOC_Probe_m_e_9_main_TranStatProf */ -#if !defined(NOC_Probe_m_e_9_main_TranStatProf_H_) -#define NOC_Probe_m_e_9_main_TranStatProf_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_M_E_9_MAIN_TRANSTATPROF_H_) +#define PERI_NOC_PROBE_M_E_9_MAIN_TRANSTATPROF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -405,5 +408,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_m_e_9_main_TranStatProf_H_ */ +#endif /* PERI_NOC_PROBE_M_E_9_MAIN_TRANSTATPROF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_RD_MAIN_PROBE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_RD_MAIN_PROBE.h index f29dadc19..956749cb3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_RD_MAIN_PROBE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_RD_MAIN_PROBE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_PXP_rd_main_Probe @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_PXP_rd_main_Probe.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_PXP_rd_main_Probe.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_PXP_rd_main_Probe * * CMSIS Peripheral Access Layer for NOC_Probe_PXP_rd_main_Probe */ -#if !defined(NOC_Probe_PXP_rd_main_Probe_H_) -#define NOC_Probe_PXP_rd_main_Probe_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_PXP_RD_MAIN_PROBE_H_) +#define PERI_NOC_PROBE_PXP_RD_MAIN_PROBE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -438,5 +441,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_PXP_rd_main_Probe_H_ */ +#endif /* PERI_NOC_PROBE_PXP_RD_MAIN_PROBE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_RD_MAIN_TRSTPROF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_RD_MAIN_TRSTPROF.h index dec7c6533..4b732a2ee 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_RD_MAIN_TRSTPROF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_RD_MAIN_TRSTPROF.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_PXP_rd_main_TrStProf @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_PXP_rd_main_TrStProf.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_PXP_rd_main_TrStProf.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_PXP_rd_main_TrStProf * * CMSIS Peripheral Access Layer for NOC_Probe_PXP_rd_main_TrStProf */ -#if !defined(NOC_Probe_PXP_rd_main_TrStProf_H_) -#define NOC_Probe_PXP_rd_main_TrStProf_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_PXP_RD_MAIN_TRSTPROF_H_) +#define PERI_NOC_PROBE_PXP_RD_MAIN_TRSTPROF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -390,5 +393,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_PXP_rd_main_TrStProf_H_ */ +#endif /* PERI_NOC_PROBE_PXP_RD_MAIN_TRSTPROF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_WR_MAIN_PROBE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_WR_MAIN_PROBE.h index d026ca653..10a46324a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_WR_MAIN_PROBE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_WR_MAIN_PROBE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_PXP_wr_main_Probe @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_PXP_wr_main_Probe.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_PXP_wr_main_Probe.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_PXP_wr_main_Probe * * CMSIS Peripheral Access Layer for NOC_Probe_PXP_wr_main_Probe */ -#if !defined(NOC_Probe_PXP_wr_main_Probe_H_) -#define NOC_Probe_PXP_wr_main_Probe_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_PXP_WR_MAIN_PROBE_H_) +#define PERI_NOC_PROBE_PXP_WR_MAIN_PROBE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -438,5 +441,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_PXP_wr_main_Probe_H_ */ +#endif /* PERI_NOC_PROBE_PXP_WR_MAIN_PROBE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_WR_MAIN_TRSTPROF.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_WR_MAIN_TRSTPROF.h index 11e7cb29f..49ae5c7b2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_WR_MAIN_TRSTPROF.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_PROBE_PXP_WR_MAIN_TRSTPROF.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_Probe_PXP_wr_main_TrStProf @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_Probe_PXP_wr_main_TrStProf.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_Probe_PXP_wr_main_TrStProf.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_Probe_PXP_wr_main_TrStProf * * CMSIS Peripheral Access Layer for NOC_Probe_PXP_wr_main_TrStProf */ -#if !defined(NOC_Probe_PXP_wr_main_TrStProf_H_) -#define NOC_Probe_PXP_wr_main_TrStProf_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_PROBE_PXP_WR_MAIN_TRSTPROF_H_) +#define PERI_NOC_PROBE_PXP_WR_MAIN_TRSTPROF_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -390,5 +393,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_Probe_PXP_wr_main_TrStProf_H_ */ +#endif /* PERI_NOC_PROBE_PXP_WR_MAIN_TRSTPROF_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_TCU.h index bcdeeb136..88f3e29c2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_TCU * * CMSIS Peripheral Access Layer for NOC_TCU */ -#if !defined(NOC_TCU_H_) -#define NOC_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_TCU_H_) +#define PERI_NOC_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -330,5 +333,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_TCU_H_ */ +#endif /* PERI_NOC_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_TRDC_MGR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_TRDC_MGR.h index 975ddf3f3..95387dc39 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_TRDC_MGR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NOC_TRDC_MGR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NOC_TRDC_MGR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NOC_TRDC_MGR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NOC_TRDC_MGR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NOC_TRDC_MGR * * CMSIS Peripheral Access Layer for NOC_TRDC_MGR */ -#if !defined(NOC_TRDC_MGR_H_) -#define NOC_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NOC_TRDC_MGR_H_) +#define PERI_NOC_TRDC_MGR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -222586,5 +222589,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NOC_TRDC_MGR_H_ */ +#endif /* PERI_NOC_TRDC_MGR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_EIM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_EIM.h index dfc9d36ae..2f71fe301 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_EIM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_EIM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NPU_EIM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NPU_EIM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NPU_EIM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NPU_EIM * * CMSIS Peripheral Access Layer for NPU_EIM */ -#if !defined(NPU_EIM_H_) -#define NPU_EIM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NPU_EIM_H_) +#define PERI_NPU_EIM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -378,5 +381,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NPU_EIM_H_ */ +#endif /* PERI_NPU_EIM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_ERM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_ERM.h index 017a67edf..8da96d2c0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_ERM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_ERM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NPU_ERM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NPU_ERM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NPU_ERM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NPU_ERM * * CMSIS Peripheral Access Layer for NPU_ERM */ -#if !defined(NPU_ERM_H_) -#define NPU_ERM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NPU_ERM_H_) +#define PERI_NPU_ERM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -346,5 +349,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NPU_ERM_H_ */ +#endif /* PERI_NPU_ERM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_LSTCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_LSTCU.h index 0cd142aba..69acca084 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_LSTCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_LSTCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NPU_LSTCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NPU_LSTCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NPU_LSTCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NPU_LSTCU * * CMSIS Peripheral Access Layer for NPU_LSTCU */ -#if !defined(NPU_LSTCU_H_) -#define NPU_LSTCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NPU_LSTCU_H_) +#define PERI_NPU_LSTCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -399,5 +402,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NPU_LSTCU_H_ */ +#endif /* PERI_NPU_LSTCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_TCU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_TCU.h index c73e6373c..b470bc926 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_TCU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_NPU_TCU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NPU_TCU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file NPU_TCU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_NPU_TCU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for NPU_TCU * * CMSIS Peripheral Access Layer for NPU_TCU */ -#if !defined(NPU_TCU_H_) -#define NPU_TCU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_NPU_TCU_H_) +#define PERI_NPU_TCU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -346,5 +349,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* NPU_TCU_H_ */ +#endif /* PERI_NPU_TCU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_OSC24M.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_OSC24M.h index fcfa6db4b..aae84a532 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_OSC24M.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_OSC24M.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSC24M @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file OSC24M.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_OSC24M.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for OSC24M * * CMSIS Peripheral Access Layer for OSC24M */ -#if !defined(OSC24M_H_) -#define OSC24M_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_OSC24M_H_) +#define PERI_OSC24M_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -293,5 +296,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* OSC24M_H_ */ +#endif /* PERI_OSC24M_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_DMA_IATU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_DMA_IATU.h index d62dde062..100b49a30 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_DMA_IATU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_DMA_IATU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PCIE_DMA_IATU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PCIE_DMA_IATU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_PCIE_DMA_IATU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PCIE_DMA_IATU * * CMSIS Peripheral Access Layer for PCIE_DMA_IATU */ -#if !defined(PCIE_DMA_IATU_H_) -#define PCIE_DMA_IATU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PCIE_DMA_IATU_H_) +#define PERI_PCIE_DMA_IATU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -6302,5 +6305,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PCIE_DMA_IATU_H_ */ +#endif /* PERI_PCIE_DMA_IATU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_EP.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_EP.h index 39bf4247c..47df23153 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_EP.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_EP.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PCIE_EP @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PCIE_EP.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_PCIE_EP.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PCIE_EP * * CMSIS Peripheral Access Layer for PCIE_EP */ -#if !defined(PCIE_EP_H_) -#define PCIE_EP_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PCIE_EP_H_) +#define PERI_PCIE_EP_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -4547,5 +4550,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PCIE_EP_H_ */ +#endif /* PERI_PCIE_EP_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_RC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_RC.h index 27ce9b82d..7f25181f1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_RC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_RC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PCIE_RC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PCIE_RC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_PCIE_RC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PCIE_RC * * CMSIS Peripheral Access Layer for PCIE_RC */ -#if !defined(PCIE_RC_H_) -#define PCIE_RC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PCIE_RC_H_) +#define PERI_PCIE_RC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -5287,5 +5290,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PCIE_RC_H_ */ +#endif /* PERI_PCIE_RC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_SHADOW_EP.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_SHADOW_EP.h index 80dcfba92..882597677 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_SHADOW_EP.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PCIE_SHADOW_EP.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PCIE_SHADOW_EP @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PCIE_SHADOW_EP.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_PCIE_SHADOW_EP.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PCIE_SHADOW_EP * * CMSIS Peripheral Access Layer for PCIE_SHADOW_EP */ -#if !defined(PCIE_SHADOW_EP_H_) -#define PCIE_SHADOW_EP_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PCIE_SHADOW_EP_H_) +#define PERI_PCIE_SHADOW_EP_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -379,5 +382,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PCIE_SHADOW_EP_H_ */ +#endif /* PERI_PCIE_SHADOW_EP_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PDM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PDM.h index c97d41525..a579828f2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PDM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PDM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PDM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PDM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_PDM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PDM * * CMSIS Peripheral Access Layer for PDM */ -#if !defined(PDM_H_) -#define PDM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PDM_H_) +#define PERI_PDM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1481,5 +1484,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PDM_H_ */ +#endif /* PERI_PDM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PLL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PLL.h index d69762fe8..4c6e3ed44 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PLL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PLL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PLL @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PLL.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_PLL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PLL * * CMSIS Peripheral Access Layer for PLL */ -#if !defined(PLL_H_) -#define PLL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PLL_H_) +#define PERI_PLL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -542,5 +545,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PLL_H_ */ +#endif /* PERI_PLL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PWM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PWM.h index a879067b4..85d6775f0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PWM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PWM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PWM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PWM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_PWM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PWM * * CMSIS Peripheral Access Layer for PWM */ -#if !defined(PWM_H_) -#define PWM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PWM_H_) +#define PERI_PWM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1954,5 +1957,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PWM_H_ */ +#endif /* PERI_PWM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PXP.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PXP.h index 81dfbcedb..67bced1ce 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PXP.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_PXP.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PXP @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file PXP.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_PXP.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for PXP * * CMSIS Peripheral Access Layer for PXP */ -#if !defined(PXP_H_) -#define PXP_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_PXP_H_) +#define PERI_PXP_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -331,32 +334,32 @@ typedef struct { uint8_t RESERVED_40[12]; __IO uint32_t POWER_REG1; /**< Power Control Register 1, offset: 0x330 */ uint8_t RESERVED_41[12]; - __IO uint32_t DATA_PATH_CTRL0; /**< Data Path Control 0 Register, offset: 0x340 */ - __IO uint32_t DATA_PATH_CTRL0_SET; /**< Data Path Control 0 Register, offset: 0x344 */ - __IO uint32_t DATA_PATH_CTRL0_CLR; /**< Data Path Control 0 Register, offset: 0x348 */ - __IO uint32_t DATA_PATH_CTRL0_TOG; /**< Data Path Control 0 Register, offset: 0x34C */ - uint8_t RESERVED_42[64]; - __IO uint32_t IRQ_MASK; /**< PXP IRQ Mask Register, offset: 0x390 */ - __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ - __IO uint32_t IRQ_MASK_CLR; /**< PXP IRQ Mask Register, offset: 0x398 */ - __IO uint32_t IRQ_MASK_TOG; /**< PXP IRQ Mask Register, offset: 0x39C */ - __IO uint32_t IRQ; /**< PXP Interrupt Register, offset: 0x3A0 */ - __IO uint32_t IRQ_SET; /**< PXP Interrupt Register, offset: 0x3A4 */ - __IO uint32_t IRQ_CLR; /**< PXP Interrupt Register, offset: 0x3A8 */ - __IO uint32_t IRQ_TOG; /**< PXP Interrupt Register, offset: 0x3AC */ + __IO uint32_t DATA_PATH_CTRL0; /**< Data Path Control 0 Register, offset: 0x340 */ + __IO uint32_t DATA_PATH_CTRL0_SET; /**< Data Path Control 0 Register, offset: 0x344 */ + __IO uint32_t DATA_PATH_CTRL0_CLR; /**< Data Path Control 0 Register, offset: 0x348 */ + __IO uint32_t DATA_PATH_CTRL0_TOG; /**< Data Path Control 0 Register, offset: 0x34C */ + uint8_t RESERVED_42[64]; + __IO uint32_t IRQ_MASK; /**< IRQ Mask Register, offset: 0x390 */ + __IO uint32_t IRQ_MASK_SET; /**< IRQ Mask Register, offset: 0x394 */ + __IO uint32_t IRQ_MASK_CLR; /**< IRQ Mask Register, offset: 0x398 */ + __IO uint32_t IRQ_MASK_TOG; /**< IRQ Mask Register, offset: 0x39C */ + __IO uint32_t IRQ; /**< Interrupt Register, offset: 0x3A0 */ + __IO uint32_t IRQ_SET; /**< Interrupt Register, offset: 0x3A4 */ + __IO uint32_t IRQ_CLR; /**< Interrupt Register, offset: 0x3A8 */ + __IO uint32_t IRQ_TOG; /**< Interrupt Register, offset: 0x3AC */ uint8_t RESERVED_43[80]; __IO uint32_t NEXT; /**< Next Frame Pointer Register, offset: 0x400 */ uint8_t RESERVED_44[60]; __IO uint32_t OUT_BUF3; /**< Output Frame Buffer Pointer #3 Register, offset: 0x440 */ uint8_t RESERVED_45[12]; - __IO uint32_t INPUT_FETCH_CTRL_CH0; /**< Pre-fetch engine Control Channel 0 Register, offset: 0x450 */ - __IO uint32_t INPUT_FETCH_CTRL_CH0_SET; /**< Pre-fetch engine Control Channel 0 Register, offset: 0x454 */ - __IO uint32_t INPUT_FETCH_CTRL_CH0_CLR; /**< Pre-fetch engine Control Channel 0 Register, offset: 0x458 */ - __IO uint32_t INPUT_FETCH_CTRL_CH0_TOG; /**< Pre-fetch engine Control Channel 0 Register, offset: 0x45C */ - __IO uint32_t INPUT_FETCH_CTRL_CH1; /**< Pre-fetch engine Control Channel 1 Register, offset: 0x460 */ - __IO uint32_t INPUT_FETCH_CTRL_CH1_SET; /**< Pre-fetch engine Control Channel 1 Register, offset: 0x464 */ - __IO uint32_t INPUT_FETCH_CTRL_CH1_CLR; /**< Pre-fetch engine Control Channel 1 Register, offset: 0x468 */ - __IO uint32_t INPUT_FETCH_CTRL_CH1_TOG; /**< Pre-fetch engine Control Channel 1 Register, offset: 0x46C */ + __IO uint32_t INPUT_FETCH_CTRL_CH0; /**< Input Fetch Control Channel 0 Register, offset: 0x450 */ + __IO uint32_t INPUT_FETCH_CTRL_CH0_SET; /**< Input Fetch Control Channel 0 Register, offset: 0x454 */ + __IO uint32_t INPUT_FETCH_CTRL_CH0_CLR; /**< Input Fetch Control Channel 0 Register, offset: 0x458 */ + __IO uint32_t INPUT_FETCH_CTRL_CH0_TOG; /**< Input Fetch Control Channel 0 Register, offset: 0x45C */ + __IO uint32_t INPUT_FETCH_CTRL_CH1; /**< Input Fetch Control Channel 1 Register, offset: 0x460 */ + __IO uint32_t INPUT_FETCH_CTRL_CH1_SET; /**< Input Fetch Control Channel 1 Register, offset: 0x464 */ + __IO uint32_t INPUT_FETCH_CTRL_CH1_CLR; /**< Input Fetch Control Channel 1 Register, offset: 0x468 */ + __IO uint32_t INPUT_FETCH_CTRL_CH1_TOG; /**< Input Fetch Control Channel 1 Register, offset: 0x46C */ __I uint32_t INPUT_FETCH_STATUS_CH0; /**< Input Fetch Status Channel 0 Register, offset: 0x470 */ uint8_t RESERVED_46[12]; __I uint32_t INPUT_FETCH_STATUS_CH1; /**< Input Fetch Status Channel 1 Register, offset: 0x480 */ @@ -379,30 +382,30 @@ typedef struct { uint8_t RESERVED_55[12]; __IO uint32_t INPUT_FETCH_PITCH; /**< Input Fetch Pitch Register, offset: 0x510 */ uint8_t RESERVED_56[12]; - __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0; /**< offset: 0x520 */ - __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0_SET; /**< offset: 0x524 */ - __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0_CLR; /**< offset: 0x528 */ - __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0_TOG; /**< offset: 0x52C */ - __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1; /**< offset: 0x530 */ - __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1_SET; /**< offset: 0x534 */ - __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1_CLR; /**< offset: 0x538 */ - __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1_TOG; /**< offset: 0x53C */ - __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0; /**< offset: 0x540 */ - __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0_SET; /**< offset: 0x544 */ - __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0_CLR; /**< offset: 0x548 */ - __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0_TOG; /**< offset: 0x54C */ - __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1; /**< offset: 0x550 */ - __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1_SET; /**< offset: 0x554 */ - __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1_CLR; /**< offset: 0x558 */ - __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1_TOG; /**< offset: 0x55C */ - __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0; /**< offset: 0x560 */ - __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0_SET; /**< offset: 0x564 */ - __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0_CLR; /**< offset: 0x568 */ - __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0_TOG; /**< offset: 0x56C */ - __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1; /**< offset: 0x570 */ - __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1_SET; /**< offset: 0x574 */ - __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1_CLR; /**< offset: 0x578 */ - __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1_TOG; /**< offset: 0x57C */ + __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0; /**< Input Fetch Shift Control Channel 0 Register, offset: 0x520 */ + __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0_SET; /**< Input Fetch Shift Control Channel 0 Register, offset: 0x524 */ + __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0_CLR; /**< Input Fetch Shift Control Channel 0 Register, offset: 0x528 */ + __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH0_TOG; /**< Input Fetch Shift Control Channel 0 Register, offset: 0x52C */ + __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1; /**< Input Fetch Shift Control Channel 1 Register, offset: 0x530 */ + __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1_SET; /**< Input Fetch Shift Control Channel 1 Register, offset: 0x534 */ + __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1_CLR; /**< Input Fetch Shift Control Channel 1 Register, offset: 0x538 */ + __IO uint32_t INPUT_FETCH_SHIFT_CTRL_CH1_TOG; /**< Input Fetch Shift Control Channel 1 Register, offset: 0x53C */ + __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0; /**< Input Fetch Shift Offset Channel 0 Register, offset: 0x540 */ + __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0_SET; /**< Input Fetch Shift Offset Channel 0 Register, offset: 0x544 */ + __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0_CLR; /**< Input Fetch Shift Offset Channel 0 Register, offset: 0x548 */ + __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH0_TOG; /**< Input Fetch Shift Offset Channel 0 Register, offset: 0x54C */ + __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1; /**< Input Fetch Shift Offset Channel 1 Register, offset: 0x550 */ + __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1_SET; /**< Input Fetch Shift Offset Channel 1 Register, offset: 0x554 */ + __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1_CLR; /**< Input Fetch Shift Offset Channel 1 Register, offset: 0x558 */ + __IO uint32_t INPUT_FETCH_SHIFT_OFFSET_CH1_TOG; /**< Input Fetch Shift Offset Channel 1 Register, offset: 0x55C */ + __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0; /**< Input Fetch Shift Width Channel 0 Register, offset: 0x560 */ + __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0_SET; /**< Input Fetch Shift Width Channel 0 Register, offset: 0x564 */ + __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0_CLR; /**< Input Fetch Shift Width Channel 0 Register, offset: 0x568 */ + __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH0_TOG; /**< Input Fetch Shift Width Channel 0 Register, offset: 0x56C */ + __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1; /**< Input Fetch Shift Width Channel 1 Register, offset: 0x570 */ + __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1_SET; /**< Input Fetch Shift Width Channel 1 Register, offset: 0x574 */ + __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1_CLR; /**< Input Fetch Shift Width Channel 1 Register, offset: 0x578 */ + __IO uint32_t INPUT_FETCH_SHIFT_WIDTH_CH1_TOG; /**< Input Fetch Shift Width Channel 1 Register, offset: 0x57C */ __IO uint32_t INPUT_FETCH_ADDR_0_CH0; /**< Input Fetch Address 0 Channel 0 Register, offset: 0x580 */ uint8_t RESERVED_57[12]; __IO uint32_t INPUT_FETCH_ADDR_1_CH0; /**< Input Fetch Address 1 Channel 0 Register, offset: 0x590 */ @@ -411,14 +414,14 @@ typedef struct { uint8_t RESERVED_59[12]; __IO uint32_t INPUT_FETCH_ADDR_1_CH1; /**< Input Fetch Address 1 Channel 1 Register, offset: 0x5B0 */ uint8_t RESERVED_60[12]; - __IO uint32_t INPUT_STORE_CTRL_CH0; /**< Store engine Control Channel 0 Register, offset: 0x5C0 */ - __IO uint32_t INPUT_STORE_CTRL_CH0_SET; /**< Store engine Control Channel 0 Register, offset: 0x5C4 */ - __IO uint32_t INPUT_STORE_CTRL_CH0_CLR; /**< Store engine Control Channel 0 Register, offset: 0x5C8 */ - __IO uint32_t INPUT_STORE_CTRL_CH0_TOG; /**< Store engine Control Channel 0 Register, offset: 0x5CC */ - __IO uint32_t INPUT_STORE_CTRL_CH1; /**< Store engine Control Channel 1 Register, offset: 0x5D0 */ - __IO uint32_t INPUT_STORE_CTRL_CH1_SET; /**< Store engine Control Channel 1 Register, offset: 0x5D4 */ - __IO uint32_t INPUT_STORE_CTRL_CH1_CLR; /**< Store engine Control Channel 1 Register, offset: 0x5D8 */ - __IO uint32_t INPUT_STORE_CTRL_CH1_TOG; /**< Store engine Control Channel 1 Register, offset: 0x5DC */ + __IO uint32_t INPUT_STORE_CTRL_CH0; /**< Input Store Control Channel 0 Register, offset: 0x5C0 */ + __IO uint32_t INPUT_STORE_CTRL_CH0_SET; /**< Input Store Control Channel 0 Register, offset: 0x5C4 */ + __IO uint32_t INPUT_STORE_CTRL_CH0_CLR; /**< Input Store Control Channel 0 Register, offset: 0x5C8 */ + __IO uint32_t INPUT_STORE_CTRL_CH0_TOG; /**< Input Store Control Channel 0 Register, offset: 0x5CC */ + __IO uint32_t INPUT_STORE_CTRL_CH1; /**< Input Store Control Channel 1 Register, offset: 0x5D0 */ + __IO uint32_t INPUT_STORE_CTRL_CH1_SET; /**< Input Store Control Channel 1 Register, offset: 0x5D4 */ + __IO uint32_t INPUT_STORE_CTRL_CH1_CLR; /**< Input Store Control Channel 1 Register, offset: 0x5D8 */ + __IO uint32_t INPUT_STORE_CTRL_CH1_TOG; /**< Input Store Control Channel 1 Register, offset: 0x5DC */ __I uint32_t INPUT_STORE_STATUS_CH0; /**< Input Store Status Channel 0 Register, offset: 0x5E0 */ uint8_t RESERVED_61[12]; __I uint32_t INPUT_STORE_STATUS_CH1; /**< Input Store Status Channel 1 Register, offset: 0x5F0 */ @@ -429,14 +432,14 @@ typedef struct { uint8_t RESERVED_64[12]; __IO uint32_t INPUT_STORE_PITCH; /**< Input Store Pitch Register, offset: 0x620 */ uint8_t RESERVED_65[12]; - __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0; /**< offset: 0x630 */ - __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0_SET; /**< offset: 0x634 */ - __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0_CLR; /**< offset: 0x638 */ - __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0_TOG; /**< offset: 0x63C */ - __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1; /**< offset: 0x640 */ - __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1_SET; /**< offset: 0x644 */ - __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1_CLR; /**< offset: 0x648 */ - __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1_TOG; /**< offset: 0x64C */ + __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0; /**< Input Store Shift Control Channel 0 Register, offset: 0x630 */ + __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0_SET; /**< Input Store Shift Control Channel 0 Register, offset: 0x634 */ + __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0_CLR; /**< Input Store Shift Control Channel 0 Register, offset: 0x638 */ + __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH0_TOG; /**< Input Store Shift Control Channel 0 Register, offset: 0x63C */ + __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1; /**< Input Store Shift Control Channel 1 Register, offset: 0x640 */ + __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1_SET; /**< Input Store Shift Control Channel 1 Register, offset: 0x644 */ + __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1_CLR; /**< Input Store Shift Control Channel 1 Register, offset: 0x648 */ + __IO uint32_t INPUT_STORE_SHIFT_CTRL_CH1_TOG; /**< Input Store Shift Control Channel 1 Register, offset: 0x64C */ uint8_t RESERVED_66[64]; __IO uint32_t INPUT_STORE_ADDR_0_CH0; /**< Input Store Address 0 Channel 0 Register, offset: 0x690 */ uint8_t RESERVED_67[12]; @@ -620,6 +623,318 @@ typedef struct { #define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) /*! @} */ +/*! @name CTRL_SET - Control Register 0 */ +/*! @{ */ + +#define PXP_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL_SET_ENABLE_SHIFT (0U) +/*! ENABLE - ENABLE */ +#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) + +#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) +/*! IRQ_ENABLE - IRQ_ENABLE */ +#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) + +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) +/*! NEXT_IRQ_ENABLE - NEXT_IRQ_ENABLE */ +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) + +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +/*! ENABLE_LCD0_HANDSHAKE - ENABLE_LCD0_HANDSHAKE */ +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK) + +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +/*! HANDSHAKE_ABORT_SKIP - HANDSHAKE_ABORT_SKIP */ +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK) + +#define PXP_CTRL_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL_SET_ROTATE0_SHIFT (8U) +/*! ROTATE0 - ROTATE0 */ +#define PXP_CTRL_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE0_SHIFT)) & PXP_CTRL_SET_ROTATE0_MASK) + +#define PXP_CTRL_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL_SET_HFLIP0_SHIFT (10U) +/*! HFLIP0 - HFLIP0 */ +#define PXP_CTRL_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP0_SHIFT)) & PXP_CTRL_SET_HFLIP0_MASK) + +#define PXP_CTRL_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL_SET_VFLIP0_SHIFT (11U) +/*! VFLIP0 - VFLIP0 */ +#define PXP_CTRL_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP0_SHIFT)) & PXP_CTRL_SET_VFLIP0_MASK) + +#define PXP_CTRL_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_SET_ROTATE1_SHIFT (12U) +/*! ROTATE1 - ROTATE1 */ +#define PXP_CTRL_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE1_SHIFT)) & PXP_CTRL_SET_ROTATE1_MASK) + +#define PXP_CTRL_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_SET_HFLIP1_SHIFT (14U) +/*! HFLIP1 - HFLIP1 */ +#define PXP_CTRL_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP1_SHIFT)) & PXP_CTRL_SET_HFLIP1_MASK) + +#define PXP_CTRL_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_SET_VFLIP1_SHIFT (15U) +/*! VFLIP1 - VFLIP1 */ +#define PXP_CTRL_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP1_SHIFT)) & PXP_CTRL_SET_VFLIP1_MASK) + +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT (16U) +/*! ENABLE_PS_AS_OUT - ENABLE_PS_AS_OUT */ +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK) + +#define PXP_CTRL_SET_ENABLE_ALPHA_B_MASK (0x200000U) +#define PXP_CTRL_SET_ENABLE_ALPHA_B_SHIFT (21U) +/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */ +#define PXP_CTRL_SET_ENABLE_ALPHA_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL_SET_ENABLE_ALPHA_B_MASK) + +#define PXP_CTRL_SET_BLOCK_32_MASK (0x400000U) +#define PXP_CTRL_SET_BLOCK_32_SHIFT (22U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_CTRL_SET_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_32_SHIFT)) & PXP_CTRL_SET_BLOCK_32_MASK) + +#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE - BLOCK_SIZE */ +#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) + +#define PXP_CTRL_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_SET_ENABLE_CSC2_SHIFT (24U) +/*! ENABLE_CSC2 - ENABLE_CSC2 */ +#define PXP_CTRL_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL_SET_ENABLE_CSC2_MASK) + +#define PXP_CTRL_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT (26U) +/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */ +#define PXP_CTRL_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE0_MASK) + +#define PXP_CTRL_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT (27U) +/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */ +#define PXP_CTRL_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE1_MASK) + +#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_SET_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE */ +#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) + +#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SET_SFTRST_SHIFT (31U) +/*! SFTRST - SFTRST */ +#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - Control Register 0 */ +/*! @{ */ + +#define PXP_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL_CLR_ENABLE_SHIFT (0U) +/*! ENABLE - ENABLE */ +#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) + +#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) +/*! IRQ_ENABLE - IRQ_ENABLE */ +#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) + +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) +/*! NEXT_IRQ_ENABLE - NEXT_IRQ_ENABLE */ +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) + +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +/*! ENABLE_LCD0_HANDSHAKE - ENABLE_LCD0_HANDSHAKE */ +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK) + +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +/*! HANDSHAKE_ABORT_SKIP - HANDSHAKE_ABORT_SKIP */ +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK) + +#define PXP_CTRL_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL_CLR_ROTATE0_SHIFT (8U) +/*! ROTATE0 - ROTATE0 */ +#define PXP_CTRL_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ROTATE0_MASK) + +#define PXP_CTRL_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL_CLR_HFLIP0_SHIFT (10U) +/*! HFLIP0 - HFLIP0 */ +#define PXP_CTRL_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP0_SHIFT)) & PXP_CTRL_CLR_HFLIP0_MASK) + +#define PXP_CTRL_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL_CLR_VFLIP0_SHIFT (11U) +/*! VFLIP0 - VFLIP0 */ +#define PXP_CTRL_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP0_SHIFT)) & PXP_CTRL_CLR_VFLIP0_MASK) + +#define PXP_CTRL_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_CLR_ROTATE1_SHIFT (12U) +/*! ROTATE1 - ROTATE1 */ +#define PXP_CTRL_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ROTATE1_MASK) + +#define PXP_CTRL_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_CLR_HFLIP1_SHIFT (14U) +/*! HFLIP1 - HFLIP1 */ +#define PXP_CTRL_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP1_SHIFT)) & PXP_CTRL_CLR_HFLIP1_MASK) + +#define PXP_CTRL_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_CLR_VFLIP1_SHIFT (15U) +/*! VFLIP1 - VFLIP1 */ +#define PXP_CTRL_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP1_SHIFT)) & PXP_CTRL_CLR_VFLIP1_MASK) + +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT (16U) +/*! ENABLE_PS_AS_OUT - ENABLE_PS_AS_OUT */ +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK) + +#define PXP_CTRL_CLR_ENABLE_ALPHA_B_MASK (0x200000U) +#define PXP_CTRL_CLR_ENABLE_ALPHA_B_SHIFT (21U) +/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */ +#define PXP_CTRL_CLR_ENABLE_ALPHA_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL_CLR_ENABLE_ALPHA_B_MASK) + +#define PXP_CTRL_CLR_BLOCK_32_MASK (0x400000U) +#define PXP_CTRL_CLR_BLOCK_32_SHIFT (22U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_CTRL_CLR_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_32_SHIFT)) & PXP_CTRL_CLR_BLOCK_32_MASK) + +#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE - BLOCK_SIZE */ +#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) + +#define PXP_CTRL_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_CLR_ENABLE_CSC2_SHIFT (24U) +/*! ENABLE_CSC2 - ENABLE_CSC2 */ +#define PXP_CTRL_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL_CLR_ENABLE_CSC2_MASK) + +#define PXP_CTRL_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT (26U) +/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */ +#define PXP_CTRL_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE0_MASK) + +#define PXP_CTRL_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT (27U) +/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */ +#define PXP_CTRL_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE1_MASK) + +#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE */ +#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) + +#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_CLR_SFTRST_SHIFT (31U) +/*! SFTRST - SFTRST */ +#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - Control Register 0 */ +/*! @{ */ + +#define PXP_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL_TOG_ENABLE_SHIFT (0U) +/*! ENABLE - ENABLE */ +#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) + +#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) +/*! IRQ_ENABLE - IRQ_ENABLE */ +#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) + +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) +/*! NEXT_IRQ_ENABLE - NEXT_IRQ_ENABLE */ +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) + +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +/*! ENABLE_LCD0_HANDSHAKE - ENABLE_LCD0_HANDSHAKE */ +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK) + +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +/*! HANDSHAKE_ABORT_SKIP - HANDSHAKE_ABORT_SKIP */ +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK) + +#define PXP_CTRL_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL_TOG_ROTATE0_SHIFT (8U) +/*! ROTATE0 - ROTATE0 */ +#define PXP_CTRL_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ROTATE0_MASK) + +#define PXP_CTRL_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL_TOG_HFLIP0_SHIFT (10U) +/*! HFLIP0 - HFLIP0 */ +#define PXP_CTRL_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP0_SHIFT)) & PXP_CTRL_TOG_HFLIP0_MASK) + +#define PXP_CTRL_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL_TOG_VFLIP0_SHIFT (11U) +/*! VFLIP0 - VFLIP0 */ +#define PXP_CTRL_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP0_SHIFT)) & PXP_CTRL_TOG_VFLIP0_MASK) + +#define PXP_CTRL_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_TOG_ROTATE1_SHIFT (12U) +/*! ROTATE1 - ROTATE1 */ +#define PXP_CTRL_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ROTATE1_MASK) + +#define PXP_CTRL_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_TOG_HFLIP1_SHIFT (14U) +/*! HFLIP1 - HFLIP1 */ +#define PXP_CTRL_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP1_SHIFT)) & PXP_CTRL_TOG_HFLIP1_MASK) + +#define PXP_CTRL_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_TOG_VFLIP1_SHIFT (15U) +/*! VFLIP1 - VFLIP1 */ +#define PXP_CTRL_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP1_SHIFT)) & PXP_CTRL_TOG_VFLIP1_MASK) + +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT (16U) +/*! ENABLE_PS_AS_OUT - ENABLE_PS_AS_OUT */ +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK) + +#define PXP_CTRL_TOG_ENABLE_ALPHA_B_MASK (0x200000U) +#define PXP_CTRL_TOG_ENABLE_ALPHA_B_SHIFT (21U) +/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */ +#define PXP_CTRL_TOG_ENABLE_ALPHA_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL_TOG_ENABLE_ALPHA_B_MASK) + +#define PXP_CTRL_TOG_BLOCK_32_MASK (0x400000U) +#define PXP_CTRL_TOG_BLOCK_32_SHIFT (22U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_CTRL_TOG_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_32_SHIFT)) & PXP_CTRL_TOG_BLOCK_32_MASK) + +#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE - BLOCK_SIZE */ +#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) + +#define PXP_CTRL_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_TOG_ENABLE_CSC2_SHIFT (24U) +/*! ENABLE_CSC2 - ENABLE_CSC2 */ +#define PXP_CTRL_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL_TOG_ENABLE_CSC2_MASK) + +#define PXP_CTRL_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT (26U) +/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */ +#define PXP_CTRL_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE0_MASK) + +#define PXP_CTRL_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT (27U) +/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */ +#define PXP_CTRL_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE1_MASK) + +#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE */ +#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) + +#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_TOG_SFTRST_SHIFT (31U) +/*! SFTRST - SFTRST */ +#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) +/*! @} */ + /*! @name STAT - Status Register */ /*! @{ */ @@ -674,6 +989,168 @@ typedef struct { #define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) /*! @} */ +/*! @name STAT_SET - Status Register */ +/*! @{ */ + +#define PXP_STAT_SET_IRQ0_MASK (0x1U) +#define PXP_STAT_SET_IRQ0_SHIFT (0U) +/*! IRQ0 - IRQ0 */ +#define PXP_STAT_SET_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ0_SHIFT)) & PXP_STAT_SET_IRQ0_MASK) + +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT (1U) +/*! AXI_WRITE_ERROR_0 - AXI_WRITE_ERROR_0 */ +#define PXP_STAT_SET_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK) + +#define PXP_STAT_SET_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT (2U) +/*! AXI_READ_ERROR_0 - AXI_READ_ERROR_0 */ +#define PXP_STAT_SET_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_0_MASK) + +#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) +/*! NEXT_IRQ - NEXT_IRQ */ +#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) + +#define PXP_STAT_SET_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT (4U) +/*! AXI_ERROR_ID_0 - AXI_ERROR_ID_0 */ +#define PXP_STAT_SET_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_0_MASK) + +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT (9U) +/*! AXI_WRITE_ERROR_1 - AXI_WRITE_ERROR_1 */ +#define PXP_STAT_SET_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK) + +#define PXP_STAT_SET_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT (10U) +/*! AXI_READ_ERROR_1 - AXI_READ_ERROR_1 */ +#define PXP_STAT_SET_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_1_MASK) + +#define PXP_STAT_SET_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT (12U) +/*! AXI_ERROR_ID_1 - AXI_ERROR_ID_1 */ +#define PXP_STAT_SET_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_1_MASK) + +#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_SET_BLOCKY_SHIFT (16U) +/*! BLOCKY - BLOCKY */ +#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) + +#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_SET_BLOCKX_SHIFT (24U) +/*! BLOCKX - BLOCKX */ +#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_CLR - Status Register */ +/*! @{ */ + +#define PXP_STAT_CLR_IRQ0_MASK (0x1U) +#define PXP_STAT_CLR_IRQ0_SHIFT (0U) +/*! IRQ0 - IRQ0 */ +#define PXP_STAT_CLR_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ0_SHIFT)) & PXP_STAT_CLR_IRQ0_MASK) + +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT (1U) +/*! AXI_WRITE_ERROR_0 - AXI_WRITE_ERROR_0 */ +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK) + +#define PXP_STAT_CLR_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT (2U) +/*! AXI_READ_ERROR_0 - AXI_READ_ERROR_0 */ +#define PXP_STAT_CLR_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_0_MASK) + +#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) +/*! NEXT_IRQ - NEXT_IRQ */ +#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) + +#define PXP_STAT_CLR_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT (4U) +/*! AXI_ERROR_ID_0 - AXI_ERROR_ID_0 */ +#define PXP_STAT_CLR_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_0_MASK) + +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT (9U) +/*! AXI_WRITE_ERROR_1 - AXI_WRITE_ERROR_1 */ +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK) + +#define PXP_STAT_CLR_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT (10U) +/*! AXI_READ_ERROR_1 - AXI_READ_ERROR_1 */ +#define PXP_STAT_CLR_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_1_MASK) + +#define PXP_STAT_CLR_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT (12U) +/*! AXI_ERROR_ID_1 - AXI_ERROR_ID_1 */ +#define PXP_STAT_CLR_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_1_MASK) + +#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_CLR_BLOCKY_SHIFT (16U) +/*! BLOCKY - BLOCKY */ +#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) + +#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_CLR_BLOCKX_SHIFT (24U) +/*! BLOCKX - BLOCKX */ +#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_TOG - Status Register */ +/*! @{ */ + +#define PXP_STAT_TOG_IRQ0_MASK (0x1U) +#define PXP_STAT_TOG_IRQ0_SHIFT (0U) +/*! IRQ0 - IRQ0 */ +#define PXP_STAT_TOG_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ0_SHIFT)) & PXP_STAT_TOG_IRQ0_MASK) + +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT (1U) +/*! AXI_WRITE_ERROR_0 - AXI_WRITE_ERROR_0 */ +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK) + +#define PXP_STAT_TOG_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT (2U) +/*! AXI_READ_ERROR_0 - AXI_READ_ERROR_0 */ +#define PXP_STAT_TOG_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_0_MASK) + +#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) +/*! NEXT_IRQ - NEXT_IRQ */ +#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) + +#define PXP_STAT_TOG_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT (4U) +/*! AXI_ERROR_ID_0 - AXI_ERROR_ID_0 */ +#define PXP_STAT_TOG_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_0_MASK) + +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT (9U) +/*! AXI_WRITE_ERROR_1 - AXI_WRITE_ERROR_1 */ +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK) + +#define PXP_STAT_TOG_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT (10U) +/*! AXI_READ_ERROR_1 - AXI_READ_ERROR_1 */ +#define PXP_STAT_TOG_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_1_MASK) + +#define PXP_STAT_TOG_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT (12U) +/*! AXI_ERROR_ID_1 - AXI_ERROR_ID_1 */ +#define PXP_STAT_TOG_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_1_MASK) + +#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_TOG_BLOCKY_SHIFT (16U) +/*! BLOCKY - BLOCKY */ +#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) + +#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_TOG_BLOCKX_SHIFT (24U) +/*! BLOCKX - BLOCKX */ +#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) +/*! @} */ + /*! @name OUT_CTRL - Output Buffer Control Register */ /*! @{ */ @@ -727,6 +1204,78 @@ typedef struct { #define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) /*! @} */ +/*! @name OUT_CTRL_SET - Output Buffer Control Register */ +/*! @{ */ + +#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) +/*! FORMAT - FORMAT */ +#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) + +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT - INTERLACED_OUTPUT */ +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) + +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) +/*! ALPHA_OUTPUT - ALPHA_OUTPUT */ +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) + +#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) +/*! ALPHA - ALPHA */ +#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +/*! @{ */ + +#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) +/*! FORMAT - FORMAT */ +#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) + +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT - INTERLACED_OUTPUT */ +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) + +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) +/*! ALPHA_OUTPUT - ALPHA_OUTPUT */ +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) + +#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) +/*! ALPHA - ALPHA */ +#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +/*! @{ */ + +#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) +/*! FORMAT - FORMAT */ +#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) + +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT - INTERLACED_OUTPUT */ +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) + +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) +/*! ALPHA_OUTPUT - ALPHA_OUTPUT */ +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) + +#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) +/*! ALPHA - ALPHA */ +#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) +/*! @} */ + /*! @name OUT_BUF - Output Frame Buffer Pointer Register */ /*! @{ */ @@ -883,6 +1432,78 @@ typedef struct { #define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) /*! @} */ +/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +/*! @{ */ + +#define PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) +/*! FORMAT - FORMAT */ +#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) + +#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U) +/*! WB_SWAP - WB_SWAP */ +#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) + +#define PXP_PS_CTRL_SET_DECY_MASK (0x300U) +#define PXP_PS_CTRL_SET_DECY_SHIFT (8U) +/*! DECY - DECY */ +#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) + +#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_SET_DECX_SHIFT (10U) +/*! DECX - DECX */ +#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) +/*! @} */ + +/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +/*! @{ */ + +#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) +/*! FORMAT - FORMAT */ +#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) + +#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U) +/*! WB_SWAP - WB_SWAP */ +#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) + +#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) +#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) +/*! DECY - DECY */ +#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) + +#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) +/*! DECX - DECX */ +#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) +/*! @} */ + +/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +/*! @{ */ + +#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) +/*! FORMAT - FORMAT */ +#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) + +#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U) +/*! WB_SWAP - WB_SWAP */ +#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) + +#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) +#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) +/*! DECY - DECY */ +#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) + +#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) +/*! DECX - DECX */ +#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) +/*! @} */ + /*! @name PS_BUF - PS Input Buffer Address Register */ /*! @{ */ @@ -1597,28 +2218,250 @@ typedef struct { #define PXP_CTRL2_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE1_MASK) /*! @} */ -/*! @name POWER_REG0 - Power Control Register 0 */ +/*! @name CTRL2_SET - Control Register 2 */ /*! @{ */ -#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK (0xE00U) -#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT (9U) -/*! ROT0_MEM_LP_STATE - ROT0_MEM_LP_STATE - * 0b000..NONE : Memory is not in low power state. - * 0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents. - * 0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents. - * 0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention. - */ -#define PXP_POWER_REG0_ROT0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK) -/*! @} */ +#define PXP_CTRL2_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL2_SET_ENABLE_SHIFT (0U) +/*! ENABLE - ENABLE */ +#define PXP_CTRL2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_SHIFT)) & PXP_CTRL2_SET_ENABLE_MASK) -/*! @name POWER_REG1 - Power Control Register 1 */ -/*! @{ */ +#define PXP_CTRL2_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_SET_ROTATE0_SHIFT (8U) +/*! ROTATE0 - ROTATE0 */ +#define PXP_CTRL2_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ROTATE0_MASK) -#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK (0x7U) -#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT (0U) -/*! ROT1_MEM_LP_STATE - ROT1_MEM_LP_STATE - * 0b000..NONE : Memory is not in low power state. - * 0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents. +#define PXP_CTRL2_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_SET_HFLIP0_SHIFT (10U) +/*! HFLIP0 - HFLIP0 */ +#define PXP_CTRL2_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP0_SHIFT)) & PXP_CTRL2_SET_HFLIP0_MASK) + +#define PXP_CTRL2_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_SET_VFLIP0_SHIFT (11U) +/*! VFLIP0 - VFLIP0 */ +#define PXP_CTRL2_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP0_SHIFT)) & PXP_CTRL2_SET_VFLIP0_MASK) + +#define PXP_CTRL2_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_SET_ROTATE1_SHIFT (12U) +/*! ROTATE1 - ROTATE1 */ +#define PXP_CTRL2_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ROTATE1_MASK) + +#define PXP_CTRL2_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_SET_HFLIP1_SHIFT (14U) +/*! HFLIP1 - HFLIP1 */ +#define PXP_CTRL2_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP1_SHIFT)) & PXP_CTRL2_SET_HFLIP1_MASK) + +#define PXP_CTRL2_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_SET_VFLIP1_SHIFT (15U) +/*! VFLIP1 - VFLIP1 */ +#define PXP_CTRL2_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP1_SHIFT)) & PXP_CTRL2_SET_VFLIP1_MASK) + +#define PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE_MASK (0x100000U) +#define PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE_SHIFT (20U) +/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */ +#define PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL2_SET_ENABLE_INPUT_FETCH_STORE_MASK) + +#define PXP_CTRL2_SET_ENABLE_ALPHA_B_MASK (0x200000U) +#define PXP_CTRL2_SET_ENABLE_ALPHA_B_SHIFT (21U) +/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */ +#define PXP_CTRL2_SET_ENABLE_ALPHA_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL2_SET_ENABLE_ALPHA_B_MASK) + +#define PXP_CTRL2_SET_BLOCK_32_MASK (0x400000U) +#define PXP_CTRL2_SET_BLOCK_32_SHIFT (22U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_CTRL2_SET_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_BLOCK_32_SHIFT)) & PXP_CTRL2_SET_BLOCK_32_MASK) + +#define PXP_CTRL2_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_SET_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE - BLOCK_SIZE */ +#define PXP_CTRL2_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_SET_BLOCK_SIZE_MASK) + +#define PXP_CTRL2_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_SET_ENABLE_CSC2_SHIFT (24U) +/*! ENABLE_CSC2 - ENABLE_CSC2 */ +#define PXP_CTRL2_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_SET_ENABLE_CSC2_MASK) + +#define PXP_CTRL2_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT (26U) +/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */ +#define PXP_CTRL2_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE0_MASK) + +#define PXP_CTRL2_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT (27U) +/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */ +#define PXP_CTRL2_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE1_MASK) +/*! @} */ + +/*! @name CTRL2_CLR - Control Register 2 */ +/*! @{ */ + +#define PXP_CTRL2_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL2_CLR_ENABLE_SHIFT (0U) +/*! ENABLE - ENABLE */ +#define PXP_CTRL2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_SHIFT)) & PXP_CTRL2_CLR_ENABLE_MASK) + +#define PXP_CTRL2_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_CLR_ROTATE0_SHIFT (8U) +/*! ROTATE0 - ROTATE0 */ +#define PXP_CTRL2_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ROTATE0_MASK) + +#define PXP_CTRL2_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_CLR_HFLIP0_SHIFT (10U) +/*! HFLIP0 - HFLIP0 */ +#define PXP_CTRL2_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP0_SHIFT)) & PXP_CTRL2_CLR_HFLIP0_MASK) + +#define PXP_CTRL2_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_CLR_VFLIP0_SHIFT (11U) +/*! VFLIP0 - VFLIP0 */ +#define PXP_CTRL2_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP0_SHIFT)) & PXP_CTRL2_CLR_VFLIP0_MASK) + +#define PXP_CTRL2_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_CLR_ROTATE1_SHIFT (12U) +/*! ROTATE1 - ROTATE1 */ +#define PXP_CTRL2_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ROTATE1_MASK) + +#define PXP_CTRL2_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_CLR_HFLIP1_SHIFT (14U) +/*! HFLIP1 - HFLIP1 */ +#define PXP_CTRL2_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP1_SHIFT)) & PXP_CTRL2_CLR_HFLIP1_MASK) + +#define PXP_CTRL2_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_CLR_VFLIP1_SHIFT (15U) +/*! VFLIP1 - VFLIP1 */ +#define PXP_CTRL2_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP1_SHIFT)) & PXP_CTRL2_CLR_VFLIP1_MASK) + +#define PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE_MASK (0x100000U) +#define PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE_SHIFT (20U) +/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */ +#define PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL2_CLR_ENABLE_INPUT_FETCH_STORE_MASK) + +#define PXP_CTRL2_CLR_ENABLE_ALPHA_B_MASK (0x200000U) +#define PXP_CTRL2_CLR_ENABLE_ALPHA_B_SHIFT (21U) +/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */ +#define PXP_CTRL2_CLR_ENABLE_ALPHA_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ALPHA_B_MASK) + +#define PXP_CTRL2_CLR_BLOCK_32_MASK (0x400000U) +#define PXP_CTRL2_CLR_BLOCK_32_SHIFT (22U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_CTRL2_CLR_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_BLOCK_32_SHIFT)) & PXP_CTRL2_CLR_BLOCK_32_MASK) + +#define PXP_CTRL2_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE - BLOCK_SIZE */ +#define PXP_CTRL2_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_CLR_BLOCK_SIZE_MASK) + +#define PXP_CTRL2_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT (24U) +/*! ENABLE_CSC2 - ENABLE_CSC2 */ +#define PXP_CTRL2_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_CLR_ENABLE_CSC2_MASK) + +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT (26U) +/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */ +#define PXP_CTRL2_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK) + +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT (27U) +/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */ +#define PXP_CTRL2_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK) +/*! @} */ + +/*! @name CTRL2_TOG - Control Register 2 */ +/*! @{ */ + +#define PXP_CTRL2_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL2_TOG_ENABLE_SHIFT (0U) +/*! ENABLE - ENABLE */ +#define PXP_CTRL2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_SHIFT)) & PXP_CTRL2_TOG_ENABLE_MASK) + +#define PXP_CTRL2_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_TOG_ROTATE0_SHIFT (8U) +/*! ROTATE0 - ROTATE0 */ +#define PXP_CTRL2_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ROTATE0_MASK) + +#define PXP_CTRL2_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_TOG_HFLIP0_SHIFT (10U) +/*! HFLIP0 - HFLIP0 */ +#define PXP_CTRL2_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP0_SHIFT)) & PXP_CTRL2_TOG_HFLIP0_MASK) + +#define PXP_CTRL2_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_TOG_VFLIP0_SHIFT (11U) +/*! VFLIP0 - VFLIP0 */ +#define PXP_CTRL2_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP0_SHIFT)) & PXP_CTRL2_TOG_VFLIP0_MASK) + +#define PXP_CTRL2_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_TOG_ROTATE1_SHIFT (12U) +/*! ROTATE1 - ROTATE1 */ +#define PXP_CTRL2_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ROTATE1_MASK) + +#define PXP_CTRL2_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_TOG_HFLIP1_SHIFT (14U) +/*! HFLIP1 - HFLIP1 */ +#define PXP_CTRL2_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP1_SHIFT)) & PXP_CTRL2_TOG_HFLIP1_MASK) + +#define PXP_CTRL2_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_TOG_VFLIP1_SHIFT (15U) +/*! VFLIP1 - VFLIP1 */ +#define PXP_CTRL2_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP1_SHIFT)) & PXP_CTRL2_TOG_VFLIP1_MASK) + +#define PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE_MASK (0x100000U) +#define PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE_SHIFT (20U) +/*! ENABLE_INPUT_FETCH_STORE - ENABLE_INPUT_FETCH_STORE */ +#define PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE_SHIFT)) & PXP_CTRL2_TOG_ENABLE_INPUT_FETCH_STORE_MASK) + +#define PXP_CTRL2_TOG_ENABLE_ALPHA_B_MASK (0x200000U) +#define PXP_CTRL2_TOG_ENABLE_ALPHA_B_SHIFT (21U) +/*! ENABLE_ALPHA_B - ENABLE_ALPHA_B */ +#define PXP_CTRL2_TOG_ENABLE_ALPHA_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ALPHA_B_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ALPHA_B_MASK) + +#define PXP_CTRL2_TOG_BLOCK_32_MASK (0x400000U) +#define PXP_CTRL2_TOG_BLOCK_32_SHIFT (22U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_CTRL2_TOG_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_BLOCK_32_SHIFT)) & PXP_CTRL2_TOG_BLOCK_32_MASK) + +#define PXP_CTRL2_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE - BLOCK_SIZE */ +#define PXP_CTRL2_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_TOG_BLOCK_SIZE_MASK) + +#define PXP_CTRL2_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT (24U) +/*! ENABLE_CSC2 - ENABLE_CSC2 */ +#define PXP_CTRL2_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_TOG_ENABLE_CSC2_MASK) + +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT (26U) +/*! ENABLE_ROTATE0 - ENABLE_ROTATE0 */ +#define PXP_CTRL2_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK) + +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT (27U) +/*! ENABLE_ROTATE1 - ENABLE_ROTATE1 */ +#define PXP_CTRL2_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK) +/*! @} */ + +/*! @name POWER_REG0 - Power Control Register 0 */ +/*! @{ */ + +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT (9U) +/*! ROT0_MEM_LP_STATE - ROT0_MEM_LP_STATE + * 0b000..NONE : Memory is not in low power state. + * 0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents. + * 0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents. + * 0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention. + */ +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK) +/*! @} */ + +/*! @name POWER_REG1 - Power Control Register 1 */ +/*! @{ */ + +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK (0x7U) +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT (0U) +/*! ROT1_MEM_LP_STATE - ROT1_MEM_LP_STATE + * 0b000..NONE : Memory is not in low power state. + * 0b001..LS : Light Sleep Mode. Low leakage mode, maintain memory contents. * 0b010..DS : Deep Sleep Mode. Low leakage mode, maintain memory contents. * 0b100..SD : Shut Down Mode. Shut Down periphery and core, no memory retention. */ @@ -1779,6 +2622,258 @@ typedef struct { #define PXP_DATA_PATH_CTRL0_MUX15_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX15_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX15_SEL_MASK) /*! @} */ +/*! @name DATA_PATH_CTRL0_SET - Data Path Control 0 Register */ +/*! @{ */ + +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT (0U) +/*! MUX0_SEL - MUX0_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT (2U) +/*! MUX1_SEL - MUX1_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX2_SEL_MASK (0x30U) +#define PXP_DATA_PATH_CTRL0_SET_MUX2_SEL_SHIFT (4U) +/*! MUX2_SEL - MUX2_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX2_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX2_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX2_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT (6U) +/*! MUX3_SEL - MUX3_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX4_SEL_MASK (0x300U) +#define PXP_DATA_PATH_CTRL0_SET_MUX4_SEL_SHIFT (8U) +/*! MUX4_SEL - MUX4_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX4_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX4_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX4_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX5_SEL_MASK (0xC00U) +#define PXP_DATA_PATH_CTRL0_SET_MUX5_SEL_SHIFT (10U) +/*! MUX5_SEL - MUX5_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX5_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX5_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX5_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX6_SEL_MASK (0x3000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX6_SEL_SHIFT (12U) +/*! MUX6_SEL - MUX6_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX6_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX6_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX6_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX7_SEL_MASK (0xC000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX7_SEL_SHIFT (14U) +/*! MUX7_SEL - MUX7_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX7_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX7_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX7_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT (16U) +/*! MUX8_SEL - MUX8_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT (18U) +/*! MUX9_SEL - MUX9_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX10_SEL_MASK (0x300000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX10_SEL_SHIFT (20U) +/*! MUX10_SEL - MUX10_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX10_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX10_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX10_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT (22U) +/*! MUX11_SEL - MUX11_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT (24U) +/*! MUX12_SEL - MUX12_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX13_SEL_MASK (0xC000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX13_SEL_SHIFT (26U) +/*! MUX13_SEL - MUX13_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX13_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX13_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX13_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT (28U) +/*! MUX14_SEL - MUX14_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_SET_MUX15_SEL_MASK (0xC0000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX15_SEL_SHIFT (30U) +/*! MUX15_SEL - MUX15_SEL */ +#define PXP_DATA_PATH_CTRL0_SET_MUX15_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX15_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX15_SEL_MASK) +/*! @} */ + +/*! @name DATA_PATH_CTRL0_CLR - Data Path Control 0 Register */ +/*! @{ */ + +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT (0U) +/*! MUX0_SEL - MUX0_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT (2U) +/*! MUX1_SEL - MUX1_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL_MASK (0x30U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL_SHIFT (4U) +/*! MUX2_SEL - MUX2_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX2_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT (6U) +/*! MUX3_SEL - MUX3_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL_MASK (0x300U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL_SHIFT (8U) +/*! MUX4_SEL - MUX4_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX4_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL_MASK (0xC00U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL_SHIFT (10U) +/*! MUX5_SEL - MUX5_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX5_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL_MASK (0x3000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL_SHIFT (12U) +/*! MUX6_SEL - MUX6_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX6_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL_MASK (0xC000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL_SHIFT (14U) +/*! MUX7_SEL - MUX7_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX7_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT (16U) +/*! MUX8_SEL - MUX8_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT (18U) +/*! MUX9_SEL - MUX9_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL_MASK (0x300000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL_SHIFT (20U) +/*! MUX10_SEL - MUX10_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX10_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT (22U) +/*! MUX11_SEL - MUX11_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT (24U) +/*! MUX12_SEL - MUX12_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL_MASK (0xC000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL_SHIFT (26U) +/*! MUX13_SEL - MUX13_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX13_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT (28U) +/*! MUX14_SEL - MUX14_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL_MASK (0xC0000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL_SHIFT (30U) +/*! MUX15_SEL - MUX15_SEL */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX15_SEL_MASK) +/*! @} */ + +/*! @name DATA_PATH_CTRL0_TOG - Data Path Control 0 Register */ +/*! @{ */ + +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT (0U) +/*! MUX0_SEL - MUX0_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT (2U) +/*! MUX1_SEL - MUX1_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL_MASK (0x30U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL_SHIFT (4U) +/*! MUX2_SEL - MUX2_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX2_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT (6U) +/*! MUX3_SEL - MUX3_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL_MASK (0x300U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL_SHIFT (8U) +/*! MUX4_SEL - MUX4_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX4_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL_MASK (0xC00U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL_SHIFT (10U) +/*! MUX5_SEL - MUX5_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX5_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL_MASK (0x3000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL_SHIFT (12U) +/*! MUX6_SEL - MUX6_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX6_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL_MASK (0xC000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL_SHIFT (14U) +/*! MUX7_SEL - MUX7_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX7_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT (16U) +/*! MUX8_SEL - MUX8_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT (18U) +/*! MUX9_SEL - MUX9_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL_MASK (0x300000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL_SHIFT (20U) +/*! MUX10_SEL - MUX10_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX10_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT (22U) +/*! MUX11_SEL - MUX11_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT (24U) +/*! MUX12_SEL - MUX12_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL_MASK (0xC000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL_SHIFT (26U) +/*! MUX13_SEL - MUX13_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX13_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT (28U) +/*! MUX14_SEL - MUX14_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK) + +#define PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL_MASK (0xC0000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL_SHIFT (30U) +/*! MUX15_SEL - MUX15_SEL */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX15_SEL_MASK) +/*! @} */ + /*! @name IRQ_MASK - IRQ Mask Register */ /*! @{ */ @@ -1808,6 +2903,93 @@ typedef struct { #define PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK) /*! @} */ +/*! @name IRQ_MASK_SET - IRQ Mask Register */ +/*! @{ */ + +#define PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN_MASK (0x1U) +#define PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT (0U) +/*! FIRST_CH0_PREFETCH_IRQ_EN - FIRST_CH0_PREFETCH_IRQ_EN */ +#define PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_CH0_PREFETCH_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN_MASK (0x2U) +#define PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT (1U) +/*! FIRST_CH1_PREFETCH_IRQ_EN - FIRST_CH1_PREFETCH_IRQ_EN */ +#define PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_CH1_PREFETCH_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN_MASK (0x4U) +#define PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN_SHIFT (2U) +/*! FIRST_CH0_STORE_IRQ_EN - FIRST_CH0_STORE_IRQ_EN */ +#define PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_CH0_STORE_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN_MASK (0x8U) +#define PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN_SHIFT (3U) +/*! FIRST_CH1_STORE_IRQ_EN - FIRST_CH1_STORE_IRQ_EN */ +#define PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_CH1_STORE_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN_MASK (0x1000U) +#define PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN_SHIFT (12U) +/*! FIRST_STORE_IRQ_EN - FIRST_STORE_IRQ_EN */ +#define PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_FIRST_STORE_IRQ_EN_MASK) +/*! @} */ + +/*! @name IRQ_MASK_CLR - IRQ Mask Register */ +/*! @{ */ + +#define PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN_MASK (0x1U) +#define PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT (0U) +/*! FIRST_CH0_PREFETCH_IRQ_EN - FIRST_CH0_PREFETCH_IRQ_EN */ +#define PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_CH0_PREFETCH_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN_MASK (0x2U) +#define PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT (1U) +/*! FIRST_CH1_PREFETCH_IRQ_EN - FIRST_CH1_PREFETCH_IRQ_EN */ +#define PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_CH1_PREFETCH_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN_MASK (0x4U) +#define PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN_SHIFT (2U) +/*! FIRST_CH0_STORE_IRQ_EN - FIRST_CH0_STORE_IRQ_EN */ +#define PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_CH0_STORE_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN_MASK (0x8U) +#define PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN_SHIFT (3U) +/*! FIRST_CH1_STORE_IRQ_EN - FIRST_CH1_STORE_IRQ_EN */ +#define PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_CH1_STORE_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN_MASK (0x1000U) +#define PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN_SHIFT (12U) +/*! FIRST_STORE_IRQ_EN - FIRST_STORE_IRQ_EN */ +#define PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_FIRST_STORE_IRQ_EN_MASK) +/*! @} */ + +/*! @name IRQ_MASK_TOG - IRQ Mask Register */ +/*! @{ */ + +#define PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN_MASK (0x1U) +#define PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT (0U) +/*! FIRST_CH0_PREFETCH_IRQ_EN - FIRST_CH0_PREFETCH_IRQ_EN */ +#define PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_CH0_PREFETCH_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN_MASK (0x2U) +#define PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT (1U) +/*! FIRST_CH1_PREFETCH_IRQ_EN - FIRST_CH1_PREFETCH_IRQ_EN */ +#define PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_CH1_PREFETCH_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN_MASK (0x4U) +#define PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN_SHIFT (2U) +/*! FIRST_CH0_STORE_IRQ_EN - FIRST_CH0_STORE_IRQ_EN */ +#define PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_CH0_STORE_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN_MASK (0x8U) +#define PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN_SHIFT (3U) +/*! FIRST_CH1_STORE_IRQ_EN - FIRST_CH1_STORE_IRQ_EN */ +#define PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_CH1_STORE_IRQ_EN_MASK) + +#define PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN_MASK (0x1000U) +#define PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN_SHIFT (12U) +/*! FIRST_STORE_IRQ_EN - FIRST_STORE_IRQ_EN */ +#define PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_FIRST_STORE_IRQ_EN_MASK) +/*! @} */ + /*! @name IRQ - Interrupt Register */ /*! @{ */ @@ -1837,6 +3019,93 @@ typedef struct { #define PXP_IRQ_FIRST_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_FIRST_STORE_IRQ_SHIFT)) & PXP_IRQ_FIRST_STORE_IRQ_MASK) /*! @} */ +/*! @name IRQ_SET - Interrupt Register */ +/*! @{ */ + +#define PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ_MASK (0x1U) +#define PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ_SHIFT (0U) +/*! FIRST_CH0_PREFETCH_IRQ - FIRST_CH0_PREFETCH_IRQ */ +#define PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_CH0_PREFETCH_IRQ_MASK) + +#define PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ_MASK (0x2U) +#define PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ_SHIFT (1U) +/*! FIRST_CH1_PREFETCH_IRQ - FIRST_CH1_PREFETCH_IRQ */ +#define PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_CH1_PREFETCH_IRQ_MASK) + +#define PXP_IRQ_SET_FIRST_CH0_STORE_IRQ_MASK (0x4U) +#define PXP_IRQ_SET_FIRST_CH0_STORE_IRQ_SHIFT (2U) +/*! FIRST_CH0_STORE_IRQ - FIRST_CH0_STORE_IRQ */ +#define PXP_IRQ_SET_FIRST_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_CH0_STORE_IRQ_MASK) + +#define PXP_IRQ_SET_FIRST_CH1_STORE_IRQ_MASK (0x8U) +#define PXP_IRQ_SET_FIRST_CH1_STORE_IRQ_SHIFT (3U) +/*! FIRST_CH1_STORE_IRQ - FIRST_CH1_STORE_IRQ */ +#define PXP_IRQ_SET_FIRST_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_CH1_STORE_IRQ_MASK) + +#define PXP_IRQ_SET_FIRST_STORE_IRQ_MASK (0x1000U) +#define PXP_IRQ_SET_FIRST_STORE_IRQ_SHIFT (12U) +/*! FIRST_STORE_IRQ - FIRST_STORE_IRQ */ +#define PXP_IRQ_SET_FIRST_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_FIRST_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_FIRST_STORE_IRQ_MASK) +/*! @} */ + +/*! @name IRQ_CLR - Interrupt Register */ +/*! @{ */ + +#define PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ_MASK (0x1U) +#define PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ_SHIFT (0U) +/*! FIRST_CH0_PREFETCH_IRQ - FIRST_CH0_PREFETCH_IRQ */ +#define PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_CH0_PREFETCH_IRQ_MASK) + +#define PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ_MASK (0x2U) +#define PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ_SHIFT (1U) +/*! FIRST_CH1_PREFETCH_IRQ - FIRST_CH1_PREFETCH_IRQ */ +#define PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_CH1_PREFETCH_IRQ_MASK) + +#define PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ_MASK (0x4U) +#define PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ_SHIFT (2U) +/*! FIRST_CH0_STORE_IRQ - FIRST_CH0_STORE_IRQ */ +#define PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_CH0_STORE_IRQ_MASK) + +#define PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ_MASK (0x8U) +#define PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ_SHIFT (3U) +/*! FIRST_CH1_STORE_IRQ - FIRST_CH1_STORE_IRQ */ +#define PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_CH1_STORE_IRQ_MASK) + +#define PXP_IRQ_CLR_FIRST_STORE_IRQ_MASK (0x1000U) +#define PXP_IRQ_CLR_FIRST_STORE_IRQ_SHIFT (12U) +/*! FIRST_STORE_IRQ - FIRST_STORE_IRQ */ +#define PXP_IRQ_CLR_FIRST_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_FIRST_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_FIRST_STORE_IRQ_MASK) +/*! @} */ + +/*! @name IRQ_TOG - Interrupt Register */ +/*! @{ */ + +#define PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ_MASK (0x1U) +#define PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ_SHIFT (0U) +/*! FIRST_CH0_PREFETCH_IRQ - FIRST_CH0_PREFETCH_IRQ */ +#define PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_CH0_PREFETCH_IRQ_MASK) + +#define PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ_MASK (0x2U) +#define PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ_SHIFT (1U) +/*! FIRST_CH1_PREFETCH_IRQ - FIRST_CH1_PREFETCH_IRQ */ +#define PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_CH1_PREFETCH_IRQ_MASK) + +#define PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ_MASK (0x4U) +#define PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ_SHIFT (2U) +/*! FIRST_CH0_STORE_IRQ - FIRST_CH0_STORE_IRQ */ +#define PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_CH0_STORE_IRQ_MASK) + +#define PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ_MASK (0x8U) +#define PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ_SHIFT (3U) +/*! FIRST_CH1_STORE_IRQ - FIRST_CH1_STORE_IRQ */ +#define PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_CH1_STORE_IRQ_MASK) + +#define PXP_IRQ_TOG_FIRST_STORE_IRQ_MASK (0x1000U) +#define PXP_IRQ_TOG_FIRST_STORE_IRQ_SHIFT (12U) +/*! FIRST_STORE_IRQ - FIRST_STORE_IRQ */ +#define PXP_IRQ_TOG_FIRST_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_FIRST_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_FIRST_STORE_IRQ_MASK) +/*! @} */ + /*! @name NEXT - Next Frame Pointer Register */ /*! @{ */ @@ -1944,6 +3213,153 @@ typedef struct { #define PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_MASK) /*! @} */ +/*! @name INPUT_FETCH_CTRL_CH0_SET - Input Fetch Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN_MASK (0x1U) +#define PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_CH_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_16_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_32_MASK (0x40U) +#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_32_SHIFT (6U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_32_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_BLOCK_32_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP_MASK (0x200U) +#define PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP_SHIFT (9U) +/*! HFLIP - HFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_HFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP_MASK (0x400U) +#define PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP_SHIFT (10U) +/*! VFLIP - VFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_VFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_MASK (0x3000U) +#define PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_SHIFT (12U) +/*! ROTATION_ANGLE - ROTATION_ANGLE */ +#define PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_ROTATION_ANGLE_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_SHIFT (16U) +/*! RD_NUM_BYTES - RD_NUM_BYTES */ +#define PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_RD_NUM_BYTES_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U) +#define PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U) +/*! ARBIT_EN - ARBIT_EN */ +#define PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_SET_ARBIT_EN_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_CTRL_CH0_CLR - Input Fetch Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN_MASK (0x1U) +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_CH_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_16_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_32_MASK (0x40U) +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_32_SHIFT (6U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_32_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_BLOCK_32_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP_MASK (0x200U) +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP_SHIFT (9U) +/*! HFLIP - HFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_HFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP_MASK (0x400U) +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP_SHIFT (10U) +/*! VFLIP - VFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_VFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_MASK (0x3000U) +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_SHIFT (12U) +/*! ROTATION_ANGLE - ROTATION_ANGLE */ +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_ROTATION_ANGLE_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_SHIFT (16U) +/*! RD_NUM_BYTES - RD_NUM_BYTES */ +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_RD_NUM_BYTES_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U) +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U) +/*! ARBIT_EN - ARBIT_EN */ +#define PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_CLR_ARBIT_EN_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_CTRL_CH0_TOG - Input Fetch Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN_MASK (0x1U) +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_CH_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_16_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_32_MASK (0x40U) +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_32_SHIFT (6U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_32_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_BLOCK_32_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP_MASK (0x200U) +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP_SHIFT (9U) +/*! HFLIP - HFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_HFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP_MASK (0x400U) +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP_SHIFT (10U) +/*! VFLIP - VFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_VFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_MASK (0x3000U) +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_SHIFT (12U) +/*! ROTATION_ANGLE - ROTATION_ANGLE */ +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_ROTATION_ANGLE_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_SHIFT (16U) +/*! RD_NUM_BYTES - RD_NUM_BYTES */ +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_RD_NUM_BYTES_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U) +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U) +/*! ARBIT_EN - ARBIT_EN */ +#define PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH0_TOG_ARBIT_EN_MASK) +/*! @} */ + /*! @name INPUT_FETCH_CTRL_CH1 - Input Fetch Control Channel 1 Register */ /*! @{ */ @@ -2020,6 +3436,138 @@ typedef struct { #define PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK) /*! @} */ +/*! @name INPUT_FETCH_CTRL_CH1_SET - Input Fetch Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN_MASK (0x1U) +#define PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_CH_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_16_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_32_MASK (0x40U) +#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_32_SHIFT (6U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_32_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_BLOCK_32_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP_MASK (0x200U) +#define PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP_SHIFT (9U) +/*! HFLIP - HFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_HFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP_MASK (0x400U) +#define PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP_SHIFT (10U) +/*! VFLIP - VFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_VFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_MASK (0x3000U) +#define PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_SHIFT (12U) +/*! ROTATION_ANGLE - ROTATION_ANGLE */ +#define PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_ROTATION_ANGLE_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_SHIFT (16U) +/*! RD_NUM_BYTES - RD_NUM_BYTES */ +#define PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_SET_RD_NUM_BYTES_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_CTRL_CH1_CLR - Input Fetch Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN_MASK (0x1U) +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_CH_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_16_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_32_MASK (0x40U) +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_32_SHIFT (6U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_32_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_BLOCK_32_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP_MASK (0x200U) +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP_SHIFT (9U) +/*! HFLIP - HFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_HFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP_MASK (0x400U) +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP_SHIFT (10U) +/*! VFLIP - VFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_VFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_MASK (0x3000U) +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_SHIFT (12U) +/*! ROTATION_ANGLE - ROTATION_ANGLE */ +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_ROTATION_ANGLE_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_SHIFT (16U) +/*! RD_NUM_BYTES - RD_NUM_BYTES */ +#define PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_CLR_RD_NUM_BYTES_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_CTRL_CH1_TOG - Input Fetch Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN_MASK (0x1U) +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_CH_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_EN_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_16_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_32_MASK (0x40U) +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_32_SHIFT (6U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_32_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_BLOCK_32_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP_MASK (0x200U) +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP_SHIFT (9U) +/*! HFLIP - HFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_HFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP_MASK (0x400U) +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP_SHIFT (10U) +/*! VFLIP - VFLIP */ +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_VFLIP_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_MASK (0x3000U) +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_SHIFT (12U) +/*! ROTATION_ANGLE - ROTATION_ANGLE */ +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_ROTATION_ANGLE_MASK) + +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_SHIFT (16U) +/*! RD_NUM_BYTES - RD_NUM_BYTES */ +#define PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_SHIFT)) & PXP_INPUT_FETCH_CTRL_CH1_TOG_RD_NUM_BYTES_MASK) +/*! @} */ + /*! @name INPUT_FETCH_STATUS_CH0 - Input Fetch Status Channel 0 Register */ /*! @{ */ @@ -2208,6 +3756,78 @@ typedef struct { #define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK) /*! @} */ +/*! @name INPUT_FETCH_SHIFT_CTRL_CH0_SET - Input Fetch Shift Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_MASK (0x3U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_SHIFT (0U) +/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_INPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_MASK (0x700U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_SHIFT (8U) +/*! EXPAND_FORMAT - EXPAND_FORMAT */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_FORMAT_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_MASK (0x800U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_SHIFT (11U) +/*! EXPAND_EN - EXPAND_EN */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_EXPAND_EN_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x1000U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (12U) +/*! SHIFT_BYPASS - SHIFT_BYPASS */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_CTRL_CH0_CLR - Input Fetch Shift Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_MASK (0x3U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_SHIFT (0U) +/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_INPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_MASK (0x700U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_SHIFT (8U) +/*! EXPAND_FORMAT - EXPAND_FORMAT */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_FORMAT_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_MASK (0x800U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_SHIFT (11U) +/*! EXPAND_EN - EXPAND_EN */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_EXPAND_EN_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x1000U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (12U) +/*! SHIFT_BYPASS - SHIFT_BYPASS */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_CTRL_CH0_TOG - Input Fetch Shift Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_MASK (0x3U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_SHIFT (0U) +/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_INPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_MASK (0x700U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_SHIFT (8U) +/*! EXPAND_FORMAT - EXPAND_FORMAT */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_FORMAT_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_MASK (0x800U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_SHIFT (11U) +/*! EXPAND_EN - EXPAND_EN */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_EXPAND_EN_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x1000U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (12U) +/*! SHIFT_BYPASS - SHIFT_BYPASS */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK) +/*! @} */ + /*! @name INPUT_FETCH_SHIFT_CTRL_CH1 - Input Fetch Shift Control Channel 1 Register */ /*! @{ */ @@ -2252,6 +3872,78 @@ typedef struct { #define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_MASK) /*! @} */ +/*! @name INPUT_FETCH_SHIFT_CTRL_CH1_SET - Input Fetch Shift Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_MASK (0x3U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_SHIFT (0U) +/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_INPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_MASK (0x700U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_SHIFT (8U) +/*! EXPAND_FORMAT - EXPAND_FORMAT */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_FORMAT_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_MASK (0x800U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_SHIFT (11U) +/*! EXPAND_EN - EXPAND_EN */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_EXPAND_EN_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_MASK (0x1000U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_SHIFT (12U) +/*! SHIFT_BYPASS - SHIFT_BYPASS */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET_SHIFT_BYPASS_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_CTRL_CH1_CLR - Input Fetch Shift Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_MASK (0x3U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_SHIFT (0U) +/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_INPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_MASK (0x700U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_SHIFT (8U) +/*! EXPAND_FORMAT - EXPAND_FORMAT */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_FORMAT_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_MASK (0x800U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_SHIFT (11U) +/*! EXPAND_EN - EXPAND_EN */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_EXPAND_EN_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_MASK (0x1000U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_SHIFT (12U) +/*! SHIFT_BYPASS - SHIFT_BYPASS */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR_SHIFT_BYPASS_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_CTRL_CH1_TOG - Input Fetch Shift Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_MASK (0x3U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_SHIFT (0U) +/*! INPUT_ACTIVE_BPP - INPUT_ACTIVE_BPP */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_INPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_MASK (0x700U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_SHIFT (8U) +/*! EXPAND_FORMAT - EXPAND_FORMAT */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_FORMAT_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_MASK (0x800U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_SHIFT (11U) +/*! EXPAND_EN - EXPAND_EN */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_EXPAND_EN_MASK) + +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_MASK (0x1000U) +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_SHIFT (12U) +/*! SHIFT_BYPASS - SHIFT_BYPASS */ +#define PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG_SHIFT_BYPASS_MASK) +/*! @} */ + /*! @name INPUT_FETCH_SHIFT_OFFSET_CH0 - Input Fetch Shift Offset Channel 0 Register */ /*! @{ */ @@ -2276,6 +3968,78 @@ typedef struct { #define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK) /*! @} */ +/*! @name INPUT_FETCH_SHIFT_OFFSET_CH0_SET - Input Fetch Shift Offset Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_MASK (0x1FU) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_SHIFT (0U) +/*! OFFSET0 - OFFSET0 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_MASK (0x1F00U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_SHIFT (8U) +/*! OFFSET1 - OFFSET1 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_MASK (0x1F0000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_SHIFT (16U) +/*! OFFSET2 - OFFSET2 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_MASK (0x1F000000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_SHIFT (24U) +/*! OFFSET3 - OFFSET3 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET_OFFSET3_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_OFFSET_CH0_CLR - Input Fetch Shift Offset Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_MASK (0x1FU) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_SHIFT (0U) +/*! OFFSET0 - OFFSET0 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_MASK (0x1F00U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_SHIFT (8U) +/*! OFFSET1 - OFFSET1 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_MASK (0x1F0000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_SHIFT (16U) +/*! OFFSET2 - OFFSET2 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_MASK (0x1F000000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_SHIFT (24U) +/*! OFFSET3 - OFFSET3 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR_OFFSET3_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_OFFSET_CH0_TOG - Input Fetch Shift Offset Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_MASK (0x1FU) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_SHIFT (0U) +/*! OFFSET0 - OFFSET0 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_MASK (0x1F00U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_SHIFT (8U) +/*! OFFSET1 - OFFSET1 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_MASK (0x1F0000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_SHIFT (16U) +/*! OFFSET2 - OFFSET2 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_MASK (0x1F000000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_SHIFT (24U) +/*! OFFSET3 - OFFSET3 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG_OFFSET3_MASK) +/*! @} */ + /*! @name INPUT_FETCH_SHIFT_OFFSET_CH1 - Input Fetch Shift Offset Channel 1 Register */ /*! @{ */ @@ -2300,6 +4064,78 @@ typedef struct { #define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK) /*! @} */ +/*! @name INPUT_FETCH_SHIFT_OFFSET_CH1_SET - Input Fetch Shift Offset Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_MASK (0x1FU) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_SHIFT (0U) +/*! OFFSET0 - OFFSET0 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_MASK (0x1F00U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_SHIFT (8U) +/*! OFFSET1 - OFFSET1 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_MASK (0x1F0000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_SHIFT (16U) +/*! OFFSET2 - OFFSET2 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_MASK (0x1F000000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_SHIFT (24U) +/*! OFFSET3 - OFFSET3 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET_OFFSET3_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_OFFSET_CH1_CLR - Input Fetch Shift Offset Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_MASK (0x1FU) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_SHIFT (0U) +/*! OFFSET0 - OFFSET0 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_MASK (0x1F00U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_SHIFT (8U) +/*! OFFSET1 - OFFSET1 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_MASK (0x1F0000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_SHIFT (16U) +/*! OFFSET2 - OFFSET2 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_MASK (0x1F000000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_SHIFT (24U) +/*! OFFSET3 - OFFSET3 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR_OFFSET3_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_OFFSET_CH1_TOG - Input Fetch Shift Offset Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_MASK (0x1FU) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_SHIFT (0U) +/*! OFFSET0 - OFFSET0 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_MASK (0x1F00U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_SHIFT (8U) +/*! OFFSET1 - OFFSET1 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_MASK (0x1F0000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_SHIFT (16U) +/*! OFFSET2 - OFFSET2 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_MASK (0x1F000000U) +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_SHIFT (24U) +/*! OFFSET3 - OFFSET3 */ +#define PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG_OFFSET3_MASK) +/*! @} */ + /*! @name INPUT_FETCH_SHIFT_WIDTH_CH0 - Input Fetch Shift Width Channel 0 Register */ /*! @{ */ @@ -2324,6 +4160,78 @@ typedef struct { #define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK) /*! @} */ +/*! @name INPUT_FETCH_SHIFT_WIDTH_CH0_SET - Input Fetch Shift Width Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_MASK (0xFU) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_SHIFT (0U) +/*! WIDTH0 - WIDTH0 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_MASK (0xF0U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_SHIFT (4U) +/*! WIDTH1 - WIDTH1 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_MASK (0xF00U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_SHIFT (8U) +/*! WIDTH2 - WIDTH2 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_MASK (0xF000U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_SHIFT (12U) +/*! WIDTH3 - WIDTH3 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET_WIDTH3_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_WIDTH_CH0_CLR - Input Fetch Shift Width Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_MASK (0xFU) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_SHIFT (0U) +/*! WIDTH0 - WIDTH0 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_MASK (0xF0U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_SHIFT (4U) +/*! WIDTH1 - WIDTH1 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_MASK (0xF00U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_SHIFT (8U) +/*! WIDTH2 - WIDTH2 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_MASK (0xF000U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_SHIFT (12U) +/*! WIDTH3 - WIDTH3 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR_WIDTH3_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_WIDTH_CH0_TOG - Input Fetch Shift Width Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_MASK (0xFU) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_SHIFT (0U) +/*! WIDTH0 - WIDTH0 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_MASK (0xF0U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_SHIFT (4U) +/*! WIDTH1 - WIDTH1 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_MASK (0xF00U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_SHIFT (8U) +/*! WIDTH2 - WIDTH2 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_MASK (0xF000U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_SHIFT (12U) +/*! WIDTH3 - WIDTH3 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG_WIDTH3_MASK) +/*! @} */ + /*! @name INPUT_FETCH_SHIFT_WIDTH_CH1 - Input Fetch Shift Width Channel 1 Register */ /*! @{ */ @@ -2348,6 +4256,78 @@ typedef struct { #define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK) /*! @} */ +/*! @name INPUT_FETCH_SHIFT_WIDTH_CH1_SET - Input Fetch Shift Width Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_MASK (0xFU) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_SHIFT (0U) +/*! WIDTH0 - WIDTH0 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_MASK (0xF0U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_SHIFT (4U) +/*! WIDTH1 - WIDTH1 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_MASK (0xF00U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_SHIFT (8U) +/*! WIDTH2 - WIDTH2 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_MASK (0xF000U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_SHIFT (12U) +/*! WIDTH3 - WIDTH3 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET_WIDTH3_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_WIDTH_CH1_CLR - Input Fetch Shift Width Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_MASK (0xFU) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_SHIFT (0U) +/*! WIDTH0 - WIDTH0 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_MASK (0xF0U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_SHIFT (4U) +/*! WIDTH1 - WIDTH1 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_MASK (0xF00U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_SHIFT (8U) +/*! WIDTH2 - WIDTH2 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_MASK (0xF000U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_SHIFT (12U) +/*! WIDTH3 - WIDTH3 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR_WIDTH3_MASK) +/*! @} */ + +/*! @name INPUT_FETCH_SHIFT_WIDTH_CH1_TOG - Input Fetch Shift Width Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_MASK (0xFU) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_SHIFT (0U) +/*! WIDTH0 - WIDTH0 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH0_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_MASK (0xF0U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_SHIFT (4U) +/*! WIDTH1 - WIDTH1 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH1_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_MASK (0xF00U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_SHIFT (8U) +/*! WIDTH2 - WIDTH2 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH2_MASK) + +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_MASK (0xF000U) +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_SHIFT (12U) +/*! WIDTH3 - WIDTH3 */ +#define PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_SHIFT)) & PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG_WIDTH3_MASK) +/*! @} */ + /*! @name INPUT_FETCH_ADDR_0_CH0 - Input Fetch Address 0 Channel 0 Register */ /*! @{ */ @@ -2458,6 +4438,138 @@ typedef struct { #define PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_MASK) /*! @} */ +/*! @name INPUT_STORE_CTRL_CH0_SET - Input Store Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN_MASK (0x1U) +#define PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_CH_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_16_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT (9U) +/*! STORE_MEMORY_EN - STORE_MEMORY_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK (0x800U) +#define PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT (11U) +/*! FILL_DATA_EN - FILL_DATA_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_32_MASK (0x1000U) +#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_32_SHIFT (12U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_32_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_BLOCK_32_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT (16U) +/*! WR_NUM_BYTES - WR_NUM_BYTES */ +#define PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U) +#define PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U) +/*! ARBIT_EN - ARBIT_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_SET_ARBIT_EN_MASK) +/*! @} */ + +/*! @name INPUT_STORE_CTRL_CH0_CLR - Input Store Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN_MASK (0x1U) +#define PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_CH_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_16_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT (9U) +/*! STORE_MEMORY_EN - STORE_MEMORY_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK (0x800U) +#define PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT (11U) +/*! FILL_DATA_EN - FILL_DATA_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_32_MASK (0x1000U) +#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_32_SHIFT (12U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_32_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_BLOCK_32_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT (16U) +/*! WR_NUM_BYTES - WR_NUM_BYTES */ +#define PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U) +#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U) +/*! ARBIT_EN - ARBIT_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK) +/*! @} */ + +/*! @name INPUT_STORE_CTRL_CH0_TOG - Input Store Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN_MASK (0x1U) +#define PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_CH_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_16_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT (9U) +/*! STORE_MEMORY_EN - STORE_MEMORY_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK (0x800U) +#define PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT (11U) +/*! FILL_DATA_EN - FILL_DATA_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_32_MASK (0x1000U) +#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_32_SHIFT (12U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_32_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_BLOCK_32_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT (16U) +/*! WR_NUM_BYTES - WR_NUM_BYTES */ +#define PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK) + +#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U) +#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U) +/*! ARBIT_EN - ARBIT_EN */ +#define PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK) +/*! @} */ + /*! @name INPUT_STORE_CTRL_CH1 - Input Store Control Channel 1 Register */ /*! @{ */ @@ -2516,6 +4628,108 @@ typedef struct { #define PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_MASK) /*! @} */ +/*! @name INPUT_STORE_CTRL_CH1_SET - Input Store Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN_MASK (0x1U) +#define PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_CH_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_16_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT (9U) +/*! STORE_MEMORY_EN - STORE_MEMORY_EN */ +#define PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_32_MASK (0x1000U) +#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_32_SHIFT (12U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_32_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_BLOCK_32_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT (16U) +/*! WR_NUM_BYTES - WR_NUM_BYTES */ +#define PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK) +/*! @} */ + +/*! @name INPUT_STORE_CTRL_CH1_CLR - Input Store Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN_MASK (0x1U) +#define PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_CH_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_16_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT (9U) +/*! STORE_MEMORY_EN - STORE_MEMORY_EN */ +#define PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_32_MASK (0x1000U) +#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_32_SHIFT (12U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_32_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_BLOCK_32_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT (16U) +/*! WR_NUM_BYTES - WR_NUM_BYTES */ +#define PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK) +/*! @} */ + +/*! @name INPUT_STORE_CTRL_CH1_TOG - Input Store Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN_MASK (0x1U) +#define PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN_SHIFT (0U) +/*! CH_EN - CH_EN */ +#define PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_CH_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U) +/*! BLOCK_EN - BLOCK_EN */ +#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U) +#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U) +/*! BLOCK_16 - BLOCK_16 */ +#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_16_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT (9U) +/*! STORE_MEMORY_EN - STORE_MEMORY_EN */ +#define PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_32_MASK (0x1000U) +#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_32_SHIFT (12U) +/*! BLOCK_32 - BLOCK_32 */ +#define PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_32(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_32_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_BLOCK_32_MASK) + +#define PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK (0x70000U) +#define PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT (16U) +/*! WR_NUM_BYTES - WR_NUM_BYTES */ +#define PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT)) & PXP_INPUT_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK) +/*! @} */ + /*! @name INPUT_STORE_STATUS_CH0 - Input Store Status Channel 0 Register */ /*! @{ */ @@ -2624,6 +4838,78 @@ typedef struct { #define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK) /*! @} */ +/*! @name INPUT_STORE_SHIFT_CTRL_CH0_SET - Input Store Shift Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT (4U) +/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT (5U) +/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x80U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (7U) +/*! SHIFT_BYPASS - SHIFT_BYPASS */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK) +/*! @} */ + +/*! @name INPUT_STORE_SHIFT_CTRL_CH0_CLR - Input Store Shift Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x80U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (7U) +/*! SHIFT_BYPASS - SHIFT_BYPASS */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK) +/*! @} */ + +/*! @name INPUT_STORE_SHIFT_CTRL_CH0_TOG - Input Store Shift Control Channel 0 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x80U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (7U) +/*! SHIFT_BYPASS - SHIFT_BYPASS */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK) +/*! @} */ + /*! @name INPUT_STORE_SHIFT_CTRL_CH1 - Input Store Shift Control Channel 1 Register */ /*! @{ */ @@ -2654,6 +4940,63 @@ typedef struct { #define PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK) /*! @} */ +/*! @name INPUT_STORE_SHIFT_CTRL_CH1_SET - Input Store Shift Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT (4U) +/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT (5U) +/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK) +/*! @} */ + +/*! @name INPUT_STORE_SHIFT_CTRL_CH1_CLR - Input Store Shift Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK) +/*! @} */ + +/*! @name INPUT_STORE_SHIFT_CTRL_CH1_TOG - Input Store Shift Control Channel 1 Register */ +/*! @{ */ + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +/*! OUTPUT_ACTIVE_BPP - OUTPUT_ACTIVE_BPP */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +/*! OUT_YUV422_1P_EN - OUT_YUV422_1P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK) + +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +/*! OUT_YUV422_2P_EN - OUT_YUV422_2P_EN */ +#define PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK) +/*! @} */ + /*! @name INPUT_STORE_ADDR_0_CH0 - Input Store Address 0 Channel 0 Register */ /*! @{ */ @@ -3002,5 +5345,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* PXP_H_ */ +#endif /* PERI_PXP_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_RGPIO.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_RGPIO.h index 8778a4667..839643c6d 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_RGPIO.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_RGPIO.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for RGPIO @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file RGPIO.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_RGPIO.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for RGPIO * * CMSIS Peripheral Access Layer for RGPIO */ -#if !defined(RGPIO_H_) -#define RGPIO_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_RGPIO_H_) +#define PERI_RGPIO_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2771,10 +2774,10 @@ typedef struct { #define RGPIO_ICR_ISF_MASK (0x1000000U) #define RGPIO_ICR_ISF_SHIFT (24U) /*! ISF - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_ISF_SHIFT)) & RGPIO_ICR_ISF_MASK) /*! @} */ @@ -3059,320 +3062,320 @@ typedef struct { #define RGPIO_ISFR_ISF0_MASK (0x1U) #define RGPIO_ISFR_ISF0_SHIFT (0U) /*! ISF0 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF0_SHIFT)) & RGPIO_ISFR_ISF0_MASK) #define RGPIO_ISFR_ISF1_MASK (0x2U) #define RGPIO_ISFR_ISF1_SHIFT (1U) /*! ISF1 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF1_SHIFT)) & RGPIO_ISFR_ISF1_MASK) #define RGPIO_ISFR_ISF2_MASK (0x4U) #define RGPIO_ISFR_ISF2_SHIFT (2U) /*! ISF2 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF2_SHIFT)) & RGPIO_ISFR_ISF2_MASK) #define RGPIO_ISFR_ISF3_MASK (0x8U) #define RGPIO_ISFR_ISF3_SHIFT (3U) /*! ISF3 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF3_SHIFT)) & RGPIO_ISFR_ISF3_MASK) #define RGPIO_ISFR_ISF4_MASK (0x10U) #define RGPIO_ISFR_ISF4_SHIFT (4U) /*! ISF4 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF4_SHIFT)) & RGPIO_ISFR_ISF4_MASK) #define RGPIO_ISFR_ISF5_MASK (0x20U) #define RGPIO_ISFR_ISF5_SHIFT (5U) /*! ISF5 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF5_SHIFT)) & RGPIO_ISFR_ISF5_MASK) #define RGPIO_ISFR_ISF6_MASK (0x40U) #define RGPIO_ISFR_ISF6_SHIFT (6U) /*! ISF6 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF6_SHIFT)) & RGPIO_ISFR_ISF6_MASK) #define RGPIO_ISFR_ISF7_MASK (0x80U) #define RGPIO_ISFR_ISF7_SHIFT (7U) /*! ISF7 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF7_SHIFT)) & RGPIO_ISFR_ISF7_MASK) #define RGPIO_ISFR_ISF8_MASK (0x100U) #define RGPIO_ISFR_ISF8_SHIFT (8U) /*! ISF8 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF8_SHIFT)) & RGPIO_ISFR_ISF8_MASK) #define RGPIO_ISFR_ISF9_MASK (0x200U) #define RGPIO_ISFR_ISF9_SHIFT (9U) /*! ISF9 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF9_SHIFT)) & RGPIO_ISFR_ISF9_MASK) #define RGPIO_ISFR_ISF10_MASK (0x400U) #define RGPIO_ISFR_ISF10_SHIFT (10U) /*! ISF10 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF10_SHIFT)) & RGPIO_ISFR_ISF10_MASK) #define RGPIO_ISFR_ISF11_MASK (0x800U) #define RGPIO_ISFR_ISF11_SHIFT (11U) /*! ISF11 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF11_SHIFT)) & RGPIO_ISFR_ISF11_MASK) #define RGPIO_ISFR_ISF12_MASK (0x1000U) #define RGPIO_ISFR_ISF12_SHIFT (12U) /*! ISF12 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF12_SHIFT)) & RGPIO_ISFR_ISF12_MASK) #define RGPIO_ISFR_ISF13_MASK (0x2000U) #define RGPIO_ISFR_ISF13_SHIFT (13U) /*! ISF13 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF13_SHIFT)) & RGPIO_ISFR_ISF13_MASK) #define RGPIO_ISFR_ISF14_MASK (0x4000U) #define RGPIO_ISFR_ISF14_SHIFT (14U) /*! ISF14 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF14_SHIFT)) & RGPIO_ISFR_ISF14_MASK) #define RGPIO_ISFR_ISF15_MASK (0x8000U) #define RGPIO_ISFR_ISF15_SHIFT (15U) /*! ISF15 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF15_SHIFT)) & RGPIO_ISFR_ISF15_MASK) #define RGPIO_ISFR_ISF16_MASK (0x10000U) #define RGPIO_ISFR_ISF16_SHIFT (16U) /*! ISF16 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF16_SHIFT)) & RGPIO_ISFR_ISF16_MASK) #define RGPIO_ISFR_ISF17_MASK (0x20000U) #define RGPIO_ISFR_ISF17_SHIFT (17U) /*! ISF17 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF17_SHIFT)) & RGPIO_ISFR_ISF17_MASK) #define RGPIO_ISFR_ISF18_MASK (0x40000U) #define RGPIO_ISFR_ISF18_SHIFT (18U) /*! ISF18 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF18_SHIFT)) & RGPIO_ISFR_ISF18_MASK) #define RGPIO_ISFR_ISF19_MASK (0x80000U) #define RGPIO_ISFR_ISF19_SHIFT (19U) /*! ISF19 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF19_SHIFT)) & RGPIO_ISFR_ISF19_MASK) #define RGPIO_ISFR_ISF20_MASK (0x100000U) #define RGPIO_ISFR_ISF20_SHIFT (20U) /*! ISF20 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF20_SHIFT)) & RGPIO_ISFR_ISF20_MASK) #define RGPIO_ISFR_ISF21_MASK (0x200000U) #define RGPIO_ISFR_ISF21_SHIFT (21U) /*! ISF21 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF21_SHIFT)) & RGPIO_ISFR_ISF21_MASK) #define RGPIO_ISFR_ISF22_MASK (0x400000U) #define RGPIO_ISFR_ISF22_SHIFT (22U) /*! ISF22 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF22_SHIFT)) & RGPIO_ISFR_ISF22_MASK) #define RGPIO_ISFR_ISF23_MASK (0x800000U) #define RGPIO_ISFR_ISF23_SHIFT (23U) /*! ISF23 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF23_SHIFT)) & RGPIO_ISFR_ISF23_MASK) #define RGPIO_ISFR_ISF24_MASK (0x1000000U) #define RGPIO_ISFR_ISF24_SHIFT (24U) /*! ISF24 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF24_SHIFT)) & RGPIO_ISFR_ISF24_MASK) #define RGPIO_ISFR_ISF25_MASK (0x2000000U) #define RGPIO_ISFR_ISF25_SHIFT (25U) /*! ISF25 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF25_SHIFT)) & RGPIO_ISFR_ISF25_MASK) #define RGPIO_ISFR_ISF26_MASK (0x4000000U) #define RGPIO_ISFR_ISF26_SHIFT (26U) /*! ISF26 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF26_SHIFT)) & RGPIO_ISFR_ISF26_MASK) #define RGPIO_ISFR_ISF27_MASK (0x8000000U) #define RGPIO_ISFR_ISF27_SHIFT (27U) /*! ISF27 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF27_SHIFT)) & RGPIO_ISFR_ISF27_MASK) #define RGPIO_ISFR_ISF28_MASK (0x10000000U) #define RGPIO_ISFR_ISF28_SHIFT (28U) /*! ISF28 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF28_SHIFT)) & RGPIO_ISFR_ISF28_MASK) #define RGPIO_ISFR_ISF29_MASK (0x20000000U) #define RGPIO_ISFR_ISF29_SHIFT (29U) /*! ISF29 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF29_SHIFT)) & RGPIO_ISFR_ISF29_MASK) #define RGPIO_ISFR_ISF30_MASK (0x40000000U) #define RGPIO_ISFR_ISF30_SHIFT (30U) /*! ISF30 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF30_SHIFT)) & RGPIO_ISFR_ISF30_MASK) #define RGPIO_ISFR_ISF31_MASK (0x80000000U) #define RGPIO_ISFR_ISF31_SHIFT (31U) /*! ISF31 - Interrupt Status Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define RGPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF31_SHIFT)) & RGPIO_ISFR_ISF31_MASK) /*! @} */ @@ -3411,5 +3414,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* RGPIO_H_ */ +#endif /* PERI_RGPIO_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_S3MU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_S3MU.h index 58642cbc7..dc03b44cb 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_S3MU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_S3MU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for S3MU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file S3MU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_S3MU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for S3MU * * CMSIS Peripheral Access Layer for S3MU */ -#if !defined(S3MU_H_) -#define S3MU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_S3MU_H_) +#define PERI_S3MU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -444,5 +447,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* S3MU_H_ */ +#endif /* PERI_S3MU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SEMA42.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SEMA42.h index 7d0fcf37d..56f366b72 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SEMA42.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SEMA42.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMA42 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SEMA42.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SEMA42.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SEMA42 * * CMSIS Peripheral Access Layer for SEMA42 */ -#if !defined(SEMA42_H_) -#define SEMA42_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SEMA42_H_) +#define PERI_SEMA42_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2044,5 +2047,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SEMA42_H_ */ +#endif /* PERI_SEMA42_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SERDES_SS.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SERDES_SS.h index 14580a72b..c03045efd 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SERDES_SS.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SERDES_SS.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SerDes_SS @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SerDes_SS.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SerDes_SS.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SerDes_SS * * CMSIS Peripheral Access Layer for SerDes_SS */ -#if !defined(SerDes_SS_H_) -#define SerDes_SS_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SERDES_SS_H_) +#define PERI_SERDES_SS_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2710,8 +2713,8 @@ typedef struct { #define SerDes_SS_PE0_ERR_STS_VC_QOVERFLOW_MASK (0x10000U) #define SerDes_SS_PE0_ERR_STS_VC_QOVERFLOW_SHIFT (16U) /*! VC_QOVERFLOW - RADM Queue Overflow Error - * 0b0..No overflow error detected * 0b0..No effect + * 0b0..No overflow error detected * 0b1..Overflow error detected * 0b1..Return this field's value to 0 */ @@ -2733,8 +2736,8 @@ typedef struct { #define SerDes_SS_PE0_ERR_STS_LINK_DOWN_STS_MASK (0x40000000U) #define SerDes_SS_PE0_ERR_STS_LINK_DOWN_STS_SHIFT (30U) /*! LINK_DOWN_STS - Link Down Event - * 0b0..No link down error detected * 0b0..No effect + * 0b0..No link down error detected * 0b1..Link down error detected * 0b1..Return this field's value to 0 */ @@ -2743,10 +2746,10 @@ typedef struct { #define SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS_MASK (0x80000000U) #define SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS_SHIFT (31U) /*! APBSLV_TIMEOUT_STS - APB Slave Timeout Error - * 0b0..No timeout error detected * 0b0..No effect - * 0b1..Timeout error detected + * 0b0..No timeout error detected * 0b1..Return this field's value to 0 + * 0b1..Timeout error detected */ #define SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS_SHIFT)) & SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS_MASK) /*! @} */ @@ -3226,5 +3229,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SerDes_SS_H_ */ +#endif /* PERI_SERDES_SS_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SINC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SINC.h index b564b44f5..e66ca48d4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SINC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SINC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SINC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SINC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SINC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SINC * * CMSIS Peripheral Access Layer for SINC */ -#if !defined(SINC_H_) -#define SINC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SINC_H_) +#define PERI_SINC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -784,120 +787,120 @@ typedef struct { #define SINC_NIS_COC0_MASK (0x1U) #define SINC_NIS_COC0_SHIFT (0U) /*! COC0 - Conversion Complete Flag - * 0b0..Not finished; data not available * 0b0..No effect - * 0b1..Finished; data available + * 0b0..Not finished; data not available * 0b1..Clear the flag + * 0b1..Finished; data available */ #define SINC_NIS_COC0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC0_SHIFT)) & SINC_NIS_COC0_MASK) #define SINC_NIS_COC1_MASK (0x2U) #define SINC_NIS_COC1_SHIFT (1U) /*! COC1 - Conversion Complete Flag - * 0b0..Not finished; data not available * 0b0..No effect - * 0b1..Finished; data available + * 0b0..Not finished; data not available * 0b1..Clear the flag + * 0b1..Finished; data available */ #define SINC_NIS_COC1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC1_SHIFT)) & SINC_NIS_COC1_MASK) #define SINC_NIS_COC2_MASK (0x4U) #define SINC_NIS_COC2_SHIFT (2U) /*! COC2 - Conversion Complete Flag - * 0b0..Not finished; data not available * 0b0..No effect - * 0b1..Finished; data available + * 0b0..Not finished; data not available * 0b1..Clear the flag + * 0b1..Finished; data available */ #define SINC_NIS_COC2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC2_SHIFT)) & SINC_NIS_COC2_MASK) #define SINC_NIS_COC3_MASK (0x8U) #define SINC_NIS_COC3_SHIFT (3U) /*! COC3 - Conversion Complete Flag - * 0b0..Not finished; data not available * 0b0..No effect - * 0b1..Finished; data available + * 0b0..Not finished; data not available * 0b1..Clear the flag + * 0b1..Finished; data available */ #define SINC_NIS_COC3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_COC3_SHIFT)) & SINC_NIS_COC3_MASK) #define SINC_NIS_CHF0_MASK (0x100U) #define SINC_NIS_CHF0_SHIFT (8U) /*! CHF0 - Data Output Ready Flag - * 0b0..No overflow; data not available * 0b0..No effect - * 0b1..Overflow; data available + * 0b0..No overflow; data not available * 0b1..Clear the flag + * 0b1..Overflow; data available */ #define SINC_NIS_CHF0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF0_SHIFT)) & SINC_NIS_CHF0_MASK) #define SINC_NIS_CHF1_MASK (0x200U) #define SINC_NIS_CHF1_SHIFT (9U) /*! CHF1 - Data Output Ready Flag - * 0b0..No overflow; data not available * 0b0..No effect - * 0b1..Overflow; data available + * 0b0..No overflow; data not available * 0b1..Clear the flag + * 0b1..Overflow; data available */ #define SINC_NIS_CHF1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF1_SHIFT)) & SINC_NIS_CHF1_MASK) #define SINC_NIS_CHF2_MASK (0x400U) #define SINC_NIS_CHF2_SHIFT (10U) /*! CHF2 - Data Output Ready Flag - * 0b0..No overflow; data not available * 0b0..No effect - * 0b1..Overflow; data available + * 0b0..No overflow; data not available * 0b1..Clear the flag + * 0b1..Overflow; data available */ #define SINC_NIS_CHF2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF2_SHIFT)) & SINC_NIS_CHF2_MASK) #define SINC_NIS_CHF3_MASK (0x800U) #define SINC_NIS_CHF3_SHIFT (11U) /*! CHF3 - Data Output Ready Flag - * 0b0..No overflow; data not available * 0b0..No effect - * 0b1..Overflow; data available + * 0b0..No overflow; data not available * 0b1..Clear the flag + * 0b1..Overflow; data available */ #define SINC_NIS_CHF3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_CHF3_SHIFT)) & SINC_NIS_CHF3_MASK) #define SINC_NIS_ZCD0_MASK (0x10000U) #define SINC_NIS_ZCD0_SHIFT (16U) /*! ZCD0 - Zero Cross Detected Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define SINC_NIS_ZCD0(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD0_SHIFT)) & SINC_NIS_ZCD0_MASK) #define SINC_NIS_ZCD1_MASK (0x20000U) #define SINC_NIS_ZCD1_SHIFT (17U) /*! ZCD1 - Zero Cross Detected Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define SINC_NIS_ZCD1(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD1_SHIFT)) & SINC_NIS_ZCD1_MASK) #define SINC_NIS_ZCD2_MASK (0x40000U) #define SINC_NIS_ZCD2_SHIFT (18U) /*! ZCD2 - Zero Cross Detected Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define SINC_NIS_ZCD2(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD2_SHIFT)) & SINC_NIS_ZCD2_MASK) #define SINC_NIS_ZCD3_MASK (0x80000U) #define SINC_NIS_ZCD3_SHIFT (19U) /*! ZCD3 - Zero Cross Detected Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define SINC_NIS_ZCD3(x) (((uint32_t)(((uint32_t)(x)) << SINC_NIS_ZCD3_SHIFT)) & SINC_NIS_ZCD3_MASK) /*! @} */ @@ -908,160 +911,160 @@ typedef struct { #define SINC_EIS_SCD0_MASK (0x1U) #define SINC_EIS_SCD0_SHIFT (0U) /*! SCD0 - Short Circuit Detected Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define SINC_EIS_SCD0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD0_SHIFT)) & SINC_EIS_SCD0_MASK) #define SINC_EIS_SCD1_MASK (0x2U) #define SINC_EIS_SCD1_SHIFT (1U) /*! SCD1 - Short Circuit Detected Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define SINC_EIS_SCD1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD1_SHIFT)) & SINC_EIS_SCD1_MASK) #define SINC_EIS_SCD2_MASK (0x4U) #define SINC_EIS_SCD2_SHIFT (2U) /*! SCD2 - Short Circuit Detected Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define SINC_EIS_SCD2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD2_SHIFT)) & SINC_EIS_SCD2_MASK) #define SINC_EIS_SCD3_MASK (0x8U) #define SINC_EIS_SCD3_SHIFT (3U) /*! SCD3 - Short Circuit Detected Flag - * 0b0..Not detected * 0b0..No effect - * 0b1..Detected + * 0b0..Not detected * 0b1..Clear the flag + * 0b1..Detected */ #define SINC_EIS_SCD3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_SCD3_SHIFT)) & SINC_EIS_SCD3_MASK) #define SINC_EIS_WLMT0_MASK (0x100U) #define SINC_EIS_WLMT0_SHIFT (8U) /*! WLMT0 - Window Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_WLMT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT0_SHIFT)) & SINC_EIS_WLMT0_MASK) #define SINC_EIS_WLMT1_MASK (0x200U) #define SINC_EIS_WLMT1_SHIFT (9U) /*! WLMT1 - Window Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_WLMT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT1_SHIFT)) & SINC_EIS_WLMT1_MASK) #define SINC_EIS_WLMT2_MASK (0x400U) #define SINC_EIS_WLMT2_SHIFT (10U) /*! WLMT2 - Window Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_WLMT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT2_SHIFT)) & SINC_EIS_WLMT2_MASK) #define SINC_EIS_WLMT3_MASK (0x800U) #define SINC_EIS_WLMT3_SHIFT (11U) /*! WLMT3 - Window Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_WLMT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_WLMT3_SHIFT)) & SINC_EIS_WLMT3_MASK) #define SINC_EIS_LLMT0_MASK (0x10000U) #define SINC_EIS_LLMT0_SHIFT (16U) /*! LLMT0 - Low Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_LLMT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT0_SHIFT)) & SINC_EIS_LLMT0_MASK) #define SINC_EIS_LLMT1_MASK (0x20000U) #define SINC_EIS_LLMT1_SHIFT (17U) /*! LLMT1 - Low Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_LLMT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT1_SHIFT)) & SINC_EIS_LLMT1_MASK) #define SINC_EIS_LLMT2_MASK (0x40000U) #define SINC_EIS_LLMT2_SHIFT (18U) /*! LLMT2 - Low Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_LLMT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT2_SHIFT)) & SINC_EIS_LLMT2_MASK) #define SINC_EIS_LLMT3_MASK (0x80000U) #define SINC_EIS_LLMT3_SHIFT (19U) /*! LLMT3 - Low Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_LLMT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_LLMT3_SHIFT)) & SINC_EIS_LLMT3_MASK) #define SINC_EIS_HLMT0_MASK (0x1000000U) #define SINC_EIS_HLMT0_SHIFT (24U) /*! HLMT0 - High Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_HLMT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT0_SHIFT)) & SINC_EIS_HLMT0_MASK) #define SINC_EIS_HLMT1_MASK (0x2000000U) #define SINC_EIS_HLMT1_SHIFT (25U) /*! HLMT1 - High Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_HLMT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT1_SHIFT)) & SINC_EIS_HLMT1_MASK) #define SINC_EIS_HLMT2_MASK (0x4000000U) #define SINC_EIS_HLMT2_SHIFT (26U) /*! HLMT2 - High Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_HLMT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT2_SHIFT)) & SINC_EIS_HLMT2_MASK) #define SINC_EIS_HLMT3_MASK (0x8000000U) #define SINC_EIS_HLMT3_SHIFT (27U) /*! HLMT3 - High Limit Flag - * 0b0..Not exceeded * 0b0..No effect - * 0b1..Exceeded + * 0b0..Not exceeded * 0b1..Clear the flag + * 0b1..Exceeded */ #define SINC_EIS_HLMT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_EIS_HLMT3_SHIFT)) & SINC_EIS_HLMT3_MASK) /*! @} */ @@ -1074,8 +1077,8 @@ typedef struct { /*! FUNF0 - FIFO Underflow Flag * 0b0..Did not occur * 0b0..No effect - * 0b1..Occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define SINC_FIFOIS_FUNF0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF0_SHIFT)) & SINC_FIFOIS_FUNF0_MASK) @@ -1084,8 +1087,8 @@ typedef struct { /*! FUNF1 - FIFO Underflow Flag * 0b0..Did not occur * 0b0..No effect - * 0b1..Occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define SINC_FIFOIS_FUNF1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF1_SHIFT)) & SINC_FIFOIS_FUNF1_MASK) @@ -1094,8 +1097,8 @@ typedef struct { /*! FUNF2 - FIFO Underflow Flag * 0b0..Did not occur * 0b0..No effect - * 0b1..Occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define SINC_FIFOIS_FUNF2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF2_SHIFT)) & SINC_FIFOIS_FUNF2_MASK) @@ -1104,8 +1107,8 @@ typedef struct { /*! FUNF3 - FIFO Underflow Flag * 0b0..Did not occur * 0b0..No effect - * 0b1..Occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define SINC_FIFOIS_FUNF3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FUNF3_SHIFT)) & SINC_FIFOIS_FUNF3_MASK) @@ -1114,8 +1117,8 @@ typedef struct { /*! FOVF0 - FIFO Overflow Flag * 0b0..Did not occur * 0b0..No effect - * 0b1..Occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define SINC_FIFOIS_FOVF0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF0_SHIFT)) & SINC_FIFOIS_FOVF0_MASK) @@ -1124,8 +1127,8 @@ typedef struct { /*! FOVF1 - FIFO Overflow Flag * 0b0..Did not occur * 0b0..No effect - * 0b1..Occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define SINC_FIFOIS_FOVF1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF1_SHIFT)) & SINC_FIFOIS_FOVF1_MASK) @@ -1134,8 +1137,8 @@ typedef struct { /*! FOVF2 - FIFO Overflow Flag * 0b0..Did not occur * 0b0..No effect - * 0b1..Occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define SINC_FIFOIS_FOVF2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF2_SHIFT)) & SINC_FIFOIS_FOVF2_MASK) @@ -1144,8 +1147,8 @@ typedef struct { /*! FOVF3 - FIFO Overflow Flag * 0b0..Did not occur * 0b0..No effect - * 0b1..Occurred * 0b1..Clear the flag + * 0b1..Occurred */ #define SINC_FIFOIS_FOVF3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_FOVF3_SHIFT)) & SINC_FIFOIS_FOVF3_MASK) @@ -1154,8 +1157,8 @@ typedef struct { /*! CAD0 - Clock Absence Flag * 0b0..Clock present * 0b0..No effect - * 0b1..Clock absent * 0b1..Clear the flag + * 0b1..Clock absent */ #define SINC_FIFOIS_CAD0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD0_SHIFT)) & SINC_FIFOIS_CAD0_MASK) @@ -1164,8 +1167,8 @@ typedef struct { /*! CAD1 - Clock Absence Flag * 0b0..Clock present * 0b0..No effect - * 0b1..Clock absent * 0b1..Clear the flag + * 0b1..Clock absent */ #define SINC_FIFOIS_CAD1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD1_SHIFT)) & SINC_FIFOIS_CAD1_MASK) @@ -1174,8 +1177,8 @@ typedef struct { /*! CAD2 - Clock Absence Flag * 0b0..Clock present * 0b0..No effect - * 0b1..Clock absent * 0b1..Clear the flag + * 0b1..Clock absent */ #define SINC_FIFOIS_CAD2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD2_SHIFT)) & SINC_FIFOIS_CAD2_MASK) @@ -1184,48 +1187,48 @@ typedef struct { /*! CAD3 - Clock Absence Flag * 0b0..Clock present * 0b0..No effect - * 0b1..Clock absent * 0b1..Clear the flag + * 0b1..Clock absent */ #define SINC_FIFOIS_CAD3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_CAD3_SHIFT)) & SINC_FIFOIS_CAD3_MASK) #define SINC_FIFOIS_SAT0_MASK (0x1000000U) #define SINC_FIFOIS_SAT0_SHIFT (24U) /*! SAT0 - Saturation Flag - * 0b0..Not saturated * 0b0..No effect - * 0b1..Saturated + * 0b0..Not saturated * 0b1..Clear the flag + * 0b1..Saturated */ #define SINC_FIFOIS_SAT0(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT0_SHIFT)) & SINC_FIFOIS_SAT0_MASK) #define SINC_FIFOIS_SAT1_MASK (0x2000000U) #define SINC_FIFOIS_SAT1_SHIFT (25U) /*! SAT1 - Saturation Flag - * 0b0..Not saturated * 0b0..No effect - * 0b1..Saturated + * 0b0..Not saturated * 0b1..Clear the flag + * 0b1..Saturated */ #define SINC_FIFOIS_SAT1(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT1_SHIFT)) & SINC_FIFOIS_SAT1_MASK) #define SINC_FIFOIS_SAT2_MASK (0x4000000U) #define SINC_FIFOIS_SAT2_SHIFT (26U) /*! SAT2 - Saturation Flag - * 0b0..Not saturated * 0b0..No effect - * 0b1..Saturated + * 0b0..Not saturated * 0b1..Clear the flag + * 0b1..Saturated */ #define SINC_FIFOIS_SAT2(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT2_SHIFT)) & SINC_FIFOIS_SAT2_MASK) #define SINC_FIFOIS_SAT3_MASK (0x8000000U) #define SINC_FIFOIS_SAT3_SHIFT (27U) /*! SAT3 - Saturation Flag - * 0b0..Not saturated * 0b0..No effect - * 0b1..Saturated + * 0b0..Not saturated * 0b1..Clear the flag + * 0b1..Saturated */ #define SINC_FIFOIS_SAT3(x) (((uint32_t)(((uint32_t)(x)) << SINC_FIFOIS_SAT3_SHIFT)) & SINC_FIFOIS_SAT3_MASK) /*! @} */ @@ -1928,5 +1931,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SINC_H_ */ +#endif /* PERI_SINC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRAMCTL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRAMCTL.h index e234c6fc6..d245d2831 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRAMCTL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRAMCTL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRAMCTL @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SRAMCTL.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SRAMCTL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SRAMCTL * * CMSIS Peripheral Access Layer for SRAMCTL */ -#if !defined(SRAMCTL_H_) -#define SRAMCTL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SRAMCTL_H_) +#define PERI_SRAMCTL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -530,5 +533,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SRAMCTL_H_ */ +#endif /* PERI_SRAMCTL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_GEN.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_GEN.h index 07496ec72..ca443c596 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_GEN.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_GEN.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_GEN @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SRC_GEN.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SRC_GEN.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SRC_GEN * * CMSIS Peripheral Access Layer for SRC_GEN */ -#if !defined(SRC_GEN_H_) -#define SRC_GEN_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SRC_GEN_H_) +#define PERI_SRC_GEN_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1837,5 +1840,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SRC_GEN_H_ */ +#endif /* PERI_SRC_GEN_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_MEM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_MEM.h index e2bd55fac..306fef2a3 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_MEM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_MEM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_MEM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SRC_MEM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SRC_MEM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SRC_MEM * * CMSIS Peripheral Access Layer for SRC_MEM */ -#if !defined(SRC_MEM_H_) -#define SRC_MEM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SRC_MEM_H_) +#define PERI_SRC_MEM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -394,5 +397,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SRC_MEM_H_ */ +#endif /* PERI_SRC_MEM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_XSPR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_XSPR.h index c5f6c843c..6058830ca 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_XSPR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SRC_XSPR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_XSPR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SRC_XSPR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SRC_XSPR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SRC_XSPR * * CMSIS Peripheral Access Layer for SRC_XSPR */ -#if !defined(SRC_XSPR_H_) -#define SRC_XSPR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SRC_XSPR_H_) +#define PERI_SRC_XSPR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1476,5 +1479,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SRC_XSPR_H_ */ +#endif /* PERI_SRC_XSPR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_GLOBAL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_GLOBAL.h index 59a9b38e7..036b7fd97 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_GLOBAL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_GLOBAL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SW_GLOBAL @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SW_GLOBAL.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SW_GLOBAL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SW_GLOBAL * * CMSIS Peripheral Access Layer for SW_GLOBAL */ -#if !defined(SW_GLOBAL_H_) -#define SW_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SW_GLOBAL_H_) +#define PERI_SW_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -717,5 +720,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SW_GLOBAL_H_ */ +#endif /* PERI_SW_GLOBAL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_PORT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_PORT.h index f9ecb3d94..aa6d4f10c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_PORT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_PORT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SW_PORT @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SW_PORT.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SW_PORT.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SW_PORT * * CMSIS Peripheral Access Layer for SW_PORT */ -#if !defined(SW_PORT_H_) -#define SW_PORT_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SW_PORT_H_) +#define PERI_SW_PORT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1642,5 +1645,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SW_PORT_H_ */ +#endif /* PERI_SW_PORT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_PSEUDO_MAC_PORT.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_PSEUDO_MAC_PORT.h index 27508ff08..62d8f0fc7 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_PSEUDO_MAC_PORT.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SW_PSEUDO_MAC_PORT.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SW_PSEUDO_MAC_PORT @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SW_PSEUDO_MAC_PORT.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SW_PSEUDO_MAC_PORT.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SW_PSEUDO_MAC_PORT * * CMSIS Peripheral Access Layer for SW_PSEUDO_MAC_PORT */ -#if !defined(SW_PSEUDO_MAC_PORT_H_) -#define SW_PSEUDO_MAC_PORT_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SW_PSEUDO_MAC_PORT_H_) +#define PERI_SW_PSEUDO_MAC_PORT_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -369,5 +372,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SW_PSEUDO_MAC_PORT_H_ */ +#endif /* PERI_SW_PSEUDO_MAC_PORT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_COMPARE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_COMPARE.h index f7341fd03..2532d015b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_COMPARE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_COMPARE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYS_CTR_COMPARE @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SYS_CTR_COMPARE.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SYS_CTR_COMPARE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SYS_CTR_COMPARE * * CMSIS Peripheral Access Layer for SYS_CTR_COMPARE */ -#if !defined(SYS_CTR_COMPARE_H_) -#define SYS_CTR_COMPARE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SYS_CTR_COMPARE_H_) +#define PERI_SYS_CTR_COMPARE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -385,5 +388,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SYS_CTR_COMPARE_H_ */ +#endif /* PERI_SYS_CTR_COMPARE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_CONTROL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_CONTROL.h index bf5911e86..cc9bd7d46 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_CONTROL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_CONTROL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYS_CTR_CONTROL @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SYS_CTR_CONTROL.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SYS_CTR_CONTROL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SYS_CTR_CONTROL * * CMSIS Peripheral Access Layer for SYS_CTR_CONTROL */ -#if !defined(SYS_CTR_CONTROL_H_) -#define SYS_CTR_CONTROL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SYS_CTR_CONTROL_H_) +#define PERI_SYS_CTR_CONTROL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -400,5 +403,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SYS_CTR_CONTROL_H_ */ +#endif /* PERI_SYS_CTR_CONTROL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_READ.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_READ.h index c2fbfe144..8a42f7b1b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_READ.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_SYS_CTR_READ.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYS_CTR_READ @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file SYS_CTR_READ.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_SYS_CTR_READ.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for SYS_CTR_READ * * CMSIS Peripheral Access Layer for SYS_CTR_READ */ -#if !defined(SYS_CTR_READ_H_) -#define SYS_CTR_READ_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_SYS_CTR_READ_H_) +#define PERI_SYS_CTR_READ_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -304,5 +307,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* SYS_CTR_READ_H_ */ +#endif /* PERI_SYS_CTR_READ_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TCM_ECC_MCM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TCM_ECC_MCM.h index b477349a5..3ef2578b0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TCM_ECC_MCM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TCM_ECC_MCM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TCM_ECC_MCM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TCM_ECC_MCM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_TCM_ECC_MCM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TCM_ECC_MCM * * CMSIS Peripheral Access Layer for TCM_ECC_MCM */ -#if !defined(TCM_ECC_MCM_H_) -#define TCM_ECC_MCM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TCM_ECC_MCM_H_) +#define PERI_TCM_ECC_MCM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -285,40 +288,40 @@ typedef struct { #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_MASK (0x400U) #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_SHIFT (10U) /*! CODE_TCM_ECC_ERRM_INT - Code TCM Access Multibit ECC Error Interrupt Status - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_MASK) #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_MASK (0x800U) #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_SHIFT (11U) /*! CODE_TCM_ECC_ERRS_INT - Code TCM Access Single-Bit ECC Error Interrupt Status - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_MASK) #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_MASK (0x1000U) #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_SHIFT (12U) /*! SYS_TCM_ECC_ERRM_INT - System TCM Access Multibit ECC Error Interrupt Status - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_MASK) #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_MASK (0x2000U) #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_SHIFT (13U) /*! SYS_TCM_ECC_ERRS_INT - System TCM Access Single-Bit ECC Error Interrupt Status - * 0b0..No error * 0b0..No effect - * 0b1..Error + * 0b0..No error * 0b1..Clear the flag + * 0b1..Error */ #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_MASK) /*! @} */ @@ -653,5 +656,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TCM_ECC_MCM_H_ */ +#endif /* PERI_TCM_ECC_MCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMPSNS.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMPSNS.h index ac59b9858..de115af9f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMPSNS.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMPSNS.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMPSNS @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TMPSNS.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_TMPSNS.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TMPSNS * * CMSIS Peripheral Access Layer for TMPSNS */ -#if !defined(TMPSNS_H_) -#define TMPSNS_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TMPSNS_H_) +#define PERI_TMPSNS_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -576,8 +579,8 @@ typedef struct { /*! THR0_IF - Threshold0 Status Flag * 0b0..Event did not occur * 0b0..No effect - * 0b1..Event occurred * 0b1..Clear the flag + * 0b1..Event occurred */ #define TMPSNS_STAT0_THR0_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_THR0_IF_SHIFT)) & TMPSNS_STAT0_THR0_IF_MASK) @@ -586,8 +589,8 @@ typedef struct { /*! THR1_IF - Threshold1 Status Flag * 0b0..Event did not occur * 0b0..No effect - * 0b1..Event occurred * 0b1..Clear the flag + * 0b1..Event occurred */ #define TMPSNS_STAT0_THR1_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_THR1_IF_SHIFT)) & TMPSNS_STAT0_THR1_IF_MASK) @@ -596,8 +599,8 @@ typedef struct { /*! THR2_IF - Threshold2 Status Flag * 0b0..Event did not occur * 0b0..No effect - * 0b1..Event occurred * 0b1..Clear the flag + * 0b1..Event occurred */ #define TMPSNS_STAT0_THR2_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_THR2_IF_SHIFT)) & TMPSNS_STAT0_THR2_IF_MASK) @@ -1221,8 +1224,8 @@ typedef struct { /*! THR4_IF - Threshold4 Status Flag * 0b0..Event did not occur * 0b0..No effect - * 0b1..Event occurred * 0b1..Clear the flag + * 0b1..Event occurred */ #define TMPSNS_STAT1_THR4_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_THR4_IF_SHIFT)) & TMPSNS_STAT1_THR4_IF_MASK) @@ -1231,8 +1234,8 @@ typedef struct { /*! THR5_IF - Threshold5 Status Flag * 0b0..Event did not occur * 0b0..No effect - * 0b1..Event occurred * 0b1..Clear the flag + * 0b1..Event occurred */ #define TMPSNS_STAT1_THR5_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_THR5_IF_SHIFT)) & TMPSNS_STAT1_THR5_IF_MASK) @@ -1698,5 +1701,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TMPSNS_H_ */ +#endif /* PERI_TMPSNS_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR.h index e06d805ad..61bf57f03 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TMR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_TMR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TMR * * CMSIS Peripheral Access Layer for TMR */ -#if !defined(TMR_H_) -#define TMR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TMR_H_) +#define PERI_TMR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -739,5 +742,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TMR_H_ */ +#endif /* PERI_TMR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR_GLOBAL.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR_GLOBAL.h index 1703a0a8e..12c55dbc9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR_GLOBAL.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR_GLOBAL.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMR_GLOBAL @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TMR_GLOBAL.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_TMR_GLOBAL.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TMR_GLOBAL * * CMSIS Peripheral Access Layer for TMR_GLOBAL */ -#if !defined(TMR_GLOBAL_H_) -#define TMR_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TMR_GLOBAL_H_) +#define PERI_TMR_GLOBAL_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -750,5 +753,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TMR_GLOBAL_H_ */ +#endif /* PERI_TMR_GLOBAL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR_PCI_HDR_TYPE0.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR_PCI_HDR_TYPE0.h index 10cfc4539..ceb9416b2 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR_PCI_HDR_TYPE0.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TMR_PCI_HDR_TYPE0.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMR_PCI_HDR_TYPE0 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TMR_PCI_HDR_TYPE0.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_TMR_PCI_HDR_TYPE0.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TMR_PCI_HDR_TYPE0 * * CMSIS Peripheral Access Layer for TMR_PCI_HDR_TYPE0 */ -#if !defined(TMR_PCI_HDR_TYPE0_H_) -#define TMR_PCI_HDR_TYPE0_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TMR_PCI_HDR_TYPE0_H_) +#define PERI_TMR_PCI_HDR_TYPE0_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -963,5 +966,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TMR_PCI_HDR_TYPE0_H_ */ +#endif /* PERI_TMR_PCI_HDR_TYPE0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TPM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TPM.h index b8a20a140..cf255132e 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TPM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TPM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TPM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TPM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_TPM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TPM * * CMSIS Peripheral Access Layer for TPM */ -#if !defined(TPM_H_) -#define TPM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TPM_H_) +#define PERI_TPM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -790,5 +793,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TPM_H_ */ +#endif /* PERI_TPM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP1.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP1.h index 675427797..cf6f5ff4f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP1.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP1.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC_MGR_WKUP1 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TRDC_MGR_WKUP1.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_TRDC_MGR_WKUP1.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TRDC_MGR_WKUP1 * * CMSIS Peripheral Access Layer for TRDC_MGR_WKUP1 */ -#if !defined(TRDC_MGR_WKUP1_H_) -#define TRDC_MGR_WKUP1_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TRDC_MGR_WKUP1_H_) +#define PERI_TRDC_MGR_WKUP1_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -17997,5 +18000,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TRDC_MGR_WKUP1_H_ */ +#endif /* PERI_TRDC_MGR_WKUP1_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP2.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP2.h index 1f9e2d9a7..328fc36c4 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP2.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TRDC_MGR_WKUP2.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC_MGR_WKUP2 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TRDC_MGR_WKUP2.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_TRDC_MGR_WKUP2.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TRDC_MGR_WKUP2 * * CMSIS Peripheral Access Layer for TRDC_MGR_WKUP2 */ -#if !defined(TRDC_MGR_WKUP2_H_) -#define TRDC_MGR_WKUP2_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TRDC_MGR_WKUP2_H_) +#define PERI_TRDC_MGR_WKUP2_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -3753,5 +3756,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TRDC_MGR_WKUP2_H_ */ +#endif /* PERI_TRDC_MGR_WKUP2_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TSTMR.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TSTMR.h index b1a89b508..904d66437 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TSTMR.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_TSTMR.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TSTMR @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file TSTMR.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_TSTMR.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for TSTMR * * CMSIS Peripheral Access Layer for TSTMR */ -#if !defined(TSTMR_H_) -#define TSTMR_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_TSTMR_H_) +#define PERI_TSTMR_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -295,5 +298,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* TSTMR_H_ */ +#endif /* PERI_TSTMR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB.h index b3aa7fa27..a8a9d2e64 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file USB.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_USB.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for USB * * CMSIS Peripheral Access Layer for USB */ -#if !defined(USB_H_) -#define USB_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_USB_H_) +#define PERI_USB_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -749,8 +752,8 @@ typedef struct { /*! UI - USB Interrupt (USBINT) Flag * 0b0..Interrupt did not occur * 0b0..No effect - * 0b1..Interrupt occurred * 0b1..Clear the flag + * 0b1..Interrupt occurred */ #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) @@ -759,18 +762,18 @@ typedef struct { /*! UEI - USB Error Interrupt (USBERRINT) Flag * 0b0..Interrupt did not occur * 0b0..No effect - * 0b1..Interrupt occurred * 0b1..Clear the flag + * 0b1..Interrupt occurred */ #define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) #define USB_USBSTS_PCI_MASK (0x4U) #define USB_USBSTS_PCI_SHIFT (2U) /*! PCI - Port Change Detect Flag - * 0b0..Port change not detected * 0b0..No effect - * 0b1..Port change detected + * 0b0..Port change not detected * 0b1..Clear the flag + * 0b1..Port change detected */ #define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) @@ -779,8 +782,8 @@ typedef struct { /*! FRI - Frame List Rollover Flag * 0b0..Frame list index did not roll over * 0b0..No effect - * 0b1..Frame list index rolled over * 0b1..Clear the flag + * 0b1..Frame list index rolled over */ #define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) @@ -789,8 +792,8 @@ typedef struct { /*! SEI - System Error Flag * 0b0..Error response did not occur * 0b0..No effect - * 0b1..Error response occurred * 0b1..Clear the flag + * 0b1..Error response occurred */ #define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) @@ -799,28 +802,28 @@ typedef struct { /*! AAI - Interrupt on Async Advance Flag * 0b0..Interrupt did not occur * 0b0..No effect - * 0b1..Interrupt occurred * 0b1..Clear the flag + * 0b1..Interrupt occurred */ #define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) #define USB_USBSTS_URI_MASK (0x40U) #define USB_USBSTS_URI_SHIFT (6U) /*! URI - USB Reset Received Flag - * 0b0..USB reset not received * 0b0..No effect - * 0b1..USB reset received + * 0b0..USB reset not received * 0b1..Clear the flag + * 0b1..USB reset received */ #define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) #define USB_USBSTS_SRI_MASK (0x80U) #define USB_USBSTS_SRI_SHIFT (7U) /*! SRI - SOF Received Flag - * 0b0..SOF not received * 0b0..No effect - * 0b1..SOF received + * 0b0..SOF not received * 0b1..Clear the flag + * 0b1..SOF received */ #define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) @@ -829,8 +832,8 @@ typedef struct { /*! SLI - Device Controller Suspend Flag * 0b0..Did not enter Suspended state * 0b0..No effect - * 0b1..Entered Suspended state * 0b1..Clear the flag + * 0b1..Entered Suspended state */ #define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) @@ -839,8 +842,8 @@ typedef struct { /*! ULPII - ULPI Interrupt Flag * 0b0..Event completion did not occur * 0b0..No effect - * 0b1..Event completion occurred * 0b1..Clear the flag + * 0b1..Event completion occurred */ #define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) @@ -883,8 +886,8 @@ typedef struct { /*! UAI - USB Host Asynchronous Interrupt Flag * 0b0..Interrupt did not occur * 0b0..No effect - * 0b1..Interrupt occurred * 0b1..Clear the flag + * 0b1..Interrupt occurred */ #define USB_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UAI_SHIFT)) & USB_USBSTS_UAI_MASK) @@ -893,8 +896,8 @@ typedef struct { /*! UPI - USB Host Periodic Interrupt Flag * 0b0..Interrupt did not occur * 0b0..No effect - * 0b1..Interrupt occurred * 0b1..Clear the flag + * 0b1..Interrupt occurred */ #define USB_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UPI_SHIFT)) & USB_USBSTS_UPI_MASK) @@ -903,8 +906,8 @@ typedef struct { /*! TI0 - General Purpose Timer Interrupt 0 (GPTINT0) Flag * 0b0..Interrupt did not occur * 0b0..No effect - * 0b1..Interrupt occurred * 0b1..Clear the flag + * 0b1..Interrupt occurred */ #define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) @@ -913,8 +916,8 @@ typedef struct { /*! TI1 - General Purpose Timer Interrupt 1 (GPTINT1) Flag * 0b0..Interrupt did not occur * 0b0..No effect - * 0b1..Interrupt occurred * 0b1..Clear the flag + * 0b1..Interrupt occurred */ #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) /*! @} */ @@ -1135,8 +1138,8 @@ typedef struct { /*! EPRN - RX Endpoint NAK Flag * 0b00000000..No NACK * 0b00000000..No effect - * 0b00000001..NACK * 0b00000001..Clear the flag + * 0b00000001..NACK */ #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) @@ -1145,8 +1148,8 @@ typedef struct { /*! EPTN - TX Endpoint NAK Flag * 0b00000000..No NACK * 0b00000000..No effect - * 0b00000001..NACK * 0b00000001..Clear the flag + * 0b00000001..NACK */ #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) /*! @} */ @@ -1466,8 +1469,8 @@ typedef struct { /*! AVVIS - A VBUS Valid Interrupt Status Flag * 0b0..No change * 0b0..No effect - * 0b1..Risen above or fallen below the threshold * 0b1..Clear the flag + * 0b1..Risen above or fallen below the threshold */ #define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) @@ -1476,8 +1479,8 @@ typedef struct { /*! ASVIS - A Session Valid Interrupt Status Flag * 0b0..No change * 0b0..No effect - * 0b1..Risen above or fallen below the threshold * 0b1..Clear the flag + * 0b1..Risen above or fallen below the threshold */ #define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) @@ -1486,8 +1489,8 @@ typedef struct { /*! BSVIS - B Session Valid Interrupt Status Flag * 0b0..No change * 0b0..No effect - * 0b1..Risen above or fallen below the threshold * 0b1..Clear the flag + * 0b1..Risen above or fallen below the threshold */ #define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) @@ -1496,8 +1499,8 @@ typedef struct { /*! BSEIS - B Session End Interrupt Status Flag * 0b0..No change * 0b0..No effect - * 0b1..Fallen below the threshold * 0b1..Clear the flag + * 0b1..Fallen below the threshold */ #define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) @@ -1511,8 +1514,8 @@ typedef struct { /*! DPIS - Data Pulse Interrupt Status Flag * 0b0..Data pulse did not occur * 0b0..No effect - * 0b1..Data pulse occurred * 0b1..Clear the flag + * 0b1..Data pulse occurred */ #define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) @@ -1596,10 +1599,10 @@ typedef struct { #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) /*! ENDPTSETUPSTAT - Endpoint Setup Status Flag - * 0b0000000000000000..Not received * 0b0000000000000000..No effect - * 0b0000000000000001..Received + * 0b0000000000000000..Not received * 0b0000000000000001..Clear the flag + * 0b0000000000000001..Received */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) /*! @} */ @@ -1652,20 +1655,20 @@ typedef struct { #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) /*! ERCE - Endpoint Receive Complete Event Flag - * 0b00000000..Receive did not complete * 0b00000000..No effect - * 0b00000001..Receive completed + * 0b00000000..Receive did not complete * 0b00000001..Clear the flag + * 0b00000001..Receive completed */ #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) /*! ETCE - Endpoint Transmit Complete Event Flag - * 0b00000000..Transmit did not complete * 0b00000000..No effect - * 0b00000001..Transmit completed + * 0b00000000..Transmit did not complete * 0b00000001..Clear the flag + * 0b00000001..Transmit completed */ #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) /*! @} */ @@ -2436,5 +2439,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* USB_H_ */ +#endif /* PERI_USB_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB3_GLUE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB3_GLUE.h index 71cd03247..0a500d1da 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB3_GLUE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB3_GLUE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB3_GLUE @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file USB3_GLUE.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_USB3_GLUE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for USB3_GLUE * * CMSIS Peripheral Access Layer for USB3_GLUE */ -#if !defined(USB3_GLUE_H_) -#define USB3_GLUE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_USB3_GLUE_H_) +#define PERI_USB3_GLUE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -1429,5 +1432,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* USB3_GLUE_H_ */ +#endif /* PERI_USB3_GLUE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB3_PHY_TCA.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB3_PHY_TCA.h index d9bf726ee..2a0044190 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB3_PHY_TCA.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USB3_PHY_TCA.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB3_PHY_TCA @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file USB3_PHY_TCA.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_USB3_PHY_TCA.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for USB3_PHY_TCA * * CMSIS Peripheral Access Layer for USB3_PHY_TCA */ -#if !defined(USB3_PHY_TCA_H_) -#define USB3_PHY_TCA_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_USB3_PHY_TCA_H_) +#define PERI_USB3_PHY_TCA_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -744,5 +747,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* USB3_PHY_TCA_H_ */ +#endif /* PERI_USB3_PHY_TCA_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USBNC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USBNC.h index 36a17408c..26b58a1bc 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USBNC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_USBNC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBNC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file USBNC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_USBNC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for USBNC * * CMSIS Peripheral Access Layer for USBNC */ -#if !defined(USBNC_H_) -#define USBNC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_USBNC_H_) +#define PERI_USBNC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -568,5 +571,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* USBNC_H_ */ +#endif /* PERI_USBNC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_ATU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_ATU.h index 140fb6d7c..dbf01a2f6 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_ATU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_ATU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_ATU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_ATU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WAKEUP_ATU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_ATU * * CMSIS Peripheral Access Layer for WAKEUP_ATU */ -#if !defined(WAKEUP_ATU_H_) -#define WAKEUP_ATU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_ATU_H_) +#define PERI_WAKEUP_ATU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -806,5 +809,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_ATU_H_ */ +#endif /* PERI_WAKEUP_ATU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_CMU.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_CMU.h index a7cbee5e3..0dedb44c5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_CMU.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_CMU.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_CMU @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_CMU.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WAKEUP_CMU.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_CMU * * CMSIS Peripheral Access Layer for WAKEUP_CMU */ -#if !defined(WAKEUP_CMU_H_) -#define WAKEUP_CMU_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_CMU_H_) +#define PERI_WAKEUP_CMU_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -365,5 +368,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_CMU_H_ */ +#endif /* PERI_WAKEUP_CMU_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_DMA_CRC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_DMA_CRC.h index 99f54fc93..bef1d12a1 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_DMA_CRC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_DMA_CRC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_DMA_CRC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_DMA_CRC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WAKEUP_DMA_CRC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_DMA_CRC * * CMSIS Peripheral Access Layer for WAKEUP_DMA_CRC */ -#if !defined(WAKEUP_DMA_CRC_H_) -#define WAKEUP_DMA_CRC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_DMA_CRC_H_) +#define PERI_WAKEUP_DMA_CRC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -405,5 +408,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_DMA_CRC_H_ */ +#endif /* PERI_WAKEUP_DMA_CRC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_EIM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_EIM.h index 231b181e3..b5a5d6ee5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_EIM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_EIM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_EIM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_EIM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WAKEUP_EIM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_EIM * * CMSIS Peripheral Access Layer for WAKEUP_EIM */ -#if !defined(WAKEUP_EIM_H_) -#define WAKEUP_EIM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_EIM_H_) +#define PERI_WAKEUP_EIM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -502,5 +505,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_EIM_H_ */ +#endif /* PERI_WAKEUP_EIM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_ERM.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_ERM.h index 17ea6fc62..93f224d02 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_ERM.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_ERM.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_ERM @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_ERM.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WAKEUP_ERM.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_ERM * * CMSIS Peripheral Access Layer for WAKEUP_ERM */ -#if !defined(WAKEUP_ERM_H_) -#define WAKEUP_ERM_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_ERM_H_) +#define PERI_WAKEUP_ERM_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -419,5 +422,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_ERM_H_ */ +#endif /* PERI_WAKEUP_ERM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_TCW.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_TCW.h index 3f585530d..3bbb7451c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_TCW.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_TCW.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_TCW @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_TCW.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WAKEUP_TCW.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_TCW * * CMSIS Peripheral Access Layer for WAKEUP_TCW */ -#if !defined(WAKEUP_TCW_H_) -#define WAKEUP_TCW_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_TCW_H_) +#define PERI_WAKEUP_TCW_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -555,5 +558,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_TCW_H_ */ +#endif /* PERI_WAKEUP_TCW_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_TRDC_MGR_MEGA.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_TRDC_MGR_MEGA.h index dac32c166..a5ba0f37f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_TRDC_MGR_MEGA.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_TRDC_MGR_MEGA.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_TRDC_MGR_MEGA @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_TRDC_MGR_MEGA.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WAKEUP_TRDC_MGR_MEGA.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_TRDC_MGR_MEGA * * CMSIS Peripheral Access Layer for WAKEUP_TRDC_MGR_MEGA */ -#if !defined(WAKEUP_TRDC_MGR_MEGA_H_) -#define WAKEUP_TRDC_MGR_MEGA_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_TRDC_MGR_MEGA_H_) +#define PERI_WAKEUP_TRDC_MGR_MEGA_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -5257,5 +5260,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_TRDC_MGR_MEGA_H_ */ +#endif /* PERI_WAKEUP_TRDC_MGR_MEGA_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_USDHC.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_USDHC.h index 693604e60..e141fba2f 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_USDHC.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_USDHC.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_USDHC @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_USDHC.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WAKEUP_USDHC.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_USDHC * * CMSIS Peripheral Access Layer for WAKEUP_USDHC */ -#if !defined(WAKEUP_USDHC_H_) -#define WAKEUP_USDHC_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_USDHC_H_) +#define PERI_WAKEUP_USDHC_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -2558,5 +2561,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_USDHC_H_ */ +#endif /* PERI_WAKEUP_USDHC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_XSPI_RESPONDER.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_XSPI_RESPONDER.h index 79d5c63d8..c2ed3f406 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_XSPI_RESPONDER.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WAKEUP_XSPI_RESPONDER.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKEUP_XSPI_RESPONDER @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WAKEUP_XSPI_RESPONDER.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WAKEUP_XSPI_RESPONDER.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WAKEUP_XSPI_RESPONDER * * CMSIS Peripheral Access Layer for WAKEUP_XSPI_RESPONDER */ -#if !defined(WAKEUP_XSPI_RESPONDER_H_) -#define WAKEUP_XSPI_RESPONDER_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WAKEUP_XSPI_RESPONDER_H_) +#define PERI_WAKEUP_XSPI_RESPONDER_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -787,5 +790,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WAKEUP_XSPI_RESPONDER_H_ */ +#endif /* PERI_WAKEUP_XSPI_RESPONDER_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WDOG.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WDOG.h index a80d8e8e7..11536df28 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WDOG.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_WDOG.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for WDOG @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file WDOG.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_WDOG.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for WDOG * * CMSIS Peripheral Access Layer for WDOG */ -#if !defined(WDOG_H_) -#define WDOG_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_WDOG_H_) +#define PERI_WDOG_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -441,5 +444,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* WDOG_H_ */ +#endif /* PERI_WDOG_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR1.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR1.h index c912de943..451af4813 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR1.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR1.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBAR1 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file XBAR1.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_XBAR1.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for XBAR1 * * CMSIS Peripheral Access Layer for XBAR1 */ -#if !defined(XBAR1_H_) -#define XBAR1_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_XBAR1_H_) +#define PERI_XBAR1_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -187,1101 +190,6 @@ #error "No valid CPU defined!" #endif -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -#if !defined(XBAR_INPUT_SIGNAL_T_) -#define XBAR_INPUT_SIGNAL_T_ -typedef enum _xbar_input_signal -{ - kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ - kXBAR1_InputLogicHigh = 1|0x10000U, /**< LOGIC_HIGH output assigned to XBAR1_IN1 input. */ - kXBAR1_InputLogicLow1 = 2|0x10000U, /**< LOGIC_LOW1 output assigned to XBAR1_IN2 input. */ - kXBAR1_InputLogicHigh1 = 3|0x10000U, /**< LOGIC_HIGH1 output assigned to XBAR1_IN3 input. */ - kXBAR1_InputIomuxXbarIn04 = 4|0x10000U, /**< IOMUX_XBAR_IN04 output assigned to XBAR1_IN4 input. */ - kXBAR1_InputIomuxXbarIn05 = 5|0x10000U, /**< IOMUX_XBAR_IN05 output assigned to XBAR1_IN5 input. */ - kXBAR1_InputIomuxXbarIn06 = 6|0x10000U, /**< IOMUX_XBAR_IN06 output assigned to XBAR1_IN6 input. */ - kXBAR1_InputIomuxXbarIn07 = 7|0x10000U, /**< IOMUX_XBAR_IN07 output assigned to XBAR1_IN7 input. */ - kXBAR1_InputIomuxXbarIn08 = 8|0x10000U, /**< IOMUX_XBAR_IN08 output assigned to XBAR1_IN8 input. */ - kXBAR1_InputIomuxXbarIn09 = 9|0x10000U, /**< IOMUX_XBAR_IN09 output assigned to XBAR1_IN9 input. */ - kXBAR1_InputIomuxXbarIn10 = 10|0x10000U, /**< IOMUX_XBAR_IN10 output assigned to XBAR1_IN10 input. */ - kXBAR1_InputIomuxXbarIn11 = 11|0x10000U, /**< IOMUX_XBAR_IN11 output assigned to XBAR1_IN11 input. */ - kXBAR1_InputIomuxXbarIn12 = 12|0x10000U, /**< IOMUX_XBAR_IN12 output assigned to XBAR1_IN12 input. */ - kXBAR1_InputIomuxXbarIn13 = 13|0x10000U, /**< IOMUX_XBAR_IN13 output assigned to XBAR1_IN13 input. */ - kXBAR1_InputIomuxXbarIn14 = 14|0x10000U, /**< IOMUX_XBAR_IN14 output assigned to XBAR1_IN14 input. */ - kXBAR1_InputIomuxXbarIn15 = 15|0x10000U, /**< IOMUX_XBAR_IN15 output assigned to XBAR1_IN15 input. */ - kXBAR1_InputIomuxXbarIn16 = 16|0x10000U, /**< IOMUX_XBAR_IN16 output assigned to XBAR1_IN16 input. */ - kXBAR1_InputIomuxXbarIn17 = 17|0x10000U, /**< IOMUX_XBAR_IN17 output assigned to XBAR1_IN17 input. */ - kXBAR1_InputIomuxXbarIn18 = 18|0x10000U, /**< IOMUX_XBAR_IN18 output assigned to XBAR1_IN18 input. */ - kXBAR1_InputIomuxXbarIn19 = 19|0x10000U, /**< IOMUX_XBAR_IN19 output assigned to XBAR1_IN19 input. */ - kXBAR1_InputIomuxXbarIn20 = 20|0x10000U, /**< IOMUX_XBAR_IN20 output assigned to XBAR1_IN20 input. */ - kXBAR1_InputIomuxXbarIn21 = 21|0x10000U, /**< IOMUX_XBAR_IN21 output assigned to XBAR1_IN21 input. */ - kXBAR1_InputIomuxXbarIn22 = 22|0x10000U, /**< IOMUX_XBAR_IN22 output assigned to XBAR1_IN22 input. */ - kXBAR1_InputIomuxXbarIn23 = 23|0x10000U, /**< IOMUX_XBAR_IN23 output assigned to XBAR1_IN23 input. */ - kXBAR1_InputIomuxXbarIn24 = 24|0x10000U, /**< IOMUX_XBAR_IN24 output assigned to XBAR1_IN24 input. */ - kXBAR1_InputIomuxXbarIn25 = 25|0x10000U, /**< IOMUX_XBAR_IN25 output assigned to XBAR1_IN25 input. */ - kXBAR1_InputIomuxXbarIn26 = 26|0x10000U, /**< IOMUX_XBAR_IN26 output assigned to XBAR1_IN26 input. */ - kXBAR1_InputIomuxXbarIn27 = 27|0x10000U, /**< IOMUX_XBAR_IN27 output assigned to XBAR1_IN27 input. */ - kXBAR1_InputIomuxXbarIn28 = 28|0x10000U, /**< IOMUX_XBAR_IN28 output assigned to XBAR1_IN28 input. */ - kXBAR1_InputIomuxXbarIn29 = 29|0x10000U, /**< IOMUX_XBAR_IN29 output assigned to XBAR1_IN29 input. */ - kXBAR1_InputIomuxXbarIn30 = 30|0x10000U, /**< IOMUX_XBAR_IN30 output assigned to XBAR1_IN30 input. */ - kXBAR1_InputIomuxXbarIn31 = 31|0x10000U, /**< IOMUX_XBAR_IN31 output assigned to XBAR1_IN31 input. */ - kXBAR1_InputIomuxXbarIn32 = 32|0x10000U, /**< IOMUX_XBAR_IN32 output assigned to XBAR1_IN32 input. */ - kXBAR1_InputIomuxXbarIn33 = 33|0x10000U, /**< IOMUX_XBAR_IN33 output assigned to XBAR1_IN33 input. */ - kXBAR1_InputIomuxXbarIn34 = 34|0x10000U, /**< IOMUX_XBAR_IN34 output assigned to XBAR1_IN34 input. */ - kXBAR1_InputIomuxXbarIn35 = 35|0x10000U, /**< IOMUX_XBAR_IN35 output assigned to XBAR1_IN35 input. */ - kXBAR1_InputIomuxXbarIn36 = 36|0x10000U, /**< IOMUX_XBAR_IN36 output assigned to XBAR1_IN36 input. */ - kXBAR1_InputIomuxXbarIn37 = 37|0x10000U, /**< IOMUX_XBAR_IN37 output assigned to XBAR1_IN37 input. */ - kXBAR1_InputIomuxXbarIn38 = 38|0x10000U, /**< IOMUX_XBAR_IN38 output assigned to XBAR1_IN38 input. */ - kXBAR1_InputIomuxXbarIn39 = 39|0x10000U, /**< IOMUX_XBAR_IN39 output assigned to XBAR1_IN39 input. */ - kXBAR1_InputIomuxXbarIn40 = 40|0x10000U, /**< IOMUX_XBAR_IN40 output assigned to XBAR1_IN40 input. */ - kXBAR1_InputIomuxXbarIn41 = 41|0x10000U, /**< IOMUX_XBAR_IN41 output assigned to XBAR1_IN41 input. */ - kXBAR1_InputIomuxXbarIn42 = 42|0x10000U, /**< IOMUX_XBAR_IN42 output assigned to XBAR1_IN42 input. */ - kXBAR1_InputIomuxXbarIn43 = 43|0x10000U, /**< IOMUX_XBAR_IN43 output assigned to XBAR1_IN43 input. */ - kXBAR1_InputIomuxXbarIn44 = 44|0x10000U, /**< IOMUX_XBAR_IN44 output assigned to XBAR1_IN44 input. */ - kXBAR1_InputIomuxXbarIn45 = 45|0x10000U, /**< IOMUX_XBAR_IN45 output assigned to XBAR1_IN45 input. */ - kXBAR1_InputIomuxXbarIn46 = 46|0x10000U, /**< IOMUX_XBAR_IN46 output assigned to XBAR1_IN46 input. */ - kXBAR1_InputIomuxXbarIn47 = 47|0x10000U, /**< IOMUX_XBAR_IN47 output assigned to XBAR1_IN47 input. */ - kXBAR1_InputIomuxXbarIn48 = 48|0x10000U, /**< IOMUX_XBAR_IN48 output assigned to XBAR1_IN48 input. */ - kXBAR1_InputQtimer1Timer0 = 49|0x10000U, /**< QTIMER1_TIMER0 output assigned to XBAR1_IN49 input. */ - kXBAR1_InputQtimer1Timer1 = 50|0x10000U, /**< QTIMER1_TIMER1 output assigned to XBAR1_IN50 input. */ - kXBAR1_InputQtimer1Timer2 = 51|0x10000U, /**< QTIMER1_TIMER2 output assigned to XBAR1_IN51 input. */ - kXBAR1_InputQtimer1Timer3 = 52|0x10000U, /**< QTIMER1_TIMER3 output assigned to XBAR1_IN52 input. */ - kXBAR1_InputQtimer2Timer0 = 53|0x10000U, /**< QTIMER2_TIMER0 output assigned to XBAR1_IN53 input. */ - kXBAR1_InputQtimer2Timer1 = 54|0x10000U, /**< QTIMER2_TIMER1 output assigned to XBAR1_IN54 input. */ - kXBAR1_InputQtimer2Timer2 = 55|0x10000U, /**< QTIMER2_TIMER2 output assigned to XBAR1_IN55 input. */ - kXBAR1_InputQtimer2Timer3 = 56|0x10000U, /**< QTIMER2_TIMER3 output assigned to XBAR1_IN56 input. */ - kXBAR1_InputQtimer3Timer0 = 57|0x10000U, /**< QTIMER3_TIMER0 output assigned to XBAR1_IN57 input. */ - kXBAR1_InputQtimer3Timer1 = 58|0x10000U, /**< QTIMER3_TIMER1 output assigned to XBAR1_IN58 input. */ - kXBAR1_InputQtimer3Timer2 = 59|0x10000U, /**< QTIMER3_TIMER2 output assigned to XBAR1_IN59 input. */ - kXBAR1_InputQtimer3Timer3 = 60|0x10000U, /**< QTIMER3_TIMER3 output assigned to XBAR1_IN60 input. */ - kXBAR1_InputQtimer4Timer0 = 61|0x10000U, /**< QTIMER4_TIMER0 output assigned to XBAR1_IN61 input. */ - kXBAR1_InputQtimer4Timer1 = 62|0x10000U, /**< QTIMER4_TIMER1 output assigned to XBAR1_IN62 input. */ - kXBAR1_InputQtimer4Timer2 = 63|0x10000U, /**< QTIMER4_TIMER2 output assigned to XBAR1_IN63 input. */ - kXBAR1_InputQtimer4Timer3 = 64|0x10000U, /**< QTIMER4_TIMER3 output assigned to XBAR1_IN64 input. */ - kXBAR1_InputQtimer5Timer0 = 65|0x10000U, /**< QTIMER5_TIMER0 output assigned to XBAR1_IN65 input. */ - kXBAR1_InputQtimer5Timer1 = 66|0x10000U, /**< QTIMER5_TIMER1 output assigned to XBAR1_IN66 input. */ - kXBAR1_InputQtimer5Timer2 = 67|0x10000U, /**< QTIMER5_TIMER2 output assigned to XBAR1_IN67 input. */ - kXBAR1_InputQtimer5Timer3 = 68|0x10000U, /**< QTIMER5_TIMER3 output assigned to XBAR1_IN68 input. */ - kXBAR1_InputQtimer6Timer0 = 69|0x10000U, /**< QTIMER6_TIMER0 output assigned to XBAR1_IN69 input. */ - kXBAR1_InputQtimer6Timer1 = 70|0x10000U, /**< QTIMER6_TIMER1 output assigned to XBAR1_IN70 input. */ - kXBAR1_InputQtimer6Timer2 = 71|0x10000U, /**< QTIMER6_TIMER2 output assigned to XBAR1_IN71 input. */ - kXBAR1_InputQtimer6Timer3 = 72|0x10000U, /**< QTIMER6_TIMER3 output assigned to XBAR1_IN72 input. */ - kXBAR1_InputQtimer7Timer0 = 73|0x10000U, /**< QTIMER7_TIMER0 output assigned to XBAR1_IN73 input. */ - kXBAR1_InputQtimer7Timer1 = 74|0x10000U, /**< QTIMER7_TIMER1 output assigned to XBAR1_IN74 input. */ - kXBAR1_InputQtimer7Timer2 = 75|0x10000U, /**< QTIMER7_TIMER2 output assigned to XBAR1_IN75 input. */ - kXBAR1_InputQtimer7Timer3 = 76|0x10000U, /**< QTIMER7_TIMER3 output assigned to XBAR1_IN76 input. */ - kXBAR1_InputQtimer8Timer0 = 77|0x10000U, /**< QTIMER8_TIMER0 output assigned to XBAR1_IN77 input. */ - kXBAR1_InputQtimer8Timer1 = 78|0x10000U, /**< QTIMER8_TIMER1 output assigned to XBAR1_IN78 input. */ - kXBAR1_InputQtimer8Timer2 = 79|0x10000U, /**< QTIMER8_TIMER2 output assigned to XBAR1_IN79 input. */ - kXBAR1_InputQtimer8Timer3 = 80|0x10000U, /**< QTIMER8_TIMER3 output assigned to XBAR1_IN80 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger0 = 81|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR1_IN81 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger0 = 82|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER0 output assigned to XBAR1_IN82 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger1 = 83|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR1_IN83 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger1 = 84|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER1 output assigned to XBAR1_IN84 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger2 = 85|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR1_IN85 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger2 = 86|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER2 output assigned to XBAR1_IN86 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger3 = 87|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR1_IN87 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger3 = 88|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER3 output assigned to XBAR1_IN88 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger0 = 89|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR1_IN89 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger0 = 90|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER0 output assigned to XBAR1_IN90 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger1 = 91|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR1_IN91 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger1 = 92|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER1 output assigned to XBAR1_IN92 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger2 = 93|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR1_IN93 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger2 = 94|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER2 output assigned to XBAR1_IN94 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger3 = 95|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR1_IN95 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger3 = 96|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER3 output assigned to XBAR1_IN96 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger0 = 97|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR1_IN97 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger0 = 98|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER0 output assigned to XBAR1_IN98 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger1 = 99|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR1_IN99 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger1 = 100|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER1 output assigned to XBAR1_IN100 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger2 = 101|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR1_IN101 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger2 = 102|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER2 output assigned to XBAR1_IN102 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger3 = 103|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR1_IN103 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger3 = 104|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER3 output assigned to XBAR1_IN104 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger0 = 105|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR1_IN105 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger0 = 106|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER0 output assigned to XBAR1_IN106 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger1 = 107|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR1_IN107 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger1 = 108|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER1 output assigned to XBAR1_IN108 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger2 = 109|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR1_IN109 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger2 = 110|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER2 output assigned to XBAR1_IN110 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger3 = 111|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR1_IN111 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger3 = 112|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER3 output assigned to XBAR1_IN112 input. */ - kXBAR1_InputLpit1LpitTrigOut0 = 113|0x10000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR1_IN113 input. */ - kXBAR1_InputLpit1LpitTrigOut1 = 114|0x10000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR1_IN114 input. */ - kXBAR1_InputLpit1LpitTrigOut2 = 115|0x10000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR1_IN115 input. */ - kXBAR1_InputLpit1LpitTrigOut3 = 116|0x10000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR1_IN116 input. */ - kXBAR1_InputLpit2LpitTrigOut0 = 117|0x10000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR1_IN117 input. */ - kXBAR1_InputLpit2LpitTrigOut1 = 118|0x10000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR1_IN118 input. */ - kXBAR1_InputLpit2LpitTrigOut2 = 119|0x10000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR1_IN119 input. */ - kXBAR1_InputLpit2LpitTrigOut3 = 120|0x10000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR1_IN120 input. */ - kXBAR1_InputLpit3LpitTrigOut0 = 121|0x10000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR1_IN121 input. */ - kXBAR1_InputLpit3LpitTrigOut1 = 122|0x10000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR1_IN122 input. */ - kXBAR1_InputLpit3LpitTrigOut2 = 123|0x10000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR1_IN123 input. */ - kXBAR1_InputLpit3LpitTrigOut3 = 124|0x10000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR1_IN124 input. */ - kXBAR1_InputTriggerSyncSyncOut0 = 125|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT0 output assigned to XBAR1_IN125 input. */ - kXBAR1_InputTriggerSyncSyncOut1 = 126|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT1 output assigned to XBAR1_IN126 input. */ - kXBAR1_InputTriggerSyncSyncOut2 = 127|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT2 output assigned to XBAR1_IN127 input. */ - kXBAR1_InputTriggerSyncSyncOut3 = 128|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT3 output assigned to XBAR1_IN128 input. */ - kXBAR1_InputEdma2DmaTriggerOut0 = 129|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN129 input. */ - kXBAR1_InputEdma2DmaTriggerOut1 = 130|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN130 input. */ - kXBAR1_InputEdma2DmaTriggerOut2 = 131|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN131 input. */ - kXBAR1_InputEdma2DmaTriggerOut3 = 132|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN132 input. */ - kXBAR1_InputEdma2DmaTriggerOut4 = 133|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN133 input. */ - kXBAR1_InputEdma2DmaTriggerOut5 = 134|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN134 input. */ - kXBAR1_InputEdma2DmaTriggerOut6 = 135|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN135 input. */ - kXBAR1_InputEdma2DmaTriggerOut7 = 136|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN136 input. */ - kXBAR1_InputEdma1DmaTriggerOut0 = 137|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN137 input. */ - kXBAR1_InputEdma1DmaTriggerOut1 = 138|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN138 input. */ - kXBAR1_InputEdma1DmaTriggerOut2 = 139|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN139 input. */ - kXBAR1_InputEdma1DmaTriggerOut3 = 140|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN140 input. */ - kXBAR1_InputEdma1DmaTriggerOut4 = 141|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN141 input. */ - kXBAR1_InputEdma1DmaTriggerOut5 = 142|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN142 input. */ - kXBAR1_InputEdma1DmaTriggerOut6 = 143|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN143 input. */ - kXBAR1_InputEdma1DmaTriggerOut7 = 144|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN144 input. */ - kXBAR1_InputEdma3DmaTriggerOut0 = 145|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN145 input. */ - kXBAR1_InputEdma3DmaTriggerOut1 = 146|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN146 input. */ - kXBAR1_InputEdma3DmaTriggerOut2 = 147|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN147 input. */ - kXBAR1_InputEdma3DmaTriggerOut3 = 148|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN148 input. */ - kXBAR1_InputEdma3DmaTriggerOut4 = 149|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN149 input. */ - kXBAR1_InputEdma3DmaTriggerOut5 = 150|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN150 input. */ - kXBAR1_InputEdma3DmaTriggerOut6 = 151|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN151 input. */ - kXBAR1_InputEdma3DmaTriggerOut7 = 152|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN152 input. */ - kXBAR1_InputEdma4DmaTriggerOut0 = 153|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN153 input. */ - kXBAR1_InputEdma4DmaTriggerOut1 = 154|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN154 input. */ - kXBAR1_InputEdma4DmaTriggerOut2 = 155|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN155 input. */ - kXBAR1_InputEdma4DmaTriggerOut3 = 156|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN156 input. */ - kXBAR1_InputEdma4DmaTriggerOut4 = 157|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN157 input. */ - kXBAR1_InputEdma4DmaTriggerOut5 = 158|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN158 input. */ - kXBAR1_InputEdma4DmaTriggerOut6 = 159|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN159 input. */ - kXBAR1_InputEdma4DmaTriggerOut7 = 160|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN160 input. */ - kXBAR1_InputAdc1IpiIntEoc = 161|0x10000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR1_IN161 input. */ - kXBAR1_InputAdc1IpiIntWd = 162|0x10000U, /**< ADC1_IPI_INT_WD output assigned to XBAR1_IN162 input. */ - kXBAR1_InputTpm1LptpmChTrigger0 = 163|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN163 input. */ - kXBAR1_InputTpm1LptpmChTrigger1 = 164|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN164 input. */ - kXBAR1_InputTpm1LptpmChTrigger2 = 165|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN165 input. */ - kXBAR1_InputTpm1LptpmChTrigger3 = 166|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN166 input. */ - kXBAR1_InputTpm1LptpmTrigger = 167|0x10000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR1_IN167 input. */ - kXBAR1_InputTpm2LptpmChTrigger0 = 168|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN168 input. */ - kXBAR1_InputTpm2LptpmChTrigger1 = 169|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN169 input. */ - kXBAR1_InputTpm2LptpmChTrigger2 = 170|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN170 input. */ - kXBAR1_InputTpm2LptpmChTrigger3 = 171|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN171 input. */ - kXBAR1_InputTpm2LptpmTrigger = 172|0x10000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR1_IN172 input. */ - kXBAR1_InputTpm3LptpmChTrigger0 = 173|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN173 input. */ - kXBAR1_InputTpm3LptpmChTrigger1 = 174|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN174 input. */ - kXBAR1_InputTpm3LptpmChTrigger2 = 175|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN175 input. */ - kXBAR1_InputTpm3LptpmChTrigger3 = 176|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN176 input. */ - kXBAR1_InputTpm3LptpmTrigger = 177|0x10000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR1_IN177 input. */ - kXBAR1_InputTpm4LptpmChTrigger0 = 178|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN178 input. */ - kXBAR1_InputTpm4LptpmChTrigger1 = 179|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN179 input. */ - kXBAR1_InputTpm4LptpmChTrigger2 = 180|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN180 input. */ - kXBAR1_InputTpm4LptpmChTrigger3 = 181|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN181 input. */ - kXBAR1_InputTpm4LptpmTrigger = 182|0x10000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR1_IN182 input. */ - kXBAR1_InputTpm5LptpmChTrigger0 = 183|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN183 input. */ - kXBAR1_InputTpm5LptpmChTrigger1 = 184|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN184 input. */ - kXBAR1_InputTpm5LptpmChTrigger2 = 185|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN185 input. */ - kXBAR1_InputTpm5LptpmChTrigger3 = 186|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN186 input. */ - kXBAR1_InputTpm5LptpmTrigger = 187|0x10000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR1_IN187 input. */ - kXBAR1_InputTpm6LptpmChTrigger0 = 188|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN188 input. */ - kXBAR1_InputTpm6LptpmChTrigger1 = 189|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN189 input. */ - kXBAR1_InputTpm6LptpmChTrigger2 = 190|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN190 input. */ - kXBAR1_InputTpm6LptpmChTrigger3 = 191|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN191 input. */ - kXBAR1_InputTpm6LptpmTrigger = 192|0x10000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR1_IN192 input. */ - kXBAR1_InputLptmr1LptimerTriggerDelay = 193|0x10000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN193 input. */ - kXBAR1_InputLptmr2LptimerTriggerDelay = 194|0x10000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN194 input. */ - kXBAR1_InputLogicLow2 = 195|0x10000U, /**< LOGIC_LOW2 output assigned to XBAR1_IN195 input. */ - kXBAR1_InputNetcTmr11588Pp1 = 196|0x10000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR1_IN196 input. */ - kXBAR1_InputNetcTmr11588Pp2 = 197|0x10000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR1_IN197 input. */ - kXBAR1_InputNetcTmr11588Pp3 = 198|0x10000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR1_IN198 input. */ - kXBAR1_InputNetcTmr11588Alarm1 = 199|0x10000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR1_IN199 input. */ - kXBAR1_InputNetcTmr11588Alarm2 = 200|0x10000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR1_IN200 input. */ - kXBAR1_InputNetcTmr21588Pp1 = 201|0x10000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR1_IN201 input. */ - kXBAR1_InputNetcTmr21588Pp2 = 202|0x10000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR1_IN202 input. */ - kXBAR1_InputNetcTmr21588Pp3 = 203|0x10000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR1_IN203 input. */ - kXBAR1_InputNetcTmr21588Alarm1 = 204|0x10000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR1_IN204 input. */ - kXBAR1_InputNetcTmr21588Alarm2 = 205|0x10000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR1_IN205 input. */ - kXBAR1_InputNetcTmr31588Pp1 = 206|0x10000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR1_IN206 input. */ - kXBAR1_InputNetcTmr31588Pp2 = 207|0x10000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR1_IN207 input. */ - kXBAR1_InputNetcTmr31588Pp3 = 208|0x10000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR1_IN208 input. */ - kXBAR1_InputNetcTmr31588Alarm1 = 209|0x10000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR1_IN209 input. */ - kXBAR1_InputNetcTmr31588Alarm2 = 210|0x10000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR1_IN210 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak0 = 211|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR1_IN211 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak1 = 212|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR1_IN212 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak2 = 213|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR1_IN213 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak3 = 214|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR1_IN214 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak0 = 215|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR1_IN215 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak1 = 216|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR1_IN216 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak2 = 217|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR1_IN217 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak3 = 218|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR1_IN218 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak0 = 219|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR1_IN219 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak1 = 220|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR1_IN220 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak2 = 221|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR1_IN221 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak3 = 222|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR1_IN222 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak0 = 223|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR1_IN223 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak1 = 224|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR1_IN224 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak2 = 225|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR1_IN225 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak3 = 226|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR1_IN226 input. */ - kXBAR1_InputAoi1AoiOut0 = 227|0x10000U, /**< AOI1_AOI_OUT0 output assigned to XBAR1_IN227 input. */ - kXBAR1_InputAoi1AoiOut1 = 228|0x10000U, /**< AOI1_AOI_OUT1 output assigned to XBAR1_IN228 input. */ - kXBAR1_InputAoi1AoiOut2 = 229|0x10000U, /**< AOI1_AOI_OUT2 output assigned to XBAR1_IN229 input. */ - kXBAR1_InputAoi1AoiOut3 = 230|0x10000U, /**< AOI1_AOI_OUT3 output assigned to XBAR1_IN230 input. */ - kXBAR1_InputAoi2AoiOut0 = 231|0x10000U, /**< AOI2_AOI_OUT0 output assigned to XBAR1_IN231 input. */ - kXBAR1_InputAoi2AoiOut1 = 232|0x10000U, /**< AOI2_AOI_OUT1 output assigned to XBAR1_IN232 input. */ - kXBAR1_InputAoi2AoiOut2 = 233|0x10000U, /**< AOI2_AOI_OUT2 output assigned to XBAR1_IN233 input. */ - kXBAR1_InputAoi2AoiOut3 = 234|0x10000U, /**< AOI2_AOI_OUT3 output assigned to XBAR1_IN234 input. */ - kXBAR1_InputTriggerSyncSyncOut4 = 235|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT4 output assigned to XBAR1_IN235 input. */ - kXBAR1_InputTriggerSyncSyncOut5 = 236|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT5 output assigned to XBAR1_IN236 input. */ - kXBAR1_InputTriggerSyncSyncOut6 = 237|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT6 output assigned to XBAR1_IN237 input. */ - kXBAR1_InputTriggerSyncSyncOut7 = 238|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT7 output assigned to XBAR1_IN238 input. */ - kXBAR1_InputAoi3AoiOut0 = 239|0x10000U, /**< AOI3_AOI_OUT0 output assigned to XBAR1_IN239 input. */ - kXBAR1_InputAoi3AoiOut1 = 240|0x10000U, /**< AOI3_AOI_OUT1 output assigned to XBAR1_IN240 input. */ - kXBAR1_InputAoi3AoiOut2 = 241|0x10000U, /**< AOI3_AOI_OUT2 output assigned to XBAR1_IN241 input. */ - kXBAR1_InputAoi3AoiOut3 = 242|0x10000U, /**< AOI3_AOI_OUT3 output assigned to XBAR1_IN242 input. */ - kXBAR1_InputAoi4AoiOut0 = 243|0x10000U, /**< AOI4_AOI_OUT0 output assigned to XBAR1_IN243 input. */ - kXBAR1_InputAoi4AoiOut1 = 244|0x10000U, /**< AOI4_AOI_OUT1 output assigned to XBAR1_IN244 input. */ - kXBAR1_InputAoi4AoiOut2 = 245|0x10000U, /**< AOI4_AOI_OUT2 output assigned to XBAR1_IN245 input. */ - kXBAR1_InputAoi4AoiOut3 = 246|0x10000U, /**< AOI4_AOI_OUT3 output assigned to XBAR1_IN246 input. */ - kXBAR1_InputEcatSyncOut0 = 247|0x10000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR1_IN247 input. */ - kXBAR1_InputEcatSyncOut1 = 248|0x10000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR1_IN248 input. */ - kXBAR1_InputFccuVfccuReactionsOut11 = 249|0x10000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR1_IN249 input. */ - kXBAR1_InputGpt1IppDoCmpout1 = 250|0x10000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR1_IN250 input. */ - kXBAR1_InputGpt1IppDoCmpout2 = 251|0x10000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR1_IN251 input. */ - kXBAR1_InputGpt1IppDoCmpout3 = 252|0x10000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR1_IN252 input. */ - kXBAR1_InputGpt2IppDoCmpout1 = 253|0x10000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR1_IN253 input. */ - kXBAR1_InputGpt2IppDoCmpout2 = 254|0x10000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR1_IN254 input. */ - kXBAR1_InputGpt2IppDoCmpout3 = 255|0x10000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR1_IN255 input. */ - kXBAR1_InputGpt3IppDoCmpout1 = 256|0x10000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR1_IN256 input. */ - kXBAR1_InputGpt3IppDoCmpout2 = 257|0x10000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR1_IN257 input. */ - kXBAR1_InputGpt3IppDoCmpout3 = 258|0x10000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR1_IN258 input. */ - kXBAR1_InputGpt4IppDoCmpout1 = 259|0x10000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR1_IN259 input. */ - kXBAR1_InputGpt4IppDoCmpout2 = 260|0x10000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR1_IN260 input. */ - kXBAR1_InputGpt4IppDoCmpout3 = 261|0x10000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR1_IN261 input. */ - kXBAR1_InputFlexio1FlexioTriggerOut0 = 262|0x10000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN262 input. */ - kXBAR1_InputFlexio2FlexioTriggerOut0 = 263|0x10000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN263 input. */ - kXBAR1_InputFlexio3FlexioTriggerOut0 = 264|0x10000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN264 input. */ - kXBAR1_InputFlexio4FlexioTriggerOut0 = 265|0x10000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN265 input. */ - kXBAR1_InputGpio1IpiIntRgpio0 = 266|0x10000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR1_IN266 input. */ - kXBAR1_InputGpio2IpiIntRgpio0 = 267|0x10000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR1_IN267 input. */ - kXBAR1_InputGpio3IpiIntRgpio0 = 268|0x10000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR1_IN268 input. */ - kXBAR1_InputGpio4IpiIntRgpio0 = 269|0x10000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR1_IN269 input. */ - kXBAR1_InputGpio5IpiIntRgpio0 = 270|0x10000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR1_IN270 input. */ - kXBAR1_InputGpio6IpiIntRgpio0 = 271|0x10000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR1_IN271 input. */ - kXBAR1_InputGpio7IpiIntRgpio0 = 272|0x10000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR1_IN272 input. */ - kXBAR1_InputCm33Txev = 273|0x10000U, /**< CM33_TXEV output assigned to XBAR1_IN273 input. */ - kXBAR1_InputCm33SyncTxev = 274|0x10000U, /**< CM33_SYNC_TXEV output assigned to XBAR1_IN274 input. */ - kXBAR1_InputEndat21SiN = 275|0x10000U, /**< ENDAT2_1_SI_N output assigned to XBAR1_IN275 input. */ - kXBAR1_InputEndat21TimerN = 276|0x10000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR1_IN276 input. */ - kXBAR1_InputEndat22SiN = 277|0x10000U, /**< ENDAT2_2_SI_N output assigned to XBAR1_IN277 input. */ - kXBAR1_InputEndat22TimerN = 278|0x10000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR1_IN278 input. */ - kXBAR1_InputBissEot = 279|0x10000U, /**< BISS_EOT output assigned to XBAR1_IN279 input. */ - kXBAR1_InputTriggerSyncSyncOut8 = 280|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT8 output assigned to XBAR1_IN280 input. */ - kXBAR1_InputTriggerSyncSyncOut9 = 281|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT9 output assigned to XBAR1_IN281 input. */ - kXBAR1_InputTriggerSyncSyncOut10 = 282|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT10 output assigned to XBAR1_IN282 input. */ - kXBAR1_InputTriggerSyncSyncOut11 = 283|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT11 output assigned to XBAR1_IN283 input. */ - kXBAR1_InputTriggerSyncSyncOut12 = 284|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT12 output assigned to XBAR1_IN284 input. */ - kXBAR1_InputTriggerSyncSyncOut13 = 285|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT13 output assigned to XBAR1_IN285 input. */ - kXBAR1_InputTriggerSyncSyncOut14 = 286|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT14 output assigned to XBAR1_IN286 input. */ - kXBAR1_InputTriggerSyncSyncOut15 = 287|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT15 output assigned to XBAR1_IN287 input. */ - kXBAR1_InputEcatResetOut = 288|0x10000U, /**< ECAT_RESET_OUT output assigned to XBAR1_IN288 input. */ - kXBAR1_InputHiperface1FastPosRcvdEvt = 289|0x10000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR1_IN289 input. */ - kXBAR1_InputHiperface2FastPosRcvdEvt = 290|0x10000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR1_IN290 input. */ - kXBAR2_InputLogicLow = 0|0x20000U, /**< LOGIC_LOW output assigned to XBAR2_IN0 input. */ - kXBAR2_InputLogicHigh = 1|0x20000U, /**< LOGIC_HIGH output assigned to XBAR2_IN1 input. */ - kXBAR2_InputLogicLow1 = 2|0x20000U, /**< LOGIC_LOW1 output assigned to XBAR2_IN2 input. */ - kXBAR2_InputLogicHigh1 = 3|0x20000U, /**< LOGIC_HIGH1 output assigned to XBAR2_IN3 input. */ - kXBAR2_InputQtimer1Timer0 = 4|0x20000U, /**< QTIMER1_TIMER0 output assigned to XBAR2_IN4 input. */ - kXBAR2_InputQtimer1Timer1 = 5|0x20000U, /**< QTIMER1_TIMER1 output assigned to XBAR2_IN5 input. */ - kXBAR2_InputQtimer1Timer2 = 6|0x20000U, /**< QTIMER1_TIMER2 output assigned to XBAR2_IN6 input. */ - kXBAR2_InputQtimer1Timer3 = 7|0x20000U, /**< QTIMER1_TIMER3 output assigned to XBAR2_IN7 input. */ - kXBAR2_InputQtimer2Timer0 = 8|0x20000U, /**< QTIMER2_TIMER0 output assigned to XBAR2_IN8 input. */ - kXBAR2_InputQtimer2Timer1 = 9|0x20000U, /**< QTIMER2_TIMER1 output assigned to XBAR2_IN9 input. */ - kXBAR2_InputQtimer2Timer2 = 10|0x20000U, /**< QTIMER2_TIMER2 output assigned to XBAR2_IN10 input. */ - kXBAR2_InputQtimer2Timer3 = 11|0x20000U, /**< QTIMER2_TIMER3 output assigned to XBAR2_IN11 input. */ - kXBAR2_InputQtimer3Timer0 = 12|0x20000U, /**< QTIMER3_TIMER0 output assigned to XBAR2_IN12 input. */ - kXBAR2_InputQtimer3Timer1 = 13|0x20000U, /**< QTIMER3_TIMER1 output assigned to XBAR2_IN13 input. */ - kXBAR2_InputQtimer3Timer2 = 14|0x20000U, /**< QTIMER3_TIMER2 output assigned to XBAR2_IN14 input. */ - kXBAR2_InputQtimer3Timer3 = 15|0x20000U, /**< QTIMER3_TIMER3 output assigned to XBAR2_IN15 input. */ - kXBAR2_InputQtimer4Timer0 = 16|0x20000U, /**< QTIMER4_TIMER0 output assigned to XBAR2_IN16 input. */ - kXBAR2_InputQtimer4Timer1 = 17|0x20000U, /**< QTIMER4_TIMER1 output assigned to XBAR2_IN17 input. */ - kXBAR2_InputQtimer4Timer2 = 18|0x20000U, /**< QTIMER4_TIMER2 output assigned to XBAR2_IN18 input. */ - kXBAR2_InputQtimer4Timer3 = 19|0x20000U, /**< QTIMER4_TIMER3 output assigned to XBAR2_IN19 input. */ - kXBAR2_InputQtimer5Timer0 = 20|0x20000U, /**< QTIMER5_TIMER0 output assigned to XBAR2_IN20 input. */ - kXBAR2_InputQtimer5Timer1 = 21|0x20000U, /**< QTIMER5_TIMER1 output assigned to XBAR2_IN21 input. */ - kXBAR2_InputQtimer5Timer2 = 22|0x20000U, /**< QTIMER5_TIMER2 output assigned to XBAR2_IN22 input. */ - kXBAR2_InputQtimer5Timer3 = 23|0x20000U, /**< QTIMER5_TIMER3 output assigned to XBAR2_IN23 input. */ - kXBAR2_InputQtimer6Timer0 = 24|0x20000U, /**< QTIMER6_TIMER0 output assigned to XBAR2_IN24 input. */ - kXBAR2_InputQtimer6Timer1 = 25|0x20000U, /**< QTIMER6_TIMER1 output assigned to XBAR2_IN25 input. */ - kXBAR2_InputQtimer6Timer2 = 26|0x20000U, /**< QTIMER6_TIMER2 output assigned to XBAR2_IN26 input. */ - kXBAR2_InputQtimer6Timer3 = 27|0x20000U, /**< QTIMER6_TIMER3 output assigned to XBAR2_IN27 input. */ - kXBAR2_InputQtimer7Timer0 = 28|0x20000U, /**< QTIMER7_TIMER0 output assigned to XBAR2_IN28 input. */ - kXBAR2_InputQtimer7Timer1 = 29|0x20000U, /**< QTIMER7_TIMER1 output assigned to XBAR2_IN29 input. */ - kXBAR2_InputQtimer7Timer2 = 30|0x20000U, /**< QTIMER7_TIMER2 output assigned to XBAR2_IN30 input. */ - kXBAR2_InputQtimer7Timer3 = 31|0x20000U, /**< QTIMER7_TIMER3 output assigned to XBAR2_IN31 input. */ - kXBAR2_InputQtimer8Timer0 = 32|0x20000U, /**< QTIMER8_TIMER0 output assigned to XBAR2_IN32 input. */ - kXBAR2_InputQtimer8Timer1 = 33|0x20000U, /**< QTIMER8_TIMER1 output assigned to XBAR2_IN33 input. */ - kXBAR2_InputQtimer8Timer2 = 34|0x20000U, /**< QTIMER8_TIMER2 output assigned to XBAR2_IN34 input. */ - kXBAR2_InputQtimer8Timer3 = 35|0x20000U, /**< QTIMER8_TIMER3 output assigned to XBAR2_IN35 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger0 = 36|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR2_IN36 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger1 = 37|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR2_IN37 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger2 = 38|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR2_IN38 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger3 = 39|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR2_IN39 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger0 = 40|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR2_IN40 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger1 = 41|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR2_IN41 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger2 = 42|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR2_IN42 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger3 = 43|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR2_IN43 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger0 = 44|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR2_IN44 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger1 = 45|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR2_IN45 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger2 = 46|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR2_IN46 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger3 = 47|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR2_IN47 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger0 = 48|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR2_IN48 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger1 = 49|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR2_IN49 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger2 = 50|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR2_IN50 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger3 = 51|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR2_IN51 input. */ - kXBAR2_InputLpit1LpitTrigOut0 = 52|0x20000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR2_IN52 input. */ - kXBAR2_InputLpit1LpitTrigOut1 = 53|0x20000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR2_IN53 input. */ - kXBAR2_InputLpit1LpitTrigOut2 = 54|0x20000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR2_IN54 input. */ - kXBAR2_InputLpit1LpitTrigOut3 = 55|0x20000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR2_IN55 input. */ - kXBAR2_InputLpit2LpitTrigOut0 = 56|0x20000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR2_IN56 input. */ - kXBAR2_InputLpit2LpitTrigOut1 = 57|0x20000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR2_IN57 input. */ - kXBAR2_InputLpit2LpitTrigOut2 = 58|0x20000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR2_IN58 input. */ - kXBAR2_InputLpit2LpitTrigOut3 = 59|0x20000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR2_IN59 input. */ - kXBAR2_InputLpit3LpitTrigOut0 = 60|0x20000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR2_IN60 input. */ - kXBAR2_InputLpit3LpitTrigOut1 = 61|0x20000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR2_IN61 input. */ - kXBAR2_InputLpit3LpitTrigOut2 = 62|0x20000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR2_IN62 input. */ - kXBAR2_InputLpit3LpitTrigOut3 = 63|0x20000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR2_IN63 input. */ - kXBAR2_InputEdma2DmaTriggerOut0 = 64|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN64 input. */ - kXBAR2_InputEdma2DmaTriggerOut1 = 65|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN65 input. */ - kXBAR2_InputEdma2DmaTriggerOut2 = 66|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN66 input. */ - kXBAR2_InputEdma2DmaTriggerOut3 = 67|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN67 input. */ - kXBAR2_InputEdma2DmaTriggerOut4 = 68|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN68 input. */ - kXBAR2_InputEdma2DmaTriggerOut5 = 69|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN69 input. */ - kXBAR2_InputEdma2DmaTriggerOut6 = 70|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN70 input. */ - kXBAR2_InputEdma2DmaTriggerOut7 = 71|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN71 input. */ - kXBAR2_InputEdma1DmaTriggerOut0 = 72|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN72 input. */ - kXBAR2_InputEdma1DmaTriggerOut1 = 73|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN73 input. */ - kXBAR2_InputEdma1DmaTriggerOut2 = 74|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN74 input. */ - kXBAR2_InputEdma1DmaTriggerOut3 = 75|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN75 input. */ - kXBAR2_InputEdma1DmaTriggerOut4 = 76|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN76 input. */ - kXBAR2_InputEdma1DmaTriggerOut5 = 77|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN77 input. */ - kXBAR2_InputEdma1DmaTriggerOut6 = 78|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN78 input. */ - kXBAR2_InputEdma1DmaTriggerOut7 = 79|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN79 input. */ - kXBAR2_InputEdma3DmaTriggerOut0 = 80|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN80 input. */ - kXBAR2_InputEdma3DmaTriggerOut1 = 81|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN81 input. */ - kXBAR2_InputEdma3DmaTriggerOut2 = 82|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN82 input. */ - kXBAR2_InputEdma3DmaTriggerOut3 = 83|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN83 input. */ - kXBAR2_InputEdma3DmaTriggerOut4 = 84|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN84 input. */ - kXBAR2_InputEdma3DmaTriggerOut5 = 85|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN85 input. */ - kXBAR2_InputEdma3DmaTriggerOut6 = 86|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN86 input. */ - kXBAR2_InputEdma3DmaTriggerOut7 = 87|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN87 input. */ - kXBAR2_InputEdma4DmaTriggerOut0 = 88|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN88 input. */ - kXBAR2_InputEdma4DmaTriggerOut1 = 89|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN89 input. */ - kXBAR2_InputEdma4DmaTriggerOut2 = 90|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN90 input. */ - kXBAR2_InputEdma4DmaTriggerOut3 = 91|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN91 input. */ - kXBAR2_InputEdma4DmaTriggerOut4 = 92|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN92 input. */ - kXBAR2_InputEdma4DmaTriggerOut5 = 93|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN93 input. */ - kXBAR2_InputEdma4DmaTriggerOut6 = 94|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN94 input. */ - kXBAR2_InputEdma4DmaTriggerOut7 = 95|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN95 input. */ - kXBAR2_InputAdc1IpiIntEoc = 96|0x20000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR2_IN96 input. */ - kXBAR2_InputAdc1IpiIntWd = 97|0x20000U, /**< ADC1_IPI_INT_WD output assigned to XBAR2_IN97 input. */ - kXBAR2_InputTpm1LptpmChTrigger0 = 98|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN98 input. */ - kXBAR2_InputTpm1LptpmChTrigger1 = 99|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN99 input. */ - kXBAR2_InputTpm1LptpmChTrigger2 = 100|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN100 input. */ - kXBAR2_InputTpm1LptpmChTrigger3 = 101|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN101 input. */ - kXBAR2_InputTpm1LptpmTrigger = 102|0x20000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR2_IN102 input. */ - kXBAR2_InputTpm2LptpmChTrigger0 = 103|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN103 input. */ - kXBAR2_InputTpm2LptpmChTrigger1 = 104|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN104 input. */ - kXBAR2_InputTpm2LptpmChTrigger2 = 105|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN105 input. */ - kXBAR2_InputTpm2LptpmChTrigger3 = 106|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN106 input. */ - kXBAR2_InputTpm2LptpmTrigger = 107|0x20000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR2_IN107 input. */ - kXBAR2_InputTpm3LptpmChTrigger0 = 108|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN108 input. */ - kXBAR2_InputTpm3LptpmChTrigger1 = 109|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN109 input. */ - kXBAR2_InputTpm3LptpmChTrigger2 = 110|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN110 input. */ - kXBAR2_InputTpm3LptpmChTrigger3 = 111|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN111 input. */ - kXBAR2_InputTpm3LptpmTrigger = 112|0x20000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR2_IN112 input. */ - kXBAR2_InputTpm4LptpmChTrigger0 = 113|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN113 input. */ - kXBAR2_InputTpm4LptpmChTrigger1 = 114|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN114 input. */ - kXBAR2_InputTpm4LptpmChTrigger2 = 115|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN115 input. */ - kXBAR2_InputTpm4LptpmChTrigger3 = 116|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN116 input. */ - kXBAR2_InputTpm4LptpmTrigger = 117|0x20000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR2_IN117 input. */ - kXBAR2_InputTpm5LptpmChTrigger0 = 118|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN118 input. */ - kXBAR2_InputTpm5LptpmChTrigger1 = 119|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN119 input. */ - kXBAR2_InputTpm5LptpmChTrigger2 = 120|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN120 input. */ - kXBAR2_InputTpm5LptpmChTrigger3 = 121|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN121 input. */ - kXBAR2_InputTpm5LptpmTrigger = 122|0x20000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR2_IN122 input. */ - kXBAR2_InputTpm6LptpmChTrigger0 = 123|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN123 input. */ - kXBAR2_InputTpm6LptpmChTrigger1 = 124|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN124 input. */ - kXBAR2_InputTpm6LptpmChTrigger2 = 125|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN125 input. */ - kXBAR2_InputTpm6LptpmChTrigger3 = 126|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN126 input. */ - kXBAR2_InputTpm6LptpmTrigger = 127|0x20000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR2_IN127 input. */ - kXBAR2_InputLptmr1LptimerTriggerDelay = 128|0x20000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN128 input. */ - kXBAR2_InputLptmr2LptimerTriggerDelay = 129|0x20000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN129 input. */ - kXBAR2_InputLogicLow2 = 130|0x20000U, /**< LOGIC_LOW2 output assigned to XBAR2_IN130 input. */ - kXBAR2_InputNetcTmr11588Pp1 = 131|0x20000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR2_IN131 input. */ - kXBAR2_InputNetcTmr11588Pp2 = 132|0x20000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR2_IN132 input. */ - kXBAR2_InputNetcTmr11588Pp3 = 133|0x20000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR2_IN133 input. */ - kXBAR2_InputNetcTmr11588Alarm1 = 134|0x20000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR2_IN134 input. */ - kXBAR2_InputNetcTmr11588Alarm2 = 135|0x20000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR2_IN135 input. */ - kXBAR2_InputNetcTmr21588Pp1 = 136|0x20000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR2_IN136 input. */ - kXBAR2_InputNetcTmr21588Pp2 = 137|0x20000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR2_IN137 input. */ - kXBAR2_InputNetcTmr21588Pp3 = 138|0x20000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR2_IN138 input. */ - kXBAR2_InputNetcTmr21588Alarm1 = 139|0x20000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR2_IN139 input. */ - kXBAR2_InputNetcTmr21588Alarm2 = 140|0x20000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR2_IN140 input. */ - kXBAR2_InputNetcTmr31588Pp1 = 141|0x20000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR2_IN141 input. */ - kXBAR2_InputNetcTmr31588Pp2 = 142|0x20000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR2_IN142 input. */ - kXBAR2_InputNetcTmr31588Pp3 = 143|0x20000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR2_IN143 input. */ - kXBAR2_InputNetcTmr31588Alarm1 = 144|0x20000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR2_IN144 input. */ - kXBAR2_InputNetcTmr31588Alarm2 = 145|0x20000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR2_IN145 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak0 = 146|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR2_IN146 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak1 = 147|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR2_IN147 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak2 = 148|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR2_IN148 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak3 = 149|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR2_IN149 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak0 = 150|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR2_IN150 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak1 = 151|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR2_IN151 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak2 = 152|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR2_IN152 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak3 = 153|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR2_IN153 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak0 = 154|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR2_IN154 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak1 = 155|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR2_IN155 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak2 = 156|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR2_IN156 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak3 = 157|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR2_IN157 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak0 = 158|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR2_IN158 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak1 = 159|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR2_IN159 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak2 = 160|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR2_IN160 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak3 = 161|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR2_IN161 input. */ - kXBAR2_InputSinc1PulseTrg0 = 162|0x20000U, /**< SINC1_PULSE_TRG0 output assigned to XBAR2_IN162 input. */ - kXBAR2_InputSinc1PulseTrg1 = 163|0x20000U, /**< SINC1_PULSE_TRG1 output assigned to XBAR2_IN163 input. */ - kXBAR2_InputSinc1PulseTrg2 = 164|0x20000U, /**< SINC1_PULSE_TRG2 output assigned to XBAR2_IN164 input. */ - kXBAR2_InputSinc1PulseTrg3 = 165|0x20000U, /**< SINC1_PULSE_TRG3 output assigned to XBAR2_IN165 input. */ - kXBAR2_InputSinc3PulseTrg0 = 166|0x20000U, /**< SINC3_PULSE_TRG0 output assigned to XBAR2_IN166 input. */ - kXBAR2_InputSinc3PulseTrg1 = 167|0x20000U, /**< SINC3_PULSE_TRG1 output assigned to XBAR2_IN167 input. */ - kXBAR2_InputSinc3PulseTrg2 = 168|0x20000U, /**< SINC3_PULSE_TRG2 output assigned to XBAR2_IN168 input. */ - kXBAR2_InputSinc3PulseTrg3 = 169|0x20000U, /**< SINC3_PULSE_TRG3 output assigned to XBAR2_IN169 input. */ - kXBAR2_InputEcatSyncOut0 = 170|0x20000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR2_IN170 input. */ - kXBAR2_InputEcatSyncOut1 = 171|0x20000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR2_IN171 input. */ - kXBAR2_InputFccuVfccuReactionsOut11 = 172|0x20000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR2_IN172 input. */ - kXBAR2_InputGpt1IppDoCmpout1 = 173|0x20000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR2_IN173 input. */ - kXBAR2_InputGpt1IppDoCmpout2 = 174|0x20000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR2_IN174 input. */ - kXBAR2_InputGpt1IppDoCmpout3 = 175|0x20000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR2_IN175 input. */ - kXBAR2_InputGpt2IppDoCmpout1 = 176|0x20000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR2_IN176 input. */ - kXBAR2_InputGpt2IppDoCmpout2 = 177|0x20000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR2_IN177 input. */ - kXBAR2_InputGpt2IppDoCmpout3 = 178|0x20000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR2_IN178 input. */ - kXBAR2_InputGpt3IppDoCmpout1 = 179|0x20000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR2_IN179 input. */ - kXBAR2_InputGpt3IppDoCmpout2 = 180|0x20000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR2_IN180 input. */ - kXBAR2_InputGpt3IppDoCmpout3 = 181|0x20000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR2_IN181 input. */ - kXBAR2_InputGpt4IppDoCmpout1 = 182|0x20000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR2_IN182 input. */ - kXBAR2_InputGpt4IppDoCmpout2 = 183|0x20000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR2_IN183 input. */ - kXBAR2_InputGpt4IppDoCmpout3 = 184|0x20000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR2_IN184 input. */ - kXBAR2_InputFlexio1FlexioTriggerOut0 = 185|0x20000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN185 input. */ - kXBAR2_InputFlexio2FlexioTriggerOut0 = 186|0x20000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN186 input. */ - kXBAR2_InputFlexio3FlexioTriggerOut0 = 187|0x20000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN187 input. */ - kXBAR2_InputFlexio4FlexioTriggerOut0 = 188|0x20000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN188 input. */ - kXBAR2_InputGpio1IpiIntRgpio0 = 189|0x20000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR2_IN189 input. */ - kXBAR2_InputGpio2IpiIntRgpio0 = 190|0x20000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR2_IN190 input. */ - kXBAR2_InputGpio3IpiIntRgpio0 = 191|0x20000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR2_IN191 input. */ - kXBAR2_InputGpio4IpiIntRgpio0 = 192|0x20000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR2_IN192 input. */ - kXBAR2_InputGpio5IpiIntRgpio0 = 193|0x20000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR2_IN193 input. */ - kXBAR2_InputGpio6IpiIntRgpio0 = 194|0x20000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR2_IN194 input. */ - kXBAR2_InputGpio7IpiIntRgpio0 = 195|0x20000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR2_IN195 input. */ - kXBAR2_InputCm33Txev = 196|0x20000U, /**< CM33_TXEV output assigned to XBAR2_IN196 input. */ - kXBAR2_InputCm33SyncTxev = 197|0x20000U, /**< CM33_SYNC_TXEV output assigned to XBAR2_IN197 input. */ - kXBAR2_InputEndat21SiN = 198|0x20000U, /**< ENDAT2_1_SI_N output assigned to XBAR2_IN198 input. */ - kXBAR2_InputEndat21TimerN = 199|0x20000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR2_IN199 input. */ - kXBAR2_InputEndat22SiN = 200|0x20000U, /**< ENDAT2_2_SI_N output assigned to XBAR2_IN200 input. */ - kXBAR2_InputEndat22TimerN = 201|0x20000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR2_IN201 input. */ - kXBAR2_InputBissEot = 202|0x20000U, /**< BISS_EOT output assigned to XBAR2_IN202 input. */ - kXBAR2_InputEnc1PosMatch0 = 203|0x20000U, /**< ENC1_POS_MATCH0 output assigned to XBAR2_IN203 input. */ - kXBAR2_InputEnc1PosMatch1 = 204|0x20000U, /**< ENC1_POS_MATCH1 output assigned to XBAR2_IN204 input. */ - kXBAR2_InputEnc1PosMatch2 = 205|0x20000U, /**< ENC1_POS_MATCH2 output assigned to XBAR2_IN205 input. */ - kXBAR2_InputEnc1PosMatch3 = 206|0x20000U, /**< ENC1_POS_MATCH3 output assigned to XBAR2_IN206 input. */ - kXBAR2_InputEnc1CompFlg0 = 207|0x20000U, /**< ENC1_COMP_FLG0 output assigned to XBAR2_IN207 input. */ - kXBAR2_InputEnc1CompFlg1 = 208|0x20000U, /**< ENC1_COMP_FLG1 output assigned to XBAR2_IN208 input. */ - kXBAR2_InputEnc1CompFlg2 = 209|0x20000U, /**< ENC1_COMP_FLG2 output assigned to XBAR2_IN209 input. */ - kXBAR2_InputEnc1CompFlg3 = 210|0x20000U, /**< ENC1_COMP_FLG3 output assigned to XBAR2_IN210 input. */ - kXBAR2_InputEnc1CntDn = 211|0x20000U, /**< ENC1_CNT_DN output assigned to XBAR2_IN211 input. */ - kXBAR2_InputEnc1CntUp = 212|0x20000U, /**< ENC1_CNT_UP output assigned to XBAR2_IN212 input. */ - kXBAR2_InputEnc1Dir = 213|0x20000U, /**< ENC1_DIR output assigned to XBAR2_IN213 input. */ - kXBAR2_InputEnc3PosMatch0 = 214|0x20000U, /**< ENC3_POS_MATCH0 output assigned to XBAR2_IN214 input. */ - kXBAR2_InputEnc3PosMatch1 = 215|0x20000U, /**< ENC3_POS_MATCH1 output assigned to XBAR2_IN215 input. */ - kXBAR2_InputEnc3PosMatch2 = 216|0x20000U, /**< ENC3_POS_MATCH2 output assigned to XBAR2_IN216 input. */ - kXBAR2_InputEnc3PosMatch3 = 217|0x20000U, /**< ENC3_POS_MATCH3 output assigned to XBAR2_IN217 input. */ - kXBAR2_InputEnc3CompFlg0 = 218|0x20000U, /**< ENC3_COMP_FLG0 output assigned to XBAR2_IN218 input. */ - kXBAR2_InputEnc3CompFlg1 = 219|0x20000U, /**< ENC3_COMP_FLG1 output assigned to XBAR2_IN219 input. */ - kXBAR2_InputEnc3CompFlg2 = 220|0x20000U, /**< ENC3_COMP_FLG2 output assigned to XBAR2_IN220 input. */ - kXBAR2_InputEnc3CompFlg3 = 221|0x20000U, /**< ENC3_COMP_FLG3 output assigned to XBAR2_IN221 input. */ - kXBAR2_InputEnc3CntDn = 222|0x20000U, /**< ENC3_CNT_DN output assigned to XBAR2_IN222 input. */ - kXBAR2_InputEnc3CntUp = 223|0x20000U, /**< ENC3_CNT_UP output assigned to XBAR2_IN223 input. */ - kXBAR2_InputEnc3Dir = 224|0x20000U, /**< ENC3_DIR output assigned to XBAR2_IN224 input. */ - kXBAR2_InputHiperface1FastPosRcvdEvt = 225|0x20000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR2_IN225 input. */ - kXBAR2_InputHiperface2FastPosRcvdEvt = 226|0x20000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR2_IN226 input. */ - kXBAR3_InputLogicLow = 0|0x30000U, /**< LOGIC_LOW output assigned to XBAR3_IN0 input. */ - kXBAR3_InputLogicHigh = 1|0x30000U, /**< LOGIC_HIGH output assigned to XBAR3_IN1 input. */ - kXBAR3_InputLogicLow1 = 2|0x30000U, /**< LOGIC_LOW1 output assigned to XBAR3_IN2 input. */ - kXBAR3_InputLogicHigh1 = 3|0x30000U, /**< LOGIC_HIGH1 output assigned to XBAR3_IN3 input. */ - kXBAR3_InputQtimer1Timer0 = 4|0x30000U, /**< QTIMER1_TIMER0 output assigned to XBAR3_IN4 input. */ - kXBAR3_InputQtimer1Timer1 = 5|0x30000U, /**< QTIMER1_TIMER1 output assigned to XBAR3_IN5 input. */ - kXBAR3_InputQtimer1Timer2 = 6|0x30000U, /**< QTIMER1_TIMER2 output assigned to XBAR3_IN6 input. */ - kXBAR3_InputQtimer1Timer3 = 7|0x30000U, /**< QTIMER1_TIMER3 output assigned to XBAR3_IN7 input. */ - kXBAR3_InputQtimer2Timer0 = 8|0x30000U, /**< QTIMER2_TIMER0 output assigned to XBAR3_IN8 input. */ - kXBAR3_InputQtimer2Timer1 = 9|0x30000U, /**< QTIMER2_TIMER1 output assigned to XBAR3_IN9 input. */ - kXBAR3_InputQtimer2Timer2 = 10|0x30000U, /**< QTIMER2_TIMER2 output assigned to XBAR3_IN10 input. */ - kXBAR3_InputQtimer2Timer3 = 11|0x30000U, /**< QTIMER2_TIMER3 output assigned to XBAR3_IN11 input. */ - kXBAR3_InputQtimer3Timer0 = 12|0x30000U, /**< QTIMER3_TIMER0 output assigned to XBAR3_IN12 input. */ - kXBAR3_InputQtimer3Timer1 = 13|0x30000U, /**< QTIMER3_TIMER1 output assigned to XBAR3_IN13 input. */ - kXBAR3_InputQtimer3Timer2 = 14|0x30000U, /**< QTIMER3_TIMER2 output assigned to XBAR3_IN14 input. */ - kXBAR3_InputQtimer3Timer3 = 15|0x30000U, /**< QTIMER3_TIMER3 output assigned to XBAR3_IN15 input. */ - kXBAR3_InputQtimer4Timer0 = 16|0x30000U, /**< QTIMER4_TIMER0 output assigned to XBAR3_IN16 input. */ - kXBAR3_InputQtimer4Timer1 = 17|0x30000U, /**< QTIMER4_TIMER1 output assigned to XBAR3_IN17 input. */ - kXBAR3_InputQtimer4Timer2 = 18|0x30000U, /**< QTIMER4_TIMER2 output assigned to XBAR3_IN18 input. */ - kXBAR3_InputQtimer4Timer3 = 19|0x30000U, /**< QTIMER4_TIMER3 output assigned to XBAR3_IN19 input. */ - kXBAR3_InputQtimer5Timer0 = 20|0x30000U, /**< QTIMER5_TIMER0 output assigned to XBAR3_IN20 input. */ - kXBAR3_InputQtimer5Timer1 = 21|0x30000U, /**< QTIMER5_TIMER1 output assigned to XBAR3_IN21 input. */ - kXBAR3_InputQtimer5Timer2 = 22|0x30000U, /**< QTIMER5_TIMER2 output assigned to XBAR3_IN22 input. */ - kXBAR3_InputQtimer5Timer3 = 23|0x30000U, /**< QTIMER5_TIMER3 output assigned to XBAR3_IN23 input. */ - kXBAR3_InputQtimer6Timer0 = 24|0x30000U, /**< QTIMER6_TIMER0 output assigned to XBAR3_IN24 input. */ - kXBAR3_InputQtimer6Timer1 = 25|0x30000U, /**< QTIMER6_TIMER1 output assigned to XBAR3_IN25 input. */ - kXBAR3_InputQtimer6Timer2 = 26|0x30000U, /**< QTIMER6_TIMER2 output assigned to XBAR3_IN26 input. */ - kXBAR3_InputQtimer6Timer3 = 27|0x30000U, /**< QTIMER6_TIMER3 output assigned to XBAR3_IN27 input. */ - kXBAR3_InputQtimer7Timer0 = 28|0x30000U, /**< QTIMER7_TIMER0 output assigned to XBAR3_IN28 input. */ - kXBAR3_InputQtimer7Timer1 = 29|0x30000U, /**< QTIMER7_TIMER1 output assigned to XBAR3_IN29 input. */ - kXBAR3_InputQtimer7Timer2 = 30|0x30000U, /**< QTIMER7_TIMER2 output assigned to XBAR3_IN30 input. */ - kXBAR3_InputQtimer7Timer3 = 31|0x30000U, /**< QTIMER7_TIMER3 output assigned to XBAR3_IN31 input. */ - kXBAR3_InputQtimer8Timer0 = 32|0x30000U, /**< QTIMER8_TIMER0 output assigned to XBAR3_IN32 input. */ - kXBAR3_InputQtimer8Timer1 = 33|0x30000U, /**< QTIMER8_TIMER1 output assigned to XBAR3_IN33 input. */ - kXBAR3_InputQtimer8Timer2 = 34|0x30000U, /**< QTIMER8_TIMER2 output assigned to XBAR3_IN34 input. */ - kXBAR3_InputQtimer8Timer3 = 35|0x30000U, /**< QTIMER8_TIMER3 output assigned to XBAR3_IN35 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger0 = 36|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR3_IN36 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger1 = 37|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR3_IN37 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger2 = 38|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR3_IN38 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger3 = 39|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR3_IN39 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger0 = 40|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR3_IN40 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger1 = 41|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR3_IN41 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger2 = 42|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR3_IN42 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger3 = 43|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR3_IN43 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger0 = 44|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR3_IN44 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger1 = 45|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR3_IN45 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger2 = 46|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR3_IN46 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger3 = 47|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR3_IN47 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger0 = 48|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR3_IN48 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger1 = 49|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR3_IN49 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger2 = 50|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR3_IN50 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger3 = 51|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR3_IN51 input. */ - kXBAR3_InputLpit1LpitTrigOut0 = 52|0x30000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR3_IN52 input. */ - kXBAR3_InputLpit1LpitTrigOut1 = 53|0x30000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR3_IN53 input. */ - kXBAR3_InputLpit1LpitTrigOut2 = 54|0x30000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR3_IN54 input. */ - kXBAR3_InputLpit1LpitTrigOut3 = 55|0x30000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR3_IN55 input. */ - kXBAR3_InputLpit2LpitTrigOut0 = 56|0x30000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR3_IN56 input. */ - kXBAR3_InputLpit2LpitTrigOut1 = 57|0x30000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR3_IN57 input. */ - kXBAR3_InputLpit2LpitTrigOut2 = 58|0x30000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR3_IN58 input. */ - kXBAR3_InputLpit2LpitTrigOut3 = 59|0x30000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR3_IN59 input. */ - kXBAR3_InputLpit3LpitTrigOut0 = 60|0x30000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR3_IN60 input. */ - kXBAR3_InputLpit3LpitTrigOut1 = 61|0x30000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR3_IN61 input. */ - kXBAR3_InputLpit3LpitTrigOut2 = 62|0x30000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR3_IN62 input. */ - kXBAR3_InputLpit3LpitTrigOut3 = 63|0x30000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR3_IN63 input. */ - kXBAR3_InputEdma2DmaTriggerOut0 = 64|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN64 input. */ - kXBAR3_InputEdma2DmaTriggerOut1 = 65|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN65 input. */ - kXBAR3_InputEdma2DmaTriggerOut2 = 66|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN66 input. */ - kXBAR3_InputEdma2DmaTriggerOut3 = 67|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN67 input. */ - kXBAR3_InputEdma2DmaTriggerOut4 = 68|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN68 input. */ - kXBAR3_InputEdma2DmaTriggerOut5 = 69|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN69 input. */ - kXBAR3_InputEdma2DmaTriggerOut6 = 70|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN70 input. */ - kXBAR3_InputEdma2DmaTriggerOut7 = 71|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN71 input. */ - kXBAR3_InputEdma1DmaTriggerOut0 = 72|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN72 input. */ - kXBAR3_InputEdma1DmaTriggerOut1 = 73|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN73 input. */ - kXBAR3_InputEdma1DmaTriggerOut2 = 74|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN74 input. */ - kXBAR3_InputEdma1DmaTriggerOut3 = 75|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN75 input. */ - kXBAR3_InputEdma1DmaTriggerOut4 = 76|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN76 input. */ - kXBAR3_InputEdma1DmaTriggerOut5 = 77|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN77 input. */ - kXBAR3_InputEdma1DmaTriggerOut6 = 78|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN78 input. */ - kXBAR3_InputEdma1DmaTriggerOut7 = 79|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN79 input. */ - kXBAR3_InputEdma3DmaTriggerOut0 = 80|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN80 input. */ - kXBAR3_InputEdma3DmaTriggerOut1 = 81|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN81 input. */ - kXBAR3_InputEdma3DmaTriggerOut2 = 82|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN82 input. */ - kXBAR3_InputEdma3DmaTriggerOut3 = 83|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN83 input. */ - kXBAR3_InputEdma3DmaTriggerOut4 = 84|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN84 input. */ - kXBAR3_InputEdma3DmaTriggerOut5 = 85|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN85 input. */ - kXBAR3_InputEdma3DmaTriggerOut6 = 86|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN86 input. */ - kXBAR3_InputEdma3DmaTriggerOut7 = 87|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN87 input. */ - kXBAR3_InputEdma4DmaTriggerOut0 = 88|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN88 input. */ - kXBAR3_InputEdma4DmaTriggerOut1 = 89|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN89 input. */ - kXBAR3_InputEdma4DmaTriggerOut2 = 90|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN90 input. */ - kXBAR3_InputEdma4DmaTriggerOut3 = 91|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN91 input. */ - kXBAR3_InputEdma4DmaTriggerOut4 = 92|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN92 input. */ - kXBAR3_InputEdma4DmaTriggerOut5 = 93|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN93 input. */ - kXBAR3_InputEdma4DmaTriggerOut6 = 94|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN94 input. */ - kXBAR3_InputEdma4DmaTriggerOut7 = 95|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN95 input. */ - kXBAR3_InputAdc1IpiIntEoc = 96|0x30000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR3_IN96 input. */ - kXBAR3_InputAdc1IpiIntWd = 97|0x30000U, /**< ADC1_IPI_INT_WD output assigned to XBAR3_IN97 input. */ - kXBAR3_InputTpm1LptpmChTrigger0 = 98|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN98 input. */ - kXBAR3_InputTpm1LptpmChTrigger1 = 99|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN99 input. */ - kXBAR3_InputTpm1LptpmChTrigger2 = 100|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN100 input. */ - kXBAR3_InputTpm1LptpmChTrigger3 = 101|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN101 input. */ - kXBAR3_InputTpm1LptpmTrigger = 102|0x30000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR3_IN102 input. */ - kXBAR3_InputTpm2LptpmChTrigger0 = 103|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN103 input. */ - kXBAR3_InputTpm2LptpmChTrigger1 = 104|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN104 input. */ - kXBAR3_InputTpm2LptpmChTrigger2 = 105|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN105 input. */ - kXBAR3_InputTpm2LptpmChTrigger3 = 106|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN106 input. */ - kXBAR3_InputTpm2LptpmTrigger = 107|0x30000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR3_IN107 input. */ - kXBAR3_InputTpm3LptpmChTrigger0 = 108|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN108 input. */ - kXBAR3_InputTpm3LptpmChTrigger1 = 109|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN109 input. */ - kXBAR3_InputTpm3LptpmChTrigger2 = 110|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN110 input. */ - kXBAR3_InputTpm3LptpmChTrigger3 = 111|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN111 input. */ - kXBAR3_InputTpm3LptpmTrigger = 112|0x30000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR3_IN112 input. */ - kXBAR3_InputTpm4LptpmChTrigger0 = 113|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN113 input. */ - kXBAR3_InputTpm4LptpmChTrigger1 = 114|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN114 input. */ - kXBAR3_InputTpm4LptpmChTrigger2 = 115|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN115 input. */ - kXBAR3_InputTpm4LptpmChTrigger3 = 116|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN116 input. */ - kXBAR3_InputTpm4LptpmTrigger = 117|0x30000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR3_IN117 input. */ - kXBAR3_InputTpm5LptpmChTrigger0 = 118|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN118 input. */ - kXBAR3_InputTpm5LptpmChTrigger1 = 119|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN119 input. */ - kXBAR3_InputTpm5LptpmChTrigger2 = 120|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN120 input. */ - kXBAR3_InputTpm5LptpmChTrigger3 = 121|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN121 input. */ - kXBAR3_InputTpm5LptpmTrigger = 122|0x30000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR3_IN122 input. */ - kXBAR3_InputTpm6LptpmChTrigger0 = 123|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN123 input. */ - kXBAR3_InputTpm6LptpmChTrigger1 = 124|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN124 input. */ - kXBAR3_InputTpm6LptpmChTrigger2 = 125|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN125 input. */ - kXBAR3_InputTpm6LptpmChTrigger3 = 126|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN126 input. */ - kXBAR3_InputTpm6LptpmTrigger = 127|0x30000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR3_IN127 input. */ - kXBAR3_InputLptmr1LptimerTriggerDelay = 128|0x30000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN128 input. */ - kXBAR3_InputLptmr2LptimerTriggerDelay = 129|0x30000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN129 input. */ - kXBAR3_InputLogicLow2 = 130|0x30000U, /**< LOGIC_LOW2 output assigned to XBAR3_IN130 input. */ - kXBAR3_InputNetcTmr11588Pp1 = 131|0x30000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR3_IN131 input. */ - kXBAR3_InputNetcTmr11588Pp2 = 132|0x30000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR3_IN132 input. */ - kXBAR3_InputNetcTmr11588Pp3 = 133|0x30000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR3_IN133 input. */ - kXBAR3_InputNetcTmr11588Alarm1 = 134|0x30000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR3_IN134 input. */ - kXBAR3_InputNetcTmr11588Alarm2 = 135|0x30000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR3_IN135 input. */ - kXBAR3_InputNetcTmr21588Pp1 = 136|0x30000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR3_IN136 input. */ - kXBAR3_InputNetcTmr21588Pp2 = 137|0x30000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR3_IN137 input. */ - kXBAR3_InputNetcTmr21588Pp3 = 138|0x30000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR3_IN138 input. */ - kXBAR3_InputNetcTmr21588Alarm1 = 139|0x30000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR3_IN139 input. */ - kXBAR3_InputNetcTmr21588Alarm2 = 140|0x30000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR3_IN140 input. */ - kXBAR3_InputNetcTmr31588Pp1 = 141|0x30000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR3_IN141 input. */ - kXBAR3_InputNetcTmr31588Pp2 = 142|0x30000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR3_IN142 input. */ - kXBAR3_InputNetcTmr31588Pp3 = 143|0x30000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR3_IN143 input. */ - kXBAR3_InputNetcTmr31588Alarm1 = 144|0x30000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR3_IN144 input. */ - kXBAR3_InputNetcTmr31588Alarm2 = 145|0x30000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR3_IN145 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak0 = 146|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR3_IN146 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak1 = 147|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR3_IN147 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak2 = 148|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR3_IN148 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak3 = 149|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR3_IN149 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak0 = 150|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR3_IN150 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak1 = 151|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR3_IN151 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak2 = 152|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR3_IN152 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak3 = 153|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR3_IN153 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak0 = 154|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR3_IN154 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak1 = 155|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR3_IN155 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak2 = 156|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR3_IN156 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak3 = 157|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR3_IN157 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak0 = 158|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR3_IN158 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak1 = 159|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR3_IN159 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak2 = 160|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR3_IN160 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak3 = 161|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR3_IN161 input. */ - kXBAR3_InputSinc2PulseTrg0 = 162|0x30000U, /**< SINC2_PULSE_TRG0 output assigned to XBAR3_IN162 input. */ - kXBAR3_InputSinc2PulseTrg1 = 163|0x30000U, /**< SINC2_PULSE_TRG1 output assigned to XBAR3_IN163 input. */ - kXBAR3_InputSinc2PulseTrg2 = 164|0x30000U, /**< SINC2_PULSE_TRG2 output assigned to XBAR3_IN164 input. */ - kXBAR3_InputSinc2PulseTrg3 = 165|0x30000U, /**< SINC2_PULSE_TRG3 output assigned to XBAR3_IN165 input. */ - kXBAR3_InputSinc4PulseTrg0 = 166|0x30000U, /**< SINC4_PULSE_TRG0 output assigned to XBAR3_IN166 input. */ - kXBAR3_InputSinc4PulseTrg1 = 167|0x30000U, /**< SINC4_PULSE_TRG1 output assigned to XBAR3_IN167 input. */ - kXBAR3_InputSinc4PulseTrg2 = 168|0x30000U, /**< SINC4_PULSE_TRG2 output assigned to XBAR3_IN168 input. */ - kXBAR3_InputSinc4PulseTrg3 = 169|0x30000U, /**< SINC4_PULSE_TRG3 output assigned to XBAR3_IN169 input. */ - kXBAR3_InputEcatSyncOut0 = 170|0x30000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR3_IN170 input. */ - kXBAR3_InputEcatSyncOut1 = 171|0x30000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR3_IN171 input. */ - kXBAR3_InputFccuVfccuReactionsOut11 = 172|0x30000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR3_IN172 input. */ - kXBAR3_InputGpt1IppDoCmpout1 = 173|0x30000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR3_IN173 input. */ - kXBAR3_InputGpt1IppDoCmpout2 = 174|0x30000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR3_IN174 input. */ - kXBAR3_InputGpt1IppDoCmpout3 = 175|0x30000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR3_IN175 input. */ - kXBAR3_InputGpt2IppDoCmpout1 = 176|0x30000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR3_IN176 input. */ - kXBAR3_InputGpt2IppDoCmpout2 = 177|0x30000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR3_IN177 input. */ - kXBAR3_InputGpt2IppDoCmpout3 = 178|0x30000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR3_IN178 input. */ - kXBAR3_InputGpt3IppDoCmpout1 = 179|0x30000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR3_IN179 input. */ - kXBAR3_InputGpt3IppDoCmpout2 = 180|0x30000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR3_IN180 input. */ - kXBAR3_InputGpt3IppDoCmpout3 = 181|0x30000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR3_IN181 input. */ - kXBAR3_InputGpt4IppDoCmpout1 = 182|0x30000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR3_IN182 input. */ - kXBAR3_InputGpt4IppDoCmpout2 = 183|0x30000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR3_IN183 input. */ - kXBAR3_InputGpt4IppDoCmpout3 = 184|0x30000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR3_IN184 input. */ - kXBAR3_InputFlexio1FlexioTriggerOut0 = 185|0x30000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN185 input. */ - kXBAR3_InputFlexio2FlexioTriggerOut0 = 186|0x30000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN186 input. */ - kXBAR3_InputFlexio3FlexioTriggerOut0 = 187|0x30000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN187 input. */ - kXBAR3_InputFlexio4FlexioTriggerOut0 = 188|0x30000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN188 input. */ - kXBAR3_InputGpio1IpiIntRgpio0 = 189|0x30000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR3_IN189 input. */ - kXBAR3_InputGpio2IpiIntRgpio0 = 190|0x30000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR3_IN190 input. */ - kXBAR3_InputGpio3IpiIntRgpio0 = 191|0x30000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR3_IN191 input. */ - kXBAR3_InputGpio4IpiIntRgpio0 = 192|0x30000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR3_IN192 input. */ - kXBAR3_InputGpio5IpiIntRgpio0 = 193|0x30000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR3_IN193 input. */ - kXBAR3_InputGpio6IpiIntRgpio0 = 194|0x30000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR3_IN194 input. */ - kXBAR3_InputGpio7IpiIntRgpio0 = 195|0x30000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR3_IN195 input. */ - kXBAR3_InputCm33Txev = 196|0x30000U, /**< CM33_TXEV output assigned to XBAR3_IN196 input. */ - kXBAR3_InputCm33SyncTxev = 197|0x30000U, /**< CM33_SYNC_TXEV output assigned to XBAR3_IN197 input. */ - kXBAR3_InputEndat21SiN = 198|0x30000U, /**< ENDAT2_1_SI_N output assigned to XBAR3_IN198 input. */ - kXBAR3_InputEndat21TimerN = 199|0x30000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR3_IN199 input. */ - kXBAR3_InputEndat22SiN = 200|0x30000U, /**< ENDAT2_2_SI_N output assigned to XBAR3_IN200 input. */ - kXBAR3_InputEndat22TimerN = 201|0x30000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR3_IN201 input. */ - kXBAR3_InputBissEot = 202|0x30000U, /**< BISS_EOT output assigned to XBAR3_IN202 input. */ - kXBAR3_InputEnc2PosMatch0 = 203|0x30000U, /**< ENC2_POS_MATCH0 output assigned to XBAR3_IN203 input. */ - kXBAR3_InputEnc2PosMatch1 = 204|0x30000U, /**< ENC2_POS_MATCH1 output assigned to XBAR3_IN204 input. */ - kXBAR3_InputEnc2PosMatch2 = 205|0x30000U, /**< ENC2_POS_MATCH2 output assigned to XBAR3_IN205 input. */ - kXBAR3_InputEnc2PosMatch3 = 206|0x30000U, /**< ENC2_POS_MATCH3 output assigned to XBAR3_IN206 input. */ - kXBAR3_InputEnc2CompFlg0 = 207|0x30000U, /**< ENC2_COMP_FLG0 output assigned to XBAR3_IN207 input. */ - kXBAR3_InputEnc2CompFlg1 = 208|0x30000U, /**< ENC2_COMP_FLG1 output assigned to XBAR3_IN208 input. */ - kXBAR3_InputEnc2CompFlg2 = 209|0x30000U, /**< ENC2_COMP_FLG2 output assigned to XBAR3_IN209 input. */ - kXBAR3_InputEnc2CompFlg3 = 210|0x30000U, /**< ENC2_COMP_FLG3 output assigned to XBAR3_IN210 input. */ - kXBAR3_InputEnc2CntDn = 211|0x30000U, /**< ENC2_CNT_DN output assigned to XBAR3_IN211 input. */ - kXBAR3_InputEnc2CntUp = 212|0x30000U, /**< ENC2_CNT_UP output assigned to XBAR3_IN212 input. */ - kXBAR3_InputEnc2Dir = 213|0x30000U, /**< ENC2_DIR output assigned to XBAR3_IN213 input. */ - kXBAR3_InputEnc4PosMatch0 = 214|0x30000U, /**< ENC4_POS_MATCH0 output assigned to XBAR3_IN214 input. */ - kXBAR3_InputEnc4PosMatch1 = 215|0x30000U, /**< ENC4_POS_MATCH1 output assigned to XBAR3_IN215 input. */ - kXBAR3_InputEnc4PosMatch2 = 216|0x30000U, /**< ENC4_POS_MATCH2 output assigned to XBAR3_IN216 input. */ - kXBAR3_InputEnc4PosMatch3 = 217|0x30000U, /**< ENC4_POS_MATCH3 output assigned to XBAR3_IN217 input. */ - kXBAR3_InputEnc4CompFlg0 = 218|0x30000U, /**< ENC4_COMP_FLG0 output assigned to XBAR3_IN218 input. */ - kXBAR3_InputEnc4CompFlg1 = 219|0x30000U, /**< ENC4_COMP_FLG1 output assigned to XBAR3_IN219 input. */ - kXBAR3_InputEnc4CompFlg2 = 220|0x30000U, /**< ENC4_COMP_FLG2 output assigned to XBAR3_IN220 input. */ - kXBAR3_InputEnc4CompFlg3 = 221|0x30000U, /**< ENC4_COMP_FLG3 output assigned to XBAR3_IN221 input. */ - kXBAR3_InputEnc4CntDn = 222|0x30000U, /**< ENC4_CNT_DN output assigned to XBAR3_IN222 input. */ - kXBAR3_InputEnc4CntUp = 223|0x30000U, /**< ENC4_CNT_UP output assigned to XBAR3_IN223 input. */ - kXBAR3_InputEnc4Dir = 224|0x30000U, /**< ENC4_DIR output assigned to XBAR3_IN224 input. */ - kXBAR3_InputHiperface1FastPosRcvdEvt = 225|0x30000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR3_IN225 input. */ - kXBAR3_InputHiperface2FastPosRcvdEvt = 226|0x30000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR3_IN226 input. */ -} xbar_input_signal_t; -#endif /* XBAR_INPUT_SIGNAL_T_ */ - -#if !defined(XBAR_OUTPUT_SIGNAL_T_) -#define XBAR_OUTPUT_SIGNAL_T_ -typedef enum _xbar_output_signal -{ - kXBAR1_OutputEdma4IpdReq76 = 0|0x10000U, /**< XBAR1_OUT0 output assigned to EDMA4_IPD_REQ76 */ - kXBAR1_OutputEdma4IpdReq77 = 1|0x10000U, /**< XBAR1_OUT1 output assigned to EDMA4_IPD_REQ77 */ - kXBAR1_OutputEdma4IpdReq78 = 2|0x10000U, /**< XBAR1_OUT2 output assigned to EDMA4_IPD_REQ78 */ - kXBAR1_OutputEdma4IpdReq79 = 3|0x10000U, /**< XBAR1_OUT3 output assigned to EDMA4_IPD_REQ79 */ - kXBAR1_OutputIomuxXbarOut04 = 4|0x10000U, /**< XBAR1_OUT4 output assigned to IOMUX_XBAR_OUT04 */ - kXBAR1_OutputIomuxXbarOut05 = 5|0x10000U, /**< XBAR1_OUT5 output assigned to IOMUX_XBAR_OUT05 */ - kXBAR1_OutputIomuxXbarOut06 = 6|0x10000U, /**< XBAR1_OUT6 output assigned to IOMUX_XBAR_OUT06 */ - kXBAR1_OutputIomuxXbarOut07 = 7|0x10000U, /**< XBAR1_OUT7 output assigned to IOMUX_XBAR_OUT07 */ - kXBAR1_OutputIomuxXbarOut08 = 8|0x10000U, /**< XBAR1_OUT8 output assigned to IOMUX_XBAR_OUT08 */ - kXBAR1_OutputIomuxXbarOut09 = 9|0x10000U, /**< XBAR1_OUT9 output assigned to IOMUX_XBAR_OUT09 */ - kXBAR1_OutputIomuxXbarOut10 = 10|0x10000U, /**< XBAR1_OUT10 output assigned to IOMUX_XBAR_OUT10 */ - kXBAR1_OutputIomuxXbarOut11 = 11|0x10000U, /**< XBAR1_OUT11 output assigned to IOMUX_XBAR_OUT11 */ - kXBAR1_OutputIomuxXbarOut12 = 12|0x10000U, /**< XBAR1_OUT12 output assigned to IOMUX_XBAR_OUT12 */ - kXBAR1_OutputIomuxXbarOut13 = 13|0x10000U, /**< XBAR1_OUT13 output assigned to IOMUX_XBAR_OUT13 */ - kXBAR1_OutputIomuxXbarOut14 = 14|0x10000U, /**< XBAR1_OUT14 output assigned to IOMUX_XBAR_OUT14 */ - kXBAR1_OutputIomuxXbarOut15 = 15|0x10000U, /**< XBAR1_OUT15 output assigned to IOMUX_XBAR_OUT15 */ - kXBAR1_OutputIomuxXbarOut16 = 16|0x10000U, /**< XBAR1_OUT16 output assigned to IOMUX_XBAR_OUT16 */ - kXBAR1_OutputIomuxXbarOut17 = 17|0x10000U, /**< XBAR1_OUT17 output assigned to IOMUX_XBAR_OUT17 */ - kXBAR1_OutputIomuxXbarOut18 = 18|0x10000U, /**< XBAR1_OUT18 output assigned to IOMUX_XBAR_OUT18 */ - kXBAR1_OutputIomuxXbarOut19 = 19|0x10000U, /**< XBAR1_OUT19 output assigned to IOMUX_XBAR_OUT19 */ - kXBAR1_OutputIomuxXbarOut20 = 20|0x10000U, /**< XBAR1_OUT20 output assigned to IOMUX_XBAR_OUT20 */ - kXBAR1_OutputIomuxXbarOut21 = 21|0x10000U, /**< XBAR1_OUT21 output assigned to IOMUX_XBAR_OUT21 */ - kXBAR1_OutputIomuxXbarOut22 = 22|0x10000U, /**< XBAR1_OUT22 output assigned to IOMUX_XBAR_OUT22 */ - kXBAR1_OutputIomuxXbarOut23 = 23|0x10000U, /**< XBAR1_OUT23 output assigned to IOMUX_XBAR_OUT23 */ - kXBAR1_OutputIomuxXbarOut24 = 24|0x10000U, /**< XBAR1_OUT24 output assigned to IOMUX_XBAR_OUT24 */ - kXBAR1_OutputIomuxXbarOut25 = 25|0x10000U, /**< XBAR1_OUT25 output assigned to IOMUX_XBAR_OUT25 */ - kXBAR1_OutputIomuxXbarOut26 = 26|0x10000U, /**< XBAR1_OUT26 output assigned to IOMUX_XBAR_OUT26 */ - kXBAR1_OutputIomuxXbarOut27 = 27|0x10000U, /**< XBAR1_OUT27 output assigned to IOMUX_XBAR_OUT27 */ - kXBAR1_OutputIomuxXbarOut28 = 28|0x10000U, /**< XBAR1_OUT28 output assigned to IOMUX_XBAR_OUT28 */ - kXBAR1_OutputIomuxXbarOut29 = 29|0x10000U, /**< XBAR1_OUT29 output assigned to IOMUX_XBAR_OUT29 */ - kXBAR1_OutputIomuxXbarOut30 = 30|0x10000U, /**< XBAR1_OUT30 output assigned to IOMUX_XBAR_OUT30 */ - kXBAR1_OutputIomuxXbarOut31 = 31|0x10000U, /**< XBAR1_OUT31 output assigned to IOMUX_XBAR_OUT31 */ - kXBAR1_OutputIomuxXbarOut32 = 32|0x10000U, /**< XBAR1_OUT32 output assigned to IOMUX_XBAR_OUT32 */ - kXBAR1_OutputIomuxXbarOut33 = 33|0x10000U, /**< XBAR1_OUT33 output assigned to IOMUX_XBAR_OUT33 */ - kXBAR1_OutputIomuxXbarOut34 = 34|0x10000U, /**< XBAR1_OUT34 output assigned to IOMUX_XBAR_OUT34 */ - kXBAR1_OutputIomuxXbarOut35 = 35|0x10000U, /**< XBAR1_OUT35 output assigned to IOMUX_XBAR_OUT35 */ - kXBAR1_OutputIomuxXbarOut36 = 36|0x10000U, /**< XBAR1_OUT36 output assigned to IOMUX_XBAR_OUT36 */ - kXBAR1_OutputIomuxXbarOut37 = 37|0x10000U, /**< XBAR1_OUT37 output assigned to IOMUX_XBAR_OUT37 */ - kXBAR1_OutputIomuxXbarOut38 = 38|0x10000U, /**< XBAR1_OUT38 output assigned to IOMUX_XBAR_OUT38 */ - kXBAR1_OutputIomuxXbarOut39 = 39|0x10000U, /**< XBAR1_OUT39 output assigned to IOMUX_XBAR_OUT39 */ - kXBAR1_OutputIomuxXbarOut40 = 40|0x10000U, /**< XBAR1_OUT40 output assigned to IOMUX_XBAR_OUT40 */ - kXBAR1_OutputTriggerSyncAsyncIn0 = 41|0x10000U, /**< XBAR1_OUT41 output assigned to TRIGGER_SYNC_ASYNC_IN0 */ - kXBAR1_OutputTriggerSyncAsyncIn1 = 42|0x10000U, /**< XBAR1_OUT42 output assigned to TRIGGER_SYNC_ASYNC_IN1 */ - kXBAR1_OutputTriggerSyncAsyncIn2 = 43|0x10000U, /**< XBAR1_OUT43 output assigned to TRIGGER_SYNC_ASYNC_IN2 */ - kXBAR1_OutputTriggerSyncAsyncIn3 = 44|0x10000U, /**< XBAR1_OUT44 output assigned to TRIGGER_SYNC_ASYNC_IN3 */ - kXBAR1_OutputTriggerSyncAsyncIn4 = 45|0x10000U, /**< XBAR1_OUT45 output assigned to TRIGGER_SYNC_ASYNC_IN4 */ - kXBAR1_OutputTriggerSyncAsyncIn5 = 46|0x10000U, /**< XBAR1_OUT46 output assigned to TRIGGER_SYNC_ASYNC_IN5 */ - kXBAR1_OutputTriggerSyncAsyncIn6 = 47|0x10000U, /**< XBAR1_OUT47 output assigned to TRIGGER_SYNC_ASYNC_IN6 */ - kXBAR1_OutputTriggerSyncAsyncIn7 = 48|0x10000U, /**< XBAR1_OUT48 output assigned to TRIGGER_SYNC_ASYNC_IN7 */ - kXBAR1_OutputFlexpwm1Exta0 = 49|0x10000U, /**< XBAR1_OUT49 output assigned to FLEXPWM1_EXTA0 */ - kXBAR1_OutputFlexpwm1Exta1 = 50|0x10000U, /**< XBAR1_OUT50 output assigned to FLEXPWM1_EXTA1 */ - kXBAR1_OutputFlexpwm1Exta2 = 51|0x10000U, /**< XBAR1_OUT51 output assigned to FLEXPWM1_EXTA2 */ - kXBAR1_OutputFlexpwm1Exta3 = 52|0x10000U, /**< XBAR1_OUT52 output assigned to FLEXPWM1_EXTA3 */ - kXBAR1_OutputFlexpwm1ExtSync0 = 53|0x10000U, /**< XBAR1_OUT53 output assigned to FLEXPWM1_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm1ExtSync1 = 54|0x10000U, /**< XBAR1_OUT54 output assigned to FLEXPWM1_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm1ExtSync2 = 55|0x10000U, /**< XBAR1_OUT55 output assigned to FLEXPWM1_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm1ExtSync3 = 56|0x10000U, /**< XBAR1_OUT56 output assigned to FLEXPWM1_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm1ExtClk = 57|0x10000U, /**< XBAR1_OUT57 output assigned to FLEXPWM1_EXT_CLK */ - kXBAR1_OutputFlexpwm1IppIndFault0 = 58|0x10000U, /**< XBAR1_OUT58 output assigned to FLEXPWM1_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm1IppIndFault1 = 59|0x10000U, /**< XBAR1_OUT59 output assigned to FLEXPWM1_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm1IppIndFault2 = 60|0x10000U, /**< XBAR1_OUT60 output assigned to FLEXPWM1_IPP_IND_FAULT2 */ - kXBAR1_OutputFlexpwm1IppIndFault3 = 61|0x10000U, /**< XBAR1_OUT61 output assigned to FLEXPWM1_IPP_IND_FAULT3 */ - kXBAR1_OutputFlexpwm1ExtForce = 62|0x10000U, /**< XBAR1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */ - kXBAR1_OutputFlexpwm2Exta0 = 63|0x10000U, /**< XBAR1_OUT63 output assigned to FLEXPWM2_EXTA0 */ - kXBAR1_OutputFlexpwm2Exta1 = 64|0x10000U, /**< XBAR1_OUT64 output assigned to FLEXPWM2_EXTA1 */ - kXBAR1_OutputFlexpwm2Exta2 = 65|0x10000U, /**< XBAR1_OUT65 output assigned to FLEXPWM2_EXTA2 */ - kXBAR1_OutputFlexpwm2Exta3 = 66|0x10000U, /**< XBAR1_OUT66 output assigned to FLEXPWM2_EXTA3 */ - kXBAR1_OutputFlexpwm2ExtSync0 = 67|0x10000U, /**< XBAR1_OUT67 output assigned to FLEXPWM2_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm2ExtSync1 = 68|0x10000U, /**< XBAR1_OUT68 output assigned to FLEXPWM2_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm2ExtSync2 = 69|0x10000U, /**< XBAR1_OUT69 output assigned to FLEXPWM2_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm2ExtSync3 = 70|0x10000U, /**< XBAR1_OUT70 output assigned to FLEXPWM2_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm2ExtClk = 71|0x10000U, /**< XBAR1_OUT71 output assigned to FLEXPWM2_EXT_CLK */ - kXBAR1_OutputFlexpwm2IppIndFault0 = 72|0x10000U, /**< XBAR1_OUT72 output assigned to FLEXPWM2_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm2IppIndFault1 = 73|0x10000U, /**< XBAR1_OUT73 output assigned to FLEXPWM2_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm2ExtForce = 74|0x10000U, /**< XBAR1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */ - kXBAR1_OutputFlexpwm3Exta0 = 75|0x10000U, /**< XBAR1_OUT75 output assigned to FLEXPWM3_EXTA0 */ - kXBAR1_OutputFlexpwm3Exta1 = 76|0x10000U, /**< XBAR1_OUT76 output assigned to FLEXPWM3_EXTA1 */ - kXBAR1_OutputFlexpwm3Exta2 = 77|0x10000U, /**< XBAR1_OUT77 output assigned to FLEXPWM3_EXTA2 */ - kXBAR1_OutputFlexpwm3Exta3 = 78|0x10000U, /**< XBAR1_OUT78 output assigned to FLEXPWM3_EXTA3 */ - kXBAR1_OutputFlexpwm3ExtClk = 79|0x10000U, /**< XBAR1_OUT79 output assigned to FLEXPWM3_EXT_CLK */ - kXBAR1_OutputFlexpwm3ExtSync0 = 80|0x10000U, /**< XBAR1_OUT80 output assigned to FLEXPWM3_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm3ExtSync1 = 81|0x10000U, /**< XBAR1_OUT81 output assigned to FLEXPWM3_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm3ExtSync2 = 82|0x10000U, /**< XBAR1_OUT82 output assigned to FLEXPWM3_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm3ExtSync3 = 83|0x10000U, /**< XBAR1_OUT83 output assigned to FLEXPWM3_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm3IppIndFault0 = 84|0x10000U, /**< XBAR1_OUT84 output assigned to FLEXPWM3_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm3IppIndFault1 = 85|0x10000U, /**< XBAR1_OUT85 output assigned to FLEXPWM3_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm3ExtForce = 86|0x10000U, /**< XBAR1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */ - kXBAR1_OutputFlexpwm4ExtSync0 = 87|0x10000U, /**< XBAR1_OUT87 output assigned to FLEXPWM4_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm4ExtSync1 = 88|0x10000U, /**< XBAR1_OUT88 output assigned to FLEXPWM4_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm4ExtSync2 = 89|0x10000U, /**< XBAR1_OUT89 output assigned to FLEXPWM4_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm4ExtSync3 = 90|0x10000U, /**< XBAR1_OUT90 output assigned to FLEXPWM4_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm4IppIndFault0 = 91|0x10000U, /**< XBAR1_OUT91 output assigned to FLEXPWM4_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm4IppIndFault1 = 92|0x10000U, /**< XBAR1_OUT92 output assigned to FLEXPWM4_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm4ExtForce = 93|0x10000U, /**< XBAR1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */ - kXBAR1_OutputEnc1PhaseAInput = 94|0x10000U, /**< XBAR1_OUT94 output assigned to ENC1_PHASE_A_INPUT */ - kXBAR1_OutputEnc1PhaseBInput = 95|0x10000U, /**< XBAR1_OUT95 output assigned to ENC1_PHASE_B_INPUT */ - kXBAR1_OutputEnc1Index = 96|0x10000U, /**< XBAR1_OUT96 output assigned to ENC1_INDEX */ - kXBAR1_OutputEnc1Home = 97|0x10000U, /**< XBAR1_OUT97 output assigned to ENC1_HOME */ - kXBAR1_OutputEnc1Trigger = 98|0x10000U, /**< XBAR1_OUT98 output assigned to ENC1_TRIGGER */ - kXBAR1_OutputEnc2PhaseAInput = 99|0x10000U, /**< XBAR1_OUT99 output assigned to ENC2_PHASE_A_INPUT */ - kXBAR1_OutputEnc2PhaseBInput = 100|0x10000U, /**< XBAR1_OUT100 output assigned to ENC2_PHASE_B_INPUT */ - kXBAR1_OutputEnc2Index = 101|0x10000U, /**< XBAR1_OUT101 output assigned to ENC2_INDEX */ - kXBAR1_OutputEnc2Home = 102|0x10000U, /**< XBAR1_OUT102 output assigned to ENC2_HOME */ - kXBAR1_OutputEnc2Trigger = 103|0x10000U, /**< XBAR1_OUT103 output assigned to ENC2_TRIGGER */ - kXBAR1_OutputEnc3PhaseAInput = 104|0x10000U, /**< XBAR1_OUT104 output assigned to ENC3_PHASE_A_INPUT */ - kXBAR1_OutputEnc3PhaseBInput = 105|0x10000U, /**< XBAR1_OUT105 output assigned to ENC3_PHASE_B_INPUT */ - kXBAR1_OutputEnc3Index = 106|0x10000U, /**< XBAR1_OUT106 output assigned to ENC3_INDEX */ - kXBAR1_OutputEnc3Home = 107|0x10000U, /**< XBAR1_OUT107 output assigned to ENC3_HOME */ - kXBAR1_OutputEnc3Trigger = 108|0x10000U, /**< XBAR1_OUT108 output assigned to ENC3_TRIGGER */ - kXBAR1_OutputEnc4PhaseAInput = 109|0x10000U, /**< XBAR1_OUT109 output assigned to ENC4_PHASE_A_INPUT */ - kXBAR1_OutputEnc4PhaseBInput = 110|0x10000U, /**< XBAR1_OUT110 output assigned to ENC4_PHASE_B_INPUT */ - kXBAR1_OutputEnc4Index = 111|0x10000U, /**< XBAR1_OUT111 output assigned to ENC4_INDEX */ - kXBAR1_OutputEnc4Home = 112|0x10000U, /**< XBAR1_OUT112 output assigned to ENC4_HOME */ - kXBAR1_OutputEnc4Trigger = 113|0x10000U, /**< XBAR1_OUT113 output assigned to ENC4_TRIGGER */ - kXBAR1_OutputQtimer1Tmr0Input = 114|0x10000U, /**< XBAR1_OUT114 output assigned to QTIMER1_TMR0_INPUT */ - kXBAR1_OutputQtimer1Tmr1Input = 115|0x10000U, /**< XBAR1_OUT115 output assigned to QTIMER1_TMR1_INPUT */ - kXBAR1_OutputQtimer1Tmr2Input = 116|0x10000U, /**< XBAR1_OUT116 output assigned to QTIMER1_TMR2_INPUT */ - kXBAR1_OutputQtimer1Tmr3Input = 117|0x10000U, /**< XBAR1_OUT117 output assigned to QTIMER1_TMR3_INPUT */ - kXBAR1_OutputQtimer2Tmr0Input = 118|0x10000U, /**< XBAR1_OUT118 output assigned to QTIMER2_TMR0_INPUT */ - kXBAR1_OutputQtimer2Tmr1Input = 119|0x10000U, /**< XBAR1_OUT119 output assigned to QTIMER2_TMR1_INPUT */ - kXBAR1_OutputQtimer2Tmr2Input = 120|0x10000U, /**< XBAR1_OUT120 output assigned to QTIMER2_TMR2_INPUT */ - kXBAR1_OutputQtimer2Tmr3Input = 121|0x10000U, /**< XBAR1_OUT121 output assigned to QTIMER2_TMR3_INPUT */ - kXBAR1_OutputQtimer3Tmr0Input = 122|0x10000U, /**< XBAR1_OUT122 output assigned to QTIMER3_TMR0_INPUT */ - kXBAR1_OutputQtimer3Tmr1Input = 123|0x10000U, /**< XBAR1_OUT123 output assigned to QTIMER3_TMR1_INPUT */ - kXBAR1_OutputQtimer3Tmr2Input = 124|0x10000U, /**< XBAR1_OUT124 output assigned to QTIMER3_TMR2_INPUT */ - kXBAR1_OutputQtimer3Tmr3Input = 125|0x10000U, /**< XBAR1_OUT125 output assigned to QTIMER3_TMR3_INPUT */ - kXBAR1_OutputQtimer4Tmr0Input = 126|0x10000U, /**< XBAR1_OUT126 output assigned to QTIMER4_TMR0_INPUT */ - kXBAR1_OutputQtimer4Tmr1Input = 127|0x10000U, /**< XBAR1_OUT127 output assigned to QTIMER4_TMR1_INPUT */ - kXBAR1_OutputQtimer4Tmr2Input = 128|0x10000U, /**< XBAR1_OUT128 output assigned to QTIMER4_TMR2_INPUT */ - kXBAR1_OutputQtimer4Tmr3Input = 129|0x10000U, /**< XBAR1_OUT129 output assigned to QTIMER4_TMR3_INPUT */ - kXBAR1_OutputQtimer5Tmr0Input = 130|0x10000U, /**< XBAR1_OUT130 output assigned to QTIMER5_TMR0_INPUT */ - kXBAR1_OutputQtimer5Tmr1Input = 131|0x10000U, /**< XBAR1_OUT131 output assigned to QTIMER5_TMR1_INPUT */ - kXBAR1_OutputQtimer5Tmr2Input = 132|0x10000U, /**< XBAR1_OUT132 output assigned to QTIMER5_TMR2_INPUT */ - kXBAR1_OutputQtimer5Tmr3Input = 133|0x10000U, /**< XBAR1_OUT133 output assigned to QTIMER5_TMR3_INPUT */ - kXBAR1_OutputQtimer6Tmr0Input = 134|0x10000U, /**< XBAR1_OUT134 output assigned to QTIMER6_TMR0_INPUT */ - kXBAR1_OutputQtimer6Tmr1Input = 135|0x10000U, /**< XBAR1_OUT135 output assigned to QTIMER6_TMR1_INPUT */ - kXBAR1_OutputQtimer6Tmr2Input = 136|0x10000U, /**< XBAR1_OUT136 output assigned to QTIMER6_TMR2_INPUT */ - kXBAR1_OutputQtimer6Tmr3Input = 137|0x10000U, /**< XBAR1_OUT137 output assigned to QTIMER6_TMR3_INPUT */ - kXBAR1_OutputQtimer7Tmr0Input = 138|0x10000U, /**< XBAR1_OUT138 output assigned to QTIMER7_TMR0_INPUT */ - kXBAR1_OutputQtimer7Tmr1Input = 139|0x10000U, /**< XBAR1_OUT139 output assigned to QTIMER7_TMR1_INPUT */ - kXBAR1_OutputQtimer7Tmr2Input = 140|0x10000U, /**< XBAR1_OUT140 output assigned to QTIMER7_TMR2_INPUT */ - kXBAR1_OutputQtimer7Tmr3Input = 141|0x10000U, /**< XBAR1_OUT141 output assigned to QTIMER7_TMR3_INPUT */ - kXBAR1_OutputQtimer8Tmr0Input = 142|0x10000U, /**< XBAR1_OUT142 output assigned to QTIMER8_TMR0_INPUT */ - kXBAR1_OutputQtimer8Tmr1Input = 143|0x10000U, /**< XBAR1_OUT143 output assigned to QTIMER8_TMR1_INPUT */ - kXBAR1_OutputQtimer8Tmr2Input = 144|0x10000U, /**< XBAR1_OUT144 output assigned to QTIMER8_TMR2_INPUT */ - kXBAR1_OutputQtimer8Tmr3Input = 145|0x10000U, /**< XBAR1_OUT145 output assigned to QTIMER8_TMR3_INPUT */ - kXBAR1_OutputEwmEwmIn = 146|0x10000U, /**< XBAR1_OUT146 output assigned to EWM_EWM_IN */ - kXBAR1_OutputAnamixGlueTrgmuxInjectionTrg = 147|0x10000U, /**< XBAR1_OUT147 output assigned to ANAMIX_GLUE_TRGMUX_INJECTION_TRG */ - kXBAR1_OutputAnamixGlueTrgmuxStartTrg = 148|0x10000U, /**< XBAR1_OUT148 output assigned to ANAMIX_GLUE_TRGMUX_START_TRG */ - kXBAR1_OutputSinc1ExtTrigger0 = 149|0x10000U, /**< XBAR1_OUT149 output assigned to SINC1_EXT_TRIGGER0 */ - kXBAR1_OutputSinc1ExtTrigger1 = 150|0x10000U, /**< XBAR1_OUT150 output assigned to SINC1_EXT_TRIGGER1 */ - kXBAR1_OutputSinc1ExtTrigger2 = 151|0x10000U, /**< XBAR1_OUT151 output assigned to SINC1_EXT_TRIGGER2 */ - kXBAR1_OutputSinc1ExtTrigger3 = 152|0x10000U, /**< XBAR1_OUT152 output assigned to SINC1_EXT_TRIGGER3 */ - kXBAR1_OutputFlexio1FlexioTriggerIn0 = 153|0x10000U, /**< XBAR1_OUT153 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio1FlexioTriggerIn1 = 154|0x10000U, /**< XBAR1_OUT154 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputFlexio2FlexioTriggerIn0 = 155|0x10000U, /**< XBAR1_OUT155 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio2FlexioTriggerIn1 = 156|0x10000U, /**< XBAR1_OUT156 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputFlexio3FlexioTriggerIn0 = 157|0x10000U, /**< XBAR1_OUT157 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio3FlexioTriggerIn1 = 158|0x10000U, /**< XBAR1_OUT158 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputFlexio4FlexioTriggerIn0 = 159|0x10000U, /**< XBAR1_OUT159 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio4FlexioTriggerIn1 = 160|0x10000U, /**< XBAR1_OUT160 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputLpi2c1Lpi2cTrgInput = 161|0x10000U, /**< XBAR1_OUT161 output assigned to LPI2C1_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c2Lpi2cTrgInput = 162|0x10000U, /**< XBAR1_OUT162 output assigned to LPI2C2_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c3Lpi2cTrgInput = 163|0x10000U, /**< XBAR1_OUT163 output assigned to LPI2C3_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c4Lpi2cTrgInput = 164|0x10000U, /**< XBAR1_OUT164 output assigned to LPI2C4_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c5Lpi2cTrgInput = 165|0x10000U, /**< XBAR1_OUT165 output assigned to LPI2C5_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c6Lpi2cTrgInput = 166|0x10000U, /**< XBAR1_OUT166 output assigned to LPI2C6_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c7Lpi2cTrgInput = 167|0x10000U, /**< XBAR1_OUT167 output assigned to LPI2C7_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c8Lpi2cTrgInput = 168|0x10000U, /**< XBAR1_OUT168 output assigned to LPI2C8_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpspi1LpspiTrgInput = 169|0x10000U, /**< XBAR1_OUT169 output assigned to LPSPI1_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi2LpspiTrgInput = 170|0x10000U, /**< XBAR1_OUT170 output assigned to LPSPI2_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi3LpspiTrgInput = 171|0x10000U, /**< XBAR1_OUT171 output assigned to LPSPI3_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi4LpspiTrgInput = 172|0x10000U, /**< XBAR1_OUT172 output assigned to LPSPI4_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi5LpspiTrgInput = 173|0x10000U, /**< XBAR1_OUT173 output assigned to LPSPI5_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi6LpspiTrgInput = 174|0x10000U, /**< XBAR1_OUT174 output assigned to LPSPI6_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi7LpspiTrgInput = 175|0x10000U, /**< XBAR1_OUT175 output assigned to LPSPI7_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi8LpspiTrgInput = 176|0x10000U, /**< XBAR1_OUT176 output assigned to LPSPI8_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpuart1LpuartTrgInput = 177|0x10000U, /**< XBAR1_OUT177 output assigned to LPUART1_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart2LpuartTrgInput = 178|0x10000U, /**< XBAR1_OUT178 output assigned to LPUART2_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart3LpuartTrgInput = 179|0x10000U, /**< XBAR1_OUT179 output assigned to LPUART3_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart4LpuartTrgInput = 180|0x10000U, /**< XBAR1_OUT180 output assigned to LPUART4_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart5LpuartTrgInput = 181|0x10000U, /**< XBAR1_OUT181 output assigned to LPUART5_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart6LpuartTrgInput = 182|0x10000U, /**< XBAR1_OUT182 output assigned to LPUART6_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart7LpuartTrgInput = 183|0x10000U, /**< XBAR1_OUT183 output assigned to LPUART7_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart8LpuartTrgInput = 184|0x10000U, /**< XBAR1_OUT184 output assigned to LPUART8_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart9LpuartTrgInput = 185|0x10000U, /**< XBAR1_OUT185 output assigned to LPUART9_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart10LpuartTrgInput = 186|0x10000U, /**< XBAR1_OUT186 output assigned to LPUART10_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart11LpuartTrgInput = 187|0x10000U, /**< XBAR1_OUT187 output assigned to LPUART11_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart12LpuartTrgInput = 188|0x10000U, /**< XBAR1_OUT188 output assigned to LPUART12_LPUART_TRG_INPUT */ - kXBAR1_OutputLpit1LpitExtTrigIn0 = 189|0x10000U, /**< XBAR1_OUT189 output assigned to LPIT1_LPIT_EXT_TRIG_IN0 */ - kXBAR1_OutputLpit1LpitExtTrigIn1 = 190|0x10000U, /**< XBAR1_OUT190 output assigned to LPIT1_LPIT_EXT_TRIG_IN1 */ - kXBAR1_OutputLpit1LpitExtTrigIn2 = 191|0x10000U, /**< XBAR1_OUT191 output assigned to LPIT1_LPIT_EXT_TRIG_IN2 */ - kXBAR1_OutputLpit1LpitExtTrigIn3 = 192|0x10000U, /**< XBAR1_OUT192 output assigned to LPIT1_LPIT_EXT_TRIG_IN3 */ - kXBAR1_OutputTpm1LptpmTriggerIn0 = 193|0x10000U, /**< XBAR1_OUT193 output assigned to TPM1_LPTPM_TRIGGER_IN0 */ - kXBAR1_OutputTpm1LptpmTriggerIn1 = 194|0x10000U, /**< XBAR1_OUT194 output assigned to TPM1_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm2LptpmTriggerIn1 = 195|0x10000U, /**< XBAR1_OUT195 output assigned to TPM2_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm3LptpmTriggerIn1 = 196|0x10000U, /**< XBAR1_OUT196 output assigned to TPM3_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm1LptpmTriggerIn2 = 197|0x10000U, /**< XBAR1_OUT197 output assigned to TPM1_LPTPM_TRIGGER_IN2 */ - kXBAR1_OutputTpm1LptpmTriggerIn3 = 198|0x10000U, /**< XBAR1_OUT198 output assigned to TPM1_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm2LptpmTriggerIn3 = 199|0x10000U, /**< XBAR1_OUT199 output assigned to TPM2_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm3LptpmTriggerIn3 = 200|0x10000U, /**< XBAR1_OUT200 output assigned to TPM3_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm4LptpmTriggerIn0 = 201|0x10000U, /**< XBAR1_OUT201 output assigned to TPM4_LPTPM_TRIGGER_IN0 */ - kXBAR1_OutputTpm4LptpmTriggerIn1 = 202|0x10000U, /**< XBAR1_OUT202 output assigned to TPM4_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm5LptpmTriggerIn1 = 203|0x10000U, /**< XBAR1_OUT203 output assigned to TPM5_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm6LptpmTriggerIn1 = 204|0x10000U, /**< XBAR1_OUT204 output assigned to TPM6_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm4LptpmTriggerIn2 = 205|0x10000U, /**< XBAR1_OUT205 output assigned to TPM4_LPTPM_TRIGGER_IN2 */ - kXBAR1_OutputTpm4LptpmTriggerIn3 = 206|0x10000U, /**< XBAR1_OUT206 output assigned to TPM4_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm5LptpmTriggerIn3 = 207|0x10000U, /**< XBAR1_OUT207 output assigned to TPM5_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm6LptpmTriggerIn3 = 208|0x10000U, /**< XBAR1_OUT208 output assigned to TPM6_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputNetcTmr11588Trig1 = 209|0x10000U, /**< XBAR1_OUT209 output assigned to NETC_TMR1_1588_TRIG1 */ - kXBAR1_OutputNetcTmr11588Trig2 = 210|0x10000U, /**< XBAR1_OUT210 output assigned to NETC_TMR1_1588_TRIG2 */ - kXBAR1_OutputNetcTmr21588Trig1 = 211|0x10000U, /**< XBAR1_OUT211 output assigned to NETC_TMR2_1588_TRIG1 */ - kXBAR1_OutputNetcTmr21588Trig2 = 212|0x10000U, /**< XBAR1_OUT212 output assigned to NETC_TMR2_1588_TRIG2 */ - kXBAR1_OutputNetcTmr31588Trig1 = 213|0x10000U, /**< XBAR1_OUT213 output assigned to NETC_TMR3_1588_TRIG1 */ - kXBAR1_OutputNetcTmr31588Trig2 = 214|0x10000U, /**< XBAR1_OUT214 output assigned to NETC_TMR3_1588_TRIG2 */ - kXBAR1_OutputEnc1Icap1 = 215|0x10000U, /**< XBAR1_OUT215 output assigned to ENC1_ICAP1 */ - kXBAR1_OutputEnc1Icap2 = 216|0x10000U, /**< XBAR1_OUT216 output assigned to ENC1_ICAP2 */ - kXBAR1_OutputEnc1Icap3 = 217|0x10000U, /**< XBAR1_OUT217 output assigned to ENC1_ICAP3 */ - kXBAR1_OutputEnc2Icap1 = 218|0x10000U, /**< XBAR1_OUT218 output assigned to ENC2_ICAP1 */ - kXBAR1_OutputEnc2Icap2 = 219|0x10000U, /**< XBAR1_OUT219 output assigned to ENC2_ICAP2 */ - kXBAR1_OutputEnc2Icap3 = 220|0x10000U, /**< XBAR1_OUT220 output assigned to ENC2_ICAP3 */ - kXBAR1_OutputEnc3Icap1 = 221|0x10000U, /**< XBAR1_OUT221 output assigned to ENC3_ICAP1 */ - kXBAR1_OutputEnc3Icap2 = 222|0x10000U, /**< XBAR1_OUT222 output assigned to ENC3_ICAP2 */ - kXBAR1_OutputEnc3Icap3 = 223|0x10000U, /**< XBAR1_OUT223 output assigned to ENC3_ICAP3 */ - kXBAR1_OutputEnc4Icap1 = 224|0x10000U, /**< XBAR1_OUT224 output assigned to ENC4_ICAP1 */ - kXBAR1_OutputEnc4Icap2 = 225|0x10000U, /**< XBAR1_OUT225 output assigned to ENC4_ICAP2 */ - kXBAR1_OutputEnc4Icap3 = 226|0x10000U, /**< XBAR1_OUT226 output assigned to ENC4_ICAP3 */ - kXBAR1_OutputEcatLatchIn0 = 227|0x10000U, /**< XBAR1_OUT227 output assigned to ECAT_LATCH_IN0 */ - kXBAR1_OutputEcatLatchIn1 = 228|0x10000U, /**< XBAR1_OUT228 output assigned to ECAT_LATCH_IN1 */ - kXBAR1_OutputSafetyClkMonDutClk = 229|0x10000U, /**< XBAR1_OUT229 output assigned to SAFETY_CLK_MON_DUT_CLK */ - kXBAR1_OutputEndat21StrN = 230|0x10000U, /**< XBAR1_OUT230 output assigned to ENDAT2_1_STR_N */ - kXBAR1_OutputEndat21Ir6N = 231|0x10000U, /**< XBAR1_OUT231 output assigned to ENDAT2_1_IR6_N */ - kXBAR1_OutputEndat21Ir7N = 232|0x10000U, /**< XBAR1_OUT232 output assigned to ENDAT2_1_IR7_N */ - kXBAR1_OutputEndat22StrN = 233|0x10000U, /**< XBAR1_OUT233 output assigned to ENDAT2_2_STR_N */ - kXBAR1_OutputEndat22Ir6N = 234|0x10000U, /**< XBAR1_OUT234 output assigned to ENDAT2_2_IR6_N */ - kXBAR1_OutputEndat22Ir7N = 235|0x10000U, /**< XBAR1_OUT235 output assigned to ENDAT2_2_IR7_N */ - kXBAR1_OutputEndat3HwStrobe = 236|0x10000U, /**< XBAR1_OUT236 output assigned to ENDAT3_HW_STROBE */ - kXBAR1_OutputBissGetsens = 237|0x10000U, /**< XBAR1_OUT237 output assigned to BISS_GETSENS */ - kXBAR1_OutputSinc3ExtTrigger2 = 238|0x10000U, /**< XBAR1_OUT238 output assigned to SINC3_EXT_TRIGGER2 */ - kXBAR1_OutputSinc3ExtTrigger3 = 239|0x10000U, /**< XBAR1_OUT239 output assigned to SINC3_EXT_TRIGGER3 */ - kXBAR1_OutputHiperface1SyncXbar = 240|0x10000U, /**< XBAR1_OUT240 output assigned to HIPERFACE1_SYNC_XBAR */ - kXBAR1_OutputHiperface2SyncXbar = 241|0x10000U, /**< XBAR1_OUT241 output assigned to HIPERFACE2_SYNC_XBAR */ - kXBAR1_OutputTriggerSyncAsyncIn8 = 242|0x10000U, /**< XBAR1_OUT242 output assigned to TRIGGER_SYNC_ASYNC_IN8 */ - kXBAR1_OutputTriggerSyncAsyncIn9 = 243|0x10000U, /**< XBAR1_OUT243 output assigned to TRIGGER_SYNC_ASYNC_IN9 */ - kXBAR1_OutputTriggerSyncAsyncIn10 = 244|0x10000U, /**< XBAR1_OUT244 output assigned to TRIGGER_SYNC_ASYNC_IN10 */ - kXBAR1_OutputTriggerSyncAsyncIn11 = 245|0x10000U, /**< XBAR1_OUT245 output assigned to TRIGGER_SYNC_ASYNC_IN11 */ - kXBAR1_OutputTriggerSyncAsyncIn12 = 246|0x10000U, /**< XBAR1_OUT246 output assigned to TRIGGER_SYNC_ASYNC_IN12 */ - kXBAR1_OutputTriggerSyncAsyncIn13 = 247|0x10000U, /**< XBAR1_OUT247 output assigned to TRIGGER_SYNC_ASYNC_IN13 */ - kXBAR1_OutputTriggerSyncAsyncIn14 = 248|0x10000U, /**< XBAR1_OUT248 output assigned to TRIGGER_SYNC_ASYNC_IN14 */ - kXBAR1_OutputTriggerSyncAsyncIn15 = 249|0x10000U, /**< XBAR1_OUT249 output assigned to TRIGGER_SYNC_ASYNC_IN15 */ - kXBAR1_OutputSinc2ExtTrigger0 = 250|0x10000U, /**< XBAR1_OUT250 output assigned to SINC2_EXT_TRIGGER0 */ - kXBAR1_OutputSinc2ExtTrigger1 = 251|0x10000U, /**< XBAR1_OUT251 output assigned to SINC2_EXT_TRIGGER1 */ - kXBAR1_OutputSinc2ExtTrigger2 = 252|0x10000U, /**< XBAR1_OUT252 output assigned to SINC2_EXT_TRIGGER2 */ - kXBAR1_OutputSinc2ExtTrigger3 = 253|0x10000U, /**< XBAR1_OUT253 output assigned to SINC2_EXT_TRIGGER3 */ - kXBAR1_OutputSinc3ExtTrigger0 = 254|0x10000U, /**< XBAR1_OUT254 output assigned to SINC3_EXT_TRIGGER0 */ - kXBAR1_OutputSinc3ExtTrigger1 = 255|0x10000U, /**< XBAR1_OUT255 output assigned to SINC3_EXT_TRIGGER1 */ - kXBAR2_OutputAoi1In00 = 0|0x20000U, /**< XBAR2_OUT0 output assigned to AOI1_IN00 */ - kXBAR2_OutputAoi1In01 = 1|0x20000U, /**< XBAR2_OUT1 output assigned to AOI1_IN01 */ - kXBAR2_OutputAoi1In02 = 2|0x20000U, /**< XBAR2_OUT2 output assigned to AOI1_IN02 */ - kXBAR2_OutputAoi1In03 = 3|0x20000U, /**< XBAR2_OUT3 output assigned to AOI1_IN03 */ - kXBAR2_OutputAoi1In04 = 4|0x20000U, /**< XBAR2_OUT4 output assigned to AOI1_IN04 */ - kXBAR2_OutputAoi1In05 = 5|0x20000U, /**< XBAR2_OUT5 output assigned to AOI1_IN05 */ - kXBAR2_OutputAoi1In06 = 6|0x20000U, /**< XBAR2_OUT6 output assigned to AOI1_IN06 */ - kXBAR2_OutputAoi1In07 = 7|0x20000U, /**< XBAR2_OUT7 output assigned to AOI1_IN07 */ - kXBAR2_OutputAoi1In08 = 8|0x20000U, /**< XBAR2_OUT8 output assigned to AOI1_IN08 */ - kXBAR2_OutputAoi1In09 = 9|0x20000U, /**< XBAR2_OUT9 output assigned to AOI1_IN09 */ - kXBAR2_OutputAoi1In10 = 10|0x20000U, /**< XBAR2_OUT10 output assigned to AOI1_IN10 */ - kXBAR2_OutputAoi1In11 = 11|0x20000U, /**< XBAR2_OUT11 output assigned to AOI1_IN11 */ - kXBAR2_OutputAoi1In12 = 12|0x20000U, /**< XBAR2_OUT12 output assigned to AOI1_IN12 */ - kXBAR2_OutputAoi1In13 = 13|0x20000U, /**< XBAR2_OUT13 output assigned to AOI1_IN13 */ - kXBAR2_OutputAoi1In14 = 14|0x20000U, /**< XBAR2_OUT14 output assigned to AOI1_IN14 */ - kXBAR2_OutputAoi1In15 = 15|0x20000U, /**< XBAR2_OUT15 output assigned to AOI1_IN15 */ - kXBAR2_OutputAoi3In00 = 16|0x20000U, /**< XBAR2_OUT16 output assigned to AOI3_IN00 */ - kXBAR2_OutputAoi3In01 = 17|0x20000U, /**< XBAR2_OUT17 output assigned to AOI3_IN01 */ - kXBAR2_OutputAoi3In02 = 18|0x20000U, /**< XBAR2_OUT18 output assigned to AOI3_IN02 */ - kXBAR2_OutputAoi3In03 = 19|0x20000U, /**< XBAR2_OUT19 output assigned to AOI3_IN03 */ - kXBAR2_OutputAoi3In04 = 20|0x20000U, /**< XBAR2_OUT20 output assigned to AOI3_IN04 */ - kXBAR2_OutputAoi3In05 = 21|0x20000U, /**< XBAR2_OUT21 output assigned to AOI3_IN05 */ - kXBAR2_OutputAoi3In06 = 22|0x20000U, /**< XBAR2_OUT22 output assigned to AOI3_IN06 */ - kXBAR2_OutputAoi3In07 = 23|0x20000U, /**< XBAR2_OUT23 output assigned to AOI3_IN07 */ - kXBAR2_OutputAoi3In08 = 24|0x20000U, /**< XBAR2_OUT24 output assigned to AOI3_IN08 */ - kXBAR2_OutputAoi3In09 = 25|0x20000U, /**< XBAR2_OUT25 output assigned to AOI3_IN09 */ - kXBAR2_OutputAoi3In10 = 26|0x20000U, /**< XBAR2_OUT26 output assigned to AOI3_IN10 */ - kXBAR2_OutputAoi3In11 = 27|0x20000U, /**< XBAR2_OUT27 output assigned to AOI3_IN11 */ - kXBAR2_OutputAoi3In12 = 28|0x20000U, /**< XBAR2_OUT28 output assigned to AOI3_IN12 */ - kXBAR2_OutputAoi3In13 = 29|0x20000U, /**< XBAR2_OUT29 output assigned to AOI3_IN13 */ - kXBAR2_OutputAoi3In14 = 30|0x20000U, /**< XBAR2_OUT30 output assigned to AOI3_IN14 */ - kXBAR2_OutputAoi3In15 = 31|0x20000U, /**< XBAR2_OUT31 output assigned to AOI3_IN15 */ - kXBAR3_OutputAoi2In00 = 0|0x30000U, /**< XBAR3_OUT0 output assigned to AOI2_IN00 */ - kXBAR3_OutputAoi2In01 = 1|0x30000U, /**< XBAR3_OUT1 output assigned to AOI2_IN01 */ - kXBAR3_OutputAoi2In02 = 2|0x30000U, /**< XBAR3_OUT2 output assigned to AOI2_IN02 */ - kXBAR3_OutputAoi2In03 = 3|0x30000U, /**< XBAR3_OUT3 output assigned to AOI2_IN03 */ - kXBAR3_OutputAoi2In04 = 4|0x30000U, /**< XBAR3_OUT4 output assigned to AOI2_IN04 */ - kXBAR3_OutputAoi2In05 = 5|0x30000U, /**< XBAR3_OUT5 output assigned to AOI2_IN05 */ - kXBAR3_OutputAoi2In06 = 6|0x30000U, /**< XBAR3_OUT6 output assigned to AOI2_IN06 */ - kXBAR3_OutputAoi2In07 = 7|0x30000U, /**< XBAR3_OUT7 output assigned to AOI2_IN07 */ - kXBAR3_OutputAoi2In08 = 8|0x30000U, /**< XBAR3_OUT8 output assigned to AOI2_IN08 */ - kXBAR3_OutputAoi2In09 = 9|0x30000U, /**< XBAR3_OUT9 output assigned to AOI2_IN09 */ - kXBAR3_OutputAoi2In10 = 10|0x30000U, /**< XBAR3_OUT10 output assigned to AOI2_IN10 */ - kXBAR3_OutputAoi2In11 = 11|0x30000U, /**< XBAR3_OUT11 output assigned to AOI2_IN11 */ - kXBAR3_OutputAoi2In12 = 12|0x30000U, /**< XBAR3_OUT12 output assigned to AOI2_IN12 */ - kXBAR3_OutputAoi2In13 = 13|0x30000U, /**< XBAR3_OUT13 output assigned to AOI2_IN13 */ - kXBAR3_OutputAoi2In14 = 14|0x30000U, /**< XBAR3_OUT14 output assigned to AOI2_IN14 */ - kXBAR3_OutputAoi2In15 = 15|0x30000U, /**< XBAR3_OUT15 output assigned to AOI2_IN15 */ - kXBAR3_OutputAoi4In00 = 16|0x30000U, /**< XBAR3_OUT16 output assigned to AOI4_IN00 */ - kXBAR3_OutputAoi4In01 = 17|0x30000U, /**< XBAR3_OUT17 output assigned to AOI4_IN01 */ - kXBAR3_OutputAoi4In02 = 18|0x30000U, /**< XBAR3_OUT18 output assigned to AOI4_IN02 */ - kXBAR3_OutputAoi4In03 = 19|0x30000U, /**< XBAR3_OUT19 output assigned to AOI4_IN03 */ - kXBAR3_OutputAoi4In04 = 20|0x30000U, /**< XBAR3_OUT20 output assigned to AOI4_IN04 */ - kXBAR3_OutputAoi4In05 = 21|0x30000U, /**< XBAR3_OUT21 output assigned to AOI4_IN05 */ - kXBAR3_OutputAoi4In06 = 22|0x30000U, /**< XBAR3_OUT22 output assigned to AOI4_IN06 */ - kXBAR3_OutputAoi4In07 = 23|0x30000U, /**< XBAR3_OUT23 output assigned to AOI4_IN07 */ - kXBAR3_OutputAoi4In08 = 24|0x30000U, /**< XBAR3_OUT24 output assigned to AOI4_IN08 */ - kXBAR3_OutputAoi4In09 = 25|0x30000U, /**< XBAR3_OUT25 output assigned to AOI4_IN09 */ - kXBAR3_OutputAoi4In10 = 26|0x30000U, /**< XBAR3_OUT26 output assigned to AOI4_IN10 */ - kXBAR3_OutputAoi4In11 = 27|0x30000U, /**< XBAR3_OUT27 output assigned to AOI4_IN11 */ - kXBAR3_OutputAoi4In12 = 28|0x30000U, /**< XBAR3_OUT28 output assigned to AOI4_IN12 */ - kXBAR3_OutputAoi4In13 = 29|0x30000U, /**< XBAR3_OUT29 output assigned to AOI4_IN13 */ - kXBAR3_OutputAoi4In14 = 30|0x30000U, /**< XBAR3_OUT30 output assigned to AOI4_IN14 */ - kXBAR3_OutputAoi4In15 = 31|0x30000U, /**< XBAR3_OUT31 output assigned to AOI4_IN15 */ -} xbar_output_signal_t; -#endif /* XBAR_OUTPUT_SIGNAL_T_ */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -1428,5 +336,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* XBAR1_H_ */ +#endif /* PERI_XBAR1_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR2.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR2.h index d59fcdf4d..aff67aa2b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR2.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR2.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBAR2 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file XBAR2.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_XBAR2.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for XBAR2 * * CMSIS Peripheral Access Layer for XBAR2 */ -#if !defined(XBAR2_H_) -#define XBAR2_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_XBAR2_H_) +#define PERI_XBAR2_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -187,1101 +190,6 @@ #error "No valid CPU defined!" #endif -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -#if !defined(XBAR_INPUT_SIGNAL_T_) -#define XBAR_INPUT_SIGNAL_T_ -typedef enum _xbar_input_signal -{ - kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ - kXBAR1_InputLogicHigh = 1|0x10000U, /**< LOGIC_HIGH output assigned to XBAR1_IN1 input. */ - kXBAR1_InputLogicLow1 = 2|0x10000U, /**< LOGIC_LOW1 output assigned to XBAR1_IN2 input. */ - kXBAR1_InputLogicHigh1 = 3|0x10000U, /**< LOGIC_HIGH1 output assigned to XBAR1_IN3 input. */ - kXBAR1_InputIomuxXbarIn04 = 4|0x10000U, /**< IOMUX_XBAR_IN04 output assigned to XBAR1_IN4 input. */ - kXBAR1_InputIomuxXbarIn05 = 5|0x10000U, /**< IOMUX_XBAR_IN05 output assigned to XBAR1_IN5 input. */ - kXBAR1_InputIomuxXbarIn06 = 6|0x10000U, /**< IOMUX_XBAR_IN06 output assigned to XBAR1_IN6 input. */ - kXBAR1_InputIomuxXbarIn07 = 7|0x10000U, /**< IOMUX_XBAR_IN07 output assigned to XBAR1_IN7 input. */ - kXBAR1_InputIomuxXbarIn08 = 8|0x10000U, /**< IOMUX_XBAR_IN08 output assigned to XBAR1_IN8 input. */ - kXBAR1_InputIomuxXbarIn09 = 9|0x10000U, /**< IOMUX_XBAR_IN09 output assigned to XBAR1_IN9 input. */ - kXBAR1_InputIomuxXbarIn10 = 10|0x10000U, /**< IOMUX_XBAR_IN10 output assigned to XBAR1_IN10 input. */ - kXBAR1_InputIomuxXbarIn11 = 11|0x10000U, /**< IOMUX_XBAR_IN11 output assigned to XBAR1_IN11 input. */ - kXBAR1_InputIomuxXbarIn12 = 12|0x10000U, /**< IOMUX_XBAR_IN12 output assigned to XBAR1_IN12 input. */ - kXBAR1_InputIomuxXbarIn13 = 13|0x10000U, /**< IOMUX_XBAR_IN13 output assigned to XBAR1_IN13 input. */ - kXBAR1_InputIomuxXbarIn14 = 14|0x10000U, /**< IOMUX_XBAR_IN14 output assigned to XBAR1_IN14 input. */ - kXBAR1_InputIomuxXbarIn15 = 15|0x10000U, /**< IOMUX_XBAR_IN15 output assigned to XBAR1_IN15 input. */ - kXBAR1_InputIomuxXbarIn16 = 16|0x10000U, /**< IOMUX_XBAR_IN16 output assigned to XBAR1_IN16 input. */ - kXBAR1_InputIomuxXbarIn17 = 17|0x10000U, /**< IOMUX_XBAR_IN17 output assigned to XBAR1_IN17 input. */ - kXBAR1_InputIomuxXbarIn18 = 18|0x10000U, /**< IOMUX_XBAR_IN18 output assigned to XBAR1_IN18 input. */ - kXBAR1_InputIomuxXbarIn19 = 19|0x10000U, /**< IOMUX_XBAR_IN19 output assigned to XBAR1_IN19 input. */ - kXBAR1_InputIomuxXbarIn20 = 20|0x10000U, /**< IOMUX_XBAR_IN20 output assigned to XBAR1_IN20 input. */ - kXBAR1_InputIomuxXbarIn21 = 21|0x10000U, /**< IOMUX_XBAR_IN21 output assigned to XBAR1_IN21 input. */ - kXBAR1_InputIomuxXbarIn22 = 22|0x10000U, /**< IOMUX_XBAR_IN22 output assigned to XBAR1_IN22 input. */ - kXBAR1_InputIomuxXbarIn23 = 23|0x10000U, /**< IOMUX_XBAR_IN23 output assigned to XBAR1_IN23 input. */ - kXBAR1_InputIomuxXbarIn24 = 24|0x10000U, /**< IOMUX_XBAR_IN24 output assigned to XBAR1_IN24 input. */ - kXBAR1_InputIomuxXbarIn25 = 25|0x10000U, /**< IOMUX_XBAR_IN25 output assigned to XBAR1_IN25 input. */ - kXBAR1_InputIomuxXbarIn26 = 26|0x10000U, /**< IOMUX_XBAR_IN26 output assigned to XBAR1_IN26 input. */ - kXBAR1_InputIomuxXbarIn27 = 27|0x10000U, /**< IOMUX_XBAR_IN27 output assigned to XBAR1_IN27 input. */ - kXBAR1_InputIomuxXbarIn28 = 28|0x10000U, /**< IOMUX_XBAR_IN28 output assigned to XBAR1_IN28 input. */ - kXBAR1_InputIomuxXbarIn29 = 29|0x10000U, /**< IOMUX_XBAR_IN29 output assigned to XBAR1_IN29 input. */ - kXBAR1_InputIomuxXbarIn30 = 30|0x10000U, /**< IOMUX_XBAR_IN30 output assigned to XBAR1_IN30 input. */ - kXBAR1_InputIomuxXbarIn31 = 31|0x10000U, /**< IOMUX_XBAR_IN31 output assigned to XBAR1_IN31 input. */ - kXBAR1_InputIomuxXbarIn32 = 32|0x10000U, /**< IOMUX_XBAR_IN32 output assigned to XBAR1_IN32 input. */ - kXBAR1_InputIomuxXbarIn33 = 33|0x10000U, /**< IOMUX_XBAR_IN33 output assigned to XBAR1_IN33 input. */ - kXBAR1_InputIomuxXbarIn34 = 34|0x10000U, /**< IOMUX_XBAR_IN34 output assigned to XBAR1_IN34 input. */ - kXBAR1_InputIomuxXbarIn35 = 35|0x10000U, /**< IOMUX_XBAR_IN35 output assigned to XBAR1_IN35 input. */ - kXBAR1_InputIomuxXbarIn36 = 36|0x10000U, /**< IOMUX_XBAR_IN36 output assigned to XBAR1_IN36 input. */ - kXBAR1_InputIomuxXbarIn37 = 37|0x10000U, /**< IOMUX_XBAR_IN37 output assigned to XBAR1_IN37 input. */ - kXBAR1_InputIomuxXbarIn38 = 38|0x10000U, /**< IOMUX_XBAR_IN38 output assigned to XBAR1_IN38 input. */ - kXBAR1_InputIomuxXbarIn39 = 39|0x10000U, /**< IOMUX_XBAR_IN39 output assigned to XBAR1_IN39 input. */ - kXBAR1_InputIomuxXbarIn40 = 40|0x10000U, /**< IOMUX_XBAR_IN40 output assigned to XBAR1_IN40 input. */ - kXBAR1_InputIomuxXbarIn41 = 41|0x10000U, /**< IOMUX_XBAR_IN41 output assigned to XBAR1_IN41 input. */ - kXBAR1_InputIomuxXbarIn42 = 42|0x10000U, /**< IOMUX_XBAR_IN42 output assigned to XBAR1_IN42 input. */ - kXBAR1_InputIomuxXbarIn43 = 43|0x10000U, /**< IOMUX_XBAR_IN43 output assigned to XBAR1_IN43 input. */ - kXBAR1_InputIomuxXbarIn44 = 44|0x10000U, /**< IOMUX_XBAR_IN44 output assigned to XBAR1_IN44 input. */ - kXBAR1_InputIomuxXbarIn45 = 45|0x10000U, /**< IOMUX_XBAR_IN45 output assigned to XBAR1_IN45 input. */ - kXBAR1_InputIomuxXbarIn46 = 46|0x10000U, /**< IOMUX_XBAR_IN46 output assigned to XBAR1_IN46 input. */ - kXBAR1_InputIomuxXbarIn47 = 47|0x10000U, /**< IOMUX_XBAR_IN47 output assigned to XBAR1_IN47 input. */ - kXBAR1_InputIomuxXbarIn48 = 48|0x10000U, /**< IOMUX_XBAR_IN48 output assigned to XBAR1_IN48 input. */ - kXBAR1_InputQtimer1Timer0 = 49|0x10000U, /**< QTIMER1_TIMER0 output assigned to XBAR1_IN49 input. */ - kXBAR1_InputQtimer1Timer1 = 50|0x10000U, /**< QTIMER1_TIMER1 output assigned to XBAR1_IN50 input. */ - kXBAR1_InputQtimer1Timer2 = 51|0x10000U, /**< QTIMER1_TIMER2 output assigned to XBAR1_IN51 input. */ - kXBAR1_InputQtimer1Timer3 = 52|0x10000U, /**< QTIMER1_TIMER3 output assigned to XBAR1_IN52 input. */ - kXBAR1_InputQtimer2Timer0 = 53|0x10000U, /**< QTIMER2_TIMER0 output assigned to XBAR1_IN53 input. */ - kXBAR1_InputQtimer2Timer1 = 54|0x10000U, /**< QTIMER2_TIMER1 output assigned to XBAR1_IN54 input. */ - kXBAR1_InputQtimer2Timer2 = 55|0x10000U, /**< QTIMER2_TIMER2 output assigned to XBAR1_IN55 input. */ - kXBAR1_InputQtimer2Timer3 = 56|0x10000U, /**< QTIMER2_TIMER3 output assigned to XBAR1_IN56 input. */ - kXBAR1_InputQtimer3Timer0 = 57|0x10000U, /**< QTIMER3_TIMER0 output assigned to XBAR1_IN57 input. */ - kXBAR1_InputQtimer3Timer1 = 58|0x10000U, /**< QTIMER3_TIMER1 output assigned to XBAR1_IN58 input. */ - kXBAR1_InputQtimer3Timer2 = 59|0x10000U, /**< QTIMER3_TIMER2 output assigned to XBAR1_IN59 input. */ - kXBAR1_InputQtimer3Timer3 = 60|0x10000U, /**< QTIMER3_TIMER3 output assigned to XBAR1_IN60 input. */ - kXBAR1_InputQtimer4Timer0 = 61|0x10000U, /**< QTIMER4_TIMER0 output assigned to XBAR1_IN61 input. */ - kXBAR1_InputQtimer4Timer1 = 62|0x10000U, /**< QTIMER4_TIMER1 output assigned to XBAR1_IN62 input. */ - kXBAR1_InputQtimer4Timer2 = 63|0x10000U, /**< QTIMER4_TIMER2 output assigned to XBAR1_IN63 input. */ - kXBAR1_InputQtimer4Timer3 = 64|0x10000U, /**< QTIMER4_TIMER3 output assigned to XBAR1_IN64 input. */ - kXBAR1_InputQtimer5Timer0 = 65|0x10000U, /**< QTIMER5_TIMER0 output assigned to XBAR1_IN65 input. */ - kXBAR1_InputQtimer5Timer1 = 66|0x10000U, /**< QTIMER5_TIMER1 output assigned to XBAR1_IN66 input. */ - kXBAR1_InputQtimer5Timer2 = 67|0x10000U, /**< QTIMER5_TIMER2 output assigned to XBAR1_IN67 input. */ - kXBAR1_InputQtimer5Timer3 = 68|0x10000U, /**< QTIMER5_TIMER3 output assigned to XBAR1_IN68 input. */ - kXBAR1_InputQtimer6Timer0 = 69|0x10000U, /**< QTIMER6_TIMER0 output assigned to XBAR1_IN69 input. */ - kXBAR1_InputQtimer6Timer1 = 70|0x10000U, /**< QTIMER6_TIMER1 output assigned to XBAR1_IN70 input. */ - kXBAR1_InputQtimer6Timer2 = 71|0x10000U, /**< QTIMER6_TIMER2 output assigned to XBAR1_IN71 input. */ - kXBAR1_InputQtimer6Timer3 = 72|0x10000U, /**< QTIMER6_TIMER3 output assigned to XBAR1_IN72 input. */ - kXBAR1_InputQtimer7Timer0 = 73|0x10000U, /**< QTIMER7_TIMER0 output assigned to XBAR1_IN73 input. */ - kXBAR1_InputQtimer7Timer1 = 74|0x10000U, /**< QTIMER7_TIMER1 output assigned to XBAR1_IN74 input. */ - kXBAR1_InputQtimer7Timer2 = 75|0x10000U, /**< QTIMER7_TIMER2 output assigned to XBAR1_IN75 input. */ - kXBAR1_InputQtimer7Timer3 = 76|0x10000U, /**< QTIMER7_TIMER3 output assigned to XBAR1_IN76 input. */ - kXBAR1_InputQtimer8Timer0 = 77|0x10000U, /**< QTIMER8_TIMER0 output assigned to XBAR1_IN77 input. */ - kXBAR1_InputQtimer8Timer1 = 78|0x10000U, /**< QTIMER8_TIMER1 output assigned to XBAR1_IN78 input. */ - kXBAR1_InputQtimer8Timer2 = 79|0x10000U, /**< QTIMER8_TIMER2 output assigned to XBAR1_IN79 input. */ - kXBAR1_InputQtimer8Timer3 = 80|0x10000U, /**< QTIMER8_TIMER3 output assigned to XBAR1_IN80 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger0 = 81|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR1_IN81 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger0 = 82|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER0 output assigned to XBAR1_IN82 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger1 = 83|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR1_IN83 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger1 = 84|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER1 output assigned to XBAR1_IN84 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger2 = 85|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR1_IN85 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger2 = 86|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER2 output assigned to XBAR1_IN86 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger3 = 87|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR1_IN87 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger3 = 88|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER3 output assigned to XBAR1_IN88 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger0 = 89|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR1_IN89 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger0 = 90|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER0 output assigned to XBAR1_IN90 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger1 = 91|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR1_IN91 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger1 = 92|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER1 output assigned to XBAR1_IN92 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger2 = 93|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR1_IN93 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger2 = 94|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER2 output assigned to XBAR1_IN94 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger3 = 95|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR1_IN95 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger3 = 96|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER3 output assigned to XBAR1_IN96 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger0 = 97|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR1_IN97 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger0 = 98|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER0 output assigned to XBAR1_IN98 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger1 = 99|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR1_IN99 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger1 = 100|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER1 output assigned to XBAR1_IN100 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger2 = 101|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR1_IN101 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger2 = 102|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER2 output assigned to XBAR1_IN102 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger3 = 103|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR1_IN103 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger3 = 104|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER3 output assigned to XBAR1_IN104 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger0 = 105|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR1_IN105 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger0 = 106|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER0 output assigned to XBAR1_IN106 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger1 = 107|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR1_IN107 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger1 = 108|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER1 output assigned to XBAR1_IN108 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger2 = 109|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR1_IN109 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger2 = 110|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER2 output assigned to XBAR1_IN110 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger3 = 111|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR1_IN111 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger3 = 112|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER3 output assigned to XBAR1_IN112 input. */ - kXBAR1_InputLpit1LpitTrigOut0 = 113|0x10000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR1_IN113 input. */ - kXBAR1_InputLpit1LpitTrigOut1 = 114|0x10000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR1_IN114 input. */ - kXBAR1_InputLpit1LpitTrigOut2 = 115|0x10000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR1_IN115 input. */ - kXBAR1_InputLpit1LpitTrigOut3 = 116|0x10000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR1_IN116 input. */ - kXBAR1_InputLpit2LpitTrigOut0 = 117|0x10000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR1_IN117 input. */ - kXBAR1_InputLpit2LpitTrigOut1 = 118|0x10000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR1_IN118 input. */ - kXBAR1_InputLpit2LpitTrigOut2 = 119|0x10000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR1_IN119 input. */ - kXBAR1_InputLpit2LpitTrigOut3 = 120|0x10000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR1_IN120 input. */ - kXBAR1_InputLpit3LpitTrigOut0 = 121|0x10000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR1_IN121 input. */ - kXBAR1_InputLpit3LpitTrigOut1 = 122|0x10000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR1_IN122 input. */ - kXBAR1_InputLpit3LpitTrigOut2 = 123|0x10000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR1_IN123 input. */ - kXBAR1_InputLpit3LpitTrigOut3 = 124|0x10000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR1_IN124 input. */ - kXBAR1_InputTriggerSyncSyncOut0 = 125|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT0 output assigned to XBAR1_IN125 input. */ - kXBAR1_InputTriggerSyncSyncOut1 = 126|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT1 output assigned to XBAR1_IN126 input. */ - kXBAR1_InputTriggerSyncSyncOut2 = 127|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT2 output assigned to XBAR1_IN127 input. */ - kXBAR1_InputTriggerSyncSyncOut3 = 128|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT3 output assigned to XBAR1_IN128 input. */ - kXBAR1_InputEdma2DmaTriggerOut0 = 129|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN129 input. */ - kXBAR1_InputEdma2DmaTriggerOut1 = 130|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN130 input. */ - kXBAR1_InputEdma2DmaTriggerOut2 = 131|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN131 input. */ - kXBAR1_InputEdma2DmaTriggerOut3 = 132|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN132 input. */ - kXBAR1_InputEdma2DmaTriggerOut4 = 133|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN133 input. */ - kXBAR1_InputEdma2DmaTriggerOut5 = 134|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN134 input. */ - kXBAR1_InputEdma2DmaTriggerOut6 = 135|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN135 input. */ - kXBAR1_InputEdma2DmaTriggerOut7 = 136|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN136 input. */ - kXBAR1_InputEdma1DmaTriggerOut0 = 137|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN137 input. */ - kXBAR1_InputEdma1DmaTriggerOut1 = 138|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN138 input. */ - kXBAR1_InputEdma1DmaTriggerOut2 = 139|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN139 input. */ - kXBAR1_InputEdma1DmaTriggerOut3 = 140|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN140 input. */ - kXBAR1_InputEdma1DmaTriggerOut4 = 141|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN141 input. */ - kXBAR1_InputEdma1DmaTriggerOut5 = 142|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN142 input. */ - kXBAR1_InputEdma1DmaTriggerOut6 = 143|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN143 input. */ - kXBAR1_InputEdma1DmaTriggerOut7 = 144|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN144 input. */ - kXBAR1_InputEdma3DmaTriggerOut0 = 145|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN145 input. */ - kXBAR1_InputEdma3DmaTriggerOut1 = 146|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN146 input. */ - kXBAR1_InputEdma3DmaTriggerOut2 = 147|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN147 input. */ - kXBAR1_InputEdma3DmaTriggerOut3 = 148|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN148 input. */ - kXBAR1_InputEdma3DmaTriggerOut4 = 149|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN149 input. */ - kXBAR1_InputEdma3DmaTriggerOut5 = 150|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN150 input. */ - kXBAR1_InputEdma3DmaTriggerOut6 = 151|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN151 input. */ - kXBAR1_InputEdma3DmaTriggerOut7 = 152|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN152 input. */ - kXBAR1_InputEdma4DmaTriggerOut0 = 153|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN153 input. */ - kXBAR1_InputEdma4DmaTriggerOut1 = 154|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN154 input. */ - kXBAR1_InputEdma4DmaTriggerOut2 = 155|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN155 input. */ - kXBAR1_InputEdma4DmaTriggerOut3 = 156|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN156 input. */ - kXBAR1_InputEdma4DmaTriggerOut4 = 157|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN157 input. */ - kXBAR1_InputEdma4DmaTriggerOut5 = 158|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN158 input. */ - kXBAR1_InputEdma4DmaTriggerOut6 = 159|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN159 input. */ - kXBAR1_InputEdma4DmaTriggerOut7 = 160|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN160 input. */ - kXBAR1_InputAdc1IpiIntEoc = 161|0x10000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR1_IN161 input. */ - kXBAR1_InputAdc1IpiIntWd = 162|0x10000U, /**< ADC1_IPI_INT_WD output assigned to XBAR1_IN162 input. */ - kXBAR1_InputTpm1LptpmChTrigger0 = 163|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN163 input. */ - kXBAR1_InputTpm1LptpmChTrigger1 = 164|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN164 input. */ - kXBAR1_InputTpm1LptpmChTrigger2 = 165|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN165 input. */ - kXBAR1_InputTpm1LptpmChTrigger3 = 166|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN166 input. */ - kXBAR1_InputTpm1LptpmTrigger = 167|0x10000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR1_IN167 input. */ - kXBAR1_InputTpm2LptpmChTrigger0 = 168|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN168 input. */ - kXBAR1_InputTpm2LptpmChTrigger1 = 169|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN169 input. */ - kXBAR1_InputTpm2LptpmChTrigger2 = 170|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN170 input. */ - kXBAR1_InputTpm2LptpmChTrigger3 = 171|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN171 input. */ - kXBAR1_InputTpm2LptpmTrigger = 172|0x10000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR1_IN172 input. */ - kXBAR1_InputTpm3LptpmChTrigger0 = 173|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN173 input. */ - kXBAR1_InputTpm3LptpmChTrigger1 = 174|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN174 input. */ - kXBAR1_InputTpm3LptpmChTrigger2 = 175|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN175 input. */ - kXBAR1_InputTpm3LptpmChTrigger3 = 176|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN176 input. */ - kXBAR1_InputTpm3LptpmTrigger = 177|0x10000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR1_IN177 input. */ - kXBAR1_InputTpm4LptpmChTrigger0 = 178|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN178 input. */ - kXBAR1_InputTpm4LptpmChTrigger1 = 179|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN179 input. */ - kXBAR1_InputTpm4LptpmChTrigger2 = 180|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN180 input. */ - kXBAR1_InputTpm4LptpmChTrigger3 = 181|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN181 input. */ - kXBAR1_InputTpm4LptpmTrigger = 182|0x10000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR1_IN182 input. */ - kXBAR1_InputTpm5LptpmChTrigger0 = 183|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN183 input. */ - kXBAR1_InputTpm5LptpmChTrigger1 = 184|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN184 input. */ - kXBAR1_InputTpm5LptpmChTrigger2 = 185|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN185 input. */ - kXBAR1_InputTpm5LptpmChTrigger3 = 186|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN186 input. */ - kXBAR1_InputTpm5LptpmTrigger = 187|0x10000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR1_IN187 input. */ - kXBAR1_InputTpm6LptpmChTrigger0 = 188|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN188 input. */ - kXBAR1_InputTpm6LptpmChTrigger1 = 189|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN189 input. */ - kXBAR1_InputTpm6LptpmChTrigger2 = 190|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN190 input. */ - kXBAR1_InputTpm6LptpmChTrigger3 = 191|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN191 input. */ - kXBAR1_InputTpm6LptpmTrigger = 192|0x10000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR1_IN192 input. */ - kXBAR1_InputLptmr1LptimerTriggerDelay = 193|0x10000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN193 input. */ - kXBAR1_InputLptmr2LptimerTriggerDelay = 194|0x10000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN194 input. */ - kXBAR1_InputLogicLow2 = 195|0x10000U, /**< LOGIC_LOW2 output assigned to XBAR1_IN195 input. */ - kXBAR1_InputNetcTmr11588Pp1 = 196|0x10000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR1_IN196 input. */ - kXBAR1_InputNetcTmr11588Pp2 = 197|0x10000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR1_IN197 input. */ - kXBAR1_InputNetcTmr11588Pp3 = 198|0x10000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR1_IN198 input. */ - kXBAR1_InputNetcTmr11588Alarm1 = 199|0x10000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR1_IN199 input. */ - kXBAR1_InputNetcTmr11588Alarm2 = 200|0x10000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR1_IN200 input. */ - kXBAR1_InputNetcTmr21588Pp1 = 201|0x10000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR1_IN201 input. */ - kXBAR1_InputNetcTmr21588Pp2 = 202|0x10000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR1_IN202 input. */ - kXBAR1_InputNetcTmr21588Pp3 = 203|0x10000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR1_IN203 input. */ - kXBAR1_InputNetcTmr21588Alarm1 = 204|0x10000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR1_IN204 input. */ - kXBAR1_InputNetcTmr21588Alarm2 = 205|0x10000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR1_IN205 input. */ - kXBAR1_InputNetcTmr31588Pp1 = 206|0x10000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR1_IN206 input. */ - kXBAR1_InputNetcTmr31588Pp2 = 207|0x10000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR1_IN207 input. */ - kXBAR1_InputNetcTmr31588Pp3 = 208|0x10000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR1_IN208 input. */ - kXBAR1_InputNetcTmr31588Alarm1 = 209|0x10000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR1_IN209 input. */ - kXBAR1_InputNetcTmr31588Alarm2 = 210|0x10000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR1_IN210 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak0 = 211|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR1_IN211 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak1 = 212|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR1_IN212 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak2 = 213|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR1_IN213 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak3 = 214|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR1_IN214 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak0 = 215|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR1_IN215 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak1 = 216|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR1_IN216 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak2 = 217|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR1_IN217 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak3 = 218|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR1_IN218 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak0 = 219|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR1_IN219 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak1 = 220|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR1_IN220 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak2 = 221|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR1_IN221 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak3 = 222|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR1_IN222 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak0 = 223|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR1_IN223 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak1 = 224|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR1_IN224 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak2 = 225|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR1_IN225 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak3 = 226|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR1_IN226 input. */ - kXBAR1_InputAoi1AoiOut0 = 227|0x10000U, /**< AOI1_AOI_OUT0 output assigned to XBAR1_IN227 input. */ - kXBAR1_InputAoi1AoiOut1 = 228|0x10000U, /**< AOI1_AOI_OUT1 output assigned to XBAR1_IN228 input. */ - kXBAR1_InputAoi1AoiOut2 = 229|0x10000U, /**< AOI1_AOI_OUT2 output assigned to XBAR1_IN229 input. */ - kXBAR1_InputAoi1AoiOut3 = 230|0x10000U, /**< AOI1_AOI_OUT3 output assigned to XBAR1_IN230 input. */ - kXBAR1_InputAoi2AoiOut0 = 231|0x10000U, /**< AOI2_AOI_OUT0 output assigned to XBAR1_IN231 input. */ - kXBAR1_InputAoi2AoiOut1 = 232|0x10000U, /**< AOI2_AOI_OUT1 output assigned to XBAR1_IN232 input. */ - kXBAR1_InputAoi2AoiOut2 = 233|0x10000U, /**< AOI2_AOI_OUT2 output assigned to XBAR1_IN233 input. */ - kXBAR1_InputAoi2AoiOut3 = 234|0x10000U, /**< AOI2_AOI_OUT3 output assigned to XBAR1_IN234 input. */ - kXBAR1_InputTriggerSyncSyncOut4 = 235|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT4 output assigned to XBAR1_IN235 input. */ - kXBAR1_InputTriggerSyncSyncOut5 = 236|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT5 output assigned to XBAR1_IN236 input. */ - kXBAR1_InputTriggerSyncSyncOut6 = 237|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT6 output assigned to XBAR1_IN237 input. */ - kXBAR1_InputTriggerSyncSyncOut7 = 238|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT7 output assigned to XBAR1_IN238 input. */ - kXBAR1_InputAoi3AoiOut0 = 239|0x10000U, /**< AOI3_AOI_OUT0 output assigned to XBAR1_IN239 input. */ - kXBAR1_InputAoi3AoiOut1 = 240|0x10000U, /**< AOI3_AOI_OUT1 output assigned to XBAR1_IN240 input. */ - kXBAR1_InputAoi3AoiOut2 = 241|0x10000U, /**< AOI3_AOI_OUT2 output assigned to XBAR1_IN241 input. */ - kXBAR1_InputAoi3AoiOut3 = 242|0x10000U, /**< AOI3_AOI_OUT3 output assigned to XBAR1_IN242 input. */ - kXBAR1_InputAoi4AoiOut0 = 243|0x10000U, /**< AOI4_AOI_OUT0 output assigned to XBAR1_IN243 input. */ - kXBAR1_InputAoi4AoiOut1 = 244|0x10000U, /**< AOI4_AOI_OUT1 output assigned to XBAR1_IN244 input. */ - kXBAR1_InputAoi4AoiOut2 = 245|0x10000U, /**< AOI4_AOI_OUT2 output assigned to XBAR1_IN245 input. */ - kXBAR1_InputAoi4AoiOut3 = 246|0x10000U, /**< AOI4_AOI_OUT3 output assigned to XBAR1_IN246 input. */ - kXBAR1_InputEcatSyncOut0 = 247|0x10000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR1_IN247 input. */ - kXBAR1_InputEcatSyncOut1 = 248|0x10000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR1_IN248 input. */ - kXBAR1_InputFccuVfccuReactionsOut11 = 249|0x10000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR1_IN249 input. */ - kXBAR1_InputGpt1IppDoCmpout1 = 250|0x10000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR1_IN250 input. */ - kXBAR1_InputGpt1IppDoCmpout2 = 251|0x10000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR1_IN251 input. */ - kXBAR1_InputGpt1IppDoCmpout3 = 252|0x10000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR1_IN252 input. */ - kXBAR1_InputGpt2IppDoCmpout1 = 253|0x10000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR1_IN253 input. */ - kXBAR1_InputGpt2IppDoCmpout2 = 254|0x10000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR1_IN254 input. */ - kXBAR1_InputGpt2IppDoCmpout3 = 255|0x10000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR1_IN255 input. */ - kXBAR1_InputGpt3IppDoCmpout1 = 256|0x10000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR1_IN256 input. */ - kXBAR1_InputGpt3IppDoCmpout2 = 257|0x10000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR1_IN257 input. */ - kXBAR1_InputGpt3IppDoCmpout3 = 258|0x10000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR1_IN258 input. */ - kXBAR1_InputGpt4IppDoCmpout1 = 259|0x10000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR1_IN259 input. */ - kXBAR1_InputGpt4IppDoCmpout2 = 260|0x10000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR1_IN260 input. */ - kXBAR1_InputGpt4IppDoCmpout3 = 261|0x10000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR1_IN261 input. */ - kXBAR1_InputFlexio1FlexioTriggerOut0 = 262|0x10000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN262 input. */ - kXBAR1_InputFlexio2FlexioTriggerOut0 = 263|0x10000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN263 input. */ - kXBAR1_InputFlexio3FlexioTriggerOut0 = 264|0x10000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN264 input. */ - kXBAR1_InputFlexio4FlexioTriggerOut0 = 265|0x10000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN265 input. */ - kXBAR1_InputGpio1IpiIntRgpio0 = 266|0x10000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR1_IN266 input. */ - kXBAR1_InputGpio2IpiIntRgpio0 = 267|0x10000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR1_IN267 input. */ - kXBAR1_InputGpio3IpiIntRgpio0 = 268|0x10000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR1_IN268 input. */ - kXBAR1_InputGpio4IpiIntRgpio0 = 269|0x10000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR1_IN269 input. */ - kXBAR1_InputGpio5IpiIntRgpio0 = 270|0x10000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR1_IN270 input. */ - kXBAR1_InputGpio6IpiIntRgpio0 = 271|0x10000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR1_IN271 input. */ - kXBAR1_InputGpio7IpiIntRgpio0 = 272|0x10000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR1_IN272 input. */ - kXBAR1_InputCm33Txev = 273|0x10000U, /**< CM33_TXEV output assigned to XBAR1_IN273 input. */ - kXBAR1_InputCm33SyncTxev = 274|0x10000U, /**< CM33_SYNC_TXEV output assigned to XBAR1_IN274 input. */ - kXBAR1_InputEndat21SiN = 275|0x10000U, /**< ENDAT2_1_SI_N output assigned to XBAR1_IN275 input. */ - kXBAR1_InputEndat21TimerN = 276|0x10000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR1_IN276 input. */ - kXBAR1_InputEndat22SiN = 277|0x10000U, /**< ENDAT2_2_SI_N output assigned to XBAR1_IN277 input. */ - kXBAR1_InputEndat22TimerN = 278|0x10000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR1_IN278 input. */ - kXBAR1_InputBissEot = 279|0x10000U, /**< BISS_EOT output assigned to XBAR1_IN279 input. */ - kXBAR1_InputTriggerSyncSyncOut8 = 280|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT8 output assigned to XBAR1_IN280 input. */ - kXBAR1_InputTriggerSyncSyncOut9 = 281|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT9 output assigned to XBAR1_IN281 input. */ - kXBAR1_InputTriggerSyncSyncOut10 = 282|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT10 output assigned to XBAR1_IN282 input. */ - kXBAR1_InputTriggerSyncSyncOut11 = 283|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT11 output assigned to XBAR1_IN283 input. */ - kXBAR1_InputTriggerSyncSyncOut12 = 284|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT12 output assigned to XBAR1_IN284 input. */ - kXBAR1_InputTriggerSyncSyncOut13 = 285|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT13 output assigned to XBAR1_IN285 input. */ - kXBAR1_InputTriggerSyncSyncOut14 = 286|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT14 output assigned to XBAR1_IN286 input. */ - kXBAR1_InputTriggerSyncSyncOut15 = 287|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT15 output assigned to XBAR1_IN287 input. */ - kXBAR1_InputEcatResetOut = 288|0x10000U, /**< ECAT_RESET_OUT output assigned to XBAR1_IN288 input. */ - kXBAR1_InputHiperface1FastPosRcvdEvt = 289|0x10000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR1_IN289 input. */ - kXBAR1_InputHiperface2FastPosRcvdEvt = 290|0x10000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR1_IN290 input. */ - kXBAR2_InputLogicLow = 0|0x20000U, /**< LOGIC_LOW output assigned to XBAR2_IN0 input. */ - kXBAR2_InputLogicHigh = 1|0x20000U, /**< LOGIC_HIGH output assigned to XBAR2_IN1 input. */ - kXBAR2_InputLogicLow1 = 2|0x20000U, /**< LOGIC_LOW1 output assigned to XBAR2_IN2 input. */ - kXBAR2_InputLogicHigh1 = 3|0x20000U, /**< LOGIC_HIGH1 output assigned to XBAR2_IN3 input. */ - kXBAR2_InputQtimer1Timer0 = 4|0x20000U, /**< QTIMER1_TIMER0 output assigned to XBAR2_IN4 input. */ - kXBAR2_InputQtimer1Timer1 = 5|0x20000U, /**< QTIMER1_TIMER1 output assigned to XBAR2_IN5 input. */ - kXBAR2_InputQtimer1Timer2 = 6|0x20000U, /**< QTIMER1_TIMER2 output assigned to XBAR2_IN6 input. */ - kXBAR2_InputQtimer1Timer3 = 7|0x20000U, /**< QTIMER1_TIMER3 output assigned to XBAR2_IN7 input. */ - kXBAR2_InputQtimer2Timer0 = 8|0x20000U, /**< QTIMER2_TIMER0 output assigned to XBAR2_IN8 input. */ - kXBAR2_InputQtimer2Timer1 = 9|0x20000U, /**< QTIMER2_TIMER1 output assigned to XBAR2_IN9 input. */ - kXBAR2_InputQtimer2Timer2 = 10|0x20000U, /**< QTIMER2_TIMER2 output assigned to XBAR2_IN10 input. */ - kXBAR2_InputQtimer2Timer3 = 11|0x20000U, /**< QTIMER2_TIMER3 output assigned to XBAR2_IN11 input. */ - kXBAR2_InputQtimer3Timer0 = 12|0x20000U, /**< QTIMER3_TIMER0 output assigned to XBAR2_IN12 input. */ - kXBAR2_InputQtimer3Timer1 = 13|0x20000U, /**< QTIMER3_TIMER1 output assigned to XBAR2_IN13 input. */ - kXBAR2_InputQtimer3Timer2 = 14|0x20000U, /**< QTIMER3_TIMER2 output assigned to XBAR2_IN14 input. */ - kXBAR2_InputQtimer3Timer3 = 15|0x20000U, /**< QTIMER3_TIMER3 output assigned to XBAR2_IN15 input. */ - kXBAR2_InputQtimer4Timer0 = 16|0x20000U, /**< QTIMER4_TIMER0 output assigned to XBAR2_IN16 input. */ - kXBAR2_InputQtimer4Timer1 = 17|0x20000U, /**< QTIMER4_TIMER1 output assigned to XBAR2_IN17 input. */ - kXBAR2_InputQtimer4Timer2 = 18|0x20000U, /**< QTIMER4_TIMER2 output assigned to XBAR2_IN18 input. */ - kXBAR2_InputQtimer4Timer3 = 19|0x20000U, /**< QTIMER4_TIMER3 output assigned to XBAR2_IN19 input. */ - kXBAR2_InputQtimer5Timer0 = 20|0x20000U, /**< QTIMER5_TIMER0 output assigned to XBAR2_IN20 input. */ - kXBAR2_InputQtimer5Timer1 = 21|0x20000U, /**< QTIMER5_TIMER1 output assigned to XBAR2_IN21 input. */ - kXBAR2_InputQtimer5Timer2 = 22|0x20000U, /**< QTIMER5_TIMER2 output assigned to XBAR2_IN22 input. */ - kXBAR2_InputQtimer5Timer3 = 23|0x20000U, /**< QTIMER5_TIMER3 output assigned to XBAR2_IN23 input. */ - kXBAR2_InputQtimer6Timer0 = 24|0x20000U, /**< QTIMER6_TIMER0 output assigned to XBAR2_IN24 input. */ - kXBAR2_InputQtimer6Timer1 = 25|0x20000U, /**< QTIMER6_TIMER1 output assigned to XBAR2_IN25 input. */ - kXBAR2_InputQtimer6Timer2 = 26|0x20000U, /**< QTIMER6_TIMER2 output assigned to XBAR2_IN26 input. */ - kXBAR2_InputQtimer6Timer3 = 27|0x20000U, /**< QTIMER6_TIMER3 output assigned to XBAR2_IN27 input. */ - kXBAR2_InputQtimer7Timer0 = 28|0x20000U, /**< QTIMER7_TIMER0 output assigned to XBAR2_IN28 input. */ - kXBAR2_InputQtimer7Timer1 = 29|0x20000U, /**< QTIMER7_TIMER1 output assigned to XBAR2_IN29 input. */ - kXBAR2_InputQtimer7Timer2 = 30|0x20000U, /**< QTIMER7_TIMER2 output assigned to XBAR2_IN30 input. */ - kXBAR2_InputQtimer7Timer3 = 31|0x20000U, /**< QTIMER7_TIMER3 output assigned to XBAR2_IN31 input. */ - kXBAR2_InputQtimer8Timer0 = 32|0x20000U, /**< QTIMER8_TIMER0 output assigned to XBAR2_IN32 input. */ - kXBAR2_InputQtimer8Timer1 = 33|0x20000U, /**< QTIMER8_TIMER1 output assigned to XBAR2_IN33 input. */ - kXBAR2_InputQtimer8Timer2 = 34|0x20000U, /**< QTIMER8_TIMER2 output assigned to XBAR2_IN34 input. */ - kXBAR2_InputQtimer8Timer3 = 35|0x20000U, /**< QTIMER8_TIMER3 output assigned to XBAR2_IN35 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger0 = 36|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR2_IN36 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger1 = 37|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR2_IN37 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger2 = 38|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR2_IN38 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger3 = 39|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR2_IN39 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger0 = 40|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR2_IN40 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger1 = 41|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR2_IN41 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger2 = 42|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR2_IN42 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger3 = 43|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR2_IN43 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger0 = 44|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR2_IN44 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger1 = 45|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR2_IN45 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger2 = 46|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR2_IN46 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger3 = 47|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR2_IN47 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger0 = 48|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR2_IN48 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger1 = 49|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR2_IN49 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger2 = 50|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR2_IN50 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger3 = 51|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR2_IN51 input. */ - kXBAR2_InputLpit1LpitTrigOut0 = 52|0x20000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR2_IN52 input. */ - kXBAR2_InputLpit1LpitTrigOut1 = 53|0x20000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR2_IN53 input. */ - kXBAR2_InputLpit1LpitTrigOut2 = 54|0x20000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR2_IN54 input. */ - kXBAR2_InputLpit1LpitTrigOut3 = 55|0x20000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR2_IN55 input. */ - kXBAR2_InputLpit2LpitTrigOut0 = 56|0x20000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR2_IN56 input. */ - kXBAR2_InputLpit2LpitTrigOut1 = 57|0x20000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR2_IN57 input. */ - kXBAR2_InputLpit2LpitTrigOut2 = 58|0x20000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR2_IN58 input. */ - kXBAR2_InputLpit2LpitTrigOut3 = 59|0x20000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR2_IN59 input. */ - kXBAR2_InputLpit3LpitTrigOut0 = 60|0x20000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR2_IN60 input. */ - kXBAR2_InputLpit3LpitTrigOut1 = 61|0x20000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR2_IN61 input. */ - kXBAR2_InputLpit3LpitTrigOut2 = 62|0x20000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR2_IN62 input. */ - kXBAR2_InputLpit3LpitTrigOut3 = 63|0x20000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR2_IN63 input. */ - kXBAR2_InputEdma2DmaTriggerOut0 = 64|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN64 input. */ - kXBAR2_InputEdma2DmaTriggerOut1 = 65|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN65 input. */ - kXBAR2_InputEdma2DmaTriggerOut2 = 66|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN66 input. */ - kXBAR2_InputEdma2DmaTriggerOut3 = 67|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN67 input. */ - kXBAR2_InputEdma2DmaTriggerOut4 = 68|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN68 input. */ - kXBAR2_InputEdma2DmaTriggerOut5 = 69|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN69 input. */ - kXBAR2_InputEdma2DmaTriggerOut6 = 70|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN70 input. */ - kXBAR2_InputEdma2DmaTriggerOut7 = 71|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN71 input. */ - kXBAR2_InputEdma1DmaTriggerOut0 = 72|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN72 input. */ - kXBAR2_InputEdma1DmaTriggerOut1 = 73|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN73 input. */ - kXBAR2_InputEdma1DmaTriggerOut2 = 74|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN74 input. */ - kXBAR2_InputEdma1DmaTriggerOut3 = 75|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN75 input. */ - kXBAR2_InputEdma1DmaTriggerOut4 = 76|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN76 input. */ - kXBAR2_InputEdma1DmaTriggerOut5 = 77|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN77 input. */ - kXBAR2_InputEdma1DmaTriggerOut6 = 78|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN78 input. */ - kXBAR2_InputEdma1DmaTriggerOut7 = 79|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN79 input. */ - kXBAR2_InputEdma3DmaTriggerOut0 = 80|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN80 input. */ - kXBAR2_InputEdma3DmaTriggerOut1 = 81|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN81 input. */ - kXBAR2_InputEdma3DmaTriggerOut2 = 82|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN82 input. */ - kXBAR2_InputEdma3DmaTriggerOut3 = 83|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN83 input. */ - kXBAR2_InputEdma3DmaTriggerOut4 = 84|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN84 input. */ - kXBAR2_InputEdma3DmaTriggerOut5 = 85|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN85 input. */ - kXBAR2_InputEdma3DmaTriggerOut6 = 86|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN86 input. */ - kXBAR2_InputEdma3DmaTriggerOut7 = 87|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN87 input. */ - kXBAR2_InputEdma4DmaTriggerOut0 = 88|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN88 input. */ - kXBAR2_InputEdma4DmaTriggerOut1 = 89|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN89 input. */ - kXBAR2_InputEdma4DmaTriggerOut2 = 90|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN90 input. */ - kXBAR2_InputEdma4DmaTriggerOut3 = 91|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN91 input. */ - kXBAR2_InputEdma4DmaTriggerOut4 = 92|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN92 input. */ - kXBAR2_InputEdma4DmaTriggerOut5 = 93|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN93 input. */ - kXBAR2_InputEdma4DmaTriggerOut6 = 94|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN94 input. */ - kXBAR2_InputEdma4DmaTriggerOut7 = 95|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN95 input. */ - kXBAR2_InputAdc1IpiIntEoc = 96|0x20000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR2_IN96 input. */ - kXBAR2_InputAdc1IpiIntWd = 97|0x20000U, /**< ADC1_IPI_INT_WD output assigned to XBAR2_IN97 input. */ - kXBAR2_InputTpm1LptpmChTrigger0 = 98|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN98 input. */ - kXBAR2_InputTpm1LptpmChTrigger1 = 99|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN99 input. */ - kXBAR2_InputTpm1LptpmChTrigger2 = 100|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN100 input. */ - kXBAR2_InputTpm1LptpmChTrigger3 = 101|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN101 input. */ - kXBAR2_InputTpm1LptpmTrigger = 102|0x20000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR2_IN102 input. */ - kXBAR2_InputTpm2LptpmChTrigger0 = 103|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN103 input. */ - kXBAR2_InputTpm2LptpmChTrigger1 = 104|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN104 input. */ - kXBAR2_InputTpm2LptpmChTrigger2 = 105|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN105 input. */ - kXBAR2_InputTpm2LptpmChTrigger3 = 106|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN106 input. */ - kXBAR2_InputTpm2LptpmTrigger = 107|0x20000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR2_IN107 input. */ - kXBAR2_InputTpm3LptpmChTrigger0 = 108|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN108 input. */ - kXBAR2_InputTpm3LptpmChTrigger1 = 109|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN109 input. */ - kXBAR2_InputTpm3LptpmChTrigger2 = 110|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN110 input. */ - kXBAR2_InputTpm3LptpmChTrigger3 = 111|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN111 input. */ - kXBAR2_InputTpm3LptpmTrigger = 112|0x20000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR2_IN112 input. */ - kXBAR2_InputTpm4LptpmChTrigger0 = 113|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN113 input. */ - kXBAR2_InputTpm4LptpmChTrigger1 = 114|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN114 input. */ - kXBAR2_InputTpm4LptpmChTrigger2 = 115|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN115 input. */ - kXBAR2_InputTpm4LptpmChTrigger3 = 116|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN116 input. */ - kXBAR2_InputTpm4LptpmTrigger = 117|0x20000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR2_IN117 input. */ - kXBAR2_InputTpm5LptpmChTrigger0 = 118|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN118 input. */ - kXBAR2_InputTpm5LptpmChTrigger1 = 119|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN119 input. */ - kXBAR2_InputTpm5LptpmChTrigger2 = 120|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN120 input. */ - kXBAR2_InputTpm5LptpmChTrigger3 = 121|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN121 input. */ - kXBAR2_InputTpm5LptpmTrigger = 122|0x20000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR2_IN122 input. */ - kXBAR2_InputTpm6LptpmChTrigger0 = 123|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN123 input. */ - kXBAR2_InputTpm6LptpmChTrigger1 = 124|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN124 input. */ - kXBAR2_InputTpm6LptpmChTrigger2 = 125|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN125 input. */ - kXBAR2_InputTpm6LptpmChTrigger3 = 126|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN126 input. */ - kXBAR2_InputTpm6LptpmTrigger = 127|0x20000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR2_IN127 input. */ - kXBAR2_InputLptmr1LptimerTriggerDelay = 128|0x20000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN128 input. */ - kXBAR2_InputLptmr2LptimerTriggerDelay = 129|0x20000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN129 input. */ - kXBAR2_InputLogicLow2 = 130|0x20000U, /**< LOGIC_LOW2 output assigned to XBAR2_IN130 input. */ - kXBAR2_InputNetcTmr11588Pp1 = 131|0x20000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR2_IN131 input. */ - kXBAR2_InputNetcTmr11588Pp2 = 132|0x20000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR2_IN132 input. */ - kXBAR2_InputNetcTmr11588Pp3 = 133|0x20000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR2_IN133 input. */ - kXBAR2_InputNetcTmr11588Alarm1 = 134|0x20000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR2_IN134 input. */ - kXBAR2_InputNetcTmr11588Alarm2 = 135|0x20000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR2_IN135 input. */ - kXBAR2_InputNetcTmr21588Pp1 = 136|0x20000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR2_IN136 input. */ - kXBAR2_InputNetcTmr21588Pp2 = 137|0x20000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR2_IN137 input. */ - kXBAR2_InputNetcTmr21588Pp3 = 138|0x20000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR2_IN138 input. */ - kXBAR2_InputNetcTmr21588Alarm1 = 139|0x20000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR2_IN139 input. */ - kXBAR2_InputNetcTmr21588Alarm2 = 140|0x20000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR2_IN140 input. */ - kXBAR2_InputNetcTmr31588Pp1 = 141|0x20000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR2_IN141 input. */ - kXBAR2_InputNetcTmr31588Pp2 = 142|0x20000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR2_IN142 input. */ - kXBAR2_InputNetcTmr31588Pp3 = 143|0x20000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR2_IN143 input. */ - kXBAR2_InputNetcTmr31588Alarm1 = 144|0x20000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR2_IN144 input. */ - kXBAR2_InputNetcTmr31588Alarm2 = 145|0x20000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR2_IN145 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak0 = 146|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR2_IN146 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak1 = 147|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR2_IN147 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak2 = 148|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR2_IN148 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak3 = 149|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR2_IN149 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak0 = 150|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR2_IN150 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak1 = 151|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR2_IN151 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak2 = 152|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR2_IN152 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak3 = 153|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR2_IN153 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak0 = 154|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR2_IN154 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak1 = 155|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR2_IN155 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak2 = 156|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR2_IN156 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak3 = 157|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR2_IN157 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak0 = 158|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR2_IN158 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak1 = 159|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR2_IN159 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak2 = 160|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR2_IN160 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak3 = 161|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR2_IN161 input. */ - kXBAR2_InputSinc1PulseTrg0 = 162|0x20000U, /**< SINC1_PULSE_TRG0 output assigned to XBAR2_IN162 input. */ - kXBAR2_InputSinc1PulseTrg1 = 163|0x20000U, /**< SINC1_PULSE_TRG1 output assigned to XBAR2_IN163 input. */ - kXBAR2_InputSinc1PulseTrg2 = 164|0x20000U, /**< SINC1_PULSE_TRG2 output assigned to XBAR2_IN164 input. */ - kXBAR2_InputSinc1PulseTrg3 = 165|0x20000U, /**< SINC1_PULSE_TRG3 output assigned to XBAR2_IN165 input. */ - kXBAR2_InputSinc3PulseTrg0 = 166|0x20000U, /**< SINC3_PULSE_TRG0 output assigned to XBAR2_IN166 input. */ - kXBAR2_InputSinc3PulseTrg1 = 167|0x20000U, /**< SINC3_PULSE_TRG1 output assigned to XBAR2_IN167 input. */ - kXBAR2_InputSinc3PulseTrg2 = 168|0x20000U, /**< SINC3_PULSE_TRG2 output assigned to XBAR2_IN168 input. */ - kXBAR2_InputSinc3PulseTrg3 = 169|0x20000U, /**< SINC3_PULSE_TRG3 output assigned to XBAR2_IN169 input. */ - kXBAR2_InputEcatSyncOut0 = 170|0x20000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR2_IN170 input. */ - kXBAR2_InputEcatSyncOut1 = 171|0x20000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR2_IN171 input. */ - kXBAR2_InputFccuVfccuReactionsOut11 = 172|0x20000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR2_IN172 input. */ - kXBAR2_InputGpt1IppDoCmpout1 = 173|0x20000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR2_IN173 input. */ - kXBAR2_InputGpt1IppDoCmpout2 = 174|0x20000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR2_IN174 input. */ - kXBAR2_InputGpt1IppDoCmpout3 = 175|0x20000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR2_IN175 input. */ - kXBAR2_InputGpt2IppDoCmpout1 = 176|0x20000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR2_IN176 input. */ - kXBAR2_InputGpt2IppDoCmpout2 = 177|0x20000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR2_IN177 input. */ - kXBAR2_InputGpt2IppDoCmpout3 = 178|0x20000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR2_IN178 input. */ - kXBAR2_InputGpt3IppDoCmpout1 = 179|0x20000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR2_IN179 input. */ - kXBAR2_InputGpt3IppDoCmpout2 = 180|0x20000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR2_IN180 input. */ - kXBAR2_InputGpt3IppDoCmpout3 = 181|0x20000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR2_IN181 input. */ - kXBAR2_InputGpt4IppDoCmpout1 = 182|0x20000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR2_IN182 input. */ - kXBAR2_InputGpt4IppDoCmpout2 = 183|0x20000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR2_IN183 input. */ - kXBAR2_InputGpt4IppDoCmpout3 = 184|0x20000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR2_IN184 input. */ - kXBAR2_InputFlexio1FlexioTriggerOut0 = 185|0x20000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN185 input. */ - kXBAR2_InputFlexio2FlexioTriggerOut0 = 186|0x20000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN186 input. */ - kXBAR2_InputFlexio3FlexioTriggerOut0 = 187|0x20000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN187 input. */ - kXBAR2_InputFlexio4FlexioTriggerOut0 = 188|0x20000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN188 input. */ - kXBAR2_InputGpio1IpiIntRgpio0 = 189|0x20000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR2_IN189 input. */ - kXBAR2_InputGpio2IpiIntRgpio0 = 190|0x20000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR2_IN190 input. */ - kXBAR2_InputGpio3IpiIntRgpio0 = 191|0x20000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR2_IN191 input. */ - kXBAR2_InputGpio4IpiIntRgpio0 = 192|0x20000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR2_IN192 input. */ - kXBAR2_InputGpio5IpiIntRgpio0 = 193|0x20000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR2_IN193 input. */ - kXBAR2_InputGpio6IpiIntRgpio0 = 194|0x20000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR2_IN194 input. */ - kXBAR2_InputGpio7IpiIntRgpio0 = 195|0x20000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR2_IN195 input. */ - kXBAR2_InputCm33Txev = 196|0x20000U, /**< CM33_TXEV output assigned to XBAR2_IN196 input. */ - kXBAR2_InputCm33SyncTxev = 197|0x20000U, /**< CM33_SYNC_TXEV output assigned to XBAR2_IN197 input. */ - kXBAR2_InputEndat21SiN = 198|0x20000U, /**< ENDAT2_1_SI_N output assigned to XBAR2_IN198 input. */ - kXBAR2_InputEndat21TimerN = 199|0x20000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR2_IN199 input. */ - kXBAR2_InputEndat22SiN = 200|0x20000U, /**< ENDAT2_2_SI_N output assigned to XBAR2_IN200 input. */ - kXBAR2_InputEndat22TimerN = 201|0x20000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR2_IN201 input. */ - kXBAR2_InputBissEot = 202|0x20000U, /**< BISS_EOT output assigned to XBAR2_IN202 input. */ - kXBAR2_InputEnc1PosMatch0 = 203|0x20000U, /**< ENC1_POS_MATCH0 output assigned to XBAR2_IN203 input. */ - kXBAR2_InputEnc1PosMatch1 = 204|0x20000U, /**< ENC1_POS_MATCH1 output assigned to XBAR2_IN204 input. */ - kXBAR2_InputEnc1PosMatch2 = 205|0x20000U, /**< ENC1_POS_MATCH2 output assigned to XBAR2_IN205 input. */ - kXBAR2_InputEnc1PosMatch3 = 206|0x20000U, /**< ENC1_POS_MATCH3 output assigned to XBAR2_IN206 input. */ - kXBAR2_InputEnc1CompFlg0 = 207|0x20000U, /**< ENC1_COMP_FLG0 output assigned to XBAR2_IN207 input. */ - kXBAR2_InputEnc1CompFlg1 = 208|0x20000U, /**< ENC1_COMP_FLG1 output assigned to XBAR2_IN208 input. */ - kXBAR2_InputEnc1CompFlg2 = 209|0x20000U, /**< ENC1_COMP_FLG2 output assigned to XBAR2_IN209 input. */ - kXBAR2_InputEnc1CompFlg3 = 210|0x20000U, /**< ENC1_COMP_FLG3 output assigned to XBAR2_IN210 input. */ - kXBAR2_InputEnc1CntDn = 211|0x20000U, /**< ENC1_CNT_DN output assigned to XBAR2_IN211 input. */ - kXBAR2_InputEnc1CntUp = 212|0x20000U, /**< ENC1_CNT_UP output assigned to XBAR2_IN212 input. */ - kXBAR2_InputEnc1Dir = 213|0x20000U, /**< ENC1_DIR output assigned to XBAR2_IN213 input. */ - kXBAR2_InputEnc3PosMatch0 = 214|0x20000U, /**< ENC3_POS_MATCH0 output assigned to XBAR2_IN214 input. */ - kXBAR2_InputEnc3PosMatch1 = 215|0x20000U, /**< ENC3_POS_MATCH1 output assigned to XBAR2_IN215 input. */ - kXBAR2_InputEnc3PosMatch2 = 216|0x20000U, /**< ENC3_POS_MATCH2 output assigned to XBAR2_IN216 input. */ - kXBAR2_InputEnc3PosMatch3 = 217|0x20000U, /**< ENC3_POS_MATCH3 output assigned to XBAR2_IN217 input. */ - kXBAR2_InputEnc3CompFlg0 = 218|0x20000U, /**< ENC3_COMP_FLG0 output assigned to XBAR2_IN218 input. */ - kXBAR2_InputEnc3CompFlg1 = 219|0x20000U, /**< ENC3_COMP_FLG1 output assigned to XBAR2_IN219 input. */ - kXBAR2_InputEnc3CompFlg2 = 220|0x20000U, /**< ENC3_COMP_FLG2 output assigned to XBAR2_IN220 input. */ - kXBAR2_InputEnc3CompFlg3 = 221|0x20000U, /**< ENC3_COMP_FLG3 output assigned to XBAR2_IN221 input. */ - kXBAR2_InputEnc3CntDn = 222|0x20000U, /**< ENC3_CNT_DN output assigned to XBAR2_IN222 input. */ - kXBAR2_InputEnc3CntUp = 223|0x20000U, /**< ENC3_CNT_UP output assigned to XBAR2_IN223 input. */ - kXBAR2_InputEnc3Dir = 224|0x20000U, /**< ENC3_DIR output assigned to XBAR2_IN224 input. */ - kXBAR2_InputHiperface1FastPosRcvdEvt = 225|0x20000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR2_IN225 input. */ - kXBAR2_InputHiperface2FastPosRcvdEvt = 226|0x20000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR2_IN226 input. */ - kXBAR3_InputLogicLow = 0|0x30000U, /**< LOGIC_LOW output assigned to XBAR3_IN0 input. */ - kXBAR3_InputLogicHigh = 1|0x30000U, /**< LOGIC_HIGH output assigned to XBAR3_IN1 input. */ - kXBAR3_InputLogicLow1 = 2|0x30000U, /**< LOGIC_LOW1 output assigned to XBAR3_IN2 input. */ - kXBAR3_InputLogicHigh1 = 3|0x30000U, /**< LOGIC_HIGH1 output assigned to XBAR3_IN3 input. */ - kXBAR3_InputQtimer1Timer0 = 4|0x30000U, /**< QTIMER1_TIMER0 output assigned to XBAR3_IN4 input. */ - kXBAR3_InputQtimer1Timer1 = 5|0x30000U, /**< QTIMER1_TIMER1 output assigned to XBAR3_IN5 input. */ - kXBAR3_InputQtimer1Timer2 = 6|0x30000U, /**< QTIMER1_TIMER2 output assigned to XBAR3_IN6 input. */ - kXBAR3_InputQtimer1Timer3 = 7|0x30000U, /**< QTIMER1_TIMER3 output assigned to XBAR3_IN7 input. */ - kXBAR3_InputQtimer2Timer0 = 8|0x30000U, /**< QTIMER2_TIMER0 output assigned to XBAR3_IN8 input. */ - kXBAR3_InputQtimer2Timer1 = 9|0x30000U, /**< QTIMER2_TIMER1 output assigned to XBAR3_IN9 input. */ - kXBAR3_InputQtimer2Timer2 = 10|0x30000U, /**< QTIMER2_TIMER2 output assigned to XBAR3_IN10 input. */ - kXBAR3_InputQtimer2Timer3 = 11|0x30000U, /**< QTIMER2_TIMER3 output assigned to XBAR3_IN11 input. */ - kXBAR3_InputQtimer3Timer0 = 12|0x30000U, /**< QTIMER3_TIMER0 output assigned to XBAR3_IN12 input. */ - kXBAR3_InputQtimer3Timer1 = 13|0x30000U, /**< QTIMER3_TIMER1 output assigned to XBAR3_IN13 input. */ - kXBAR3_InputQtimer3Timer2 = 14|0x30000U, /**< QTIMER3_TIMER2 output assigned to XBAR3_IN14 input. */ - kXBAR3_InputQtimer3Timer3 = 15|0x30000U, /**< QTIMER3_TIMER3 output assigned to XBAR3_IN15 input. */ - kXBAR3_InputQtimer4Timer0 = 16|0x30000U, /**< QTIMER4_TIMER0 output assigned to XBAR3_IN16 input. */ - kXBAR3_InputQtimer4Timer1 = 17|0x30000U, /**< QTIMER4_TIMER1 output assigned to XBAR3_IN17 input. */ - kXBAR3_InputQtimer4Timer2 = 18|0x30000U, /**< QTIMER4_TIMER2 output assigned to XBAR3_IN18 input. */ - kXBAR3_InputQtimer4Timer3 = 19|0x30000U, /**< QTIMER4_TIMER3 output assigned to XBAR3_IN19 input. */ - kXBAR3_InputQtimer5Timer0 = 20|0x30000U, /**< QTIMER5_TIMER0 output assigned to XBAR3_IN20 input. */ - kXBAR3_InputQtimer5Timer1 = 21|0x30000U, /**< QTIMER5_TIMER1 output assigned to XBAR3_IN21 input. */ - kXBAR3_InputQtimer5Timer2 = 22|0x30000U, /**< QTIMER5_TIMER2 output assigned to XBAR3_IN22 input. */ - kXBAR3_InputQtimer5Timer3 = 23|0x30000U, /**< QTIMER5_TIMER3 output assigned to XBAR3_IN23 input. */ - kXBAR3_InputQtimer6Timer0 = 24|0x30000U, /**< QTIMER6_TIMER0 output assigned to XBAR3_IN24 input. */ - kXBAR3_InputQtimer6Timer1 = 25|0x30000U, /**< QTIMER6_TIMER1 output assigned to XBAR3_IN25 input. */ - kXBAR3_InputQtimer6Timer2 = 26|0x30000U, /**< QTIMER6_TIMER2 output assigned to XBAR3_IN26 input. */ - kXBAR3_InputQtimer6Timer3 = 27|0x30000U, /**< QTIMER6_TIMER3 output assigned to XBAR3_IN27 input. */ - kXBAR3_InputQtimer7Timer0 = 28|0x30000U, /**< QTIMER7_TIMER0 output assigned to XBAR3_IN28 input. */ - kXBAR3_InputQtimer7Timer1 = 29|0x30000U, /**< QTIMER7_TIMER1 output assigned to XBAR3_IN29 input. */ - kXBAR3_InputQtimer7Timer2 = 30|0x30000U, /**< QTIMER7_TIMER2 output assigned to XBAR3_IN30 input. */ - kXBAR3_InputQtimer7Timer3 = 31|0x30000U, /**< QTIMER7_TIMER3 output assigned to XBAR3_IN31 input. */ - kXBAR3_InputQtimer8Timer0 = 32|0x30000U, /**< QTIMER8_TIMER0 output assigned to XBAR3_IN32 input. */ - kXBAR3_InputQtimer8Timer1 = 33|0x30000U, /**< QTIMER8_TIMER1 output assigned to XBAR3_IN33 input. */ - kXBAR3_InputQtimer8Timer2 = 34|0x30000U, /**< QTIMER8_TIMER2 output assigned to XBAR3_IN34 input. */ - kXBAR3_InputQtimer8Timer3 = 35|0x30000U, /**< QTIMER8_TIMER3 output assigned to XBAR3_IN35 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger0 = 36|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR3_IN36 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger1 = 37|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR3_IN37 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger2 = 38|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR3_IN38 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger3 = 39|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR3_IN39 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger0 = 40|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR3_IN40 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger1 = 41|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR3_IN41 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger2 = 42|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR3_IN42 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger3 = 43|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR3_IN43 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger0 = 44|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR3_IN44 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger1 = 45|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR3_IN45 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger2 = 46|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR3_IN46 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger3 = 47|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR3_IN47 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger0 = 48|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR3_IN48 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger1 = 49|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR3_IN49 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger2 = 50|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR3_IN50 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger3 = 51|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR3_IN51 input. */ - kXBAR3_InputLpit1LpitTrigOut0 = 52|0x30000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR3_IN52 input. */ - kXBAR3_InputLpit1LpitTrigOut1 = 53|0x30000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR3_IN53 input. */ - kXBAR3_InputLpit1LpitTrigOut2 = 54|0x30000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR3_IN54 input. */ - kXBAR3_InputLpit1LpitTrigOut3 = 55|0x30000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR3_IN55 input. */ - kXBAR3_InputLpit2LpitTrigOut0 = 56|0x30000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR3_IN56 input. */ - kXBAR3_InputLpit2LpitTrigOut1 = 57|0x30000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR3_IN57 input. */ - kXBAR3_InputLpit2LpitTrigOut2 = 58|0x30000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR3_IN58 input. */ - kXBAR3_InputLpit2LpitTrigOut3 = 59|0x30000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR3_IN59 input. */ - kXBAR3_InputLpit3LpitTrigOut0 = 60|0x30000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR3_IN60 input. */ - kXBAR3_InputLpit3LpitTrigOut1 = 61|0x30000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR3_IN61 input. */ - kXBAR3_InputLpit3LpitTrigOut2 = 62|0x30000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR3_IN62 input. */ - kXBAR3_InputLpit3LpitTrigOut3 = 63|0x30000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR3_IN63 input. */ - kXBAR3_InputEdma2DmaTriggerOut0 = 64|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN64 input. */ - kXBAR3_InputEdma2DmaTriggerOut1 = 65|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN65 input. */ - kXBAR3_InputEdma2DmaTriggerOut2 = 66|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN66 input. */ - kXBAR3_InputEdma2DmaTriggerOut3 = 67|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN67 input. */ - kXBAR3_InputEdma2DmaTriggerOut4 = 68|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN68 input. */ - kXBAR3_InputEdma2DmaTriggerOut5 = 69|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN69 input. */ - kXBAR3_InputEdma2DmaTriggerOut6 = 70|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN70 input. */ - kXBAR3_InputEdma2DmaTriggerOut7 = 71|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN71 input. */ - kXBAR3_InputEdma1DmaTriggerOut0 = 72|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN72 input. */ - kXBAR3_InputEdma1DmaTriggerOut1 = 73|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN73 input. */ - kXBAR3_InputEdma1DmaTriggerOut2 = 74|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN74 input. */ - kXBAR3_InputEdma1DmaTriggerOut3 = 75|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN75 input. */ - kXBAR3_InputEdma1DmaTriggerOut4 = 76|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN76 input. */ - kXBAR3_InputEdma1DmaTriggerOut5 = 77|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN77 input. */ - kXBAR3_InputEdma1DmaTriggerOut6 = 78|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN78 input. */ - kXBAR3_InputEdma1DmaTriggerOut7 = 79|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN79 input. */ - kXBAR3_InputEdma3DmaTriggerOut0 = 80|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN80 input. */ - kXBAR3_InputEdma3DmaTriggerOut1 = 81|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN81 input. */ - kXBAR3_InputEdma3DmaTriggerOut2 = 82|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN82 input. */ - kXBAR3_InputEdma3DmaTriggerOut3 = 83|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN83 input. */ - kXBAR3_InputEdma3DmaTriggerOut4 = 84|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN84 input. */ - kXBAR3_InputEdma3DmaTriggerOut5 = 85|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN85 input. */ - kXBAR3_InputEdma3DmaTriggerOut6 = 86|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN86 input. */ - kXBAR3_InputEdma3DmaTriggerOut7 = 87|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN87 input. */ - kXBAR3_InputEdma4DmaTriggerOut0 = 88|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN88 input. */ - kXBAR3_InputEdma4DmaTriggerOut1 = 89|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN89 input. */ - kXBAR3_InputEdma4DmaTriggerOut2 = 90|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN90 input. */ - kXBAR3_InputEdma4DmaTriggerOut3 = 91|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN91 input. */ - kXBAR3_InputEdma4DmaTriggerOut4 = 92|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN92 input. */ - kXBAR3_InputEdma4DmaTriggerOut5 = 93|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN93 input. */ - kXBAR3_InputEdma4DmaTriggerOut6 = 94|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN94 input. */ - kXBAR3_InputEdma4DmaTriggerOut7 = 95|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN95 input. */ - kXBAR3_InputAdc1IpiIntEoc = 96|0x30000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR3_IN96 input. */ - kXBAR3_InputAdc1IpiIntWd = 97|0x30000U, /**< ADC1_IPI_INT_WD output assigned to XBAR3_IN97 input. */ - kXBAR3_InputTpm1LptpmChTrigger0 = 98|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN98 input. */ - kXBAR3_InputTpm1LptpmChTrigger1 = 99|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN99 input. */ - kXBAR3_InputTpm1LptpmChTrigger2 = 100|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN100 input. */ - kXBAR3_InputTpm1LptpmChTrigger3 = 101|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN101 input. */ - kXBAR3_InputTpm1LptpmTrigger = 102|0x30000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR3_IN102 input. */ - kXBAR3_InputTpm2LptpmChTrigger0 = 103|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN103 input. */ - kXBAR3_InputTpm2LptpmChTrigger1 = 104|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN104 input. */ - kXBAR3_InputTpm2LptpmChTrigger2 = 105|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN105 input. */ - kXBAR3_InputTpm2LptpmChTrigger3 = 106|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN106 input. */ - kXBAR3_InputTpm2LptpmTrigger = 107|0x30000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR3_IN107 input. */ - kXBAR3_InputTpm3LptpmChTrigger0 = 108|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN108 input. */ - kXBAR3_InputTpm3LptpmChTrigger1 = 109|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN109 input. */ - kXBAR3_InputTpm3LptpmChTrigger2 = 110|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN110 input. */ - kXBAR3_InputTpm3LptpmChTrigger3 = 111|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN111 input. */ - kXBAR3_InputTpm3LptpmTrigger = 112|0x30000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR3_IN112 input. */ - kXBAR3_InputTpm4LptpmChTrigger0 = 113|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN113 input. */ - kXBAR3_InputTpm4LptpmChTrigger1 = 114|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN114 input. */ - kXBAR3_InputTpm4LptpmChTrigger2 = 115|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN115 input. */ - kXBAR3_InputTpm4LptpmChTrigger3 = 116|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN116 input. */ - kXBAR3_InputTpm4LptpmTrigger = 117|0x30000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR3_IN117 input. */ - kXBAR3_InputTpm5LptpmChTrigger0 = 118|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN118 input. */ - kXBAR3_InputTpm5LptpmChTrigger1 = 119|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN119 input. */ - kXBAR3_InputTpm5LptpmChTrigger2 = 120|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN120 input. */ - kXBAR3_InputTpm5LptpmChTrigger3 = 121|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN121 input. */ - kXBAR3_InputTpm5LptpmTrigger = 122|0x30000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR3_IN122 input. */ - kXBAR3_InputTpm6LptpmChTrigger0 = 123|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN123 input. */ - kXBAR3_InputTpm6LptpmChTrigger1 = 124|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN124 input. */ - kXBAR3_InputTpm6LptpmChTrigger2 = 125|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN125 input. */ - kXBAR3_InputTpm6LptpmChTrigger3 = 126|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN126 input. */ - kXBAR3_InputTpm6LptpmTrigger = 127|0x30000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR3_IN127 input. */ - kXBAR3_InputLptmr1LptimerTriggerDelay = 128|0x30000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN128 input. */ - kXBAR3_InputLptmr2LptimerTriggerDelay = 129|0x30000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN129 input. */ - kXBAR3_InputLogicLow2 = 130|0x30000U, /**< LOGIC_LOW2 output assigned to XBAR3_IN130 input. */ - kXBAR3_InputNetcTmr11588Pp1 = 131|0x30000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR3_IN131 input. */ - kXBAR3_InputNetcTmr11588Pp2 = 132|0x30000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR3_IN132 input. */ - kXBAR3_InputNetcTmr11588Pp3 = 133|0x30000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR3_IN133 input. */ - kXBAR3_InputNetcTmr11588Alarm1 = 134|0x30000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR3_IN134 input. */ - kXBAR3_InputNetcTmr11588Alarm2 = 135|0x30000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR3_IN135 input. */ - kXBAR3_InputNetcTmr21588Pp1 = 136|0x30000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR3_IN136 input. */ - kXBAR3_InputNetcTmr21588Pp2 = 137|0x30000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR3_IN137 input. */ - kXBAR3_InputNetcTmr21588Pp3 = 138|0x30000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR3_IN138 input. */ - kXBAR3_InputNetcTmr21588Alarm1 = 139|0x30000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR3_IN139 input. */ - kXBAR3_InputNetcTmr21588Alarm2 = 140|0x30000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR3_IN140 input. */ - kXBAR3_InputNetcTmr31588Pp1 = 141|0x30000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR3_IN141 input. */ - kXBAR3_InputNetcTmr31588Pp2 = 142|0x30000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR3_IN142 input. */ - kXBAR3_InputNetcTmr31588Pp3 = 143|0x30000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR3_IN143 input. */ - kXBAR3_InputNetcTmr31588Alarm1 = 144|0x30000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR3_IN144 input. */ - kXBAR3_InputNetcTmr31588Alarm2 = 145|0x30000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR3_IN145 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak0 = 146|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR3_IN146 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak1 = 147|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR3_IN147 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak2 = 148|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR3_IN148 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak3 = 149|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR3_IN149 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak0 = 150|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR3_IN150 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak1 = 151|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR3_IN151 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak2 = 152|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR3_IN152 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak3 = 153|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR3_IN153 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak0 = 154|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR3_IN154 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak1 = 155|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR3_IN155 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak2 = 156|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR3_IN156 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak3 = 157|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR3_IN157 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak0 = 158|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR3_IN158 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak1 = 159|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR3_IN159 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak2 = 160|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR3_IN160 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak3 = 161|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR3_IN161 input. */ - kXBAR3_InputSinc2PulseTrg0 = 162|0x30000U, /**< SINC2_PULSE_TRG0 output assigned to XBAR3_IN162 input. */ - kXBAR3_InputSinc2PulseTrg1 = 163|0x30000U, /**< SINC2_PULSE_TRG1 output assigned to XBAR3_IN163 input. */ - kXBAR3_InputSinc2PulseTrg2 = 164|0x30000U, /**< SINC2_PULSE_TRG2 output assigned to XBAR3_IN164 input. */ - kXBAR3_InputSinc2PulseTrg3 = 165|0x30000U, /**< SINC2_PULSE_TRG3 output assigned to XBAR3_IN165 input. */ - kXBAR3_InputSinc4PulseTrg0 = 166|0x30000U, /**< SINC4_PULSE_TRG0 output assigned to XBAR3_IN166 input. */ - kXBAR3_InputSinc4PulseTrg1 = 167|0x30000U, /**< SINC4_PULSE_TRG1 output assigned to XBAR3_IN167 input. */ - kXBAR3_InputSinc4PulseTrg2 = 168|0x30000U, /**< SINC4_PULSE_TRG2 output assigned to XBAR3_IN168 input. */ - kXBAR3_InputSinc4PulseTrg3 = 169|0x30000U, /**< SINC4_PULSE_TRG3 output assigned to XBAR3_IN169 input. */ - kXBAR3_InputEcatSyncOut0 = 170|0x30000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR3_IN170 input. */ - kXBAR3_InputEcatSyncOut1 = 171|0x30000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR3_IN171 input. */ - kXBAR3_InputFccuVfccuReactionsOut11 = 172|0x30000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR3_IN172 input. */ - kXBAR3_InputGpt1IppDoCmpout1 = 173|0x30000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR3_IN173 input. */ - kXBAR3_InputGpt1IppDoCmpout2 = 174|0x30000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR3_IN174 input. */ - kXBAR3_InputGpt1IppDoCmpout3 = 175|0x30000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR3_IN175 input. */ - kXBAR3_InputGpt2IppDoCmpout1 = 176|0x30000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR3_IN176 input. */ - kXBAR3_InputGpt2IppDoCmpout2 = 177|0x30000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR3_IN177 input. */ - kXBAR3_InputGpt2IppDoCmpout3 = 178|0x30000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR3_IN178 input. */ - kXBAR3_InputGpt3IppDoCmpout1 = 179|0x30000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR3_IN179 input. */ - kXBAR3_InputGpt3IppDoCmpout2 = 180|0x30000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR3_IN180 input. */ - kXBAR3_InputGpt3IppDoCmpout3 = 181|0x30000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR3_IN181 input. */ - kXBAR3_InputGpt4IppDoCmpout1 = 182|0x30000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR3_IN182 input. */ - kXBAR3_InputGpt4IppDoCmpout2 = 183|0x30000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR3_IN183 input. */ - kXBAR3_InputGpt4IppDoCmpout3 = 184|0x30000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR3_IN184 input. */ - kXBAR3_InputFlexio1FlexioTriggerOut0 = 185|0x30000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN185 input. */ - kXBAR3_InputFlexio2FlexioTriggerOut0 = 186|0x30000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN186 input. */ - kXBAR3_InputFlexio3FlexioTriggerOut0 = 187|0x30000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN187 input. */ - kXBAR3_InputFlexio4FlexioTriggerOut0 = 188|0x30000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN188 input. */ - kXBAR3_InputGpio1IpiIntRgpio0 = 189|0x30000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR3_IN189 input. */ - kXBAR3_InputGpio2IpiIntRgpio0 = 190|0x30000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR3_IN190 input. */ - kXBAR3_InputGpio3IpiIntRgpio0 = 191|0x30000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR3_IN191 input. */ - kXBAR3_InputGpio4IpiIntRgpio0 = 192|0x30000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR3_IN192 input. */ - kXBAR3_InputGpio5IpiIntRgpio0 = 193|0x30000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR3_IN193 input. */ - kXBAR3_InputGpio6IpiIntRgpio0 = 194|0x30000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR3_IN194 input. */ - kXBAR3_InputGpio7IpiIntRgpio0 = 195|0x30000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR3_IN195 input. */ - kXBAR3_InputCm33Txev = 196|0x30000U, /**< CM33_TXEV output assigned to XBAR3_IN196 input. */ - kXBAR3_InputCm33SyncTxev = 197|0x30000U, /**< CM33_SYNC_TXEV output assigned to XBAR3_IN197 input. */ - kXBAR3_InputEndat21SiN = 198|0x30000U, /**< ENDAT2_1_SI_N output assigned to XBAR3_IN198 input. */ - kXBAR3_InputEndat21TimerN = 199|0x30000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR3_IN199 input. */ - kXBAR3_InputEndat22SiN = 200|0x30000U, /**< ENDAT2_2_SI_N output assigned to XBAR3_IN200 input. */ - kXBAR3_InputEndat22TimerN = 201|0x30000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR3_IN201 input. */ - kXBAR3_InputBissEot = 202|0x30000U, /**< BISS_EOT output assigned to XBAR3_IN202 input. */ - kXBAR3_InputEnc2PosMatch0 = 203|0x30000U, /**< ENC2_POS_MATCH0 output assigned to XBAR3_IN203 input. */ - kXBAR3_InputEnc2PosMatch1 = 204|0x30000U, /**< ENC2_POS_MATCH1 output assigned to XBAR3_IN204 input. */ - kXBAR3_InputEnc2PosMatch2 = 205|0x30000U, /**< ENC2_POS_MATCH2 output assigned to XBAR3_IN205 input. */ - kXBAR3_InputEnc2PosMatch3 = 206|0x30000U, /**< ENC2_POS_MATCH3 output assigned to XBAR3_IN206 input. */ - kXBAR3_InputEnc2CompFlg0 = 207|0x30000U, /**< ENC2_COMP_FLG0 output assigned to XBAR3_IN207 input. */ - kXBAR3_InputEnc2CompFlg1 = 208|0x30000U, /**< ENC2_COMP_FLG1 output assigned to XBAR3_IN208 input. */ - kXBAR3_InputEnc2CompFlg2 = 209|0x30000U, /**< ENC2_COMP_FLG2 output assigned to XBAR3_IN209 input. */ - kXBAR3_InputEnc2CompFlg3 = 210|0x30000U, /**< ENC2_COMP_FLG3 output assigned to XBAR3_IN210 input. */ - kXBAR3_InputEnc2CntDn = 211|0x30000U, /**< ENC2_CNT_DN output assigned to XBAR3_IN211 input. */ - kXBAR3_InputEnc2CntUp = 212|0x30000U, /**< ENC2_CNT_UP output assigned to XBAR3_IN212 input. */ - kXBAR3_InputEnc2Dir = 213|0x30000U, /**< ENC2_DIR output assigned to XBAR3_IN213 input. */ - kXBAR3_InputEnc4PosMatch0 = 214|0x30000U, /**< ENC4_POS_MATCH0 output assigned to XBAR3_IN214 input. */ - kXBAR3_InputEnc4PosMatch1 = 215|0x30000U, /**< ENC4_POS_MATCH1 output assigned to XBAR3_IN215 input. */ - kXBAR3_InputEnc4PosMatch2 = 216|0x30000U, /**< ENC4_POS_MATCH2 output assigned to XBAR3_IN216 input. */ - kXBAR3_InputEnc4PosMatch3 = 217|0x30000U, /**< ENC4_POS_MATCH3 output assigned to XBAR3_IN217 input. */ - kXBAR3_InputEnc4CompFlg0 = 218|0x30000U, /**< ENC4_COMP_FLG0 output assigned to XBAR3_IN218 input. */ - kXBAR3_InputEnc4CompFlg1 = 219|0x30000U, /**< ENC4_COMP_FLG1 output assigned to XBAR3_IN219 input. */ - kXBAR3_InputEnc4CompFlg2 = 220|0x30000U, /**< ENC4_COMP_FLG2 output assigned to XBAR3_IN220 input. */ - kXBAR3_InputEnc4CompFlg3 = 221|0x30000U, /**< ENC4_COMP_FLG3 output assigned to XBAR3_IN221 input. */ - kXBAR3_InputEnc4CntDn = 222|0x30000U, /**< ENC4_CNT_DN output assigned to XBAR3_IN222 input. */ - kXBAR3_InputEnc4CntUp = 223|0x30000U, /**< ENC4_CNT_UP output assigned to XBAR3_IN223 input. */ - kXBAR3_InputEnc4Dir = 224|0x30000U, /**< ENC4_DIR output assigned to XBAR3_IN224 input. */ - kXBAR3_InputHiperface1FastPosRcvdEvt = 225|0x30000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR3_IN225 input. */ - kXBAR3_InputHiperface2FastPosRcvdEvt = 226|0x30000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR3_IN226 input. */ -} xbar_input_signal_t; -#endif /* XBAR_INPUT_SIGNAL_T_ */ - -#if !defined(XBAR_OUTPUT_SIGNAL_T_) -#define XBAR_OUTPUT_SIGNAL_T_ -typedef enum _xbar_output_signal -{ - kXBAR1_OutputEdma4IpdReq76 = 0|0x10000U, /**< XBAR1_OUT0 output assigned to EDMA4_IPD_REQ76 */ - kXBAR1_OutputEdma4IpdReq77 = 1|0x10000U, /**< XBAR1_OUT1 output assigned to EDMA4_IPD_REQ77 */ - kXBAR1_OutputEdma4IpdReq78 = 2|0x10000U, /**< XBAR1_OUT2 output assigned to EDMA4_IPD_REQ78 */ - kXBAR1_OutputEdma4IpdReq79 = 3|0x10000U, /**< XBAR1_OUT3 output assigned to EDMA4_IPD_REQ79 */ - kXBAR1_OutputIomuxXbarOut04 = 4|0x10000U, /**< XBAR1_OUT4 output assigned to IOMUX_XBAR_OUT04 */ - kXBAR1_OutputIomuxXbarOut05 = 5|0x10000U, /**< XBAR1_OUT5 output assigned to IOMUX_XBAR_OUT05 */ - kXBAR1_OutputIomuxXbarOut06 = 6|0x10000U, /**< XBAR1_OUT6 output assigned to IOMUX_XBAR_OUT06 */ - kXBAR1_OutputIomuxXbarOut07 = 7|0x10000U, /**< XBAR1_OUT7 output assigned to IOMUX_XBAR_OUT07 */ - kXBAR1_OutputIomuxXbarOut08 = 8|0x10000U, /**< XBAR1_OUT8 output assigned to IOMUX_XBAR_OUT08 */ - kXBAR1_OutputIomuxXbarOut09 = 9|0x10000U, /**< XBAR1_OUT9 output assigned to IOMUX_XBAR_OUT09 */ - kXBAR1_OutputIomuxXbarOut10 = 10|0x10000U, /**< XBAR1_OUT10 output assigned to IOMUX_XBAR_OUT10 */ - kXBAR1_OutputIomuxXbarOut11 = 11|0x10000U, /**< XBAR1_OUT11 output assigned to IOMUX_XBAR_OUT11 */ - kXBAR1_OutputIomuxXbarOut12 = 12|0x10000U, /**< XBAR1_OUT12 output assigned to IOMUX_XBAR_OUT12 */ - kXBAR1_OutputIomuxXbarOut13 = 13|0x10000U, /**< XBAR1_OUT13 output assigned to IOMUX_XBAR_OUT13 */ - kXBAR1_OutputIomuxXbarOut14 = 14|0x10000U, /**< XBAR1_OUT14 output assigned to IOMUX_XBAR_OUT14 */ - kXBAR1_OutputIomuxXbarOut15 = 15|0x10000U, /**< XBAR1_OUT15 output assigned to IOMUX_XBAR_OUT15 */ - kXBAR1_OutputIomuxXbarOut16 = 16|0x10000U, /**< XBAR1_OUT16 output assigned to IOMUX_XBAR_OUT16 */ - kXBAR1_OutputIomuxXbarOut17 = 17|0x10000U, /**< XBAR1_OUT17 output assigned to IOMUX_XBAR_OUT17 */ - kXBAR1_OutputIomuxXbarOut18 = 18|0x10000U, /**< XBAR1_OUT18 output assigned to IOMUX_XBAR_OUT18 */ - kXBAR1_OutputIomuxXbarOut19 = 19|0x10000U, /**< XBAR1_OUT19 output assigned to IOMUX_XBAR_OUT19 */ - kXBAR1_OutputIomuxXbarOut20 = 20|0x10000U, /**< XBAR1_OUT20 output assigned to IOMUX_XBAR_OUT20 */ - kXBAR1_OutputIomuxXbarOut21 = 21|0x10000U, /**< XBAR1_OUT21 output assigned to IOMUX_XBAR_OUT21 */ - kXBAR1_OutputIomuxXbarOut22 = 22|0x10000U, /**< XBAR1_OUT22 output assigned to IOMUX_XBAR_OUT22 */ - kXBAR1_OutputIomuxXbarOut23 = 23|0x10000U, /**< XBAR1_OUT23 output assigned to IOMUX_XBAR_OUT23 */ - kXBAR1_OutputIomuxXbarOut24 = 24|0x10000U, /**< XBAR1_OUT24 output assigned to IOMUX_XBAR_OUT24 */ - kXBAR1_OutputIomuxXbarOut25 = 25|0x10000U, /**< XBAR1_OUT25 output assigned to IOMUX_XBAR_OUT25 */ - kXBAR1_OutputIomuxXbarOut26 = 26|0x10000U, /**< XBAR1_OUT26 output assigned to IOMUX_XBAR_OUT26 */ - kXBAR1_OutputIomuxXbarOut27 = 27|0x10000U, /**< XBAR1_OUT27 output assigned to IOMUX_XBAR_OUT27 */ - kXBAR1_OutputIomuxXbarOut28 = 28|0x10000U, /**< XBAR1_OUT28 output assigned to IOMUX_XBAR_OUT28 */ - kXBAR1_OutputIomuxXbarOut29 = 29|0x10000U, /**< XBAR1_OUT29 output assigned to IOMUX_XBAR_OUT29 */ - kXBAR1_OutputIomuxXbarOut30 = 30|0x10000U, /**< XBAR1_OUT30 output assigned to IOMUX_XBAR_OUT30 */ - kXBAR1_OutputIomuxXbarOut31 = 31|0x10000U, /**< XBAR1_OUT31 output assigned to IOMUX_XBAR_OUT31 */ - kXBAR1_OutputIomuxXbarOut32 = 32|0x10000U, /**< XBAR1_OUT32 output assigned to IOMUX_XBAR_OUT32 */ - kXBAR1_OutputIomuxXbarOut33 = 33|0x10000U, /**< XBAR1_OUT33 output assigned to IOMUX_XBAR_OUT33 */ - kXBAR1_OutputIomuxXbarOut34 = 34|0x10000U, /**< XBAR1_OUT34 output assigned to IOMUX_XBAR_OUT34 */ - kXBAR1_OutputIomuxXbarOut35 = 35|0x10000U, /**< XBAR1_OUT35 output assigned to IOMUX_XBAR_OUT35 */ - kXBAR1_OutputIomuxXbarOut36 = 36|0x10000U, /**< XBAR1_OUT36 output assigned to IOMUX_XBAR_OUT36 */ - kXBAR1_OutputIomuxXbarOut37 = 37|0x10000U, /**< XBAR1_OUT37 output assigned to IOMUX_XBAR_OUT37 */ - kXBAR1_OutputIomuxXbarOut38 = 38|0x10000U, /**< XBAR1_OUT38 output assigned to IOMUX_XBAR_OUT38 */ - kXBAR1_OutputIomuxXbarOut39 = 39|0x10000U, /**< XBAR1_OUT39 output assigned to IOMUX_XBAR_OUT39 */ - kXBAR1_OutputIomuxXbarOut40 = 40|0x10000U, /**< XBAR1_OUT40 output assigned to IOMUX_XBAR_OUT40 */ - kXBAR1_OutputTriggerSyncAsyncIn0 = 41|0x10000U, /**< XBAR1_OUT41 output assigned to TRIGGER_SYNC_ASYNC_IN0 */ - kXBAR1_OutputTriggerSyncAsyncIn1 = 42|0x10000U, /**< XBAR1_OUT42 output assigned to TRIGGER_SYNC_ASYNC_IN1 */ - kXBAR1_OutputTriggerSyncAsyncIn2 = 43|0x10000U, /**< XBAR1_OUT43 output assigned to TRIGGER_SYNC_ASYNC_IN2 */ - kXBAR1_OutputTriggerSyncAsyncIn3 = 44|0x10000U, /**< XBAR1_OUT44 output assigned to TRIGGER_SYNC_ASYNC_IN3 */ - kXBAR1_OutputTriggerSyncAsyncIn4 = 45|0x10000U, /**< XBAR1_OUT45 output assigned to TRIGGER_SYNC_ASYNC_IN4 */ - kXBAR1_OutputTriggerSyncAsyncIn5 = 46|0x10000U, /**< XBAR1_OUT46 output assigned to TRIGGER_SYNC_ASYNC_IN5 */ - kXBAR1_OutputTriggerSyncAsyncIn6 = 47|0x10000U, /**< XBAR1_OUT47 output assigned to TRIGGER_SYNC_ASYNC_IN6 */ - kXBAR1_OutputTriggerSyncAsyncIn7 = 48|0x10000U, /**< XBAR1_OUT48 output assigned to TRIGGER_SYNC_ASYNC_IN7 */ - kXBAR1_OutputFlexpwm1Exta0 = 49|0x10000U, /**< XBAR1_OUT49 output assigned to FLEXPWM1_EXTA0 */ - kXBAR1_OutputFlexpwm1Exta1 = 50|0x10000U, /**< XBAR1_OUT50 output assigned to FLEXPWM1_EXTA1 */ - kXBAR1_OutputFlexpwm1Exta2 = 51|0x10000U, /**< XBAR1_OUT51 output assigned to FLEXPWM1_EXTA2 */ - kXBAR1_OutputFlexpwm1Exta3 = 52|0x10000U, /**< XBAR1_OUT52 output assigned to FLEXPWM1_EXTA3 */ - kXBAR1_OutputFlexpwm1ExtSync0 = 53|0x10000U, /**< XBAR1_OUT53 output assigned to FLEXPWM1_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm1ExtSync1 = 54|0x10000U, /**< XBAR1_OUT54 output assigned to FLEXPWM1_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm1ExtSync2 = 55|0x10000U, /**< XBAR1_OUT55 output assigned to FLEXPWM1_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm1ExtSync3 = 56|0x10000U, /**< XBAR1_OUT56 output assigned to FLEXPWM1_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm1ExtClk = 57|0x10000U, /**< XBAR1_OUT57 output assigned to FLEXPWM1_EXT_CLK */ - kXBAR1_OutputFlexpwm1IppIndFault0 = 58|0x10000U, /**< XBAR1_OUT58 output assigned to FLEXPWM1_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm1IppIndFault1 = 59|0x10000U, /**< XBAR1_OUT59 output assigned to FLEXPWM1_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm1IppIndFault2 = 60|0x10000U, /**< XBAR1_OUT60 output assigned to FLEXPWM1_IPP_IND_FAULT2 */ - kXBAR1_OutputFlexpwm1IppIndFault3 = 61|0x10000U, /**< XBAR1_OUT61 output assigned to FLEXPWM1_IPP_IND_FAULT3 */ - kXBAR1_OutputFlexpwm1ExtForce = 62|0x10000U, /**< XBAR1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */ - kXBAR1_OutputFlexpwm2Exta0 = 63|0x10000U, /**< XBAR1_OUT63 output assigned to FLEXPWM2_EXTA0 */ - kXBAR1_OutputFlexpwm2Exta1 = 64|0x10000U, /**< XBAR1_OUT64 output assigned to FLEXPWM2_EXTA1 */ - kXBAR1_OutputFlexpwm2Exta2 = 65|0x10000U, /**< XBAR1_OUT65 output assigned to FLEXPWM2_EXTA2 */ - kXBAR1_OutputFlexpwm2Exta3 = 66|0x10000U, /**< XBAR1_OUT66 output assigned to FLEXPWM2_EXTA3 */ - kXBAR1_OutputFlexpwm2ExtSync0 = 67|0x10000U, /**< XBAR1_OUT67 output assigned to FLEXPWM2_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm2ExtSync1 = 68|0x10000U, /**< XBAR1_OUT68 output assigned to FLEXPWM2_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm2ExtSync2 = 69|0x10000U, /**< XBAR1_OUT69 output assigned to FLEXPWM2_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm2ExtSync3 = 70|0x10000U, /**< XBAR1_OUT70 output assigned to FLEXPWM2_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm2ExtClk = 71|0x10000U, /**< XBAR1_OUT71 output assigned to FLEXPWM2_EXT_CLK */ - kXBAR1_OutputFlexpwm2IppIndFault0 = 72|0x10000U, /**< XBAR1_OUT72 output assigned to FLEXPWM2_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm2IppIndFault1 = 73|0x10000U, /**< XBAR1_OUT73 output assigned to FLEXPWM2_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm2ExtForce = 74|0x10000U, /**< XBAR1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */ - kXBAR1_OutputFlexpwm3Exta0 = 75|0x10000U, /**< XBAR1_OUT75 output assigned to FLEXPWM3_EXTA0 */ - kXBAR1_OutputFlexpwm3Exta1 = 76|0x10000U, /**< XBAR1_OUT76 output assigned to FLEXPWM3_EXTA1 */ - kXBAR1_OutputFlexpwm3Exta2 = 77|0x10000U, /**< XBAR1_OUT77 output assigned to FLEXPWM3_EXTA2 */ - kXBAR1_OutputFlexpwm3Exta3 = 78|0x10000U, /**< XBAR1_OUT78 output assigned to FLEXPWM3_EXTA3 */ - kXBAR1_OutputFlexpwm3ExtClk = 79|0x10000U, /**< XBAR1_OUT79 output assigned to FLEXPWM3_EXT_CLK */ - kXBAR1_OutputFlexpwm3ExtSync0 = 80|0x10000U, /**< XBAR1_OUT80 output assigned to FLEXPWM3_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm3ExtSync1 = 81|0x10000U, /**< XBAR1_OUT81 output assigned to FLEXPWM3_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm3ExtSync2 = 82|0x10000U, /**< XBAR1_OUT82 output assigned to FLEXPWM3_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm3ExtSync3 = 83|0x10000U, /**< XBAR1_OUT83 output assigned to FLEXPWM3_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm3IppIndFault0 = 84|0x10000U, /**< XBAR1_OUT84 output assigned to FLEXPWM3_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm3IppIndFault1 = 85|0x10000U, /**< XBAR1_OUT85 output assigned to FLEXPWM3_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm3ExtForce = 86|0x10000U, /**< XBAR1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */ - kXBAR1_OutputFlexpwm4ExtSync0 = 87|0x10000U, /**< XBAR1_OUT87 output assigned to FLEXPWM4_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm4ExtSync1 = 88|0x10000U, /**< XBAR1_OUT88 output assigned to FLEXPWM4_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm4ExtSync2 = 89|0x10000U, /**< XBAR1_OUT89 output assigned to FLEXPWM4_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm4ExtSync3 = 90|0x10000U, /**< XBAR1_OUT90 output assigned to FLEXPWM4_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm4IppIndFault0 = 91|0x10000U, /**< XBAR1_OUT91 output assigned to FLEXPWM4_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm4IppIndFault1 = 92|0x10000U, /**< XBAR1_OUT92 output assigned to FLEXPWM4_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm4ExtForce = 93|0x10000U, /**< XBAR1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */ - kXBAR1_OutputEnc1PhaseAInput = 94|0x10000U, /**< XBAR1_OUT94 output assigned to ENC1_PHASE_A_INPUT */ - kXBAR1_OutputEnc1PhaseBInput = 95|0x10000U, /**< XBAR1_OUT95 output assigned to ENC1_PHASE_B_INPUT */ - kXBAR1_OutputEnc1Index = 96|0x10000U, /**< XBAR1_OUT96 output assigned to ENC1_INDEX */ - kXBAR1_OutputEnc1Home = 97|0x10000U, /**< XBAR1_OUT97 output assigned to ENC1_HOME */ - kXBAR1_OutputEnc1Trigger = 98|0x10000U, /**< XBAR1_OUT98 output assigned to ENC1_TRIGGER */ - kXBAR1_OutputEnc2PhaseAInput = 99|0x10000U, /**< XBAR1_OUT99 output assigned to ENC2_PHASE_A_INPUT */ - kXBAR1_OutputEnc2PhaseBInput = 100|0x10000U, /**< XBAR1_OUT100 output assigned to ENC2_PHASE_B_INPUT */ - kXBAR1_OutputEnc2Index = 101|0x10000U, /**< XBAR1_OUT101 output assigned to ENC2_INDEX */ - kXBAR1_OutputEnc2Home = 102|0x10000U, /**< XBAR1_OUT102 output assigned to ENC2_HOME */ - kXBAR1_OutputEnc2Trigger = 103|0x10000U, /**< XBAR1_OUT103 output assigned to ENC2_TRIGGER */ - kXBAR1_OutputEnc3PhaseAInput = 104|0x10000U, /**< XBAR1_OUT104 output assigned to ENC3_PHASE_A_INPUT */ - kXBAR1_OutputEnc3PhaseBInput = 105|0x10000U, /**< XBAR1_OUT105 output assigned to ENC3_PHASE_B_INPUT */ - kXBAR1_OutputEnc3Index = 106|0x10000U, /**< XBAR1_OUT106 output assigned to ENC3_INDEX */ - kXBAR1_OutputEnc3Home = 107|0x10000U, /**< XBAR1_OUT107 output assigned to ENC3_HOME */ - kXBAR1_OutputEnc3Trigger = 108|0x10000U, /**< XBAR1_OUT108 output assigned to ENC3_TRIGGER */ - kXBAR1_OutputEnc4PhaseAInput = 109|0x10000U, /**< XBAR1_OUT109 output assigned to ENC4_PHASE_A_INPUT */ - kXBAR1_OutputEnc4PhaseBInput = 110|0x10000U, /**< XBAR1_OUT110 output assigned to ENC4_PHASE_B_INPUT */ - kXBAR1_OutputEnc4Index = 111|0x10000U, /**< XBAR1_OUT111 output assigned to ENC4_INDEX */ - kXBAR1_OutputEnc4Home = 112|0x10000U, /**< XBAR1_OUT112 output assigned to ENC4_HOME */ - kXBAR1_OutputEnc4Trigger = 113|0x10000U, /**< XBAR1_OUT113 output assigned to ENC4_TRIGGER */ - kXBAR1_OutputQtimer1Tmr0Input = 114|0x10000U, /**< XBAR1_OUT114 output assigned to QTIMER1_TMR0_INPUT */ - kXBAR1_OutputQtimer1Tmr1Input = 115|0x10000U, /**< XBAR1_OUT115 output assigned to QTIMER1_TMR1_INPUT */ - kXBAR1_OutputQtimer1Tmr2Input = 116|0x10000U, /**< XBAR1_OUT116 output assigned to QTIMER1_TMR2_INPUT */ - kXBAR1_OutputQtimer1Tmr3Input = 117|0x10000U, /**< XBAR1_OUT117 output assigned to QTIMER1_TMR3_INPUT */ - kXBAR1_OutputQtimer2Tmr0Input = 118|0x10000U, /**< XBAR1_OUT118 output assigned to QTIMER2_TMR0_INPUT */ - kXBAR1_OutputQtimer2Tmr1Input = 119|0x10000U, /**< XBAR1_OUT119 output assigned to QTIMER2_TMR1_INPUT */ - kXBAR1_OutputQtimer2Tmr2Input = 120|0x10000U, /**< XBAR1_OUT120 output assigned to QTIMER2_TMR2_INPUT */ - kXBAR1_OutputQtimer2Tmr3Input = 121|0x10000U, /**< XBAR1_OUT121 output assigned to QTIMER2_TMR3_INPUT */ - kXBAR1_OutputQtimer3Tmr0Input = 122|0x10000U, /**< XBAR1_OUT122 output assigned to QTIMER3_TMR0_INPUT */ - kXBAR1_OutputQtimer3Tmr1Input = 123|0x10000U, /**< XBAR1_OUT123 output assigned to QTIMER3_TMR1_INPUT */ - kXBAR1_OutputQtimer3Tmr2Input = 124|0x10000U, /**< XBAR1_OUT124 output assigned to QTIMER3_TMR2_INPUT */ - kXBAR1_OutputQtimer3Tmr3Input = 125|0x10000U, /**< XBAR1_OUT125 output assigned to QTIMER3_TMR3_INPUT */ - kXBAR1_OutputQtimer4Tmr0Input = 126|0x10000U, /**< XBAR1_OUT126 output assigned to QTIMER4_TMR0_INPUT */ - kXBAR1_OutputQtimer4Tmr1Input = 127|0x10000U, /**< XBAR1_OUT127 output assigned to QTIMER4_TMR1_INPUT */ - kXBAR1_OutputQtimer4Tmr2Input = 128|0x10000U, /**< XBAR1_OUT128 output assigned to QTIMER4_TMR2_INPUT */ - kXBAR1_OutputQtimer4Tmr3Input = 129|0x10000U, /**< XBAR1_OUT129 output assigned to QTIMER4_TMR3_INPUT */ - kXBAR1_OutputQtimer5Tmr0Input = 130|0x10000U, /**< XBAR1_OUT130 output assigned to QTIMER5_TMR0_INPUT */ - kXBAR1_OutputQtimer5Tmr1Input = 131|0x10000U, /**< XBAR1_OUT131 output assigned to QTIMER5_TMR1_INPUT */ - kXBAR1_OutputQtimer5Tmr2Input = 132|0x10000U, /**< XBAR1_OUT132 output assigned to QTIMER5_TMR2_INPUT */ - kXBAR1_OutputQtimer5Tmr3Input = 133|0x10000U, /**< XBAR1_OUT133 output assigned to QTIMER5_TMR3_INPUT */ - kXBAR1_OutputQtimer6Tmr0Input = 134|0x10000U, /**< XBAR1_OUT134 output assigned to QTIMER6_TMR0_INPUT */ - kXBAR1_OutputQtimer6Tmr1Input = 135|0x10000U, /**< XBAR1_OUT135 output assigned to QTIMER6_TMR1_INPUT */ - kXBAR1_OutputQtimer6Tmr2Input = 136|0x10000U, /**< XBAR1_OUT136 output assigned to QTIMER6_TMR2_INPUT */ - kXBAR1_OutputQtimer6Tmr3Input = 137|0x10000U, /**< XBAR1_OUT137 output assigned to QTIMER6_TMR3_INPUT */ - kXBAR1_OutputQtimer7Tmr0Input = 138|0x10000U, /**< XBAR1_OUT138 output assigned to QTIMER7_TMR0_INPUT */ - kXBAR1_OutputQtimer7Tmr1Input = 139|0x10000U, /**< XBAR1_OUT139 output assigned to QTIMER7_TMR1_INPUT */ - kXBAR1_OutputQtimer7Tmr2Input = 140|0x10000U, /**< XBAR1_OUT140 output assigned to QTIMER7_TMR2_INPUT */ - kXBAR1_OutputQtimer7Tmr3Input = 141|0x10000U, /**< XBAR1_OUT141 output assigned to QTIMER7_TMR3_INPUT */ - kXBAR1_OutputQtimer8Tmr0Input = 142|0x10000U, /**< XBAR1_OUT142 output assigned to QTIMER8_TMR0_INPUT */ - kXBAR1_OutputQtimer8Tmr1Input = 143|0x10000U, /**< XBAR1_OUT143 output assigned to QTIMER8_TMR1_INPUT */ - kXBAR1_OutputQtimer8Tmr2Input = 144|0x10000U, /**< XBAR1_OUT144 output assigned to QTIMER8_TMR2_INPUT */ - kXBAR1_OutputQtimer8Tmr3Input = 145|0x10000U, /**< XBAR1_OUT145 output assigned to QTIMER8_TMR3_INPUT */ - kXBAR1_OutputEwmEwmIn = 146|0x10000U, /**< XBAR1_OUT146 output assigned to EWM_EWM_IN */ - kXBAR1_OutputAnamixGlueTrgmuxInjectionTrg = 147|0x10000U, /**< XBAR1_OUT147 output assigned to ANAMIX_GLUE_TRGMUX_INJECTION_TRG */ - kXBAR1_OutputAnamixGlueTrgmuxStartTrg = 148|0x10000U, /**< XBAR1_OUT148 output assigned to ANAMIX_GLUE_TRGMUX_START_TRG */ - kXBAR1_OutputSinc1ExtTrigger0 = 149|0x10000U, /**< XBAR1_OUT149 output assigned to SINC1_EXT_TRIGGER0 */ - kXBAR1_OutputSinc1ExtTrigger1 = 150|0x10000U, /**< XBAR1_OUT150 output assigned to SINC1_EXT_TRIGGER1 */ - kXBAR1_OutputSinc1ExtTrigger2 = 151|0x10000U, /**< XBAR1_OUT151 output assigned to SINC1_EXT_TRIGGER2 */ - kXBAR1_OutputSinc1ExtTrigger3 = 152|0x10000U, /**< XBAR1_OUT152 output assigned to SINC1_EXT_TRIGGER3 */ - kXBAR1_OutputFlexio1FlexioTriggerIn0 = 153|0x10000U, /**< XBAR1_OUT153 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio1FlexioTriggerIn1 = 154|0x10000U, /**< XBAR1_OUT154 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputFlexio2FlexioTriggerIn0 = 155|0x10000U, /**< XBAR1_OUT155 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio2FlexioTriggerIn1 = 156|0x10000U, /**< XBAR1_OUT156 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputFlexio3FlexioTriggerIn0 = 157|0x10000U, /**< XBAR1_OUT157 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio3FlexioTriggerIn1 = 158|0x10000U, /**< XBAR1_OUT158 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputFlexio4FlexioTriggerIn0 = 159|0x10000U, /**< XBAR1_OUT159 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio4FlexioTriggerIn1 = 160|0x10000U, /**< XBAR1_OUT160 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputLpi2c1Lpi2cTrgInput = 161|0x10000U, /**< XBAR1_OUT161 output assigned to LPI2C1_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c2Lpi2cTrgInput = 162|0x10000U, /**< XBAR1_OUT162 output assigned to LPI2C2_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c3Lpi2cTrgInput = 163|0x10000U, /**< XBAR1_OUT163 output assigned to LPI2C3_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c4Lpi2cTrgInput = 164|0x10000U, /**< XBAR1_OUT164 output assigned to LPI2C4_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c5Lpi2cTrgInput = 165|0x10000U, /**< XBAR1_OUT165 output assigned to LPI2C5_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c6Lpi2cTrgInput = 166|0x10000U, /**< XBAR1_OUT166 output assigned to LPI2C6_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c7Lpi2cTrgInput = 167|0x10000U, /**< XBAR1_OUT167 output assigned to LPI2C7_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c8Lpi2cTrgInput = 168|0x10000U, /**< XBAR1_OUT168 output assigned to LPI2C8_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpspi1LpspiTrgInput = 169|0x10000U, /**< XBAR1_OUT169 output assigned to LPSPI1_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi2LpspiTrgInput = 170|0x10000U, /**< XBAR1_OUT170 output assigned to LPSPI2_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi3LpspiTrgInput = 171|0x10000U, /**< XBAR1_OUT171 output assigned to LPSPI3_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi4LpspiTrgInput = 172|0x10000U, /**< XBAR1_OUT172 output assigned to LPSPI4_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi5LpspiTrgInput = 173|0x10000U, /**< XBAR1_OUT173 output assigned to LPSPI5_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi6LpspiTrgInput = 174|0x10000U, /**< XBAR1_OUT174 output assigned to LPSPI6_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi7LpspiTrgInput = 175|0x10000U, /**< XBAR1_OUT175 output assigned to LPSPI7_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi8LpspiTrgInput = 176|0x10000U, /**< XBAR1_OUT176 output assigned to LPSPI8_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpuart1LpuartTrgInput = 177|0x10000U, /**< XBAR1_OUT177 output assigned to LPUART1_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart2LpuartTrgInput = 178|0x10000U, /**< XBAR1_OUT178 output assigned to LPUART2_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart3LpuartTrgInput = 179|0x10000U, /**< XBAR1_OUT179 output assigned to LPUART3_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart4LpuartTrgInput = 180|0x10000U, /**< XBAR1_OUT180 output assigned to LPUART4_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart5LpuartTrgInput = 181|0x10000U, /**< XBAR1_OUT181 output assigned to LPUART5_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart6LpuartTrgInput = 182|0x10000U, /**< XBAR1_OUT182 output assigned to LPUART6_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart7LpuartTrgInput = 183|0x10000U, /**< XBAR1_OUT183 output assigned to LPUART7_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart8LpuartTrgInput = 184|0x10000U, /**< XBAR1_OUT184 output assigned to LPUART8_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart9LpuartTrgInput = 185|0x10000U, /**< XBAR1_OUT185 output assigned to LPUART9_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart10LpuartTrgInput = 186|0x10000U, /**< XBAR1_OUT186 output assigned to LPUART10_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart11LpuartTrgInput = 187|0x10000U, /**< XBAR1_OUT187 output assigned to LPUART11_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart12LpuartTrgInput = 188|0x10000U, /**< XBAR1_OUT188 output assigned to LPUART12_LPUART_TRG_INPUT */ - kXBAR1_OutputLpit1LpitExtTrigIn0 = 189|0x10000U, /**< XBAR1_OUT189 output assigned to LPIT1_LPIT_EXT_TRIG_IN0 */ - kXBAR1_OutputLpit1LpitExtTrigIn1 = 190|0x10000U, /**< XBAR1_OUT190 output assigned to LPIT1_LPIT_EXT_TRIG_IN1 */ - kXBAR1_OutputLpit1LpitExtTrigIn2 = 191|0x10000U, /**< XBAR1_OUT191 output assigned to LPIT1_LPIT_EXT_TRIG_IN2 */ - kXBAR1_OutputLpit1LpitExtTrigIn3 = 192|0x10000U, /**< XBAR1_OUT192 output assigned to LPIT1_LPIT_EXT_TRIG_IN3 */ - kXBAR1_OutputTpm1LptpmTriggerIn0 = 193|0x10000U, /**< XBAR1_OUT193 output assigned to TPM1_LPTPM_TRIGGER_IN0 */ - kXBAR1_OutputTpm1LptpmTriggerIn1 = 194|0x10000U, /**< XBAR1_OUT194 output assigned to TPM1_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm2LptpmTriggerIn1 = 195|0x10000U, /**< XBAR1_OUT195 output assigned to TPM2_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm3LptpmTriggerIn1 = 196|0x10000U, /**< XBAR1_OUT196 output assigned to TPM3_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm1LptpmTriggerIn2 = 197|0x10000U, /**< XBAR1_OUT197 output assigned to TPM1_LPTPM_TRIGGER_IN2 */ - kXBAR1_OutputTpm1LptpmTriggerIn3 = 198|0x10000U, /**< XBAR1_OUT198 output assigned to TPM1_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm2LptpmTriggerIn3 = 199|0x10000U, /**< XBAR1_OUT199 output assigned to TPM2_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm3LptpmTriggerIn3 = 200|0x10000U, /**< XBAR1_OUT200 output assigned to TPM3_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm4LptpmTriggerIn0 = 201|0x10000U, /**< XBAR1_OUT201 output assigned to TPM4_LPTPM_TRIGGER_IN0 */ - kXBAR1_OutputTpm4LptpmTriggerIn1 = 202|0x10000U, /**< XBAR1_OUT202 output assigned to TPM4_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm5LptpmTriggerIn1 = 203|0x10000U, /**< XBAR1_OUT203 output assigned to TPM5_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm6LptpmTriggerIn1 = 204|0x10000U, /**< XBAR1_OUT204 output assigned to TPM6_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm4LptpmTriggerIn2 = 205|0x10000U, /**< XBAR1_OUT205 output assigned to TPM4_LPTPM_TRIGGER_IN2 */ - kXBAR1_OutputTpm4LptpmTriggerIn3 = 206|0x10000U, /**< XBAR1_OUT206 output assigned to TPM4_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm5LptpmTriggerIn3 = 207|0x10000U, /**< XBAR1_OUT207 output assigned to TPM5_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm6LptpmTriggerIn3 = 208|0x10000U, /**< XBAR1_OUT208 output assigned to TPM6_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputNetcTmr11588Trig1 = 209|0x10000U, /**< XBAR1_OUT209 output assigned to NETC_TMR1_1588_TRIG1 */ - kXBAR1_OutputNetcTmr11588Trig2 = 210|0x10000U, /**< XBAR1_OUT210 output assigned to NETC_TMR1_1588_TRIG2 */ - kXBAR1_OutputNetcTmr21588Trig1 = 211|0x10000U, /**< XBAR1_OUT211 output assigned to NETC_TMR2_1588_TRIG1 */ - kXBAR1_OutputNetcTmr21588Trig2 = 212|0x10000U, /**< XBAR1_OUT212 output assigned to NETC_TMR2_1588_TRIG2 */ - kXBAR1_OutputNetcTmr31588Trig1 = 213|0x10000U, /**< XBAR1_OUT213 output assigned to NETC_TMR3_1588_TRIG1 */ - kXBAR1_OutputNetcTmr31588Trig2 = 214|0x10000U, /**< XBAR1_OUT214 output assigned to NETC_TMR3_1588_TRIG2 */ - kXBAR1_OutputEnc1Icap1 = 215|0x10000U, /**< XBAR1_OUT215 output assigned to ENC1_ICAP1 */ - kXBAR1_OutputEnc1Icap2 = 216|0x10000U, /**< XBAR1_OUT216 output assigned to ENC1_ICAP2 */ - kXBAR1_OutputEnc1Icap3 = 217|0x10000U, /**< XBAR1_OUT217 output assigned to ENC1_ICAP3 */ - kXBAR1_OutputEnc2Icap1 = 218|0x10000U, /**< XBAR1_OUT218 output assigned to ENC2_ICAP1 */ - kXBAR1_OutputEnc2Icap2 = 219|0x10000U, /**< XBAR1_OUT219 output assigned to ENC2_ICAP2 */ - kXBAR1_OutputEnc2Icap3 = 220|0x10000U, /**< XBAR1_OUT220 output assigned to ENC2_ICAP3 */ - kXBAR1_OutputEnc3Icap1 = 221|0x10000U, /**< XBAR1_OUT221 output assigned to ENC3_ICAP1 */ - kXBAR1_OutputEnc3Icap2 = 222|0x10000U, /**< XBAR1_OUT222 output assigned to ENC3_ICAP2 */ - kXBAR1_OutputEnc3Icap3 = 223|0x10000U, /**< XBAR1_OUT223 output assigned to ENC3_ICAP3 */ - kXBAR1_OutputEnc4Icap1 = 224|0x10000U, /**< XBAR1_OUT224 output assigned to ENC4_ICAP1 */ - kXBAR1_OutputEnc4Icap2 = 225|0x10000U, /**< XBAR1_OUT225 output assigned to ENC4_ICAP2 */ - kXBAR1_OutputEnc4Icap3 = 226|0x10000U, /**< XBAR1_OUT226 output assigned to ENC4_ICAP3 */ - kXBAR1_OutputEcatLatchIn0 = 227|0x10000U, /**< XBAR1_OUT227 output assigned to ECAT_LATCH_IN0 */ - kXBAR1_OutputEcatLatchIn1 = 228|0x10000U, /**< XBAR1_OUT228 output assigned to ECAT_LATCH_IN1 */ - kXBAR1_OutputSafetyClkMonDutClk = 229|0x10000U, /**< XBAR1_OUT229 output assigned to SAFETY_CLK_MON_DUT_CLK */ - kXBAR1_OutputEndat21StrN = 230|0x10000U, /**< XBAR1_OUT230 output assigned to ENDAT2_1_STR_N */ - kXBAR1_OutputEndat21Ir6N = 231|0x10000U, /**< XBAR1_OUT231 output assigned to ENDAT2_1_IR6_N */ - kXBAR1_OutputEndat21Ir7N = 232|0x10000U, /**< XBAR1_OUT232 output assigned to ENDAT2_1_IR7_N */ - kXBAR1_OutputEndat22StrN = 233|0x10000U, /**< XBAR1_OUT233 output assigned to ENDAT2_2_STR_N */ - kXBAR1_OutputEndat22Ir6N = 234|0x10000U, /**< XBAR1_OUT234 output assigned to ENDAT2_2_IR6_N */ - kXBAR1_OutputEndat22Ir7N = 235|0x10000U, /**< XBAR1_OUT235 output assigned to ENDAT2_2_IR7_N */ - kXBAR1_OutputEndat3HwStrobe = 236|0x10000U, /**< XBAR1_OUT236 output assigned to ENDAT3_HW_STROBE */ - kXBAR1_OutputBissGetsens = 237|0x10000U, /**< XBAR1_OUT237 output assigned to BISS_GETSENS */ - kXBAR1_OutputSinc3ExtTrigger2 = 238|0x10000U, /**< XBAR1_OUT238 output assigned to SINC3_EXT_TRIGGER2 */ - kXBAR1_OutputSinc3ExtTrigger3 = 239|0x10000U, /**< XBAR1_OUT239 output assigned to SINC3_EXT_TRIGGER3 */ - kXBAR1_OutputHiperface1SyncXbar = 240|0x10000U, /**< XBAR1_OUT240 output assigned to HIPERFACE1_SYNC_XBAR */ - kXBAR1_OutputHiperface2SyncXbar = 241|0x10000U, /**< XBAR1_OUT241 output assigned to HIPERFACE2_SYNC_XBAR */ - kXBAR1_OutputTriggerSyncAsyncIn8 = 242|0x10000U, /**< XBAR1_OUT242 output assigned to TRIGGER_SYNC_ASYNC_IN8 */ - kXBAR1_OutputTriggerSyncAsyncIn9 = 243|0x10000U, /**< XBAR1_OUT243 output assigned to TRIGGER_SYNC_ASYNC_IN9 */ - kXBAR1_OutputTriggerSyncAsyncIn10 = 244|0x10000U, /**< XBAR1_OUT244 output assigned to TRIGGER_SYNC_ASYNC_IN10 */ - kXBAR1_OutputTriggerSyncAsyncIn11 = 245|0x10000U, /**< XBAR1_OUT245 output assigned to TRIGGER_SYNC_ASYNC_IN11 */ - kXBAR1_OutputTriggerSyncAsyncIn12 = 246|0x10000U, /**< XBAR1_OUT246 output assigned to TRIGGER_SYNC_ASYNC_IN12 */ - kXBAR1_OutputTriggerSyncAsyncIn13 = 247|0x10000U, /**< XBAR1_OUT247 output assigned to TRIGGER_SYNC_ASYNC_IN13 */ - kXBAR1_OutputTriggerSyncAsyncIn14 = 248|0x10000U, /**< XBAR1_OUT248 output assigned to TRIGGER_SYNC_ASYNC_IN14 */ - kXBAR1_OutputTriggerSyncAsyncIn15 = 249|0x10000U, /**< XBAR1_OUT249 output assigned to TRIGGER_SYNC_ASYNC_IN15 */ - kXBAR1_OutputSinc2ExtTrigger0 = 250|0x10000U, /**< XBAR1_OUT250 output assigned to SINC2_EXT_TRIGGER0 */ - kXBAR1_OutputSinc2ExtTrigger1 = 251|0x10000U, /**< XBAR1_OUT251 output assigned to SINC2_EXT_TRIGGER1 */ - kXBAR1_OutputSinc2ExtTrigger2 = 252|0x10000U, /**< XBAR1_OUT252 output assigned to SINC2_EXT_TRIGGER2 */ - kXBAR1_OutputSinc2ExtTrigger3 = 253|0x10000U, /**< XBAR1_OUT253 output assigned to SINC2_EXT_TRIGGER3 */ - kXBAR1_OutputSinc3ExtTrigger0 = 254|0x10000U, /**< XBAR1_OUT254 output assigned to SINC3_EXT_TRIGGER0 */ - kXBAR1_OutputSinc3ExtTrigger1 = 255|0x10000U, /**< XBAR1_OUT255 output assigned to SINC3_EXT_TRIGGER1 */ - kXBAR2_OutputAoi1In00 = 0|0x20000U, /**< XBAR2_OUT0 output assigned to AOI1_IN00 */ - kXBAR2_OutputAoi1In01 = 1|0x20000U, /**< XBAR2_OUT1 output assigned to AOI1_IN01 */ - kXBAR2_OutputAoi1In02 = 2|0x20000U, /**< XBAR2_OUT2 output assigned to AOI1_IN02 */ - kXBAR2_OutputAoi1In03 = 3|0x20000U, /**< XBAR2_OUT3 output assigned to AOI1_IN03 */ - kXBAR2_OutputAoi1In04 = 4|0x20000U, /**< XBAR2_OUT4 output assigned to AOI1_IN04 */ - kXBAR2_OutputAoi1In05 = 5|0x20000U, /**< XBAR2_OUT5 output assigned to AOI1_IN05 */ - kXBAR2_OutputAoi1In06 = 6|0x20000U, /**< XBAR2_OUT6 output assigned to AOI1_IN06 */ - kXBAR2_OutputAoi1In07 = 7|0x20000U, /**< XBAR2_OUT7 output assigned to AOI1_IN07 */ - kXBAR2_OutputAoi1In08 = 8|0x20000U, /**< XBAR2_OUT8 output assigned to AOI1_IN08 */ - kXBAR2_OutputAoi1In09 = 9|0x20000U, /**< XBAR2_OUT9 output assigned to AOI1_IN09 */ - kXBAR2_OutputAoi1In10 = 10|0x20000U, /**< XBAR2_OUT10 output assigned to AOI1_IN10 */ - kXBAR2_OutputAoi1In11 = 11|0x20000U, /**< XBAR2_OUT11 output assigned to AOI1_IN11 */ - kXBAR2_OutputAoi1In12 = 12|0x20000U, /**< XBAR2_OUT12 output assigned to AOI1_IN12 */ - kXBAR2_OutputAoi1In13 = 13|0x20000U, /**< XBAR2_OUT13 output assigned to AOI1_IN13 */ - kXBAR2_OutputAoi1In14 = 14|0x20000U, /**< XBAR2_OUT14 output assigned to AOI1_IN14 */ - kXBAR2_OutputAoi1In15 = 15|0x20000U, /**< XBAR2_OUT15 output assigned to AOI1_IN15 */ - kXBAR2_OutputAoi3In00 = 16|0x20000U, /**< XBAR2_OUT16 output assigned to AOI3_IN00 */ - kXBAR2_OutputAoi3In01 = 17|0x20000U, /**< XBAR2_OUT17 output assigned to AOI3_IN01 */ - kXBAR2_OutputAoi3In02 = 18|0x20000U, /**< XBAR2_OUT18 output assigned to AOI3_IN02 */ - kXBAR2_OutputAoi3In03 = 19|0x20000U, /**< XBAR2_OUT19 output assigned to AOI3_IN03 */ - kXBAR2_OutputAoi3In04 = 20|0x20000U, /**< XBAR2_OUT20 output assigned to AOI3_IN04 */ - kXBAR2_OutputAoi3In05 = 21|0x20000U, /**< XBAR2_OUT21 output assigned to AOI3_IN05 */ - kXBAR2_OutputAoi3In06 = 22|0x20000U, /**< XBAR2_OUT22 output assigned to AOI3_IN06 */ - kXBAR2_OutputAoi3In07 = 23|0x20000U, /**< XBAR2_OUT23 output assigned to AOI3_IN07 */ - kXBAR2_OutputAoi3In08 = 24|0x20000U, /**< XBAR2_OUT24 output assigned to AOI3_IN08 */ - kXBAR2_OutputAoi3In09 = 25|0x20000U, /**< XBAR2_OUT25 output assigned to AOI3_IN09 */ - kXBAR2_OutputAoi3In10 = 26|0x20000U, /**< XBAR2_OUT26 output assigned to AOI3_IN10 */ - kXBAR2_OutputAoi3In11 = 27|0x20000U, /**< XBAR2_OUT27 output assigned to AOI3_IN11 */ - kXBAR2_OutputAoi3In12 = 28|0x20000U, /**< XBAR2_OUT28 output assigned to AOI3_IN12 */ - kXBAR2_OutputAoi3In13 = 29|0x20000U, /**< XBAR2_OUT29 output assigned to AOI3_IN13 */ - kXBAR2_OutputAoi3In14 = 30|0x20000U, /**< XBAR2_OUT30 output assigned to AOI3_IN14 */ - kXBAR2_OutputAoi3In15 = 31|0x20000U, /**< XBAR2_OUT31 output assigned to AOI3_IN15 */ - kXBAR3_OutputAoi2In00 = 0|0x30000U, /**< XBAR3_OUT0 output assigned to AOI2_IN00 */ - kXBAR3_OutputAoi2In01 = 1|0x30000U, /**< XBAR3_OUT1 output assigned to AOI2_IN01 */ - kXBAR3_OutputAoi2In02 = 2|0x30000U, /**< XBAR3_OUT2 output assigned to AOI2_IN02 */ - kXBAR3_OutputAoi2In03 = 3|0x30000U, /**< XBAR3_OUT3 output assigned to AOI2_IN03 */ - kXBAR3_OutputAoi2In04 = 4|0x30000U, /**< XBAR3_OUT4 output assigned to AOI2_IN04 */ - kXBAR3_OutputAoi2In05 = 5|0x30000U, /**< XBAR3_OUT5 output assigned to AOI2_IN05 */ - kXBAR3_OutputAoi2In06 = 6|0x30000U, /**< XBAR3_OUT6 output assigned to AOI2_IN06 */ - kXBAR3_OutputAoi2In07 = 7|0x30000U, /**< XBAR3_OUT7 output assigned to AOI2_IN07 */ - kXBAR3_OutputAoi2In08 = 8|0x30000U, /**< XBAR3_OUT8 output assigned to AOI2_IN08 */ - kXBAR3_OutputAoi2In09 = 9|0x30000U, /**< XBAR3_OUT9 output assigned to AOI2_IN09 */ - kXBAR3_OutputAoi2In10 = 10|0x30000U, /**< XBAR3_OUT10 output assigned to AOI2_IN10 */ - kXBAR3_OutputAoi2In11 = 11|0x30000U, /**< XBAR3_OUT11 output assigned to AOI2_IN11 */ - kXBAR3_OutputAoi2In12 = 12|0x30000U, /**< XBAR3_OUT12 output assigned to AOI2_IN12 */ - kXBAR3_OutputAoi2In13 = 13|0x30000U, /**< XBAR3_OUT13 output assigned to AOI2_IN13 */ - kXBAR3_OutputAoi2In14 = 14|0x30000U, /**< XBAR3_OUT14 output assigned to AOI2_IN14 */ - kXBAR3_OutputAoi2In15 = 15|0x30000U, /**< XBAR3_OUT15 output assigned to AOI2_IN15 */ - kXBAR3_OutputAoi4In00 = 16|0x30000U, /**< XBAR3_OUT16 output assigned to AOI4_IN00 */ - kXBAR3_OutputAoi4In01 = 17|0x30000U, /**< XBAR3_OUT17 output assigned to AOI4_IN01 */ - kXBAR3_OutputAoi4In02 = 18|0x30000U, /**< XBAR3_OUT18 output assigned to AOI4_IN02 */ - kXBAR3_OutputAoi4In03 = 19|0x30000U, /**< XBAR3_OUT19 output assigned to AOI4_IN03 */ - kXBAR3_OutputAoi4In04 = 20|0x30000U, /**< XBAR3_OUT20 output assigned to AOI4_IN04 */ - kXBAR3_OutputAoi4In05 = 21|0x30000U, /**< XBAR3_OUT21 output assigned to AOI4_IN05 */ - kXBAR3_OutputAoi4In06 = 22|0x30000U, /**< XBAR3_OUT22 output assigned to AOI4_IN06 */ - kXBAR3_OutputAoi4In07 = 23|0x30000U, /**< XBAR3_OUT23 output assigned to AOI4_IN07 */ - kXBAR3_OutputAoi4In08 = 24|0x30000U, /**< XBAR3_OUT24 output assigned to AOI4_IN08 */ - kXBAR3_OutputAoi4In09 = 25|0x30000U, /**< XBAR3_OUT25 output assigned to AOI4_IN09 */ - kXBAR3_OutputAoi4In10 = 26|0x30000U, /**< XBAR3_OUT26 output assigned to AOI4_IN10 */ - kXBAR3_OutputAoi4In11 = 27|0x30000U, /**< XBAR3_OUT27 output assigned to AOI4_IN11 */ - kXBAR3_OutputAoi4In12 = 28|0x30000U, /**< XBAR3_OUT28 output assigned to AOI4_IN12 */ - kXBAR3_OutputAoi4In13 = 29|0x30000U, /**< XBAR3_OUT29 output assigned to AOI4_IN13 */ - kXBAR3_OutputAoi4In14 = 30|0x30000U, /**< XBAR3_OUT30 output assigned to AOI4_IN14 */ - kXBAR3_OutputAoi4In15 = 31|0x30000U, /**< XBAR3_OUT31 output assigned to AOI4_IN15 */ -} xbar_output_signal_t; -#endif /* XBAR_OUTPUT_SIGNAL_T_ */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -1428,5 +336,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* XBAR2_H_ */ +#endif /* PERI_XBAR2_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR3.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR3.h index 8347ac481..ac106ed44 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR3.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XBAR3.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBAR3 @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file XBAR3.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_XBAR3.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for XBAR3 * * CMSIS Peripheral Access Layer for XBAR3 */ -#if !defined(XBAR3_H_) -#define XBAR3_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_XBAR3_H_) +#define PERI_XBAR3_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -187,1101 +190,6 @@ #error "No valid CPU defined!" #endif -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -#if !defined(XBAR_INPUT_SIGNAL_T_) -#define XBAR_INPUT_SIGNAL_T_ -typedef enum _xbar_input_signal -{ - kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ - kXBAR1_InputLogicHigh = 1|0x10000U, /**< LOGIC_HIGH output assigned to XBAR1_IN1 input. */ - kXBAR1_InputLogicLow1 = 2|0x10000U, /**< LOGIC_LOW1 output assigned to XBAR1_IN2 input. */ - kXBAR1_InputLogicHigh1 = 3|0x10000U, /**< LOGIC_HIGH1 output assigned to XBAR1_IN3 input. */ - kXBAR1_InputIomuxXbarIn04 = 4|0x10000U, /**< IOMUX_XBAR_IN04 output assigned to XBAR1_IN4 input. */ - kXBAR1_InputIomuxXbarIn05 = 5|0x10000U, /**< IOMUX_XBAR_IN05 output assigned to XBAR1_IN5 input. */ - kXBAR1_InputIomuxXbarIn06 = 6|0x10000U, /**< IOMUX_XBAR_IN06 output assigned to XBAR1_IN6 input. */ - kXBAR1_InputIomuxXbarIn07 = 7|0x10000U, /**< IOMUX_XBAR_IN07 output assigned to XBAR1_IN7 input. */ - kXBAR1_InputIomuxXbarIn08 = 8|0x10000U, /**< IOMUX_XBAR_IN08 output assigned to XBAR1_IN8 input. */ - kXBAR1_InputIomuxXbarIn09 = 9|0x10000U, /**< IOMUX_XBAR_IN09 output assigned to XBAR1_IN9 input. */ - kXBAR1_InputIomuxXbarIn10 = 10|0x10000U, /**< IOMUX_XBAR_IN10 output assigned to XBAR1_IN10 input. */ - kXBAR1_InputIomuxXbarIn11 = 11|0x10000U, /**< IOMUX_XBAR_IN11 output assigned to XBAR1_IN11 input. */ - kXBAR1_InputIomuxXbarIn12 = 12|0x10000U, /**< IOMUX_XBAR_IN12 output assigned to XBAR1_IN12 input. */ - kXBAR1_InputIomuxXbarIn13 = 13|0x10000U, /**< IOMUX_XBAR_IN13 output assigned to XBAR1_IN13 input. */ - kXBAR1_InputIomuxXbarIn14 = 14|0x10000U, /**< IOMUX_XBAR_IN14 output assigned to XBAR1_IN14 input. */ - kXBAR1_InputIomuxXbarIn15 = 15|0x10000U, /**< IOMUX_XBAR_IN15 output assigned to XBAR1_IN15 input. */ - kXBAR1_InputIomuxXbarIn16 = 16|0x10000U, /**< IOMUX_XBAR_IN16 output assigned to XBAR1_IN16 input. */ - kXBAR1_InputIomuxXbarIn17 = 17|0x10000U, /**< IOMUX_XBAR_IN17 output assigned to XBAR1_IN17 input. */ - kXBAR1_InputIomuxXbarIn18 = 18|0x10000U, /**< IOMUX_XBAR_IN18 output assigned to XBAR1_IN18 input. */ - kXBAR1_InputIomuxXbarIn19 = 19|0x10000U, /**< IOMUX_XBAR_IN19 output assigned to XBAR1_IN19 input. */ - kXBAR1_InputIomuxXbarIn20 = 20|0x10000U, /**< IOMUX_XBAR_IN20 output assigned to XBAR1_IN20 input. */ - kXBAR1_InputIomuxXbarIn21 = 21|0x10000U, /**< IOMUX_XBAR_IN21 output assigned to XBAR1_IN21 input. */ - kXBAR1_InputIomuxXbarIn22 = 22|0x10000U, /**< IOMUX_XBAR_IN22 output assigned to XBAR1_IN22 input. */ - kXBAR1_InputIomuxXbarIn23 = 23|0x10000U, /**< IOMUX_XBAR_IN23 output assigned to XBAR1_IN23 input. */ - kXBAR1_InputIomuxXbarIn24 = 24|0x10000U, /**< IOMUX_XBAR_IN24 output assigned to XBAR1_IN24 input. */ - kXBAR1_InputIomuxXbarIn25 = 25|0x10000U, /**< IOMUX_XBAR_IN25 output assigned to XBAR1_IN25 input. */ - kXBAR1_InputIomuxXbarIn26 = 26|0x10000U, /**< IOMUX_XBAR_IN26 output assigned to XBAR1_IN26 input. */ - kXBAR1_InputIomuxXbarIn27 = 27|0x10000U, /**< IOMUX_XBAR_IN27 output assigned to XBAR1_IN27 input. */ - kXBAR1_InputIomuxXbarIn28 = 28|0x10000U, /**< IOMUX_XBAR_IN28 output assigned to XBAR1_IN28 input. */ - kXBAR1_InputIomuxXbarIn29 = 29|0x10000U, /**< IOMUX_XBAR_IN29 output assigned to XBAR1_IN29 input. */ - kXBAR1_InputIomuxXbarIn30 = 30|0x10000U, /**< IOMUX_XBAR_IN30 output assigned to XBAR1_IN30 input. */ - kXBAR1_InputIomuxXbarIn31 = 31|0x10000U, /**< IOMUX_XBAR_IN31 output assigned to XBAR1_IN31 input. */ - kXBAR1_InputIomuxXbarIn32 = 32|0x10000U, /**< IOMUX_XBAR_IN32 output assigned to XBAR1_IN32 input. */ - kXBAR1_InputIomuxXbarIn33 = 33|0x10000U, /**< IOMUX_XBAR_IN33 output assigned to XBAR1_IN33 input. */ - kXBAR1_InputIomuxXbarIn34 = 34|0x10000U, /**< IOMUX_XBAR_IN34 output assigned to XBAR1_IN34 input. */ - kXBAR1_InputIomuxXbarIn35 = 35|0x10000U, /**< IOMUX_XBAR_IN35 output assigned to XBAR1_IN35 input. */ - kXBAR1_InputIomuxXbarIn36 = 36|0x10000U, /**< IOMUX_XBAR_IN36 output assigned to XBAR1_IN36 input. */ - kXBAR1_InputIomuxXbarIn37 = 37|0x10000U, /**< IOMUX_XBAR_IN37 output assigned to XBAR1_IN37 input. */ - kXBAR1_InputIomuxXbarIn38 = 38|0x10000U, /**< IOMUX_XBAR_IN38 output assigned to XBAR1_IN38 input. */ - kXBAR1_InputIomuxXbarIn39 = 39|0x10000U, /**< IOMUX_XBAR_IN39 output assigned to XBAR1_IN39 input. */ - kXBAR1_InputIomuxXbarIn40 = 40|0x10000U, /**< IOMUX_XBAR_IN40 output assigned to XBAR1_IN40 input. */ - kXBAR1_InputIomuxXbarIn41 = 41|0x10000U, /**< IOMUX_XBAR_IN41 output assigned to XBAR1_IN41 input. */ - kXBAR1_InputIomuxXbarIn42 = 42|0x10000U, /**< IOMUX_XBAR_IN42 output assigned to XBAR1_IN42 input. */ - kXBAR1_InputIomuxXbarIn43 = 43|0x10000U, /**< IOMUX_XBAR_IN43 output assigned to XBAR1_IN43 input. */ - kXBAR1_InputIomuxXbarIn44 = 44|0x10000U, /**< IOMUX_XBAR_IN44 output assigned to XBAR1_IN44 input. */ - kXBAR1_InputIomuxXbarIn45 = 45|0x10000U, /**< IOMUX_XBAR_IN45 output assigned to XBAR1_IN45 input. */ - kXBAR1_InputIomuxXbarIn46 = 46|0x10000U, /**< IOMUX_XBAR_IN46 output assigned to XBAR1_IN46 input. */ - kXBAR1_InputIomuxXbarIn47 = 47|0x10000U, /**< IOMUX_XBAR_IN47 output assigned to XBAR1_IN47 input. */ - kXBAR1_InputIomuxXbarIn48 = 48|0x10000U, /**< IOMUX_XBAR_IN48 output assigned to XBAR1_IN48 input. */ - kXBAR1_InputQtimer1Timer0 = 49|0x10000U, /**< QTIMER1_TIMER0 output assigned to XBAR1_IN49 input. */ - kXBAR1_InputQtimer1Timer1 = 50|0x10000U, /**< QTIMER1_TIMER1 output assigned to XBAR1_IN50 input. */ - kXBAR1_InputQtimer1Timer2 = 51|0x10000U, /**< QTIMER1_TIMER2 output assigned to XBAR1_IN51 input. */ - kXBAR1_InputQtimer1Timer3 = 52|0x10000U, /**< QTIMER1_TIMER3 output assigned to XBAR1_IN52 input. */ - kXBAR1_InputQtimer2Timer0 = 53|0x10000U, /**< QTIMER2_TIMER0 output assigned to XBAR1_IN53 input. */ - kXBAR1_InputQtimer2Timer1 = 54|0x10000U, /**< QTIMER2_TIMER1 output assigned to XBAR1_IN54 input. */ - kXBAR1_InputQtimer2Timer2 = 55|0x10000U, /**< QTIMER2_TIMER2 output assigned to XBAR1_IN55 input. */ - kXBAR1_InputQtimer2Timer3 = 56|0x10000U, /**< QTIMER2_TIMER3 output assigned to XBAR1_IN56 input. */ - kXBAR1_InputQtimer3Timer0 = 57|0x10000U, /**< QTIMER3_TIMER0 output assigned to XBAR1_IN57 input. */ - kXBAR1_InputQtimer3Timer1 = 58|0x10000U, /**< QTIMER3_TIMER1 output assigned to XBAR1_IN58 input. */ - kXBAR1_InputQtimer3Timer2 = 59|0x10000U, /**< QTIMER3_TIMER2 output assigned to XBAR1_IN59 input. */ - kXBAR1_InputQtimer3Timer3 = 60|0x10000U, /**< QTIMER3_TIMER3 output assigned to XBAR1_IN60 input. */ - kXBAR1_InputQtimer4Timer0 = 61|0x10000U, /**< QTIMER4_TIMER0 output assigned to XBAR1_IN61 input. */ - kXBAR1_InputQtimer4Timer1 = 62|0x10000U, /**< QTIMER4_TIMER1 output assigned to XBAR1_IN62 input. */ - kXBAR1_InputQtimer4Timer2 = 63|0x10000U, /**< QTIMER4_TIMER2 output assigned to XBAR1_IN63 input. */ - kXBAR1_InputQtimer4Timer3 = 64|0x10000U, /**< QTIMER4_TIMER3 output assigned to XBAR1_IN64 input. */ - kXBAR1_InputQtimer5Timer0 = 65|0x10000U, /**< QTIMER5_TIMER0 output assigned to XBAR1_IN65 input. */ - kXBAR1_InputQtimer5Timer1 = 66|0x10000U, /**< QTIMER5_TIMER1 output assigned to XBAR1_IN66 input. */ - kXBAR1_InputQtimer5Timer2 = 67|0x10000U, /**< QTIMER5_TIMER2 output assigned to XBAR1_IN67 input. */ - kXBAR1_InputQtimer5Timer3 = 68|0x10000U, /**< QTIMER5_TIMER3 output assigned to XBAR1_IN68 input. */ - kXBAR1_InputQtimer6Timer0 = 69|0x10000U, /**< QTIMER6_TIMER0 output assigned to XBAR1_IN69 input. */ - kXBAR1_InputQtimer6Timer1 = 70|0x10000U, /**< QTIMER6_TIMER1 output assigned to XBAR1_IN70 input. */ - kXBAR1_InputQtimer6Timer2 = 71|0x10000U, /**< QTIMER6_TIMER2 output assigned to XBAR1_IN71 input. */ - kXBAR1_InputQtimer6Timer3 = 72|0x10000U, /**< QTIMER6_TIMER3 output assigned to XBAR1_IN72 input. */ - kXBAR1_InputQtimer7Timer0 = 73|0x10000U, /**< QTIMER7_TIMER0 output assigned to XBAR1_IN73 input. */ - kXBAR1_InputQtimer7Timer1 = 74|0x10000U, /**< QTIMER7_TIMER1 output assigned to XBAR1_IN74 input. */ - kXBAR1_InputQtimer7Timer2 = 75|0x10000U, /**< QTIMER7_TIMER2 output assigned to XBAR1_IN75 input. */ - kXBAR1_InputQtimer7Timer3 = 76|0x10000U, /**< QTIMER7_TIMER3 output assigned to XBAR1_IN76 input. */ - kXBAR1_InputQtimer8Timer0 = 77|0x10000U, /**< QTIMER8_TIMER0 output assigned to XBAR1_IN77 input. */ - kXBAR1_InputQtimer8Timer1 = 78|0x10000U, /**< QTIMER8_TIMER1 output assigned to XBAR1_IN78 input. */ - kXBAR1_InputQtimer8Timer2 = 79|0x10000U, /**< QTIMER8_TIMER2 output assigned to XBAR1_IN79 input. */ - kXBAR1_InputQtimer8Timer3 = 80|0x10000U, /**< QTIMER8_TIMER3 output assigned to XBAR1_IN80 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger0 = 81|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR1_IN81 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger0 = 82|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER0 output assigned to XBAR1_IN82 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger1 = 83|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR1_IN83 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger1 = 84|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER1 output assigned to XBAR1_IN84 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger2 = 85|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR1_IN85 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger2 = 86|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER2 output assigned to XBAR1_IN86 input. */ - kXBAR1_InputFlexpwm1Mux0Trigger3 = 87|0x10000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR1_IN87 input. */ - kXBAR1_InputFlexpwm1Mux1Trigger3 = 88|0x10000U, /**< FLEXPWM1_MUX1_TRIGGER3 output assigned to XBAR1_IN88 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger0 = 89|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR1_IN89 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger0 = 90|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER0 output assigned to XBAR1_IN90 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger1 = 91|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR1_IN91 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger1 = 92|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER1 output assigned to XBAR1_IN92 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger2 = 93|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR1_IN93 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger2 = 94|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER2 output assigned to XBAR1_IN94 input. */ - kXBAR1_InputFlexpwm2Mux0Trigger3 = 95|0x10000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR1_IN95 input. */ - kXBAR1_InputFlexpwm2Mux1Trigger3 = 96|0x10000U, /**< FLEXPWM2_MUX1_TRIGGER3 output assigned to XBAR1_IN96 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger0 = 97|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR1_IN97 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger0 = 98|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER0 output assigned to XBAR1_IN98 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger1 = 99|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR1_IN99 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger1 = 100|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER1 output assigned to XBAR1_IN100 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger2 = 101|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR1_IN101 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger2 = 102|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER2 output assigned to XBAR1_IN102 input. */ - kXBAR1_InputFlexpwm3Mux0Trigger3 = 103|0x10000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR1_IN103 input. */ - kXBAR1_InputFlexpwm3Mux1Trigger3 = 104|0x10000U, /**< FLEXPWM3_MUX1_TRIGGER3 output assigned to XBAR1_IN104 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger0 = 105|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR1_IN105 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger0 = 106|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER0 output assigned to XBAR1_IN106 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger1 = 107|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR1_IN107 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger1 = 108|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER1 output assigned to XBAR1_IN108 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger2 = 109|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR1_IN109 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger2 = 110|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER2 output assigned to XBAR1_IN110 input. */ - kXBAR1_InputFlexpwm4Mux0Trigger3 = 111|0x10000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR1_IN111 input. */ - kXBAR1_InputFlexpwm4Mux1Trigger3 = 112|0x10000U, /**< FLEXPWM4_MUX1_TRIGGER3 output assigned to XBAR1_IN112 input. */ - kXBAR1_InputLpit1LpitTrigOut0 = 113|0x10000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR1_IN113 input. */ - kXBAR1_InputLpit1LpitTrigOut1 = 114|0x10000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR1_IN114 input. */ - kXBAR1_InputLpit1LpitTrigOut2 = 115|0x10000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR1_IN115 input. */ - kXBAR1_InputLpit1LpitTrigOut3 = 116|0x10000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR1_IN116 input. */ - kXBAR1_InputLpit2LpitTrigOut0 = 117|0x10000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR1_IN117 input. */ - kXBAR1_InputLpit2LpitTrigOut1 = 118|0x10000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR1_IN118 input. */ - kXBAR1_InputLpit2LpitTrigOut2 = 119|0x10000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR1_IN119 input. */ - kXBAR1_InputLpit2LpitTrigOut3 = 120|0x10000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR1_IN120 input. */ - kXBAR1_InputLpit3LpitTrigOut0 = 121|0x10000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR1_IN121 input. */ - kXBAR1_InputLpit3LpitTrigOut1 = 122|0x10000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR1_IN122 input. */ - kXBAR1_InputLpit3LpitTrigOut2 = 123|0x10000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR1_IN123 input. */ - kXBAR1_InputLpit3LpitTrigOut3 = 124|0x10000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR1_IN124 input. */ - kXBAR1_InputTriggerSyncSyncOut0 = 125|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT0 output assigned to XBAR1_IN125 input. */ - kXBAR1_InputTriggerSyncSyncOut1 = 126|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT1 output assigned to XBAR1_IN126 input. */ - kXBAR1_InputTriggerSyncSyncOut2 = 127|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT2 output assigned to XBAR1_IN127 input. */ - kXBAR1_InputTriggerSyncSyncOut3 = 128|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT3 output assigned to XBAR1_IN128 input. */ - kXBAR1_InputEdma2DmaTriggerOut0 = 129|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN129 input. */ - kXBAR1_InputEdma2DmaTriggerOut1 = 130|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN130 input. */ - kXBAR1_InputEdma2DmaTriggerOut2 = 131|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN131 input. */ - kXBAR1_InputEdma2DmaTriggerOut3 = 132|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN132 input. */ - kXBAR1_InputEdma2DmaTriggerOut4 = 133|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN133 input. */ - kXBAR1_InputEdma2DmaTriggerOut5 = 134|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN134 input. */ - kXBAR1_InputEdma2DmaTriggerOut6 = 135|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN135 input. */ - kXBAR1_InputEdma2DmaTriggerOut7 = 136|0x10000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN136 input. */ - kXBAR1_InputEdma1DmaTriggerOut0 = 137|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN137 input. */ - kXBAR1_InputEdma1DmaTriggerOut1 = 138|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN138 input. */ - kXBAR1_InputEdma1DmaTriggerOut2 = 139|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN139 input. */ - kXBAR1_InputEdma1DmaTriggerOut3 = 140|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN140 input. */ - kXBAR1_InputEdma1DmaTriggerOut4 = 141|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN141 input. */ - kXBAR1_InputEdma1DmaTriggerOut5 = 142|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN142 input. */ - kXBAR1_InputEdma1DmaTriggerOut6 = 143|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN143 input. */ - kXBAR1_InputEdma1DmaTriggerOut7 = 144|0x10000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN144 input. */ - kXBAR1_InputEdma3DmaTriggerOut0 = 145|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN145 input. */ - kXBAR1_InputEdma3DmaTriggerOut1 = 146|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN146 input. */ - kXBAR1_InputEdma3DmaTriggerOut2 = 147|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN147 input. */ - kXBAR1_InputEdma3DmaTriggerOut3 = 148|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN148 input. */ - kXBAR1_InputEdma3DmaTriggerOut4 = 149|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN149 input. */ - kXBAR1_InputEdma3DmaTriggerOut5 = 150|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN150 input. */ - kXBAR1_InputEdma3DmaTriggerOut6 = 151|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN151 input. */ - kXBAR1_InputEdma3DmaTriggerOut7 = 152|0x10000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN152 input. */ - kXBAR1_InputEdma4DmaTriggerOut0 = 153|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR1_IN153 input. */ - kXBAR1_InputEdma4DmaTriggerOut1 = 154|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR1_IN154 input. */ - kXBAR1_InputEdma4DmaTriggerOut2 = 155|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR1_IN155 input. */ - kXBAR1_InputEdma4DmaTriggerOut3 = 156|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR1_IN156 input. */ - kXBAR1_InputEdma4DmaTriggerOut4 = 157|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR1_IN157 input. */ - kXBAR1_InputEdma4DmaTriggerOut5 = 158|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR1_IN158 input. */ - kXBAR1_InputEdma4DmaTriggerOut6 = 159|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR1_IN159 input. */ - kXBAR1_InputEdma4DmaTriggerOut7 = 160|0x10000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR1_IN160 input. */ - kXBAR1_InputAdc1IpiIntEoc = 161|0x10000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR1_IN161 input. */ - kXBAR1_InputAdc1IpiIntWd = 162|0x10000U, /**< ADC1_IPI_INT_WD output assigned to XBAR1_IN162 input. */ - kXBAR1_InputTpm1LptpmChTrigger0 = 163|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN163 input. */ - kXBAR1_InputTpm1LptpmChTrigger1 = 164|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN164 input. */ - kXBAR1_InputTpm1LptpmChTrigger2 = 165|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN165 input. */ - kXBAR1_InputTpm1LptpmChTrigger3 = 166|0x10000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN166 input. */ - kXBAR1_InputTpm1LptpmTrigger = 167|0x10000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR1_IN167 input. */ - kXBAR1_InputTpm2LptpmChTrigger0 = 168|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN168 input. */ - kXBAR1_InputTpm2LptpmChTrigger1 = 169|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN169 input. */ - kXBAR1_InputTpm2LptpmChTrigger2 = 170|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN170 input. */ - kXBAR1_InputTpm2LptpmChTrigger3 = 171|0x10000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN171 input. */ - kXBAR1_InputTpm2LptpmTrigger = 172|0x10000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR1_IN172 input. */ - kXBAR1_InputTpm3LptpmChTrigger0 = 173|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN173 input. */ - kXBAR1_InputTpm3LptpmChTrigger1 = 174|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN174 input. */ - kXBAR1_InputTpm3LptpmChTrigger2 = 175|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN175 input. */ - kXBAR1_InputTpm3LptpmChTrigger3 = 176|0x10000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN176 input. */ - kXBAR1_InputTpm3LptpmTrigger = 177|0x10000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR1_IN177 input. */ - kXBAR1_InputTpm4LptpmChTrigger0 = 178|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN178 input. */ - kXBAR1_InputTpm4LptpmChTrigger1 = 179|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN179 input. */ - kXBAR1_InputTpm4LptpmChTrigger2 = 180|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN180 input. */ - kXBAR1_InputTpm4LptpmChTrigger3 = 181|0x10000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN181 input. */ - kXBAR1_InputTpm4LptpmTrigger = 182|0x10000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR1_IN182 input. */ - kXBAR1_InputTpm5LptpmChTrigger0 = 183|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN183 input. */ - kXBAR1_InputTpm5LptpmChTrigger1 = 184|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN184 input. */ - kXBAR1_InputTpm5LptpmChTrigger2 = 185|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN185 input. */ - kXBAR1_InputTpm5LptpmChTrigger3 = 186|0x10000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN186 input. */ - kXBAR1_InputTpm5LptpmTrigger = 187|0x10000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR1_IN187 input. */ - kXBAR1_InputTpm6LptpmChTrigger0 = 188|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR1_IN188 input. */ - kXBAR1_InputTpm6LptpmChTrigger1 = 189|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR1_IN189 input. */ - kXBAR1_InputTpm6LptpmChTrigger2 = 190|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR1_IN190 input. */ - kXBAR1_InputTpm6LptpmChTrigger3 = 191|0x10000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR1_IN191 input. */ - kXBAR1_InputTpm6LptpmTrigger = 192|0x10000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR1_IN192 input. */ - kXBAR1_InputLptmr1LptimerTriggerDelay = 193|0x10000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN193 input. */ - kXBAR1_InputLptmr2LptimerTriggerDelay = 194|0x10000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR1_IN194 input. */ - kXBAR1_InputLogicLow2 = 195|0x10000U, /**< LOGIC_LOW2 output assigned to XBAR1_IN195 input. */ - kXBAR1_InputNetcTmr11588Pp1 = 196|0x10000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR1_IN196 input. */ - kXBAR1_InputNetcTmr11588Pp2 = 197|0x10000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR1_IN197 input. */ - kXBAR1_InputNetcTmr11588Pp3 = 198|0x10000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR1_IN198 input. */ - kXBAR1_InputNetcTmr11588Alarm1 = 199|0x10000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR1_IN199 input. */ - kXBAR1_InputNetcTmr11588Alarm2 = 200|0x10000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR1_IN200 input. */ - kXBAR1_InputNetcTmr21588Pp1 = 201|0x10000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR1_IN201 input. */ - kXBAR1_InputNetcTmr21588Pp2 = 202|0x10000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR1_IN202 input. */ - kXBAR1_InputNetcTmr21588Pp3 = 203|0x10000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR1_IN203 input. */ - kXBAR1_InputNetcTmr21588Alarm1 = 204|0x10000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR1_IN204 input. */ - kXBAR1_InputNetcTmr21588Alarm2 = 205|0x10000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR1_IN205 input. */ - kXBAR1_InputNetcTmr31588Pp1 = 206|0x10000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR1_IN206 input. */ - kXBAR1_InputNetcTmr31588Pp2 = 207|0x10000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR1_IN207 input. */ - kXBAR1_InputNetcTmr31588Pp3 = 208|0x10000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR1_IN208 input. */ - kXBAR1_InputNetcTmr31588Alarm1 = 209|0x10000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR1_IN209 input. */ - kXBAR1_InputNetcTmr31588Alarm2 = 210|0x10000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR1_IN210 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak0 = 211|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR1_IN211 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak1 = 212|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR1_IN212 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak2 = 213|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR1_IN213 input. */ - kXBAR1_InputSincFilterGlue1IppDoBreak3 = 214|0x10000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR1_IN214 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak0 = 215|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR1_IN215 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak1 = 216|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR1_IN216 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak2 = 217|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR1_IN217 input. */ - kXBAR1_InputSincFilterGlue2IppDoBreak3 = 218|0x10000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR1_IN218 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak0 = 219|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR1_IN219 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak1 = 220|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR1_IN220 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak2 = 221|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR1_IN221 input. */ - kXBAR1_InputSincFilterGlue3IppDoBreak3 = 222|0x10000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR1_IN222 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak0 = 223|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR1_IN223 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak1 = 224|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR1_IN224 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak2 = 225|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR1_IN225 input. */ - kXBAR1_InputSincFilterGlue4IppDoBreak3 = 226|0x10000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR1_IN226 input. */ - kXBAR1_InputAoi1AoiOut0 = 227|0x10000U, /**< AOI1_AOI_OUT0 output assigned to XBAR1_IN227 input. */ - kXBAR1_InputAoi1AoiOut1 = 228|0x10000U, /**< AOI1_AOI_OUT1 output assigned to XBAR1_IN228 input. */ - kXBAR1_InputAoi1AoiOut2 = 229|0x10000U, /**< AOI1_AOI_OUT2 output assigned to XBAR1_IN229 input. */ - kXBAR1_InputAoi1AoiOut3 = 230|0x10000U, /**< AOI1_AOI_OUT3 output assigned to XBAR1_IN230 input. */ - kXBAR1_InputAoi2AoiOut0 = 231|0x10000U, /**< AOI2_AOI_OUT0 output assigned to XBAR1_IN231 input. */ - kXBAR1_InputAoi2AoiOut1 = 232|0x10000U, /**< AOI2_AOI_OUT1 output assigned to XBAR1_IN232 input. */ - kXBAR1_InputAoi2AoiOut2 = 233|0x10000U, /**< AOI2_AOI_OUT2 output assigned to XBAR1_IN233 input. */ - kXBAR1_InputAoi2AoiOut3 = 234|0x10000U, /**< AOI2_AOI_OUT3 output assigned to XBAR1_IN234 input. */ - kXBAR1_InputTriggerSyncSyncOut4 = 235|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT4 output assigned to XBAR1_IN235 input. */ - kXBAR1_InputTriggerSyncSyncOut5 = 236|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT5 output assigned to XBAR1_IN236 input. */ - kXBAR1_InputTriggerSyncSyncOut6 = 237|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT6 output assigned to XBAR1_IN237 input. */ - kXBAR1_InputTriggerSyncSyncOut7 = 238|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT7 output assigned to XBAR1_IN238 input. */ - kXBAR1_InputAoi3AoiOut0 = 239|0x10000U, /**< AOI3_AOI_OUT0 output assigned to XBAR1_IN239 input. */ - kXBAR1_InputAoi3AoiOut1 = 240|0x10000U, /**< AOI3_AOI_OUT1 output assigned to XBAR1_IN240 input. */ - kXBAR1_InputAoi3AoiOut2 = 241|0x10000U, /**< AOI3_AOI_OUT2 output assigned to XBAR1_IN241 input. */ - kXBAR1_InputAoi3AoiOut3 = 242|0x10000U, /**< AOI3_AOI_OUT3 output assigned to XBAR1_IN242 input. */ - kXBAR1_InputAoi4AoiOut0 = 243|0x10000U, /**< AOI4_AOI_OUT0 output assigned to XBAR1_IN243 input. */ - kXBAR1_InputAoi4AoiOut1 = 244|0x10000U, /**< AOI4_AOI_OUT1 output assigned to XBAR1_IN244 input. */ - kXBAR1_InputAoi4AoiOut2 = 245|0x10000U, /**< AOI4_AOI_OUT2 output assigned to XBAR1_IN245 input. */ - kXBAR1_InputAoi4AoiOut3 = 246|0x10000U, /**< AOI4_AOI_OUT3 output assigned to XBAR1_IN246 input. */ - kXBAR1_InputEcatSyncOut0 = 247|0x10000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR1_IN247 input. */ - kXBAR1_InputEcatSyncOut1 = 248|0x10000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR1_IN248 input. */ - kXBAR1_InputFccuVfccuReactionsOut11 = 249|0x10000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR1_IN249 input. */ - kXBAR1_InputGpt1IppDoCmpout1 = 250|0x10000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR1_IN250 input. */ - kXBAR1_InputGpt1IppDoCmpout2 = 251|0x10000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR1_IN251 input. */ - kXBAR1_InputGpt1IppDoCmpout3 = 252|0x10000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR1_IN252 input. */ - kXBAR1_InputGpt2IppDoCmpout1 = 253|0x10000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR1_IN253 input. */ - kXBAR1_InputGpt2IppDoCmpout2 = 254|0x10000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR1_IN254 input. */ - kXBAR1_InputGpt2IppDoCmpout3 = 255|0x10000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR1_IN255 input. */ - kXBAR1_InputGpt3IppDoCmpout1 = 256|0x10000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR1_IN256 input. */ - kXBAR1_InputGpt3IppDoCmpout2 = 257|0x10000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR1_IN257 input. */ - kXBAR1_InputGpt3IppDoCmpout3 = 258|0x10000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR1_IN258 input. */ - kXBAR1_InputGpt4IppDoCmpout1 = 259|0x10000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR1_IN259 input. */ - kXBAR1_InputGpt4IppDoCmpout2 = 260|0x10000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR1_IN260 input. */ - kXBAR1_InputGpt4IppDoCmpout3 = 261|0x10000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR1_IN261 input. */ - kXBAR1_InputFlexio1FlexioTriggerOut0 = 262|0x10000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN262 input. */ - kXBAR1_InputFlexio2FlexioTriggerOut0 = 263|0x10000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN263 input. */ - kXBAR1_InputFlexio3FlexioTriggerOut0 = 264|0x10000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN264 input. */ - kXBAR1_InputFlexio4FlexioTriggerOut0 = 265|0x10000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR1_IN265 input. */ - kXBAR1_InputGpio1IpiIntRgpio0 = 266|0x10000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR1_IN266 input. */ - kXBAR1_InputGpio2IpiIntRgpio0 = 267|0x10000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR1_IN267 input. */ - kXBAR1_InputGpio3IpiIntRgpio0 = 268|0x10000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR1_IN268 input. */ - kXBAR1_InputGpio4IpiIntRgpio0 = 269|0x10000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR1_IN269 input. */ - kXBAR1_InputGpio5IpiIntRgpio0 = 270|0x10000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR1_IN270 input. */ - kXBAR1_InputGpio6IpiIntRgpio0 = 271|0x10000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR1_IN271 input. */ - kXBAR1_InputGpio7IpiIntRgpio0 = 272|0x10000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR1_IN272 input. */ - kXBAR1_InputCm33Txev = 273|0x10000U, /**< CM33_TXEV output assigned to XBAR1_IN273 input. */ - kXBAR1_InputCm33SyncTxev = 274|0x10000U, /**< CM33_SYNC_TXEV output assigned to XBAR1_IN274 input. */ - kXBAR1_InputEndat21SiN = 275|0x10000U, /**< ENDAT2_1_SI_N output assigned to XBAR1_IN275 input. */ - kXBAR1_InputEndat21TimerN = 276|0x10000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR1_IN276 input. */ - kXBAR1_InputEndat22SiN = 277|0x10000U, /**< ENDAT2_2_SI_N output assigned to XBAR1_IN277 input. */ - kXBAR1_InputEndat22TimerN = 278|0x10000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR1_IN278 input. */ - kXBAR1_InputBissEot = 279|0x10000U, /**< BISS_EOT output assigned to XBAR1_IN279 input. */ - kXBAR1_InputTriggerSyncSyncOut8 = 280|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT8 output assigned to XBAR1_IN280 input. */ - kXBAR1_InputTriggerSyncSyncOut9 = 281|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT9 output assigned to XBAR1_IN281 input. */ - kXBAR1_InputTriggerSyncSyncOut10 = 282|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT10 output assigned to XBAR1_IN282 input. */ - kXBAR1_InputTriggerSyncSyncOut11 = 283|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT11 output assigned to XBAR1_IN283 input. */ - kXBAR1_InputTriggerSyncSyncOut12 = 284|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT12 output assigned to XBAR1_IN284 input. */ - kXBAR1_InputTriggerSyncSyncOut13 = 285|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT13 output assigned to XBAR1_IN285 input. */ - kXBAR1_InputTriggerSyncSyncOut14 = 286|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT14 output assigned to XBAR1_IN286 input. */ - kXBAR1_InputTriggerSyncSyncOut15 = 287|0x10000U, /**< TRIGGER_SYNC_SYNC_OUT15 output assigned to XBAR1_IN287 input. */ - kXBAR1_InputEcatResetOut = 288|0x10000U, /**< ECAT_RESET_OUT output assigned to XBAR1_IN288 input. */ - kXBAR1_InputHiperface1FastPosRcvdEvt = 289|0x10000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR1_IN289 input. */ - kXBAR1_InputHiperface2FastPosRcvdEvt = 290|0x10000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR1_IN290 input. */ - kXBAR2_InputLogicLow = 0|0x20000U, /**< LOGIC_LOW output assigned to XBAR2_IN0 input. */ - kXBAR2_InputLogicHigh = 1|0x20000U, /**< LOGIC_HIGH output assigned to XBAR2_IN1 input. */ - kXBAR2_InputLogicLow1 = 2|0x20000U, /**< LOGIC_LOW1 output assigned to XBAR2_IN2 input. */ - kXBAR2_InputLogicHigh1 = 3|0x20000U, /**< LOGIC_HIGH1 output assigned to XBAR2_IN3 input. */ - kXBAR2_InputQtimer1Timer0 = 4|0x20000U, /**< QTIMER1_TIMER0 output assigned to XBAR2_IN4 input. */ - kXBAR2_InputQtimer1Timer1 = 5|0x20000U, /**< QTIMER1_TIMER1 output assigned to XBAR2_IN5 input. */ - kXBAR2_InputQtimer1Timer2 = 6|0x20000U, /**< QTIMER1_TIMER2 output assigned to XBAR2_IN6 input. */ - kXBAR2_InputQtimer1Timer3 = 7|0x20000U, /**< QTIMER1_TIMER3 output assigned to XBAR2_IN7 input. */ - kXBAR2_InputQtimer2Timer0 = 8|0x20000U, /**< QTIMER2_TIMER0 output assigned to XBAR2_IN8 input. */ - kXBAR2_InputQtimer2Timer1 = 9|0x20000U, /**< QTIMER2_TIMER1 output assigned to XBAR2_IN9 input. */ - kXBAR2_InputQtimer2Timer2 = 10|0x20000U, /**< QTIMER2_TIMER2 output assigned to XBAR2_IN10 input. */ - kXBAR2_InputQtimer2Timer3 = 11|0x20000U, /**< QTIMER2_TIMER3 output assigned to XBAR2_IN11 input. */ - kXBAR2_InputQtimer3Timer0 = 12|0x20000U, /**< QTIMER3_TIMER0 output assigned to XBAR2_IN12 input. */ - kXBAR2_InputQtimer3Timer1 = 13|0x20000U, /**< QTIMER3_TIMER1 output assigned to XBAR2_IN13 input. */ - kXBAR2_InputQtimer3Timer2 = 14|0x20000U, /**< QTIMER3_TIMER2 output assigned to XBAR2_IN14 input. */ - kXBAR2_InputQtimer3Timer3 = 15|0x20000U, /**< QTIMER3_TIMER3 output assigned to XBAR2_IN15 input. */ - kXBAR2_InputQtimer4Timer0 = 16|0x20000U, /**< QTIMER4_TIMER0 output assigned to XBAR2_IN16 input. */ - kXBAR2_InputQtimer4Timer1 = 17|0x20000U, /**< QTIMER4_TIMER1 output assigned to XBAR2_IN17 input. */ - kXBAR2_InputQtimer4Timer2 = 18|0x20000U, /**< QTIMER4_TIMER2 output assigned to XBAR2_IN18 input. */ - kXBAR2_InputQtimer4Timer3 = 19|0x20000U, /**< QTIMER4_TIMER3 output assigned to XBAR2_IN19 input. */ - kXBAR2_InputQtimer5Timer0 = 20|0x20000U, /**< QTIMER5_TIMER0 output assigned to XBAR2_IN20 input. */ - kXBAR2_InputQtimer5Timer1 = 21|0x20000U, /**< QTIMER5_TIMER1 output assigned to XBAR2_IN21 input. */ - kXBAR2_InputQtimer5Timer2 = 22|0x20000U, /**< QTIMER5_TIMER2 output assigned to XBAR2_IN22 input. */ - kXBAR2_InputQtimer5Timer3 = 23|0x20000U, /**< QTIMER5_TIMER3 output assigned to XBAR2_IN23 input. */ - kXBAR2_InputQtimer6Timer0 = 24|0x20000U, /**< QTIMER6_TIMER0 output assigned to XBAR2_IN24 input. */ - kXBAR2_InputQtimer6Timer1 = 25|0x20000U, /**< QTIMER6_TIMER1 output assigned to XBAR2_IN25 input. */ - kXBAR2_InputQtimer6Timer2 = 26|0x20000U, /**< QTIMER6_TIMER2 output assigned to XBAR2_IN26 input. */ - kXBAR2_InputQtimer6Timer3 = 27|0x20000U, /**< QTIMER6_TIMER3 output assigned to XBAR2_IN27 input. */ - kXBAR2_InputQtimer7Timer0 = 28|0x20000U, /**< QTIMER7_TIMER0 output assigned to XBAR2_IN28 input. */ - kXBAR2_InputQtimer7Timer1 = 29|0x20000U, /**< QTIMER7_TIMER1 output assigned to XBAR2_IN29 input. */ - kXBAR2_InputQtimer7Timer2 = 30|0x20000U, /**< QTIMER7_TIMER2 output assigned to XBAR2_IN30 input. */ - kXBAR2_InputQtimer7Timer3 = 31|0x20000U, /**< QTIMER7_TIMER3 output assigned to XBAR2_IN31 input. */ - kXBAR2_InputQtimer8Timer0 = 32|0x20000U, /**< QTIMER8_TIMER0 output assigned to XBAR2_IN32 input. */ - kXBAR2_InputQtimer8Timer1 = 33|0x20000U, /**< QTIMER8_TIMER1 output assigned to XBAR2_IN33 input. */ - kXBAR2_InputQtimer8Timer2 = 34|0x20000U, /**< QTIMER8_TIMER2 output assigned to XBAR2_IN34 input. */ - kXBAR2_InputQtimer8Timer3 = 35|0x20000U, /**< QTIMER8_TIMER3 output assigned to XBAR2_IN35 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger0 = 36|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR2_IN36 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger1 = 37|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR2_IN37 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger2 = 38|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR2_IN38 input. */ - kXBAR2_InputFlexpwm1Mux0Trigger3 = 39|0x20000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR2_IN39 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger0 = 40|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR2_IN40 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger1 = 41|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR2_IN41 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger2 = 42|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR2_IN42 input. */ - kXBAR2_InputFlexpwm2Mux0Trigger3 = 43|0x20000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR2_IN43 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger0 = 44|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR2_IN44 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger1 = 45|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR2_IN45 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger2 = 46|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR2_IN46 input. */ - kXBAR2_InputFlexpwm3Mux0Trigger3 = 47|0x20000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR2_IN47 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger0 = 48|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR2_IN48 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger1 = 49|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR2_IN49 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger2 = 50|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR2_IN50 input. */ - kXBAR2_InputFlexpwm4Mux0Trigger3 = 51|0x20000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR2_IN51 input. */ - kXBAR2_InputLpit1LpitTrigOut0 = 52|0x20000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR2_IN52 input. */ - kXBAR2_InputLpit1LpitTrigOut1 = 53|0x20000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR2_IN53 input. */ - kXBAR2_InputLpit1LpitTrigOut2 = 54|0x20000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR2_IN54 input. */ - kXBAR2_InputLpit1LpitTrigOut3 = 55|0x20000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR2_IN55 input. */ - kXBAR2_InputLpit2LpitTrigOut0 = 56|0x20000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR2_IN56 input. */ - kXBAR2_InputLpit2LpitTrigOut1 = 57|0x20000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR2_IN57 input. */ - kXBAR2_InputLpit2LpitTrigOut2 = 58|0x20000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR2_IN58 input. */ - kXBAR2_InputLpit2LpitTrigOut3 = 59|0x20000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR2_IN59 input. */ - kXBAR2_InputLpit3LpitTrigOut0 = 60|0x20000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR2_IN60 input. */ - kXBAR2_InputLpit3LpitTrigOut1 = 61|0x20000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR2_IN61 input. */ - kXBAR2_InputLpit3LpitTrigOut2 = 62|0x20000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR2_IN62 input. */ - kXBAR2_InputLpit3LpitTrigOut3 = 63|0x20000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR2_IN63 input. */ - kXBAR2_InputEdma2DmaTriggerOut0 = 64|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN64 input. */ - kXBAR2_InputEdma2DmaTriggerOut1 = 65|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN65 input. */ - kXBAR2_InputEdma2DmaTriggerOut2 = 66|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN66 input. */ - kXBAR2_InputEdma2DmaTriggerOut3 = 67|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN67 input. */ - kXBAR2_InputEdma2DmaTriggerOut4 = 68|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN68 input. */ - kXBAR2_InputEdma2DmaTriggerOut5 = 69|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN69 input. */ - kXBAR2_InputEdma2DmaTriggerOut6 = 70|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN70 input. */ - kXBAR2_InputEdma2DmaTriggerOut7 = 71|0x20000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN71 input. */ - kXBAR2_InputEdma1DmaTriggerOut0 = 72|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN72 input. */ - kXBAR2_InputEdma1DmaTriggerOut1 = 73|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN73 input. */ - kXBAR2_InputEdma1DmaTriggerOut2 = 74|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN74 input. */ - kXBAR2_InputEdma1DmaTriggerOut3 = 75|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN75 input. */ - kXBAR2_InputEdma1DmaTriggerOut4 = 76|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN76 input. */ - kXBAR2_InputEdma1DmaTriggerOut5 = 77|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN77 input. */ - kXBAR2_InputEdma1DmaTriggerOut6 = 78|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN78 input. */ - kXBAR2_InputEdma1DmaTriggerOut7 = 79|0x20000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN79 input. */ - kXBAR2_InputEdma3DmaTriggerOut0 = 80|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN80 input. */ - kXBAR2_InputEdma3DmaTriggerOut1 = 81|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN81 input. */ - kXBAR2_InputEdma3DmaTriggerOut2 = 82|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN82 input. */ - kXBAR2_InputEdma3DmaTriggerOut3 = 83|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN83 input. */ - kXBAR2_InputEdma3DmaTriggerOut4 = 84|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN84 input. */ - kXBAR2_InputEdma3DmaTriggerOut5 = 85|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN85 input. */ - kXBAR2_InputEdma3DmaTriggerOut6 = 86|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN86 input. */ - kXBAR2_InputEdma3DmaTriggerOut7 = 87|0x20000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN87 input. */ - kXBAR2_InputEdma4DmaTriggerOut0 = 88|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR2_IN88 input. */ - kXBAR2_InputEdma4DmaTriggerOut1 = 89|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR2_IN89 input. */ - kXBAR2_InputEdma4DmaTriggerOut2 = 90|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR2_IN90 input. */ - kXBAR2_InputEdma4DmaTriggerOut3 = 91|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR2_IN91 input. */ - kXBAR2_InputEdma4DmaTriggerOut4 = 92|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR2_IN92 input. */ - kXBAR2_InputEdma4DmaTriggerOut5 = 93|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR2_IN93 input. */ - kXBAR2_InputEdma4DmaTriggerOut6 = 94|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR2_IN94 input. */ - kXBAR2_InputEdma4DmaTriggerOut7 = 95|0x20000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR2_IN95 input. */ - kXBAR2_InputAdc1IpiIntEoc = 96|0x20000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR2_IN96 input. */ - kXBAR2_InputAdc1IpiIntWd = 97|0x20000U, /**< ADC1_IPI_INT_WD output assigned to XBAR2_IN97 input. */ - kXBAR2_InputTpm1LptpmChTrigger0 = 98|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN98 input. */ - kXBAR2_InputTpm1LptpmChTrigger1 = 99|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN99 input. */ - kXBAR2_InputTpm1LptpmChTrigger2 = 100|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN100 input. */ - kXBAR2_InputTpm1LptpmChTrigger3 = 101|0x20000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN101 input. */ - kXBAR2_InputTpm1LptpmTrigger = 102|0x20000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR2_IN102 input. */ - kXBAR2_InputTpm2LptpmChTrigger0 = 103|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN103 input. */ - kXBAR2_InputTpm2LptpmChTrigger1 = 104|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN104 input. */ - kXBAR2_InputTpm2LptpmChTrigger2 = 105|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN105 input. */ - kXBAR2_InputTpm2LptpmChTrigger3 = 106|0x20000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN106 input. */ - kXBAR2_InputTpm2LptpmTrigger = 107|0x20000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR2_IN107 input. */ - kXBAR2_InputTpm3LptpmChTrigger0 = 108|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN108 input. */ - kXBAR2_InputTpm3LptpmChTrigger1 = 109|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN109 input. */ - kXBAR2_InputTpm3LptpmChTrigger2 = 110|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN110 input. */ - kXBAR2_InputTpm3LptpmChTrigger3 = 111|0x20000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN111 input. */ - kXBAR2_InputTpm3LptpmTrigger = 112|0x20000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR2_IN112 input. */ - kXBAR2_InputTpm4LptpmChTrigger0 = 113|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN113 input. */ - kXBAR2_InputTpm4LptpmChTrigger1 = 114|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN114 input. */ - kXBAR2_InputTpm4LptpmChTrigger2 = 115|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN115 input. */ - kXBAR2_InputTpm4LptpmChTrigger3 = 116|0x20000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN116 input. */ - kXBAR2_InputTpm4LptpmTrigger = 117|0x20000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR2_IN117 input. */ - kXBAR2_InputTpm5LptpmChTrigger0 = 118|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN118 input. */ - kXBAR2_InputTpm5LptpmChTrigger1 = 119|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN119 input. */ - kXBAR2_InputTpm5LptpmChTrigger2 = 120|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN120 input. */ - kXBAR2_InputTpm5LptpmChTrigger3 = 121|0x20000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN121 input. */ - kXBAR2_InputTpm5LptpmTrigger = 122|0x20000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR2_IN122 input. */ - kXBAR2_InputTpm6LptpmChTrigger0 = 123|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR2_IN123 input. */ - kXBAR2_InputTpm6LptpmChTrigger1 = 124|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR2_IN124 input. */ - kXBAR2_InputTpm6LptpmChTrigger2 = 125|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR2_IN125 input. */ - kXBAR2_InputTpm6LptpmChTrigger3 = 126|0x20000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR2_IN126 input. */ - kXBAR2_InputTpm6LptpmTrigger = 127|0x20000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR2_IN127 input. */ - kXBAR2_InputLptmr1LptimerTriggerDelay = 128|0x20000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN128 input. */ - kXBAR2_InputLptmr2LptimerTriggerDelay = 129|0x20000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR2_IN129 input. */ - kXBAR2_InputLogicLow2 = 130|0x20000U, /**< LOGIC_LOW2 output assigned to XBAR2_IN130 input. */ - kXBAR2_InputNetcTmr11588Pp1 = 131|0x20000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR2_IN131 input. */ - kXBAR2_InputNetcTmr11588Pp2 = 132|0x20000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR2_IN132 input. */ - kXBAR2_InputNetcTmr11588Pp3 = 133|0x20000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR2_IN133 input. */ - kXBAR2_InputNetcTmr11588Alarm1 = 134|0x20000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR2_IN134 input. */ - kXBAR2_InputNetcTmr11588Alarm2 = 135|0x20000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR2_IN135 input. */ - kXBAR2_InputNetcTmr21588Pp1 = 136|0x20000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR2_IN136 input. */ - kXBAR2_InputNetcTmr21588Pp2 = 137|0x20000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR2_IN137 input. */ - kXBAR2_InputNetcTmr21588Pp3 = 138|0x20000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR2_IN138 input. */ - kXBAR2_InputNetcTmr21588Alarm1 = 139|0x20000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR2_IN139 input. */ - kXBAR2_InputNetcTmr21588Alarm2 = 140|0x20000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR2_IN140 input. */ - kXBAR2_InputNetcTmr31588Pp1 = 141|0x20000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR2_IN141 input. */ - kXBAR2_InputNetcTmr31588Pp2 = 142|0x20000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR2_IN142 input. */ - kXBAR2_InputNetcTmr31588Pp3 = 143|0x20000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR2_IN143 input. */ - kXBAR2_InputNetcTmr31588Alarm1 = 144|0x20000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR2_IN144 input. */ - kXBAR2_InputNetcTmr31588Alarm2 = 145|0x20000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR2_IN145 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak0 = 146|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR2_IN146 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak1 = 147|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR2_IN147 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak2 = 148|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR2_IN148 input. */ - kXBAR2_InputSincFilterGlue1IppDoBreak3 = 149|0x20000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR2_IN149 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak0 = 150|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR2_IN150 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak1 = 151|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR2_IN151 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak2 = 152|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR2_IN152 input. */ - kXBAR2_InputSincFilterGlue2IppDoBreak3 = 153|0x20000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR2_IN153 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak0 = 154|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR2_IN154 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak1 = 155|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR2_IN155 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak2 = 156|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR2_IN156 input. */ - kXBAR2_InputSincFilterGlue3IppDoBreak3 = 157|0x20000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR2_IN157 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak0 = 158|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR2_IN158 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak1 = 159|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR2_IN159 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak2 = 160|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR2_IN160 input. */ - kXBAR2_InputSincFilterGlue4IppDoBreak3 = 161|0x20000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR2_IN161 input. */ - kXBAR2_InputSinc1PulseTrg0 = 162|0x20000U, /**< SINC1_PULSE_TRG0 output assigned to XBAR2_IN162 input. */ - kXBAR2_InputSinc1PulseTrg1 = 163|0x20000U, /**< SINC1_PULSE_TRG1 output assigned to XBAR2_IN163 input. */ - kXBAR2_InputSinc1PulseTrg2 = 164|0x20000U, /**< SINC1_PULSE_TRG2 output assigned to XBAR2_IN164 input. */ - kXBAR2_InputSinc1PulseTrg3 = 165|0x20000U, /**< SINC1_PULSE_TRG3 output assigned to XBAR2_IN165 input. */ - kXBAR2_InputSinc3PulseTrg0 = 166|0x20000U, /**< SINC3_PULSE_TRG0 output assigned to XBAR2_IN166 input. */ - kXBAR2_InputSinc3PulseTrg1 = 167|0x20000U, /**< SINC3_PULSE_TRG1 output assigned to XBAR2_IN167 input. */ - kXBAR2_InputSinc3PulseTrg2 = 168|0x20000U, /**< SINC3_PULSE_TRG2 output assigned to XBAR2_IN168 input. */ - kXBAR2_InputSinc3PulseTrg3 = 169|0x20000U, /**< SINC3_PULSE_TRG3 output assigned to XBAR2_IN169 input. */ - kXBAR2_InputEcatSyncOut0 = 170|0x20000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR2_IN170 input. */ - kXBAR2_InputEcatSyncOut1 = 171|0x20000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR2_IN171 input. */ - kXBAR2_InputFccuVfccuReactionsOut11 = 172|0x20000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR2_IN172 input. */ - kXBAR2_InputGpt1IppDoCmpout1 = 173|0x20000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR2_IN173 input. */ - kXBAR2_InputGpt1IppDoCmpout2 = 174|0x20000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR2_IN174 input. */ - kXBAR2_InputGpt1IppDoCmpout3 = 175|0x20000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR2_IN175 input. */ - kXBAR2_InputGpt2IppDoCmpout1 = 176|0x20000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR2_IN176 input. */ - kXBAR2_InputGpt2IppDoCmpout2 = 177|0x20000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR2_IN177 input. */ - kXBAR2_InputGpt2IppDoCmpout3 = 178|0x20000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR2_IN178 input. */ - kXBAR2_InputGpt3IppDoCmpout1 = 179|0x20000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR2_IN179 input. */ - kXBAR2_InputGpt3IppDoCmpout2 = 180|0x20000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR2_IN180 input. */ - kXBAR2_InputGpt3IppDoCmpout3 = 181|0x20000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR2_IN181 input. */ - kXBAR2_InputGpt4IppDoCmpout1 = 182|0x20000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR2_IN182 input. */ - kXBAR2_InputGpt4IppDoCmpout2 = 183|0x20000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR2_IN183 input. */ - kXBAR2_InputGpt4IppDoCmpout3 = 184|0x20000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR2_IN184 input. */ - kXBAR2_InputFlexio1FlexioTriggerOut0 = 185|0x20000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN185 input. */ - kXBAR2_InputFlexio2FlexioTriggerOut0 = 186|0x20000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN186 input. */ - kXBAR2_InputFlexio3FlexioTriggerOut0 = 187|0x20000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN187 input. */ - kXBAR2_InputFlexio4FlexioTriggerOut0 = 188|0x20000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR2_IN188 input. */ - kXBAR2_InputGpio1IpiIntRgpio0 = 189|0x20000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR2_IN189 input. */ - kXBAR2_InputGpio2IpiIntRgpio0 = 190|0x20000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR2_IN190 input. */ - kXBAR2_InputGpio3IpiIntRgpio0 = 191|0x20000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR2_IN191 input. */ - kXBAR2_InputGpio4IpiIntRgpio0 = 192|0x20000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR2_IN192 input. */ - kXBAR2_InputGpio5IpiIntRgpio0 = 193|0x20000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR2_IN193 input. */ - kXBAR2_InputGpio6IpiIntRgpio0 = 194|0x20000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR2_IN194 input. */ - kXBAR2_InputGpio7IpiIntRgpio0 = 195|0x20000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR2_IN195 input. */ - kXBAR2_InputCm33Txev = 196|0x20000U, /**< CM33_TXEV output assigned to XBAR2_IN196 input. */ - kXBAR2_InputCm33SyncTxev = 197|0x20000U, /**< CM33_SYNC_TXEV output assigned to XBAR2_IN197 input. */ - kXBAR2_InputEndat21SiN = 198|0x20000U, /**< ENDAT2_1_SI_N output assigned to XBAR2_IN198 input. */ - kXBAR2_InputEndat21TimerN = 199|0x20000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR2_IN199 input. */ - kXBAR2_InputEndat22SiN = 200|0x20000U, /**< ENDAT2_2_SI_N output assigned to XBAR2_IN200 input. */ - kXBAR2_InputEndat22TimerN = 201|0x20000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR2_IN201 input. */ - kXBAR2_InputBissEot = 202|0x20000U, /**< BISS_EOT output assigned to XBAR2_IN202 input. */ - kXBAR2_InputEnc1PosMatch0 = 203|0x20000U, /**< ENC1_POS_MATCH0 output assigned to XBAR2_IN203 input. */ - kXBAR2_InputEnc1PosMatch1 = 204|0x20000U, /**< ENC1_POS_MATCH1 output assigned to XBAR2_IN204 input. */ - kXBAR2_InputEnc1PosMatch2 = 205|0x20000U, /**< ENC1_POS_MATCH2 output assigned to XBAR2_IN205 input. */ - kXBAR2_InputEnc1PosMatch3 = 206|0x20000U, /**< ENC1_POS_MATCH3 output assigned to XBAR2_IN206 input. */ - kXBAR2_InputEnc1CompFlg0 = 207|0x20000U, /**< ENC1_COMP_FLG0 output assigned to XBAR2_IN207 input. */ - kXBAR2_InputEnc1CompFlg1 = 208|0x20000U, /**< ENC1_COMP_FLG1 output assigned to XBAR2_IN208 input. */ - kXBAR2_InputEnc1CompFlg2 = 209|0x20000U, /**< ENC1_COMP_FLG2 output assigned to XBAR2_IN209 input. */ - kXBAR2_InputEnc1CompFlg3 = 210|0x20000U, /**< ENC1_COMP_FLG3 output assigned to XBAR2_IN210 input. */ - kXBAR2_InputEnc1CntDn = 211|0x20000U, /**< ENC1_CNT_DN output assigned to XBAR2_IN211 input. */ - kXBAR2_InputEnc1CntUp = 212|0x20000U, /**< ENC1_CNT_UP output assigned to XBAR2_IN212 input. */ - kXBAR2_InputEnc1Dir = 213|0x20000U, /**< ENC1_DIR output assigned to XBAR2_IN213 input. */ - kXBAR2_InputEnc3PosMatch0 = 214|0x20000U, /**< ENC3_POS_MATCH0 output assigned to XBAR2_IN214 input. */ - kXBAR2_InputEnc3PosMatch1 = 215|0x20000U, /**< ENC3_POS_MATCH1 output assigned to XBAR2_IN215 input. */ - kXBAR2_InputEnc3PosMatch2 = 216|0x20000U, /**< ENC3_POS_MATCH2 output assigned to XBAR2_IN216 input. */ - kXBAR2_InputEnc3PosMatch3 = 217|0x20000U, /**< ENC3_POS_MATCH3 output assigned to XBAR2_IN217 input. */ - kXBAR2_InputEnc3CompFlg0 = 218|0x20000U, /**< ENC3_COMP_FLG0 output assigned to XBAR2_IN218 input. */ - kXBAR2_InputEnc3CompFlg1 = 219|0x20000U, /**< ENC3_COMP_FLG1 output assigned to XBAR2_IN219 input. */ - kXBAR2_InputEnc3CompFlg2 = 220|0x20000U, /**< ENC3_COMP_FLG2 output assigned to XBAR2_IN220 input. */ - kXBAR2_InputEnc3CompFlg3 = 221|0x20000U, /**< ENC3_COMP_FLG3 output assigned to XBAR2_IN221 input. */ - kXBAR2_InputEnc3CntDn = 222|0x20000U, /**< ENC3_CNT_DN output assigned to XBAR2_IN222 input. */ - kXBAR2_InputEnc3CntUp = 223|0x20000U, /**< ENC3_CNT_UP output assigned to XBAR2_IN223 input. */ - kXBAR2_InputEnc3Dir = 224|0x20000U, /**< ENC3_DIR output assigned to XBAR2_IN224 input. */ - kXBAR2_InputHiperface1FastPosRcvdEvt = 225|0x20000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR2_IN225 input. */ - kXBAR2_InputHiperface2FastPosRcvdEvt = 226|0x20000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR2_IN226 input. */ - kXBAR3_InputLogicLow = 0|0x30000U, /**< LOGIC_LOW output assigned to XBAR3_IN0 input. */ - kXBAR3_InputLogicHigh = 1|0x30000U, /**< LOGIC_HIGH output assigned to XBAR3_IN1 input. */ - kXBAR3_InputLogicLow1 = 2|0x30000U, /**< LOGIC_LOW1 output assigned to XBAR3_IN2 input. */ - kXBAR3_InputLogicHigh1 = 3|0x30000U, /**< LOGIC_HIGH1 output assigned to XBAR3_IN3 input. */ - kXBAR3_InputQtimer1Timer0 = 4|0x30000U, /**< QTIMER1_TIMER0 output assigned to XBAR3_IN4 input. */ - kXBAR3_InputQtimer1Timer1 = 5|0x30000U, /**< QTIMER1_TIMER1 output assigned to XBAR3_IN5 input. */ - kXBAR3_InputQtimer1Timer2 = 6|0x30000U, /**< QTIMER1_TIMER2 output assigned to XBAR3_IN6 input. */ - kXBAR3_InputQtimer1Timer3 = 7|0x30000U, /**< QTIMER1_TIMER3 output assigned to XBAR3_IN7 input. */ - kXBAR3_InputQtimer2Timer0 = 8|0x30000U, /**< QTIMER2_TIMER0 output assigned to XBAR3_IN8 input. */ - kXBAR3_InputQtimer2Timer1 = 9|0x30000U, /**< QTIMER2_TIMER1 output assigned to XBAR3_IN9 input. */ - kXBAR3_InputQtimer2Timer2 = 10|0x30000U, /**< QTIMER2_TIMER2 output assigned to XBAR3_IN10 input. */ - kXBAR3_InputQtimer2Timer3 = 11|0x30000U, /**< QTIMER2_TIMER3 output assigned to XBAR3_IN11 input. */ - kXBAR3_InputQtimer3Timer0 = 12|0x30000U, /**< QTIMER3_TIMER0 output assigned to XBAR3_IN12 input. */ - kXBAR3_InputQtimer3Timer1 = 13|0x30000U, /**< QTIMER3_TIMER1 output assigned to XBAR3_IN13 input. */ - kXBAR3_InputQtimer3Timer2 = 14|0x30000U, /**< QTIMER3_TIMER2 output assigned to XBAR3_IN14 input. */ - kXBAR3_InputQtimer3Timer3 = 15|0x30000U, /**< QTIMER3_TIMER3 output assigned to XBAR3_IN15 input. */ - kXBAR3_InputQtimer4Timer0 = 16|0x30000U, /**< QTIMER4_TIMER0 output assigned to XBAR3_IN16 input. */ - kXBAR3_InputQtimer4Timer1 = 17|0x30000U, /**< QTIMER4_TIMER1 output assigned to XBAR3_IN17 input. */ - kXBAR3_InputQtimer4Timer2 = 18|0x30000U, /**< QTIMER4_TIMER2 output assigned to XBAR3_IN18 input. */ - kXBAR3_InputQtimer4Timer3 = 19|0x30000U, /**< QTIMER4_TIMER3 output assigned to XBAR3_IN19 input. */ - kXBAR3_InputQtimer5Timer0 = 20|0x30000U, /**< QTIMER5_TIMER0 output assigned to XBAR3_IN20 input. */ - kXBAR3_InputQtimer5Timer1 = 21|0x30000U, /**< QTIMER5_TIMER1 output assigned to XBAR3_IN21 input. */ - kXBAR3_InputQtimer5Timer2 = 22|0x30000U, /**< QTIMER5_TIMER2 output assigned to XBAR3_IN22 input. */ - kXBAR3_InputQtimer5Timer3 = 23|0x30000U, /**< QTIMER5_TIMER3 output assigned to XBAR3_IN23 input. */ - kXBAR3_InputQtimer6Timer0 = 24|0x30000U, /**< QTIMER6_TIMER0 output assigned to XBAR3_IN24 input. */ - kXBAR3_InputQtimer6Timer1 = 25|0x30000U, /**< QTIMER6_TIMER1 output assigned to XBAR3_IN25 input. */ - kXBAR3_InputQtimer6Timer2 = 26|0x30000U, /**< QTIMER6_TIMER2 output assigned to XBAR3_IN26 input. */ - kXBAR3_InputQtimer6Timer3 = 27|0x30000U, /**< QTIMER6_TIMER3 output assigned to XBAR3_IN27 input. */ - kXBAR3_InputQtimer7Timer0 = 28|0x30000U, /**< QTIMER7_TIMER0 output assigned to XBAR3_IN28 input. */ - kXBAR3_InputQtimer7Timer1 = 29|0x30000U, /**< QTIMER7_TIMER1 output assigned to XBAR3_IN29 input. */ - kXBAR3_InputQtimer7Timer2 = 30|0x30000U, /**< QTIMER7_TIMER2 output assigned to XBAR3_IN30 input. */ - kXBAR3_InputQtimer7Timer3 = 31|0x30000U, /**< QTIMER7_TIMER3 output assigned to XBAR3_IN31 input. */ - kXBAR3_InputQtimer8Timer0 = 32|0x30000U, /**< QTIMER8_TIMER0 output assigned to XBAR3_IN32 input. */ - kXBAR3_InputQtimer8Timer1 = 33|0x30000U, /**< QTIMER8_TIMER1 output assigned to XBAR3_IN33 input. */ - kXBAR3_InputQtimer8Timer2 = 34|0x30000U, /**< QTIMER8_TIMER2 output assigned to XBAR3_IN34 input. */ - kXBAR3_InputQtimer8Timer3 = 35|0x30000U, /**< QTIMER8_TIMER3 output assigned to XBAR3_IN35 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger0 = 36|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER0 output assigned to XBAR3_IN36 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger1 = 37|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER1 output assigned to XBAR3_IN37 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger2 = 38|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER2 output assigned to XBAR3_IN38 input. */ - kXBAR3_InputFlexpwm1Mux0Trigger3 = 39|0x30000U, /**< FLEXPWM1_MUX0_TRIGGER3 output assigned to XBAR3_IN39 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger0 = 40|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER0 output assigned to XBAR3_IN40 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger1 = 41|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER1 output assigned to XBAR3_IN41 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger2 = 42|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER2 output assigned to XBAR3_IN42 input. */ - kXBAR3_InputFlexpwm2Mux0Trigger3 = 43|0x30000U, /**< FLEXPWM2_MUX0_TRIGGER3 output assigned to XBAR3_IN43 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger0 = 44|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER0 output assigned to XBAR3_IN44 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger1 = 45|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER1 output assigned to XBAR3_IN45 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger2 = 46|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER2 output assigned to XBAR3_IN46 input. */ - kXBAR3_InputFlexpwm3Mux0Trigger3 = 47|0x30000U, /**< FLEXPWM3_MUX0_TRIGGER3 output assigned to XBAR3_IN47 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger0 = 48|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER0 output assigned to XBAR3_IN48 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger1 = 49|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER1 output assigned to XBAR3_IN49 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger2 = 50|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER2 output assigned to XBAR3_IN50 input. */ - kXBAR3_InputFlexpwm4Mux0Trigger3 = 51|0x30000U, /**< FLEXPWM4_MUX0_TRIGGER3 output assigned to XBAR3_IN51 input. */ - kXBAR3_InputLpit1LpitTrigOut0 = 52|0x30000U, /**< LPIT1_LPIT_TRIG_OUT0 output assigned to XBAR3_IN52 input. */ - kXBAR3_InputLpit1LpitTrigOut1 = 53|0x30000U, /**< LPIT1_LPIT_TRIG_OUT1 output assigned to XBAR3_IN53 input. */ - kXBAR3_InputLpit1LpitTrigOut2 = 54|0x30000U, /**< LPIT1_LPIT_TRIG_OUT2 output assigned to XBAR3_IN54 input. */ - kXBAR3_InputLpit1LpitTrigOut3 = 55|0x30000U, /**< LPIT1_LPIT_TRIG_OUT3 output assigned to XBAR3_IN55 input. */ - kXBAR3_InputLpit2LpitTrigOut0 = 56|0x30000U, /**< LPIT2_LPIT_TRIG_OUT0 output assigned to XBAR3_IN56 input. */ - kXBAR3_InputLpit2LpitTrigOut1 = 57|0x30000U, /**< LPIT2_LPIT_TRIG_OUT1 output assigned to XBAR3_IN57 input. */ - kXBAR3_InputLpit2LpitTrigOut2 = 58|0x30000U, /**< LPIT2_LPIT_TRIG_OUT2 output assigned to XBAR3_IN58 input. */ - kXBAR3_InputLpit2LpitTrigOut3 = 59|0x30000U, /**< LPIT2_LPIT_TRIG_OUT3 output assigned to XBAR3_IN59 input. */ - kXBAR3_InputLpit3LpitTrigOut0 = 60|0x30000U, /**< LPIT3_LPIT_TRIG_OUT0 output assigned to XBAR3_IN60 input. */ - kXBAR3_InputLpit3LpitTrigOut1 = 61|0x30000U, /**< LPIT3_LPIT_TRIG_OUT1 output assigned to XBAR3_IN61 input. */ - kXBAR3_InputLpit3LpitTrigOut2 = 62|0x30000U, /**< LPIT3_LPIT_TRIG_OUT2 output assigned to XBAR3_IN62 input. */ - kXBAR3_InputLpit3LpitTrigOut3 = 63|0x30000U, /**< LPIT3_LPIT_TRIG_OUT3 output assigned to XBAR3_IN63 input. */ - kXBAR3_InputEdma2DmaTriggerOut0 = 64|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN64 input. */ - kXBAR3_InputEdma2DmaTriggerOut1 = 65|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN65 input. */ - kXBAR3_InputEdma2DmaTriggerOut2 = 66|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN66 input. */ - kXBAR3_InputEdma2DmaTriggerOut3 = 67|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN67 input. */ - kXBAR3_InputEdma2DmaTriggerOut4 = 68|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN68 input. */ - kXBAR3_InputEdma2DmaTriggerOut5 = 69|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN69 input. */ - kXBAR3_InputEdma2DmaTriggerOut6 = 70|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN70 input. */ - kXBAR3_InputEdma2DmaTriggerOut7 = 71|0x30000U, /**< EDMA2_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN71 input. */ - kXBAR3_InputEdma1DmaTriggerOut0 = 72|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN72 input. */ - kXBAR3_InputEdma1DmaTriggerOut1 = 73|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN73 input. */ - kXBAR3_InputEdma1DmaTriggerOut2 = 74|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN74 input. */ - kXBAR3_InputEdma1DmaTriggerOut3 = 75|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN75 input. */ - kXBAR3_InputEdma1DmaTriggerOut4 = 76|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN76 input. */ - kXBAR3_InputEdma1DmaTriggerOut5 = 77|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN77 input. */ - kXBAR3_InputEdma1DmaTriggerOut6 = 78|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN78 input. */ - kXBAR3_InputEdma1DmaTriggerOut7 = 79|0x30000U, /**< EDMA1_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN79 input. */ - kXBAR3_InputEdma3DmaTriggerOut0 = 80|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN80 input. */ - kXBAR3_InputEdma3DmaTriggerOut1 = 81|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN81 input. */ - kXBAR3_InputEdma3DmaTriggerOut2 = 82|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN82 input. */ - kXBAR3_InputEdma3DmaTriggerOut3 = 83|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN83 input. */ - kXBAR3_InputEdma3DmaTriggerOut4 = 84|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN84 input. */ - kXBAR3_InputEdma3DmaTriggerOut5 = 85|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN85 input. */ - kXBAR3_InputEdma3DmaTriggerOut6 = 86|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN86 input. */ - kXBAR3_InputEdma3DmaTriggerOut7 = 87|0x30000U, /**< EDMA3_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN87 input. */ - kXBAR3_InputEdma4DmaTriggerOut0 = 88|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT0 output assigned to XBAR3_IN88 input. */ - kXBAR3_InputEdma4DmaTriggerOut1 = 89|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT1 output assigned to XBAR3_IN89 input. */ - kXBAR3_InputEdma4DmaTriggerOut2 = 90|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT2 output assigned to XBAR3_IN90 input. */ - kXBAR3_InputEdma4DmaTriggerOut3 = 91|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT3 output assigned to XBAR3_IN91 input. */ - kXBAR3_InputEdma4DmaTriggerOut4 = 92|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT4 output assigned to XBAR3_IN92 input. */ - kXBAR3_InputEdma4DmaTriggerOut5 = 93|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT5 output assigned to XBAR3_IN93 input. */ - kXBAR3_InputEdma4DmaTriggerOut6 = 94|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT6 output assigned to XBAR3_IN94 input. */ - kXBAR3_InputEdma4DmaTriggerOut7 = 95|0x30000U, /**< EDMA4_DMA_TRIGGER_OUT7 output assigned to XBAR3_IN95 input. */ - kXBAR3_InputAdc1IpiIntEoc = 96|0x30000U, /**< ADC1_IPI_INT_EOC output assigned to XBAR3_IN96 input. */ - kXBAR3_InputAdc1IpiIntWd = 97|0x30000U, /**< ADC1_IPI_INT_WD output assigned to XBAR3_IN97 input. */ - kXBAR3_InputTpm1LptpmChTrigger0 = 98|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN98 input. */ - kXBAR3_InputTpm1LptpmChTrigger1 = 99|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN99 input. */ - kXBAR3_InputTpm1LptpmChTrigger2 = 100|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN100 input. */ - kXBAR3_InputTpm1LptpmChTrigger3 = 101|0x30000U, /**< TPM1_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN101 input. */ - kXBAR3_InputTpm1LptpmTrigger = 102|0x30000U, /**< TPM1_LPTPM_TRIGGER output assigned to XBAR3_IN102 input. */ - kXBAR3_InputTpm2LptpmChTrigger0 = 103|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN103 input. */ - kXBAR3_InputTpm2LptpmChTrigger1 = 104|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN104 input. */ - kXBAR3_InputTpm2LptpmChTrigger2 = 105|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN105 input. */ - kXBAR3_InputTpm2LptpmChTrigger3 = 106|0x30000U, /**< TPM2_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN106 input. */ - kXBAR3_InputTpm2LptpmTrigger = 107|0x30000U, /**< TPM2_LPTPM_TRIGGER output assigned to XBAR3_IN107 input. */ - kXBAR3_InputTpm3LptpmChTrigger0 = 108|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN108 input. */ - kXBAR3_InputTpm3LptpmChTrigger1 = 109|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN109 input. */ - kXBAR3_InputTpm3LptpmChTrigger2 = 110|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN110 input. */ - kXBAR3_InputTpm3LptpmChTrigger3 = 111|0x30000U, /**< TPM3_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN111 input. */ - kXBAR3_InputTpm3LptpmTrigger = 112|0x30000U, /**< TPM3_LPTPM_TRIGGER output assigned to XBAR3_IN112 input. */ - kXBAR3_InputTpm4LptpmChTrigger0 = 113|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN113 input. */ - kXBAR3_InputTpm4LptpmChTrigger1 = 114|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN114 input. */ - kXBAR3_InputTpm4LptpmChTrigger2 = 115|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN115 input. */ - kXBAR3_InputTpm4LptpmChTrigger3 = 116|0x30000U, /**< TPM4_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN116 input. */ - kXBAR3_InputTpm4LptpmTrigger = 117|0x30000U, /**< TPM4_LPTPM_TRIGGER output assigned to XBAR3_IN117 input. */ - kXBAR3_InputTpm5LptpmChTrigger0 = 118|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN118 input. */ - kXBAR3_InputTpm5LptpmChTrigger1 = 119|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN119 input. */ - kXBAR3_InputTpm5LptpmChTrigger2 = 120|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN120 input. */ - kXBAR3_InputTpm5LptpmChTrigger3 = 121|0x30000U, /**< TPM5_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN121 input. */ - kXBAR3_InputTpm5LptpmTrigger = 122|0x30000U, /**< TPM5_LPTPM_TRIGGER output assigned to XBAR3_IN122 input. */ - kXBAR3_InputTpm6LptpmChTrigger0 = 123|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER0 output assigned to XBAR3_IN123 input. */ - kXBAR3_InputTpm6LptpmChTrigger1 = 124|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER1 output assigned to XBAR3_IN124 input. */ - kXBAR3_InputTpm6LptpmChTrigger2 = 125|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER2 output assigned to XBAR3_IN125 input. */ - kXBAR3_InputTpm6LptpmChTrigger3 = 126|0x30000U, /**< TPM6_LPTPM_CH_TRIGGER3 output assigned to XBAR3_IN126 input. */ - kXBAR3_InputTpm6LptpmTrigger = 127|0x30000U, /**< TPM6_LPTPM_TRIGGER output assigned to XBAR3_IN127 input. */ - kXBAR3_InputLptmr1LptimerTriggerDelay = 128|0x30000U, /**< LPTMR1_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN128 input. */ - kXBAR3_InputLptmr2LptimerTriggerDelay = 129|0x30000U, /**< LPTMR2_LPTIMER_TRIGGER_DELAY output assigned to XBAR3_IN129 input. */ - kXBAR3_InputLogicLow2 = 130|0x30000U, /**< LOGIC_LOW2 output assigned to XBAR3_IN130 input. */ - kXBAR3_InputNetcTmr11588Pp1 = 131|0x30000U, /**< NETC_TMR1_1588_PP1 output assigned to XBAR3_IN131 input. */ - kXBAR3_InputNetcTmr11588Pp2 = 132|0x30000U, /**< NETC_TMR1_1588_PP2 output assigned to XBAR3_IN132 input. */ - kXBAR3_InputNetcTmr11588Pp3 = 133|0x30000U, /**< NETC_TMR1_1588_PP3 output assigned to XBAR3_IN133 input. */ - kXBAR3_InputNetcTmr11588Alarm1 = 134|0x30000U, /**< NETC_TMR1_1588_ALARM1 output assigned to XBAR3_IN134 input. */ - kXBAR3_InputNetcTmr11588Alarm2 = 135|0x30000U, /**< NETC_TMR1_1588_ALARM2 output assigned to XBAR3_IN135 input. */ - kXBAR3_InputNetcTmr21588Pp1 = 136|0x30000U, /**< NETC_TMR2_1588_PP1 output assigned to XBAR3_IN136 input. */ - kXBAR3_InputNetcTmr21588Pp2 = 137|0x30000U, /**< NETC_TMR2_1588_PP2 output assigned to XBAR3_IN137 input. */ - kXBAR3_InputNetcTmr21588Pp3 = 138|0x30000U, /**< NETC_TMR2_1588_PP3 output assigned to XBAR3_IN138 input. */ - kXBAR3_InputNetcTmr21588Alarm1 = 139|0x30000U, /**< NETC_TMR2_1588_ALARM1 output assigned to XBAR3_IN139 input. */ - kXBAR3_InputNetcTmr21588Alarm2 = 140|0x30000U, /**< NETC_TMR2_1588_ALARM2 output assigned to XBAR3_IN140 input. */ - kXBAR3_InputNetcTmr31588Pp1 = 141|0x30000U, /**< NETC_TMR3_1588_PP1 output assigned to XBAR3_IN141 input. */ - kXBAR3_InputNetcTmr31588Pp2 = 142|0x30000U, /**< NETC_TMR3_1588_PP2 output assigned to XBAR3_IN142 input. */ - kXBAR3_InputNetcTmr31588Pp3 = 143|0x30000U, /**< NETC_TMR3_1588_PP3 output assigned to XBAR3_IN143 input. */ - kXBAR3_InputNetcTmr31588Alarm1 = 144|0x30000U, /**< NETC_TMR3_1588_ALARM1 output assigned to XBAR3_IN144 input. */ - kXBAR3_InputNetcTmr31588Alarm2 = 145|0x30000U, /**< NETC_TMR3_1588_ALARM2 output assigned to XBAR3_IN145 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak0 = 146|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK0 output assigned to XBAR3_IN146 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak1 = 147|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK1 output assigned to XBAR3_IN147 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak2 = 148|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK2 output assigned to XBAR3_IN148 input. */ - kXBAR3_InputSincFilterGlue1IppDoBreak3 = 149|0x30000U, /**< SINC_FILTER_GLUE1_IPP_DO_BREAK3 output assigned to XBAR3_IN149 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak0 = 150|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK0 output assigned to XBAR3_IN150 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak1 = 151|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK1 output assigned to XBAR3_IN151 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak2 = 152|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK2 output assigned to XBAR3_IN152 input. */ - kXBAR3_InputSincFilterGlue2IppDoBreak3 = 153|0x30000U, /**< SINC_FILTER_GLUE2_IPP_DO_BREAK3 output assigned to XBAR3_IN153 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak0 = 154|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK0 output assigned to XBAR3_IN154 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak1 = 155|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK1 output assigned to XBAR3_IN155 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak2 = 156|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK2 output assigned to XBAR3_IN156 input. */ - kXBAR3_InputSincFilterGlue3IppDoBreak3 = 157|0x30000U, /**< SINC_FILTER_GLUE3_IPP_DO_BREAK3 output assigned to XBAR3_IN157 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak0 = 158|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK0 output assigned to XBAR3_IN158 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak1 = 159|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK1 output assigned to XBAR3_IN159 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak2 = 160|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK2 output assigned to XBAR3_IN160 input. */ - kXBAR3_InputSincFilterGlue4IppDoBreak3 = 161|0x30000U, /**< SINC_FILTER_GLUE4_IPP_DO_BREAK3 output assigned to XBAR3_IN161 input. */ - kXBAR3_InputSinc2PulseTrg0 = 162|0x30000U, /**< SINC2_PULSE_TRG0 output assigned to XBAR3_IN162 input. */ - kXBAR3_InputSinc2PulseTrg1 = 163|0x30000U, /**< SINC2_PULSE_TRG1 output assigned to XBAR3_IN163 input. */ - kXBAR3_InputSinc2PulseTrg2 = 164|0x30000U, /**< SINC2_PULSE_TRG2 output assigned to XBAR3_IN164 input. */ - kXBAR3_InputSinc2PulseTrg3 = 165|0x30000U, /**< SINC2_PULSE_TRG3 output assigned to XBAR3_IN165 input. */ - kXBAR3_InputSinc4PulseTrg0 = 166|0x30000U, /**< SINC4_PULSE_TRG0 output assigned to XBAR3_IN166 input. */ - kXBAR3_InputSinc4PulseTrg1 = 167|0x30000U, /**< SINC4_PULSE_TRG1 output assigned to XBAR3_IN167 input. */ - kXBAR3_InputSinc4PulseTrg2 = 168|0x30000U, /**< SINC4_PULSE_TRG2 output assigned to XBAR3_IN168 input. */ - kXBAR3_InputSinc4PulseTrg3 = 169|0x30000U, /**< SINC4_PULSE_TRG3 output assigned to XBAR3_IN169 input. */ - kXBAR3_InputEcatSyncOut0 = 170|0x30000U, /**< ECAT_SYNC_OUT0 output assigned to XBAR3_IN170 input. */ - kXBAR3_InputEcatSyncOut1 = 171|0x30000U, /**< ECAT_SYNC_OUT1 output assigned to XBAR3_IN171 input. */ - kXBAR3_InputFccuVfccuReactionsOut11 = 172|0x30000U, /**< FCCU_VFCCU_REACTIONS_OUT11 output assigned to XBAR3_IN172 input. */ - kXBAR3_InputGpt1IppDoCmpout1 = 173|0x30000U, /**< GPT1_IPP_DO_CMPOUT1 output assigned to XBAR3_IN173 input. */ - kXBAR3_InputGpt1IppDoCmpout2 = 174|0x30000U, /**< GPT1_IPP_DO_CMPOUT2 output assigned to XBAR3_IN174 input. */ - kXBAR3_InputGpt1IppDoCmpout3 = 175|0x30000U, /**< GPT1_IPP_DO_CMPOUT3 output assigned to XBAR3_IN175 input. */ - kXBAR3_InputGpt2IppDoCmpout1 = 176|0x30000U, /**< GPT2_IPP_DO_CMPOUT1 output assigned to XBAR3_IN176 input. */ - kXBAR3_InputGpt2IppDoCmpout2 = 177|0x30000U, /**< GPT2_IPP_DO_CMPOUT2 output assigned to XBAR3_IN177 input. */ - kXBAR3_InputGpt2IppDoCmpout3 = 178|0x30000U, /**< GPT2_IPP_DO_CMPOUT3 output assigned to XBAR3_IN178 input. */ - kXBAR3_InputGpt3IppDoCmpout1 = 179|0x30000U, /**< GPT3_IPP_DO_CMPOUT1 output assigned to XBAR3_IN179 input. */ - kXBAR3_InputGpt3IppDoCmpout2 = 180|0x30000U, /**< GPT3_IPP_DO_CMPOUT2 output assigned to XBAR3_IN180 input. */ - kXBAR3_InputGpt3IppDoCmpout3 = 181|0x30000U, /**< GPT3_IPP_DO_CMPOUT3 output assigned to XBAR3_IN181 input. */ - kXBAR3_InputGpt4IppDoCmpout1 = 182|0x30000U, /**< GPT4_IPP_DO_CMPOUT1 output assigned to XBAR3_IN182 input. */ - kXBAR3_InputGpt4IppDoCmpout2 = 183|0x30000U, /**< GPT4_IPP_DO_CMPOUT2 output assigned to XBAR3_IN183 input. */ - kXBAR3_InputGpt4IppDoCmpout3 = 184|0x30000U, /**< GPT4_IPP_DO_CMPOUT3 output assigned to XBAR3_IN184 input. */ - kXBAR3_InputFlexio1FlexioTriggerOut0 = 185|0x30000U, /**< FLEXIO1_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN185 input. */ - kXBAR3_InputFlexio2FlexioTriggerOut0 = 186|0x30000U, /**< FLEXIO2_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN186 input. */ - kXBAR3_InputFlexio3FlexioTriggerOut0 = 187|0x30000U, /**< FLEXIO3_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN187 input. */ - kXBAR3_InputFlexio4FlexioTriggerOut0 = 188|0x30000U, /**< FLEXIO4_FLEXIO_TRIGGER_OUT0 output assigned to XBAR3_IN188 input. */ - kXBAR3_InputGpio1IpiIntRgpio0 = 189|0x30000U, /**< GPIO1_IPI_INT_RGPIO0 output assigned to XBAR3_IN189 input. */ - kXBAR3_InputGpio2IpiIntRgpio0 = 190|0x30000U, /**< GPIO2_IPI_INT_RGPIO0 output assigned to XBAR3_IN190 input. */ - kXBAR3_InputGpio3IpiIntRgpio0 = 191|0x30000U, /**< GPIO3_IPI_INT_RGPIO0 output assigned to XBAR3_IN191 input. */ - kXBAR3_InputGpio4IpiIntRgpio0 = 192|0x30000U, /**< GPIO4_IPI_INT_RGPIO0 output assigned to XBAR3_IN192 input. */ - kXBAR3_InputGpio5IpiIntRgpio0 = 193|0x30000U, /**< GPIO5_IPI_INT_RGPIO0 output assigned to XBAR3_IN193 input. */ - kXBAR3_InputGpio6IpiIntRgpio0 = 194|0x30000U, /**< GPIO6_IPI_INT_RGPIO0 output assigned to XBAR3_IN194 input. */ - kXBAR3_InputGpio7IpiIntRgpio0 = 195|0x30000U, /**< GPIO7_IPI_INT_RGPIO0 output assigned to XBAR3_IN195 input. */ - kXBAR3_InputCm33Txev = 196|0x30000U, /**< CM33_TXEV output assigned to XBAR3_IN196 input. */ - kXBAR3_InputCm33SyncTxev = 197|0x30000U, /**< CM33_SYNC_TXEV output assigned to XBAR3_IN197 input. */ - kXBAR3_InputEndat21SiN = 198|0x30000U, /**< ENDAT2_1_SI_N output assigned to XBAR3_IN198 input. */ - kXBAR3_InputEndat21TimerN = 199|0x30000U, /**< ENDAT2_1_TIMER_N output assigned to XBAR3_IN199 input. */ - kXBAR3_InputEndat22SiN = 200|0x30000U, /**< ENDAT2_2_SI_N output assigned to XBAR3_IN200 input. */ - kXBAR3_InputEndat22TimerN = 201|0x30000U, /**< ENDAT2_2_TIMER_N output assigned to XBAR3_IN201 input. */ - kXBAR3_InputBissEot = 202|0x30000U, /**< BISS_EOT output assigned to XBAR3_IN202 input. */ - kXBAR3_InputEnc2PosMatch0 = 203|0x30000U, /**< ENC2_POS_MATCH0 output assigned to XBAR3_IN203 input. */ - kXBAR3_InputEnc2PosMatch1 = 204|0x30000U, /**< ENC2_POS_MATCH1 output assigned to XBAR3_IN204 input. */ - kXBAR3_InputEnc2PosMatch2 = 205|0x30000U, /**< ENC2_POS_MATCH2 output assigned to XBAR3_IN205 input. */ - kXBAR3_InputEnc2PosMatch3 = 206|0x30000U, /**< ENC2_POS_MATCH3 output assigned to XBAR3_IN206 input. */ - kXBAR3_InputEnc2CompFlg0 = 207|0x30000U, /**< ENC2_COMP_FLG0 output assigned to XBAR3_IN207 input. */ - kXBAR3_InputEnc2CompFlg1 = 208|0x30000U, /**< ENC2_COMP_FLG1 output assigned to XBAR3_IN208 input. */ - kXBAR3_InputEnc2CompFlg2 = 209|0x30000U, /**< ENC2_COMP_FLG2 output assigned to XBAR3_IN209 input. */ - kXBAR3_InputEnc2CompFlg3 = 210|0x30000U, /**< ENC2_COMP_FLG3 output assigned to XBAR3_IN210 input. */ - kXBAR3_InputEnc2CntDn = 211|0x30000U, /**< ENC2_CNT_DN output assigned to XBAR3_IN211 input. */ - kXBAR3_InputEnc2CntUp = 212|0x30000U, /**< ENC2_CNT_UP output assigned to XBAR3_IN212 input. */ - kXBAR3_InputEnc2Dir = 213|0x30000U, /**< ENC2_DIR output assigned to XBAR3_IN213 input. */ - kXBAR3_InputEnc4PosMatch0 = 214|0x30000U, /**< ENC4_POS_MATCH0 output assigned to XBAR3_IN214 input. */ - kXBAR3_InputEnc4PosMatch1 = 215|0x30000U, /**< ENC4_POS_MATCH1 output assigned to XBAR3_IN215 input. */ - kXBAR3_InputEnc4PosMatch2 = 216|0x30000U, /**< ENC4_POS_MATCH2 output assigned to XBAR3_IN216 input. */ - kXBAR3_InputEnc4PosMatch3 = 217|0x30000U, /**< ENC4_POS_MATCH3 output assigned to XBAR3_IN217 input. */ - kXBAR3_InputEnc4CompFlg0 = 218|0x30000U, /**< ENC4_COMP_FLG0 output assigned to XBAR3_IN218 input. */ - kXBAR3_InputEnc4CompFlg1 = 219|0x30000U, /**< ENC4_COMP_FLG1 output assigned to XBAR3_IN219 input. */ - kXBAR3_InputEnc4CompFlg2 = 220|0x30000U, /**< ENC4_COMP_FLG2 output assigned to XBAR3_IN220 input. */ - kXBAR3_InputEnc4CompFlg3 = 221|0x30000U, /**< ENC4_COMP_FLG3 output assigned to XBAR3_IN221 input. */ - kXBAR3_InputEnc4CntDn = 222|0x30000U, /**< ENC4_CNT_DN output assigned to XBAR3_IN222 input. */ - kXBAR3_InputEnc4CntUp = 223|0x30000U, /**< ENC4_CNT_UP output assigned to XBAR3_IN223 input. */ - kXBAR3_InputEnc4Dir = 224|0x30000U, /**< ENC4_DIR output assigned to XBAR3_IN224 input. */ - kXBAR3_InputHiperface1FastPosRcvdEvt = 225|0x30000U, /**< HIPERFACE1_FAST_POS_RCVD_EVT output assigned to XBAR3_IN225 input. */ - kXBAR3_InputHiperface2FastPosRcvdEvt = 226|0x30000U, /**< HIPERFACE2_FAST_POS_RCVD_EVT output assigned to XBAR3_IN226 input. */ -} xbar_input_signal_t; -#endif /* XBAR_INPUT_SIGNAL_T_ */ - -#if !defined(XBAR_OUTPUT_SIGNAL_T_) -#define XBAR_OUTPUT_SIGNAL_T_ -typedef enum _xbar_output_signal -{ - kXBAR1_OutputEdma4IpdReq76 = 0|0x10000U, /**< XBAR1_OUT0 output assigned to EDMA4_IPD_REQ76 */ - kXBAR1_OutputEdma4IpdReq77 = 1|0x10000U, /**< XBAR1_OUT1 output assigned to EDMA4_IPD_REQ77 */ - kXBAR1_OutputEdma4IpdReq78 = 2|0x10000U, /**< XBAR1_OUT2 output assigned to EDMA4_IPD_REQ78 */ - kXBAR1_OutputEdma4IpdReq79 = 3|0x10000U, /**< XBAR1_OUT3 output assigned to EDMA4_IPD_REQ79 */ - kXBAR1_OutputIomuxXbarOut04 = 4|0x10000U, /**< XBAR1_OUT4 output assigned to IOMUX_XBAR_OUT04 */ - kXBAR1_OutputIomuxXbarOut05 = 5|0x10000U, /**< XBAR1_OUT5 output assigned to IOMUX_XBAR_OUT05 */ - kXBAR1_OutputIomuxXbarOut06 = 6|0x10000U, /**< XBAR1_OUT6 output assigned to IOMUX_XBAR_OUT06 */ - kXBAR1_OutputIomuxXbarOut07 = 7|0x10000U, /**< XBAR1_OUT7 output assigned to IOMUX_XBAR_OUT07 */ - kXBAR1_OutputIomuxXbarOut08 = 8|0x10000U, /**< XBAR1_OUT8 output assigned to IOMUX_XBAR_OUT08 */ - kXBAR1_OutputIomuxXbarOut09 = 9|0x10000U, /**< XBAR1_OUT9 output assigned to IOMUX_XBAR_OUT09 */ - kXBAR1_OutputIomuxXbarOut10 = 10|0x10000U, /**< XBAR1_OUT10 output assigned to IOMUX_XBAR_OUT10 */ - kXBAR1_OutputIomuxXbarOut11 = 11|0x10000U, /**< XBAR1_OUT11 output assigned to IOMUX_XBAR_OUT11 */ - kXBAR1_OutputIomuxXbarOut12 = 12|0x10000U, /**< XBAR1_OUT12 output assigned to IOMUX_XBAR_OUT12 */ - kXBAR1_OutputIomuxXbarOut13 = 13|0x10000U, /**< XBAR1_OUT13 output assigned to IOMUX_XBAR_OUT13 */ - kXBAR1_OutputIomuxXbarOut14 = 14|0x10000U, /**< XBAR1_OUT14 output assigned to IOMUX_XBAR_OUT14 */ - kXBAR1_OutputIomuxXbarOut15 = 15|0x10000U, /**< XBAR1_OUT15 output assigned to IOMUX_XBAR_OUT15 */ - kXBAR1_OutputIomuxXbarOut16 = 16|0x10000U, /**< XBAR1_OUT16 output assigned to IOMUX_XBAR_OUT16 */ - kXBAR1_OutputIomuxXbarOut17 = 17|0x10000U, /**< XBAR1_OUT17 output assigned to IOMUX_XBAR_OUT17 */ - kXBAR1_OutputIomuxXbarOut18 = 18|0x10000U, /**< XBAR1_OUT18 output assigned to IOMUX_XBAR_OUT18 */ - kXBAR1_OutputIomuxXbarOut19 = 19|0x10000U, /**< XBAR1_OUT19 output assigned to IOMUX_XBAR_OUT19 */ - kXBAR1_OutputIomuxXbarOut20 = 20|0x10000U, /**< XBAR1_OUT20 output assigned to IOMUX_XBAR_OUT20 */ - kXBAR1_OutputIomuxXbarOut21 = 21|0x10000U, /**< XBAR1_OUT21 output assigned to IOMUX_XBAR_OUT21 */ - kXBAR1_OutputIomuxXbarOut22 = 22|0x10000U, /**< XBAR1_OUT22 output assigned to IOMUX_XBAR_OUT22 */ - kXBAR1_OutputIomuxXbarOut23 = 23|0x10000U, /**< XBAR1_OUT23 output assigned to IOMUX_XBAR_OUT23 */ - kXBAR1_OutputIomuxXbarOut24 = 24|0x10000U, /**< XBAR1_OUT24 output assigned to IOMUX_XBAR_OUT24 */ - kXBAR1_OutputIomuxXbarOut25 = 25|0x10000U, /**< XBAR1_OUT25 output assigned to IOMUX_XBAR_OUT25 */ - kXBAR1_OutputIomuxXbarOut26 = 26|0x10000U, /**< XBAR1_OUT26 output assigned to IOMUX_XBAR_OUT26 */ - kXBAR1_OutputIomuxXbarOut27 = 27|0x10000U, /**< XBAR1_OUT27 output assigned to IOMUX_XBAR_OUT27 */ - kXBAR1_OutputIomuxXbarOut28 = 28|0x10000U, /**< XBAR1_OUT28 output assigned to IOMUX_XBAR_OUT28 */ - kXBAR1_OutputIomuxXbarOut29 = 29|0x10000U, /**< XBAR1_OUT29 output assigned to IOMUX_XBAR_OUT29 */ - kXBAR1_OutputIomuxXbarOut30 = 30|0x10000U, /**< XBAR1_OUT30 output assigned to IOMUX_XBAR_OUT30 */ - kXBAR1_OutputIomuxXbarOut31 = 31|0x10000U, /**< XBAR1_OUT31 output assigned to IOMUX_XBAR_OUT31 */ - kXBAR1_OutputIomuxXbarOut32 = 32|0x10000U, /**< XBAR1_OUT32 output assigned to IOMUX_XBAR_OUT32 */ - kXBAR1_OutputIomuxXbarOut33 = 33|0x10000U, /**< XBAR1_OUT33 output assigned to IOMUX_XBAR_OUT33 */ - kXBAR1_OutputIomuxXbarOut34 = 34|0x10000U, /**< XBAR1_OUT34 output assigned to IOMUX_XBAR_OUT34 */ - kXBAR1_OutputIomuxXbarOut35 = 35|0x10000U, /**< XBAR1_OUT35 output assigned to IOMUX_XBAR_OUT35 */ - kXBAR1_OutputIomuxXbarOut36 = 36|0x10000U, /**< XBAR1_OUT36 output assigned to IOMUX_XBAR_OUT36 */ - kXBAR1_OutputIomuxXbarOut37 = 37|0x10000U, /**< XBAR1_OUT37 output assigned to IOMUX_XBAR_OUT37 */ - kXBAR1_OutputIomuxXbarOut38 = 38|0x10000U, /**< XBAR1_OUT38 output assigned to IOMUX_XBAR_OUT38 */ - kXBAR1_OutputIomuxXbarOut39 = 39|0x10000U, /**< XBAR1_OUT39 output assigned to IOMUX_XBAR_OUT39 */ - kXBAR1_OutputIomuxXbarOut40 = 40|0x10000U, /**< XBAR1_OUT40 output assigned to IOMUX_XBAR_OUT40 */ - kXBAR1_OutputTriggerSyncAsyncIn0 = 41|0x10000U, /**< XBAR1_OUT41 output assigned to TRIGGER_SYNC_ASYNC_IN0 */ - kXBAR1_OutputTriggerSyncAsyncIn1 = 42|0x10000U, /**< XBAR1_OUT42 output assigned to TRIGGER_SYNC_ASYNC_IN1 */ - kXBAR1_OutputTriggerSyncAsyncIn2 = 43|0x10000U, /**< XBAR1_OUT43 output assigned to TRIGGER_SYNC_ASYNC_IN2 */ - kXBAR1_OutputTriggerSyncAsyncIn3 = 44|0x10000U, /**< XBAR1_OUT44 output assigned to TRIGGER_SYNC_ASYNC_IN3 */ - kXBAR1_OutputTriggerSyncAsyncIn4 = 45|0x10000U, /**< XBAR1_OUT45 output assigned to TRIGGER_SYNC_ASYNC_IN4 */ - kXBAR1_OutputTriggerSyncAsyncIn5 = 46|0x10000U, /**< XBAR1_OUT46 output assigned to TRIGGER_SYNC_ASYNC_IN5 */ - kXBAR1_OutputTriggerSyncAsyncIn6 = 47|0x10000U, /**< XBAR1_OUT47 output assigned to TRIGGER_SYNC_ASYNC_IN6 */ - kXBAR1_OutputTriggerSyncAsyncIn7 = 48|0x10000U, /**< XBAR1_OUT48 output assigned to TRIGGER_SYNC_ASYNC_IN7 */ - kXBAR1_OutputFlexpwm1Exta0 = 49|0x10000U, /**< XBAR1_OUT49 output assigned to FLEXPWM1_EXTA0 */ - kXBAR1_OutputFlexpwm1Exta1 = 50|0x10000U, /**< XBAR1_OUT50 output assigned to FLEXPWM1_EXTA1 */ - kXBAR1_OutputFlexpwm1Exta2 = 51|0x10000U, /**< XBAR1_OUT51 output assigned to FLEXPWM1_EXTA2 */ - kXBAR1_OutputFlexpwm1Exta3 = 52|0x10000U, /**< XBAR1_OUT52 output assigned to FLEXPWM1_EXTA3 */ - kXBAR1_OutputFlexpwm1ExtSync0 = 53|0x10000U, /**< XBAR1_OUT53 output assigned to FLEXPWM1_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm1ExtSync1 = 54|0x10000U, /**< XBAR1_OUT54 output assigned to FLEXPWM1_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm1ExtSync2 = 55|0x10000U, /**< XBAR1_OUT55 output assigned to FLEXPWM1_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm1ExtSync3 = 56|0x10000U, /**< XBAR1_OUT56 output assigned to FLEXPWM1_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm1ExtClk = 57|0x10000U, /**< XBAR1_OUT57 output assigned to FLEXPWM1_EXT_CLK */ - kXBAR1_OutputFlexpwm1IppIndFault0 = 58|0x10000U, /**< XBAR1_OUT58 output assigned to FLEXPWM1_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm1IppIndFault1 = 59|0x10000U, /**< XBAR1_OUT59 output assigned to FLEXPWM1_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm1IppIndFault2 = 60|0x10000U, /**< XBAR1_OUT60 output assigned to FLEXPWM1_IPP_IND_FAULT2 */ - kXBAR1_OutputFlexpwm1IppIndFault3 = 61|0x10000U, /**< XBAR1_OUT61 output assigned to FLEXPWM1_IPP_IND_FAULT3 */ - kXBAR1_OutputFlexpwm1ExtForce = 62|0x10000U, /**< XBAR1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */ - kXBAR1_OutputFlexpwm2Exta0 = 63|0x10000U, /**< XBAR1_OUT63 output assigned to FLEXPWM2_EXTA0 */ - kXBAR1_OutputFlexpwm2Exta1 = 64|0x10000U, /**< XBAR1_OUT64 output assigned to FLEXPWM2_EXTA1 */ - kXBAR1_OutputFlexpwm2Exta2 = 65|0x10000U, /**< XBAR1_OUT65 output assigned to FLEXPWM2_EXTA2 */ - kXBAR1_OutputFlexpwm2Exta3 = 66|0x10000U, /**< XBAR1_OUT66 output assigned to FLEXPWM2_EXTA3 */ - kXBAR1_OutputFlexpwm2ExtSync0 = 67|0x10000U, /**< XBAR1_OUT67 output assigned to FLEXPWM2_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm2ExtSync1 = 68|0x10000U, /**< XBAR1_OUT68 output assigned to FLEXPWM2_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm2ExtSync2 = 69|0x10000U, /**< XBAR1_OUT69 output assigned to FLEXPWM2_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm2ExtSync3 = 70|0x10000U, /**< XBAR1_OUT70 output assigned to FLEXPWM2_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm2ExtClk = 71|0x10000U, /**< XBAR1_OUT71 output assigned to FLEXPWM2_EXT_CLK */ - kXBAR1_OutputFlexpwm2IppIndFault0 = 72|0x10000U, /**< XBAR1_OUT72 output assigned to FLEXPWM2_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm2IppIndFault1 = 73|0x10000U, /**< XBAR1_OUT73 output assigned to FLEXPWM2_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm2ExtForce = 74|0x10000U, /**< XBAR1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */ - kXBAR1_OutputFlexpwm3Exta0 = 75|0x10000U, /**< XBAR1_OUT75 output assigned to FLEXPWM3_EXTA0 */ - kXBAR1_OutputFlexpwm3Exta1 = 76|0x10000U, /**< XBAR1_OUT76 output assigned to FLEXPWM3_EXTA1 */ - kXBAR1_OutputFlexpwm3Exta2 = 77|0x10000U, /**< XBAR1_OUT77 output assigned to FLEXPWM3_EXTA2 */ - kXBAR1_OutputFlexpwm3Exta3 = 78|0x10000U, /**< XBAR1_OUT78 output assigned to FLEXPWM3_EXTA3 */ - kXBAR1_OutputFlexpwm3ExtClk = 79|0x10000U, /**< XBAR1_OUT79 output assigned to FLEXPWM3_EXT_CLK */ - kXBAR1_OutputFlexpwm3ExtSync0 = 80|0x10000U, /**< XBAR1_OUT80 output assigned to FLEXPWM3_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm3ExtSync1 = 81|0x10000U, /**< XBAR1_OUT81 output assigned to FLEXPWM3_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm3ExtSync2 = 82|0x10000U, /**< XBAR1_OUT82 output assigned to FLEXPWM3_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm3ExtSync3 = 83|0x10000U, /**< XBAR1_OUT83 output assigned to FLEXPWM3_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm3IppIndFault0 = 84|0x10000U, /**< XBAR1_OUT84 output assigned to FLEXPWM3_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm3IppIndFault1 = 85|0x10000U, /**< XBAR1_OUT85 output assigned to FLEXPWM3_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm3ExtForce = 86|0x10000U, /**< XBAR1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */ - kXBAR1_OutputFlexpwm4ExtSync0 = 87|0x10000U, /**< XBAR1_OUT87 output assigned to FLEXPWM4_EXT_SYNC0 */ - kXBAR1_OutputFlexpwm4ExtSync1 = 88|0x10000U, /**< XBAR1_OUT88 output assigned to FLEXPWM4_EXT_SYNC1 */ - kXBAR1_OutputFlexpwm4ExtSync2 = 89|0x10000U, /**< XBAR1_OUT89 output assigned to FLEXPWM4_EXT_SYNC2 */ - kXBAR1_OutputFlexpwm4ExtSync3 = 90|0x10000U, /**< XBAR1_OUT90 output assigned to FLEXPWM4_EXT_SYNC3 */ - kXBAR1_OutputFlexpwm4IppIndFault0 = 91|0x10000U, /**< XBAR1_OUT91 output assigned to FLEXPWM4_IPP_IND_FAULT0 */ - kXBAR1_OutputFlexpwm4IppIndFault1 = 92|0x10000U, /**< XBAR1_OUT92 output assigned to FLEXPWM4_IPP_IND_FAULT1 */ - kXBAR1_OutputFlexpwm4ExtForce = 93|0x10000U, /**< XBAR1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */ - kXBAR1_OutputEnc1PhaseAInput = 94|0x10000U, /**< XBAR1_OUT94 output assigned to ENC1_PHASE_A_INPUT */ - kXBAR1_OutputEnc1PhaseBInput = 95|0x10000U, /**< XBAR1_OUT95 output assigned to ENC1_PHASE_B_INPUT */ - kXBAR1_OutputEnc1Index = 96|0x10000U, /**< XBAR1_OUT96 output assigned to ENC1_INDEX */ - kXBAR1_OutputEnc1Home = 97|0x10000U, /**< XBAR1_OUT97 output assigned to ENC1_HOME */ - kXBAR1_OutputEnc1Trigger = 98|0x10000U, /**< XBAR1_OUT98 output assigned to ENC1_TRIGGER */ - kXBAR1_OutputEnc2PhaseAInput = 99|0x10000U, /**< XBAR1_OUT99 output assigned to ENC2_PHASE_A_INPUT */ - kXBAR1_OutputEnc2PhaseBInput = 100|0x10000U, /**< XBAR1_OUT100 output assigned to ENC2_PHASE_B_INPUT */ - kXBAR1_OutputEnc2Index = 101|0x10000U, /**< XBAR1_OUT101 output assigned to ENC2_INDEX */ - kXBAR1_OutputEnc2Home = 102|0x10000U, /**< XBAR1_OUT102 output assigned to ENC2_HOME */ - kXBAR1_OutputEnc2Trigger = 103|0x10000U, /**< XBAR1_OUT103 output assigned to ENC2_TRIGGER */ - kXBAR1_OutputEnc3PhaseAInput = 104|0x10000U, /**< XBAR1_OUT104 output assigned to ENC3_PHASE_A_INPUT */ - kXBAR1_OutputEnc3PhaseBInput = 105|0x10000U, /**< XBAR1_OUT105 output assigned to ENC3_PHASE_B_INPUT */ - kXBAR1_OutputEnc3Index = 106|0x10000U, /**< XBAR1_OUT106 output assigned to ENC3_INDEX */ - kXBAR1_OutputEnc3Home = 107|0x10000U, /**< XBAR1_OUT107 output assigned to ENC3_HOME */ - kXBAR1_OutputEnc3Trigger = 108|0x10000U, /**< XBAR1_OUT108 output assigned to ENC3_TRIGGER */ - kXBAR1_OutputEnc4PhaseAInput = 109|0x10000U, /**< XBAR1_OUT109 output assigned to ENC4_PHASE_A_INPUT */ - kXBAR1_OutputEnc4PhaseBInput = 110|0x10000U, /**< XBAR1_OUT110 output assigned to ENC4_PHASE_B_INPUT */ - kXBAR1_OutputEnc4Index = 111|0x10000U, /**< XBAR1_OUT111 output assigned to ENC4_INDEX */ - kXBAR1_OutputEnc4Home = 112|0x10000U, /**< XBAR1_OUT112 output assigned to ENC4_HOME */ - kXBAR1_OutputEnc4Trigger = 113|0x10000U, /**< XBAR1_OUT113 output assigned to ENC4_TRIGGER */ - kXBAR1_OutputQtimer1Tmr0Input = 114|0x10000U, /**< XBAR1_OUT114 output assigned to QTIMER1_TMR0_INPUT */ - kXBAR1_OutputQtimer1Tmr1Input = 115|0x10000U, /**< XBAR1_OUT115 output assigned to QTIMER1_TMR1_INPUT */ - kXBAR1_OutputQtimer1Tmr2Input = 116|0x10000U, /**< XBAR1_OUT116 output assigned to QTIMER1_TMR2_INPUT */ - kXBAR1_OutputQtimer1Tmr3Input = 117|0x10000U, /**< XBAR1_OUT117 output assigned to QTIMER1_TMR3_INPUT */ - kXBAR1_OutputQtimer2Tmr0Input = 118|0x10000U, /**< XBAR1_OUT118 output assigned to QTIMER2_TMR0_INPUT */ - kXBAR1_OutputQtimer2Tmr1Input = 119|0x10000U, /**< XBAR1_OUT119 output assigned to QTIMER2_TMR1_INPUT */ - kXBAR1_OutputQtimer2Tmr2Input = 120|0x10000U, /**< XBAR1_OUT120 output assigned to QTIMER2_TMR2_INPUT */ - kXBAR1_OutputQtimer2Tmr3Input = 121|0x10000U, /**< XBAR1_OUT121 output assigned to QTIMER2_TMR3_INPUT */ - kXBAR1_OutputQtimer3Tmr0Input = 122|0x10000U, /**< XBAR1_OUT122 output assigned to QTIMER3_TMR0_INPUT */ - kXBAR1_OutputQtimer3Tmr1Input = 123|0x10000U, /**< XBAR1_OUT123 output assigned to QTIMER3_TMR1_INPUT */ - kXBAR1_OutputQtimer3Tmr2Input = 124|0x10000U, /**< XBAR1_OUT124 output assigned to QTIMER3_TMR2_INPUT */ - kXBAR1_OutputQtimer3Tmr3Input = 125|0x10000U, /**< XBAR1_OUT125 output assigned to QTIMER3_TMR3_INPUT */ - kXBAR1_OutputQtimer4Tmr0Input = 126|0x10000U, /**< XBAR1_OUT126 output assigned to QTIMER4_TMR0_INPUT */ - kXBAR1_OutputQtimer4Tmr1Input = 127|0x10000U, /**< XBAR1_OUT127 output assigned to QTIMER4_TMR1_INPUT */ - kXBAR1_OutputQtimer4Tmr2Input = 128|0x10000U, /**< XBAR1_OUT128 output assigned to QTIMER4_TMR2_INPUT */ - kXBAR1_OutputQtimer4Tmr3Input = 129|0x10000U, /**< XBAR1_OUT129 output assigned to QTIMER4_TMR3_INPUT */ - kXBAR1_OutputQtimer5Tmr0Input = 130|0x10000U, /**< XBAR1_OUT130 output assigned to QTIMER5_TMR0_INPUT */ - kXBAR1_OutputQtimer5Tmr1Input = 131|0x10000U, /**< XBAR1_OUT131 output assigned to QTIMER5_TMR1_INPUT */ - kXBAR1_OutputQtimer5Tmr2Input = 132|0x10000U, /**< XBAR1_OUT132 output assigned to QTIMER5_TMR2_INPUT */ - kXBAR1_OutputQtimer5Tmr3Input = 133|0x10000U, /**< XBAR1_OUT133 output assigned to QTIMER5_TMR3_INPUT */ - kXBAR1_OutputQtimer6Tmr0Input = 134|0x10000U, /**< XBAR1_OUT134 output assigned to QTIMER6_TMR0_INPUT */ - kXBAR1_OutputQtimer6Tmr1Input = 135|0x10000U, /**< XBAR1_OUT135 output assigned to QTIMER6_TMR1_INPUT */ - kXBAR1_OutputQtimer6Tmr2Input = 136|0x10000U, /**< XBAR1_OUT136 output assigned to QTIMER6_TMR2_INPUT */ - kXBAR1_OutputQtimer6Tmr3Input = 137|0x10000U, /**< XBAR1_OUT137 output assigned to QTIMER6_TMR3_INPUT */ - kXBAR1_OutputQtimer7Tmr0Input = 138|0x10000U, /**< XBAR1_OUT138 output assigned to QTIMER7_TMR0_INPUT */ - kXBAR1_OutputQtimer7Tmr1Input = 139|0x10000U, /**< XBAR1_OUT139 output assigned to QTIMER7_TMR1_INPUT */ - kXBAR1_OutputQtimer7Tmr2Input = 140|0x10000U, /**< XBAR1_OUT140 output assigned to QTIMER7_TMR2_INPUT */ - kXBAR1_OutputQtimer7Tmr3Input = 141|0x10000U, /**< XBAR1_OUT141 output assigned to QTIMER7_TMR3_INPUT */ - kXBAR1_OutputQtimer8Tmr0Input = 142|0x10000U, /**< XBAR1_OUT142 output assigned to QTIMER8_TMR0_INPUT */ - kXBAR1_OutputQtimer8Tmr1Input = 143|0x10000U, /**< XBAR1_OUT143 output assigned to QTIMER8_TMR1_INPUT */ - kXBAR1_OutputQtimer8Tmr2Input = 144|0x10000U, /**< XBAR1_OUT144 output assigned to QTIMER8_TMR2_INPUT */ - kXBAR1_OutputQtimer8Tmr3Input = 145|0x10000U, /**< XBAR1_OUT145 output assigned to QTIMER8_TMR3_INPUT */ - kXBAR1_OutputEwmEwmIn = 146|0x10000U, /**< XBAR1_OUT146 output assigned to EWM_EWM_IN */ - kXBAR1_OutputAnamixGlueTrgmuxInjectionTrg = 147|0x10000U, /**< XBAR1_OUT147 output assigned to ANAMIX_GLUE_TRGMUX_INJECTION_TRG */ - kXBAR1_OutputAnamixGlueTrgmuxStartTrg = 148|0x10000U, /**< XBAR1_OUT148 output assigned to ANAMIX_GLUE_TRGMUX_START_TRG */ - kXBAR1_OutputSinc1ExtTrigger0 = 149|0x10000U, /**< XBAR1_OUT149 output assigned to SINC1_EXT_TRIGGER0 */ - kXBAR1_OutputSinc1ExtTrigger1 = 150|0x10000U, /**< XBAR1_OUT150 output assigned to SINC1_EXT_TRIGGER1 */ - kXBAR1_OutputSinc1ExtTrigger2 = 151|0x10000U, /**< XBAR1_OUT151 output assigned to SINC1_EXT_TRIGGER2 */ - kXBAR1_OutputSinc1ExtTrigger3 = 152|0x10000U, /**< XBAR1_OUT152 output assigned to SINC1_EXT_TRIGGER3 */ - kXBAR1_OutputFlexio1FlexioTriggerIn0 = 153|0x10000U, /**< XBAR1_OUT153 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio1FlexioTriggerIn1 = 154|0x10000U, /**< XBAR1_OUT154 output assigned to FLEXIO1_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputFlexio2FlexioTriggerIn0 = 155|0x10000U, /**< XBAR1_OUT155 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio2FlexioTriggerIn1 = 156|0x10000U, /**< XBAR1_OUT156 output assigned to FLEXIO2_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputFlexio3FlexioTriggerIn0 = 157|0x10000U, /**< XBAR1_OUT157 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio3FlexioTriggerIn1 = 158|0x10000U, /**< XBAR1_OUT158 output assigned to FLEXIO3_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputFlexio4FlexioTriggerIn0 = 159|0x10000U, /**< XBAR1_OUT159 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN0 */ - kXBAR1_OutputFlexio4FlexioTriggerIn1 = 160|0x10000U, /**< XBAR1_OUT160 output assigned to FLEXIO4_FLEXIO_TRIGGER_IN1 */ - kXBAR1_OutputLpi2c1Lpi2cTrgInput = 161|0x10000U, /**< XBAR1_OUT161 output assigned to LPI2C1_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c2Lpi2cTrgInput = 162|0x10000U, /**< XBAR1_OUT162 output assigned to LPI2C2_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c3Lpi2cTrgInput = 163|0x10000U, /**< XBAR1_OUT163 output assigned to LPI2C3_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c4Lpi2cTrgInput = 164|0x10000U, /**< XBAR1_OUT164 output assigned to LPI2C4_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c5Lpi2cTrgInput = 165|0x10000U, /**< XBAR1_OUT165 output assigned to LPI2C5_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c6Lpi2cTrgInput = 166|0x10000U, /**< XBAR1_OUT166 output assigned to LPI2C6_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c7Lpi2cTrgInput = 167|0x10000U, /**< XBAR1_OUT167 output assigned to LPI2C7_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpi2c8Lpi2cTrgInput = 168|0x10000U, /**< XBAR1_OUT168 output assigned to LPI2C8_LPI2C_TRG_INPUT */ - kXBAR1_OutputLpspi1LpspiTrgInput = 169|0x10000U, /**< XBAR1_OUT169 output assigned to LPSPI1_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi2LpspiTrgInput = 170|0x10000U, /**< XBAR1_OUT170 output assigned to LPSPI2_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi3LpspiTrgInput = 171|0x10000U, /**< XBAR1_OUT171 output assigned to LPSPI3_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi4LpspiTrgInput = 172|0x10000U, /**< XBAR1_OUT172 output assigned to LPSPI4_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi5LpspiTrgInput = 173|0x10000U, /**< XBAR1_OUT173 output assigned to LPSPI5_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi6LpspiTrgInput = 174|0x10000U, /**< XBAR1_OUT174 output assigned to LPSPI6_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi7LpspiTrgInput = 175|0x10000U, /**< XBAR1_OUT175 output assigned to LPSPI7_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpspi8LpspiTrgInput = 176|0x10000U, /**< XBAR1_OUT176 output assigned to LPSPI8_LPSPI_TRG_INPUT */ - kXBAR1_OutputLpuart1LpuartTrgInput = 177|0x10000U, /**< XBAR1_OUT177 output assigned to LPUART1_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart2LpuartTrgInput = 178|0x10000U, /**< XBAR1_OUT178 output assigned to LPUART2_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart3LpuartTrgInput = 179|0x10000U, /**< XBAR1_OUT179 output assigned to LPUART3_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart4LpuartTrgInput = 180|0x10000U, /**< XBAR1_OUT180 output assigned to LPUART4_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart5LpuartTrgInput = 181|0x10000U, /**< XBAR1_OUT181 output assigned to LPUART5_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart6LpuartTrgInput = 182|0x10000U, /**< XBAR1_OUT182 output assigned to LPUART6_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart7LpuartTrgInput = 183|0x10000U, /**< XBAR1_OUT183 output assigned to LPUART7_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart8LpuartTrgInput = 184|0x10000U, /**< XBAR1_OUT184 output assigned to LPUART8_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart9LpuartTrgInput = 185|0x10000U, /**< XBAR1_OUT185 output assigned to LPUART9_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart10LpuartTrgInput = 186|0x10000U, /**< XBAR1_OUT186 output assigned to LPUART10_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart11LpuartTrgInput = 187|0x10000U, /**< XBAR1_OUT187 output assigned to LPUART11_LPUART_TRG_INPUT */ - kXBAR1_OutputLpuart12LpuartTrgInput = 188|0x10000U, /**< XBAR1_OUT188 output assigned to LPUART12_LPUART_TRG_INPUT */ - kXBAR1_OutputLpit1LpitExtTrigIn0 = 189|0x10000U, /**< XBAR1_OUT189 output assigned to LPIT1_LPIT_EXT_TRIG_IN0 */ - kXBAR1_OutputLpit1LpitExtTrigIn1 = 190|0x10000U, /**< XBAR1_OUT190 output assigned to LPIT1_LPIT_EXT_TRIG_IN1 */ - kXBAR1_OutputLpit1LpitExtTrigIn2 = 191|0x10000U, /**< XBAR1_OUT191 output assigned to LPIT1_LPIT_EXT_TRIG_IN2 */ - kXBAR1_OutputLpit1LpitExtTrigIn3 = 192|0x10000U, /**< XBAR1_OUT192 output assigned to LPIT1_LPIT_EXT_TRIG_IN3 */ - kXBAR1_OutputTpm1LptpmTriggerIn0 = 193|0x10000U, /**< XBAR1_OUT193 output assigned to TPM1_LPTPM_TRIGGER_IN0 */ - kXBAR1_OutputTpm1LptpmTriggerIn1 = 194|0x10000U, /**< XBAR1_OUT194 output assigned to TPM1_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm2LptpmTriggerIn1 = 195|0x10000U, /**< XBAR1_OUT195 output assigned to TPM2_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm3LptpmTriggerIn1 = 196|0x10000U, /**< XBAR1_OUT196 output assigned to TPM3_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm1LptpmTriggerIn2 = 197|0x10000U, /**< XBAR1_OUT197 output assigned to TPM1_LPTPM_TRIGGER_IN2 */ - kXBAR1_OutputTpm1LptpmTriggerIn3 = 198|0x10000U, /**< XBAR1_OUT198 output assigned to TPM1_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm2LptpmTriggerIn3 = 199|0x10000U, /**< XBAR1_OUT199 output assigned to TPM2_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm3LptpmTriggerIn3 = 200|0x10000U, /**< XBAR1_OUT200 output assigned to TPM3_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm4LptpmTriggerIn0 = 201|0x10000U, /**< XBAR1_OUT201 output assigned to TPM4_LPTPM_TRIGGER_IN0 */ - kXBAR1_OutputTpm4LptpmTriggerIn1 = 202|0x10000U, /**< XBAR1_OUT202 output assigned to TPM4_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm5LptpmTriggerIn1 = 203|0x10000U, /**< XBAR1_OUT203 output assigned to TPM5_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm6LptpmTriggerIn1 = 204|0x10000U, /**< XBAR1_OUT204 output assigned to TPM6_LPTPM_TRIGGER_IN1 */ - kXBAR1_OutputTpm4LptpmTriggerIn2 = 205|0x10000U, /**< XBAR1_OUT205 output assigned to TPM4_LPTPM_TRIGGER_IN2 */ - kXBAR1_OutputTpm4LptpmTriggerIn3 = 206|0x10000U, /**< XBAR1_OUT206 output assigned to TPM4_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm5LptpmTriggerIn3 = 207|0x10000U, /**< XBAR1_OUT207 output assigned to TPM5_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputTpm6LptpmTriggerIn3 = 208|0x10000U, /**< XBAR1_OUT208 output assigned to TPM6_LPTPM_TRIGGER_IN3 */ - kXBAR1_OutputNetcTmr11588Trig1 = 209|0x10000U, /**< XBAR1_OUT209 output assigned to NETC_TMR1_1588_TRIG1 */ - kXBAR1_OutputNetcTmr11588Trig2 = 210|0x10000U, /**< XBAR1_OUT210 output assigned to NETC_TMR1_1588_TRIG2 */ - kXBAR1_OutputNetcTmr21588Trig1 = 211|0x10000U, /**< XBAR1_OUT211 output assigned to NETC_TMR2_1588_TRIG1 */ - kXBAR1_OutputNetcTmr21588Trig2 = 212|0x10000U, /**< XBAR1_OUT212 output assigned to NETC_TMR2_1588_TRIG2 */ - kXBAR1_OutputNetcTmr31588Trig1 = 213|0x10000U, /**< XBAR1_OUT213 output assigned to NETC_TMR3_1588_TRIG1 */ - kXBAR1_OutputNetcTmr31588Trig2 = 214|0x10000U, /**< XBAR1_OUT214 output assigned to NETC_TMR3_1588_TRIG2 */ - kXBAR1_OutputEnc1Icap1 = 215|0x10000U, /**< XBAR1_OUT215 output assigned to ENC1_ICAP1 */ - kXBAR1_OutputEnc1Icap2 = 216|0x10000U, /**< XBAR1_OUT216 output assigned to ENC1_ICAP2 */ - kXBAR1_OutputEnc1Icap3 = 217|0x10000U, /**< XBAR1_OUT217 output assigned to ENC1_ICAP3 */ - kXBAR1_OutputEnc2Icap1 = 218|0x10000U, /**< XBAR1_OUT218 output assigned to ENC2_ICAP1 */ - kXBAR1_OutputEnc2Icap2 = 219|0x10000U, /**< XBAR1_OUT219 output assigned to ENC2_ICAP2 */ - kXBAR1_OutputEnc2Icap3 = 220|0x10000U, /**< XBAR1_OUT220 output assigned to ENC2_ICAP3 */ - kXBAR1_OutputEnc3Icap1 = 221|0x10000U, /**< XBAR1_OUT221 output assigned to ENC3_ICAP1 */ - kXBAR1_OutputEnc3Icap2 = 222|0x10000U, /**< XBAR1_OUT222 output assigned to ENC3_ICAP2 */ - kXBAR1_OutputEnc3Icap3 = 223|0x10000U, /**< XBAR1_OUT223 output assigned to ENC3_ICAP3 */ - kXBAR1_OutputEnc4Icap1 = 224|0x10000U, /**< XBAR1_OUT224 output assigned to ENC4_ICAP1 */ - kXBAR1_OutputEnc4Icap2 = 225|0x10000U, /**< XBAR1_OUT225 output assigned to ENC4_ICAP2 */ - kXBAR1_OutputEnc4Icap3 = 226|0x10000U, /**< XBAR1_OUT226 output assigned to ENC4_ICAP3 */ - kXBAR1_OutputEcatLatchIn0 = 227|0x10000U, /**< XBAR1_OUT227 output assigned to ECAT_LATCH_IN0 */ - kXBAR1_OutputEcatLatchIn1 = 228|0x10000U, /**< XBAR1_OUT228 output assigned to ECAT_LATCH_IN1 */ - kXBAR1_OutputSafetyClkMonDutClk = 229|0x10000U, /**< XBAR1_OUT229 output assigned to SAFETY_CLK_MON_DUT_CLK */ - kXBAR1_OutputEndat21StrN = 230|0x10000U, /**< XBAR1_OUT230 output assigned to ENDAT2_1_STR_N */ - kXBAR1_OutputEndat21Ir6N = 231|0x10000U, /**< XBAR1_OUT231 output assigned to ENDAT2_1_IR6_N */ - kXBAR1_OutputEndat21Ir7N = 232|0x10000U, /**< XBAR1_OUT232 output assigned to ENDAT2_1_IR7_N */ - kXBAR1_OutputEndat22StrN = 233|0x10000U, /**< XBAR1_OUT233 output assigned to ENDAT2_2_STR_N */ - kXBAR1_OutputEndat22Ir6N = 234|0x10000U, /**< XBAR1_OUT234 output assigned to ENDAT2_2_IR6_N */ - kXBAR1_OutputEndat22Ir7N = 235|0x10000U, /**< XBAR1_OUT235 output assigned to ENDAT2_2_IR7_N */ - kXBAR1_OutputEndat3HwStrobe = 236|0x10000U, /**< XBAR1_OUT236 output assigned to ENDAT3_HW_STROBE */ - kXBAR1_OutputBissGetsens = 237|0x10000U, /**< XBAR1_OUT237 output assigned to BISS_GETSENS */ - kXBAR1_OutputSinc3ExtTrigger2 = 238|0x10000U, /**< XBAR1_OUT238 output assigned to SINC3_EXT_TRIGGER2 */ - kXBAR1_OutputSinc3ExtTrigger3 = 239|0x10000U, /**< XBAR1_OUT239 output assigned to SINC3_EXT_TRIGGER3 */ - kXBAR1_OutputHiperface1SyncXbar = 240|0x10000U, /**< XBAR1_OUT240 output assigned to HIPERFACE1_SYNC_XBAR */ - kXBAR1_OutputHiperface2SyncXbar = 241|0x10000U, /**< XBAR1_OUT241 output assigned to HIPERFACE2_SYNC_XBAR */ - kXBAR1_OutputTriggerSyncAsyncIn8 = 242|0x10000U, /**< XBAR1_OUT242 output assigned to TRIGGER_SYNC_ASYNC_IN8 */ - kXBAR1_OutputTriggerSyncAsyncIn9 = 243|0x10000U, /**< XBAR1_OUT243 output assigned to TRIGGER_SYNC_ASYNC_IN9 */ - kXBAR1_OutputTriggerSyncAsyncIn10 = 244|0x10000U, /**< XBAR1_OUT244 output assigned to TRIGGER_SYNC_ASYNC_IN10 */ - kXBAR1_OutputTriggerSyncAsyncIn11 = 245|0x10000U, /**< XBAR1_OUT245 output assigned to TRIGGER_SYNC_ASYNC_IN11 */ - kXBAR1_OutputTriggerSyncAsyncIn12 = 246|0x10000U, /**< XBAR1_OUT246 output assigned to TRIGGER_SYNC_ASYNC_IN12 */ - kXBAR1_OutputTriggerSyncAsyncIn13 = 247|0x10000U, /**< XBAR1_OUT247 output assigned to TRIGGER_SYNC_ASYNC_IN13 */ - kXBAR1_OutputTriggerSyncAsyncIn14 = 248|0x10000U, /**< XBAR1_OUT248 output assigned to TRIGGER_SYNC_ASYNC_IN14 */ - kXBAR1_OutputTriggerSyncAsyncIn15 = 249|0x10000U, /**< XBAR1_OUT249 output assigned to TRIGGER_SYNC_ASYNC_IN15 */ - kXBAR1_OutputSinc2ExtTrigger0 = 250|0x10000U, /**< XBAR1_OUT250 output assigned to SINC2_EXT_TRIGGER0 */ - kXBAR1_OutputSinc2ExtTrigger1 = 251|0x10000U, /**< XBAR1_OUT251 output assigned to SINC2_EXT_TRIGGER1 */ - kXBAR1_OutputSinc2ExtTrigger2 = 252|0x10000U, /**< XBAR1_OUT252 output assigned to SINC2_EXT_TRIGGER2 */ - kXBAR1_OutputSinc2ExtTrigger3 = 253|0x10000U, /**< XBAR1_OUT253 output assigned to SINC2_EXT_TRIGGER3 */ - kXBAR1_OutputSinc3ExtTrigger0 = 254|0x10000U, /**< XBAR1_OUT254 output assigned to SINC3_EXT_TRIGGER0 */ - kXBAR1_OutputSinc3ExtTrigger1 = 255|0x10000U, /**< XBAR1_OUT255 output assigned to SINC3_EXT_TRIGGER1 */ - kXBAR2_OutputAoi1In00 = 0|0x20000U, /**< XBAR2_OUT0 output assigned to AOI1_IN00 */ - kXBAR2_OutputAoi1In01 = 1|0x20000U, /**< XBAR2_OUT1 output assigned to AOI1_IN01 */ - kXBAR2_OutputAoi1In02 = 2|0x20000U, /**< XBAR2_OUT2 output assigned to AOI1_IN02 */ - kXBAR2_OutputAoi1In03 = 3|0x20000U, /**< XBAR2_OUT3 output assigned to AOI1_IN03 */ - kXBAR2_OutputAoi1In04 = 4|0x20000U, /**< XBAR2_OUT4 output assigned to AOI1_IN04 */ - kXBAR2_OutputAoi1In05 = 5|0x20000U, /**< XBAR2_OUT5 output assigned to AOI1_IN05 */ - kXBAR2_OutputAoi1In06 = 6|0x20000U, /**< XBAR2_OUT6 output assigned to AOI1_IN06 */ - kXBAR2_OutputAoi1In07 = 7|0x20000U, /**< XBAR2_OUT7 output assigned to AOI1_IN07 */ - kXBAR2_OutputAoi1In08 = 8|0x20000U, /**< XBAR2_OUT8 output assigned to AOI1_IN08 */ - kXBAR2_OutputAoi1In09 = 9|0x20000U, /**< XBAR2_OUT9 output assigned to AOI1_IN09 */ - kXBAR2_OutputAoi1In10 = 10|0x20000U, /**< XBAR2_OUT10 output assigned to AOI1_IN10 */ - kXBAR2_OutputAoi1In11 = 11|0x20000U, /**< XBAR2_OUT11 output assigned to AOI1_IN11 */ - kXBAR2_OutputAoi1In12 = 12|0x20000U, /**< XBAR2_OUT12 output assigned to AOI1_IN12 */ - kXBAR2_OutputAoi1In13 = 13|0x20000U, /**< XBAR2_OUT13 output assigned to AOI1_IN13 */ - kXBAR2_OutputAoi1In14 = 14|0x20000U, /**< XBAR2_OUT14 output assigned to AOI1_IN14 */ - kXBAR2_OutputAoi1In15 = 15|0x20000U, /**< XBAR2_OUT15 output assigned to AOI1_IN15 */ - kXBAR2_OutputAoi3In00 = 16|0x20000U, /**< XBAR2_OUT16 output assigned to AOI3_IN00 */ - kXBAR2_OutputAoi3In01 = 17|0x20000U, /**< XBAR2_OUT17 output assigned to AOI3_IN01 */ - kXBAR2_OutputAoi3In02 = 18|0x20000U, /**< XBAR2_OUT18 output assigned to AOI3_IN02 */ - kXBAR2_OutputAoi3In03 = 19|0x20000U, /**< XBAR2_OUT19 output assigned to AOI3_IN03 */ - kXBAR2_OutputAoi3In04 = 20|0x20000U, /**< XBAR2_OUT20 output assigned to AOI3_IN04 */ - kXBAR2_OutputAoi3In05 = 21|0x20000U, /**< XBAR2_OUT21 output assigned to AOI3_IN05 */ - kXBAR2_OutputAoi3In06 = 22|0x20000U, /**< XBAR2_OUT22 output assigned to AOI3_IN06 */ - kXBAR2_OutputAoi3In07 = 23|0x20000U, /**< XBAR2_OUT23 output assigned to AOI3_IN07 */ - kXBAR2_OutputAoi3In08 = 24|0x20000U, /**< XBAR2_OUT24 output assigned to AOI3_IN08 */ - kXBAR2_OutputAoi3In09 = 25|0x20000U, /**< XBAR2_OUT25 output assigned to AOI3_IN09 */ - kXBAR2_OutputAoi3In10 = 26|0x20000U, /**< XBAR2_OUT26 output assigned to AOI3_IN10 */ - kXBAR2_OutputAoi3In11 = 27|0x20000U, /**< XBAR2_OUT27 output assigned to AOI3_IN11 */ - kXBAR2_OutputAoi3In12 = 28|0x20000U, /**< XBAR2_OUT28 output assigned to AOI3_IN12 */ - kXBAR2_OutputAoi3In13 = 29|0x20000U, /**< XBAR2_OUT29 output assigned to AOI3_IN13 */ - kXBAR2_OutputAoi3In14 = 30|0x20000U, /**< XBAR2_OUT30 output assigned to AOI3_IN14 */ - kXBAR2_OutputAoi3In15 = 31|0x20000U, /**< XBAR2_OUT31 output assigned to AOI3_IN15 */ - kXBAR3_OutputAoi2In00 = 0|0x30000U, /**< XBAR3_OUT0 output assigned to AOI2_IN00 */ - kXBAR3_OutputAoi2In01 = 1|0x30000U, /**< XBAR3_OUT1 output assigned to AOI2_IN01 */ - kXBAR3_OutputAoi2In02 = 2|0x30000U, /**< XBAR3_OUT2 output assigned to AOI2_IN02 */ - kXBAR3_OutputAoi2In03 = 3|0x30000U, /**< XBAR3_OUT3 output assigned to AOI2_IN03 */ - kXBAR3_OutputAoi2In04 = 4|0x30000U, /**< XBAR3_OUT4 output assigned to AOI2_IN04 */ - kXBAR3_OutputAoi2In05 = 5|0x30000U, /**< XBAR3_OUT5 output assigned to AOI2_IN05 */ - kXBAR3_OutputAoi2In06 = 6|0x30000U, /**< XBAR3_OUT6 output assigned to AOI2_IN06 */ - kXBAR3_OutputAoi2In07 = 7|0x30000U, /**< XBAR3_OUT7 output assigned to AOI2_IN07 */ - kXBAR3_OutputAoi2In08 = 8|0x30000U, /**< XBAR3_OUT8 output assigned to AOI2_IN08 */ - kXBAR3_OutputAoi2In09 = 9|0x30000U, /**< XBAR3_OUT9 output assigned to AOI2_IN09 */ - kXBAR3_OutputAoi2In10 = 10|0x30000U, /**< XBAR3_OUT10 output assigned to AOI2_IN10 */ - kXBAR3_OutputAoi2In11 = 11|0x30000U, /**< XBAR3_OUT11 output assigned to AOI2_IN11 */ - kXBAR3_OutputAoi2In12 = 12|0x30000U, /**< XBAR3_OUT12 output assigned to AOI2_IN12 */ - kXBAR3_OutputAoi2In13 = 13|0x30000U, /**< XBAR3_OUT13 output assigned to AOI2_IN13 */ - kXBAR3_OutputAoi2In14 = 14|0x30000U, /**< XBAR3_OUT14 output assigned to AOI2_IN14 */ - kXBAR3_OutputAoi2In15 = 15|0x30000U, /**< XBAR3_OUT15 output assigned to AOI2_IN15 */ - kXBAR3_OutputAoi4In00 = 16|0x30000U, /**< XBAR3_OUT16 output assigned to AOI4_IN00 */ - kXBAR3_OutputAoi4In01 = 17|0x30000U, /**< XBAR3_OUT17 output assigned to AOI4_IN01 */ - kXBAR3_OutputAoi4In02 = 18|0x30000U, /**< XBAR3_OUT18 output assigned to AOI4_IN02 */ - kXBAR3_OutputAoi4In03 = 19|0x30000U, /**< XBAR3_OUT19 output assigned to AOI4_IN03 */ - kXBAR3_OutputAoi4In04 = 20|0x30000U, /**< XBAR3_OUT20 output assigned to AOI4_IN04 */ - kXBAR3_OutputAoi4In05 = 21|0x30000U, /**< XBAR3_OUT21 output assigned to AOI4_IN05 */ - kXBAR3_OutputAoi4In06 = 22|0x30000U, /**< XBAR3_OUT22 output assigned to AOI4_IN06 */ - kXBAR3_OutputAoi4In07 = 23|0x30000U, /**< XBAR3_OUT23 output assigned to AOI4_IN07 */ - kXBAR3_OutputAoi4In08 = 24|0x30000U, /**< XBAR3_OUT24 output assigned to AOI4_IN08 */ - kXBAR3_OutputAoi4In09 = 25|0x30000U, /**< XBAR3_OUT25 output assigned to AOI4_IN09 */ - kXBAR3_OutputAoi4In10 = 26|0x30000U, /**< XBAR3_OUT26 output assigned to AOI4_IN10 */ - kXBAR3_OutputAoi4In11 = 27|0x30000U, /**< XBAR3_OUT27 output assigned to AOI4_IN11 */ - kXBAR3_OutputAoi4In12 = 28|0x30000U, /**< XBAR3_OUT28 output assigned to AOI4_IN12 */ - kXBAR3_OutputAoi4In13 = 29|0x30000U, /**< XBAR3_OUT29 output assigned to AOI4_IN13 */ - kXBAR3_OutputAoi4In14 = 30|0x30000U, /**< XBAR3_OUT30 output assigned to AOI4_IN14 */ - kXBAR3_OutputAoi4In15 = 31|0x30000U, /**< XBAR3_OUT31 output assigned to AOI4_IN15 */ -} xbar_output_signal_t; -#endif /* XBAR_OUTPUT_SIGNAL_T_ */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -1428,5 +336,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* XBAR3_H_ */ +#endif /* PERI_XBAR3_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XCACHE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XCACHE.h index 8d360a80a..e70db4a59 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XCACHE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XCACHE.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCACHE @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file XCACHE.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_XCACHE.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for XCACHE * * CMSIS Peripheral Access Layer for XCACHE */ -#if !defined(XCACHE_H_) -#define XCACHE_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_XCACHE_H_) +#define PERI_XCACHE_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -452,5 +455,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* XCACHE_H_ */ +#endif /* PERI_XCACHE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XSPI.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XSPI.h index cc2565e2e..83f41f1cc 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XSPI.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_XSPI.h @@ -121,8 +121,8 @@ ** MIMX94398XVMM_cm7_core0 ** MIMX94398XVMM_cm7_core1 ** -** Version: rev. 1.0, 2023-11-01 -** Build: b250109 +** Version: rev. 2.0, 2024-10-29 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for XSPI @@ -157,21 +157,24 @@ ** +---------------------------------------------------------------------+ ** | ca55_core3 | a55, ca55, a55_3, ca55_3 | ** +---------------------------------------------------------------------+ +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ /*! - * @file XSPI.h - * @version 1.0 - * @date 2023-11-01 + * @file PERI_XSPI.h + * @version 2.0 + * @date 2024-10-29 * @brief CMSIS Peripheral Access Layer for XSPI * * CMSIS Peripheral Access Layer for XSPI */ -#if !defined(XSPI_H_) -#define XSPI_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(PERI_XSPI_H_) +#define PERI_XSPI_H_ /**< Symbol preventing repeated inclusion */ #if (defined(CPU_MIMX94398AVKE_ca55) || defined(CPU_MIMX94398AVKJ_ca55) || defined(CPU_MIMX94398AVKM_ca55) || defined(CPU_MIMX94398AVME_ca55) || defined(CPU_MIMX94398AVMJ_ca55) || defined(CPU_MIMX94398AVMM_ca55) || defined(CPU_MIMX94398CVKE_ca55) || defined(CPU_MIMX94398CVKJ_ca55) || defined(CPU_MIMX94398CVKM_ca55) || defined(CPU_MIMX94398CVME_ca55) || defined(CPU_MIMX94398CVMJ_ca55) || defined(CPU_MIMX94398CVMM_ca55) || defined(CPU_MIMX94398DVKE_ca55) || defined(CPU_MIMX94398DVKJ_ca55) || defined(CPU_MIMX94398DVKM_ca55) || defined(CPU_MIMX94398DVME_ca55) || defined(CPU_MIMX94398DVMJ_ca55) || defined(CPU_MIMX94398DVMM_ca55) || defined(CPU_MIMX94398XVKE_ca55) || defined(CPU_MIMX94398XVKJ_ca55) || defined(CPU_MIMX94398XVKM_ca55) || defined(CPU_MIMX94398XVME_ca55) || defined(CPU_MIMX94398XVMJ_ca55) || defined(CPU_MIMX94398XVMM_ca55)) #include "MIMX94398_ca55_COMMON.h" @@ -657,8 +660,8 @@ typedef struct { /*! IPS_TG_RST - Software Reset for IPS Target Group Queue 0 * 0b0..No action * 0b0..No action - * 0b1..Resets * 0b1..Reset of IPS TG queue is in progress if is having TG Grant + * 0b1..Resets */ #define XSPI_MCR_IPS_TG_RST(x) (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_IPS_TG_RST_SHIFT)) & XSPI_MCR_IPS_TG_RST_MASK) @@ -1715,230 +1718,230 @@ typedef struct { #define XSPI_FR_TFF_MASK (0x1U) #define XSPI_FR_TFF_SHIFT (0U) /*! TFF - IP Command Transaction Finished Flag - * 0b0..Not completed * 0b0..No action - * 0b1..Completed + * 0b0..Not completed * 0b1..Clears flag + * 0b1..Completed */ #define XSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_TFF_SHIFT)) & XSPI_FR_TFF_MASK) #define XSPI_FR_RDADDR_MASK (0x2U) #define XSPI_FR_RDADDR_SHIFT (1U) /*! RDADDR - AHB Read Address Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears flag + * 0b1..Error */ #define XSPI_FR_RDADDR(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_RDADDR_SHIFT)) & XSPI_FR_RDADDR_MASK) #define XSPI_FR_PERFOVF_MASK (0x4U) #define XSPI_FR_PERFOVF_SHIFT (2U) /*! PERFOVF - AHB Performance Monitor Overflow Flag - * 0b0..No overflow * 0b0..No action - * 0b1..Overflow + * 0b0..No overflow * 0b1..Clears flags + * 0b1..Overflow */ #define XSPI_FR_PERFOVF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_PERFOVF_SHIFT)) & XSPI_FR_PERFOVF_MASK) #define XSPI_FR_ARDB_TO_MASK (0x8U) #define XSPI_FR_ARDB_TO_SHIFT (3U) /*! ARDB_TO - ARDB Timeout - * 0b0..No timeout * 0b0..No action - * 0b1..Timeout + * 0b0..No timeout * 0b1..Clears flags + * 0b1..Timeout */ #define XSPI_FR_ARDB_TO(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_ARDB_TO_SHIFT)) & XSPI_FR_ARDB_TO_MASK) #define XSPI_FR_IPEDERR_MASK (0x20U) #define XSPI_FR_IPEDERR_SHIFT (5U) /*! IPEDERR - IPED RX Decryption Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears error flag + * 0b1..Error */ #define XSPI_FR_IPEDERR(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_IPEDERR_SHIFT)) & XSPI_FR_IPEDERR_MASK) #define XSPI_FR_IPIEF_MASK (0x40U) #define XSPI_FR_IPIEF_SHIFT (6U) /*! IPIEF - IP Command Trigger Fail Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears error flag + * 0b1..Error */ #define XSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_IPIEF_SHIFT)) & XSPI_FR_IPIEF_MASK) #define XSPI_FR_PPWF_MASK (0x100U) #define XSPI_FR_PPWF_SHIFT (8U) /*! PPWF - Page-Program Wait Flag - * 0b0..No page program wait * 0b0..No action - * 0b1..Page program wait in effect + * 0b0..No page program wait * 0b1..Clears flag + * 0b1..Page program wait in effect */ #define XSPI_FR_PPWF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_PPWF_SHIFT)) & XSPI_FR_PPWF_MASK) #define XSPI_FR_CRCAEF_MASK (0x400U) #define XSPI_FR_CRCAEF_SHIFT (10U) /*! CRCAEF - CRC Error Flash Memory A Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears error flag + * 0b1..Error */ #define XSPI_FR_CRCAEF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_CRCAEF_SHIFT)) & XSPI_FR_CRCAEF_MASK) #define XSPI_FR_ABOF_MASK (0x1000U) #define XSPI_FR_ABOF_SHIFT (12U) /*! ABOF - AHB Buffer Overflow Flag - * 0b0..No overflow * 0b0..No action - * 0b1..Overflow + * 0b0..No overflow * 0b1..Clears overflow flag + * 0b1..Overflow */ #define XSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_ABOF_SHIFT)) & XSPI_FR_ABOF_MASK) #define XSPI_FR_AIBSEF_MASK (0x2000U) #define XSPI_FR_AIBSEF_SHIFT (13U) /*! AIBSEF - AHB Illegal Burst Size Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears error flag + * 0b1..Error */ #define XSPI_FR_AIBSEF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_AIBSEF_SHIFT)) & XSPI_FR_AIBSEF_MASK) #define XSPI_FR_AITEF_MASK (0x4000U) #define XSPI_FR_AITEF_SHIFT (14U) /*! AITEF - AHB Illegal Transaction Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears error flag + * 0b1..Error */ #define XSPI_FR_AITEF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_AITEF_SHIFT)) & XSPI_FR_AITEF_MASK) #define XSPI_FR_AAEF_MASK (0x8000U) #define XSPI_FR_AAEF_SHIFT (15U) /*! AAEF - AHB Abort Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears error flag + * 0b1..Error */ #define XSPI_FR_AAEF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_AAEF_SHIFT)) & XSPI_FR_AAEF_MASK) #define XSPI_FR_RBDF_MASK (0x10000U) #define XSPI_FR_RBDF_SHIFT (16U) /*! RBDF - RX Buffer Drain Flag - * 0b0..RX buffer is not over the watermark * 0b0..No action - * 0b1..RX buffer is over the watermark + * 0b0..RX buffer is not over the watermark * 0b1..Clears flag if RX buffer is not over the watermark after POP + * 0b1..RX buffer is over the watermark */ #define XSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_RBDF_SHIFT)) & XSPI_FR_RBDF_MASK) #define XSPI_FR_RBOF_MASK (0x20000U) #define XSPI_FR_RBOF_SHIFT (17U) /*! RBOF - RX Buffer Overflow Flag - * 0b0..No overflow * 0b0..No action - * 0b1..Overflow + * 0b0..No overflow * 0b1..Clears flag + * 0b1..Overflow */ #define XSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_RBOF_SHIFT)) & XSPI_FR_RBOF_MASK) #define XSPI_FR_PECMDF_MASK (0x200000U) #define XSPI_FR_PECMDF_SHIFT (21U) /*! PECMDF - Program Execute Command Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears flag + * 0b1..Error */ #define XSPI_FR_PECMDF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_PECMDF_SHIFT)) & XSPI_FR_PECMDF_MASK) #define XSPI_FR_ILLACC_MASK (0x400000U) #define XSPI_FR_ILLACC_SHIFT (22U) /*! ILLACC - Illegal Access Event Flag - * 0b0..No event * 0b0..No action - * 0b1..Illegal access event + * 0b0..No event * 0b1..Clears flag + * 0b1..Illegal access event */ #define XSPI_FR_ILLACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_ILLACC_SHIFT)) & XSPI_FR_ILLACC_MASK) #define XSPI_FR_ILLINE_MASK (0x800000U) #define XSPI_FR_ILLINE_SHIFT (23U) /*! ILLINE - Illegal Instruction Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears error flag + * 0b1..Error */ #define XSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_ILLINE_SHIFT)) & XSPI_FR_ILLINE_MASK) #define XSPI_FR_DLLUNLCK_MASK (0x1000000U) #define XSPI_FR_DLLUNLCK_SHIFT (24U) /*! DLLUNLCK - DLL Unlock - * 0b0..No unlock event * 0b0..No action - * 0b1..Unlock event has occurred + * 0b0..No unlock event * 0b1..Clears the flag + * 0b1..Unlock event has occurred */ #define XSPI_FR_DLLUNLCK(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_DLLUNLCK_SHIFT)) & XSPI_FR_DLLUNLCK_MASK) #define XSPI_FR_PRWF_MASK (0x2000000U) #define XSPI_FR_PRWF_SHIFT (25U) /*! PRWF - Page-Read Wait Flag - * 0b0..No page read wait * 0b0..No action - * 0b1..Page read wait in effect + * 0b0..No page read wait * 0b1..Clears flag + * 0b1..Page read wait in effect */ #define XSPI_FR_PRWF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_PRWF_SHIFT)) & XSPI_FR_PRWF_MASK) #define XSPI_FR_TBUF_MASK (0x4000000U) #define XSPI_FR_TBUF_SHIFT (26U) /*! TBUF - TX Buffer Underrun Flag - * 0b0..No underrun * 0b0..No action - * 0b1..Underrun + * 0b0..No underrun * 0b1..Clears flag + * 0b1..Underrun */ #define XSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_TBUF_SHIFT)) & XSPI_FR_TBUF_MASK) #define XSPI_FR_TBFF_MASK (0x8000000U) #define XSPI_FR_TBFF_SHIFT (27U) /*! TBFF - TX Buffer Fill Flag - * 0b0..No room in the TX buffer * 0b0..No action - * 0b1..TX buffer has room + * 0b0..No room in the TX buffer * 0b1..Clears flag + * 0b1..TX buffer has room */ #define XSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_TBFF_SHIFT)) & XSPI_FR_TBFF_MASK) #define XSPI_FR_DLLABRT_MASK (0x10000000U) #define XSPI_FR_DLLABRT_SHIFT (28U) /*! DLLABRT - DLL Terminate - * 0b0..No lock has occurred * 0b0..No action - * 0b1..DLL unlock occurred + * 0b0..No lock has occurred * 0b1..Clears flag + * 0b1..DLL unlock occurred */ #define XSPI_FR_DLLABRT(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_DLLABRT_SHIFT)) & XSPI_FR_DLLABRT_MASK) #define XSPI_FR_DLPFF_MASK (0x80000000U) #define XSPI_FR_DLPFF_SHIFT (31U) /*! DLPFF - Data Learning Pattern Failure Flag - * 0b0..No failure * 0b0..No action - * 0b1..Failure + * 0b0..No failure * 0b1..Clears flag + * 0b1..Failure */ #define XSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_DLPFF_SHIFT)) & XSPI_FR_DLPFF_MASK) /*! @} */ @@ -2825,40 +2828,40 @@ typedef struct { #define XSPI_MCR_EXT_IPS_TG_RST1_MASK (0x1U) #define XSPI_MCR_EXT_IPS_TG_RST1_SHIFT (0U) /*! IPS_TG_RST1 - TG Software Reset - * 0b0..No action * 0b0..Contains no useful information - * 0b1..Resets + * 0b0..No action * 0b1..Contains no useful information + * 0b1..Resets */ #define XSPI_MCR_EXT_IPS_TG_RST1(x) (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_EXT_IPS_TG_RST1_SHIFT)) & XSPI_MCR_EXT_IPS_TG_RST1_MASK) #define XSPI_MCR_EXT_IPS_TG_RST2_MASK (0x2U) #define XSPI_MCR_EXT_IPS_TG_RST2_SHIFT (1U) /*! IPS_TG_RST2 - TG Software Reset - * 0b0..No action * 0b0..Contains no useful information - * 0b1..Resets + * 0b0..No action * 0b1..Contains no useful information + * 0b1..Resets */ #define XSPI_MCR_EXT_IPS_TG_RST2(x) (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_EXT_IPS_TG_RST2_SHIFT)) & XSPI_MCR_EXT_IPS_TG_RST2_MASK) #define XSPI_MCR_EXT_IPS_TG_RST3_MASK (0x4U) #define XSPI_MCR_EXT_IPS_TG_RST3_SHIFT (2U) /*! IPS_TG_RST3 - TG Software Reset - * 0b0..No action * 0b0..Contains no useful information - * 0b1..Resets + * 0b0..No action * 0b1..Contains no useful information + * 0b1..Resets */ #define XSPI_MCR_EXT_IPS_TG_RST3(x) (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_EXT_IPS_TG_RST3_SHIFT)) & XSPI_MCR_EXT_IPS_TG_RST3_MASK) #define XSPI_MCR_EXT_IPS_TG_RST4_MASK (0x8U) #define XSPI_MCR_EXT_IPS_TG_RST4_SHIFT (3U) /*! IPS_TG_RST4 - TG Software Reset - * 0b0..No action * 0b0..Contains no useful information - * 0b1..Resets + * 0b0..No action * 0b1..Contains no useful information + * 0b1..Resets */ #define XSPI_MCR_EXT_IPS_TG_RST4(x) (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_EXT_IPS_TG_RST4_SHIFT)) & XSPI_MCR_EXT_IPS_TG_RST4_MASK) /*! @} */ @@ -4848,90 +4851,90 @@ typedef struct { #define XSPI_ERRSTAT_FRADMTCH_MASK (0x1U) #define XSPI_ERRSTAT_FRADMTCH_SHIFT (0U) /*! FRADMTCH - No FRAD Match Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRADMTCH(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRADMTCH_SHIFT)) & XSPI_ERRSTAT_FRADMTCH_MASK) #define XSPI_ERRSTAT_FRAD0ACC_MASK (0x2U) #define XSPI_ERRSTAT_FRAD0ACC_SHIFT (1U) /*! FRAD0ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD0ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD0ACC_SHIFT)) & XSPI_ERRSTAT_FRAD0ACC_MASK) #define XSPI_ERRSTAT_FRAD1ACC_MASK (0x4U) #define XSPI_ERRSTAT_FRAD1ACC_SHIFT (2U) /*! FRAD1ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD1ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD1ACC_SHIFT)) & XSPI_ERRSTAT_FRAD1ACC_MASK) #define XSPI_ERRSTAT_FRAD2ACC_MASK (0x8U) #define XSPI_ERRSTAT_FRAD2ACC_SHIFT (3U) /*! FRAD2ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD2ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD2ACC_SHIFT)) & XSPI_ERRSTAT_FRAD2ACC_MASK) #define XSPI_ERRSTAT_FRAD3ACC_MASK (0x10U) #define XSPI_ERRSTAT_FRAD3ACC_SHIFT (4U) /*! FRAD3ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD3ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD3ACC_SHIFT)) & XSPI_ERRSTAT_FRAD3ACC_MASK) #define XSPI_ERRSTAT_FRAD4ACC_MASK (0x20U) #define XSPI_ERRSTAT_FRAD4ACC_SHIFT (5U) /*! FRAD4ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD4ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD4ACC_SHIFT)) & XSPI_ERRSTAT_FRAD4ACC_MASK) #define XSPI_ERRSTAT_FRAD5ACC_MASK (0x40U) #define XSPI_ERRSTAT_FRAD5ACC_SHIFT (6U) /*! FRAD5ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD5ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD5ACC_SHIFT)) & XSPI_ERRSTAT_FRAD5ACC_MASK) #define XSPI_ERRSTAT_FRAD6ACC_MASK (0x80U) #define XSPI_ERRSTAT_FRAD6ACC_SHIFT (7U) /*! FRAD6ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD6ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD6ACC_SHIFT)) & XSPI_ERRSTAT_FRAD6ACC_MASK) #define XSPI_ERRSTAT_FRAD7ACC_MASK (0x100U) #define XSPI_ERRSTAT_FRAD7ACC_SHIFT (8U) /*! FRAD7ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD7ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD7ACC_SHIFT)) & XSPI_ERRSTAT_FRAD7ACC_MASK) @@ -4962,120 +4965,120 @@ typedef struct { #define XSPI_ERRSTAT_TO_ERR_MASK (0x4000U) #define XSPI_ERRSTAT_TO_ERR_SHIFT (14U) /*! TO_ERR - Timeout Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_TO_ERR(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_TO_ERR_SHIFT)) & XSPI_ERRSTAT_TO_ERR_MASK) #define XSPI_ERRSTAT_FRAD8ACC_MASK (0x10000U) #define XSPI_ERRSTAT_FRAD8ACC_SHIFT (16U) /*! FRAD8ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD8ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD8ACC_SHIFT)) & XSPI_ERRSTAT_FRAD8ACC_MASK) #define XSPI_ERRSTAT_FRAD9ACC_MASK (0x20000U) #define XSPI_ERRSTAT_FRAD9ACC_SHIFT (17U) /*! FRAD9ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD9ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD9ACC_SHIFT)) & XSPI_ERRSTAT_FRAD9ACC_MASK) #define XSPI_ERRSTAT_FRAD10ACC_MASK (0x40000U) #define XSPI_ERRSTAT_FRAD10ACC_SHIFT (18U) /*! FRAD10ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD10ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD10ACC_SHIFT)) & XSPI_ERRSTAT_FRAD10ACC_MASK) #define XSPI_ERRSTAT_FRAD11ACC_MASK (0x80000U) #define XSPI_ERRSTAT_FRAD11ACC_SHIFT (19U) /*! FRAD11ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD11ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD11ACC_SHIFT)) & XSPI_ERRSTAT_FRAD11ACC_MASK) #define XSPI_ERRSTAT_FRAD12ACC_MASK (0x100000U) #define XSPI_ERRSTAT_FRAD12ACC_SHIFT (20U) /*! FRAD12ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD12ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD12ACC_SHIFT)) & XSPI_ERRSTAT_FRAD12ACC_MASK) #define XSPI_ERRSTAT_FRAD13ACC_MASK (0x200000U) #define XSPI_ERRSTAT_FRAD13ACC_SHIFT (21U) /*! FRAD13ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD13ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD13ACC_SHIFT)) & XSPI_ERRSTAT_FRAD13ACC_MASK) #define XSPI_ERRSTAT_FRAD14ACC_MASK (0x400000U) #define XSPI_ERRSTAT_FRAD14ACC_SHIFT (22U) /*! FRAD14ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD14ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD14ACC_SHIFT)) & XSPI_ERRSTAT_FRAD14ACC_MASK) #define XSPI_ERRSTAT_FRAD15ACC_MASK (0x800000U) #define XSPI_ERRSTAT_FRAD15ACC_SHIFT (23U) /*! FRAD15ACC - FRAD Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_FRAD15ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_FRAD15ACC_SHIFT)) & XSPI_ERRSTAT_FRAD15ACC_MASK) #define XSPI_ERRSTAT_ARB_WIN_MASK (0x10000000U) #define XSPI_ERRSTAT_ARB_WIN_SHIFT (28U) /*! ARB_WIN - Arbitration Win Event Status - * 0b0..Request not granted or the interrupt is already cleared * 0b0..No action - * 0b1..Request granted and interrupt generated + * 0b0..Request not granted or the interrupt is already cleared * 0b1..Clears interrupt + * 0b1..Request granted and interrupt generated */ #define XSPI_ERRSTAT_ARB_WIN(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_ARB_WIN_SHIFT)) & XSPI_ERRSTAT_ARB_WIN_MASK) #define XSPI_ERRSTAT_ARB_LOCK_TO_MASK (0x20000000U) #define XSPI_ERRSTAT_ARB_LOCK_TO_SHIFT (29U) /*! ARB_LOCK_TO - Arbitration Lock Timeout Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears flag + * 0b1..Error */ #define XSPI_ERRSTAT_ARB_LOCK_TO(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_ARB_LOCK_TO_SHIFT)) & XSPI_ERRSTAT_ARB_LOCK_TO_MASK) #define XSPI_ERRSTAT_LOCK_ERR_MASK (0x40000000U) #define XSPI_ERRSTAT_LOCK_ERR_SHIFT (30U) /*! LOCK_ERR - Lock Register Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_LOCK_ERR(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_LOCK_ERR_SHIFT)) & XSPI_ERRSTAT_LOCK_ERR_MASK) /*! @} */ @@ -6809,10 +6812,10 @@ typedef struct { #define XSPI_MCR_SUB_IPS_TG_RST_MASK (0x200U) #define XSPI_MCR_SUB_IPS_TG_RST_SHIFT (9U) /*! IPS_TG_RST - IPS TG3 Software Reset - * 0b0..No action * 0b0..Contains no useful information - * 0b1..Resets + * 0b0..No action * 0b1..Contains no useful information + * 0b1..Resets */ #define XSPI_MCR_SUB_IPS_TG_RST(x) (((uint32_t)(((uint32_t)(x)) << XSPI_MCR_SUB_IPS_TG_RST_SHIFT)) & XSPI_MCR_SUB_IPS_TG_RST_MASK) @@ -7223,20 +7226,20 @@ typedef struct { #define XSPI_FR_SUB_TFF_MASK (0x1U) #define XSPI_FR_SUB_TFF_SHIFT (0U) /*! TFF - IP Command Transaction Finished Flag - * 0b0..Not completed * 0b0..No action - * 0b1..Completed + * 0b0..Not completed * 0b1..Clears flag + * 0b1..Completed */ #define XSPI_FR_SUB_TFF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_TFF_SHIFT)) & XSPI_FR_SUB_TFF_MASK) #define XSPI_FR_SUB_RDADDR_MASK (0x2U) #define XSPI_FR_SUB_RDADDR_SHIFT (1U) /*! RDADDR - AHB Read Address Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears flag + * 0b1..Error */ #define XSPI_FR_SUB_RDADDR(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_RDADDR_SHIFT)) & XSPI_FR_SUB_RDADDR_MASK) @@ -7251,40 +7254,40 @@ typedef struct { #define XSPI_FR_SUB_ARDB_TO_MASK (0x8U) #define XSPI_FR_SUB_ARDB_TO_SHIFT (3U) /*! ARDB_TO - ARDB Timeout - * 0b0..No timeout * 0b0..No action - * 0b1..Timeout + * 0b0..No timeout * 0b1..Clears flags + * 0b1..Timeout */ #define XSPI_FR_SUB_ARDB_TO(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_ARDB_TO_SHIFT)) & XSPI_FR_SUB_ARDB_TO_MASK) #define XSPI_FR_SUB_IPEDERR_MASK (0x20U) #define XSPI_FR_SUB_IPEDERR_SHIFT (5U) /*! IPEDERR - IPED RX Decryption Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears error flag + * 0b1..Error */ #define XSPI_FR_SUB_IPEDERR(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_IPEDERR_SHIFT)) & XSPI_FR_SUB_IPEDERR_MASK) #define XSPI_FR_SUB_IPIEF_MASK (0x40U) #define XSPI_FR_SUB_IPIEF_SHIFT (6U) /*! IPIEF - IP Command Trigger Fail Error Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears error flag + * 0b1..Error */ #define XSPI_FR_SUB_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_IPIEF_SHIFT)) & XSPI_FR_SUB_IPIEF_MASK) #define XSPI_FR_SUB_PPWF_MASK (0x100U) #define XSPI_FR_SUB_PPWF_SHIFT (8U) /*! PPWF - Page-Program Wait Flag - * 0b0..No page program wait * 0b0..No action - * 0b1..Page program wait in effect + * 0b0..No page program wait * 0b1..Clears flag + * 0b1..Page program wait in effect */ #define XSPI_FR_SUB_PPWF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_PPWF_SHIFT)) & XSPI_FR_SUB_PPWF_MASK) @@ -7299,10 +7302,10 @@ typedef struct { #define XSPI_FR_SUB_ABOF_MASK (0x1000U) #define XSPI_FR_SUB_ABOF_SHIFT (12U) /*! ABOF - AHB Buffer Overflow Flag - * 0b0..No overflow * 0b0..No action - * 0b1..Overflow + * 0b0..No overflow * 0b1..Clears overflow flag + * 0b1..Overflow */ #define XSPI_FR_SUB_ABOF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_ABOF_SHIFT)) & XSPI_FR_SUB_ABOF_MASK) @@ -7333,40 +7336,40 @@ typedef struct { #define XSPI_FR_SUB_RBDF_MASK (0x10000U) #define XSPI_FR_SUB_RBDF_SHIFT (16U) /*! RBDF - RX Buffer Drain Flag - * 0b0..RX buffer is not over the watermark * 0b0..No action - * 0b1..RX buffer is over the watermark + * 0b0..RX buffer is not over the watermark * 0b1..Clears flag if RX buffer is not over the watermark after POP + * 0b1..RX buffer is over the watermark */ #define XSPI_FR_SUB_RBDF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_RBDF_SHIFT)) & XSPI_FR_SUB_RBDF_MASK) #define XSPI_FR_SUB_RBOF_MASK (0x20000U) #define XSPI_FR_SUB_RBOF_SHIFT (17U) /*! RBOF - RX Buffer Overflow Flag - * 0b0..No overflow * 0b0..No action - * 0b1..Overflow + * 0b0..No overflow * 0b1..Clears flag + * 0b1..Overflow */ #define XSPI_FR_SUB_RBOF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_RBOF_SHIFT)) & XSPI_FR_SUB_RBOF_MASK) #define XSPI_FR_SUB_PECMDF_MASK (0x200000U) #define XSPI_FR_SUB_PECMDF_SHIFT (21U) /*! PECMDF - Program Execute Command Flag - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears flag + * 0b1..Error */ #define XSPI_FR_SUB_PECMDF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_PECMDF_SHIFT)) & XSPI_FR_SUB_PECMDF_MASK) #define XSPI_FR_SUB_ILLACC_MASK (0x400000U) #define XSPI_FR_SUB_ILLACC_SHIFT (22U) /*! ILLACC - Illegal Access Event Flag - * 0b0..No event * 0b0..No action - * 0b1..Illegal access event + * 0b0..No event * 0b1..Clears flag + * 0b1..Illegal access event */ #define XSPI_FR_SUB_ILLACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_ILLACC_SHIFT)) & XSPI_FR_SUB_ILLACC_MASK) @@ -7381,40 +7384,40 @@ typedef struct { #define XSPI_FR_SUB_PRWF_MASK (0x2000000U) #define XSPI_FR_SUB_PRWF_SHIFT (25U) /*! PRWF - Page-Read Wait Flag - * 0b0..No page read wait * 0b0..No action - * 0b1..Page read wait in effect + * 0b0..No page read wait * 0b1..Clears flag + * 0b1..Page read wait in effect */ #define XSPI_FR_SUB_PRWF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_PRWF_SHIFT)) & XSPI_FR_SUB_PRWF_MASK) #define XSPI_FR_SUB_TBUF_MASK (0x4000000U) #define XSPI_FR_SUB_TBUF_SHIFT (26U) /*! TBUF - TX Buffer Underrun Flag - * 0b0..No underrun * 0b0..No action - * 0b1..Underrun + * 0b0..No underrun * 0b1..Clears flag + * 0b1..Underrun */ #define XSPI_FR_SUB_TBUF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_TBUF_SHIFT)) & XSPI_FR_SUB_TBUF_MASK) #define XSPI_FR_SUB_TBFF_MASK (0x8000000U) #define XSPI_FR_SUB_TBFF_SHIFT (27U) /*! TBFF - TX Buffer Fill Flag - * 0b0..No room in the TX buffer * 0b0..No action - * 0b1..TX buffer has room + * 0b0..No room in the TX buffer * 0b1..Clears flag + * 0b1..TX buffer has room */ #define XSPI_FR_SUB_TBFF(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_TBFF_SHIFT)) & XSPI_FR_SUB_TBFF_MASK) #define XSPI_FR_SUB_DLLABRT_MASK (0x10000000U) #define XSPI_FR_SUB_DLLABRT_SHIFT (28U) /*! DLLABRT - DLL Abort - * 0b0..No lock has occurred * 0b0..No action - * 0b1..DLL unlock occurred + * 0b0..No lock has occurred * 0b1..Clears flag + * 0b1..DLL unlock occurred */ #define XSPI_FR_SUB_DLLABRT(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FR_SUB_DLLABRT_SHIFT)) & XSPI_FR_SUB_DLLABRT_MASK) @@ -8538,90 +8541,90 @@ typedef struct { #define XSPI_ERRSTAT_SUB_FRADMTCH_MASK (0x1U) #define XSPI_ERRSTAT_SUB_FRADMTCH_SHIFT (0U) /*! FRADMTCH - No FRAD Match Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRADMTCH(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRADMTCH_SHIFT)) & XSPI_ERRSTAT_SUB_FRADMTCH_MASK) #define XSPI_ERRSTAT_SUB_FRAD0ACC_MASK (0x2U) #define XSPI_ERRSTAT_SUB_FRAD0ACC_SHIFT (1U) /*! FRAD0ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD0ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD0ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD0ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD1ACC_MASK (0x4U) #define XSPI_ERRSTAT_SUB_FRAD1ACC_SHIFT (2U) /*! FRAD1ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD1ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD1ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD1ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD2ACC_MASK (0x8U) #define XSPI_ERRSTAT_SUB_FRAD2ACC_SHIFT (3U) /*! FRAD2ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD2ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD2ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD2ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD3ACC_MASK (0x10U) #define XSPI_ERRSTAT_SUB_FRAD3ACC_SHIFT (4U) /*! FRAD3ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD3ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD3ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD3ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD4ACC_MASK (0x20U) #define XSPI_ERRSTAT_SUB_FRAD4ACC_SHIFT (5U) /*! FRAD4ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD4ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD4ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD4ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD5ACC_MASK (0x40U) #define XSPI_ERRSTAT_SUB_FRAD5ACC_SHIFT (6U) /*! FRAD5ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD5ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD5ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD5ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD6ACC_MASK (0x80U) #define XSPI_ERRSTAT_SUB_FRAD6ACC_SHIFT (7U) /*! FRAD6ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD6ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD6ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD6ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD7ACC_MASK (0x100U) #define XSPI_ERRSTAT_SUB_FRAD7ACC_SHIFT (8U) /*! FRAD7ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD7ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD7ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD7ACC_MASK) @@ -8652,100 +8655,100 @@ typedef struct { #define XSPI_ERRSTAT_SUB_TO_ERR_MASK (0x4000U) #define XSPI_ERRSTAT_SUB_TO_ERR_SHIFT (14U) /*! TO_ERR - Timeout Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_TO_ERR(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_TO_ERR_SHIFT)) & XSPI_ERRSTAT_SUB_TO_ERR_MASK) #define XSPI_ERRSTAT_SUB_FRAD8ACC_MASK (0x10000U) #define XSPI_ERRSTAT_SUB_FRAD8ACC_SHIFT (16U) /*! FRAD8ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD8ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD8ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD8ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD9ACC_MASK (0x20000U) #define XSPI_ERRSTAT_SUB_FRAD9ACC_SHIFT (17U) /*! FRAD9ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD9ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD9ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD9ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD10ACC_MASK (0x40000U) #define XSPI_ERRSTAT_SUB_FRAD10ACC_SHIFT (18U) /*! FRAD10ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD10ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD10ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD10ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD11ACC_MASK (0x80000U) #define XSPI_ERRSTAT_SUB_FRAD11ACC_SHIFT (19U) /*! FRAD11ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD11ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD11ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD11ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD12ACC_MASK (0x100000U) #define XSPI_ERRSTAT_SUB_FRAD12ACC_SHIFT (20U) /*! FRAD12ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD12ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD12ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD12ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD13ACC_MASK (0x200000U) #define XSPI_ERRSTAT_SUB_FRAD13ACC_SHIFT (21U) /*! FRAD13ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD13ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD13ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD13ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD14ACC_MASK (0x400000U) #define XSPI_ERRSTAT_SUB_FRAD14ACC_SHIFT (22U) /*! FRAD14ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD14ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD14ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD14ACC_MASK) #define XSPI_ERRSTAT_SUB_FRAD15ACC_MASK (0x800000U) #define XSPI_ERRSTAT_SUB_FRAD15ACC_SHIFT (23U) /*! FRAD15ACC - FRADn Access Error - * 0b0..No error * 0b0..No action - * 0b1..Error + * 0b0..No error * 0b1..Clears + * 0b1..Error */ #define XSPI_ERRSTAT_SUB_FRAD15ACC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_FRAD15ACC_SHIFT)) & XSPI_ERRSTAT_SUB_FRAD15ACC_MASK) #define XSPI_ERRSTAT_SUB_ARB_WIN_MASK (0x10000000U) #define XSPI_ERRSTAT_SUB_ARB_WIN_SHIFT (28U) /*! ARB_WIN - Arbitration Win Event Status - * 0b0..Request not granted or the interrupt is already cleared * 0b0..No action - * 0b1..Request granted and interrupt generated + * 0b0..Request not granted or the interrupt is already cleared * 0b1..Clears interrupt + * 0b1..Request granted and interrupt generated */ #define XSPI_ERRSTAT_SUB_ARB_WIN(x) (((uint32_t)(((uint32_t)(x)) << XSPI_ERRSTAT_SUB_ARB_WIN_SHIFT)) & XSPI_ERRSTAT_SUB_ARB_WIN_MASK) @@ -9520,5 +9523,5 @@ typedef struct { */ /* end of group Peripheral_access_layer */ -#endif /* XSPI_H_ */ +#endif /* PERI_XSPI_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9506/MIMX9506_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9506/MIMX9506_cm7_features.h index ecad27369..055276495 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9506/MIMX9506_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9506/MIMX9506_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9534/MIMX9534_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9534/MIMX9534_cm7_features.h index 93f30208d..727888bec 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9534/MIMX9534_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9534/MIMX9534_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9536/MIMX9536_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9536/MIMX9536_cm7_features.h index 6d891a294..c5d65d659 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9536/MIMX9536_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9536/MIMX9536_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9546/MIMX9546_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9546/MIMX9546_cm7_features.h index 7a33919ce..2198c1116 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9546/MIMX9546_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9546/MIMX9546_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9554/MIMX9554_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9554/MIMX9554_cm7_features.h index e54876351..2f6ac3125 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9554/MIMX9554_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9554/MIMX9554_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9556/MIMX9556_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9556/MIMX9556_cm7_features.h index 26b92f456..502205022 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9556/MIMX9556_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9556/MIMX9556_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9574/MIMX9574_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9574/MIMX9574_cm7_features.h index cc8ad955d..17e05c5c9 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9574/MIMX9574_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9574/MIMX9574_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9576/MIMX9576_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9576/MIMX9576_cm7_features.h index 9ad83b01f..93a276029 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9576/MIMX9576_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9576/MIMX9576_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9586/MIMX9586_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9586/MIMX9586_cm7_features.h index 0870ee886..782a70735 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9586/MIMX9586_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9586/MIMX9586_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9594/MIMX9594_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9594/MIMX9594_cm7_features.h index 094d45cca..41b3da28b 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9594/MIMX9594_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9594/MIMX9594_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9596/MIMX9596_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9596/MIMX9596_cm7_features.h index 7400d5caa..271d6bdb5 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9596/MIMX9596_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX9596/MIMX9596_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX95N4/MIMX95N4_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX95N4/MIMX95N4_cm7_features.h index 76877f968..496a48b1c 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX95N4/MIMX95N4_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX95N4/MIMX95N4_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX95N6/MIMX95N6_cm7_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX95N6/MIMX95N6_cm7_features.h index b5403a371..3dffde4cb 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX95N6/MIMX95N6_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/MIMX95N6/MIMX95N6_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-11-16 -** Build: b250513 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,13 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) + +/* DISPLAY_SEERIS module features */ + +/* @brief Display SEERIS MDR version */ +#define FSL_FEATURE_DISPLAY_SEERIS_MDR5 (1) /* EDMA module features */ @@ -392,8 +399,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -422,6 +427,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -438,7 +445,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -455,6 +462,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* RGPIO module features */ @@ -479,14 +512,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -590,8 +623,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -634,6 +665,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* XCACHE module features */ @@ -686,13 +721,25 @@ /* @brief Max number of ENETC SI Tx/Rx BD rings. */ #define FSL_FEATURE_NETC_SI_RING_NUM_MAX (24) /* @brief NETC MSI-X table base address. */ -#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x60BC0000) +#define FSL_FEATURE_NETC_MSIX_TABLE_BASE (0x4CD00000) /* @brief No switch support. */ #define FSL_FEATURE_NETC_HAS_NO_SWITCH (1) /* @brief No XGMII support. */ #define FSL_FEATURE_NETC_HAS_NO_XGMII (0) /* @brief NXP Switch Tag support. */ #define FSL_FEATURE_NETC_HAS_SWITCH_TAG (0) +/* @brief Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052167 (0) +/* @brief The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is not as document. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052206 (0) +/* @brief The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052129 (0) +/* @brief PTCaTSDR registers are implemented in the wrong order within the memory map. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_052031 (0) +/* @brief The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051994 (0) +/* @brief MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. */ +#define FSL_FEATURE_NETC_HAS_ERRATA_051936 (0) /* @brief NXP Switch port seamless redundacy support. */ #define FSL_FEATURE_NETC_HAS_PORT_PSRCR (0) /* @brief NXP Switch port group support. */ @@ -727,8 +774,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ (((x) == SAI1) ? (32) : \ @@ -767,14 +812,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ @@ -847,6 +896,33 @@ /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + /* WDOG module features */ /* @brief Watchdog is available. */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/periph/PERI_USB3_CORE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/periph/PERI_USB3_CORE.h index 51033e962..febd0f4a0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/periph/PERI_USB3_CORE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/periph/PERI_USB3_CORE.h @@ -421,7 +421,6 @@ typedef struct { __I uint32_t HCCPARAMS2; /**< Host Controller Capability Parameters 2, offset: 0x1C */ __IO uint32_t USBCMD; /**< USB Command, offset: 0x20 */ __IO uint32_t USBSTS; /**< USB Status, offset: 0x24 */ -#undef PAGESIZE __I uint32_t PAGESIZE; /**< Page Size, offset: 0x28 */ uint8_t RESERVED_0[8]; __IO uint32_t DNCTRL; /**< Device Notification, offset: 0x34 */ From d680ad19b39de31540bd44ad4c34ba0a705af321 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:11:07 +0800 Subject: [PATCH 05/21] hal_nxp: mcux-sdk-ng: Update device/kinetis to sdk 25.09.00 Signed-off-by: Zhaoxiang Jin --- .../K/MK02F12810/MK02F12810_features.h | 2 +- .../K/MK22F12810/MK22F12810_features.h | 36 +++-- .../K/MK22F25612/MK22F25612_features.h | 36 +++-- .../K/MK22F51212/MK22F51212_features.h | 36 +++-- .../Kinetis/K/MK22F51212/drivers/fsl_clock.c | 137 +++++++++-------- .../Kinetis/K/MK22F51212/drivers/fsl_clock.h | 10 +- .../Kinetis/K/MK22F51212/system_MK22F51212.c | 31 ++-- .../K32L/K32L2A31A/K32L2A31A_features.h | 22 ++- .../K32L/K32L2A41A/K32L2A41A_features.h | 22 ++- .../K32L/K32L2B11A/K32L2B11A_features.h | 26 ++-- .../K32L/K32L2B21A/K32L2B21A_features.h | 26 ++-- .../K32L/K32L2B31A/K32L2B31A_features.h | 26 ++-- .../K32L/K32L3A60/K32L3A60_cm0plus_features.h | 36 ++--- .../K32L/K32L3A60/K32L3A60_cm4_features.h | 36 ++--- .../Kinetis/K32L/K32L3A60/drivers/fsl_clock.c | 3 +- .../Kinetis/KE/MKE02Z4/MKE02Z4_features.h | 2 +- .../Kinetis/KE/MKE02Z4/drivers/fsl_clock.c | 50 +++--- .../Kinetis/KE/MKE02Z4/drivers/fsl_clock.h | 10 +- .../Kinetis/KE/MKE02Z4/system_MKE02Z4.c | 11 +- .../Kinetis/KE/MKE12Z7/MKE12Z7_features.h | 10 +- .../Kinetis/KE/MKE12Z9/MKE12Z9_features.h | 20 ++- .../Kinetis/KE/MKE13Z7/MKE13Z7_features.h | 10 +- .../Kinetis/KE/MKE13Z9/MKE13Z9_features.h | 20 ++- .../Kinetis/KE/MKE14Z4/MKE14Z4_features.h | 16 +- .../Kinetis/KE/MKE14Z7/MKE14Z7_features.h | 16 +- .../Kinetis/KE/MKE15Z4/MKE15Z4_features.h | 16 +- .../Kinetis/KE/MKE15Z7/MKE15Z7_features.h | 16 +- .../Kinetis/KE/MKE15Z7/drivers/fsl_clock.c | 2 +- .../Kinetis/KE/MKE16Z4/MKE16Z4_features.h | 16 +- .../Kinetis/KE/MKE17Z7/MKE17Z7_features.h | 10 +- .../Kinetis/KE/MKE17Z7/drivers/fsl_clock.c | 1 + .../Kinetis/KE/MKE17Z9/MKE17Z9_features.h | 20 ++- .../Kinetis/KM/MKM14ZA5/MKM14ZA5_features.h | 6 +- .../Kinetis/KM/MKM33ZA5/MKM33ZA5_features.h | 6 +- .../Kinetis/KM/MKM34Z7/MKM34Z7_features.h | 14 +- .../Kinetis/KM/MKM34ZA5/MKM34ZA5_features.h | 6 +- .../Kinetis/KM/MKM35Z7/MKM35Z7_features.h | 8 +- .../Kinetis/KM/MKM35Z7/drivers/fsl_clock.c | 144 +++++++++--------- .../Kinetis/KM/MKM35Z7/drivers/fsl_clock.h | 10 +- .../Kinetis/KM/MKM35Z7/system_MKM35Z7.c | 35 +++-- 40 files changed, 593 insertions(+), 367 deletions(-) diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/MK02F12810_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/MK02F12810_features.h index 4e45d4e27..d5c3f5977 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/MK02F12810_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/MK02F12810_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.9, 2015-06-08 -** Build: b250324 +** Build: b250603 ** ** Abstract: ** Chip specific module features. diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F12810/MK22F12810_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F12810/MK22F12810_features.h index 7b3ed63f4..24c844f50 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F12810/MK22F12810_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F12810/MK22F12810_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.12, 2015-06-08 -** Build: b250506 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -513,8 +513,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -533,18 +531,28 @@ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) -/* @brief Ihe interrupt source number */ +/* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (0) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -1033,8 +1041,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (1) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -1057,8 +1063,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -1101,6 +1105,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -1222,6 +1232,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ @@ -1362,6 +1374,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F25612/MK22F25612_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F25612/MK22F25612_features.h index 4d0653bd1..79de5a905 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F25612/MK22F25612_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F25612/MK22F25612_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.14, 2015-06-08 -** Build: b250506 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -715,8 +715,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -735,18 +733,28 @@ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) -/* @brief Ihe interrupt source number */ +/* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (0) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -1235,8 +1243,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (1) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -1259,8 +1265,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -1303,6 +1307,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -1424,6 +1434,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ @@ -1564,6 +1576,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/MK22F51212_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/MK22F51212_features.h index 9f1a5e239..c5b06294c 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/MK22F51212_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/MK22F51212_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.15, 2016-03-21 -** Build: b250506 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -613,8 +613,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -633,18 +631,28 @@ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) -/* @brief Ihe interrupt source number */ +/* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (0) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -1366,8 +1374,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (1) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -1390,8 +1396,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -1434,6 +1438,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -1555,6 +1565,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ @@ -1695,6 +1707,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/drivers/fsl_clock.c index 0e77fef47..2f5cca94b 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/drivers/fsl_clock.c @@ -193,8 +193,8 @@ static void CLOCK_FllStableDelay(void) Should wait at least 1ms. Because in these modes, the core clock is 100MHz at most, so this function could obtain the 1ms delay. */ - volatile uint32_t i = 30000U; - while (0U != (i--)) + volatile uint32_t i = 30001U; + while (0U != (--i)) { __NOP(); } @@ -796,6 +796,7 @@ uint32_t CLOCK_GetPll0Freq(void) mcgpll0prdiv = ((uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL); mcgpll0clk /= (uint32_t)mcgpll0prdiv; mcgpll0vdiv = ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); + assert((UINT32_MAX / mcgpll0clk) >= mcgpll0vdiv); mcgpll0clk *= (uint32_t)mcgpll0vdiv; freq = mcgpll0clk; @@ -839,12 +840,12 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) needDelay = false; } - MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); + MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_OSCSEL_MASK) & 0xFFU) | MCG_C7_OSCSEL(oscsel); if (needDelay) { /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */ - i = 1500U; - while (0U != (i--)) + i = 1501U; + while (0U != (--i)) { __NOP(); } @@ -894,19 +895,19 @@ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) && (kMCG_IrcFast == curIrcs)) { - MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); + MCG->C2 = (uint8_t)(((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))) & 0xFFU); while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) { } } /* Update FCRDIV. */ MCG->SC = - (uint8_t)(MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv); + (uint8_t)((MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) & 0xFFU) | MCG_SC_FCRDIV(fcrdiv); } /* Set internal reference clock selection. */ - MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode); + MCG->C2 = (uint8_t)(((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))) & 0xFFU); + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode) & 0xFFU); /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) @@ -972,13 +973,22 @@ uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, prdiv_min = (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX); + assert(prdiv_min >= 1U); + /* PRDIV traversal. */ for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) { /* Reference frequency after PRDIV. */ ref_div = refFreq / prdiv_cur; - vdiv_cur = (uint8_t)(desireFreq / ref_div); + if ((desireFreq / ref_div) > 0xFFU) + { + continue; + } + else + { + vdiv_cur = (uint8_t)((desireFreq / ref_div) & 0xFFU); + } if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) || (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) @@ -998,6 +1008,7 @@ uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, return ret_freq; } /* New PRDIV/VDIV is closer. */ + assert(desireFreq > ret_freq); if (diff > desireFreq - ret_freq) { diff = desireFreq - ret_freq; @@ -1054,7 +1065,7 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config) mcg_c5 |= MCG_C5_PRDIV0(config->prdiv); MCG->C5 = mcg_c5; /* Disable the PLL first. */ - MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); + MCG->C6 = (uint8_t)(((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)) & 0xFFU); /* Set enable mode. */ MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); @@ -1075,17 +1086,17 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config) void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) { /* Clear the previous flag, MCG_SC[LOCS0]. */ - MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK; + MCG->SC &= (uint8_t)((~MCG_SC_ATMF_MASK) & 0xFFU); if (kMCG_MonitorNone == mode) { - MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK; + MCG->C6 &= (uint8_t)((~MCG_C6_CME0_MASK) & 0xFFU); } else { if (kMCG_MonitorInt == mode) { - MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; + MCG->C2 &= (uint8_t)((~MCG_C2_LOCRE0_MASK) & 0xFFU); } else { @@ -1106,7 +1117,7 @@ void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) { uint8_t mcg_c8 = MCG->C8; - mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK); + mcg_c8 &= (uint8_t)(~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK) & 0xFFU); if (kMCG_MonitorNone != mode) { @@ -1135,17 +1146,17 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) if (kMCG_MonitorNone == mode) { - MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK); + MCG->C6 &= (uint8_t)((~MCG_C6_LOLIE0_MASK) & 0xFFU); } else { mcg_c8 = MCG->C8; - mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK); + mcg_c8 &= (uint8_t)((~MCG_C8_LOCS1_MASK) & 0xFFU); if (kMCG_MonitorInt == mode) { - mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK); + mcg_c8 &= (uint8_t)((~MCG_C8_LOLRE_MASK) & 0xFFU); } else { @@ -1232,7 +1243,7 @@ void CLOCK_ClearStatusFlags(uint32_t mask) if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) { - MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK); + MCG->SC &= (uint8_t)((~MCG_SC_ATMF_MASK) & 0xFFU); } if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) { @@ -1258,7 +1269,7 @@ void CLOCK_InitOsc0(osc_config_t const *config) OSC_SetCapLoad(OSC0, config->capLoad); - MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); + MCG->C2 = (uint8_t)(((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode) & 0xFFU); OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) @@ -1278,7 +1289,7 @@ void CLOCK_InitOsc0(osc_config_t const *config) void CLOCK_DeinitOsc0(void) { OSC0->CR = 0U; - MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; + MCG->C2 &= (uint8_t)((~OSC_MODE_MASK) & 0xFFU); } /*! @@ -1551,9 +1562,9 @@ status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela } /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | - (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ - | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ + MCG->C1 = (uint8_t)((((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | + (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal))) & 0xFFU); /* IREFS = 1 */ /* Wait and check status. */ while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) @@ -1567,8 +1578,8 @@ status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela } /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */ - MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + MCG->C4 = (uint8_t)(((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | + (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))) & 0xFFU); /* Check MCG_S[CLKST] */ while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) @@ -1627,10 +1638,10 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ - | MCG_C1_FRDIV(frdiv) /* FRDIV */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))) & 0xFFU); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) @@ -1655,8 +1666,8 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set DRS and DMX32. */ - mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + mcg_c4 = (uint8_t)(((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | + (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))) & 0xFFU); MCG->C4 = mcg_c4; /* Wait for DRST_DRS update. */ @@ -1712,7 +1723,7 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela mcg_c4 = MCG->C4; - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */ + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); /* Disable lowpower. */ /* Errata: ERR007993 @@ -1728,9 +1739,9 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela } /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ - | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal))) & 0xFFU); /* IREFS = 1 */ /* Wait and check status. */ while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) @@ -1747,8 +1758,8 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela { } - MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + MCG->C4 = (uint8_t)(((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | + (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))) & 0xFFU); /* Wait for FLL stable time. */ if (NULL != fllStableDelay) @@ -1789,13 +1800,13 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void #endif /* Change to FLL mode. */ - MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK; + MCG->C6 &= (uint8_t)((~MCG_C6_PLLS_MASK) & 0xFFU); while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } /* Set LP bit to enable the FLL */ - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); mcg_c4 = MCG->C4; @@ -1813,10 +1824,10 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ - | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))) & 0xFFU); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) @@ -1841,8 +1852,8 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set DRST_DRS and DMX32. */ - mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + mcg_c4 = (uint8_t)(((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | + (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))) & 0xFFU); MCG->C4 = mcg_c4; /* Wait for clock status bits to show clock source is ext ref clk */ @@ -1934,10 +1945,10 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co This function is designed to change MCG to PBE mode from PEE/BLPE/FBE, but with this workflow, the source mode could be all modes except PEI/PBI. */ - MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); /* Disable lowpower. */ + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); /* Disable lowpower. */ /* Change to use external clock first. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)) & 0xFFU); /* Wait for CLKST clock status bits to show clock source is ext ref clk */ while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != @@ -1946,7 +1957,7 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co } /* Disable PLL first, then configure PLL. */ - MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK); + MCG->C6 &= (uint8_t)((~MCG_C6_PLLS_MASK) & 0xFFU); while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } @@ -1990,7 +2001,7 @@ status_t CLOCK_SetPeeMode(void) #endif /* Change to use PLL/FLL output clock first. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)) & 0xFFU); /* Wait for clock status bits to update */ while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) @@ -2026,15 +2037,15 @@ status_t CLOCK_ExternalModeToFbeModeQuick(void) #endif /* MCG_CONFIG_CHECK_PARAM */ /* Disable low power */ - MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)) & 0xFFU); while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) { } /* Disable PLL. */ - MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK; + MCG->C6 &= (uint8_t)((~MCG_C6_PLLS_MASK) & 0xFFU); while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } @@ -2068,9 +2079,9 @@ status_t CLOCK_InternalModeToFbiModeQuick(void) #endif /* Disable low power */ - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)) & 0xFFU); while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) { } @@ -2140,7 +2151,7 @@ status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEn (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv); /* If reset mode is not BLPI, first enter FBI mode. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)) & 0xFFU); while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) { } @@ -2167,9 +2178,9 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) (void)CLOCK_SetExternalRefClkConfig(oscsel); /* Set to FBE mode. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))) & 0xFFU); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) @@ -2216,7 +2227,7 @@ status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mc (void)CLOCK_SetPbeMode(pllcs, config); /* Change to use PLL output clock. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)) & 0xFFU); while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) { } @@ -2291,7 +2302,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) { - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */ + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); /* Disable lowpower. */ { (void)CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); @@ -2342,7 +2353,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) } else { - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)) & 0xFFU); while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) { } @@ -2369,7 +2380,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) } else { - MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; + MCG->C5 &= (uint8_t)((~kMCG_PllEnableIndependent) & 0xFFU); } } diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/drivers/fsl_clock.h index 5ab47bd41..b73f735fe 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/drivers/fsl_clock.h @@ -921,7 +921,7 @@ static inline void CLOCK_SetLowPowerEnable(bool enable) } else { - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); } } @@ -966,7 +966,7 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); */ static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv) { - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)) & 0xFFU); } /*! @@ -990,7 +990,7 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config); */ static inline void CLOCK_DisablePll0(void) { - MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); + MCG->C5 &= (uint8_t)((~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)) & 0xFFU); } /*! @@ -1119,7 +1119,7 @@ static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const * { uint8_t reg = base->CR; - reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK)); + reg &= (uint8_t)((~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK)) & 0xFFU); reg |= config->enableMode; base->CR = reg; @@ -1147,7 +1147,7 @@ static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) { uint8_t reg = base->CR; - reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK)); + reg &= (uint8_t)((~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK)) & 0xFFU); reg |= capLoad; base->CR = reg; diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/system_MK22F51212.c b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/system_MK22F51212.c index 1bbcd9aa6..9e91cc2ed 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/system_MK22F51212.c +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K/MK22F51212/system_MK22F51212.c @@ -82,7 +82,7 @@ #include #include "fsl_device_registers.h" - +#define SAFE_MULTI(multi, max) ((multi) > (max) ? 0U : (multi)) /* ---------------------------------------------------------------------------- -- Core clock @@ -125,6 +125,7 @@ void SystemCoreClockUpdate (void) { uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ uint16_t Divider; uint8_t tmpC7 = 0; + uint32_t max; if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { /* Output of FLL or PLL is selected */ @@ -154,44 +155,45 @@ void SystemCoreClockUpdate (void) { Divider = 1280U; break; default: - Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + Divider = (uint16_t)((32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)) & 0xFFFFU); break; } } else { - Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + Divider = (uint16_t)((1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)) & 0xFFFFU); } MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ } else { MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ } /* Select correct multiplier to calculate the MCG output clock */ + max = UINT32_MAX / MCGOUTClock; switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { case 0x00U: - MCGOUTClock *= 640U; + MCGOUTClock *= SAFE_MULTI(640U, max); break; case 0x20U: - MCGOUTClock *= 1280U; + MCGOUTClock *= SAFE_MULTI(1280U, max); break; case 0x40U: - MCGOUTClock *= 1920U; + MCGOUTClock *= SAFE_MULTI(1920U, max); break; case 0x60U: - MCGOUTClock *= 2560U; + MCGOUTClock *= SAFE_MULTI(2560U, max); break; case 0x80U: - MCGOUTClock *= 732U; + MCGOUTClock *= SAFE_MULTI(732U, max); break; case 0xA0U: - MCGOUTClock *= 1464U; + MCGOUTClock *= SAFE_MULTI(1464U, max); break; case 0xC0U: - MCGOUTClock *= 2197U; + MCGOUTClock *= SAFE_MULTI(2197U, max); break; case 0xE0U: - MCGOUTClock *= 2929U; + MCGOUTClock *= SAFE_MULTI(2929U, max); break; default: - MCGOUTClock *= 640U; + MCGOUTClock *= SAFE_MULTI(640U, max); break; } } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ @@ -199,14 +201,15 @@ void SystemCoreClockUpdate (void) { Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); - MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + max = UINT32_MAX / MCGOUTClock; + MCGOUTClock *= SAFE_MULTI(Divider, max); /* Calculate the MCG output clock */ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { /* Internal reference clock is selected */ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ } else { /* Fast internal reference clock selected */ - Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); + Divider = (uint16_t)((0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)) & 0xFFFFU); MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); } } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2A31A/K32L2A31A_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2A31A/K32L2A31A_features.h index f04fc3cb1..895db0b3b 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2A31A/K32L2A31A_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2A31A/K32L2A31A_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2019-10-30 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -990,8 +990,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -1034,6 +1032,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -1194,6 +1196,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -1456,13 +1464,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2A41A/K32L2A41A_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2A41A/K32L2A41A_features.h index 94d90b198..b7e3585ba 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2A41A/K32L2A41A_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2A41A/K32L2A41A_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2019-10-30 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -990,8 +990,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -1034,6 +1032,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -1194,6 +1196,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -1456,13 +1464,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B11A/K32L2B11A_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B11A/K32L2B11A_features.h index 2c571bd4f..6b277a884 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B11A/K32L2B11A_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B11A/K32L2B11A_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2019-07-30 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -719,8 +719,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -743,8 +741,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -787,6 +783,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -985,6 +987,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1166,13 +1174,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B21A/K32L2B21A_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B21A/K32L2B21A_features.h index f5c6439bb..72bcfd46c 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B21A/K32L2B21A_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B21A/K32L2B21A_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2019-07-30 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -719,8 +719,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -743,8 +741,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -787,6 +783,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -985,6 +987,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1166,13 +1174,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B31A/K32L2B31A_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B31A/K32L2B31A_features.h index 7e2513704..6fa26abb6 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B31A/K32L2B31A_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L2B31A/K32L2B31A_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2019-07-30 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -719,8 +719,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -743,8 +741,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -787,6 +783,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -985,6 +987,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1166,13 +1174,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/K32L3A60_cm0plus_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/K32L3A60_cm0plus_features.h index e0416cbc1..e9542d05e 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/K32L3A60_cm0plus_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/K32L3A60_cm0plus_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2019-04-22 -** Build: b250512 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -185,8 +185,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -215,6 +213,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLASH module features */ @@ -454,8 +454,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -484,14 +482,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* INTMUX module features */ @@ -918,8 +920,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -962,6 +962,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MCM module features */ @@ -1092,6 +1096,10 @@ #define FSL_FEATURE_RTC_HAS_PCR (1) /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -1567,11 +1575,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (1) : \ - (((x) == TPM3) ? (0) : (-1))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -1587,11 +1591,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (1) : \ - (((x) == TPM3) ? (0) : (-1))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/K32L3A60_cm4_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/K32L3A60_cm4_features.h index 68e7663ec..d31074992 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/K32L3A60_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/K32L3A60_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2019-04-22 -** Build: b250512 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -177,8 +177,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -207,6 +205,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLASH module features */ @@ -446,8 +446,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -476,14 +474,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -897,8 +899,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -941,6 +941,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MCM module features */ @@ -1071,6 +1075,10 @@ #define FSL_FEATURE_RTC_HAS_PCR (1) /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -1546,11 +1554,7 @@ /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Whether TRIG register has effect. */ -#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (1) : \ - (((x) == TPM3) ? (0) : (-1))))) +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) /* @brief Has global time base enable. */ #define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) /* @brief Has global time base sync. */ @@ -1566,11 +1570,7 @@ /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Whether POL register has effect. */ -#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ - (((x) == TPM0) ? (1) : \ - (((x) == TPM1) ? (0) : \ - (((x) == TPM2) ? (1) : \ - (((x) == TPM3) ? (0) : (-1))))) +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/drivers/fsl_clock.c index c1f95c029..d58b14c96 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/Kinetis/K32L/K32L3A60/drivers/fsl_clock.c @@ -270,6 +270,7 @@ uint32_t CLOCK_GetIpFreq(clock_ip_name_t name) if (0U != (reg & (PCC_CLKCFG_PCD_MASK | PCC_CLKCFG_FRAC_MASK))) { + assert((UINT32_MAX / freq) >= (PCC_FRAC_VAL(reg) + 1U)); return freq * (PCC_FRAC_VAL(reg) + 1U) / (PCC_PCD_VAL(reg) + 1U); } else @@ -297,7 +298,7 @@ bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ USBVREG->CTRL |= USBVREG_CTRL_EN_MASK; - USB0->CONTROL &= (uint8_t)(~USB_CONTROL_DPPULLUPNONOTG_MASK); + USB0->CONTROL &= (uint8_t)((~USB_CONTROL_DPPULLUPNONOTG_MASK) & 0xFFU); if (kCLOCK_UsbSrcIrc48M == src) { diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/MKE02Z4_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/MKE02Z4_features.h index d6a3b4d97..9b94d0502 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/MKE02Z4_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/MKE02Z4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2017-05-19 -** Build: b250324 +** Build: b250603 ** ** Abstract: ** Chip specific module features. diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/drivers/fsl_clock.c index 61f672379..f07c5170d 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/drivers/fsl_clock.c @@ -436,7 +436,7 @@ void CLOCK_InitOsc0(osc_config_t const *config) { uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); - OSC0->CR = ((OSC0->CR & (uint8_t)(~OSC_MODE_MASK)) | (uint8_t)(OSC_CR_RANGE(range)) | ((uint8_t)config->workMode) | + OSC0->CR = ((OSC0->CR & (uint8_t)((~OSC_MODE_MASK) & 0xFFU)) | (uint8_t)(OSC_CR_RANGE(range)) | ((uint8_t)config->workMode) | ((uint8_t)config->enableMode)); if (((uint8_t)kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_OSCEN_MASK) != 0U)) @@ -560,12 +560,12 @@ status_t CLOCK_SetFeiMode(uint8_t bDiv) #endif /* Set IREFS. */ - ICS->C1 = (uint8_t)((ICS->C1 & ~(ICS_C1_IREFS_MASK)) | ICS_C1_IREFS(kICS_FllSrcInternal)); /* IREFS = 1 */ + ICS->C1 = (uint8_t)(((ICS->C1 & ~(ICS_C1_IREFS_MASK)) | ICS_C1_IREFS(kICS_FllSrcInternal)) & 0xFFU); /* IREFS = 1 */ /* Set CLKS */ - ICS->C1 = (uint8_t)((ICS->C1 & (~ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(kICS_ClkOutSrcFll)); /* CLKS = 0 */ + ICS->C1 = (uint8_t)(((ICS->C1 & (~ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(kICS_ClkOutSrcFll)) & 0xFFU); /* CLKS = 0 */ /* set bus clock divider */ - ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); + ICS->C2 = (uint8_t)(((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)) & 0xFFU); /* Wait and check status. */ while ((uint8_t)kICS_FllSrcInternal != ICS_S_IREFST_VAL) @@ -610,12 +610,12 @@ status_t CLOCK_SetFeeMode(uint8_t bDiv, uint8_t rDiv) #endif /* Set CLKS, rDiv and IREFS. */ - ICS->C1 = (uint8_t)((ICS->C1 & ~(ICS_C1_CLKS_MASK | ICS_C1_RDIV_MASK | ICS_C1_IREFS_MASK)) | - (ICS_C1_CLKS(kICS_ClkOutSrcFll) /* CLKS = 0 */ - | ICS_C1_RDIV(rDiv) /* FRDIV */ - | ICS_C1_IREFS(kICS_FllSrcExternal))); /* IREFS = 0 */ + ICS->C1 = (uint8_t)(((ICS->C1 & ~(ICS_C1_CLKS_MASK | ICS_C1_RDIV_MASK | ICS_C1_IREFS_MASK)) | + (ICS_C1_CLKS(kICS_ClkOutSrcFll) /* CLKS = 0 */ + | ICS_C1_RDIV(rDiv) /* FRDIV */ + | ICS_C1_IREFS(kICS_FllSrcExternal))) & 0xFFU); /* IREFS = 0 */ /* set bus clock divider */ - ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); + ICS->C2 = (uint8_t)(((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)) & 0xFFU); /* If use external crystal as clock source, wait for it stable. */ { @@ -672,11 +672,11 @@ status_t CLOCK_SetFbiMode(uint8_t bDiv) #endif /* set bus clock divider and disable low power */ - ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); + ICS->C2 = (uint8_t)(((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)) & 0xFFU); /* Set CLKS and IREFS. */ - ICS->C1 = (uint8_t)((ICS->C1 & ~(ICS_C1_CLKS_MASK | ICS_C1_IREFS_MASK)) | + ICS->C1 = (uint8_t)(((ICS->C1 & ~(ICS_C1_CLKS_MASK | ICS_C1_IREFS_MASK)) | (ICS_C1_CLKS(kICS_ClkOutSrcInternal) /* CLKS = 1 */ - | ICS_C1_IREFS(kICS_FllSrcInternal))); /* IREFS = 1 */ + | ICS_C1_IREFS(kICS_FllSrcInternal))) & 0xFFU); /* IREFS = 1 */ /* Wait and check status. */ while ((uint8_t)kICS_FllSrcInternal != ICS_S_IREFST_VAL) @@ -717,13 +717,13 @@ status_t CLOCK_SetFbeMode(uint8_t bDiv, uint8_t rDiv) #endif /* set bus clock divider and disable low power */ - ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); + ICS->C2 = (uint8_t)(((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)) & 0xFFU); /* Set CLKS and IREFS. */ - ICS->C1 = (uint8_t)((ICS->C1 & ~(ICS_C1_CLKS_MASK | ICS_C1_RDIV_MASK | ICS_C1_IREFS_MASK)) | - (ICS_C1_CLKS(kICS_ClkOutSrcExternal) /* CLKS = 2 */ - | ICS_C1_RDIV(rDiv) /* FRDIV = frDiv */ - | ICS_C1_IREFS(kICS_FllSrcExternal))); /* IREFS = 0 */ + ICS->C1 = (uint8_t)(((ICS->C1 & ~(ICS_C1_CLKS_MASK | ICS_C1_RDIV_MASK | ICS_C1_IREFS_MASK)) | + (ICS_C1_CLKS(kICS_ClkOutSrcExternal) /* CLKS = 2 */ + | ICS_C1_RDIV(rDiv) /* FRDIV = frDiv */ + | ICS_C1_IREFS(kICS_FllSrcExternal))) & 0xFFU); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ { @@ -771,7 +771,7 @@ status_t CLOCK_SetBilpMode(uint8_t bDiv) #endif /* ICS_CONFIG_CHECK_PARAM */ /* set bus clock divider and enable low power */ - ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); + ICS->C2 = (uint8_t)(((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK) & 0xFFU); return kStatus_Success; } @@ -796,7 +796,7 @@ status_t CLOCK_SetBelpMode(uint8_t bDiv) #endif /* set bus clock divider and enable low power */ - ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); + ICS->C2 = (uint8_t)(((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK) & 0xFFU); return kStatus_Success; } @@ -847,13 +847,13 @@ status_t CLOCK_BootToFeeMode(uint8_t bDiv, uint8_t rDiv) status_t CLOCK_BootToBilpMode(uint8_t bDiv) { /* If reset mode is not BILP, first enter FBI mode. */ - ICS->C1 = (uint8_t)((ICS->C1 & ~ICS_C1_CLKS_MASK) | ICS_C1_CLKS(kICS_ClkOutSrcInternal)); + ICS->C1 = (uint8_t)(((ICS->C1 & ~ICS_C1_CLKS_MASK) | ICS_C1_CLKS(kICS_ClkOutSrcInternal)) & 0xFFU); while (ICS_S_CLKST_VAL != (uint8_t)kICS_ClkOutStatInt) { } /* set bus clock divider and enable low power */ - ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); + ICS->C2 = (uint8_t)(((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK) & 0xFFU); return kStatus_Success; } @@ -871,9 +871,9 @@ status_t CLOCK_BootToBilpMode(uint8_t bDiv) status_t CLOCK_BootToBelpMode(uint8_t bDiv) { /* Set to FBE mode. */ - ICS->C1 = (uint8_t)((ICS->C1 & ~(ICS_C1_CLKS_MASK | ICS_C1_IREFS_MASK)) | - (ICS_C1_CLKS(kICS_ClkOutSrcExternal) /* CLKS = 2 */ - | ICS_C1_IREFS(kICS_FllSrcExternal))); /* IREFS = 0 */ + ICS->C1 = (uint8_t)(((ICS->C1 & ~(ICS_C1_CLKS_MASK | ICS_C1_IREFS_MASK)) | + (ICS_C1_CLKS(kICS_ClkOutSrcExternal) /* CLKS = 2 */ + | ICS_C1_IREFS(kICS_FllSrcExternal))) & 0xFFU); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ { @@ -892,7 +892,7 @@ status_t CLOCK_BootToBelpMode(uint8_t bDiv) } /* set bus clock divider and enable low power */ - ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); + ICS->C2 = (uint8_t)(((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK) & 0xFFU); return kStatus_Success; } diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/drivers/fsl_clock.h index 3ac9f45db..76765ec10 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/drivers/fsl_clock.h @@ -522,7 +522,7 @@ static inline void CLOCK_SetLowPowerEnable(bool enable) } else { - ICS->C2 &= (uint8_t)(~ICS_C2_LP_MASK); + ICS->C2 &= (uint8_t)((~ICS_C2_LP_MASK) & 0xFFU); } } @@ -540,7 +540,7 @@ static inline void CLOCK_SetLowPowerEnable(bool enable) static inline void CLOCK_SetInternalRefClkConfig(uint8_t enableMode) { /* Set internal reference clock selection. */ - ICS->C1 = (uint8_t)((ICS->C1 & ~(ICS_C1_IRCLKEN_MASK | ICS_C1_IREFSTEN_MASK)) | (uint8_t)enableMode); + ICS->C1 = (uint8_t)(((ICS->C1 & ~(ICS_C1_IRCLKEN_MASK | ICS_C1_IREFSTEN_MASK)) | (uint8_t)enableMode) & 0xFFU); } /*! @@ -553,7 +553,7 @@ static inline void CLOCK_SetInternalRefClkConfig(uint8_t enableMode) */ static inline void CLOCK_SetFllExtRefDiv(uint8_t rdiv) { - ICS->C1 = (uint8_t)((ICS->C1 & ~ICS_C1_RDIV_MASK) | ICS_C1_RDIV(rdiv)); + ICS->C1 = (uint8_t)(((ICS->C1 & ~ICS_C1_RDIV_MASK) | ICS_C1_RDIV(rdiv)) & 0xFFU); } /*@}*/ @@ -576,7 +576,7 @@ static inline void CLOCK_SetOsc0MonitorMode(bool enable) } else { - ICS->C4 &= (uint8_t)(~ICS_C4_CME_MASK); + ICS->C4 &= (uint8_t)((~ICS_C4_CME_MASK) & 0xFFU); } } @@ -627,7 +627,7 @@ static inline void CLOCK_SetXtal0Freq(uint32_t freq) */ static inline void CLOCK_SetOsc0Enable(uint8_t enable) { - OSC0->CR |= (uint8_t)((OSC0->CR & (~(OSC_CR_OSCSTEN_MASK | OSC_CR_OSCEN_MASK))) | enable); + OSC0->CR |= (uint8_t)(((OSC0->CR & (~(OSC_CR_OSCSTEN_MASK | OSC_CR_OSCEN_MASK))) | enable) & 0xFFU); } /* @} */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/system_MKE02Z4.c b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/system_MKE02Z4.c index 06bf474d9..b38eccfb5 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/system_MKE02Z4.c +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE02Z4/system_MKE02Z4.c @@ -95,7 +95,7 @@ void SystemCoreClockUpdate (void) { uint16_t Divider; uint16_t Temp; - Divider = (uint16_t)(0x01U) << (((uint16_t)ICS->C2 & ICS_C2_BDIV_MASK) >> ICS_C2_BDIV_SHIFT); + Divider = (uint16_t)(((0x01U) << (((uint16_t)(ICS->C2) & ICS_C2_BDIV_MASK) >> ICS_C2_BDIV_SHIFT)) & 0xFFFFU); switch ((ICS->C1 & ICS_C1_CLKS_MASK) >> ICS_C1_CLKS_SHIFT) { case 0x0: @@ -109,7 +109,14 @@ void SystemCoreClockUpdate (void) { /* Reference Divider */ Temp = ((uint16_t)ICS->C1 & ICS_C1_RDIV_MASK) >> ICS_C1_RDIV_SHIFT; Temp = (Temp + 1U) * (((OSC->CR & OSC_CR_RANGE_MASK) != 0x0U) ? 32U : 1U); - ICSOUTClock = CPU_XTAL_CLK_HZ / Temp * 1024UL; + if (Temp >= 3U) + { + ICSOUTClock = CPU_XTAL_CLK_HZ / Temp * 1024UL; + } + else /* Wrong Temp value handling */ + { + ICSOUTClock = 0U; + } } break; diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE12Z7/MKE12Z7_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE12Z7/MKE12Z7_features.h index c253d8ea8..7fbf92dd3 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE12Z7/MKE12Z7_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE12Z7/MKE12Z7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2021-06-25 -** Build: b250428 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -732,8 +732,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -776,6 +774,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -1002,6 +1004,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE12Z9/MKE12Z9_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE12Z9/MKE12Z9_features.h index 01c59e955..29a0b2f6f 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE12Z9/MKE12Z9_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE12Z9/MKE12Z9_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2023-03-01 -** Build: b250514 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -182,8 +182,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -212,6 +210,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLASH module features */ @@ -479,6 +479,8 @@ (((x) == FTM0) ? (4) : \ (((x) == FTM1) ? (0) : \ (((x) == FTM2) ? (0) : (-1)))) +/* @brief Is affected by errata with ID 010856 (FTM: Safe state is not removed from channel outputs after fault condition ends if SWOCTRL is being used to control the pin). */ +#define FSL_FEATURE_FTM_HAS_ERRATA_010856 (0) /* GPIO module features */ @@ -567,8 +569,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -611,6 +611,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -760,6 +764,10 @@ #define FSL_FEATURE_RTC_HAS_PCR (0) /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -892,6 +900,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE13Z7/MKE13Z7_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE13Z7/MKE13Z7_features.h index b5acfaad3..8e6a4577c 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE13Z7/MKE13Z7_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE13Z7/MKE13Z7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2021-06-25 -** Build: b250428 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -734,8 +734,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -778,6 +776,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -1004,6 +1006,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE13Z9/MKE13Z9_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE13Z9/MKE13Z9_features.h index 6c6d4ce14..9dcd3b19e 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE13Z9/MKE13Z9_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE13Z9/MKE13Z9_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2023-03-01 -** Build: b250514 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -184,8 +184,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -214,6 +212,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLASH module features */ @@ -481,6 +481,8 @@ (((x) == FTM0) ? (4) : \ (((x) == FTM1) ? (0) : \ (((x) == FTM2) ? (0) : (-1)))) +/* @brief Is affected by errata with ID 010856 (FTM: Safe state is not removed from channel outputs after fault condition ends if SWOCTRL is being used to control the pin). */ +#define FSL_FEATURE_FTM_HAS_ERRATA_010856 (0) /* GPIO module features */ @@ -569,8 +571,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -613,6 +613,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -762,6 +766,10 @@ #define FSL_FEATURE_RTC_HAS_PCR (0) /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -894,6 +902,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE14Z4/MKE14Z4_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE14Z4/MKE14Z4_features.h index f233074d5..cc4136d6f 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE14Z4/MKE14Z4_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE14Z4/MKE14Z4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-05-09 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -660,8 +660,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -704,6 +702,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MMDVSQ module features */ @@ -870,6 +872,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -994,6 +1002,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE14Z7/MKE14Z7_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE14Z7/MKE14Z7_features.h index efc04461a..6d5eefba0 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE14Z7/MKE14Z7_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE14Z7/MKE14Z7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 6.0, 2016-09-20 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -736,8 +736,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -780,6 +778,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MMDVSQ module features */ @@ -950,6 +952,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -1074,6 +1082,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z4/MKE15Z4_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z4/MKE15Z4_features.h index 4f8e03a3b..7d3187681 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z4/MKE15Z4_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z4/MKE15Z4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-05-09 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -662,8 +662,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -706,6 +704,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MMDVSQ module features */ @@ -872,6 +874,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -996,6 +1004,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z7/MKE15Z7_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z7/MKE15Z7_features.h index e33eb06d5..2abedc0c9 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z7/MKE15Z7_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z7/MKE15Z7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 6.0, 2016-09-20 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -738,8 +738,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -782,6 +780,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MMDVSQ module features */ @@ -952,6 +954,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -1076,6 +1084,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z7/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z7/drivers/fsl_clock.c index d7a5a3ded..ac7c821a0 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z7/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE15Z7/drivers/fsl_clock.c @@ -251,7 +251,7 @@ void OSC32_Init(OSC32_Type *base, osc32_mode_t mode) /* Set work mode. */ base->CR = (uint8_t)mode; - if (((uint8_t)mode & OSC32_CR_ROSCEREFS_MASK) != 0U) + if (((uint8_t)((uint32_t)mode & 0xFFU) & OSC32_CR_ROSCEREFS_MASK) != 0U) { /* If use crystal mode, wait for stable. */ while (0U == (base->CR & OSC32_CR_ROSCSTB_MASK)) diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE16Z4/MKE16Z4_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE16Z4/MKE16Z4_features.h index 5e75e140f..483182ab7 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE16Z4/MKE16Z4_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE16Z4/MKE16Z4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-05-09 -** Build: b250428 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -664,8 +664,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -708,6 +706,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MMDVSQ module features */ @@ -874,6 +876,12 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -998,6 +1006,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z7/MKE17Z7_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z7/MKE17Z7_features.h index 0bd2147d1..332cf1c70 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z7/MKE17Z7_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z7/MKE17Z7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2021-06-25 -** Build: b250428 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -734,8 +734,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -778,6 +776,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -1004,6 +1006,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z7/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z7/drivers/fsl_clock.c index f4416073b..8a84ad4ea 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z7/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z7/drivers/fsl_clock.c @@ -871,6 +871,7 @@ uint32_t CLOCK_GetLpFllFreq(void) if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ { + assert(SCG_LPFLLCFG_FSEL_VAL < ARRAY_SIZE(lpfllFreq)); freq = lpfllFreq[SCG_LPFLLCFG_FSEL_VAL]; } else diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z9/MKE17Z9_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z9/MKE17Z9_features.h index 1611954df..c165014ba 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z9/MKE17Z9_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KE/MKE17Z9/MKE17Z9_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2023-03-01 -** Build: b250514 +** Build: b250811 ** ** Abstract: ** Chip specific module features. @@ -184,8 +184,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -214,6 +212,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLASH module features */ @@ -481,6 +481,8 @@ (((x) == FTM0) ? (4) : \ (((x) == FTM1) ? (0) : \ (((x) == FTM2) ? (0) : (-1)))) +/* @brief Is affected by errata with ID 010856 (FTM: Safe state is not removed from channel outputs after fault condition ends if SWOCTRL is being used to control the pin). */ +#define FSL_FEATURE_FTM_HAS_ERRATA_010856 (0) /* GPIO module features */ @@ -569,8 +571,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -613,6 +613,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -762,6 +766,10 @@ #define FSL_FEATURE_RTC_HAS_PCR (0) /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output (bitfield CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ @@ -894,6 +902,8 @@ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) +/* @brief Is affected by errata with ID 011063 (SMC: An asynchronous wakeup event during VLPS mode entry may result in possible system hang scenario). */ +#define FSL_FEATURE_SMC_HAS_ERRATA_011063 (0) /* SysTick module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM14ZA5/MKM14ZA5_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM14ZA5/MKM14ZA5_features.h index 21c66e45a..00c8d552e 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM14ZA5/MKM14ZA5_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM14ZA5/MKM14ZA5_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.3, 2015-05-25 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -953,6 +953,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM33ZA5/MKM33ZA5_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM33ZA5/MKM33ZA5_features.h index 6b4c32a58..1ffae5cd1 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM33ZA5/MKM33ZA5_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM33ZA5/MKM33ZA5_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2015-05-25 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -1209,6 +1209,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM34Z7/MKM34Z7_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM34Z7/MKM34Z7_features.h index 63670843a..01ac9b394 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM34Z7/MKM34Z7_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM34Z7/MKM34Z7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.4, 2015-05-25 -** Build: b250428 +** Build: b250731 ** ** Abstract: ** Chip specific module features. @@ -943,8 +943,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (1) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -967,8 +965,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -1011,6 +1007,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -1132,6 +1134,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM34ZA5/MKM34ZA5_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM34ZA5/MKM34ZA5_features.h index 9d6f7cfd7..3a82124cf 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM34ZA5/MKM34ZA5_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM34ZA5/MKM34ZA5_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.3, 2015-05-25 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -781,6 +781,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/MKM35Z7_features.h b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/MKM35Z7_features.h index aec5f72e9..76161a4ec 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/MKM35Z7_features.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/MKM35Z7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2019-08-01 -** Build: b250428 +** Build: b250723 ** ** Abstract: ** Chip specific module features. @@ -1154,8 +1154,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -1198,6 +1196,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/drivers/fsl_clock.c index ddf140d92..c62ceecd3 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/drivers/fsl_clock.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 - 2020,2022-2023 NXP + * Copyright 2016 - 2020, 2022-2023, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -672,6 +672,7 @@ uint32_t CLOCK_GetFllFreq(void) { drs = MCG_C4_DRST_DRS_VAL; dmx32 = MCG_C4_DMX32_VAL; + assert((UINT32_MAX / freq) >= fllFactorTable[drs][dmx32]); ret = freq * fllFactorTable[drs][dmx32]; } } @@ -799,7 +800,7 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) needDelay = false; } - MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); + MCG->C7 = (uint8_t)(((MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel)) & 0xFFU); if (needDelay) { /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */ @@ -854,19 +855,19 @@ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) && (kMCG_IrcFast == curIrcs)) { - MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); + MCG->C2 = (uint8_t)(((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))) & 0xFFU); while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) { } } /* Update FCRDIV. */ MCG->SC = - (uint8_t)(MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv); + (uint8_t)((MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) & 0xFFU) | MCG_SC_FCRDIV(fcrdiv); } /* Set internal reference clock selection. */ - MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode); + MCG->C2 = (uint8_t)(((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))) & 0xFFU); + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode) & 0xFFU); /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) @@ -898,7 +899,7 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config) MCG->C5 = mcg_c5; /* Disable the PLL first. */ - MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); + MCG->C7 = (uint8_t)(((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)) & 0xFFU); /* Set enable mode. */ MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); @@ -919,17 +920,17 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config) void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) { /* Clear the previous flag, MCG_SC[LOCS0]. */ - MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK; + MCG->SC &= (uint8_t)((~MCG_SC_ATMF_MASK) & 0xFFU); if (kMCG_MonitorNone == mode) { - MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK; + MCG->C6 &= (uint8_t)((~MCG_C6_CME0_MASK) & 0xFFU); } else { if (kMCG_MonitorInt == mode) { - MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; + MCG->C2 &= (uint8_t)((~MCG_C2_LOCRE0_MASK) & 0xFFU); } else { @@ -979,17 +980,17 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) if (kMCG_MonitorNone == mode) { - MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK); + MCG->C6 &= (uint8_t)((~MCG_C6_LOLIE0_MASK) & 0xFFU); } else { mcg_c8 = MCG->C8; - mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK); + mcg_c8 &= (uint8_t)((~MCG_C8_LOCS1_MASK) & 0xFFU); if (kMCG_MonitorInt == mode) { - mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK); + mcg_c8 &= (uint8_t)((~MCG_C8_LOLRE_MASK) & 0xFFU); } else { @@ -1076,7 +1077,7 @@ void CLOCK_ClearStatusFlags(uint32_t mask) if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) { - MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK); + MCG->SC &= (uint8_t)((~MCG_SC_ATMF_MASK) & 0xFFU); } if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) { @@ -1102,7 +1103,7 @@ void CLOCK_InitOsc0(osc_config_t const *config) OSC_SetCapLoad(OSC0, config->capLoad); - MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); + MCG->C2 = (uint8_t)(((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode) & 0xFFU); OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) @@ -1122,7 +1123,7 @@ void CLOCK_InitOsc0(osc_config_t const *config) void CLOCK_DeinitOsc0(void) { OSC0->CR = 0U; - MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; + MCG->C2 &= (uint8_t)((~OSC_MODE_MASK) & 0xFFU); } /*! @@ -1200,15 +1201,16 @@ status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_ if (kMCG_AtmSel4m == atms) { + assert(actv <= (UINT32_MAX / 128U)); actv *= 128U; } /* Now begin to start trim. */ MCG->ATCVL = (uint8_t)actv; - MCG->ATCVH = (uint8_t)(actv >> 8U); + MCG->ATCVH = (uint8_t)((actv >> 8U) & 0xFFU); mcg_sc = MCG->SC; - mcg_sc &= ~(uint8_t)(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK); + mcg_sc &= (uint8_t)((~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK)) & 0xFFU); mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms)); MCG->SC = (mcg_sc | MCG_SC_ATME_MASK); @@ -1405,9 +1407,9 @@ status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela } /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | - (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ - | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ + MCG->C1 = (uint8_t)((((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | + (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal))) & 0xFFU); /* IREFS = 1 */ /* Wait and check status. */ while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) @@ -1421,8 +1423,8 @@ status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela } /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */ - MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + MCG->C4 = (uint8_t)(((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | + (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))) & 0xFFU); /* Check MCG_S[CLKST] */ while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) @@ -1481,10 +1483,10 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ - | MCG_C1_FRDIV(frdiv) /* FRDIV */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))) & 0xFFU); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) @@ -1509,8 +1511,8 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set DRS and DMX32. */ - mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + mcg_c4 = (uint8_t)(((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | + (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))) & 0xFFU); MCG->C4 = mcg_c4; /* Wait for DRST_DRS update. */ @@ -1567,11 +1569,11 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela mcg_c4 = MCG->C4; /* Change to FLL mode. */ - MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK); + MCG->C6 &= (uint8_t)((~MCG_C6_PLLS_MASK) & 0xFFU); while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */ + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); /* Disable lowpower. */ /* Errata: ERR007993 @@ -1587,9 +1589,9 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela } /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ - | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal))) & 0xFFU); /* IREFS = 1 */ /* Wait and check status. */ while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) @@ -1606,8 +1608,8 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela { } - MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + MCG->C4 = (uint8_t)(((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | + (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))) & 0xFFU); /* Wait for FLL stable time. */ if (NULL != fllStableDelay) @@ -1648,13 +1650,13 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void #endif /* Change to FLL mode. */ - MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK; + MCG->C6 &= (uint8_t)((~MCG_C6_PLLS_MASK) & 0xFFU); while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } /* Set LP bit to enable the FLL */ - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); mcg_c4 = MCG->C4; @@ -1672,10 +1674,10 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ - | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))) & 0xFFU); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) @@ -1700,8 +1702,8 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set DRST_DRS and DMX32. */ - mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | - (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + mcg_c4 = (uint8_t)(((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | + (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))) & 0xFFU); MCG->C4 = mcg_c4; /* Wait for clock status bits to show clock source is ext ref clk */ @@ -1804,12 +1806,12 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co pllcs = pllcs; /* pllcs is not used. */ /* Clear LP */ - MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); /* Disable lowpower. */ + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); /* Disable lowpower. */ /* Set CLKS and IREFS. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ - | MCG_C1_FRDIV(config->frdiv))); /* FRDIV = frdiv */ + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_FRDIV(config->frdiv))) & 0xFFU); /* FRDIV = frdiv */ /* If use external crystal as clock source, wait for it stable. */ if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) @@ -1829,7 +1831,7 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co } /* Set MCG_C7[PLL32KREFSEL] to select PLL reference clock source */ - MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); + MCG->C7 = (uint8_t)(((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)) & 0xFFU); /* Enable PLL. */ MCG->C6 |= MCG_C6_PLLS_MASK; @@ -1865,7 +1867,7 @@ status_t CLOCK_SetPeeMode(void) #endif /* Change to use PLL/FLL output clock first. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)) & 0xFFU); /* Wait for clock status bits to update */ while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) @@ -1900,10 +1902,10 @@ status_t CLOCK_SetPbiMode(void) { } - MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); /* Disable lowpower. */ + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); /* Disable lowpower. */ /* Set CLKS and IREFS. */ - MCG->C1 = ((MCG->C1 & (uint8_t)(~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | + MCG->C1 = ((MCG->C1 & (uint8_t)((~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) & 0xFFU)) | (uint8_t)(MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ @@ -1914,7 +1916,7 @@ status_t CLOCK_SetPbiMode(void) } /* Set MCG_C7[PLL32KREFSEL] to select slow IRC clock source */ - MCG->C7 = (MCG->C7 & (uint8_t)(~MCG_C7_PLL32KREFSEL_MASK)) | MCG_C7_PLL32KREFSEL(kMCG_PllRefIrc); + MCG->C7 = (MCG->C7 & (uint8_t)((~MCG_C7_PLL32KREFSEL_MASK) & 0xFFU)) | MCG_C7_PLL32KREFSEL(kMCG_PllRefIrc); while (0U == (MCG->S & MCG_S_LOCK0_MASK)) { @@ -1942,7 +1944,7 @@ status_t CLOCK_SetPeiMode(void) #endif /* Change to use PLL/FLL output clock first. */ - MCG->C1 = (MCG->C1 & (uint8_t)(~MCG_C1_CLKS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); + MCG->C1 = (MCG->C1 & (uint8_t)((~MCG_C1_CLKS_MASK) & 0xFFU)) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); /* Wait for clock status bits to update */ while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) @@ -1978,7 +1980,7 @@ status_t CLOCK_ExternalModeToFbeModeQuick(void) #endif /* MCG_CONFIG_CHECK_PARAM */ /* Disable low power */ - MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) @@ -1986,7 +1988,7 @@ status_t CLOCK_ExternalModeToFbeModeQuick(void) } /* Disable PLL. */ - MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK; + MCG->C6 &= (uint8_t)((~MCG_C6_PLLS_MASK) & 0xFFU); while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } @@ -2020,15 +2022,15 @@ status_t CLOCK_InternalModeToFbiModeQuick(void) #endif /* Disable low power */ - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)) & 0xFFU); while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) { } /* Disable PLL. */ - MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK); + MCG->C6 &= (uint8_t)((~MCG_C6_PLLS_MASK) & 0xFFU); while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } @@ -2054,7 +2056,7 @@ status_t CLOCK_InternalModeToFbiModeQuick(void) status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { /* If reset mode is BLPI, first disable LP to enter FBI mode. */ - MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay); } @@ -2077,7 +2079,7 @@ status_t CLOCK_BootToFeeMode( mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { /* If reset mode is BLPI, first disable LP to enter FBI mode. */ - MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); (void)CLOCK_SetExternalRefClkConfig(oscsel); @@ -2117,14 +2119,14 @@ status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEn status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) { /* If reset mode is BLPI, first disable LP to enter FBI mode. */ - MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); (void)CLOCK_SetExternalRefClkConfig(oscsel); /* Set to FBE mode. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + MCG->C1 = (uint8_t)(((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))) & 0xFFU); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) @@ -2171,7 +2173,7 @@ status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mc (void)CLOCK_SetPbeMode(pllcs, config); /* Change to use PLL output clock. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)) & 0xFFU); while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) { } @@ -2197,17 +2199,17 @@ status_t CLOCK_BootToPeiMode(void) } /* Disable lowpower. */ - MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); /* Set MCG_C7[PLL32KREFSEL] to select slow IRC clock source */ - MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(kMCG_PllRefIrc)); + MCG->C7 = (uint8_t)(((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(kMCG_PllRefIrc)) & 0xFFU); while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) { } /* Change to use PLL output clock. */ - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)) & 0xFFU); while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) { } @@ -2288,7 +2290,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) { - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */ + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); /* Disable lowpower. */ if ((MCG->S & MCG_S_PLLST_MASK) != 0U) { @@ -2364,7 +2366,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) } else { - MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; + MCG->C5 &= (uint8_t)((~kMCG_PllEnableIndependent) & 0xFFU); } } diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/drivers/fsl_clock.h index af62f5a33..6d687ec6a 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/drivers/fsl_clock.h @@ -902,7 +902,7 @@ static inline void CLOCK_SetLowPowerEnable(bool enable) } else { - MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; + MCG->C2 &= (uint8_t)((~MCG_C2_LP_MASK) & 0xFFU); } } @@ -947,7 +947,7 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); */ static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv) { - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); + MCG->C1 = (uint8_t)(((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)) & 0xFFU); } /*! @@ -971,7 +971,7 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config); */ static inline void CLOCK_DisablePll0(void) { - MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); + MCG->C5 &= (uint8_t)((~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)) & 0xFFU); } /*@}*/ @@ -1083,7 +1083,7 @@ static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const * { uint8_t reg = base->CR; - reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK)); + reg &= (uint8_t)((~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK)) & 0xFFU); reg |= config->enableMode; base->CR = reg; @@ -1109,7 +1109,7 @@ static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) { uint8_t reg = base->CR; - reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK)); + reg &= (uint8_t)((~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK)) & 0xFFU); reg |= capLoad; base->CR = reg; diff --git a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/system_MKM35Z7.c b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/system_MKM35Z7.c index c9443e2f1..667a0d899 100644 --- a/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/system_MKM35Z7.c +++ b/mcux/mcux-sdk-ng/devices/Kinetis/KM/MKM35Z7/system_MKM35Z7.c @@ -57,7 +57,7 @@ #include #include "fsl_device_registers.h" - +#define SAFE_MULTI(multi, max) ((multi) > (max) ? 0U : (multi)) /* ---------------------------------------------------------------------------- -- Core clock @@ -95,6 +95,7 @@ void SystemCoreClockUpdate (void) { uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ uint16_t Divider; + uint32_t max; if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { /* Output of FLL or PLL is selected */ @@ -116,44 +117,45 @@ void SystemCoreClockUpdate (void) { Divider = 1280U; break; default: - Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + Divider = (uint16_t)((32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)) & 0xFFFFU); break; } } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */ - Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + Divider = (uint16_t)((1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)) & 0xFFFFU); } MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ } else { MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ } /* Select correct multiplier to calculate the MCG output clock */ + max = UINT32_MAX / MCGOUTClock; switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { case 0x00U: - MCGOUTClock *= 640U; + MCGOUTClock *= SAFE_MULTI(640U, max); break; case 0x20U: - MCGOUTClock *= 1280U; + MCGOUTClock *= SAFE_MULTI(1280U, max); break; case 0x40U: - MCGOUTClock *= 1920U; + MCGOUTClock *= SAFE_MULTI(1920U, max); break; case 0x60U: - MCGOUTClock *= 2560U; + MCGOUTClock *= SAFE_MULTI(2560U, max); break; case 0x80U: - MCGOUTClock *= 732U; + MCGOUTClock *= SAFE_MULTI(732U, max); break; case 0xA0U: - MCGOUTClock *= 1464U; + MCGOUTClock *= SAFE_MULTI(1464U, max); break; case 0xC0U: - MCGOUTClock *= 2197U; + MCGOUTClock *= SAFE_MULTI(2197U, max); break; case 0xE0U: - MCGOUTClock *= 2929U; + MCGOUTClock *= SAFE_MULTI(2929U, max); break; default: - MCGOUTClock *= 640U; + MCGOUTClock *= SAFE_MULTI(640U, max); break; } } @@ -181,25 +183,26 @@ void SystemCoreClockUpdate (void) { Divider = 1280U; break; default: - Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + Divider = (uint16_t)((32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)) & 0xFFFFU); break; } } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */ - Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + Divider = (uint16_t)((1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)) & 0xFFFFU); } MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ } else { /* (MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0xB0U */ /* Reserved value */ return; } - MCGOUTClock *= 375U; /* Calculate the MCG output clock */ + max = UINT32_MAX / MCGOUTClock; + MCGOUTClock *= SAFE_MULTI(375U, max); /* Calculate the MCG output clock */ } } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { /* Internal reference clock is selected */ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ } else { /* Fast internal reference clock selected */ - Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); + Divider = (uint16_t)((0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)) & 0xFFFFU); MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); } } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { From 070df1f5178002d346a91e636d0452f6522d97c6 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:12:24 +0800 Subject: [PATCH 06/21] hal_nxp: mcux-sdk-ng: Update device/LPC to sdk 25.09.00 Signed-off-by: Zhaoxiang Jin --- .../LPC/LPC51U68/LPC51U68/LPC51U68_features.h | 18 +++- .../LPC/LPC54000/LPC54005/LPC54005_features.h | 18 +++- .../LPC/LPC54000/LPC54016/LPC54016_features.h | 18 +++- .../LPC/LPC54000/LPC54018/LPC54018_features.h | 18 +++- .../LPC54000/LPC54018M/LPC54018M_features.h | 18 +++- .../LPC/LPC54000/LPC54605/LPC54605_features.h | 18 +++- .../LPC/LPC54000/LPC54606/LPC54606_features.h | 18 +++- .../LPC/LPC54000/LPC54607/LPC54607_features.h | 18 +++- .../LPC/LPC54000/LPC54608/LPC54608_features.h | 18 +++- .../LPC/LPC54000/LPC54616/LPC54616_features.h | 18 +++- .../LPC/LPC54000/LPC54618/LPC54618_features.h | 18 +++- .../LPC/LPC54000/LPC54628/LPC54628_features.h | 18 +++- .../LPC54000/LPC54S005/LPC54S005_features.h | 18 +++- .../LPC54000/LPC54S016/LPC54S016_features.h | 18 +++- .../LPC54000/LPC54S018/LPC54S018_features.h | 18 +++- .../LPC54000/LPC54S018M/LPC54S018M_features.h | 18 +++- .../LPC/LPC5500/LPC5502/LPC5502_features.h | 16 +++- .../LPC/LPC5500/LPC5504/LPC5504_features.h | 16 +++- .../LPC/LPC5500/LPC5506/LPC5506_features.h | 16 +++- .../LPC/LPC5500/LPC5512/LPC5512_features.h | 16 +++- .../LPC/LPC5500/LPC5514/LPC5514_features.h | 16 +++- .../LPC/LPC5500/LPC5516/LPC5516_features.h | 16 +++- .../devices/LPC/LPC5500/LPC5526/LPC5526.h | 2 +- .../LPC/LPC5500/LPC5526/LPC5526_COMMON.h | 2 +- .../LPC/LPC5500/LPC5526/LPC5526_features.h | 16 +++- .../LPC/LPC5500/LPC5526/system_LPC5526.c | 2 +- .../LPC/LPC5500/LPC5526/system_LPC5526.h | 2 +- .../devices/LPC/LPC5500/LPC5528/LPC5528.h | 2 +- .../LPC/LPC5500/LPC5528/LPC5528_COMMON.h | 2 +- .../LPC/LPC5500/LPC5528/LPC5528_features.h | 16 +++- .../LPC/LPC5500/LPC5528/system_LPC5528.c | 2 +- .../LPC/LPC5500/LPC5528/system_LPC5528.h | 2 +- .../LPC/LPC5500/LPC5534/LPC5534_COMMON.h | 35 ++++---- .../LPC/LPC5500/LPC5534/LPC5534_features.h | 83 +++++++++++++------ .../LPC/LPC5500/LPC5536/LPC5536_COMMON.h | 35 ++++---- .../LPC/LPC5500/LPC5536/LPC5536_features.h | 83 +++++++++++++------ .../LPC/LPC5500/LPC55S04/LPC55S04_features.h | 16 +++- .../LPC/LPC5500/LPC55S06/LPC55S06_features.h | 16 +++- .../LPC/LPC5500/LPC55S06/drivers/fsl_reset.h | 6 +- .../LPC/LPC5500/LPC55S14/LPC55S14_features.h | 16 +++- .../LPC/LPC5500/LPC55S16/LPC55S16_features.h | 16 +++- .../LPC/LPC5500/LPC55S16/drivers/fsl_reset.h | 6 +- .../devices/LPC/LPC5500/LPC55S26/LPC55S26.h | 2 +- .../LPC/LPC5500/LPC55S26/LPC55S26_COMMON.h | 2 +- .../LPC/LPC5500/LPC55S26/LPC55S26_features.h | 16 +++- .../LPC/LPC5500/LPC55S26/system_LPC55S26.c | 2 +- .../LPC/LPC5500/LPC55S26/system_LPC55S26.h | 2 +- .../devices/LPC/LPC5500/LPC55S28/LPC55S28.h | 2 +- .../LPC/LPC5500/LPC55S28/LPC55S28_COMMON.h | 2 +- .../LPC/LPC5500/LPC55S28/LPC55S28_features.h | 16 +++- .../LPC/LPC5500/LPC55S28/system_LPC55S28.c | 2 +- .../LPC/LPC5500/LPC55S28/system_LPC55S28.h | 2 +- .../LPC/LPC5500/LPC55S36/LPC55S36_COMMON.h | 35 ++++---- .../LPC/LPC5500/LPC55S36/LPC55S36_features.h | 83 +++++++++++++------ .../LPC5500/LPC55S36/drivers/CMakeLists.txt | 24 +----- .../runbootloader/src/fsl_runbootloader.c | 3 - .../LPC5500/LPC55S66/LPC55S66_cm33_core0.h | 2 +- .../LPC55S66/LPC55S66_cm33_core0_COMMON.h | 2 +- .../LPC55S66/LPC55S66_cm33_core0_features.h | 16 +++- .../LPC5500/LPC55S66/LPC55S66_cm33_core1.h | 2 +- .../LPC55S66/LPC55S66_cm33_core1_COMMON.h | 2 +- .../LPC55S66/LPC55S66_cm33_core1_features.h | 16 +++- .../LPC55S66/system_LPC55S66_cm33_core0.c | 2 +- .../LPC55S66/system_LPC55S66_cm33_core0.h | 2 +- .../LPC55S66/system_LPC55S66_cm33_core1.c | 2 +- .../LPC55S66/system_LPC55S66_cm33_core1.h | 2 +- .../LPC5500/LPC55S69/LPC55S69_cm33_core0.h | 2 +- .../LPC55S69/LPC55S69_cm33_core0_COMMON.h | 2 +- .../LPC55S69/LPC55S69_cm33_core0_features.h | 16 +++- .../LPC5500/LPC55S69/LPC55S69_cm33_core1.h | 2 +- .../LPC55S69/LPC55S69_cm33_core1_COMMON.h | 2 +- .../LPC55S69/LPC55S69_cm33_core1_features.h | 16 +++- .../LPC55S69/system_LPC55S69_cm33_core0.c | 2 +- .../LPC55S69/system_LPC55S69_cm33_core0.h | 2 +- .../LPC55S69/system_LPC55S69_cm33_core1.c | 2 +- .../LPC55S69/system_LPC55S69_cm33_core1.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_ADC.h | 2 +- .../LPC/LPC5500/periph/PERI_AHB_SECURE_CTRL.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_ANACTRL.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_CASPER.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_CRC.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_CTIMER.h | 2 +- .../LPC/LPC5500/periph/PERI_DBGMAILBOX.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_DMA.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_FLASH.h | 2 +- .../LPC/LPC5500/periph/PERI_FLASH_CFPA.h | 2 +- .../LPC/LPC5500/periph/PERI_FLASH_CMPA.h | 2 +- .../LPC/LPC5500/periph/PERI_FLASH_KEY_STORE.h | 2 +- .../LPC/LPC5500/periph/PERI_FLEXCOMM.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_GINT.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_GPIO.h | 2 +- .../LPC/LPC5500/periph/PERI_HASHCRYPT.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_I2C.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_I2S.h | 2 +- .../LPC/LPC5500/periph/PERI_INPUTMUX.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_IOCON.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_MAILBOX.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_MRT.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_OSTIMER.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_PINT.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_PLU.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_PMC.h | 2 +- .../LPC/LPC5500/periph/PERI_POWERQUAD.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_PRINCE.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_PUF.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_RNG.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_RTC.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_SCT.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_SDIF.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_SPI.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_SYSCON.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_SYSCTL.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_USART.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_USB.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_USBFSH.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_USBHSD.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_USBHSH.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_USBPHY.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_UTICK.h | 2 +- .../devices/LPC/LPC5500/periph/PERI_WWDT.h | 2 +- .../LPC/LPC800/LPC802/LPC802_features.h | 12 ++- .../LPC/LPC800/LPC802/drivers/fsl_power.c | 2 +- .../LPC/LPC800/LPC804/LPC804_features.h | 12 ++- .../LPC/LPC800/LPC804/drivers/fsl_power.c | 2 +- .../LPC/LPC800/LPC822/LPC822_features.h | 12 ++- .../LPC/LPC800/LPC824/LPC824_features.h | 12 ++- .../LPC/LPC800/LPC824/drivers/fsl_power.c | 2 +- .../LPC/LPC800/LPC832/LPC832_features.h | 12 ++- .../LPC/LPC800/LPC834/LPC834_features.h | 12 ++- .../LPC/LPC800/LPC844/LPC844_features.h | 12 ++- .../LPC/LPC800/LPC845/LPC845_features.h | 12 ++- .../LPC/LPC800/LPC845/drivers/fsl_power.c | 2 +- .../LPC/LPC800/LPC864/LPC864_features.h | 27 +++--- .../LPC/LPC800/LPC865/LPC865_features.h | 27 +++--- .../LPC/LPC800/LPC865/drivers/fsl_power.c | 2 +- 135 files changed, 881 insertions(+), 400 deletions(-) diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC51U68/LPC51U68/LPC51U68_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC51U68/LPC51U68/LPC51U68_features.h index d05fcd8f3..656ce98b5 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC51U68/LPC51U68/LPC51U68_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC51U68/LPC51U68/LPC51U68_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2017-12-15 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -224,6 +224,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SPI module features */ @@ -261,10 +263,20 @@ /* @brief Number of the endpoint in USB FS */ #define FSL_FEATURE_USB_EP_NUM (5) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC51U68_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54005/LPC54005_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54005/LPC54005_features.h index b31ed169e..5984895a4 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54005/LPC54005_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54005/LPC54005_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -276,6 +276,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -361,10 +363,20 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54005_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54016/LPC54016_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54016/LPC54016_features.h index d1eb5ebb1..44031a737 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54016/LPC54016_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54016/LPC54016_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -285,6 +285,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -370,10 +372,20 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54016_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54018/LPC54018_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54018/LPC54018_features.h index 848a95c5b..8ff33feb9 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54018/LPC54018_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54018/LPC54018_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -287,6 +287,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -372,10 +374,20 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54018_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54018M/LPC54018M_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54018M/LPC54018M_features.h index 4e97874bf..d578161c9 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54018M/LPC54018M_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54018M/LPC54018M_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -287,6 +287,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -370,10 +372,20 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54018M_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54605/LPC54605_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54605/LPC54605_features.h index f7ea36f6c..3cade1757 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54605/LPC54605_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54605/LPC54605_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -290,6 +290,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -397,10 +399,20 @@ /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54605_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54606/LPC54606_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54606/LPC54606_features.h index bc5494c6b..8eda9d17a 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54606/LPC54606_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54606/LPC54606_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -299,6 +299,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -406,10 +408,20 @@ /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54606_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54607/LPC54607_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54607/LPC54607_features.h index 950d635a2..fd5e47034 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54607/LPC54607_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54607/LPC54607_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -292,6 +292,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -399,10 +401,20 @@ /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54607_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54608/LPC54608_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54608/LPC54608_features.h index d94d5b0e7..9bbf13b34 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54608/LPC54608_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54608/LPC54608_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -301,6 +301,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -385,10 +387,20 @@ /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54608_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54616/LPC54616_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54616/LPC54616_features.h index 643078a39..8a469aa31 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54616/LPC54616_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54616/LPC54616_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -299,6 +299,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -406,10 +408,20 @@ /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54616_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54618/LPC54618_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54618/LPC54618_features.h index 8404012e7..603abacd7 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54618/LPC54618_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54618/LPC54618_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -301,6 +301,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -385,10 +387,20 @@ /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54618_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54628/LPC54628_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54628/LPC54628_features.h index 6a603c1b3..862f4f79d 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54628/LPC54628_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54628/LPC54628_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -303,6 +303,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -392,10 +394,20 @@ /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54628_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S005/LPC54S005_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S005/LPC54S005_features.h index 48adfebe0..668d8bf1b 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S005/LPC54S005_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S005/LPC54S005_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -284,6 +284,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -367,10 +369,20 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54S005_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S016/LPC54S016_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S016/LPC54S016_features.h index 5b21ddfa2..50ba3c5da 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S016/LPC54S016_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S016/LPC54S016_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -293,6 +293,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -376,10 +378,20 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54S016_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S018/LPC54S018_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S018/LPC54S018_features.h index 301f3dbb1..62f6833ce 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S018/LPC54S018_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S018/LPC54S018_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -295,6 +295,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -378,10 +380,20 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54S018_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S018M/LPC54S018M_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S018M/LPC54S018M_features.h index 23fb80d59..1a0ce6424 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S018M/LPC54S018M_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC54000/LPC54S018M/LPC54S018M_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -293,6 +293,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -376,10 +378,20 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC54S018M_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5502/LPC5502_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5502/LPC5502_features.h index e3b89dfde..b8cab22bb 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5502/LPC5502_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5502/LPC5502_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-04-09 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -490,6 +490,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -521,12 +523,20 @@ /* @brief SYSCTRL has Code Gray feature. */ #define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5502_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5504/LPC5504_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5504/LPC5504_features.h index 237d46d5f..d281f71e4 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5504/LPC5504_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5504/LPC5504_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-04-09 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -490,6 +490,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -521,12 +523,20 @@ /* @brief SYSCTRL has Code Gray feature. */ #define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5504_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5506/LPC5506_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5506/LPC5506_features.h index 4465ceedd..cea488e36 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5506/LPC5506_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5506/LPC5506_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-04-09 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -490,6 +490,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -521,12 +523,20 @@ /* @brief SYSCTRL has Code Gray feature. */ #define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5506_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5512/LPC5512_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5512/LPC5512_features.h index 7a26e10b0..4f628db81 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5512/LPC5512_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5512/LPC5512_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-12-03 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -378,6 +378,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -421,12 +423,20 @@ /* @brief USBFSH version */ #define FSL_FEATURE_USBFSH_VERSION (200) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5512_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5514/LPC5514_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5514/LPC5514_features.h index 84e5618f3..8627e906b 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5514/LPC5514_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5514/LPC5514_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-12-03 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -384,6 +384,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -466,12 +468,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5514_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5516/LPC5516_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5516/LPC5516_features.h index fa7aef330..5fb3b126a 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5516/LPC5516_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5516/LPC5516_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-12-03 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -384,6 +384,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -466,12 +468,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5516_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526.h index b871203f5..ef7ebd223 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC5526 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526_COMMON.h index e1cfdfad2..04b679fc4 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC5526 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526_features.h index 92edafc4b..615ac259b 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/LPC5526_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-05-16 -** Build: b250512 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -359,6 +359,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -451,12 +453,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5526_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/system_LPC5526.c b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/system_LPC5526.c index 3f09ab861..3dd511329 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/system_LPC5526.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/system_LPC5526.c @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/system_LPC5526.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/system_LPC5526.h index eca175037..c709c5cf7 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/system_LPC5526.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5526/system_LPC5526.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528.h index c71f52c7b..653fcc076 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC5528 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528_COMMON.h index 620f0b6da..3b0cd94e5 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC5528 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528_features.h index bcf4d5dd8..1f377efb2 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/LPC5528_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-05-16 -** Build: b250512 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -359,6 +359,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -451,12 +453,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5528_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/system_LPC5528.c b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/system_LPC5528.c index 69f070cca..a87eb6c06 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/system_LPC5528.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/system_LPC5528.c @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/system_LPC5528.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/system_LPC5528.h index 4cd7ecd0d..55222f527 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/system_LPC5528.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5528/system_LPC5528.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5534/LPC5534_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5534/LPC5534_COMMON.h index 9d2353f67..d330454e8 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5534/LPC5534_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5534/LPC5534_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC5534 @@ -939,25 +939,22 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5534/LPC5534_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5534/LPC5534_features.h index c750178b2..f6fbc748d 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5534/LPC5534_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5534/LPC5534_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.1, 2021-08-04 -** Build: b250512 +** Version: rev. 2.0, 2024-10-29 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,9 @@ ** Initial version based on RM DraftF ** - rev. 1.1 (2021-08-04) ** Initial version based on RM DraftG +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ @@ -506,22 +509,34 @@ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) /* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) -/* @brief FlexSPI has no IPCR1 IPAREN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN (1) -/* @brief FlexSPI has no AHBCR APAREN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN (1) /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) -/* @brief FlexSPI has no FLSHCR4 WMENB bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) /* @brief FlexSPI has no STS2 BSLVLOCK bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (1) /* @brief FlexSPI has no STS2 BREFLOCK bit */ @@ -530,24 +545,24 @@ #define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (1) /* @brief FlexSPI LUTKEY is read only. */ #define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (1) -/* @brief There is AHBBUSERROREN bit in INTEN register. */ -#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) -/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ -#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) -/* @brief FLEXSPI has no IP parallel mode. */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) -/* @brief FLEXSPI has no AHB parallel mode. */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) -/* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) -/* @brief FlexSPI AHB RX buffer size (byte) */ -#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) /* @brief FlexSPI IPED REGION COUNT */ #define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (4) -/* @brief FlexSPI Array Length */ -#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GINT module features */ @@ -573,14 +588,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -652,6 +667,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTC module features */ @@ -692,6 +709,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SPI module features */ @@ -737,6 +756,10 @@ #define FSL_FEATURE_USBFSH_VERSION (200) #endif /* defined(CPU_LPC5534JBD100) */ +/* UTICK module features */ + +/* No feature definitions */ + /* VREF module features */ /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ @@ -752,8 +775,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5534_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5536/LPC5536_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5536/LPC5536_COMMON.h index 66eff23f4..3d248636e 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5536/LPC5536_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5536/LPC5536_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC5536 @@ -939,25 +939,22 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5536/LPC5536_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5536/LPC5536_features.h index 0f6a1b888..7d89c4b41 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5536/LPC5536_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC5536/LPC5536_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.1, 2021-08-04 -** Build: b250512 +** Version: rev. 2.0, 2024-10-29 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,9 @@ ** Initial version based on RM DraftF ** - rev. 1.1 (2021-08-04) ** Initial version based on RM DraftG +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ @@ -506,22 +509,34 @@ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) /* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) -/* @brief FlexSPI has no IPCR1 IPAREN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN (1) -/* @brief FlexSPI has no AHBCR APAREN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN (1) /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) -/* @brief FlexSPI has no FLSHCR4 WMENB bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) /* @brief FlexSPI has no STS2 BSLVLOCK bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (1) /* @brief FlexSPI has no STS2 BREFLOCK bit */ @@ -530,24 +545,24 @@ #define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (1) /* @brief FlexSPI LUTKEY is read only. */ #define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (1) -/* @brief There is AHBBUSERROREN bit in INTEN register. */ -#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) -/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ -#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) -/* @brief FLEXSPI has no IP parallel mode. */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) -/* @brief FLEXSPI has no AHB parallel mode. */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) -/* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) -/* @brief FlexSPI AHB RX buffer size (byte) */ -#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) /* @brief FlexSPI IPED REGION COUNT */ #define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (4) -/* @brief FlexSPI Array Length */ -#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GINT module features */ @@ -573,14 +588,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -652,6 +667,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTC module features */ @@ -692,6 +709,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SPI module features */ @@ -737,6 +756,10 @@ #define FSL_FEATURE_USBFSH_VERSION (200) #endif /* defined(CPU_LPC5536JBD100) */ +/* UTICK module features */ + +/* No feature definitions */ + /* VREF module features */ /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ @@ -752,8 +775,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC5536_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S04/LPC55S04_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S04/LPC55S04_features.h index 733b3991e..68dddc08a 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S04/LPC55S04_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S04/LPC55S04_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-04-09 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -533,6 +533,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -564,12 +566,20 @@ /* @brief SYSCTRL has Code Gray feature. */ #define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S04_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S06/LPC55S06_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S06/LPC55S06_features.h index 2b76bc856..f528b3fea 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S06/LPC55S06_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S06/LPC55S06_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-04-09 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -533,6 +533,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -564,12 +566,20 @@ /* @brief SYSCTRL has Code Gray feature. */ #define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S06_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S06/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S06/drivers/fsl_reset.h index 6cdceace6..c49987fa9 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S06/drivers/fsl_reset.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S06/drivers/fsl_reset.h @@ -145,9 +145,9 @@ typedef enum _SYSCON_RSTn { \ kMRT_RST_SHIFT_RSTn \ } /* Reset bits for MRT peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn, kGPIOSECINT_RST_SHIFT_RSTn \ } /* Reset bits for PINT peripheral */ #define CDOG_RSTS \ { \ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S14/LPC55S14_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S14/LPC55S14_features.h index 89675ed0b..07249a1bb 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S14/LPC55S14_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S14/LPC55S14_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-12-03 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -419,6 +419,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -501,12 +503,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S14_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S16/LPC55S16_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S16/LPC55S16_features.h index 428aa8760..0f23b3424 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S16/LPC55S16_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S16/LPC55S16_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-12-03 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -419,6 +419,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -501,12 +503,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S16_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S16/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S16/drivers/fsl_reset.h index 988b1ef31..d2f7d9564 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S16/drivers/fsl_reset.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S16/drivers/fsl_reset.h @@ -151,9 +151,9 @@ typedef enum _SYSCON_RSTn { \ kMRT_RST_SHIFT_RSTn \ } /* Reset bits for MRT peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn, kGPIOSECINT_RST_SHIFT_RSTn \ } /* Reset bits for PINT peripheral */ #define CDOG_RSTS \ { \ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26.h index ae20f7d3f..d6bf9d28e 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S26 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26_COMMON.h index ae52ec96f..1de49c24d 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S26 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26_features.h index 5c3c57e98..ef903701b 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/LPC55S26_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-05-16 -** Build: b250512 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -390,6 +390,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -482,12 +484,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S26_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/system_LPC55S26.c b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/system_LPC55S26.c index bf50a0817..d57541963 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/system_LPC55S26.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/system_LPC55S26.c @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/system_LPC55S26.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/system_LPC55S26.h index 5a6cc2d23..5172cb5cf 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/system_LPC55S26.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S26/system_LPC55S26.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28.h index 0ea824c66..68cc346e9 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S28 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28_COMMON.h index b90b3929d..4806e1bab 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S28 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28_features.h index 6c6ea8ca8..eed6cedd7 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/LPC55S28_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-05-16 -** Build: b250512 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -390,6 +390,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -482,12 +484,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S28_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/system_LPC55S28.c b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/system_LPC55S28.c index 713f60c70..dc89251f5 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/system_LPC55S28.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/system_LPC55S28.c @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/system_LPC55S28.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/system_LPC55S28.h index 4d8b98626..7bdf9b872 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/system_LPC55S28.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S28/system_LPC55S28.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/LPC55S36_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/LPC55S36_COMMON.h index 69f2f7600..d1982d207 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/LPC55S36_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/LPC55S36_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: LPC55S3x Reference Manual Rev. DraftG, 07/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S36 @@ -938,25 +938,22 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/LPC55S36_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/LPC55S36_features.h index 2b1979715..89b670a11 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/LPC55S36_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/LPC55S36_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.1, 2021-08-04 -** Build: b250512 +** Version: rev. 2.0, 2024-10-29 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,9 @@ ** Initial version based on RM DraftF ** - rev. 1.1 (2021-08-04) ** Initial version based on RM DraftG +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ @@ -526,22 +529,34 @@ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) /* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) -/* @brief FlexSPI has no IPCR1 IPAREN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN (1) -/* @brief FlexSPI has no AHBCR APAREN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN (1) /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) -/* @brief FlexSPI has no FLSHCR4 WMENB bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) /* @brief FlexSPI has no STS2 BSLVLOCK bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (1) /* @brief FlexSPI has no STS2 BREFLOCK bit */ @@ -550,24 +565,24 @@ #define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (1) /* @brief FlexSPI LUTKEY is read only. */ #define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (1) -/* @brief There is AHBBUSERROREN bit in INTEN register. */ -#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) -/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ -#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) -/* @brief FLEXSPI has no IP parallel mode. */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) -/* @brief FLEXSPI has no AHB parallel mode. */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) -/* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) -/* @brief FlexSPI AHB RX buffer size (byte) */ -#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) /* @brief FlexSPI IPED REGION COUNT */ #define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (4) -/* @brief FlexSPI Array Length */ -#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GINT module features */ @@ -593,14 +608,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -681,6 +696,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTC module features */ @@ -721,6 +738,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SPI module features */ @@ -766,6 +785,10 @@ #define FSL_FEATURE_USBFSH_VERSION (200) #endif /* defined(CPU_LPC55S36JBD100) */ +/* UTICK module features */ + +/* No feature definitions */ + /* VREF module features */ /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ @@ -781,8 +804,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S36_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/drivers/CMakeLists.txt index 7522bccad..928abe874 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/drivers/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/drivers/CMakeLists.txt @@ -87,27 +87,7 @@ endif() if (CONFIG_MCUX_COMPONENT_driver.romapi) mcux_component_version(2.0.0) mcux_add_source( - SOURCES - ./romapi/flash/fsl_efuse.h - ./romapi/flash/fsl_flash.h - ./romapi/flash/fsl_flash_ffr.h - ./romapi/flash/fsl_flexspi_nor_flash.h - ./romapi/flash/src/fsl_flash.c - ./romapi/mem_interface/fsl_mem_interface.h - ./romapi/mem_interface/fsl_sbloader.h - ./romapi/mem_interface/fsl_sbloader_v3.h - ./romapi/mem_interface/src/fsl_mem_interface.c - ./romapi/nboot/fsl_nboot.h - ./romapi/nboot/fsl_nboot_hal.h - ./romapi/nboot/src/fsl_nboot.c - ./romapi/runbootloader/fsl_runbootloader.h - ./romapi/runbootloader/src/fsl_runbootloader.c - ) - - mcux_add_include( - INCLUDES ./romapi/mem_interface - ./romapi/flash - ./romapi/nboot - ./romapi/runbootloader + SOURCES ./romapi/flash/fsl_flash.h ) + mcux_add_include( INCLUDES ./romapi/flash ) endif() diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/drivers/romapi/runbootloader/src/fsl_runbootloader.c b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/drivers/romapi/runbootloader/src/fsl_runbootloader.c index c440a1e65..e95d48d59 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/drivers/romapi/runbootloader/src/fsl_runbootloader.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S36/drivers/romapi/runbootloader/src/fsl_runbootloader.c @@ -4,9 +4,6 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#include "fsl_flash.h" -#include "fsl_flash_ffr.h" -#include "fsl_flexspi_nor_flash.h" #include "fsl_runbootloader.h" /*! @brief Component ID definition, used by tools. */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0.h index 6ccecfc5e..115ae9fa2 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S66_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0_COMMON.h index 5ae4f71ee..e6e427af0 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S66_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0_features.h index 390edc794..10e5332fb 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-05-16 -** Build: b250512 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -404,6 +404,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -496,12 +498,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S66_cm33_core0_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1.h index e8e0852c4..271502148 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S66_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1_COMMON.h index 395ac24a8..4b6b5ac79 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S66_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1_features.h index b17d82fe4..a4e2021ee 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/LPC55S66_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-05-16 -** Build: b250512 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -404,6 +404,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -496,12 +498,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S66_cm33_core1_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core0.c b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core0.c index 021d9546a..04a14ba01 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core0.c @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core0.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core0.h index 47e9e4585..18b85a226 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core0.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core1.c b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core1.c index 7867c5ac0..37a52399d 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core1.c @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core1.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core1.h index 5e2314517..99b6d32c2 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S66/system_LPC55S66_cm33_core1.h @@ -11,7 +11,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0.h index 7661ad3ac..47b81b962 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0_COMMON.h index ee88e8b7e..93a5d9ad5 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0_features.h index cff661007..8afb581e0 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-05-16 -** Build: b250512 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -404,6 +404,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -496,12 +498,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1.h index b0ad1b432..e433c2f27 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1_COMMON.h index a1eb86d34..83421201e 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1_features.h index cd7424c90..e1bd5a6bb 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/LPC55S69_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-05-16 -** Build: b250512 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -404,6 +404,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SDIF module features */ @@ -496,12 +498,20 @@ /* @brief Number of the endpoint in USB HS */ #define FSL_FEATURE_USBPHY_EP_NUM (6) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC55S69_cm33_core1_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core0.c b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core0.c index a705bc8cb..6c5bb2d5e 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core0.c @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core0.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core0.h index b817e9067..6f4b0ce5b 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core0.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core1.c b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core1.c index 31916157d..8217409c7 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core1.c @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core1.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core1.h index 3cea18be0..e21d0b17d 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/system_LPC55S69_cm33_core1.h @@ -12,7 +12,7 @@ ** ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_ADC.h index 4b8e1347a..a45f4cc5d 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_ADC.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_AHB_SECURE_CTRL.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_AHB_SECURE_CTRL.h index bf2c59077..9ddb40cbb 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_AHB_SECURE_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_AHB_SECURE_CTRL.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for AHB_SECURE_CTRL diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_ANACTRL.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_ANACTRL.h index f078b0c3e..c0ae09376 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_ANACTRL.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_ANACTRL.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANACTRL diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CASPER.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CASPER.h index c8a7ded82..df622f680 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CASPER.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CASPER.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for CASPER diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CRC.h index 7815be93c..0a2f024c8 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CRC.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CTIMER.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CTIMER.h index 554801ed1..2dff9ef7c 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CTIMER.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_CTIMER.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for CTIMER diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_DBGMAILBOX.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_DBGMAILBOX.h index c13ec0411..a18acfcbf 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_DBGMAILBOX.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_DBGMAILBOX.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for DBGMAILBOX diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_DMA.h index e9ef2e11e..b6777ba2e 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_DMA.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH.h index 567ff69e4..e62b88867 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_CFPA.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_CFPA.h index 5fcf28b40..00b8a725b 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_CFPA.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_CFPA.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH_CFPA diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_CMPA.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_CMPA.h index 08775edf4..e0d21d4d6 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_CMPA.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_CMPA.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH_CMPA diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_KEY_STORE.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_KEY_STORE.h index 1716641f5..e00159328 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_KEY_STORE.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLASH_KEY_STORE.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH_KEY_STORE diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLEXCOMM.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLEXCOMM.h index fa7775d29..884ebd8e2 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLEXCOMM.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_FLEXCOMM.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXCOMM diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_GINT.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_GINT.h index a937a5230..17d4d16b9 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_GINT.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_GINT.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for GINT diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_GPIO.h index e29438d38..37319caf1 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_GPIO.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_HASHCRYPT.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_HASHCRYPT.h index cd3b982dd..8904ef885 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_HASHCRYPT.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_HASHCRYPT.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for HASHCRYPT diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_I2C.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_I2C.h index 037f00488..8dbaa89d8 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_I2C.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_I2C.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2C diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_I2S.h index 27a87f6e7..e743d5bdf 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_I2S.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_INPUTMUX.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_INPUTMUX.h index 5b699a427..702bf82b8 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_INPUTMUX.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_INPUTMUX.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for INPUTMUX diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_IOCON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_IOCON.h index 0905ec815..be24a28ad 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_IOCON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_IOCON.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOCON diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_MAILBOX.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_MAILBOX.h index c058ca830..1a8ba120c 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_MAILBOX.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_MAILBOX.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for MAILBOX diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_MRT.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_MRT.h index 401fe59e0..ecf3b36ae 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_MRT.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_MRT.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for MRT diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_OSTIMER.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_OSTIMER.h index 8c68c09f7..d12de4133 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_OSTIMER.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_OSTIMER.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSTIMER diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PINT.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PINT.h index 7082475f3..ce9950a43 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PINT.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PINT.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for PINT diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PLU.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PLU.h index c5589bbd9..b1bf8192e 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PLU.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PLU.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for PLU diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PMC.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PMC.h index ec13300ef..5dafcb718 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PMC.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PMC.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for PMC diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_POWERQUAD.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_POWERQUAD.h index 26dbb0a56..6ec59b65a 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_POWERQUAD.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_POWERQUAD.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for POWERQUAD diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PRINCE.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PRINCE.h index 1c98fe15c..365ede601 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PRINCE.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PRINCE.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for PRINCE diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PUF.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PUF.h index 8118916a7..a609ad550 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PUF.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_PUF.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for PUF diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_RNG.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_RNG.h index e65528443..2bd8eb095 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_RNG.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_RNG.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for RNG diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_RTC.h index 7a9d0921a..337a512a7 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_RTC.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SCT.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SCT.h index f78e14a86..2123da744 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SCT.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SCT.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for SCT diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SDIF.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SDIF.h index 13107651c..0f4192136 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SDIF.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SDIF.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for SDIF diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SPI.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SPI.h index 358465459..a5bfa98ad 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SPI.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SPI.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPI diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SYSCON.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SYSCON.h index 0e6a2d7a0..7a3eb47de 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SYSCON.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SYSCON.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SYSCTL.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SYSCTL.h index 64ce51f89..3b8a5948b 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SYSCTL.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_SYSCTL.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCTL diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USART.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USART.h index 012b4f5c3..bb9255c12 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USART.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USART.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USART diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USB.h index fab869fb1..e2c848385 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USB.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBFSH.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBFSH.h index 1fa24c394..ff62a4250 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBFSH.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBFSH.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBFSH diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBHSD.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBHSD.h index 8d4ea98d8..807f76e4c 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBHSD.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBHSD.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBHSD diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBHSH.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBHSH.h index e3fa1dda7..37313554e 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBHSH.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBHSH.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBHSH diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBPHY.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBPHY.h index 3689314c3..d5cda7323 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBPHY.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_USBPHY.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBPHY diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_UTICK.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_UTICK.h index 501e22552..7500231ed 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_UTICK.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_UTICK.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for UTICK diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_WWDT.h b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_WWDT.h index f0e864cea..fc890311a 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_WWDT.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC5500/periph/PERI_WWDT.h @@ -30,7 +30,7 @@ ** LPC55S69JEV98_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for WWDT diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC802/LPC802_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC802/LPC802_features.h index d8ced1e28..640f9e493 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC802/LPC802_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC802/LPC802_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-01-09 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -190,10 +190,14 @@ /* WWDT module features */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief Has LPOSC as clock source. */ #define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (1) -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC802_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC802/drivers/fsl_power.c b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC802/drivers/fsl_power.c index 7c899cf16..e9faff96d 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC802/drivers/fsl_power.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC802/drivers/fsl_power.c @@ -8,7 +8,7 @@ #include "fsl_power.h" /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power_no_lib" +#define FSL_COMPONENT_ID "platform.drivers.power" #endif /******************************************************************************* * Definitions diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC804/LPC804_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC804/LPC804_features.h index e557495ae..067076bfc 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC804/LPC804_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC804/LPC804_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-01-09 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -246,10 +246,14 @@ /* WWDT module features */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief Has LPOSC as clock source. */ #define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (1) -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC804_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC804/drivers/fsl_power.c b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC804/drivers/fsl_power.c index 919d4378f..540de5277 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC804/drivers/fsl_power.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC804/drivers/fsl_power.c @@ -8,7 +8,7 @@ #include "fsl_power.h" /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power_no_lib" +#define FSL_COMPONENT_ID "platform.drivers.power" #endif /******************************************************************************* * Definitions diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC822/LPC822_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC822/LPC822_features.h index f2e5cc656..15e10427e 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC822/LPC822_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC822/LPC822_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -209,8 +209,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC822_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC824/LPC824_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC824/LPC824_features.h index 05c9657b1..cb36d3e71 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC824/LPC824_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC824/LPC824_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -209,8 +209,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC824_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC824/drivers/fsl_power.c b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC824/drivers/fsl_power.c index 8a2de409b..7b880858c 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC824/drivers/fsl_power.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC824/drivers/fsl_power.c @@ -8,7 +8,7 @@ #include "fsl_power.h" /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power_no_lib" +#define FSL_COMPONENT_ID "platform.drivers.power" #endif /******************************************************************************* diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC832/LPC832_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC832/LPC832_features.h index 1eaf0814f..e3ea28141 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC832/LPC832_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC832/LPC832_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -202,8 +202,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC832_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC834/LPC834_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC834/LPC834_features.h index d119f515b..97f93e7e3 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC834/LPC834_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC834/LPC834_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -202,8 +202,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC834_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC844/LPC844_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC844/LPC844_features.h index 31d999a30..deb2f2aab 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC844/LPC844_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC844/LPC844_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -243,8 +243,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC844_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC845/LPC845_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC845/LPC845_features.h index 7f8cd0368..18ed820a5 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC845/LPC845_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC845/LPC845_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b241212 +** Build: b250801 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2024 NXP +** Copyright 2016-2025 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -302,8 +302,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC845_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC845/drivers/fsl_power.c b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC845/drivers/fsl_power.c index 334ef0423..5917b93f2 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC845/drivers/fsl_power.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC845/drivers/fsl_power.c @@ -8,7 +8,7 @@ #include "fsl_power.h" /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power_no_lib" +#define FSL_COMPONENT_ID "platform.drivers.power" #endif /******************************************************************************* * Definitions diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC864/LPC864_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC864/LPC864_features.h index 901e94dec..8bc4e45fd 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC864/LPC864_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC864/LPC864_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2022-03-15 -** Build: b250322 +** Version: rev. 2.0, 2024-10-29 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,9 @@ ** Initial version. ** - rev. 1.0 (2022-03-15) ** Revesion of Rev. 1. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ @@ -101,10 +104,6 @@ /* @brief GPIOINT clock source. */ #define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1) -/* CRC module features */ - -/* No feature definitions */ - /* DMA module features */ /* @brief Number of channels */ @@ -161,14 +160,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -273,8 +272,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC864_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC865/LPC865_features.h b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC865/LPC865_features.h index 0477ee4e7..e086290bb 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC865/LPC865_features.h +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC865/LPC865_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2022-03-15 -** Build: b250322 +** Version: rev. 2.0, 2024-10-29 +** Build: b250801 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,9 @@ ** Initial version. ** - rev. 1.0 (2022-03-15) ** Revesion of Rev. 1. +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. ** ** ################################################################### */ @@ -101,10 +104,6 @@ /* @brief GPIOINT clock source. */ #define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1) -/* CRC module features */ - -/* No feature definitions */ - /* DMA module features */ /* @brief Number of channels */ @@ -161,14 +160,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -273,8 +272,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _LPC865_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC865/drivers/fsl_power.c b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC865/drivers/fsl_power.c index e4ef68f00..75dcf85fd 100644 --- a/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC865/drivers/fsl_power.c +++ b/mcux/mcux-sdk-ng/devices/LPC/LPC800/LPC865/drivers/fsl_power.c @@ -8,7 +8,7 @@ #include "fsl_power.h" /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power_no_lib" +#define FSL_COMPONENT_ID "platform.drivers.power" #endif /******************************************************************************* * Definitions From 4e6fc9ceaa5b9d2d8fa2bdb47ceb7b93960c6368 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:13:56 +0800 Subject: [PATCH 07/21] hal_nxp: mcux-sdk-ng: Update device/MCX to sdk 25.09.00 Signed-off-by: Zhaoxiang Jin --- .../devices/MCX/MCXA/MCXA132/MCXA132_COMMON.h | 4 +- .../MCX/MCXA/MCXA132/MCXA132_features.h | 28 +- .../devices/MCX/MCXA/MCXA133/MCXA133_COMMON.h | 4 +- .../MCX/MCXA/MCXA133/MCXA133_features.h | 28 +- .../devices/MCX/MCXA/MCXA142/MCXA142_COMMON.h | 4 +- .../MCX/MCXA/MCXA142/MCXA142_features.h | 28 +- .../devices/MCX/MCXA/MCXA143/MCXA143_COMMON.h | 4 +- .../MCX/MCXA/MCXA143/MCXA143_features.h | 28 +- .../devices/MCX/MCXA/MCXA144/MCXA144_COMMON.h | 4 +- .../MCX/MCXA/MCXA144/MCXA144_features.h | 36 +- .../devices/MCX/MCXA/MCXA145/MCXA145_COMMON.h | 4 +- .../MCX/MCXA/MCXA145/MCXA145_features.h | 36 +- .../devices/MCX/MCXA/MCXA146/MCXA146_COMMON.h | 4 +- .../MCX/MCXA/MCXA146/MCXA146_features.h | 36 +- .../devices/MCX/MCXA/MCXA152/MCXA152_COMMON.h | 4 +- .../MCX/MCXA/MCXA152/MCXA152_features.h | 28 +- .../devices/MCX/MCXA/MCXA153/MCXA153_COMMON.h | 4 +- .../MCX/MCXA/MCXA153/MCXA153_features.h | 28 +- .../MCX/MCXA/MCXA153/drivers/fsl_clock.c | 37 +- .../MCX/MCXA/MCXA153/drivers/fsl_clock.h | 16 +- .../MCX/MCXA/MCXA153/drivers/fsl_reset.h | 8 + .../devices/MCX/MCXA/MCXA154/MCXA154_COMMON.h | 4 +- .../MCX/MCXA/MCXA154/MCXA154_features.h | 36 +- .../devices/MCX/MCXA/MCXA155/MCXA155_COMMON.h | 4 +- .../MCX/MCXA/MCXA155/MCXA155_features.h | 36 +- .../devices/MCX/MCXA/MCXA156/MCXA156_COMMON.h | 4 +- .../MCX/MCXA/MCXA156/MCXA156_features.h | 36 +- .../MCX/MCXA/MCXA156/drivers/fsl_clock.c | 37 +- .../MCX/MCXA/MCXA156/drivers/fsl_clock.h | 16 +- .../devices/MCX/MCXA/MCXA175/CMakeLists.txt | 11 + .../devices/MCX/MCXA/MCXA175/MCXA175.h | 93 + .../devices/MCX/MCXA/MCXA175/MCXA175_COMMON.h | 872 +++ .../MCX/MCXA/MCXA175/MCXA175_features.h | 945 +++ .../MCX/MCXA/MCXA175/fsl_device_registers.h | 26 + .../MCX/MCXA/MCXA175/startup_MCXA175.c | 1464 ++++ .../MCX/MCXA/MCXA175/startup_MCXA175.cpp | 1464 ++++ .../devices/MCX/MCXA/MCXA175/system_MCXA175.c | 112 + .../devices/MCX/MCXA/MCXA175/system_MCXA175.h | 113 + .../devices/MCX/MCXA/MCXA175/variable.cmake | 15 + .../devices/MCX/MCXA/MCXA176/CMakeLists.txt | 11 + .../devices/MCX/MCXA/MCXA176/MCXA176.h | 93 + .../devices/MCX/MCXA/MCXA176/MCXA176_COMMON.h | 872 +++ .../MCX/MCXA/MCXA176/MCXA176_features.h | 945 +++ .../MCX/MCXA/MCXA176/fsl_device_registers.h | 26 + .../MCX/MCXA/MCXA176/startup_MCXA176.c | 1464 ++++ .../MCX/MCXA/MCXA176/startup_MCXA176.cpp | 1464 ++++ .../devices/MCX/MCXA/MCXA176/system_MCXA176.c | 112 + .../devices/MCX/MCXA/MCXA176/system_MCXA176.h | 113 + .../devices/MCX/MCXA/MCXA176/variable.cmake | 15 + .../devices/MCX/MCXA/MCXA185/CMakeLists.txt | 11 + .../devices/MCX/MCXA/MCXA185/MCXA185.h | 94 + .../devices/MCX/MCXA/MCXA185/MCXA185_COMMON.h | 896 +++ .../MCX/MCXA/MCXA185/MCXA185_features.h | 964 +++ .../MCX/MCXA/MCXA185/fsl_device_registers.h | 26 + .../MCX/MCXA/MCXA185/startup_MCXA185.c | 1472 ++++ .../MCX/MCXA/MCXA185/startup_MCXA185.cpp | 1472 ++++ .../devices/MCX/MCXA/MCXA185/system_MCXA185.c | 112 + .../devices/MCX/MCXA/MCXA185/system_MCXA185.h | 113 + .../devices/MCX/MCXA/MCXA185/variable.cmake | 15 + .../devices/MCX/MCXA/MCXA186/CMakeLists.txt | 11 + .../devices/MCX/MCXA/MCXA186/MCXA186.h | 94 + .../devices/MCX/MCXA/MCXA186/MCXA186_COMMON.h | 896 +++ .../MCX/MCXA/MCXA186/MCXA186_features.h | 964 +++ .../MCX/MCXA/MCXA186/fsl_device_registers.h | 26 + .../MCX/MCXA/MCXA186/startup_MCXA186.c | 1472 ++++ .../MCX/MCXA/MCXA186/startup_MCXA186.cpp | 1472 ++++ .../devices/MCX/MCXA/MCXA186/system_MCXA186.c | 112 + .../devices/MCX/MCXA/MCXA186/system_MCXA186.h | 113 + .../devices/MCX/MCXA/MCXA186/variable.cmake | 15 + .../devices/MCX/MCXA/MCXA255/CMakeLists.txt | 11 + .../devices/MCX/MCXA/MCXA255/MCXA255.h | 97 + .../devices/MCX/MCXA/MCXA255/MCXA255_COMMON.h | 912 +++ .../MCX/MCXA/MCXA255/MCXA255_features.h | 972 +++ .../MCX/MCXA/MCXA255/fsl_device_registers.h | 26 + .../MCX/MCXA/MCXA255/startup_MCXA255.c | 1464 ++++ .../MCX/MCXA/MCXA255/startup_MCXA255.cpp | 1464 ++++ .../devices/MCX/MCXA/MCXA255/system_MCXA255.c | 112 + .../devices/MCX/MCXA/MCXA255/system_MCXA255.h | 113 + .../devices/MCX/MCXA/MCXA255/variable.cmake | 15 + .../devices/MCX/MCXA/MCXA256/CMakeLists.txt | 11 + .../devices/MCX/MCXA/MCXA256/MCXA256.h | 97 + .../devices/MCX/MCXA/MCXA256/MCXA256_COMMON.h | 912 +++ .../MCX/MCXA/MCXA256/MCXA256_features.h | 972 +++ .../MCX/MCXA/MCXA256/fsl_device_registers.h | 26 + .../MCX/MCXA/MCXA256/startup_MCXA256.c | 1464 ++++ .../MCX/MCXA/MCXA256/startup_MCXA256.cpp | 1464 ++++ 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.../MCX/MCXA/MCXA344/startup_MCXA344.cpp | 1464 ++++ .../devices/MCX/MCXA/MCXA344/system_MCXA344.c | 115 + .../devices/MCX/MCXA/MCXA344/system_MCXA344.h | 116 + .../devices/MCX/MCXA/MCXA344/variable.cmake | 14 + .../devices/MCX/MCXA/MCXA345/CMakeLists.txt | 2 +- .../devices/MCX/MCXA/MCXA345/MCXA345.h | 4 +- .../devices/MCX/MCXA/MCXA345/MCXA345_COMMON.h | 38 +- .../MCX/MCXA/MCXA345/MCXA345_features.h | 283 +- .../MCX/MCXA/MCXA345/startup_MCXA345.c | 22 +- .../MCX/MCXA/MCXA345/startup_MCXA345.cpp | 22 +- .../devices/MCX/MCXA/MCXA345/system_MCXA345.c | 2 +- .../devices/MCX/MCXA/MCXA345/system_MCXA345.h | 2 +- .../devices/MCX/MCXA/MCXA345/variable.cmake | 2 +- .../devices/MCX/MCXA/MCXA346/CMakeLists.txt | 2 +- .../devices/MCX/MCXA/MCXA346/MCXA346.h | 4 +- .../devices/MCX/MCXA/MCXA346/MCXA346_COMMON.h | 38 +- .../MCX/MCXA/MCXA346/MCXA346_features.h | 283 +- .../MCX/MCXA/MCXA346/drivers/CMakeLists.txt | 4 +- .../MCX/MCXA/MCXA346/drivers/fsl_clock.c | 128 +- .../MCX/MCXA/MCXA346/drivers/fsl_clock.h | 44 +- .../MCX/MCXA/MCXA346/drivers/fsl_edma_soc.c | 2 +- .../MCX/MCXA/MCXA346/drivers/fsl_edma_soc.h | 2 +- .../drivers/fsl_inputmux_connections.h | 4 +- .../MCX/MCXA/MCXA346/drivers/fsl_reset.c | 2 +- .../MCX/MCXA/MCXA346/drivers/fsl_reset.h | 4 +- .../MCX/MCXA/MCXA346/drivers/fsl_trdc_soc.h | 2 +- .../MCX/MCXA/MCXA346/startup_MCXA346.c | 22 +- .../MCX/MCXA/MCXA346/startup_MCXA346.cpp | 22 +- .../devices/MCX/MCXA/MCXA346/system_MCXA346.c | 2 +- .../devices/MCX/MCXA/MCXA346/system_MCXA346.h | 2 +- .../devices/MCX/MCXA/MCXA346/variable.cmake | 2 +- .../devices/MCX/MCXA/MCXA355/CMakeLists.txt | 11 + .../devices/MCX/MCXA/MCXA355/MCXA355.h | 91 + .../devices/MCX/MCXA/MCXA355/MCXA355_COMMON.h | 876 +++ .../MCX/MCXA/MCXA355/MCXA355_features.h | 858 +++ .../MCX/MCXA/MCXA355/fsl_device_registers.h | 26 + .../MCX/MCXA/MCXA355/startup_MCXA355.c | 1464 ++++ .../MCX/MCXA/MCXA355/startup_MCXA355.cpp | 1464 ++++ .../devices/MCX/MCXA/MCXA355/system_MCXA355.c | 112 + .../devices/MCX/MCXA/MCXA355/system_MCXA355.h | 113 + .../devices/MCX/MCXA/MCXA355/variable.cmake | 15 + .../devices/MCX/MCXA/MCXA356/CMakeLists.txt | 11 + .../devices/MCX/MCXA/MCXA356/MCXA356.h | 91 + .../devices/MCX/MCXA/MCXA356/MCXA356_COMMON.h | 876 +++ .../MCX/MCXA/MCXA356/MCXA356_features.h | 858 +++ .../MCX/MCXA/MCXA356/fsl_device_registers.h | 26 + .../MCX/MCXA/MCXA356/startup_MCXA356.c | 1464 ++++ .../MCX/MCXA/MCXA356/startup_MCXA356.cpp | 1464 ++++ .../devices/MCX/MCXA/MCXA356/system_MCXA356.c | 112 + .../devices/MCX/MCXA/MCXA356/system_MCXA356.h | 113 + .../devices/MCX/MCXA/MCXA356/variable.cmake | 15 + .../devices/MCX/MCXA/MCXA365/CMakeLists.txt | 11 + .../devices/MCX/MCXA/MCXA365/MCXA365.h | 99 + .../devices/MCX/MCXA/MCXA365/MCXA365_COMMON.h | 972 +++ .../MCX/MCXA/MCXA365/MCXA365_features.h | 995 +++ .../MCX/MCXA/MCXA365/fsl_device_registers.h | 26 + .../MCX/MCXA/MCXA365/startup_MCXA365.c | 1472 ++++ .../MCX/MCXA/MCXA365/startup_MCXA365.cpp | 1472 ++++ .../devices/MCX/MCXA/MCXA365/system_MCXA365.c | 112 + .../devices/MCX/MCXA/MCXA365/system_MCXA365.h | 113 + .../devices/MCX/MCXA/MCXA365/variable.cmake | 15 + .../devices/MCX/MCXA/MCXA366/CMakeLists.txt | 2 +- .../devices/MCX/MCXA/MCXA366/MCXA366.h | 2 +- .../devices/MCX/MCXA/MCXA366/MCXA366_COMMON.h | 2 +- .../MCX/MCXA/MCXA366/MCXA366_features.h | 68 +- .../MCX/MCXA/MCXA366/startup_MCXA366.c | 2 +- .../MCX/MCXA/MCXA366/startup_MCXA366.cpp | 2 +- .../devices/MCX/MCXA/MCXA366/system_MCXA366.c | 2 +- .../devices/MCX/MCXA/MCXA366/system_MCXA366.h | 2 +- .../devices/MCX/MCXA/MCXA366/variable.cmake | 2 +- .../devices/MCX/MCXA/periph2/PERI_ADC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_AOI.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_CAN.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_CDOG.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_CMC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_CRC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_CTIMER.h | 30 +- .../MCX/MCXA/periph2/PERI_DEBUGMAILBOX.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_DIGTMP.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_DMA.h | 36 +- .../devices/MCX/MCXA/periph2/PERI_EIM.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_EQDC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_ERM.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_FLEXIO.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_FMC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_FMU.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_FREQME.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_GLIKEY.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_GPIO.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_I3C.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_INPUTMUX.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_LCD.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_LPCMP.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_LPDAC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_LPI2C.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_LPSPI.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_LPTMR.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_LPUART.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_MAU.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_MRCC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_OPAMP.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_OSTIMER.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_PKC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_PORT.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_PWM.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_RTC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_SCG.h | 33 +- .../devices/MCX/MCXA/periph2/PERI_SGI.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_SMARTDMA.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_SPC.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_SYSCON.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_TRDC.h | 31 +- .../devices/MCX/MCXA/periph2/PERI_TRNG.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_UDF.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_USB.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_UTICK.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_VBAT.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_WAKETIMER.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_WUU.h | 30 +- .../devices/MCX/MCXA/periph2/PERI_WWDT.h | 30 +- .../devices/MCX/MCXA/periph3/PERI_ADC.h | 1018 +++ .../devices/MCX/MCXA/periph3/PERI_AOI.h | 322 + .../devices/MCX/MCXA/periph3/PERI_CAN.h | 2255 ++++++ .../devices/MCX/MCXA/periph3/PERI_CDOG.h | 472 ++ .../devices/MCX/MCXA/periph3/PERI_CMC.h | 767 ++ .../devices/MCX/MCXA/periph3/PERI_CRC.h | 404 ++ .../devices/MCX/MCXA/periph3/PERI_CTIMER.h | 681 ++ .../MCX/MCXA/periph3/PERI_DEBUGMAILBOX.h | 225 + .../devices/MCX/MCXA/periph3/PERI_DMA.h | 1035 +++ .../devices/MCX/MCXA/periph3/PERI_EIM.h | 254 + .../devices/MCX/MCXA/periph3/PERI_EQDC.h | 1013 +++ .../devices/MCX/MCXA/periph3/PERI_ERM.h | 300 + .../devices/MCX/MCXA/periph3/PERI_FMC.h | 264 + .../devices/MCX/MCXA/periph3/PERI_FMU.h | 345 + .../devices/MCX/MCXA/periph3/PERI_FREQME.h | 336 + .../devices/MCX/MCXA/periph3/PERI_GLIKEY.h | 322 + .../devices/MCX/MCXA/periph3/PERI_GPIO.h | 2662 +++++++ .../devices/MCX/MCXA/periph3/PERI_INPUTMUX.h | 5123 ++++++++++++++ .../devices/MCX/MCXA/periph3/PERI_LPCMP.h | 821 +++ .../devices/MCX/MCXA/periph3/PERI_LPI2C.h | 1428 ++++ .../devices/MCX/MCXA/periph3/PERI_LPSPI.h | 860 +++ .../devices/MCX/MCXA/periph3/PERI_LPTMR.h | 279 + .../devices/MCX/MCXA/periph3/PERI_LPUART.h | 1133 +++ .../devices/MCX/MCXA/periph3/PERI_MAU.h | 598 ++ .../devices/MCX/MCXA/periph3/PERI_MRCC.h | 2600 +++++++ .../devices/MCX/MCXA/periph3/PERI_OPAMP.h | 204 + .../devices/MCX/MCXA/periph3/PERI_OSTIMER.h | 233 + .../devices/MCX/MCXA/periph3/PERI_PORT.h | 602 ++ .../devices/MCX/MCXA/periph3/PERI_PWM.h | 1355 ++++ .../devices/MCX/MCXA/periph3/PERI_RTC.h | 358 + .../devices/MCX/MCXA/periph3/PERI_SCG.h | 720 ++ .../devices/MCX/MCXA/periph3/PERI_SMARTDMA.h | 253 + .../devices/MCX/MCXA/periph3/PERI_SPC.h | 818 +++ .../devices/MCX/MCXA/periph3/PERI_SYSCON.h | 1337 ++++ .../devices/MCX/MCXA/periph3/PERI_TRDC.h | 904 +++ .../devices/MCX/MCXA/periph3/PERI_UTICK.h | 310 + .../devices/MCX/MCXA/periph3/PERI_VBAT.h | 234 + .../devices/MCX/MCXA/periph3/PERI_WAKETIMER.h | 189 + .../devices/MCX/MCXA/periph3/PERI_WUU.h | 1573 +++++ .../devices/MCX/MCXA/periph3/PERI_WWDT.h | 245 + .../devices/MCX/MCXA/periph5/PERI_ADC.h | 1051 +++ .../devices/MCX/MCXA/periph5/PERI_AOI.h | 355 + .../devices/MCX/MCXA/periph5/PERI_CAN.h | 2288 ++++++ .../devices/MCX/MCXA/periph5/PERI_CDOG.h | 505 ++ .../devices/MCX/MCXA/periph5/PERI_CMC.h | 848 +++ .../devices/MCX/MCXA/periph5/PERI_CRC.h | 437 ++ .../devices/MCX/MCXA/periph5/PERI_CTIMER.h | 714 ++ .../MCX/MCXA/periph5/PERI_DEBUGMAILBOX.h | 258 + .../devices/MCX/MCXA/periph5/PERI_DIGTMP.h | 959 +++ .../devices/MCX/MCXA/periph5/PERI_DMA.h | 1089 +++ .../devices/MCX/MCXA/periph5/PERI_EIM.h | 287 + .../devices/MCX/MCXA/periph5/PERI_EQDC.h | 1046 +++ .../devices/MCX/MCXA/periph5/PERI_ERM.h | 333 + .../devices/MCX/MCXA/periph5/PERI_FLEXIO.h | 945 +++ .../devices/MCX/MCXA/periph5/PERI_FMC.h | 309 + .../devices/MCX/MCXA/periph5/PERI_FMU.h | 378 + .../devices/MCX/MCXA/periph5/PERI_FREQME.h | 369 + .../devices/MCX/MCXA/periph5/PERI_GLIKEY.h | 355 + .../devices/MCX/MCXA/periph5/PERI_GPIO.h | 2695 +++++++ .../devices/MCX/MCXA/periph5/PERI_I3C.h | 2513 +++++++ .../devices/MCX/MCXA/periph5/PERI_INPUTMUX.h | 6279 +++++++++++++++++ .../devices/MCX/MCXA/periph5/PERI_LCD.h | 1434 ++++ .../devices/MCX/MCXA/periph5/PERI_LPCMP.h | 854 +++ .../devices/MCX/MCXA/periph5/PERI_LPDAC.h | 532 ++ .../devices/MCX/MCXA/periph5/PERI_LPI2C.h | 1461 ++++ .../devices/MCX/MCXA/periph5/PERI_LPSPI.h | 893 +++ .../devices/MCX/MCXA/periph5/PERI_LPTMR.h | 312 + .../devices/MCX/MCXA/periph5/PERI_LPUART.h | 1166 +++ .../devices/MCX/MCXA/periph5/PERI_MRCC.h | 3710 ++++++++++ .../devices/MCX/MCXA/periph5/PERI_OPAMP.h | 237 + .../devices/MCX/MCXA/periph5/PERI_OSTIMER.h | 266 + .../devices/MCX/MCXA/periph5/PERI_PKC.h | 657 ++ .../devices/MCX/MCXA/periph5/PERI_PORT.h | 635 ++ .../devices/MCX/MCXA/periph5/PERI_PWM.h | 1388 ++++ .../devices/MCX/MCXA/periph5/PERI_RTC.h | 391 + .../devices/MCX/MCXA/periph5/PERI_SCG.h | 1120 +++ .../devices/MCX/MCXA/periph5/PERI_SGI.h | 1562 ++++ .../devices/MCX/MCXA/periph5/PERI_SMARTDMA.h | 286 + .../devices/MCX/MCXA/periph5/PERI_SPC.h | 683 ++ .../devices/MCX/MCXA/periph5/PERI_SYSCON.h | 1507 ++++ .../devices/MCX/MCXA/periph5/PERI_TRDC.h | 937 +++ .../devices/MCX/MCXA/periph5/PERI_TRNG.h | 1162 +++ .../devices/MCX/MCXA/periph5/PERI_UDF.h | 263 + .../devices/MCX/MCXA/periph5/PERI_USB.h | 1490 ++++ .../devices/MCX/MCXA/periph5/PERI_UTICK.h | 343 + .../devices/MCX/MCXA/periph5/PERI_VBAT.h | 267 + .../devices/MCX/MCXA/periph5/PERI_WAKETIMER.h | 222 + .../devices/MCX/MCXA/periph5/PERI_WUU.h | 1622 +++++ .../devices/MCX/MCXA/periph5/PERI_WWDT.h | 278 + .../devices/MCX/MCXA/periph_mapping.md | 5 +- .../MCX/MCXC/MCXC041/MCXC041_features.h | 28 +- .../MCX/MCXC/MCXC141/MCXC141_features.h | 28 +- .../MCX/MCXC/MCXC142/MCXC142_features.h | 28 +- .../devices/MCX/MCXC/MCXC143/MCXC143.h | 2 +- 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.../devices/MCX/MCXE/periph4/PERI_PMC.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_PRAMC.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_RTC.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_SDA_AP.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_SIRC.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_SIUL2.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_STCU.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_STM.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_SWT.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_SXOSC.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_TEMPSENSE.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_TRGMUX.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_TSPC.h | 10 +- .../MCX/MCXE/periph4/PERI_VIRT_WRAPPER.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_WKPU.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_XBIC.h | 10 +- .../devices/MCX/MCXE/periph4/PERI_XRDC.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_ADC.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_BCTU.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_CAN.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_CMU_FC.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_CMU_FM.h | 10 +- .../MCX/MCXE/periph5/PERI_CONFIGURATION.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_CRC.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_DCM.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_DCM_GPR.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_DMA.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_DMAMUX.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_EIM.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_EMIOS.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_ERM.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_FCCU.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_FIRC.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_FLASH.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_FLEXIO.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_FXOSC.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_INTM.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_JDC.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_LCU.h | 10 +- .../devices/MCX/MCXE/periph5/PERI_LPCMP.h | 10 +- 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.../MCX/MCXL/MCXL254/system_MCXL254_cm33.h | 12 +- .../devices/MCX/MCXL/MCXL254/variable.cmake | 16 + .../MCX/MCXL/MCXL255/MCXL255_cm0plus.h | 12 +- .../MCX/MCXL/MCXL255/MCXL255_cm0plus_COMMON.h | 68 +- .../MCXL/MCXL255/MCXL255_cm0plus_features.h | 84 +- .../devices/MCX/MCXL/MCXL255/MCXL255_cm33.h | 12 +- .../MCX/MCXL/MCXL255/MCXL255_cm33_COMMON.h | 169 +- .../MCX/MCXL/MCXL255/MCXL255_cm33_features.h | 183 +- .../MCX/MCXL/MCXL255/drivers/CMakeLists.txt | 22 +- .../MCX/MCXL/MCXL255/drivers/fsl_advc.c | 303 + .../MCX/MCXL/MCXL255/drivers/fsl_advc.h | 137 + .../MCX/MCXL/MCXL255/drivers/fsl_clock.c | 388 +- .../MCX/MCXL/MCXL255/drivers/fsl_clock.h | 105 +- .../MCX/MCXL/MCXL255/drivers/fsl_power.c | 1774 +++-- .../MCX/MCXL/MCXL255/drivers/fsl_power.h | 1130 ++- .../MCX/MCXL/MCXL255/drivers/fsl_reset.c | 4 +- .../MCX/MCXL/MCXL255/drivers/fsl_reset.h | 53 +- .../MCX/MCXL/MCXL255/system_MCXL255_cm0plus.c | 12 +- .../MCX/MCXL/MCXL255/system_MCXL255_cm0plus.h | 12 +- .../MCX/MCXL/MCXL255/system_MCXL255_cm33.c | 12 +- .../MCX/MCXL/MCXL255/system_MCXL255_cm33.h | 12 +- .../devices/MCX/MCXL/periph_L2/PERI_ADC.h | 14 +- .../devices/MCX/MCXL/periph_L2/PERI_AHBSC.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_AOI.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_ATX.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_CDOG.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_CGU.h | 362 +- .../devices/MCX/MCXL/periph_L2/PERI_CMC.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_CRC.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_CTIMER.h | 10 +- .../MCX/MCXL/periph_L2/PERI_DEBUGMAILBOX.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_DMA.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_ERM.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_FMC.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_FMU.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_FMUTEST.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_FREQME.h | 10 +- .../devices/MCX/MCXL/periph_L2/PERI_GLIKEY.h | 10 +- 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.../devices/MCX/MCXN/MCXN247/MCXN247_COMMON.h | 3329 +++++++++ .../MCX/MCXN/MCXN247/MCXN247_features.h | 1072 +++ .../MCX/MCXN/MCXN247/fsl_device_registers.h | 26 + .../devices/MCX/MCXN/MCXN247/system_MCXN247.c | 141 + .../devices/MCX/MCXN/MCXN247/system_MCXN247.h | 111 + .../devices/MCX/MCXN/MCXN247/variable.cmake | 13 + .../devices/MCX/MCXN/MCXN526/CMakeLists.txt | 12 + .../MCX/MCXN/MCXN526/MCXN526_cm33_core0.h | 119 + .../MCXN/MCXN526/MCXN526_cm33_core0_COMMON.h | 3368 +++++++++ .../MCXN526/MCXN526_cm33_core0_features.h | 1011 +++ .../MCX/MCXN/MCXN526/MCXN526_cm33_core1.h | 119 + .../MCXN/MCXN526/MCXN526_cm33_core1_COMMON.h | 3368 +++++++++ .../MCXN526/MCXN526_cm33_core1_features.h | 1004 +++ .../MCXN/MCXN526/cm33_core0/variable.cmake | 9 + .../MCXN/MCXN526/cm33_core1/variable.cmake | 8 + .../MCX/MCXN/MCXN526/fsl_device_registers.h | 28 + .../MCXN/MCXN526/system_MCXN526_cm33_core0.c | 140 + .../MCXN/MCXN526/system_MCXN526_cm33_core0.h | 109 + .../MCXN/MCXN526/system_MCXN526_cm33_core1.c | 134 + .../MCXN/MCXN526/system_MCXN526_cm33_core1.h | 109 + .../devices/MCX/MCXN/MCXN526/variable.cmake | 19 + .../devices/MCX/MCXN/MCXN527/CMakeLists.txt | 12 + .../MCX/MCXN/MCXN527/MCXN527_cm33_core0.h | 120 + .../MCXN/MCXN527/MCXN527_cm33_core0_COMMON.h | 3369 +++++++++ .../MCXN527/MCXN527_cm33_core0_features.h | 1011 +++ .../MCX/MCXN/MCXN527/MCXN527_cm33_core1.h | 120 + .../MCXN/MCXN527/MCXN527_cm33_core1_COMMON.h | 3369 +++++++++ .../MCXN527/MCXN527_cm33_core1_features.h | 1004 +++ .../MCXN/MCXN527/cm33_core0/variable.cmake | 9 + .../MCXN/MCXN527/cm33_core1/variable.cmake | 8 + .../MCX/MCXN/MCXN527/fsl_device_registers.h | 28 + .../MCXN/MCXN527/system_MCXN527_cm33_core0.c | 141 + .../MCXN/MCXN527/system_MCXN527_cm33_core0.h | 110 + .../MCXN/MCXN527/system_MCXN527_cm33_core1.c | 135 + .../MCXN/MCXN527/system_MCXN527_cm33_core1.h | 110 + .../devices/MCX/MCXN/MCXN527/variable.cmake | 19 + .../devices/MCX/MCXN/MCXN536/CMakeLists.txt | 12 + .../MCX/MCXN/MCXN536/MCXN536_cm33_core0.h | 121 + .../MCXN/MCXN536/MCXN536_cm33_core0_COMMON.h | 3384 +++++++++ .../MCXN536/MCXN536_cm33_core0_features.h | 1165 +++ .../MCX/MCXN/MCXN536/MCXN536_cm33_core1.h | 121 + .../MCXN/MCXN536/MCXN536_cm33_core1_COMMON.h | 3384 +++++++++ .../MCXN536/MCXN536_cm33_core1_features.h | 1158 +++ .../MCXN/MCXN536/cm33_core0/variable.cmake | 9 + .../MCXN/MCXN536/cm33_core1/variable.cmake | 8 + .../MCX/MCXN/MCXN536/fsl_device_registers.h | 28 + .../MCXN/MCXN536/system_MCXN536_cm33_core0.c | 142 + .../MCXN/MCXN536/system_MCXN536_cm33_core0.h | 111 + .../MCXN/MCXN536/system_MCXN536_cm33_core1.c | 136 + .../MCXN/MCXN536/system_MCXN536_cm33_core1.h | 111 + .../devices/MCX/MCXN/MCXN536/variable.cmake | 19 + .../devices/MCX/MCXN/MCXN537/CMakeLists.txt | 12 + .../MCX/MCXN/MCXN537/MCXN537_cm33_core0.h | 121 + .../MCXN/MCXN537/MCXN537_cm33_core0_COMMON.h | 3384 +++++++++ .../MCXN537/MCXN537_cm33_core0_features.h | 1165 +++ .../MCX/MCXN/MCXN537/MCXN537_cm33_core1.h | 121 + .../MCXN/MCXN537/MCXN537_cm33_core1_COMMON.h | 3384 +++++++++ .../MCXN537/MCXN537_cm33_core1_features.h | 1158 +++ .../MCXN/MCXN537/cm33_core0/variable.cmake | 9 + .../MCXN/MCXN537/cm33_core1/variable.cmake | 8 + .../MCX/MCXN/MCXN537/fsl_device_registers.h | 28 + .../MCXN/MCXN537/system_MCXN537_cm33_core0.c | 142 + .../MCXN/MCXN537/system_MCXN537_cm33_core0.h | 111 + .../MCXN/MCXN537/system_MCXN537_cm33_core1.c | 136 + .../MCXN/MCXN537/system_MCXN537_cm33_core1.h | 111 + .../devices/MCX/MCXN/MCXN537/variable.cmake | 19 + .../devices/MCX/MCXN/MCXN546/CMakeLists.txt | 1 + .../MCX/MCXN/MCXN546/MCXN546_cm33_core0.h | 5 +- .../MCXN/MCXN546/MCXN546_cm33_core0_COMMON.h | 179 +- .../MCXN546/MCXN546_cm33_core0_features.h | 110 +- .../MCX/MCXN/MCXN546/MCXN546_cm33_core1.h | 5 +- .../MCXN/MCXN546/MCXN546_cm33_core1_COMMON.h | 181 +- .../MCXN546/MCXN546_cm33_core1_features.h | 110 +- .../MCX/MCXN/MCXN546/fsl_device_registers.h | 4 +- .../MCXN/MCXN546/system_MCXN546_cm33_core0.c | 5 +- .../MCXN/MCXN546/system_MCXN546_cm33_core0.h | 5 +- .../MCXN/MCXN546/system_MCXN546_cm33_core1.c | 5 +- .../MCXN/MCXN546/system_MCXN546_cm33_core1.h | 5 +- .../devices/MCX/MCXN/MCXN547/CMakeLists.txt | 1 + .../MCX/MCXN/MCXN547/MCXN547_cm33_core0.h | 5 +- .../MCXN/MCXN547/MCXN547_cm33_core0_COMMON.h | 179 +- .../MCXN547/MCXN547_cm33_core0_features.h | 110 +- .../MCX/MCXN/MCXN547/MCXN547_cm33_core1.h | 5 +- .../MCXN/MCXN547/MCXN547_cm33_core1_COMMON.h | 181 +- .../MCXN547/MCXN547_cm33_core1_features.h | 110 +- .../MCX/MCXN/MCXN547/fsl_device_registers.h | 4 +- .../MCXN/MCXN547/system_MCXN547_cm33_core0.c | 5 +- .../MCXN/MCXN547/system_MCXN547_cm33_core0.h | 5 +- .../MCXN/MCXN547/system_MCXN547_cm33_core1.c | 5 +- .../MCXN/MCXN547/system_MCXN547_cm33_core1.h | 5 +- .../devices/MCX/MCXN/MCXN556S/CMakeLists.txt | 12 + .../MCX/MCXN/MCXN556S/MCXN556S_cm33_core0.h | 122 + .../MCXN556S/MCXN556S_cm33_core0_COMMON.h | 3531 +++++++++ .../MCXN556S/MCXN556S_cm33_core0_features.h | 1207 ++++ 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.../MCX/MCXW/periph4/PERI_FLASH_NMPA.h | 8 +- .../MCX/MCXW/periph4/PERI_FLASH_ROMPATCH.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_FLEXCOMM.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_FMU.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_GINT.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_GPIO.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_HASHCRYPT.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_I2C.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_INPUTMUX.h | 10 +- .../devices/MCX/MCXW/periph4/PERI_IOCON.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_MRT.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_NPX.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_OSTIMER.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_PINT.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_PLU.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_PMC.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_PUF.h | 8 +- .../MCX/MCXW/periph4/PERI_PUF_SRAM_CTRL.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_RADIO.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_ROMCP.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_RTC.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_SCT.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_SPI.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_SPIFI.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_SYSCON.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_SYSCTL.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_TRNG.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_USART.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_UTICK.h | 8 +- .../devices/MCX/MCXW/periph4/PERI_WWDT.h | 8 +- 1151 files changed, 241550 insertions(+), 11771 deletions(-) create mode 100644 mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/CMakeLists.txt create mode 100644 mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/MCXA175.h create mode 100644 mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/MCXA175_COMMON.h create mode 100644 mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/MCXA175_features.h create mode 100644 mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/fsl_device_registers.h create mode 100644 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a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA132/MCXA132_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA132/MCXA132_COMMON.h index 1d2cc1d59..f2d498b53 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA132/MCXA132_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA132/MCXA132_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXA1 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250704 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA132 @@ -367,6 +367,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA132/MCXA132_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA132/MCXA132_features.h index 3c2b36340..83579c5d2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA132/MCXA132_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA132/MCXA132_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -325,6 +325,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* GLIKEY module features */ @@ -356,14 +358,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (1) /* @brief Has SCL delay after START. */ @@ -442,8 +444,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -486,6 +486,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -625,7 +629,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -647,8 +651,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA132_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA133/MCXA133_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA133/MCXA133_COMMON.h index 0e6d0c33f..b86de1bf5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA133/MCXA133_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA133/MCXA133_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXA1 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250704 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA133 @@ -367,6 +367,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA133/MCXA133_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA133/MCXA133_features.h index 023fe9af0..85db9a7ee 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA133/MCXA133_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA133/MCXA133_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -325,6 +325,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* GLIKEY module features */ @@ -356,14 +358,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (1) /* @brief Has SCL delay after START. */ @@ -442,8 +444,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -486,6 +486,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -625,7 +629,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -647,8 +651,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA133_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA142/MCXA142_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA142/MCXA142_COMMON.h index b5dfea8cc..79ac15301 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA142/MCXA142_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA142/MCXA142_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: MCXA1 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250704 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA142 @@ -368,6 +368,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA142/MCXA142_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA142/MCXA142_features.h index 3afdd6b2a..a1c20a6a4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA142/MCXA142_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA142/MCXA142_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -337,6 +337,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* GLIKEY module features */ @@ -368,14 +370,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (1) /* @brief Has SCL delay after START. */ @@ -454,8 +456,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -498,6 +498,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -662,7 +666,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -684,8 +688,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA142_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA143/MCXA143_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA143/MCXA143_COMMON.h index 8d44bb4a8..b23f8c0fa 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA143/MCXA143_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA143/MCXA143_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: MCXA1 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250704 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA143 @@ -368,6 +368,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA143/MCXA143_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA143/MCXA143_features.h index c1e0e1f8a..e8d96afd7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA143/MCXA143_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA143/MCXA143_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -337,6 +337,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* GLIKEY module features */ @@ -368,14 +370,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (1) /* @brief Has SCL delay after START. */ @@ -454,8 +456,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -498,6 +498,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -662,7 +666,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -684,8 +688,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA143_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA144/MCXA144_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA144/MCXA144_COMMON.h index 476745189..1374493bf 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA144/MCXA144_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA144/MCXA144_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXA18 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250807 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA144 @@ -423,6 +423,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA144/MCXA144_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA144/MCXA144_features.h index 319eddeb9..1c3b7ecf5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA144/MCXA144_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA144/MCXA144_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -244,6 +244,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -376,8 +380,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -406,6 +408,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* PWM module features */ @@ -435,6 +439,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -497,14 +503,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -583,8 +589,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -627,6 +631,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -791,7 +799,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -813,8 +821,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA144_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA145/MCXA145_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA145/MCXA145_COMMON.h index 8ad628a92..9b0d3fbb4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA145/MCXA145_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA145/MCXA145_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXA18 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250807 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA145 @@ -423,6 +423,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA145/MCXA145_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA145/MCXA145_features.h index 8a748faf0..2c325bd6b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA145/MCXA145_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA145/MCXA145_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -254,6 +254,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -386,8 +390,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -416,6 +418,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* PWM module features */ @@ -445,6 +449,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -507,14 +513,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -593,8 +599,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -637,6 +641,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -801,7 +809,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -823,8 +831,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA145_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA146/MCXA146_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA146/MCXA146_COMMON.h index b8b5baab0..f582b0368 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA146/MCXA146_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA146/MCXA146_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXA18 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250807 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA146 @@ -423,6 +423,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA146/MCXA146_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA146/MCXA146_features.h index eca8c4044..40537ab50 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA146/MCXA146_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA146/MCXA146_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -254,6 +254,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -386,8 +390,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -416,6 +418,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* PWM module features */ @@ -445,6 +449,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -507,14 +513,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -593,8 +599,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -637,6 +641,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -801,7 +809,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -823,8 +831,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA146_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA152/MCXA152_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA152/MCXA152_COMMON.h index 3f7b119b9..c7ec352e9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA152/MCXA152_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA152/MCXA152_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: MCXA1 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250704 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA152 @@ -368,6 +368,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA152/MCXA152_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA152/MCXA152_features.h index bace3ea9e..0490800a7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA152/MCXA152_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA152/MCXA152_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -337,6 +337,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* GLIKEY module features */ @@ -368,14 +370,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (1) /* @brief Has SCL delay after START. */ @@ -454,8 +456,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -498,6 +498,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -662,7 +666,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -684,8 +688,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA152_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/MCXA153_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/MCXA153_COMMON.h index 85bc4af3a..7d9315c84 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/MCXA153_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/MCXA153_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: MCXA1 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250704 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA153 @@ -368,6 +368,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/MCXA153_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/MCXA153_features.h index da3aad298..0a5a0d408 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/MCXA153_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/MCXA153_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -337,6 +337,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* GLIKEY module features */ @@ -368,14 +370,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (1) /* @brief Has SCL delay after START. */ @@ -454,8 +456,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -498,6 +498,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -662,7 +666,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -684,8 +688,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA153_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_clock.c index 4b4e995f0..b3fbcf15d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_clock.c @@ -1024,41 +1024,8 @@ uint32_t CLOCK_GetClkoutClkFreq(void) return freq / ((clkdiv & 0xFFU) + 1U); } -/*! brief Return Frequency of Systick Clock - * return Frequency of Systick. - */ -uint32_t CLOCK_GetSystickClkFreq(void) -{ - uint32_t freq = 0U; - uint32_t clksel = (MRCC0->MRCC_SYSTICK_CLKSEL); - uint32_t clkdiv = (MRCC0->MRCC_SYSTICK_CLKDIV); - - if (true == CLOCK_IsDivHalt(clkdiv)) - { - return 0; - } - - switch (clksel) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetClk1MFreq(); - break; - case 2U: - freq = CLOCK_GetClk16KFreq(1); - break; - default: - freq = 0U; - break; - } - - return freq / ((clkdiv & 0xFFU) + 1U); -} - -/*! brief Return Frequency of Systick Clock - * return Frequency of Systick. +/*! brief Return Frequency of WWDT Clock + * return Frequency of WWDT. */ uint32_t CLOCK_GetWwdtClkFreq(void) { diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_clock.h index bdbff39c7..f025e1429 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_clock.h @@ -272,7 +272,6 @@ typedef enum _clock_select_name kCLOCK_SelCMP1_RR = (0x130U), /*!< CMP1_RR clock selection */ kCLOCK_SelTRACE = (0x138U), /*!< TRACE clock selection */ kCLOCK_SelCLKOUT = (0x140U), /*!< CLKOUT clock selection */ - kCLOCK_SelSYSTICK = (0x148U), /*!< SYSTICK clock selection */ kCLOCK_SelSCGSCS = (0x200U), /*!< SCG SCS clock selection */ kCLOCK_SelMax = (0x200U), /*!< MAX clock selection */ } clock_select_name_t; @@ -398,11 +397,6 @@ typedef enum _clock_attach_id kSLOW_CLK_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 6U), /*!< Attach SLOW_CLK to CLKOUT. */ kNONE_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 7U), /*!< Attach NONE to CLKOUT. */ - kCPU_CLK_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 0U), /*!< Attach CPU_CLK to SYSTICK. */ - kCLK_1M_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 1U), /*!< Attach CLK_1M to SYSTICK. */ - kCLK_16K_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 2U), /*!< Attach CLK_16K to SYSTICK. */ - kNONE_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 3U), /*!< Attach NONE to SYSTICK. */ - kNONE_to_NONE = (0xFFFFFFFFU), /*!< Attach NONE to NONE. */ } clock_attach_id_t; @@ -429,7 +423,6 @@ typedef enum _clock_div_name kCLOCK_DivCMP1_RR = (0x134U), /*!< CMP1_RR clock divider */ kCLOCK_DivTRACE = (0x13CU), /*!< TRACE clock divider */ kCLOCK_DivCLKOUT = (0x144U), /*!< CLKOUT clock divider */ - kCLOCK_DivSYSTICK = (0x14CU), /*!< SYSTICK clock divider */ kCLOCK_DivFRO_HF_DIV = (0x154U), /*!< FRO_HF_DIV clock divider */ kCLOCK_DivSLOWCLK = (0x378U), /*!< SLOWCLK clock divider */ kCLOCK_DivAHBCLK = (0x380U), /*!< System clock divider */ @@ -773,13 +766,8 @@ uint32_t CLOCK_GetTraceClkFreq(void); */ uint32_t CLOCK_GetClkoutClkFreq(void); -/*! @brief Return Frequency of Systick Clock - * @return Frequency of Systick. - */ -uint32_t CLOCK_GetSystickClkFreq(void); - -/*! brief Return Frequency of Systick Clock - * return Frequency of Systick. +/*! brief Return Frequency of WWDT Clock + * return Frequency of WWDT. */ uint32_t CLOCK_GetWwdtClkFreq(void); diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_reset.h index f14eb186f..1b01be31a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_reset.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA153/drivers/fsl_reset.h @@ -145,6 +145,14 @@ typedef enum _SYSCON_RSTn { \ kUTICK0_RST_SHIFT_RSTn \ } /* Reset bits for UTICK peripheral */ +#define EIM_RSTS_N \ + { \ + kEIM_RST_SHIFT_RSTn \ + } /* Reset bits for EIM peripheral */ +#define ERM_RSTS_N \ + { \ + kERM_RST_SHIFT_RSTn \ + } /* Reset bits for ERM peripheral */ typedef SYSCON_RSTn_t reset_ip_name_t; diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA154/MCXA154_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA154/MCXA154_COMMON.h index 03d9d87ab..2a7c24b13 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA154/MCXA154_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA154/MCXA154_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXA18 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250807 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA154 @@ -427,6 +427,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA154/MCXA154_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA154/MCXA154_features.h index 6ab78de4b..72b54a0bd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA154/MCXA154_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA154/MCXA154_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -258,6 +258,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -407,8 +411,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -437,6 +439,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* PWM module features */ @@ -466,6 +470,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -528,14 +534,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -614,8 +620,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -658,6 +662,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -839,7 +847,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -861,8 +869,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA154_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA155/MCXA155_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA155/MCXA155_COMMON.h index 5c94a96c5..e233d211b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA155/MCXA155_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA155/MCXA155_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXA18 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250807 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA155 @@ -427,6 +427,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA155/MCXA155_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA155/MCXA155_features.h index 34ee36173..b00250e74 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA155/MCXA155_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA155/MCXA155_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -258,6 +258,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -407,8 +411,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -437,6 +439,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* PWM module features */ @@ -466,6 +470,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -528,14 +534,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -614,8 +620,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -658,6 +662,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -839,7 +847,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -861,8 +869,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA155_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/MCXA156_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/MCXA156_COMMON.h index eaed46dbd..609134001 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/MCXA156_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/MCXA156_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXA18 User manual ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250807 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA156 @@ -427,6 +427,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/MCXA156_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/MCXA156_features.h index 1c06fa203..b1da1c7e7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/MCXA156_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/MCXA156_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -258,6 +258,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -407,8 +411,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -437,6 +439,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* PWM module features */ @@ -466,6 +470,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -528,14 +534,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -614,8 +620,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -658,6 +662,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* TRDC module features */ @@ -839,7 +847,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -861,8 +869,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA156_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/drivers/fsl_clock.c index b4b6a0a03..6acfb40d0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/drivers/fsl_clock.c @@ -1137,41 +1137,8 @@ uint32_t CLOCK_GetClkoutClkFreq(void) return freq / ((clkdiv & 0xFFU) + 1U); } -/*! brief Return Frequency of Systick Clock - * return Frequency of Systick. - */ -uint32_t CLOCK_GetSystickClkFreq(void) -{ - uint32_t freq = 0U; - uint32_t clksel = (MRCC0->MRCC_SYSTICK_CLKSEL); - uint32_t clkdiv = (MRCC0->MRCC_SYSTICK_CLKDIV); - - if (true == CLOCK_IsDivHalt(clkdiv)) - { - return 0; - } - - switch (clksel) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetClk1MFreq(); - break; - case 2U: - freq = CLOCK_GetClk16KFreq(1); - break; - default: - freq = 0U; - break; - } - - return freq / ((clkdiv & 0xFFU) + 1U); -} - -/*! brief Return Frequency of Systick Clock - * return Frequency of Systick. +/*! brief Return Frequency of WWDT Clock + * return Frequency of WWDT. */ uint32_t CLOCK_GetWwdtClkFreq(void) { diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/drivers/fsl_clock.h index 7762fe708..d2d35a31f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA156/drivers/fsl_clock.h @@ -325,7 +325,6 @@ typedef enum _clock_select_name kCLOCK_SelLPI2C3 = (0x188), /*= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA175_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/MCXA175_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/MCXA175_features.h new file mode 100644 index 000000000..44ae4fdf5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/MCXA175_features.h @@ -0,0 +1,945 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA175_FEATURES_H_ +#define _MCXA175_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (5) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (516096) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (0) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA175_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/fsl_device_registers.h new file mode 100644 index 000000000..61008dbd9 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/startup_MCXA175.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/startup_MCXA175.c new file mode 100644 index 000000000..86be1bcc1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/startup_MCXA175.c @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA175 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA175 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/startup_MCXA175.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/startup_MCXA175.cpp new file mode 100644 index 000000000..86be1bcc1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/startup_MCXA175.cpp @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA175 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA175 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/system_MCXA175.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/system_MCXA175.c new file mode 100644 index 000000000..a8ad11189 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/system_MCXA175.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA175 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA175 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/system_MCXA175.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/system_MCXA175.h new file mode 100644 index 000000000..721bd5155 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/system_MCXA175.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA175 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA175 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA175_H_ +#define _SYSTEM_MCXA175_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA175_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/variable.cmake new file mode 100644 index 000000000..7b72cb85f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA175/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA175) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph5) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/CMakeLists.txt new file mode 100644 index 000000000..2f026fc9d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA266/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/MCXA176.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/MCXA176.h new file mode 100644 index 000000000..2c24def44 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/MCXA176.h @@ -0,0 +1,93 @@ +/* +** ################################################################### +** Processors: MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA176 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA176.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA176 + * + * CMSIS Peripheral Access Layer for MCXA176 + */ + +#if !defined(MCXA176_H_) /* Check if memory map has not been already included */ +#define MCXA176_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_USB.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA176_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/MCXA176_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/MCXA176_COMMON.h new file mode 100644 index 000000000..f3c29ff32 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/MCXA176_COMMON.h @@ -0,0 +1,872 @@ +/* +** ################################################################### +** Processors: MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA176 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA176_COMMON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA176 + * + * CMSIS Peripheral Access Layer for MCXA176 + */ + +#if !defined(MCXA176_COMMON_H_) +#define MCXA176_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + Reserved36_IRQn = 20, /**< Reserved interrupt */ + FLEXIO_IRQn = 23, /**< Flexible Input/Output interrupt */ + I3C0_IRQn = 24, /**< Improved Inter Integrated Circuit interrupt 0 */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit 4 interrupt */ + USB0_IRQn = 36, /**< Universal Serial Bus - Full Speed interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + Reserved82_IRQn = 66, /**< Reserved interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit 3 interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + Reserved111_IRQn = 95, /**< Reserved interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ + Reserved126_IRQn = 110, /**< Reserved interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + Reserved129_IRQn = 113, /**< Reserved interrupt */ + Reserved130_IRQn = 114, /**< Reserved interrupt */ + Reserved132_IRQn = 116, /**< Reserved interrupt */ + Reserved133_IRQn = 117, /**< Reserved interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + Reserved137_IRQn = 121 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA176.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA176_SERIES +#define MCXA176_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA176_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO0 base address */ +#define FLEXIO0_BASE (0x40099000u) +/** Peripheral FLEXIO0 base pointer */ +#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO0 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C0 base address */ +#define I3C0_BASE (0x40002000u) +/** Peripheral I3C0 base pointer */ +#define I3C0 ((I3C_Type *)I3C0_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { I3C0_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { I3C0 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1 } + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x400A4000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA176_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/MCXA176_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/MCXA176_features.h new file mode 100644 index 000000000..9cce1a177 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/MCXA176_features.h @@ -0,0 +1,945 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA176_FEATURES_H_ +#define _MCXA176_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (5) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1040384) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (0) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA176_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/fsl_device_registers.h new file mode 100644 index 000000000..1397f93fb --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/startup_MCXA176.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/startup_MCXA176.c new file mode 100644 index 000000000..188a65a9c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/startup_MCXA176.c @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA176 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA176 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/startup_MCXA176.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/startup_MCXA176.cpp new file mode 100644 index 000000000..188a65a9c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/startup_MCXA176.cpp @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA176 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA176 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/system_MCXA176.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/system_MCXA176.c new file mode 100644 index 000000000..1b30eb356 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/system_MCXA176.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA176 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA176 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/system_MCXA176.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/system_MCXA176.h new file mode 100644 index 000000000..c7a0e4fb8 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/system_MCXA176.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA176 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA176 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA176_H_ +#define _SYSTEM_MCXA176_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA176_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/variable.cmake new file mode 100644 index 000000000..f18cad5f4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA176/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA176) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph5) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/CMakeLists.txt new file mode 100644 index 000000000..2f026fc9d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA266/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/MCXA185.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/MCXA185.h new file mode 100644 index 000000000..f34090ebb --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/MCXA185.h @@ -0,0 +1,94 @@ +/* +** ################################################################### +** Processors: MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA185 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA185.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA185 + * + * CMSIS Peripheral Access Layer for MCXA185 + */ + +#if !defined(MCXA185_H_) /* Check if memory map has not been already included */ +#define MCXA185_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LCD.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_USB.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA185_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/MCXA185_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/MCXA185_COMMON.h new file mode 100644 index 000000000..012ab2ad3 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/MCXA185_COMMON.h @@ -0,0 +1,896 @@ +/* +** ################################################################### +** Processors: MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA185 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA185_COMMON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA185 + * + * CMSIS Peripheral Access Layer for MCXA185 + */ + +#if !defined(MCXA185_COMMON_H_) +#define MCXA185_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + CAN1_IRQn = 20, /**< Controller Area Network 1 interrupt */ + FLEXIO_IRQn = 23, /**< Flexible Input/Output interrupt */ + I3C0_IRQn = 24, /**< Improved Inter Integrated Circuit interrupt 0 */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit 4 interrupt */ + USB0_IRQn = 36, /**< Universal Serial Bus - Full Speed interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + Reserved82_IRQn = 66, /**< Reserved interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit 3 interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + LPUART5_IRQn = 95, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ + Reserved126_IRQn = 110, /**< Reserved interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + Reserved129_IRQn = 113, /**< Reserved interrupt */ + Reserved130_IRQn = 114, /**< Reserved interrupt */ + Reserved132_IRQn = 116, /**< Reserved interrupt */ + Reserved133_IRQn = 117, /**< Reserved interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + LCD_IRQn = 121 /**< SLCD frame start interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA185.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA185_SERIES +#define MCXA185_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA185_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x400D0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0, CAN1 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn, CAN1_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO0 base address */ +#define FLEXIO0_BASE (0x40099000u) +/** Peripheral FLEXIO0 base pointer */ +#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO0 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C0 base address */ +#define I3C0_BASE (0x40002000u) +/** Peripheral I3C0 base pointer */ +#define I3C0 ((I3C_Type *)I3C0_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { I3C0_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { I3C0 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LCD - Peripheral instance base addresses */ +/** Peripheral LCD0 base address */ +#define LCD0_BASE (0x400C2000u) +/** Peripheral LCD0 base pointer */ +#define LCD0 ((LCD_Type *)LCD0_BASE) +/** Array initializer of LCD peripheral base addresses */ +#define LCD_BASE_ADDRS { LCD0_BASE } +/** Array initializer of LCD peripheral base pointers */ +#define LCD_BASE_PTRS { LCD0 } +/** Interrupt vectors for the LCD peripheral type */ +#define LCD_IRQS { LCD_IRQn } +/* Backward compatibility */ +#define LCD_WFOVERLAY_WFACCESS8BIT_WF8B_COUNT LCD_WF_ACCESS_WF8BIT_WF8B_COUNT +#define LCD_WFOVERLAY_WFACCESS32BIT_WF_COUNT LCD_WF_ACCESS_WF32BIT_WF_COUNT + + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1 } + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x400DA000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x400A4000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA185_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/MCXA185_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/MCXA185_features.h new file mode 100644 index 000000000..51d333172 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/MCXA185_features.h @@ -0,0 +1,964 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA185_FEATURES_H_ +#define _MCXA185_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* SLCD module features */ + +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (516096) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA185_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/fsl_device_registers.h new file mode 100644 index 000000000..a343020ba --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/startup_MCXA185.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/startup_MCXA185.c new file mode 100644 index 000000000..6a9e77e6e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/startup_MCXA185.c @@ -0,0 +1,1472 @@ +//***************************************************************************** +// MCXA185 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); +WEAK void LCD_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); +void LCD_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA185 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 36 : Controller Area Network 1 interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt + LCD_IRQHandler, // 137: SLCD frame start interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ + CAN1_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +WEAK void LCD_IRQHandler(void) +{ + LCD_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/startup_MCXA185.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/startup_MCXA185.cpp new file mode 100644 index 000000000..6a9e77e6e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/startup_MCXA185.cpp @@ -0,0 +1,1472 @@ +//***************************************************************************** +// MCXA185 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); +WEAK void LCD_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); +void LCD_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA185 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 36 : Controller Area Network 1 interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt + LCD_IRQHandler, // 137: SLCD frame start interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ + CAN1_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +WEAK void LCD_IRQHandler(void) +{ + LCD_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/system_MCXA185.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/system_MCXA185.c new file mode 100644 index 000000000..e3d3dc8bc --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/system_MCXA185.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA185 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA185 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/system_MCXA185.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/system_MCXA185.h new file mode 100644 index 000000000..94c4b5c2a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/system_MCXA185.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA185 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA185 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA185_H_ +#define _SYSTEM_MCXA185_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA185_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/variable.cmake new file mode 100644 index 000000000..745cf1ea9 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA185/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA185) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph5) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/CMakeLists.txt new file mode 100644 index 000000000..2f026fc9d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA266/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/MCXA186.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/MCXA186.h new file mode 100644 index 000000000..b45b5e947 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/MCXA186.h @@ -0,0 +1,94 @@ +/* +** ################################################################### +** Processors: MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA186 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA186.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA186 + * + * CMSIS Peripheral Access Layer for MCXA186 + */ + +#if !defined(MCXA186_H_) /* Check if memory map has not been already included */ +#define MCXA186_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LCD.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_USB.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA186_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/MCXA186_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/MCXA186_COMMON.h new file mode 100644 index 000000000..a5b3afcfe --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/MCXA186_COMMON.h @@ -0,0 +1,896 @@ +/* +** ################################################################### +** Processors: MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA186 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA186_COMMON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA186 + * + * CMSIS Peripheral Access Layer for MCXA186 + */ + +#if !defined(MCXA186_COMMON_H_) +#define MCXA186_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + CAN1_IRQn = 20, /**< Controller Area Network 1 interrupt */ + FLEXIO_IRQn = 23, /**< Flexible Input/Output interrupt */ + I3C0_IRQn = 24, /**< Improved Inter Integrated Circuit interrupt 0 */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit 4 interrupt */ + USB0_IRQn = 36, /**< Universal Serial Bus - Full Speed interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + Reserved82_IRQn = 66, /**< Reserved interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit 3 interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + LPUART5_IRQn = 95, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ + Reserved126_IRQn = 110, /**< Reserved interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + Reserved129_IRQn = 113, /**< Reserved interrupt */ + Reserved130_IRQn = 114, /**< Reserved interrupt */ + Reserved132_IRQn = 116, /**< Reserved interrupt */ + Reserved133_IRQn = 117, /**< Reserved interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + LCD_IRQn = 121 /**< SLCD frame start interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA186.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA186_SERIES +#define MCXA186_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA186_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x400D0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0, CAN1 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn, CAN1_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO0 base address */ +#define FLEXIO0_BASE (0x40099000u) +/** Peripheral FLEXIO0 base pointer */ +#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO0 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C0 base address */ +#define I3C0_BASE (0x40002000u) +/** Peripheral I3C0 base pointer */ +#define I3C0 ((I3C_Type *)I3C0_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { I3C0_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { I3C0 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LCD - Peripheral instance base addresses */ +/** Peripheral LCD0 base address */ +#define LCD0_BASE (0x400C2000u) +/** Peripheral LCD0 base pointer */ +#define LCD0 ((LCD_Type *)LCD0_BASE) +/** Array initializer of LCD peripheral base addresses */ +#define LCD_BASE_ADDRS { LCD0_BASE } +/** Array initializer of LCD peripheral base pointers */ +#define LCD_BASE_PTRS { LCD0 } +/** Interrupt vectors for the LCD peripheral type */ +#define LCD_IRQS { LCD_IRQn } +/* Backward compatibility */ +#define LCD_WFOVERLAY_WFACCESS8BIT_WF8B_COUNT LCD_WF_ACCESS_WF8BIT_WF8B_COUNT +#define LCD_WFOVERLAY_WFACCESS32BIT_WF_COUNT LCD_WF_ACCESS_WF32BIT_WF_COUNT + + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1 } + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x400DA000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x400A4000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA186_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/MCXA186_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/MCXA186_features.h new file mode 100644 index 000000000..6110a8670 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/MCXA186_features.h @@ -0,0 +1,964 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA186_FEATURES_H_ +#define _MCXA186_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* SLCD module features */ + +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1040384) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA186_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/fsl_device_registers.h new file mode 100644 index 000000000..3986e9262 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/startup_MCXA186.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/startup_MCXA186.c new file mode 100644 index 000000000..e8d90570e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/startup_MCXA186.c @@ -0,0 +1,1472 @@ +//***************************************************************************** +// MCXA186 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); +WEAK void LCD_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); +void LCD_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA186 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 36 : Controller Area Network 1 interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt + LCD_IRQHandler, // 137: SLCD frame start interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ + CAN1_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +WEAK void LCD_IRQHandler(void) +{ + LCD_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/startup_MCXA186.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/startup_MCXA186.cpp new file mode 100644 index 000000000..e8d90570e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/startup_MCXA186.cpp @@ -0,0 +1,1472 @@ +//***************************************************************************** +// MCXA186 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); +WEAK void LCD_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); +void LCD_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA186 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 36 : Controller Area Network 1 interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt + LCD_IRQHandler, // 137: SLCD frame start interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ + CAN1_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +WEAK void LCD_IRQHandler(void) +{ + LCD_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/system_MCXA186.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/system_MCXA186.c new file mode 100644 index 000000000..2c639adb5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/system_MCXA186.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA186 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA186 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/system_MCXA186.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/system_MCXA186.h new file mode 100644 index 000000000..7d62d9666 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/system_MCXA186.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA186 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA186 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA186_H_ +#define _SYSTEM_MCXA186_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA186_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/variable.cmake new file mode 100644 index 000000000..a281bc53d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA186/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA186) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph5) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/CMakeLists.txt new file mode 100644 index 000000000..2f026fc9d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA266/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/MCXA255.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/MCXA255.h new file mode 100644 index 000000000..1af340386 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/MCXA255.h @@ -0,0 +1,97 @@ +/* +** ################################################################### +** Processors: MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA255 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA255.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA255 + * + * CMSIS Peripheral Access Layer for MCXA255 + */ + +#if !defined(MCXA255_H_) /* Check if memory map has not been already included */ +#define MCXA255_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SGI.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_TRNG.h" +#include "PERI_UDF.h" +#include "PERI_USB.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA255_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/MCXA255_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/MCXA255_COMMON.h new file mode 100644 index 000000000..f2d5e8c58 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/MCXA255_COMMON.h @@ -0,0 +1,912 @@ +/* +** ################################################################### +** Processors: MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA255 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA255_COMMON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA255 + * + * CMSIS Peripheral Access Layer for MCXA255 + */ + +#if !defined(MCXA255_COMMON_H_) +#define MCXA255_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + Reserved36_IRQn = 20, /**< Reserved interrupt */ + FLEXIO_IRQn = 23, /**< Flexible Input/Output interrupt */ + I3C0_IRQn = 24, /**< Improved Inter Integrated Circuit interrupt 0 */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit 4 interrupt */ + USB0_IRQn = 36, /**< Universal Serial Bus - Full Speed interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + Reserved82_IRQn = 66, /**< Reserved interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit 3 interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + Reserved111_IRQn = 95, /**< Reserved interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ + PKC_IRQn = 110, /**< PKC interrupt */ + SGI_IRQn = 111, /**< SGI interrupt */ + TRNG0_IRQn = 113, /**< True Random Number Generator interrupt */ + SECURE_ERR_IRQn = 114, /**< Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. */ + Reserved132_IRQn = 116, /**< Reserved interrupt */ + Reserved133_IRQn = 117, /**< Reserved interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + Reserved137_IRQn = 121 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA255.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA255_SERIES +#define MCXA255_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA255_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO0 base address */ +#define FLEXIO0_BASE (0x40099000u) +/** Peripheral FLEXIO0 base pointer */ +#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO0 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C0 base address */ +#define I3C0_BASE (0x40002000u) +/** Peripheral I3C0 base pointer */ +#define I3C0 ((I3C_Type *)I3C0_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { I3C0_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { I3C0 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1 } + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PKC - Peripheral instance base addresses */ +/** Peripheral PKC0 base address */ +#define PKC0_BASE (0x400EA000u) +/** Peripheral PKC0 base pointer */ +#define PKC0 ((PKC_Type *)PKC0_BASE) +/** Array initializer of PKC peripheral base addresses */ +#define PKC_BASE_ADDRS { PKC0_BASE } +/** Array initializer of PKC peripheral base pointers */ +#define PKC_BASE_PTRS { PKC0 } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SGI - Peripheral instance base addresses */ +/** Peripheral SGI0 base address */ +#define SGI0_BASE (0x400EB000u) +/** Peripheral SGI0 base pointer */ +#define SGI0 ((SGI_Type *)SGI0_BASE) +/** Array initializer of SGI peripheral base addresses */ +#define SGI_BASE_ADDRS { SGI0_BASE } +/** Array initializer of SGI peripheral base pointers */ +#define SGI_BASE_PTRS { SGI0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TRNG - Peripheral instance base addresses */ +/** Peripheral TRNG0 base address */ +#define TRNG0_BASE (0x400EC000u) +/** Peripheral TRNG0 base pointer */ +#define TRNG0 ((TRNG_Type *)TRNG0_BASE) +/** Array initializer of TRNG peripheral base addresses */ +#define TRNG_BASE_ADDRS { TRNG0_BASE } +/** Array initializer of TRNG peripheral base pointers */ +#define TRNG_BASE_PTRS { TRNG0 } + +/* UDF - Peripheral instance base addresses */ +/** Peripheral UDF0 base address */ +#define UDF0_BASE (0x400ED000u) +/** Peripheral UDF0 base pointer */ +#define UDF0 ((UDF_Type *)UDF0_BASE) +/** Array initializer of UDF peripheral base addresses */ +#define UDF_BASE_ADDRS { UDF0_BASE } +/** Array initializer of UDF peripheral base pointers */ +#define UDF_BASE_PTRS { UDF0 } + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x400A4000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA255_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/MCXA255_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/MCXA255_features.h new file mode 100644 index 000000000..1fc2d4050 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/MCXA255_features.h @@ -0,0 +1,972 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA255_FEATURES_H_ +#define _MCXA255_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (5) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (516096) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (0) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRNG module features */ + +/* @brief TRNG does not support SCR4L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (0) +/* @brief TRNG does not support SCR5L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (0) +/* @brief TRNG does not support SCR6L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) +/* @brief TRNG does not support PKRMAX. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (0) +/* @brief TRNG does not support SAMP mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) +/* @brief TRNG does not support ACC. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) +/* @brief TRNG does not support SBLIM. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (0) +/* @brief TRNG supports reset control. */ +#define FSL_FEATURE_TRNG_HAS_RSTCTL (0) +/* @brief TRNG does not support FOR_CLK mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1) +/* @brief TRNG has two oscillators. */ +#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA255_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/fsl_device_registers.h new file mode 100644 index 000000000..96249b3cd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/startup_MCXA255.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/startup_MCXA255.c new file mode 100644 index 000000000..2669231be --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/startup_MCXA255.c @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA255 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void SGI_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void TRNG0_IRQHandler(void); +WEAK void SECURE_ERR_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void PKC_DriverIRQHandler(void) ALIAS(DefaultISR); +void SGI_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void TRNG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SECURE_ERR_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA255 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + PKC_IRQHandler, // 126: PKC interrupt + SGI_IRQHandler, // 127: SGI interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + TRNG0_IRQHandler, // 129: True Random Number Generator interrupt + SECURE_ERR_IRQHandler, // 130: Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ + PKC_DriverIRQHandler(); +} + +WEAK void SGI_IRQHandler(void) +{ + SGI_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void TRNG0_IRQHandler(void) +{ + TRNG0_DriverIRQHandler(); +} + +WEAK void SECURE_ERR_IRQHandler(void) +{ + SECURE_ERR_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/startup_MCXA255.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/startup_MCXA255.cpp new file mode 100644 index 000000000..2669231be --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/startup_MCXA255.cpp @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA255 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void SGI_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void TRNG0_IRQHandler(void); +WEAK void SECURE_ERR_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void PKC_DriverIRQHandler(void) ALIAS(DefaultISR); +void SGI_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void TRNG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SECURE_ERR_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA255 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + PKC_IRQHandler, // 126: PKC interrupt + SGI_IRQHandler, // 127: SGI interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + TRNG0_IRQHandler, // 129: True Random Number Generator interrupt + SECURE_ERR_IRQHandler, // 130: Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ + PKC_DriverIRQHandler(); +} + +WEAK void SGI_IRQHandler(void) +{ + SGI_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void TRNG0_IRQHandler(void) +{ + TRNG0_DriverIRQHandler(); +} + +WEAK void SECURE_ERR_IRQHandler(void) +{ + SECURE_ERR_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/system_MCXA255.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/system_MCXA255.c new file mode 100644 index 000000000..cca961e57 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/system_MCXA255.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA255 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA255 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/system_MCXA255.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/system_MCXA255.h new file mode 100644 index 000000000..d1b69de2e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/system_MCXA255.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA255 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA255 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA255_H_ +#define _SYSTEM_MCXA255_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA255_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/variable.cmake new file mode 100644 index 000000000..eb2de156c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA255/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA255) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph5) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/CMakeLists.txt new file mode 100644 index 000000000..2f026fc9d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA266/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/MCXA256.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/MCXA256.h new file mode 100644 index 000000000..2948b068e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/MCXA256.h @@ -0,0 +1,97 @@ +/* +** ################################################################### +** Processors: MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA256 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA256.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA256 + * + * CMSIS Peripheral Access Layer for MCXA256 + */ + +#if !defined(MCXA256_H_) /* Check if memory map has not been already included */ +#define MCXA256_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SGI.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_TRNG.h" +#include "PERI_UDF.h" +#include "PERI_USB.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA256_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/MCXA256_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/MCXA256_COMMON.h new file mode 100644 index 000000000..d991a9e61 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/MCXA256_COMMON.h @@ -0,0 +1,912 @@ +/* +** ################################################################### +** Processors: MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA256 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA256_COMMON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA256 + * + * CMSIS Peripheral Access Layer for MCXA256 + */ + +#if !defined(MCXA256_COMMON_H_) +#define MCXA256_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + Reserved36_IRQn = 20, /**< Reserved interrupt */ + FLEXIO_IRQn = 23, /**< Flexible Input/Output interrupt */ + I3C0_IRQn = 24, /**< Improved Inter Integrated Circuit interrupt 0 */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit 4 interrupt */ + USB0_IRQn = 36, /**< Universal Serial Bus - Full Speed interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + Reserved82_IRQn = 66, /**< Reserved interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit 3 interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + Reserved111_IRQn = 95, /**< Reserved interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ + PKC_IRQn = 110, /**< PKC interrupt */ + SGI_IRQn = 111, /**< SGI interrupt */ + TRNG0_IRQn = 113, /**< True Random Number Generator interrupt */ + SECURE_ERR_IRQn = 114, /**< Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. */ + Reserved132_IRQn = 116, /**< Reserved interrupt */ + Reserved133_IRQn = 117, /**< Reserved interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + Reserved137_IRQn = 121 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA256.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA256_SERIES +#define MCXA256_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA256_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO0 base address */ +#define FLEXIO0_BASE (0x40099000u) +/** Peripheral FLEXIO0 base pointer */ +#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO0 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C0 base address */ +#define I3C0_BASE (0x40002000u) +/** Peripheral I3C0 base pointer */ +#define I3C0 ((I3C_Type *)I3C0_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { I3C0_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { I3C0 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1 } + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PKC - Peripheral instance base addresses */ +/** Peripheral PKC0 base address */ +#define PKC0_BASE (0x400EA000u) +/** Peripheral PKC0 base pointer */ +#define PKC0 ((PKC_Type *)PKC0_BASE) +/** Array initializer of PKC peripheral base addresses */ +#define PKC_BASE_ADDRS { PKC0_BASE } +/** Array initializer of PKC peripheral base pointers */ +#define PKC_BASE_PTRS { PKC0 } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SGI - Peripheral instance base addresses */ +/** Peripheral SGI0 base address */ +#define SGI0_BASE (0x400EB000u) +/** Peripheral SGI0 base pointer */ +#define SGI0 ((SGI_Type *)SGI0_BASE) +/** Array initializer of SGI peripheral base addresses */ +#define SGI_BASE_ADDRS { SGI0_BASE } +/** Array initializer of SGI peripheral base pointers */ +#define SGI_BASE_PTRS { SGI0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TRNG - Peripheral instance base addresses */ +/** Peripheral TRNG0 base address */ +#define TRNG0_BASE (0x400EC000u) +/** Peripheral TRNG0 base pointer */ +#define TRNG0 ((TRNG_Type *)TRNG0_BASE) +/** Array initializer of TRNG peripheral base addresses */ +#define TRNG_BASE_ADDRS { TRNG0_BASE } +/** Array initializer of TRNG peripheral base pointers */ +#define TRNG_BASE_PTRS { TRNG0 } + +/* UDF - Peripheral instance base addresses */ +/** Peripheral UDF0 base address */ +#define UDF0_BASE (0x400ED000u) +/** Peripheral UDF0 base pointer */ +#define UDF0 ((UDF_Type *)UDF0_BASE) +/** Array initializer of UDF peripheral base addresses */ +#define UDF_BASE_ADDRS { UDF0_BASE } +/** Array initializer of UDF peripheral base pointers */ +#define UDF_BASE_PTRS { UDF0 } + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x400A4000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA256_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/MCXA256_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/MCXA256_features.h new file mode 100644 index 000000000..2b4b71915 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/MCXA256_features.h @@ -0,0 +1,972 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA256_FEATURES_H_ +#define _MCXA256_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (5) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1040384) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (0) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRNG module features */ + +/* @brief TRNG does not support SCR4L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (0) +/* @brief TRNG does not support SCR5L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (0) +/* @brief TRNG does not support SCR6L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) +/* @brief TRNG does not support PKRMAX. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (0) +/* @brief TRNG does not support SAMP mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) +/* @brief TRNG does not support ACC. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) +/* @brief TRNG does not support SBLIM. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (0) +/* @brief TRNG supports reset control. */ +#define FSL_FEATURE_TRNG_HAS_RSTCTL (0) +/* @brief TRNG does not support FOR_CLK mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1) +/* @brief TRNG has two oscillators. */ +#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA256_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/fsl_device_registers.h new file mode 100644 index 000000000..c13370f2c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/startup_MCXA256.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/startup_MCXA256.c new file mode 100644 index 000000000..24d795620 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/startup_MCXA256.c @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA256 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void SGI_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void TRNG0_IRQHandler(void); +WEAK void SECURE_ERR_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void PKC_DriverIRQHandler(void) ALIAS(DefaultISR); +void SGI_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void TRNG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SECURE_ERR_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA256 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + PKC_IRQHandler, // 126: PKC interrupt + SGI_IRQHandler, // 127: SGI interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + TRNG0_IRQHandler, // 129: True Random Number Generator interrupt + SECURE_ERR_IRQHandler, // 130: Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ + PKC_DriverIRQHandler(); +} + +WEAK void SGI_IRQHandler(void) +{ + SGI_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void TRNG0_IRQHandler(void) +{ + TRNG0_DriverIRQHandler(); +} + +WEAK void SECURE_ERR_IRQHandler(void) +{ + SECURE_ERR_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/startup_MCXA256.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/startup_MCXA256.cpp new file mode 100644 index 000000000..24d795620 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/startup_MCXA256.cpp @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA256 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void SGI_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void TRNG0_IRQHandler(void); +WEAK void SECURE_ERR_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void PKC_DriverIRQHandler(void) ALIAS(DefaultISR); +void SGI_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void TRNG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SECURE_ERR_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA256 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + PKC_IRQHandler, // 126: PKC interrupt + SGI_IRQHandler, // 127: SGI interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + TRNG0_IRQHandler, // 129: True Random Number Generator interrupt + SECURE_ERR_IRQHandler, // 130: Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ + PKC_DriverIRQHandler(); +} + +WEAK void SGI_IRQHandler(void) +{ + SGI_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void TRNG0_IRQHandler(void) +{ + TRNG0_DriverIRQHandler(); +} + +WEAK void SECURE_ERR_IRQHandler(void) +{ + SECURE_ERR_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/system_MCXA256.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/system_MCXA256.c new file mode 100644 index 000000000..74fb6843f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/system_MCXA256.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA256 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA256 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/system_MCXA256.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/system_MCXA256.h new file mode 100644 index 000000000..f4b33f917 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/system_MCXA256.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA256 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA256 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA256_H_ +#define _SYSTEM_MCXA256_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA256_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/variable.cmake new file mode 100644 index 000000000..ed229720c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA256/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA256) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph5) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/CMakeLists.txt new file mode 100644 index 000000000..2f026fc9d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA266/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/MCXA265.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/MCXA265.h new file mode 100644 index 000000000..a3c67ff4c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/MCXA265.h @@ -0,0 +1,98 @@ +/* +** ################################################################### +** Processors: MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA265 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA265.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA265 + * + * CMSIS Peripheral Access Layer for MCXA265 + */ + +#if !defined(MCXA265_H_) /* Check if memory map has not been already included */ +#define MCXA265_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LCD.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SGI.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_TRNG.h" +#include "PERI_UDF.h" +#include "PERI_USB.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA265_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/MCXA265_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/MCXA265_COMMON.h new file mode 100644 index 000000000..de9853673 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/MCXA265_COMMON.h @@ -0,0 +1,936 @@ +/* +** ################################################################### +** Processors: MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA265 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA265_COMMON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA265 + * + * CMSIS Peripheral Access Layer for MCXA265 + */ + +#if !defined(MCXA265_COMMON_H_) +#define MCXA265_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + CAN1_IRQn = 20, /**< Controller Area Network 1 interrupt */ + FLEXIO_IRQn = 23, /**< Flexible Input/Output interrupt */ + I3C0_IRQn = 24, /**< Improved Inter Integrated Circuit interrupt 0 */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit 4 interrupt */ + USB0_IRQn = 36, /**< Universal Serial Bus - Full Speed interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + Reserved82_IRQn = 66, /**< Reserved interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit 3 interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + LPUART5_IRQn = 95, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ + PKC_IRQn = 110, /**< PKC interrupt */ + SGI_IRQn = 111, /**< SGI interrupt */ + TRNG0_IRQn = 113, /**< True Random Number Generator interrupt */ + SECURE_ERR_IRQn = 114, /**< Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. */ + Reserved132_IRQn = 116, /**< Reserved interrupt */ + Reserved133_IRQn = 117, /**< Reserved interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + LCD_IRQn = 121 /**< SLCD frame start interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA265.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA265_SERIES +#define MCXA265_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA265_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x400D0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0, CAN1 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn, CAN1_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO0 base address */ +#define FLEXIO0_BASE (0x40099000u) +/** Peripheral FLEXIO0 base pointer */ +#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO0 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C0 base address */ +#define I3C0_BASE (0x40002000u) +/** Peripheral I3C0 base pointer */ +#define I3C0 ((I3C_Type *)I3C0_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { I3C0_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { I3C0 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LCD - Peripheral instance base addresses */ +/** Peripheral LCD0 base address */ +#define LCD0_BASE (0x400C2000u) +/** Peripheral LCD0 base pointer */ +#define LCD0 ((LCD_Type *)LCD0_BASE) +/** Array initializer of LCD peripheral base addresses */ +#define LCD_BASE_ADDRS { LCD0_BASE } +/** Array initializer of LCD peripheral base pointers */ +#define LCD_BASE_PTRS { LCD0 } +/** Interrupt vectors for the LCD peripheral type */ +#define LCD_IRQS { LCD_IRQn } +/* Backward compatibility */ +#define LCD_WFOVERLAY_WFACCESS8BIT_WF8B_COUNT LCD_WF_ACCESS_WF8BIT_WF8B_COUNT +#define LCD_WFOVERLAY_WFACCESS32BIT_WF_COUNT LCD_WF_ACCESS_WF32BIT_WF_COUNT + + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1 } + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x400DA000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PKC - Peripheral instance base addresses */ +/** Peripheral PKC0 base address */ +#define PKC0_BASE (0x400EA000u) +/** Peripheral PKC0 base pointer */ +#define PKC0 ((PKC_Type *)PKC0_BASE) +/** Array initializer of PKC peripheral base addresses */ +#define PKC_BASE_ADDRS { PKC0_BASE } +/** Array initializer of PKC peripheral base pointers */ +#define PKC_BASE_PTRS { PKC0 } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SGI - Peripheral instance base addresses */ +/** Peripheral SGI0 base address */ +#define SGI0_BASE (0x400EB000u) +/** Peripheral SGI0 base pointer */ +#define SGI0 ((SGI_Type *)SGI0_BASE) +/** Array initializer of SGI peripheral base addresses */ +#define SGI_BASE_ADDRS { SGI0_BASE } +/** Array initializer of SGI peripheral base pointers */ +#define SGI_BASE_PTRS { SGI0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TRNG - Peripheral instance base addresses */ +/** Peripheral TRNG0 base address */ +#define TRNG0_BASE (0x400EC000u) +/** Peripheral TRNG0 base pointer */ +#define TRNG0 ((TRNG_Type *)TRNG0_BASE) +/** Array initializer of TRNG peripheral base addresses */ +#define TRNG_BASE_ADDRS { TRNG0_BASE } +/** Array initializer of TRNG peripheral base pointers */ +#define TRNG_BASE_PTRS { TRNG0 } + +/* UDF - Peripheral instance base addresses */ +/** Peripheral UDF0 base address */ +#define UDF0_BASE (0x400ED000u) +/** Peripheral UDF0 base pointer */ +#define UDF0 ((UDF_Type *)UDF0_BASE) +/** Array initializer of UDF peripheral base addresses */ +#define UDF_BASE_ADDRS { UDF0_BASE } +/** Array initializer of UDF peripheral base pointers */ +#define UDF_BASE_PTRS { UDF0 } + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x400A4000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA265_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/MCXA265_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/MCXA265_features.h new file mode 100644 index 000000000..e17d2ae66 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/MCXA265_features.h @@ -0,0 +1,991 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA265_FEATURES_H_ +#define _MCXA265_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* SLCD module features */ + +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (516096) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRNG module features */ + +/* @brief TRNG does not support SCR4L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (0) +/* @brief TRNG does not support SCR5L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (0) +/* @brief TRNG does not support SCR6L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) +/* @brief TRNG does not support PKRMAX. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (0) +/* @brief TRNG does not support SAMP mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) +/* @brief TRNG does not support ACC. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) +/* @brief TRNG does not support SBLIM. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (0) +/* @brief TRNG supports reset control. */ +#define FSL_FEATURE_TRNG_HAS_RSTCTL (0) +/* @brief TRNG does not support FOR_CLK mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1) +/* @brief TRNG has two oscillators. */ +#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA265_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/fsl_device_registers.h new file mode 100644 index 000000000..539322cf8 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/startup_MCXA265.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/startup_MCXA265.c new file mode 100644 index 000000000..e5d0561a6 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/startup_MCXA265.c @@ -0,0 +1,1472 @@ +//***************************************************************************** +// MCXA265 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void SGI_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void TRNG0_IRQHandler(void); +WEAK void SECURE_ERR_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); +WEAK void LCD_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void PKC_DriverIRQHandler(void) ALIAS(DefaultISR); +void SGI_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void TRNG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SECURE_ERR_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); +void LCD_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA265 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 36 : Controller Area Network 1 interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + PKC_IRQHandler, // 126: PKC interrupt + SGI_IRQHandler, // 127: SGI interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + TRNG0_IRQHandler, // 129: True Random Number Generator interrupt + SECURE_ERR_IRQHandler, // 130: Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt + LCD_IRQHandler, // 137: SLCD frame start interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ + CAN1_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ + PKC_DriverIRQHandler(); +} + +WEAK void SGI_IRQHandler(void) +{ + SGI_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void TRNG0_IRQHandler(void) +{ + TRNG0_DriverIRQHandler(); +} + +WEAK void SECURE_ERR_IRQHandler(void) +{ + SECURE_ERR_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +WEAK void LCD_IRQHandler(void) +{ + LCD_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/startup_MCXA265.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/startup_MCXA265.cpp new file mode 100644 index 000000000..e5d0561a6 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/startup_MCXA265.cpp @@ -0,0 +1,1472 @@ +//***************************************************************************** +// MCXA265 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void Reserved82_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void SGI_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void TRNG0_IRQHandler(void); +WEAK void SECURE_ERR_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); +WEAK void LCD_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved82_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void PKC_DriverIRQHandler(void) ALIAS(DefaultISR); +void SGI_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void TRNG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SECURE_ERR_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); +void LCD_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA265 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 36 : Controller Area Network 1 interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + Reserved82_IRQHandler, // 82 : Reserved interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + PKC_IRQHandler, // 126: PKC interrupt + SGI_IRQHandler, // 127: SGI interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + TRNG0_IRQHandler, // 129: True Random Number Generator interrupt + SECURE_ERR_IRQHandler, // 130: Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt + LCD_IRQHandler, // 137: SLCD frame start interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ + CAN1_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void Reserved82_IRQHandler(void) +{ + Reserved82_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ + PKC_DriverIRQHandler(); +} + +WEAK void SGI_IRQHandler(void) +{ + SGI_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void TRNG0_IRQHandler(void) +{ + TRNG0_DriverIRQHandler(); +} + +WEAK void SECURE_ERR_IRQHandler(void) +{ + SECURE_ERR_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +WEAK void LCD_IRQHandler(void) +{ + LCD_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/system_MCXA265.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/system_MCXA265.c new file mode 100644 index 000000000..87b784e6c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/system_MCXA265.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA265 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA265 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/system_MCXA265.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/system_MCXA265.h new file mode 100644 index 000000000..2a47819b3 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/system_MCXA265.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA265 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA265 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA265_H_ +#define _SYSTEM_MCXA265_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA265_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/variable.cmake new file mode 100644 index 000000000..8d938387d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA265/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA265) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph5) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/CMakeLists.txt index d394a2184..2f026fc9d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/CMakeLists.txt @@ -1,11 +1,11 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) -mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA346/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA266/drivers) #### MCX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266.h index f652e2b40..193f90fbb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA266 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266_COMMON.h index 398a434b2..5f358dece 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA266 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266_features.h index 086e4c942..ee6855198 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/MCXA266_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-26 -** Build: b250725 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -270,6 +270,8 @@ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) /* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -481,6 +483,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -782,10 +786,56 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) /* SPC module features */ @@ -906,7 +956,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -928,8 +978,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA266_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/CMakeLists.txt new file mode 100644 index 000000000..6837e437b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/CMakeLists.txt @@ -0,0 +1,36 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA153/drivers/romapi) + +if (CONFIG_MCUX_COMPONENT_driver.clock) + mcux_component_version(2.0.1) + mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) + mcux_add_include( INCLUDES . ) +endif() + +if (CONFIG_MCUX_COMPONENT_driver.edma_soc) + mcux_component_version(2.0.0) + mcux_add_source( SOURCES fsl_edma_soc.c fsl_edma_soc.h ) + mcux_add_include( INCLUDES . ) +endif() + +if (CONFIG_MCUX_COMPONENT_driver.inputmux_connections) + mcux_component_version(2.0.0) + mcux_add_source( SOURCES fsl_inputmux_connections.h ) + mcux_add_include( INCLUDES . ) +endif() + +if (CONFIG_MCUX_COMPONENT_driver.reset) + mcux_component_version(2.4.0) + mcux_add_source( SOURCES fsl_reset.c fsl_reset.h ) + mcux_add_include( INCLUDES . ) +endif() + +if (CONFIG_MCUX_COMPONENT_driver.trdc_soc) + mcux_component_version(2.0.0) + mcux_add_source( SOURCES fsl_trdc_soc.h ) + mcux_add_include( INCLUDES . ) +endif() diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_clock.c new file mode 100644 index 000000000..cb5000b77 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_clock.c @@ -0,0 +1,2266 @@ +/* + * Copyright 2025, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +#define IFR1_ADDR (0x01100000U) +#define IFR1_VAL_180M_TRIM *((volatile uint32_t *)(IFR1_ADDR + 0x870U)) +#if FSL_FEATURE_FIRC_SUPPORT_240M +#define IFR1_VAL_240M_TRIM *((volatile uint32_t *)(IFR1_ADDR + 0x874U)) +#endif + +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) +#define PLL_MAX_N_DIV (0x100U) + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_NDIV_VAL_P (0U) /* NDIV is in bits 7:0 */ +#define PLL_NDIV_VAL_M (0xFFUL << PLL_NDIV_VAL_P) +#define PLL_MDIV_VAL_P (0U) /* MDIV is in bits 15:0 */ +#define PLL_MDIV_VAL_M (0xFFFFULL << PLL_MDIV_VAL_P) +#define PLL_PDIV_VAL_P (0U) /* PDIV is in bits 4:0 */ +#define PLL_PDIV_VAL_M (0x1FUL << PLL_PDIV_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (32000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDIV reg */ +#define PLL_NDIV_VAL_SET(value) (((unsigned long)(value) << PLL_NDIV_VAL_P) & PLL_NDIV_VAL_M) +/* PLL MDIV reg */ +#define PLL_MDIV_VAL_SET(value) (((unsigned long long)(value) << PLL_MDIV_VAL_P) & PLL_MDIV_VAL_M) +/* PLL PDIV reg */ +#define PLL_PDIV_VAL_SET(value) (((unsigned long)(value) << PLL_PDIV_VAL_P) & PLL_PDIV_VAL_M) + +/* PLL SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P (0U) +#define PLL_SSCG_MD_INT_P (25U) +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) +#define PLL_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL_SSCG_MD_FRACT_P) & PLL_SSCG_MD_FRACT_M) +#define PLL_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL_SSCG_MD_INT_P) & PLL_SSCG_MD_INT_M) + +/******************************************************************************* + * Variables + ******************************************************************************/ +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +volatile static uint32_t s_Ext_Clk_Freq = 16000000U; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Get FRO 12M Clk */ +static uint32_t CLOCK_GetFro12MFreq(void); +/* Get LF FRO_DIV Clk */ +static uint32_t CLOCK_GetFroLfDivFreq(void); +/* Get CLK 1M Clk */ +static uint32_t CLOCK_GetClk1MFreq(void); +/* Get HF FRO Clk */ +static uint32_t CLOCK_GetFroHfFreq(void); +/* Get HF FRO_DIV Clk */ +static uint32_t CLOCK_GetFroHfDivFreq(void); +/* Get CLK 45M Clk */ +static uint32_t CLOCK_GetClk45MFreq(void); +/* Get CLK 16K Clk */ +static uint32_t CLOCK_GetClk16KFreq(uint8_t id); +/* Get EXT OSC Clk */ +static uint32_t CLOCK_GetExtClkFreq(void); +/* Get Main_Clk */ +uint32_t CLOCK_GetMainClk(void); +/* Get FRO_16K */ +static uint32_t CLOCK_GetFRO16KFreq(void); +/* Get Pll1ClkDiv */ +static uint32_t CLOCK_GetPll1ClkDivFreq(void); +/* Get Pll1Clk */ +uint32_t CLOCK_GetPll1OutFreq(void); +#define CLOCK_GetPll1ClkFreq CLOCK_GetPll1OutFreq + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL1 NDIV setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL1 PDIV setting */ +static uint32_t findPll1PostDiv(void); +/* Get multiplier (M) from PLL1 MDIV and SSCG settings */ +static float findPll1MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Set PLL0 output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Get PLL input clock rate from setup structure */ +static uint32_t CLOCK_GetPLLInClockRateFromSetup(pll_setup_t *pSetup); +/* Get predivider (N) from setup structure */ +static uint32_t findPllPreDivFromSetup(pll_setup_t *pSetup); +/* Get postdivider (P) from setup structure */ +static uint32_t findPllPostDivFromSetup(pll_setup_t *pSetup); +/* Get multiplier (M) from setup structure */ +static float findPllMMultFromSetup(pll_setup_t *pSetup); + +/* Check if DIV is halt */ +static inline bool CLOCK_IsDivHalt(uint32_t div_value) +{ + if (0U != (div_value & (1UL << 30U))) + { + return true; + } + else + { + return false; + } +} + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); + const uint32_t clk_sel = CLK_ATTACH_CLK_SEL(connection); + + if (kNONE_to_NONE != connection) + { + CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param connection : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection) +{ + const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); + uint32_t actual_sel = 0U; + uint32_t clock_attach_id = 0U; + + if (kNONE_to_NONE == connection) + { + return kNONE_to_NONE; + } + + actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); + clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); + + return (clock_attach_id_t)clock_attach_id; +} + +/* Set the clock selection value */ +void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value) +{ + volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name); + assert(sel_name <= kCLOCK_SelMax); + + if (sel_name == kCLOCK_SelSCGSCS) + { + SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); + while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) + { + } + } + else + { + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + *pClkCtrl = value; + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; + } +} + +/* Get the clock selection value */ +uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name) +{ + volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name); + uint32_t actual_sel = 0U; + assert(sel_name <= kCLOCK_SelMax); + + if (sel_name == kCLOCK_SelSCGSCS) + { + actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); + } + else + { + actual_sel = *pClkCtrl; + } + + return actual_sel; +} + +/* Set the clock divider value */ +void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value) +{ + volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name); + assert(div_name <= kCLOCK_DivMax); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + /* halt and reset clock dividers */ + *pDivCtrl = 0x3UL << 29U; + + if (value == 0U) /*!< halt */ + { + *pDivCtrl |= (1UL << 30U); + } + else + { + *pDivCtrl = (value - 1U); + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/* Get the clock divider value */ +uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name) +{ + volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name); + assert(div_name <= kCLOCK_DivMax); + + if (((*pDivCtrl) & (1UL << 30U)) != 0U) + { + return 0; + } + else + { + return ((*pDivCtrl & 0xFFU) + 1U); + } +} + +/* Halt the clock divider value */ +void CLOCK_HaltClockDiv(clock_div_name_t div_name) +{ + volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name); + assert(div_name <= kCLOCK_DivMax); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + *pDivCtrl |= (1UL << 30U); + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/* Initialize the FROHF to given frequency (45,60,90,180) + * (80,120,240) are only supported for 240M part */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq) +{ + uint8_t freq_select = 0x0U; + uint8_t need_switch_frohf = 0x0U; + uint32_t trim_value = 0x0U; + switch (iFreq) + { + case 45000000U: + freq_select = 1U; + trim_value = IFR1_VAL_180M_TRIM; + break; + case 60000000U: + freq_select = 3U; + trim_value = IFR1_VAL_180M_TRIM; + break; + case 90000000U: + freq_select = 5U; + trim_value = IFR1_VAL_180M_TRIM; + break; + case 180000000U: + freq_select = 7U; + trim_value = IFR1_VAL_180M_TRIM; + break; +#if FSL_FEATURE_FIRC_SUPPORT_240M + case 80000000U: + freq_select = 3U; + trim_value = IFR1_VAL_240M_TRIM; + break; + case 120000000U: + freq_select = 5U; + trim_value = IFR1_VAL_240M_TRIM; + break; + case 240000000U: + freq_select = 7U; + trim_value = IFR1_VAL_240M_TRIM; + break; +#endif + default: + freq_select = 0xFU; + break; + } + + if (0xFU == freq_select) + { + return kStatus_Fail; + } + + /* Check if the trim value is valid */ + if (trim_value == 0xFFFFFFFFU) + { + return kStatus_Fail; + } + + /* Switch to FRO LF is FRO HF is in use */ + if (0x3U == ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)) + { + need_switch_frohf = 1; + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); + } + + /* Load trim value from IFR */ + if (SCG0->FIRCTRIM != trim_value) + { + SCG0->TRIM_LOCK = 0x5A5A0001U; + SCG0->FIRCTRIM = trim_value; + SCG0->TRIM_LOCK = 0x5A5A0000U; + } + + /* Set FIRC frequency */ + SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); + + /* Unlock FIRCCSR */ + SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; + + /* Enable CLK 45 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; + /* Enable FIRC HF clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; + /* Enable FIRC */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; + + /* Lock FIRCCSR */ + SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; + + /* Wait for FIRC clock to be stable. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCACC_MASK) == 0U) + { + } + + /* Switch back to FRO HF */ + if (1 == need_switch_frohf) + { + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); + } + + return kStatus_Success; +} + +/* Initialize the FRO12M. */ +status_t CLOCK_SetupFRO12MClocking(void) +{ + /* Unlock SIRCCSR */ + SCG0->SIRCCSR &= ~SCG_SIRCCSR_LK_MASK; + + /* Enable FRO12M clock for peripheral use */ + SCG0->SIRCCSR |= SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK; + + /* Lock SIRCCSR */ + SCG0->SIRCCSR |= SCG_SIRCCSR_LK_MASK; + + /* Wait for SIRC clock to be valid. */ + while ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0U) + { + } + + /* Release FROLFDIV */ + SYSCON->FROLFDIV &= ~SYSCON_FROLFDIV_HALT_MASK; + + return kStatus_Success; +} + +/*! + * brief Initialize the FRO16K. + * This function turns on FRO16K. + * return returns success or fail status. + */ +status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask) +{ + /* Enable clk_16k */ + VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; + VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; + + /* Enable clk_16k output clock to corresponding modules according to the enable_mask. */ + VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(((uint32_t)clk_16k_enable_mask)); + + return kStatus_Success; +} + +/*! + * brief Initialize the external osc clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 8000000U) && (iFreq < 16000000U)) + { + range = 0U; + } + else if ((iFreq >= 16000000U) && (iFreq < 25000000U)) + { + range = 1U; + } + else if ((iFreq >= 25000000U) && (iFreq < 40000000U)) + { + range = 2U; + } + else if ((iFreq >= 40000000U) && (iFreq <= 50000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (internal crystal oscillator) and Configure SOSC range */ + SCG0->SOSCCFG = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/*! + * @brief Initialize the external reference clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq) +{ + if (iFreq > 50000000U) + { + return kStatus_InvalidArgument; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (external reference clock)*/ + SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK; + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq = 0U; + + switch (clockName) + { + case kCLOCK_MainClk: /* MAIN_CLK */ + freq = CLOCK_GetMainClk(); + break; + case kCLOCK_CoreSysClk: /* Core/system clock(CPU_CLK) */ + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_SYSTEM_CLK: /* AHB clock */ + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: /* Bus clock */ + freq = (CLOCK_GetCoreSysClkFreq() >> 1); + break; + case kCLOCK_ExtClk: /* External Clock */ + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_FroHf: /* FROHF */ + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_FroHfDiv: /* Divided by FROHF */ + freq = CLOCK_GetFroHfDivFreq(); + break; + case kCLOCK_Clk45M: /* CLK_45M */ + freq = CLOCK_GetClk45MFreq(); + break; + case kCLOCK_Fro12M: /* FRO12M */ + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_Fro12MDiv: /* FRO_LF_DIV */ + freq = CLOCK_GetFro12MFreq() / ((SYSCON->FROLFDIV & 0xfU) + 1U); + break; + case kCLOCK_Clk1M: /* CLK1M */ + freq = CLOCK_GetClk1MFreq(); + break; + case kCLOCK_Fro16K: /* FRO16K */ + freq = CLOCK_GetFRO16KFreq(); + break; + case kCLOCK_Clk16K0: /* CLK16K[0] */ + freq = CLOCK_GetClk16KFreq(0); + break; + case kCLOCK_Clk16K1: /* CLK16K[1] */ + freq = CLOCK_GetClk16KFreq(1); + break; + case kCLOCK_SLOW_CLK: /* SYSTEM_CLK divided by 6 */ + freq = (CLOCK_GetCoreSysClkFreq() / 6); + break; + case kCLOCK_Pll1Clk: /* Pll1Clk */ + freq = CLOCK_GetPll1ClkFreq(); + break; + case kCLOCK_Pll1ClkDiv: /* Pll1ClkDiv */ + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) != 0U) ? 12000000U : 0U; +} + +/* Get CLK 1M Clk */ +/*! brief Return Frequency of CLK 1MHz + * return Frequency of CLK 1MHz + */ +static uint32_t CLOCK_GetClk1MFreq(void) +{ + return 1000000U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfFreq(void) +{ + uint8_t div; + + if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || + ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) + { + div = 0U; + } + + switch ((SCG0->FIRCCFG & SCG_FIRCCFG_FREQ_SEL_MASK) >> SCG_FIRCCFG_FREQ_SEL_SHIFT) + { + case 1U: + div = 4U; + break; + case 3U: + div = 3U; + break; + case 5U: + div = 2U; + break; + case 7U: + div = 1U; + break; + default: + div = 0U; + break; + } + +#if FSL_FEATURE_FIRC_SUPPORT_240M + if (SCG0->FIRCTRIM == IFR1_VAL_180M_TRIM) + { + return (div != 0U) ? (180000000U / div) : 0U; + } + else + { + return (div != 0U) ? (240000000U / div) : 0U; + } +#else + return (div != 0U) ? (180000000U / div) : 0U; +#endif +} + +/* Get HF FRO DIV Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfDivFreq(void) +{ + return CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & SYSCON_FROHFDIV_DIV_MASK) + 1U); +} + +/* Get LF FRO DIV Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroLfDivFreq(void) +{ + return CLOCK_GetFro12MFreq() / ((SYSCON->FROLFDIV & SYSCON_FROLFDIV_DIV_MASK) + 1U); +} + +/* Get CLK_45M frequency */ +/*! brief Return Frequency of CLK 45MHz + * return Frequency of CLK 45MHz + */ +static uint32_t CLOCK_GetClk45MFreq(void) +{ + if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) == 0U) + { + return 0U; + } + else + { + return 45000000U; + } +} + +/*! brief Return Frequency of FRO16K + * return Frequency of FRO_16K + */ +static uint32_t CLOCK_GetFRO16KFreq(void) +{ + return ((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) ? 16000U : 0U; +} +/* Get CLK 16K Clk */ +/*! brief Return Frequency of CLK 16KHz + * return Frequency of CLK 16KHz + */ +static uint32_t CLOCK_GetClk16KFreq(uint8_t id) +{ + return (((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) && + ((VBAT0->FROCLKE & VBAT_FROCLKE_CLKE((((uint32_t)id) << 1U))) != 0U)) ? + 16000U : + 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) != 0U) ? s_Ext_Clk_Freq : 0U; +} + +/* Get Pll1ClkDiv */ +uint32_t CLOCK_GetPll1ClkDivFreq(void) +{ + return CLOCK_GetPll1ClkFreq() / ((SYSCON->PLL1CLKDIV & SYSCON_PLL1CLKDIV_DIV_MASK) + 1U); +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetMainClk(void) +{ + uint32_t freq = 0U; + + switch ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 1U: + freq = CLOCK_GetExtClkFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 6U: + freq = CLOCK_GetPll1ClkFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! brief Return Frequency of core + * return Frequency of the core + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + return CLOCK_GetMainClk() / ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) + 1U); +} + +/* Get I3C Clk */ +/*! brief Return Frequency of I3C Clock + * return Frequency of I3C Clock + */ +uint32_t CLOCK_GetI3CFClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_I3C0_FCLK_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_I3C0_FCLK_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_CTIMER0_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_CTIMER1_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER1_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_CTIMER2_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER2_CLKDIV; + break; + case 3U: + clksel = MRCC0->MRCC_CTIMER3_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER3_CLKDIV; + break; + case 4U: + clksel = MRCC0->MRCC_CTIMER4_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER4_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_CTIMER0_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 4U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/* Get LPI2C Clk */ +/*! brief Return Frequency of LPI2C functional Clock + * return Frequency of LPI2C functional Clock + */ +uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_LPI2C0_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_LPI2C1_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C1_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_LPI2C2_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C2_CLKDIV; + break; + case 3U: + clksel = MRCC0->MRCC_LPI2C3_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C3_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_LPI2C0_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of LPSPI Clock + * return Frequency of LPSPI Clock + */ +uint32_t CLOCK_GetLpspiClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKSEL) : (MRCC0->MRCC_LPSPI1_CLKSEL); + uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKDIV) : (MRCC0->MRCC_LPSPI1_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of LPUART Clock + * return Frequency of LPUART Clock + */ +uint32_t CLOCK_GetLpuartClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_LPUART0_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART0_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_LPUART1_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART1_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_LPUART2_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART2_CLKDIV; + break; + case 3U: + clksel = MRCC0->MRCC_LPUART3_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART3_CLKDIV; + break; + case 4U: + clksel = MRCC0->MRCC_LPUART4_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART4_CLKDIV; + break; + case 5U: + clksel = MRCC0->MRCC_LPUART5_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART5_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_LPUART0_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART0_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 4U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of LPTMR Clock + * return Frequency of LPTMR Clock + */ +uint32_t CLOCK_GetLptmrClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_LPTMR0_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_LPTMR0_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of OSTIMER + * return Frequency of OSTIMER Clock + */ +uint32_t CLOCK_GetOstimerClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_OSTIMER0_CLKSEL); + + switch (clksel) + { + case 0U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + uint32_t clksel = MRCC0->MRCC_ADC_CLKSEL; + uint32_t clkdiv = MRCC0->MRCC_ADC_CLKDIV; + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of Dac Clock + * return Frequency of Dac. + */ +uint32_t CLOCK_GetDacClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_DAC0_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_DAC0_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of CMP Function Clock + * return Frequency of CMP Function. + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_CMP0_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP0_FUNC_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_CMP1_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP1_FUNC_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_CMP2_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP2_FUNC_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_CMP0_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP0_FUNC_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of CMP Round Robin Clock + * return Frequency of CMP Round Robin. + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_CMP0_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP0_RR_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_CMP1_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP1_RR_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_CMP2_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP2_RR_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_CMP0_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP0_RR_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of Trace Clock + * return Frequency of Trace. + */ +uint32_t CLOCK_GetTraceClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_DBG_TRACE_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_DBG_TRACE_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetClk1MFreq(); + break; + case 2U: + freq = CLOCK_GetClk16KFreq(1); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of CLKOUT Clock + * return Frequency of CLKOUT. + */ +uint32_t CLOCK_GetClkoutClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_CLKOUT_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_CLKOUT_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 5U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + case 6U: + freq = CLOCK_GetFreq(kCLOCK_SLOW_CLK); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of WWDT Clock + * return Frequency of WWDT. + */ +uint32_t CLOCK_GetWwdtClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clkdiv = (MRCC0->MRCC_WWDT0_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + freq = CLOCK_GetClk1MFreq(); + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of FLEXIO FCLK + * return Frequency of FLEXIO FCLK. + */ +uint32_t CLOCK_GetFlexioClkFreq(void) +{ + uint32_t freq = 0U; + + uint32_t clksel = MRCC0->MRCC_FLEXIO0_CLKSEL; + uint32_t clkdiv = MRCC0->MRCC_FLEXIO0_CLKDIV; + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of FlexCAN FCLK + * return Frequency of FlexCAN FCLK. + */ +uint32_t CLOCK_GetFlexcanClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + uint32_t clksel = (0U == id) ? (MRCC0->MRCC_FLEXCAN0_CLKSEL) : (MRCC0->MRCC_FLEXCAN1_CLKSEL); + uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_FLEXCAN0_CLKDIV) : (MRCC0->MRCC_FLEXCAN1_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 6U: + freq = CLOCK_GetPll1ClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config) +{ + SCG0->SIRCTCFG = SCG_SIRCTCFG_TRIMDIV(config.trimDiv) | SCG_SIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_SircTrimNonUpdate == config.trimMode) + { + SCG0->SIRCSTAT = (SCG0->SIRCSTAT & ~SCG_SIRCSTAT_CLTRIM_MASK) | SCG_SIRCSTAT_CLTRIM(config.cltrim); + SCG0->SIRCSTAT = (SCG0->SIRCSTAT & ~SCG_SIRCSTAT_CCOTRIM_MASK) | SCG_SIRCSTAT_CCOTRIM(config.ccotrim); + } + + /* Set trim mode. */ + SCG0->SIRCCSR = (SCG0->SIRCCSR & ~(SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK)) | (uint32_t)config.trimMode; + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0U) + { + return (status_t)kStatus_Fail; + } + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCERR_MASK) == SCG_SIRCCSR_SIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_TRIM_LOCK_MASK) == 0U) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SOSCCSR; + + reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SOSCCSR = reg; +} + +/*! brief Enable USB FS clock. + * Enable USB Full Speed clock. + */ +bool CLOCK_EnableUsbfsClock(void) +{ + /* Enable USB clock */ + CLOCK_EnableClock(kCLOCK_GateUSB0); + + /*!< Set up PLL1 output 48 MHz with FRO12M as source */ + const pll_setup_t pll1Setup = {.pllctrl = SCG_SPLLCTRL_SOURCE(3U) | SCG_SPLLCTRL_SELI(19U) | SCG_SPLLCTRL_SELP(9U), + .pllndiv = SCG_SPLLNDIV_NDIV(1U), + .pllpdiv = SCG_SPLLPDIV_PDIV(4U), + .pllmdiv = SCG_SPLLMDIV_MDIV(32U), + .pllRate = 48000000U}; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + CLOCK_AttachClk(kPll1Clk_to_USB0); /* !< Switch USB0 to Pll1Clk */ + CLOCK_SetClockDiv(kCLOCK_DivUSB0, 1U); /* !< Set USB0_CLKDIV divider to value 1 */ + + return true; +} + +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash + * access time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode) +{ + uint32_t num_wait_states_added = 3UL; /* Default 3 additional wait states */ + switch ((uint32_t)mode) + { + case (uint32_t)kMD_Mode: + { + if (system_freq_hz > 45000000U) + { + return kStatus_Fail; + } + else if (system_freq_hz > 22500000U) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case (uint32_t)kOD_Mode: + { + if (system_freq_hz > 180000000U) + { + return kStatus_Fail; + } + else if (system_freq_hz > 90000000U) + { + num_wait_states_added = 4U; + } + else if (system_freq_hz > 60000000U) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000U) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + default: + num_wait_states_added = 0U; + break; + } + + /* additional wait-states are added */ + FMU0->FCTRL = (FMU0->FCTRL & ~FMU_FCTRL_RWSC_MASK) | FMU_FCTRL_RWSC(num_wait_states_added); + + return kStatus_Success; +} + +/* Get SYSTEM PLL1 Clk */ +/*! brief Return Frequency of PLL1 + * return Frequency of PLL1 + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL1InClockRate(); + + /* If PLL1 is work */ + if (CLOCK_IsPLL1Locked() == true) + { + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll1MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/*! + * @brief Sets the PLL1 monitor mode. + * + * This function sets the PLL1 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SPLLCSR; + + reg &= ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SPLLCSR = reg; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) >> SCG_SPLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk45MFreq(); + break; + case 0x03U: + clkRate = CLOCK_GetFro12MFreq(); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLLOutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLLInClockRateFromSetup(pSetup); + + prediv = findPllPreDivFromSetup(pSetup); + postdiv = findPllPostDivFromSetup(pSetup); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPllMMultFromSetup(pSetup); + workRate /= (float)postdiv; + + return (uint32_t)workRate; +} + +/* Set PLL output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL); + + pll_error_t pllError; + + /* Get PLL Input Clock Rate */ + switch (pControl->inputSource) + { + case (uint32_t)kPll_ClkSrcSysOsc: + inRate = CLOCK_GetExtClkFreq(); + break; + case (uint32_t)kPll_ClkSrcFirc: + inRate = CLOCK_GetClk45MFreq(); + break; + case (uint32_t)kPll_ClkSrcSirc: + inRate = CLOCK_GetFro12MFreq(); + break; + default: + inRate = 0U; + break; + } + + /* PLL flag options */ + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, useSS); + pSetup->pllctrl |= (uint32_t)pControl->inputSource; + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1UL << SCG_SPLLSSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Power off PLL1 and disable PLL1 clock during setup changes */ + SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); + + /* Write PLL setup data */ + SCG0->SPLLCTRL = pSetup->pllctrl; + SCG0->SPLLNDIV = pSetup->pllndiv; + SCG0->SPLLNDIV = pSetup->pllndiv | (1UL << SCG_SPLLNDIV_NREQ_SHIFT); /* latch */ + SCG0->SPLLPDIV = pSetup->pllpdiv; + SCG0->SPLLPDIV = pSetup->pllpdiv | (1UL << SCG_SPLLPDIV_PREQ_SHIFT); /* latch */ + SCG0->SPLLMDIV = pSetup->pllmdiv; + SCG0->SPLLMDIV = pSetup->pllmdiv | (1UL << SCG_SPLLMDIV_MREQ_SHIFT); /* latch */ + SCG0->SPLLSSCG0 = pSetup->pllsscg[0]; + SCG0->SPLLSSCG1 = pSetup->pllsscg[1]; + + /* Unlock SPLLLOCK_CNFG register */ + SCG0->TRIM_LOCK = 0x5a5a0001; + + /* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */ + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + SCG0->SPLLLOCK_CNFG = SCG_SPLLLOCK_CNFG_LOCK_TIME(clkRate / 2000U + 300U); + + /* Power on PLL1 and enable PLL1 clock */ + SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); + + /* Wait for APLL lock */ + while (CLOCK_IsPLL1Locked() == false) + { + } + + if (pSetup->pllRate != CLOCK_GetPll1OutFreq()) + { + return kStatus_PLL_OutputError; + } + + return kStatus_PLL_Success; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_LIMUPOFF_MASK) == 0UL) /* normal mode */ + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 8000UL) + { + seli = 1UL; + } + else if (M >= 122UL) + { + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63UL) + { + seli = 63UL; + } + *pSelI = seli; + + *pSelR = 0U; + } + else + { + /* Note: If the spread spectrum and fractional mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL1 NDIV setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SCG0->SPLLNDIV & SCG_SPLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL1 PDIV setting. */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from PLL1 MDEC. */ +static float findPll1MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(SCG0->SPLLMDIV & SCG_SPLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((SCG0->SPLLSSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = + ((float)(uint32_t)((SCG0->SPLLSSCG0) & PLL_SSCG_MD_FRACT_M) / (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndiv = s_PllSetupCacheStruct[i].pllndiv; + pSetup->pllmdiv = s_PllSetupCacheStruct[i].pllmdiv; + pSetup->pllpdiv = s_PllSetupCacheStruct[i].pllpdiv; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndiv = pSetup->pllndiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllmdiv = pSetup->pllmdiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdiv = pSetup->pllpdiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndiv", "pllpdiv", "pllmdiv" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllmdiv = (uint32_t)PLL_MDIV_VAL_SET(pllMultiplier); + pSetup->pllsscg[1] &= ~SCG_SPLLSSCG1_SEL_SS_MDIV_MASK; + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = 0UL; + pllSelI = 0UL; + pllSelP = 0UL; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) | PLL_SSCG_MD_FRACT_SET((uint32_t)fc)); + pSetup->pllsscg[1] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) >> 32U) | SCG_SPLLSSCG1_SEL_SS_MDIV_MASK; + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndiv = PLL_NDIV_VAL_SET(pllPreDivider); + pSetup->pllpdiv = PLL_PDIV_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SCG_SPLLCTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SCG_SPLLCTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SCG_SPLLCTRL_SELP_SHIFT) | /* Filter coefficient */ + (uplimoff << SCG_SPLLCTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SCG_SPLLCTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT); /* Bypass post-divider? */ + + return kStatus_PLL_Success; +} + +/* Get PLL input clock rate from setup structure */ +static uint32_t CLOCK_GetPLLInClockRateFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0U; + + switch ((pSetup->pllctrl & SCG_SPLLCTRL_SOURCE_MASK) >> SCG_SPLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk45MFreq(); + break; + case 0x03U: + clkRate = CLOCK_GetFro12MFreq(); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Get predivider (N) from from setup structure */ +static uint32_t findPllPreDivFromSetup(pll_setup_t *pSetup) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((pSetup->pllctrl & SCG_SPLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = pSetup->pllndiv & SCG_SPLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from from setup structure */ +static uint32_t findPllPostDivFromSetup(pll_setup_t *pSetup) +{ + uint32_t postDiv = 1UL; + + if ((pSetup->pllctrl & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((pSetup->pllctrl & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = pSetup->pllpdiv & SCG_SPLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (pSetup->pllpdiv & SCG_SPLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from from setup structure */ +static float findPllMMultFromSetup(pll_setup_t *pSetup) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((pSetup->pllsscg[1] & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(pSetup->pllmdiv & SCG_SPLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((pSetup->pllsscg[1] & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((pSetup->pllsscg[0]) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((pSetup->pllsscg[0]) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_clock.h new file mode 100644 index 000000000..8e47ed72f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_clock.h @@ -0,0 +1,1251 @@ +/* + * Copyright 2025, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.0.1. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0U +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#if FSL_FEATURE_FIRC_SUPPORT_240M +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (240000000U) +#else +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000U) +#endif +#endif + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ +#define CLK_GATE_REG_OFFSET(value) (((uint32_t)(value)) >> 16U) +#define CLK_GATE_BIT_SHIFT(value) (((uint32_t)(value)) & 0x0000FFFFU) + +#define REG_PWM0SUBCTL (250U) +#define REG_PWM1SUBCTL (240U) + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_InputMux = ((0x00U << 16U) | (0U)), /*!< Clock gate name: INPUTMUX0 */ + kCLOCK_GateINPUTMUX0 = ((0x00U << 16U) | (0U)), /*!< Clock gate name: INPUTMUX0 */ + kCLOCK_GateI3C0 = ((0x00U << 16U) | (1U)), /*!< Clock gate name: I3C0 */ + kCLOCK_GateCTIMER0 = ((0x00U << 16U) | (2U)), /*!< Clock gate name: CTIMER0 */ + kCLOCK_GateCTIMER1 = ((0x00U << 16U) | (3U)), /*!< Clock gate name: CTIMER1 */ + kCLOCK_GateCTIMER2 = ((0x00U << 16U) | (4U)), /*!< Clock gate name: CTIMER2 */ + kCLOCK_GateCTIMER3 = ((0x00U << 16U) | (5U)), /*!< Clock gate name: CTIMER3 */ + kCLOCK_GateCTIMER4 = ((0x00U << 16U) | (6U)), /*!< Clock gate name: CTIMER4 */ + kCLOCK_GateFREQME = ((0x00U << 16U) | (7U)), /*!< Clock gate name: FREQME */ + kCLOCK_GateUTICK0 = ((0x00U << 16U) | (8U)), /*!< Clock gate name: UTICK0 */ + kCLOCK_GateWWDT0 = ((0x00U << 16U) | (9U)), /*!< Clock gate name: WWDT0 */ + kCLOCK_Smartdma = ((0x00U << 16U) | (10U)), /*!< Clock gate name: SMARTDMA0 */ + kCLOCK_GateDMA0 = ((0x00U << 16U) | (11U)), /*!< Clock gate name: DMA0 */ + kCLOCK_GateAOI0 = ((0x00U << 16U) | (12U)), /*!< Clock gate name: AOI0 */ + kCLOCK_GateCRC0 = ((0x00U << 16U) | (13U)), /*!< Clock gate name: CRC0 */ + kCLOCK_Crc0 = ((0x00U << 16U) | (13U)), /*!< Clock gate name: CRC0 */ + kCLOCK_GateEIM0 = ((0x00U << 16U) | (14U)), /*!< Clock gate name: EIM0 */ + kCLOCK_GateERM0 = ((0x00U << 16U) | (15U)), /*!< Clock gate name: ERM0 */ + kCLOCK_GateFMC = ((0x00U << 16U) | (16U)), /*!< Clock gate name: FMC */ + kCLOCK_GateAOI1 = ((0x00U << 16U) | (17U)), /*!< Clock gate name: AOI1 */ + kCLOCK_GateFLEXIO0 = ((0x00U << 16U) | (18U)), /*!< Clock gate name: FLEXIO0 */ + kCLOCK_GateLPI2C0 = ((0x00U << 16U) | (19U)), /*!< Clock gate name: LPI2C0 */ + kCLOCK_GateLPI2C1 = ((0x00U << 16U) | (20U)), /*!< Clock gate name: LPI2C1 */ + kCLOCK_GateLPSPI0 = ((0x00U << 16U) | (21U)), /*!< Clock gate name: LPSPI0 */ + kCLOCK_GateLPSPI1 = ((0x00U << 16U) | (22U)), /*!< Clock gate name: LPSPI1 */ + kCLOCK_GateLPUART0 = ((0x00U << 16U) | (23U)), /*!< Clock gate name: LPUART0 */ + kCLOCK_GateLPUART1 = ((0x00U << 16U) | (24U)), /*!< Clock gate name: LPUART1 */ + kCLOCK_GateLPUART2 = ((0x00U << 16U) | (25U)), /*!< Clock gate name: LPUART2 */ + kCLOCK_GateLPUART3 = ((0x00U << 16U) | (26U)), /*!< Clock gate name: LPUART3 */ + kCLOCK_GateLPUART4 = ((0x00U << 16U) | (27U)), /*!< Clock gate name: LPUART4 */ + kCLOCK_GateUSB0 = ((0x00U << 16U) | (28U)), /*!< Clock gate name: USB0 */ + kCLOCK_GateQDC0 = ((0x00U << 16U) | (29U)), /*!< Clock gate name: QDC0 */ + kCLOCK_GateQDC1 = ((0x00U << 16U) | (30U)), /*!< Clock gate name: QDC1 */ + kCLOCK_GateFLEXPWM0 = ((0x00U << 16U) | (31U)), /*!< Clock gate name: FLEXPWM0 */ + kCLOCK_GateFLEXPWM1 = ((0x10U << 16U) | (0U)), /*!< Clock gate name: FLEXPWM1 */ + kCLOCK_GateOSTIMER0 = ((0x10U << 16U) | (1U)), /*!< Clock gate name: OSTIMER0 */ + kCLOCK_GateADC0 = ((0x10U << 16U) | (2U)), /*!< Clock gate name: ADC0 */ + kCLOCK_GateADC1 = ((0x10U << 16U) | (3U)), /*!< Clock gate name: ADC1 */ + kCLOCK_GateCMP0 = ((0x10U << 16U) | (4U)), /*!< Clock gate name: CMP0 */ + kCLOCK_GateCMP1 = ((0x10U << 16U) | (5U)), /*!< Clock gate name: CMP1 */ + kCLOCK_GateCMP2 = ((0x10U << 16U) | (6U)), /*!< Clock gate name: CMP2 */ + kCLOCK_GateDAC0 = ((0x10U << 16U) | (7U)), /*!< Clock gate name: DAC0 */ + kCLOCK_GateOPAMP0 = ((0x10U << 16U) | (8U)), /*!< Clock gate name: OPAMP0 */ + kCLOCK_GateOPAMP1 = ((0x10U << 16U) | (9U)), /*!< Clock gate name: OPAMP1 */ + kCLOCK_GateOPAMP2 = ((0x10U << 16U) | (10U)), /*!< Clock gate name: OPAMP2 */ + kCLOCK_GateOPAMP3 = ((0x10U << 16U) | (11U)), /*!< Clock gate name: OPAMP3 */ + kCLOCK_GatePORT0 = ((0x10U << 16U) | (12U)), /*!< Clock gate name: PORT0 */ + kCLOCK_GatePORT1 = ((0x10U << 16U) | (13U)), /*!< Clock gate name: PORT1 */ + kCLOCK_GatePORT2 = ((0x10U << 16U) | (14U)), /*!< Clock gate name: PORT2 */ + kCLOCK_GatePORT3 = ((0x10U << 16U) | (15U)), /*!< Clock gate name: PORT3 */ + kCLOCK_GatePORT4 = ((0x10U << 16U) | (16U)), /*!< Clock gate name: PORT4 */ + kCLOCK_GateSLCD0 = ((0x10U << 16U) | (17U)), /*!< Clock gate name: SLCD0 */ + kCLOCK_GateFLEXCAN0 = ((0x10U << 16U) | (18U)), /*!< Clock gate name: FLEXCAN0 */ + kCLOCK_GateFLEXCAN1 = ((0x10U << 16U) | (19U)), /*!< Clock gate name: FLEXCAN1 */ + kCLOCK_GateLPI2C2 = ((0x10U << 16U) | (20U)), /*!< Clock gate name: LPI2C2 */ + kCLOCK_GateLPI2C3 = ((0x10U << 16U) | (21U)), /*!< Clock gate name: LPI2C3 */ + kCLOCK_GateLPUART5 = ((0x10U << 16U) | (22U)), /*!< Clock gate name: LPUART5 */ + kCLOCK_GateTDET0 = ((0x10U << 16U) | (23U)), /*!< Clock gate name: TDET0 */ + kCLOCK_GatePKC0 = ((0x10U << 16U) | (24U)), /*!< Clock gate name: PKC0 */ + kCLOCK_GateSGI0 = ((0x10U << 16U) | (25U)), /*!< Clock gate name: SGI0 */ + kCLOCK_GateTRNG0 = ((0x10U << 16U) | (26U)), /*!< Clock gate name: TRNG0 */ + kCLOCK_GateUDF0 = ((0x10U << 16U) | (27U)), /*!< Clock gate name: UDF0 */ + kCLOCK_GateADC2 = ((0x10U << 16U) | (28U)), /*!< Clock gate name: ADC2 */ + kCLOCK_GateADC3 = ((0x10U << 16U) | (29U)), /*!< Clock gate name: ADC3 */ + kCLOCK_GateRAMA = ((0x20U << 16U) | (1U)), /*!< Clock gate name: RAMA */ + kCLOCK_GateRAMB = ((0x20U << 16U) | (2U)), /*!< Clock gate name: RAMB */ + kCLOCK_GateRAMC = ((0x20U << 16U) | (3U)), /*!< Clock gate name: RAMC */ + kCLOCK_GateGPIO0 = ((0x20U << 16U) | (4U)), /*!< Clock gate name: GPIO0 */ + kCLOCK_GateGPIO1 = ((0x20U << 16U) | (5U)), /*!< Clock gate name: GPIO1 */ + kCLOCK_GateGPIO2 = ((0x20U << 16U) | (6U)), /*!< Clock gate name: GPIO2 */ + kCLOCK_GateGPIO3 = ((0x20U << 16U) | (7U)), /*!< Clock gate name: GPIO3 */ + kCLOCK_GateGPIO4 = ((0x20U << 16U) | (8U)), /*!< Clock gate name: GPIO4 */ + kCLOCK_GateMAU0 = ((0x20U << 16U) | (9U)), /*!< Clock gate name: MAU0 */ + kCLOCK_GateROMC = ((0x20U << 16U) | (10U)), /*!< Clock gate name: ROMC */ + kCLOCK_GatePWM0SM0 = ((REG_PWM0SUBCTL << 16U) | (0U)), /*!< Clock gate name: PWM0 SM0 */ + kCLOCK_GatePWM0SM1 = ((REG_PWM0SUBCTL << 16U) | (1U)), /*!< Clock gate name: PWM0 SM1 */ + kCLOCK_GatePWM0SM2 = ((REG_PWM0SUBCTL << 16U) | (2U)), /*!< Clock gate name: PWM0 SM2 */ + kCLOCK_GatePWM0SM3 = ((REG_PWM0SUBCTL << 16U) | (3U)), /*!< Clock gate name: PWM0 SM3 */ + kCLOCK_GatePWM1SM0 = ((REG_PWM1SUBCTL << 16U) | (0U)), /*!< Clock gate name: PWM1 SM0 */ + kCLOCK_GatePWM1SM1 = ((REG_PWM1SUBCTL << 16U) | (1U)), /*!< Clock gate name: PWM1 SM1 */ + kCLOCK_GatePWM1SM2 = ((REG_PWM1SUBCTL << 16U) | (2U)), /*!< Clock gate name: PWM1 SM2 */ + kCLOCK_GatePWM1SM3 = ((REG_PWM1SUBCTL << 16U) | (3U)), /*!< Clock gate name: PWM1 SM3 */ + kCLOCK_GateNotAvail = (0xFFFFFFFFU), /*!< Clock gate name: None */ +} clock_ip_name_t; + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_GateAOI0, kCLOCK_GateAOI1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_GateCRC0 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_GateCTIMER0, kCLOCK_GateCTIMER1, kCLOCK_GateCTIMER2, kCLOCK_GateCTIMER3, kCLOCK_GateCTIMER4 \ + } +/*! @brief Clock ip name array for DAC. */ +#define LPDAC_CLOCKS \ + { \ + kCLOCK_GateDAC0 \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_GateDMA0 \ + } +/*! @brief Clock gate name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_GateDMA0 \ + } +/*! @brief Clock ip name array for ERM. */ +#define ERM_CLOCKS \ + { \ + kCLOCK_GateERM0 \ + } +/*! @brief Clock ip name array for EIM. */ +#define EIM_CLOCKS \ + { \ + kCLOCK_GateEIM0 \ + } +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_GateFLEXCAN0, kCLOCK_GateFLEXCAN1 \ + } +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_GateFLEXIO0 \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_GateFREQME \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_GateGPIO0, kCLOCK_GateGPIO1, kCLOCK_GateGPIO2, kCLOCK_GateGPIO3, kCLOCK_GateGPIO4 \ + } +/*! @brief Clock ip name array for I3C */ +#define I3C_CLOCKS \ + { \ + kCLOCK_GateI3C0 \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_GateINPUTMUX0 \ + } +/*! @brief Clock ip name array for GPIO. */ +#define LPCMP_CLOCKS \ + { \ + kCLOCK_GateCMP0, kCLOCK_GateCMP1, kCLOCK_GateCMP2 \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_GateADC0, kCLOCK_GateADC1, kCLOCK_GateADC2, kCLOCK_GateADC3 \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_GateLPUART0, kCLOCK_GateLPUART1, kCLOCK_GateLPUART2, kCLOCK_GateLPUART3, kCLOCK_GateLPUART4, \ + kCLOCK_GateLPUART5 \ + } +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_GateLPI2C0, kCLOCK_GateLPI2C1, kCLOCK_GateLPI2C2, kCLOCK_GateLPI2C3 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_GateLPSPI0, kCLOCK_GateLPSPI1 \ + } +/*! @brief Clock ip name array for MAU. */ +#define MAU_CLOCKS \ + { \ + kCLOCK_GateMAU0 \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_GateOSTIMER0 \ + } +/*! @brief Clock ip name array for DAC. */ +#define OPAMP_CLOCKS \ + { \ + kCLOCK_GateOPAMP0, kCLOCK_GateOPAMP1, kCLOCK_GateOPAMP2, kCLOCK_GateOPAMP3 \ + } +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_GatePWM0SM0, kCLOCK_GatePWM0SM1, kCLOCK_GatePWM0SM2, kCLOCK_GatePWM0SM3}, \ + { \ + kCLOCK_GatePWM1SM0, kCLOCK_GatePWM1SM1, kCLOCK_GatePWM1SM2, kCLOCK_GatePWM1SM3 \ + } \ + } +/*! @brief Clock ip name array for PKC. */ +#define PKC_CLOCKS \ + { \ + kCLOCK_GatePKC0 \ + } +/*! @brief Clock ip name array for PORT. */ +#define PORT_CLOCKS \ + { \ + kCLOCK_GatePORT0, kCLOCK_GatePORT1, kCLOCK_GatePORT2, kCLOCK_GatePORT3, kCLOCK_GatePORT4 \ + } +/*! @brief Clock ip name array for QDC. */ +#define QDC_CLOCKS \ + { \ + kCLOCK_GateQDC0, kCLOCK_GateQDC1 \ + } +/*! @brief Clock ip name array for SGI. */ +#define SGI_CLOCKS \ + { \ + kCLOCK_GateSGI0 \ + } +/*! @brief Clock ip name array for SLCD. */ +#define SLCD_CLOCKS \ + { \ + kCLOCK_GateSLCD0 \ + } +/*! @brief Clock ip name array for SMARTDMA. */ +#define SMARTDMA_CLOCKS \ + { \ + kCLOCK_Smartdma \ + } +/*! @brief Clock ip name array for TDET. */ +#define TDET_CLOCKS \ + { \ + kCLOCK_GateTDET0 \ + } +/*! @brief Clock ip name array for TDET. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_GateTRNG0 \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_GateUTICK0 \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_GateWWDT0 \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_MainClk, /*!< MAIN_CLK */ + kCLOCK_CoreSysClk, /*!< Core/system clock(CPU_CLK) */ + kCLOCK_SYSTEM_CLK, /*!< SYSTEM clock/AHB_BUS */ + kCLOCK_BusClk, /*!< SYSTEM clock divided by 2 */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_FroHf, /*!< FRO192 */ + kCLOCK_FroHfDiv, /*!< Divided by FRO192 */ + kCLOCK_Clk45M, /*!< CLK45M */ + kCLOCK_Pll1Clk, /*!< Pll1Clk */ + kCLOCK_Pll1ClkDiv, /*!< Pll1CkDiv */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_Fro12MDiv, /*!< FRO12MDiv */ + kCLOCK_Clk1M, /*!< CLK1M */ + kCLOCK_Fro16K, /*!< FRO16K */ + kCLOCK_Clk16K0, /*!< CLK16K[0] */ + kCLOCK_Clk16K1, /*!< CLK16K[1] */ + kCLOCK_SLOW_CLK, /*!< SYSTEM_CLK divided by 6 */ +} clock_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_REG_OFFSET(value) (((uint32_t)(value)) >> 16U) +#define CLK_ATTACH_CLK_SEL(value) (((uint32_t)(value)) & 0x0000FFFFU) +#define CLK_ATTACH_MUX(reg, sel) ((((uint32_t)(reg)) << 16U) | (sel)) + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_select_name +{ + kCLOCK_SelI3C0_FCLK = (0x0A0U), /*!< I3C0_FCLK clock selection */ + kCLOCK_SelCTIMER0 = (0x0A8U), /*!< CTIMER0 clock selection */ + kCLOCK_SelCTIMER1 = (0x0B0U), /*!< CTIMER1 clock selection */ + kCLOCK_SelCTIMER2 = (0x0B8U), /*!< CTIMER2 clock selection */ + kCLOCK_SelCTIMER3 = (0x0C0U), /*!< CTIMER3 clock selection */ + kCLOCK_SelCTIMER4 = (0x0C8U), /*!< CTIMER4 clock selection */ + kCLOCK_SelFLEXIO0 = (0x0D8U), /*!< FLEXIO0 clock selection */ + kCLOCK_SelLPI2C0 = (0x0E0U), /*!< LPI2C0 clock selection */ + kCLOCK_SelLPI2C1 = (0x0E8U), /*!< LPI2C1 clock selection */ + kCLOCK_SelLPSPI0 = (0x0F0U), /*!< LPSPI0 clock selection */ + kCLOCK_SelLPSPI1 = (0x0F8U), /*!< LPSPI1 clock selection */ + kCLOCK_SelLPUART0 = (0x100U), /*!< LPUART0 clock selection */ + kCLOCK_SelLPUART1 = (0x108U), /*!< LPUART1 clock selection */ + kCLOCK_SelLPUART2 = (0x110U), /*!< LPUART2 clock selection */ + kCLOCK_SelLPUART3 = (0x118U), /*!< LPUART3 clock selection */ + kCLOCK_SelLPUART4 = (0x120U), /*!< LPUART4 clock selection */ + kCLOCK_SelUSB0 = (0x128U), /*!< USB0 clock selection */ + kCLOCK_SelLPTMR0 = (0x130U), /*!< LPTMR0 clock selection */ + kCLOCK_SelOSTIMER0 = (0x138U), /*!< OSTIMER0 clock selection */ + kCLOCK_SelADC = (0x140U), /*!< ADC0 clock selection */ + kCLOCK_SelCMP0_RR = (0x150U), /*!< CMP0_RR clock selection */ + kCLOCK_SelCMP1_RR = (0x160U), /*!< CMP1_RR clock selection */ + kCLOCK_SelCMP2_RR = (0x170U), /*!< CMP2_RR clock selection */ + kCLOCK_SelDAC0 = (0x178U), /*!< DAC0 clock selection */ + kCLOCK_SelFLEXCAN0 = (0x180U), /*!< FLEXCAN0 clock selection */ + kCLOCK_SelFLEXCAN1 = (0x188U), /*!< FLEXCAN1 clock selection */ + kCLOCK_SelLPI2C2 = (0x190U), /*!< LPI2C2 clock selection */ + kCLOCK_SelLPI2C3 = (0x198U), /*!< LPI2C3 clock selection */ + kCLOCK_SelLPUART5 = (0x1A0U), /*!< LPUART5 clock selection */ + kCLOCK_SelTRACE = (0x1A8U), /*!< TRACE clock selection */ + kCLOCK_SelCLKOUT = (0x1B0U), /*!< CLKOUT clock selection */ + kCLOCK_SelSCGSCS = (0x200U), /*!< SCG SCS clock selection */ + kCLOCK_SelMax = (0x200U), /*!< MAX clock selection */ +} clock_select_name_t; + +/*! + * @brief The enumerator of clock attach Id. + */ +typedef enum _clock_attach_id +{ + kCLK_IN_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 1U), /*!< Attach clk_in to MAIN_CLK. */ + kFRO12M_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 2U), /*!< Attach FRO_12M to MAIN_CLK. */ + kFRO_HF_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 3U), /*!< Attach FRO_HF to MAIN_CLK. */ + kCLK_16K_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 4U), /*!< Attach CLK_16K[1] to MAIN_CLK. */ + kPll1Clk_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 6U), /*!< Attach Pll1Clk to MAIN_CLK. */ + kNONE_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 7U), /*!< Attach NONE to MAIN_CLK. */ + + kFRO_LF_DIV_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 0U), /*!< Attach FRO_LF_DIV to I3C0FCLK. */ + kFRO_HF_DIV_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 2U), /*!< Attach FRO_HF_DIV to I3C0FCLK. */ + kCLK_IN_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 3U), /*!< Attach CLK_IN to I3C0FCLK. */ + kCLK_1M_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 5U), /*!< Attach CLK_1M to I3C0FCLK. */ + kPll1ClkDiv_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 6U), /*!< Attach Pll1ClkDiv to I3C0FCLK. */ + kNONE_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 7U), /*!< Attach NONE to I3C0FCLK. */ + + kFRO_LF_DIV_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 0U), /*!< Attach FRO_LF_DIV to CTIMER0. */ + kFRO_HF_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 1U), /*!< Attach FRO_HF to CTIMER0. */ + kCLK_IN_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 3U), /*!< Attach CLK_IN to CTIMER0. */ + kCLK_16K_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 4U), /*!< Attach CLK_16K to CTIMER0. */ + kCLK_1M_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 5U), /*!< Attach CLK_1M to CTIMER0. */ + kPll1ClkDiv_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 6U), /*!< Attach Pll1ClkDiv to CTIMER0. */ + kNONE_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 7U), /*!< Attach NONE to CTIMER0. */ + + kFRO_LF_DIV_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 0U), /*!< Attach FRO_LF_DIV to CTIMER1. */ + kFRO_HF_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 1U), /*!< Attach FRO_HF to CTIMER1. */ + kCLK_IN_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 3U), /*!< Attach CLK_IN to CTIMER1. */ + kCLK_16K_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 4U), /*!< Attach CLK_16K to CTIMER1. */ + kCLK_1M_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 5U), /*!< Attach CLK_1M to CTIMER1. */ + kPll1ClkDiv_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 6U), /*!< Attach Pll1ClkDiv to CTIMER1. */ + kNONE_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 7U), /*!< Attach NONE to CTIMER1. */ + + kFRO_LF_DIV_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 0U), /*!< Attach FRO_LF_DIV to CTIMER2. */ + kFRO_HF_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 1U), /*!< Attach FRO_HF to CTIMER2. */ + kCLK_IN_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 3U), /*!< Attach CLK_IN to CTIMER2. */ + kCLK_16K_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 4U), /*!< Attach CLK_16K to CTIMER2. */ + kCLK_1M_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 5U), /*!< Attach CLK_1M to CTIMER2. */ + kPll1ClkDiv_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 6U), /*!< Attach Pll1ClkDiv to CTIMER2. */ + kNONE_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 7U), /*!< Attach NONE to CTIMER2. */ + + kFRO_LF_DIV_to_CTIMER3 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER3, 0U), /*!< Attach FRO_LF_DIV to CTIMER3. */ + kFRO_HF_to_CTIMER3 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER3, 1U), /*!< Attach FRO_HF to CTIMER3. */ + kCLK_IN_to_CTIMER3 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER3, 3U), /*!< Attach CLK_IN to CTIMER3. */ + kCLK_16K_to_CTIMER3 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER3, 4U), /*!< Attach CLK_16K to CTIMER3. */ + kCLK_1M_to_CTIMER3 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER3, 5U), /*!< Attach CLK_1M to CTIMER3. */ + kPll1ClkDiv_to_CTIMER3 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER3, 6U), /*!< Attach Pll1ClkDiv to CTIMER3. */ + kNONE_to_CTIMER3 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER3, 7U), /*!< Attach NONE to CTIMER3. */ + + kFRO_LF_DIV_to_CTIMER4 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER4, 0U), /*!< Attach FRO_LF_DIV to CTIMER4. */ + kFRO_HF_to_CTIMER4 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER4, 1U), /*!< Attach FRO_HF to CTIMER4. */ + kCLK_IN_to_CTIMER4 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER4, 3U), /*!< Attach CLK_IN to CTIMER4. */ + kCLK_16K_to_CTIMER4 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER4, 4U), /*!< Attach CLK_16K to CTIMER4. */ + kCLK_1M_to_CTIMER4 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER4, 5U), /*!< Attach CLK_1M to CTIMER4. */ + kPll1ClkDiv_to_CTIMER4 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER4, 6U), /*!< Attach Pll1ClkDiv to CTIMER4. */ + kNONE_to_CTIMER4 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER4, 7U), /*!< Attach NONE to CTIMER4. */ + + kFRO_LF_DIV_to_FLEXIO0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXIO0, 0U), /*!< Attach FRO_LF_DIV to FLEXIO0. */ + kFRO_HF_to_FLEXIO0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXIO0, 1U), /*!< Attach FRO_HF to FLEXIO0. */ + kCLK_IN_to_FLEXIO0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXIO0, 3U), /*!< Attach CLK_IN to FLEXIO0. */ + kCLK_1M_to_FLEXIO0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXIO0, 5U), /*!< Attach CLK_1M to FLEXIO0. */ + kPll1ClkDiv_to_FLEXIO0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXIO0, 6U), /*!< Attach Pll1ClkDiv to FLEXIO0. */ + kNONE_to_FLEXIO0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXIO0, 7U), /*!< Attach NONE to FLEXIO0. */ + + kFRO_HF_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 1U), /*!< Attach FRO_HF to FLEXCAN0. */ + kFRO_HF_DIV_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 2U), /*!< Attach FRO_HF_DIV to FLEXCAN0. */ + kCLK_IN_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 3U), /*!< Attach CLK_IN to FLEXCAN0. */ + kPll1Clk_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 6U), /*!< Attach Pll1Clk to FLEXCAN0. */ + kNONE_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 7U), /*!< Attach NONE to FLEXCAN0. */ + + kFRO_HF_to_FLEXCAN1 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN1, 1U), /*!< Attach FRO_HF to FLEXCAN1. */ + kFRO_HF_DIV_to_FLEXCAN1 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN1, 2U), /*!< Attach FRO_HF_DIV to FLEXCAN1. */ + kCLK_IN_to_FLEXCAN1 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN1, 3U), /*!< Attach CLK_IN to FLEXCAN1. */ + kPll1Clk_to_FLEXCAN1 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN1, 6U), /*!< Attach Pll1Clk to FLEXCAN1. */ + kNONE_to_FLEXCAN1 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN1, 7U), /*!< Attach NONE to FLEXCAN1. */ + + kFRO_LF_DIV_to_DAC0 = CLK_ATTACH_MUX(kCLOCK_SelDAC0, 0U), /*!< Attach FRO_LF_DIV to DAC0. */ + kFRO_HF_DIV_to_DAC0 = CLK_ATTACH_MUX(kCLOCK_SelDAC0, 2U), /*!< Attach FRO_HF_DIV to DAC0. */ + kCLK_IN_to_DAC0 = CLK_ATTACH_MUX(kCLOCK_SelDAC0, 3U), /*!< Attach CLK_IN to DAC0. */ + kCLK_1M_to_DAC0 = CLK_ATTACH_MUX(kCLOCK_SelDAC0, 5U), /*!< Attach CLK_1M to DAC0. */ + kPll1ClkDiv_to_DAC0 = CLK_ATTACH_MUX(kCLOCK_SelDAC0, 6U), /*!< Attach Pll1ClkDiv to DAC0. */ + kNONE_to_DAC0 = CLK_ATTACH_MUX(kCLOCK_SelDAC0, 7U), /*!< Attach NONE to DAC0. */ + + kFRO_LF_DIV_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 0U), /*!< Attach FRO_LF_DIV to LPI2C0. */ + kFRO_HF_DIV_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 2U), /*!< Attach FRO_HF_DIV to LPI2C0. */ + kCLK_IN_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 3U), /*!< Attach CLK_IN to LPI2C0. */ + kCLK_1M_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 5U), /*!< Attach CLK_1M to LPI2C0. */ + kPll1ClkDiv_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 6U), /*!< Attach Pll1ClkDiv to LPI2C0. */ + kNONE_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 7U), /*!< Attach NONE to LPI2C0. */ + + kFRO_LF_DIV_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 0U), /*!< Attach FRO_LF_DIV to LPI2C1. */ + kFRO_HF_DIV_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 2U), /*!< Attach FRO_HF_DIV to LPI2C1. */ + kCLK_IN_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 3U), /*!< Attach CLK_IN to LPI2C1. */ + kCLK_1M_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 5U), /*!< Attach CLK_1M to LPI2C1. */ + kPll1ClkDiv_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 6U), /*!< Attach Pll1ClkDiv to LPI2C1. */ + kNONE_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 7U), /*!< Attach NONE to LPI2C1. */ + + kFRO_LF_DIV_to_LPI2C2 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C2, 0U), /*!< Attach FRO_LF_DIV to LPI2C2. */ + kFRO_HF_DIV_to_LPI2C2 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C2, 2U), /*!< Attach FRO_HF_DIV to LPI2C2. */ + kCLK_IN_to_LPI2C2 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C2, 3U), /*!< Attach CLK_IN to LPI2C2. */ + kCLK_1M_to_LPI2C2 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C2, 5U), /*!< Attach CLK_1M to LPI2C2. */ + kPll1ClkDiv_to_LPI2C2 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C2, 6U), /*!< Attach Pll1ClkDiv to LPI2C2. */ + kNONE_to_LPI2C2 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C2, 7U), /*!< Attach NONE to LPI2C2. */ + + kFRO_LF_DIV_to_LPI2C3 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C3, 0U), /*!< Attach FRO_LF_DIV to LPI2C3. */ + kFRO_HF_DIV_to_LPI2C3 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C3, 2U), /*!< Attach FRO_HF_DIV to LPI2C3. */ + kCLK_IN_to_LPI2C3 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C3, 3U), /*!< Attach CLK_IN to LPI2C3. */ + kCLK_1M_to_LPI2C3 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C3, 5U), /*!< Attach CLK_1M to LPI2C3. */ + kPll1ClkDiv_to_LPI2C3 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C3, 6U), /*!< Attach Pll1ClkDiv to LPI2C3. */ + kNONE_to_LPI2C3 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C3, 7U), /*!< Attach NONE to LPI2C3. */ + + kFRO_LF_DIV_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 0U), /*!< Attach FRO_LF_DIV to LPSPI0. */ + kFRO_HF_DIV_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 2U), /*!< Attach FRO_HF_DIV to LPSPI0. */ + kCLK_IN_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 3U), /*!< Attach CLK_IN to LPSPI0. */ + kCLK_1M_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 5U), /*!< Attach CLK_1M to LPSPI0. */ + kPll1ClkDiv_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 6U), /*!< Attach Pll1ClkDiv to LPSPI0. */ + kNONE_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 7U), /*!< Attach NONE to LPSPI0. */ + + kFRO_LF_DIV_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 0U), /*!< Attach FRO_LF_DIV to LPSPI1. */ + kFRO_HF_DIV_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 2U), /*!< Attach FRO_HF_DIV to LPSPI1. */ + kCLK_IN_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 3U), /*!< Attach CLK_IN to LPSPI1. */ + kCLK_1M_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 5U), /*!< Attach CLK_1M to LPSPI1. */ + kPll1ClkDiv_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 6U), /*!< Attach Pll1ClkDiv to LPSPI1. */ + kNONE_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 7U), /*!< Attach NONE to LPSPI1. */ + + kFRO_LF_DIV_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 0U), /*!< Attach FRO_LF_DIV to LPUART0. */ + kFRO_HF_DIV_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 2U), /*!< Attach FRO_HF_DIV to LPUART0. */ + kCLK_IN_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 3U), /*!< Attach CLK_IN to LPUART0. */ + kCLK_16K_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 4U), /*!< Attach CLK_16K to LPUART0. */ + kCLK_1M_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 5U), /*!< Attach CLK_1M to LPUART0. */ + kPll1ClkDiv_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 6U), /*!< Attach Pll1ClkDiv to LPUART0. */ + kNONE_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 7U), /*!< Attach NONE to LPUART0. */ + + kFRO_LF_DIV_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 0U), /*!< Attach FRO_LF_DIV to LPUART1. */ + kFRO_HF_DIV_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 2U), /*!< Attach FRO_HF_DIV to LPUART1. */ + kCLK_IN_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 3U), /*!< Attach CLK_IN to LPUART1. */ + kCLK_16K_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 4U), /*!< Attach CLK_16K to LPUART1. */ + kCLK_1M_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 5U), /*!< Attach CLK_1M to LPUART1. */ + kPll1ClkDiv_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 6U), /*!< Attach Pll1ClkDiv to LPUART1. */ + kNONE_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 7U), /*!< Attach NONE to LPUART1. */ + + kFRO_LF_DIV_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 0U), /*!< Attach FRO_LF_DIV to LPUART2. */ + kFRO_HF_DIV_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 2U), /*!< Attach FRO_HF_DIV to LPUART2. */ + kCLK_IN_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 3U), /*!< Attach CLK_IN to LPUART2. */ + kCLK_16K_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 4U), /*!< Attach CLK_16K to LPUART2. */ + kCLK_1M_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 5U), /*!< Attach CLK_1M to LPUART2. */ + kPll1ClkDiv_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 6U), /*!< Attach Pll1ClkDiv to LPUART2. */ + kNONE_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 7U), /*!< Attach NONE to LPUART2. */ + + kFRO_LF_DIV_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 0U), /*!< Attach FRO_LF_DIV to LPUART2. */ + kFRO_HF_DIV_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 2U), /*!< Attach FRO_HF_DIV to LPUART2. */ + kCLK_IN_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 3U), /*!< Attach CLK_IN to LPUART2. */ + kCLK_16K_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 4U), /*!< Attach CLK_16K to LPUART2. */ + kCLK_1M_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 5U), /*!< Attach CLK_1M to LPUART2. */ + kPll1ClkDiv_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 6U), /*!< Attach Pll1ClkDiv to LPUART3. */ + kNONE_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 7U), /*!< Attach NONE to LPUART2. */ + + kFRO_LF_DIV_to_LPUART4 = CLK_ATTACH_MUX(kCLOCK_SelLPUART4, 0U), /*!< Attach FRO_LF_DIV to LPUART4. */ + kFRO_HF_DIV_to_LPUART4 = CLK_ATTACH_MUX(kCLOCK_SelLPUART4, 2U), /*!< Attach FRO_HF_DIV to LPUART4. */ + kCLK_IN_to_LPUART4 = CLK_ATTACH_MUX(kCLOCK_SelLPUART4, 3U), /*!< Attach CLK_IN to LPUART4. */ + kCLK_16K_to_LPUART4 = CLK_ATTACH_MUX(kCLOCK_SelLPUART4, 4U), /*!< Attach CLK_16K to LPUART4. */ + kCLK_1M_to_LPUART4 = CLK_ATTACH_MUX(kCLOCK_SelLPUART4, 5U), /*!< Attach CLK_1M to LPUART4. */ + kPll1ClkDiv_to_LPUART4 = CLK_ATTACH_MUX(kCLOCK_SelLPUART4, 6U), /*!< Attach Pll1ClkDiv to LPUART4. */ + kNONE_to_LPUART4 = CLK_ATTACH_MUX(kCLOCK_SelLPUART4, 7U), /*!< Attach NONE to LPUART4. */ + + kFRO_LF_DIV_to_LPUART5 = CLK_ATTACH_MUX(kCLOCK_SelLPUART5, 0U), /*!< Attach FRO_LF_DIV to LPUART5. */ + kFRO_HF_DIV_to_LPUART5 = CLK_ATTACH_MUX(kCLOCK_SelLPUART5, 2U), /*!< Attach FRO_HF_DIV to LPUART5. */ + kCLK_IN_to_LPUART5 = CLK_ATTACH_MUX(kCLOCK_SelLPUART5, 3U), /*!< Attach CLK_IN to LPUART5. */ + kCLK_16K_to_LPUART5 = CLK_ATTACH_MUX(kCLOCK_SelLPUART5, 4U), /*!< Attach CLK_16K to LPUART5. */ + kCLK_1M_to_LPUART5 = CLK_ATTACH_MUX(kCLOCK_SelLPUART5, 5U), /*!< Attach CLK_1M to LPUART5. */ + kPll1ClkDiv_to_LPUART5 = CLK_ATTACH_MUX(kCLOCK_SelLPUART5, 6U), /*!< Attach Pll1ClkDiv to LPUART5. */ + kNONE_to_LPUART5 = CLK_ATTACH_MUX(kCLOCK_SelLPUART5, 7U), /*!< Attach NONE to LPUART5. */ + + kPll1Clk_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 0U), /*!< Attach Pll1Clk to USB0. */ + kCLK_45M_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 1U), /*!< Attach FRO_HF to USB0. */ + kCLK_IN_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 2U), /*!< Attach CLK_IN to USB0. */ + kNONE_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 3U), /*!< Attach NONE to USB0. */ + + kFRO_LF_DIV_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 0U), /*!< Attach FRO_LF_DIV to LPTMR0. */ + kFRO_HF_DIV_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 2U), /*!< Attach FRO_HF_DIV to LPTMR0. */ + kCLK_IN_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 3U), /*!< Attach CLK_IN to LPTMR0. */ + kCLK_1M_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 5U), /*!< Attach CLK_1M to LPTMR0. */ + kPll1ClkDiv_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 6U), /*!< Attach Pll1ClkDiv to LPTMR0. */ + kNONE_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 7U), /*!< Attach NONE to LPTMR0. */ + + kCLK_16K_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 0U), /*!< Attach FRO16K to OSTIMER0. */ + kCLK_1M_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 2U), /*!< Attach CLK_1M to OSTIMER0. */ + kNONE_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 3U), /*!< Attach NONE to OSTIMER0. */ + + kFRO_LF_DIV_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 0U), /*!< Attach FRO_LF_DIV to ADC. */ + kFRO_HF_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 1U), /*!< Attach FRO_HF to ADC. */ + kCLK_IN_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 3U), /*!< Attach CLK_IN to ADC. */ + kCLK_1M_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 5U), /*!< Attach CLK_1M to ADC. */ + kPll1ClkDiv_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 6U), /*!< Attach Pll1ClkDiv to ADC. */ + kNONE_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 7U), /*!< Attach NONE to ADC. */ + + kFRO_LF_DIV_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 0U), /*!< Attach FRO_LF_DIV to CMP0. */ + kFRO_HF_DIV_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 2U), /*!< Attach FRO_HF_DIV to CMP0. */ + kCLK_IN_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 3U), /*!< Attach CLK_IN to CMP0. */ + kCLK_1M_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 5U), /*!< Attach CLK_1M to CMP0. */ + kPll1ClkDiv_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 6U), /*!< Attach Pll1ClkDiv to CMP0. */ + kNONE_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 7U), /*!< Attach NONE to CMP0. */ + + kFRO_LF_DIV_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 0U), /*!< Attach FRO_LF_DIV to CMP1. */ + kFRO_HF_DIV_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 2U), /*!< Attach FRO_HF_DIV to CMP1. */ + kCLK_IN_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 3U), /*!< Attach CLK_IN to CMP1. */ + kCLK_1M_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 5U), /*!< Attach CLK_1M to CMP1. */ + kPll1ClkDiv_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 6U), /*!< Attach Pll1ClkDiv to CMP1. */ + kNONE_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 7U), /*!< Attach NONE to CMP1. */ + + kFRO_LF_DIV_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 0U), /*!< Attach FRO_LF_DIV to CMP2. */ + kFRO_HF_DIV_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 2U), /*!< Attach FRO_HF_DIV to CMP2. */ + kCLK_IN_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 3U), /*!< Attach CLK_IN to CMP2. */ + kCLK_1M_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 5U), /*!< Attach CLK_1M to CMP2. */ + kPll1ClkDiv_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 6U), /*!< Attach Pll1ClkDiv to CMP2. */ + kNONE_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 7U), /*!< Attach NONE to CMP2. */ + + kCPU_CLK_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 0U), /*!< Attach CPU_CLK to TRACE. */ + kCLK_1M_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 1U), /*!< Attach CLK_1M to TRACE. */ + kCLK_16K_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 2U), /*!< Attach CLK_16K to TRACE. */ + kNONE_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 3U), /*!< Attach NONE to TRACE. */ + + kFRO12M_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 0U), /*!< Attach FRO_12M to CLKOUT. */ + kFRO_HF_DIV_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 1U), /*!< Attach FRO_HF_DIV to CLKOUT. */ + kCLK_IN_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 2U), /*!< Attach CLK_IN to CLKOUT. */ + kCLK_16K_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 3U), /*!< Attach CLK_16K to CLKOUT. */ + kPll1Clk_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 5U), /*!< Attach Pll1Clk to CLKOUT. */ + kSLOW_CLK_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 6U), /*!< Attach SLOW_CLK to CLKOUT. */ + kNONE_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 7U), /*!< Attach NONE to CLKOUT. */ + + kNONE_to_NONE = (0xFFFFFFFFU), /*!< Attach NONE to NONE. */ + +} clock_attach_id_t; + +/*! @brief Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivI3C0_FCLK = (0x0A4U), /*!< I3C0_FCLK clock divider */ + kCLOCK_DivCTIMER0 = (0x0ACU), /*!< CTIMER0 clock divider */ + kCLOCK_DivCTIMER1 = (0x0B4U), /*!< CTIMER1 clock divider */ + kCLOCK_DivCTIMER2 = (0x0BCU), /*!< CTIMER2 clock divider */ + kCLOCK_DivCTIMER3 = (0x0C4U), /*!< CTIMER3 clock divider */ + kCLOCK_DivCTIMER4 = (0x0CCU), /*!< CTIMER4 clock divider */ + kCLOCK_DivWWDT0 = (0x0D4U), /*!< WWDT0 clock divider */ + kCLOCK_DivFLEXIO0 = (0x0DCU), /*!< FLEXIO0 clock divider */ + kCLOCK_DivLPI2C0 = (0x0E4U), /*!< LPI2C0 clock divider */ + kCLOCK_DivLPI2C1 = (0x0ECU), /*!< LPI2C1 clock divider */ + kCLOCK_DivLPSPI0 = (0x0F4U), /*!< LPSPI0 clock divider */ + kCLOCK_DivLPSPI1 = (0x0FCU), /*!< LPSPI1 clock divider */ + kCLOCK_DivLPUART0 = (0x104U), /*!< LPUART0 clock divider */ + kCLOCK_DivLPUART1 = (0x10CU), /*!< LPUART1 clock divider */ + kCLOCK_DivLPUART2 = (0x114U), /*!< LPUART2 clock divider */ + kCLOCK_DivLPUART3 = (0x11CU), /*!< LPUART3 clock divider */ + kCLOCK_DivLPUART4 = (0x124U), /*!< LPUART4 clock divider */ + kCLOCK_DivUSB0 = (0x12CU), /*!< USB0 clock divider */ + kCLOCK_DivLPTMR0 = (0x134U), /*!< LPTMR0 clock divider */ + kCLOCK_DivADC = (0x144U), /*!< ADC clock divider */ + kCLOCK_DivCMP0_FUNC = (0x14CU), /*!< CMP0_FUNC clock divider */ + kCLOCK_DivCMP0_RR = (0x154U), /*!< CMP0_RR clock divider */ + kCLOCK_DivCMP1_FUNC = (0x15CU), /*!< CMP1_FUNC clock divider */ + kCLOCK_DivCMP1_RR = (0x164U), /*!< CMP1_RR clock divider */ + kCLOCK_DivCMP2_FUNC = (0x16CU), /*!< CMP2_FUNC clock divider */ + kCLOCK_DivCMP2_RR = (0x174U), /*!< CMP2_RR clock divider */ + kCLOCK_DivDAC0 = (0x17CU), /*!< DAC0 clock divider */ + kCLOCK_DivFLEXCAN0 = (0x184U), /*!< FLEXCAN0 clock divider */ + kCLOCK_DivFLEXCAN1 = (0x18CU), /*!< FLEXCAN1 clock divider */ + kCLOCK_DivLPI2C2 = (0x194U), /*!< LPI2C2 clock divider */ + kCLOCK_DivLPI2C3 = (0x19CU), /*!< LPI2C3 clock divider */ + kCLOCK_DivLPUART5 = (0x1A4U), /*!< LPUART5 clock divider */ + kCLOCK_DivTRACE = (0x1ACU), /*!< DBG_TRACE clock divider */ + kCLOCK_DivCLKOUT = (0x1B4U), /*!< CLKOUT clock divider */ + kCLOCK_DivSLOWCLK = (0x378U), /*!< SLOWCLK clock divider */ + kCLOCK_DivBUSCLK = (0x37CU), /*!< BUSCLK clock divider */ + kCLOCK_DivAHBCLK = (0x380U), /*!< AHBCLK clock divider */ + kCLOCK_DivFRO_HF = (0x388U), /*!< FROHF clock divider */ + kCLOCK_DivFRO_LF = (0x38CU), /*!< FROLF clock divider */ + kCLOCK_DivPLL1CLK = (0x3E4U), /*!< PLL1CLK clock divider */ + kCLOCK_DivMax = (0x3E4U), /*!< MAX clock divider */ +} clock_div_name_t; + +/*! + * @brief firc trim source. + */ +typedef enum _clke_16k +{ + kCLKE_16K_SYSTEM = VBAT_FROCLKE_CLKE(1U), /*!< To VSYS domain. */ + kCLKE_16K_COREMAIN = VBAT_FROCLKE_CLKE(2U) /*!< To VDD_CORE domain. */ +} clke_16k_t; + +/*! + * @brief SCG status return codes. + */ +enum _scg_status +{ + kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), /*!< Clock is busy. */ + kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */ +}; + +/*! + * @brief sirc trim mode. + */ +typedef enum _sirc_trim_mode +{ + kSCG_SircTrimNonUpdate = SCG_SIRCCSR_SIRCTREN_MASK, + /*!< Trim enable but not enable trim value update. In this mode, the + trim value is fixed to the initialized value which is defined by + trimCoar and trimFine in configure structure \ref sirc_trim_mode_t.*/ + + kSCG_SircTrimUpdate = SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK + /*!< Trim enable and trim value update enable. In this mode, the trim + value is auto update. */ + +} sirc_trim_mode_t; + +/*! + * @brief sirc trim source. + */ +typedef enum _sirc_trim_src +{ + kNoTrimSrc = 0, /*!< No external tirm source. */ + kSCG_SircTrimSrcSysOsc = 2U /*!< System OSC. */ +} sirc_trim_src_t; + +/*! + * @brief sirc trim configuration. + */ +typedef struct _sirc_trim_config +{ + sirc_trim_mode_t trimMode; /*!< Trim mode. */ + sirc_trim_src_t trimSrc; /*!< Trim source. */ + uint16_t trimDiv; /*!< Divider of SOSC. */ + uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ +} sirc_trim_config_t; + +/*! + * @brief SCG system OSC monitor mode. + */ +typedef enum _scg_sosc_monitor_mode +{ + kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC error is detected. */ + kSCG_SysOscMonitorReset = + SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */ +} scg_sosc_monitor_mode_t; + +/*! + * @brief SCG PLL1 monitor mode. + */ +typedef enum _scg_pll1_monitor_mode +{ + kSCG_Pll1MonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_Pll1MonitorInt = SCG_SPLLCSR_SPLLCM_MASK, /*!< Interrupt when the PLL1 Clock error is detected. */ + kSCG_Pll1MonitorReset = + SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK /*!< Reset when the PLL1 Clock error is detected. */ +} scg_pll1_monitor_mode_t; + +/*! + * @brief The active run mode (voltage level). + */ +typedef enum _run_mode +{ + kMD_Mode, /*!< Mid voltage (1.0 V). */ + kOD_Mode, /*!< Overdrive voltage (1.2 V). */ +} run_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); + uint32_t bit_shift = CLK_GATE_BIT_SHIFT(clk); + volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); + + if (clk == kCLOCK_GateNotAvail) + { + return; + } + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + if (reg_offset == REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL |= (1UL << bit_shift); + MRCC0->MRCC_GLB_CC0_SET = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK; + } + else if (reg_offset == REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL |= (1UL << bit_shift); + MRCC0->MRCC_GLB_CC1_SET = MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK; + } + else + { + *pClkCtrl = (1UL << bit_shift); + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); + uint32_t bit_shift = CLK_GATE_BIT_SHIFT(clk); + volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); + + if (clk == kCLOCK_GateNotAvail) + { + return; + } + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + if (reg_offset == REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL &= ~(1UL << bit_shift); + + if (0U == (SYSCON->PWM0SUBCTL & 0xFU)) + { + MRCC0->MRCC_GLB_CC0_CLR = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK; + } + } + else if (reg_offset == REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL &= ~(1UL << bit_shift); + + if (0U == (SYSCON->PWM1SUBCTL & 0xFU)) + { + MRCC0->MRCC_GLB_CC1_CLR = MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK; + } + } + else + { + *pClkCtrl = (1UL << bit_shift); + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + */ +void CLOCK_AttachClk(clock_attach_id_t connection); + +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param connection : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection); + +/** + * @brief Set the clock select value. + * This fuction set the peripheral clock select value. + * @param sel_name : Clock select. + * @param value : value to be set. + */ +void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value); + +/** + * @brief Get the clock select value. + * This fuction get the peripheral clock select value. + * @param sel_name : Clock select. + * @return Clock source value. + */ +uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name); + +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param value : Value to be divided + */ +void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value); + +/** + * @brief Get peripheral clock dividers. + * @param div_name : Clock divider name + * @return peripheral clock dividers + */ +uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name); + +/** + * @brief Halt peripheral clock dividers. + * @param div_name : Clock divider name + */ +void CLOCK_HaltClockDiv(clock_div_name_t div_name); + +/** + * @brief Initialize the FROHF to given frequency. + * This function turns on FIRC and select the given frequency as the source of fro_hf + * @param iFreq : Desired frequency. + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq); + +/** + * @brief Initialize the FRO12M. + * This function turns on FRO12M. + * @return returns success or fail status. + */ +status_t CLOCK_SetupFRO12MClocking(void); + +/** + * @brief Initialize the FRO16K. + * This function turns on FRO16K. + * @param clk_16k_enable_mask: 0-3 + * 0b00: disable both clk_16k0 and clk_16k1 + * 0b01: only enable clk_16k0 + * 0b10: only enable clk_16k1 + * 0b11: enable both clk_16k0 and clk_16k1 + * @return returns success or fail status. + */ +status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask); + +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); + +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! @brief Return Frequency of core + * @return Frequency of the core + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! @brief Return Frequency of I3C FCLK + * @return Frequency of I3C FCLK. + */ +uint32_t CLOCK_GetI3CFClkFreq(void); + +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPI2C0 functional Clock + * @return Frequency of LPI2C0 functional Clock + */ +uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPSPI functional Clock + * @return Frequency of LPSPI functional Clock + */ +uint32_t CLOCK_GetLpspiClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPUART functional Clock + * @return Frequency of LPUART functional Clock + */ +uint32_t CLOCK_GetLpuartClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPTMR functional Clock + * @return Frequency of LPTMR functional Clock + */ +uint32_t CLOCK_GetLptmrClkFreq(void); + +/*! @brief Return Frequency of OSTIMER + * @return Frequency of OSTIMER Clock + */ +uint32_t CLOCK_GetOstimerClkFreq(void); + +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id); + +/*! @brief Return Frequency of Dac Clock + * @return Frequency of Dac. + */ +uint32_t CLOCK_GetDacClkFreq(void); + +/*! @brief Return Frequency of CMP Function Clock + * @return Frequency of CMP Function. + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id); + +/*! @brief Return Frequency of CMP Round Robin Clock + * @return Frequency of CMP Round Robin. + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id); + +/*! @brief Return Frequency of Trace Clock + * @return Frequency of Trace. + */ +uint32_t CLOCK_GetTraceClkFreq(void); + +/*! @brief Return Frequency of CLKOUT Clock + * @return Frequency of CLKOUT. + */ +uint32_t CLOCK_GetClkoutClkFreq(void); + +/*! brief Return Frequency of WWDT Clock + * return Frequency of WWDT. + */ +uint32_t CLOCK_GetWwdtClkFreq(void); + +/*! @brief Return Frequency of FLEXIO FCLK + * @return Frequency of FLEXIO FCLK. + */ +uint32_t CLOCK_GetFlexioClkFreq(void); + +/*! @brief Return Frequency of FlexCAN FCLK + * @return Frequency of FlexCAN FCLK. + */ +uint32_t CLOCK_GetFlexcanClkFreq(uint32_t id); + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config); + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode); + +/*! brief Enable USB FS clock. + * Enable USB Full Speed clock. + */ +bool CLOCK_EnableUsbfsClock(void); + +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash + * access time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode); + +/*! + * @brief Sets the PLL1 monitor mode. + * + * This function sets the PLL1 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SCG0->SPLLCSR & SCG_SPLLCSR_SPLL_LOCK_MASK) != 0UL); +} + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! + * @brief PLL clock source. + */ +typedef enum _pll_clk_src +{ + kPll_ClkSrcSysOsc = (0 << 25), /*!< System OSC. */ + kPll_ClkSrcFirc = (1 << 25), /*!< Fast IRC. */ + kPll_ClkSrcSirc = (3 << 25), /*!< Slow IRC. */ +} pll_clk_src_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 2), /*!< Nss = 512 (fm ~= 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 2), /*!< Nss ~= 384 (fm ~= 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 2), /*!< Nss = 256 (fm ~= 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 2), /*!< Nss = 128 (fm ~= 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 2), /*!< Nss = 64 (fm ~= 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 2), /*!< Nss = 32 (fm ~= 62.5 - 125 kHz) */ + kSS_MF_24 = (6 << 2), /*!< Nss ~= 24 (fm ~= 83.3 - 166.6 kHz) */ + kSS_MF_16 = (7 << 2) /*!< Nss = 16 (fm ~= 125 - 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 5), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 5), /*!< k ~= 1 */ + kSS_MR_K1_5 = (2 << 5), /*!< k ~= 1.5 */ + kSS_MR_K2 = (3 << 5), /*!< k ~= 2 */ + kSS_MR_K3 = (4 << 5), /*!< k ~= 3 */ + kSS_MR_K4 = (5 << 5), /*!< k ~= 4 */ + kSS_MR_K6 = (6 << 5), /*!< k ~= 6 */ + kSS_MR_K8 = (7 << 5) /*!< k ~= 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 8), /*!< no compensation */ + kSS_MC_RECC = (2 << 8), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 8), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputSource; /*!< PLL input source */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag + */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL Control register APLLCTRL */ + uint32_t pllndiv; /*!< PLL N Divider register APLLNDIV */ + uint32_t pllpdiv; /*!< PLL P Divider register APLLPDIV */ + uint32_t pllmdiv; /*!< PLL M Divider register APLLMDIV */ + uint32_t pllsscg[2]; /*!< PLL Spread Spectrum Control registers APLLSSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_OutputError = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL output rate error */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 8) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief Return PLL0 output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLLOutFromSetup(pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the passed PLL setup data + * @param pControl : Pointer to populated PLL control structure to generate setup with + * @param pSetup : Pointer to PLL setup structure to be filled + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_edma_soc.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_edma_soc.c new file mode 100644 index 000000000..97635fbfb --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_edma_soc.c @@ -0,0 +1,112 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma_soc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma_soc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +extern void DMA_CH0_DriverIRQHandler(void); +extern void DMA_CH1_DriverIRQHandler(void); +extern void DMA_CH2_DriverIRQHandler(void); +extern void DMA_CH3_DriverIRQHandler(void); +extern void DMA_CH4_DriverIRQHandler(void); +extern void DMA_CH5_DriverIRQHandler(void); +extern void DMA_CH6_DriverIRQHandler(void); +extern void DMA_CH7_DriverIRQHandler(void); +extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief DMA instance 0, channel 0 IRQ handler. + * + */ +void DMA_CH0_DriverIRQHandler(void) +{ + /* Instance 0 channel 0 */ + EDMA_DriverIRQHandler(0U, 0U); +} + +/*! + * brief DMA instance 0, channel 1 IRQ handler. + * + */ +void DMA_CH1_DriverIRQHandler(void) +{ + /* Instance 0 channel 1 */ + EDMA_DriverIRQHandler(0U, 1U); +} + +/*! + * brief DMA instance 0, channel 2 IRQ handler. + * + */ +void DMA_CH2_DriverIRQHandler(void) +{ + /* Instance 0 channel 2 */ + EDMA_DriverIRQHandler(0U, 2U); +} + +/*! + * brief DMA instance 0, channel 3 IRQ handler. + * + */ +void DMA_CH3_DriverIRQHandler(void) +{ + /* Instance 0 channel 3 */ + EDMA_DriverIRQHandler(0U, 3U); +} + +/*! + * brief DMA instance 0, channel 4 IRQ handler. + * + */ +void DMA_CH4_DriverIRQHandler(void) +{ + /* Instance 0 channel 4 */ + EDMA_DriverIRQHandler(0U, 4U); +} +/*! + * brief DMA instance 0, channel 5 IRQ handler. + * + */ +void DMA_CH5_DriverIRQHandler(void) +{ + /* Instance 0 channel 5 */ + EDMA_DriverIRQHandler(0U, 5U); +} + +/*! + * brief DMA instance 0, channel 6 IRQ handler. + * + */ +void DMA_CH6_DriverIRQHandler(void) +{ + /* Instance 0 channel 6 */ + EDMA_DriverIRQHandler(0U, 6U); +} + +/*! + * brief DMA instance 0, channel 7 IRQ handler. + * + */ +void DMA_CH7_DriverIRQHandler(void) +{ + /* Instance 0 channel 7 */ + EDMA_DriverIRQHandler(0U, 7U); +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_edma_soc.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_edma_soc.h new file mode 100644 index 000000000..b28b39789 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_edma_soc.h @@ -0,0 +1,64 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_EDMA_SOC_H_ +#define _FSL_EDMA_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.0. */ +#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*!@brief DMA IP version */ +#define FSL_EDMA_SOC_IP_DMA3 (1) +#define FSL_EDMA_SOC_IP_DMA4 (0) + +/*!@brief DMA base table */ +#define EDMA_BASE_PTRS \ + { \ + DMA0 \ + } + +#define EDMA_CHN_IRQS \ + { \ + { \ + DMA_CH0_IRQn, DMA_CH1_IRQn, DMA_CH2_IRQn, DMA_CH3_IRQn, DMA_CH4_IRQn, DMA_CH5_IRQn, DMA_CH6_IRQn, \ + DMA_CH7_IRQn \ + } \ + } + +/*!@brief EDMA base address convert macro */ +#define EDMA_CHANNEL_OFFSET 0x1000U +#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U) + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_EDMA_SOC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_inputmux_connections.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_inputmux_connections.h new file mode 100644 index 000000000..cee5b5ea6 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_inputmux_connections.h @@ -0,0 +1,4648 @@ +/* + * Copyright 2025 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief INPUTMUX_CONNECTION driver version 2.0.0. */ +#define FSL_INPUTMUX_CONNECTION_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define INPUTMUX_GpioPortPinToPintsel(port, pin) ((pin) + (PINTSEL_PMUX_ID << PMUX_SHIFT)) + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define TIMER0CAPTSEL0 (0x020U) +#define TIMER0TRIGIN (0x030U) +#define TIMER1CAPTSEL0 (0x040U) +#define TIMER1TRIGIN (0x050U) +#define TIMER2CAPTSEL0 (0x060U) +#define TIMER2TRIGIN (0x070U) +#define SMARTDMA0_TRIG0_REG (0x0A0U) +#define FREQMEAS_REF_REG (0x180U) +#define FREQMEAS_TAR_REG (0x184U) +#define TIMER3CAPTSEL0 (0x1A0U) +#define TIMER3TRIGIN (0x1B0U) +#define TIMER4CAPTSEL0 (0x1C0U) +#define TIMER4TRIGIN (0x1D0U) +#define AOI1_MUX_REG (0x200U) +#define CMP0_TRIG_REG (0x260U) +#define ADC0_TRIG0_REG (0x280U) +#define ADC2_TRIG0_REG (0x2A0U) +#define ADC1_TRIG0_REG (0x2C0U) +#define ADC3_TRIG0_REG (0x2E0U) +#define DAC0_TRIG0_REG (0x300U) +#define QDC0_TRIG_REG (0x360U) +#define QDC0_HOME_REG (0x364U) +#define QDC0_INDEX_REG (0x368U) +#define QDC0_PHASEB_REG (0x36CU) +#define QDC0_PHASEA_REG (0x370U) +#define QDC0_ICAP0_REG (0x370U) +#define QDC1_TRIG_REG (0x380U) +#define QDC1_HOME_REG (0x384U) +#define QDC1_INDEX_REG (0x388U) +#define QDC1_PHASEB_REG (0x38CU) +#define QDC1_PHASEA_REG (0x390U) +#define QDC1_ICAP0_REG (0x390U) +#define FlexPWM0_SM0_EXTA0_REG (0x3A0U) +#define FlexPWM0_SM0_EXTSYNC0_REG (0x3A4U) +#define FlexPWM0_SM1_EXTA1_REG (0x3A8U) +#define FlexPWM0_SM1_EXTSYNC1_REG (0x3ACU) +#define FlexPWM0_SM2_EXTA2_REG (0x3B0U) +#define FlexPWM0_SM2_EXTSYNC2_REG (0x3B4U) +#define FlexPWM0_SM3_EXTA3_REG (0x3B8U) +#define FlexPWM0_SM3_EXTSYNC3_REG (0x3BCU) +#define FlexPWM0_FAULT_REG (0x3C0U) +#define FlexPWM0_FORCE_REG (0x3D0U) +#define FlexPWM1_SM0_EXTA0_REG (0x3E0U) +#define FlexPWM1_SM0_EXTSYNC0_REG (0x3E4U) +#define FlexPWM1_SM1_EXTA1_REG (0x3E8U) +#define FlexPWM1_SM1_EXTSYNC1_REG (0x3ECU) +#define FlexPWM1_SM2_EXTA2_REG (0x3F0U) +#define FlexPWM1_SM2_EXTSYNC2_REG (0x3F4U) +#define FlexPWM1_SM3_EXTA3_REG (0x3F8U) +#define FlexPWM1_SM3_EXTSYNC3_REG (0x3FCU) +#define FlexPWM1_FAULT_REG (0x400U) +#define FlexPWM1_FORCE_REG (0x410U) +#define PWM0_EXT_CLK_REG (0x420U) +#define PWM1_EXT_CLK_REG (0x424U) +#define AOI0_MUX_REG (0x440U) +#define USBFS_TRIG_REG (0x480U) +#define EXT_TRIG0_REG (0x4C0U) +#define CMP1_TRIG_REG (0x4E0U) +#define CMP2_TRIG_REG (0x500U) +#define LPI2C2_TRIG_REG (0x540U) +#define LPI2C3_TRIG_REG (0x560U) +#define LPI2C0_TRIG_REG (0x5A0U) +#define LPI2C1_TRIG_REG (0x5C0U) +#define LPSPI0_TRIG_REG (0x5E0U) +#define LPSPI1_TRIG_REG (0x600U) +#define LPUART0_TRIG_REG (0x620U) +#define LPUART1_TRIG_REG (0x640U) +#define LPUART2_TRIG_REG (0x660U) +#define LPUART3_TRIG_REG (0x680U) +#define LPUART4_TRIG_REG (0x6A0U) +#define LPUART5_TRIG_REG (0x6C0U) +#define FLEXIO_TRIG0_REG (0x6E0U) +#define PMUX_SHIFT (20U) + +typedef enum _inputmux_index_t +{ + kINPUTMUX_INDEX_CTIMER0CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER0CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER0CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER0CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER3CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER3CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER3CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER3CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER4CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER4CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER4CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER4CAPTSEL3 = 3U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL5 = 5U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL7 = 7U, + kINPUTMUX_INDEX_ADC0_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_ADC0_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_ADC0_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_ADC0_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_ADC1_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_ADC1_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_ADC1_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_ADC1_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_ADC2_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_ADC2_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_ADC2_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_ADC2_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_ADC3_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_ADC3_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_ADC3_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_ADC3_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_QDC0_ICAPSEL1 = 1U, + kINPUTMUX_INDEX_QDC0_ICAPSEL2 = 2U, + kINPUTMUX_INDEX_QDC0_ICAPSEL3 = 3U, + kINPUTMUX_INDEX_QDC1_ICAPSEL1 = 1U, + kINPUTMUX_INDEX_QDC1_ICAPSEL2 = 2U, + kINPUTMUX_INDEX_QDC1_ICAPSEL3 = 3U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL0 = 0U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL1 = 1U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL2 = 2U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL3 = 3U, + kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL0 = 0U, + kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL1 = 1U, + kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL2 = 2U, + kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL3 = 3U, + kINPUTMUX_INDEX_AOI0_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_AOI0_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_AOI0_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_AOI0_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_AOI0_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_AOI0_TRIGSEL5 = 5U, + kINPUTMUX_INDEX_AOI0_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_AOI0_TRIGSEL7 = 7U, + kINPUTMUX_INDEX_AOI0_TRIGSEL8 = 8U, + kINPUTMUX_INDEX_AOI0_TRIGSEL9 = 9U, + kINPUTMUX_INDEX_AOI0_TRIGSEL10 = 10U, + kINPUTMUX_INDEX_AOI0_TRIGSEL11 = 11U, + kINPUTMUX_INDEX_AOI0_TRIGSEL12 = 12U, + kINPUTMUX_INDEX_AOI0_TRIGSEL13 = 13U, + kINPUTMUX_INDEX_AOI0_TRIGSEL14 = 14U, + kINPUTMUX_INDEX_AOI0_TRIGSEL15 = 15U, + kINPUTMUX_INDEX_AOI1_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_AOI1_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_AOI1_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_AOI1_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_AOI1_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_AOI1_TRIGSEL5 = 5U, + kINPUTMUX_INDEX_AOI1_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_AOI1_TRIGSEL7 = 7U, + kINPUTMUX_INDEX_AOI1_TRIGSEL8 = 8U, + kINPUTMUX_INDEX_AOI1_TRIGSEL9 = 9U, + kINPUTMUX_INDEX_AOI1_TRIGSEL10 = 10U, + kINPUTMUX_INDEX_AOI1_TRIGSEL11 = 11U, + kINPUTMUX_INDEX_AOI1_TRIGSEL12 = 12U, + kINPUTMUX_INDEX_AOI1_TRIGSEL13 = 13U, + kINPUTMUX_INDEX_AOI1_TRIGSEL14 = 14U, + kINPUTMUX_INDEX_AOI1_TRIGSEL15 = 15U, + kINPUTMUX_INDEX_EXT_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_EXT_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_EXT_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_EXT_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_EXT_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_EXT_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_EXT_TRIGSEL7 = 7U, + kINPUTMUX_INDEX_FLEXIO_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_FLEXIO_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_FLEXIO_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_FLEXIO_TRIGSEL3 = 3U +} inputmux_index_t; + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer0Captsel = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer0Captsel = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer0Captsel = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer0Captsel = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer0Captsel = 29U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Captsel = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Captsel = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer0Captsel = 32U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer0Captsel = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer0Captsel = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer0Captsel = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer0Captsel = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer0Captsel = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer0Captsel = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer0Captsel = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer0Captsel = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer0Captsel = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Captsel = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Captsel = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Captsel = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer0Captsel = 47U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Captsel = 48U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Captsel = 49U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer0Captsel = 50U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer0Captsel = 51U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer0Captsel = 52U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Captsel = 53U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer0Captsel = 54U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Captsel = 55U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Captsel = 56U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Captsel = 57U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Captsel = 58U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Captsel = 59U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Captsel = 60U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Captsel = 61U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Captsel = 62U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Captsel = 63U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Captsel = 64U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Captsel = 65U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Captsel = 66U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Captsel = 67U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Captsel = 68U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Captsel = 69U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Captsel = 70U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer0Captsel = 71U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer0Captsel = 72U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer0Captsel = 73U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer0Captsel = 74U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer0Captsel = 75U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer0Captsel = 76U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer0Captsel = 77U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer0Captsel = 78U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer0Captsel = 79U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer0Captsel = 80U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer0Captsel = 81U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer0Captsel = 82U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer0Captsel = 83U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer0Captsel = 84U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer0Captsel = 85U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer0Captsel = 86U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer0Captsel = 87U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer0Captsel = 88U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer0Captsel = 89U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Captsel = 90U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Captsel = 91U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Captsel = 92U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer0Captsel = 93U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Captsel = 94U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Captsel = 95U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Captsel = 96U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Captsel = 97U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer0Captsel = 98U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer0Captsel = 99U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer0Captsel = 100U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer0Captsel = 105U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer0Captsel = 106U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer0Captsel = 107U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer0Captsel = 108U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer0Captsel = 109U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer0Captsel = 110U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer0Captsel = 111U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer0Captsel = 112U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer1Captsel = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer1Captsel = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer1Captsel = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer1Captsel = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer1Captsel = 29U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Captsel = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Captsel = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer1Captsel = 32U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer1Captsel = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer1Captsel = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer1Captsel = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer1Captsel = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer1Captsel = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer1Captsel = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer1Captsel = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer1Captsel = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer1Captsel = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Captsel = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Captsel = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Captsel = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer1Captsel = 47U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Captsel = 48U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Captsel = 49U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer1Captsel = 50U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer1Captsel = 51U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer1Captsel = 52U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Captsel = 53U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer1Captsel = 54U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Captsel = 55U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Captsel = 56U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Captsel = 57U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Captsel = 58U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Captsel = 59U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Captsel = 60U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Captsel = 61U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Captsel = 62U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Captsel = 63U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Captsel = 64U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Captsel = 65U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Captsel = 66U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Captsel = 67U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Captsel = 68U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Captsel = 69U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Captsel = 70U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer1Captsel = 71U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer1Captsel = 72U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer1Captsel = 73U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer1Captsel = 74U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer1Captsel = 75U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer1Captsel = 76U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer1Captsel = 77U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer1Captsel = 78U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer1Captsel = 79U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer1Captsel = 80U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer1Captsel = 81U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer1Captsel = 82U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer1Captsel = 83U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer1Captsel = 84U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer1Captsel = 85U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer1Captsel = 86U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer1Captsel = 87U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer1Captsel = 88U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer1Captsel = 89U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Captsel = 90U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Captsel = 91U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Captsel = 92U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer1Captsel = 93U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Captsel = 94U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Captsel = 95U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Captsel = 96U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Captsel = 97U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer1Captsel = 98U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer1Captsel = 99U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer1Captsel = 100U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer1Captsel = 105U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer1Captsel = 106U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer1Captsel = 107U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer1Captsel = 108U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer1Captsel = 109U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer1Captsel = 110U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer1Captsel = 111U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer1Captsel = 112U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer2Captsel = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer2Captsel = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer2Captsel = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer2Captsel = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer2Captsel = 29U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Captsel = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Captsel = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer2Captsel = 32U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer2Captsel = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer2Captsel = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer2Captsel = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer2Captsel = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer2Captsel = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer2Captsel = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer2Captsel = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer2Captsel = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer2Captsel = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Captsel = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Captsel = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Captsel = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer2Captsel = 47U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Captsel = 48U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Captsel = 49U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer2Captsel = 50U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer2Captsel = 51U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer2Captsel = 52U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Captsel = 53U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer2Captsel = 54U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Captsel = 55U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Captsel = 56U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Captsel = 57U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Captsel = 58U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Captsel = 59U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Captsel = 60U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Captsel = 61U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Captsel = 62U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Captsel = 63U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Captsel = 64U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Captsel = 65U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Captsel = 66U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Captsel = 67U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Captsel = 68U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Captsel = 69U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Captsel = 70U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer2Captsel = 71U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer2Captsel = 72U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer2Captsel = 73U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer2Captsel = 74U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer2Captsel = 75U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer2Captsel = 76U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer2Captsel = 77U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer2Captsel = 78U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer2Captsel = 79U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer2Captsel = 80U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer2Captsel = 81U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer2Captsel = 82U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer2Captsel = 83U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer2Captsel = 84U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer2Captsel = 85U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer2Captsel = 86U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer2Captsel = 87U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer2Captsel = 88U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer2Captsel = 89U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Captsel = 90U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Captsel = 91U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Captsel = 92U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer2Captsel = 93U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Captsel = 94U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Captsel = 95U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Captsel = 96U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Captsel = 97U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer2Captsel = 98U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer2Captsel = 99U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer2Captsel = 100U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer2Captsel = 105U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer2Captsel = 106U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer2Captsel = 107U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer2Captsel = 108U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer2Captsel = 109U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer2Captsel = 110U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer2Captsel = 111U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer2Captsel = 112U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer3Captsel = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer3Captsel = 26U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer3Captsel = 27U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer3Captsel = 28U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer3Captsel = 29U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Captsel = 30U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Captsel = 31U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer3Captsel = 32U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer3Captsel = 33U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer3Captsel = 34U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer3Captsel = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer3Captsel = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer3Captsel = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer3Captsel = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer3Captsel = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer3Captsel = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer3Captsel = 43U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Captsel = 44U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Captsel = 45U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Captsel = 46U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer3Captsel = 47U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Captsel = 48U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Captsel = 49U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer3Captsel = 50U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer3Captsel = 51U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer3Captsel = 52U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Captsel = 53U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer3Captsel = 54U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Captsel = 55U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Captsel = 56U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Captsel = 57U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Captsel = 58U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Captsel = 59U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Captsel = 60U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Captsel = 61U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Captsel = 62U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Captsel = 63U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Captsel = 64U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Captsel = 65U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Captsel = 66U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Captsel = 67U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Captsel = 68U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Captsel = 69U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Captsel = 70U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer3Captsel = 71U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer3Captsel = 72U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer3Captsel = 73U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer3Captsel = 74U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer3Captsel = 75U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer3Captsel = 76U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer3Captsel = 77U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer3Captsel = 78U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer3Captsel = 79U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer3Captsel = 80U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer3Captsel = 81U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer3Captsel = 82U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer3Captsel = 83U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer3Captsel = 84U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer3Captsel = 85U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer3Captsel = 86U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer3Captsel = 87U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer3Captsel = 88U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer3Captsel = 89U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Captsel = 90U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Captsel = 91U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Captsel = 92U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer3Captsel = 93U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Captsel = 94U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Captsel = 95U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Captsel = 96U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Captsel = 97U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer3Captsel = 98U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer3Captsel = 99U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer3Captsel = 100U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer3Captsel = 105U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer3Captsel = 106U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer3Captsel = 107U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer3Captsel = 108U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer3Captsel = 109U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer3Captsel = 110U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer3Captsel = 111U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer3Captsel = 112U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToTimer3Captsel = 113U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToTimer3Captsel = 114U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToTimer3Captsel = 115U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToTimer3Captsel = 116U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToTimer3Captsel = 117U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToTimer3Captsel = 118U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToTimer3Captsel = 119U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToTimer3Captsel = 120U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToTimer3Captsel = 121U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToTimer3Captsel = 122U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToTimer3Captsel = 123U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToTimer3Captsel = 124U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer4Captsel = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer4Captsel = 26U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer4Captsel = 27U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer4Captsel = 28U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer4Captsel = 29U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Captsel = 30U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Captsel = 31U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer4Captsel = 32U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer4Captsel = 33U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer4Captsel = 34U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer4Captsel = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer4Captsel = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer4Captsel = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer4Captsel = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer4Captsel = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer4Captsel = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer4Captsel = 43U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Captsel = 44U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Captsel = 45U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Captsel = 46U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer4Captsel = 47U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Captsel = 48U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Captsel = 49U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer4Captsel = 50U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer4Captsel = 51U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer4Captsel = 52U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Captsel = 53U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer4Captsel = 54U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Captsel = 55U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Captsel = 56U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Captsel = 57U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Captsel = 58U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Captsel = 59U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Captsel = 60U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Captsel = 61U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Captsel = 62U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Captsel = 63U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Captsel = 64U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Captsel = 65U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Captsel = 66U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Captsel = 67U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Captsel = 68U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Captsel = 69U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Captsel = 70U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer4Captsel = 71U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer4Captsel = 72U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer4Captsel = 73U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer4Captsel = 74U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer4Captsel = 75U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer4Captsel = 76U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer4Captsel = 77U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer4Captsel = 78U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer4Captsel = 79U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer4Captsel = 80U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer4Captsel = 81U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer4Captsel = 82U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer4Captsel = 83U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer4Captsel = 84U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer4Captsel = 85U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer4Captsel = 86U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer4Captsel = 87U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer4Captsel = 88U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer4Captsel = 89U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Captsel = 90U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Captsel = 91U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Captsel = 92U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer4Captsel = 93U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Captsel = 94U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Captsel = 95U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Captsel = 96U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Captsel = 97U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer4Captsel = 98U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer4Captsel = 99U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer4Captsel = 100U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer4Captsel = 105U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer4Captsel = 106U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer4Captsel = 107U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer4Captsel = 108U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer4Captsel = 109U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer4Captsel = 110U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer4Captsel = 111U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer4Captsel = 112U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToTimer4Captsel = 113U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToTimer4Captsel = 114U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToTimer4Captsel = 115U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToTimer4Captsel = 116U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToTimer4Captsel = 117U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToTimer4Captsel = 118U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToTimer4Captsel = 119U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToTimer4Captsel = 120U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToTimer4Captsel = 121U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToTimer4Captsel = 122U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToTimer4Captsel = 123U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToTimer4Captsel = 124U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER0 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer0Trigger = 1U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Trigger = 2U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Trigger = 3U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Trigger = 4U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Trigger = 5U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Trigger = 6U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Trigger = 7U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Trigger = 8U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Trigger = 9U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Trigger = 10U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Trigger = 11U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Trigger = 12U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Trigger = 13U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Trigger = 14U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Trigger = 15U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Trigger = 16U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Trigger = 17U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Trigger = 18U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Trigger = 19U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Trigger = 20U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Trigger = 21U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer0Trigger = 22U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer0Trigger = 23U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer0Trigger = 24U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer0Trigger = 25U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer0Trigger = 26U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer0Trigger = 27U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer0Trigger = 28U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer0Trigger = 29U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Trigger = 30U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Trigger = 31U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer0Trigger = 32U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer0Trigger = 33U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer0Trigger = 34U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer0Trigger = 35U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer0Trigger = 36U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer0Trigger = 37U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer0Trigger = 40U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer0Trigger = 41U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer0Trigger = 42U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer0Trigger = 43U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Trigger = 44U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Trigger = 45U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Trigger = 46U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer0Trigger = 47U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Trigger = 48U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Trigger = 49U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer0Trigger = 50U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer0Trigger = 51U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer0Trigger = 52U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Trigger = 53U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer0Trigger = 54U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Trigger = 55U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Trigger = 56U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Trigger = 57U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Trigger = 58U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Trigger = 59U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Trigger = 60U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Trigger = 61U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Trigger = 62U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Trigger = 63U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Trigger = 64U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Trigger = 65U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Trigger = 66U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Trigger = 67U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Trigger = 68U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Trigger = 69U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Trigger = 70U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer0Trigger = 71U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer0Trigger = 72U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer0Trigger = 73U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer0Trigger = 74U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer0Trigger = 75U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer0Trigger = 76U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer0Trigger = 77U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer0Trigger = 78U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer0Trigger = 79U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer0Trigger = 80U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer0Trigger = 81U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer0Trigger = 82U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer0Trigger = 83U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer0Trigger = 84U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer0Trigger = 85U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer0Trigger = 86U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer0Trigger = 87U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer0Trigger = 88U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer0Trigger = 89U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Trigger = 90U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Trigger = 91U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Trigger = 92U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer0Trigger = 93U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Trigger = 94U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Trigger = 95U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Trigger = 96U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Trigger = 97U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer0Trigger = 98U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer0Trigger = 99U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer0Trigger = 100U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer0Trigger = 105U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer0Trigger = 106U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer0Trigger = 107U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer0Trigger = 108U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer0Trigger = 109U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer0Trigger = 110U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer0Trigger = 111U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer0Trigger = 112U + (TIMER0TRIGIN << PMUX_SHIFT), + + /*!< TIMER1 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer1Trigger = 1U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Trigger = 2U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Trigger = 3U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Trigger = 4U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Trigger = 5U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Trigger = 6U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Trigger = 7U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Trigger = 8U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Trigger = 9U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Trigger = 10U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Trigger = 11U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Trigger = 12U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Trigger = 13U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Trigger = 14U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Trigger = 15U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Trigger = 16U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Trigger = 17U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Trigger = 18U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Trigger = 19U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Trigger = 20U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Trigger = 21U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer1Trigger = 22U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer1Trigger = 23U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer1Trigger = 24U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer1Trigger = 25U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer1Trigger = 26U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer1Trigger = 27U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer1Trigger = 28U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer1Trigger = 29U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Trigger = 30U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Trigger = 31U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer1Trigger = 32U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer1Trigger = 33U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer1Trigger = 34U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer1Trigger = 35U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer1Trigger = 36U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer1Trigger = 37U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer1Trigger = 40U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer1Trigger = 41U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer1Trigger = 42U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer1Trigger = 43U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Trigger = 44U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Trigger = 45U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Trigger = 46U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer1Trigger = 47U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Trigger = 48U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Trigger = 49U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer1Trigger = 50U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer1Trigger = 51U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer1Trigger = 52U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Trigger = 53U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer1Trigger = 54U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Trigger = 55U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Trigger = 56U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Trigger = 57U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Trigger = 58U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Trigger = 59U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Trigger = 60U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Trigger = 61U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Trigger = 62U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Trigger = 63U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Trigger = 64U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Trigger = 65U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Trigger = 66U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Trigger = 67U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Trigger = 68U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Trigger = 69U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Trigger = 70U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer1Trigger = 71U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer1Trigger = 72U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer1Trigger = 73U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer1Trigger = 74U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer1Trigger = 75U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer1Trigger = 76U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer1Trigger = 77U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer1Trigger = 78U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer1Trigger = 79U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer1Trigger = 80U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer1Trigger = 81U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer1Trigger = 82U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer1Trigger = 83U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer1Trigger = 84U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer1Trigger = 85U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer1Trigger = 86U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer1Trigger = 87U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer1Trigger = 88U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer1Trigger = 89U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Trigger = 90U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Trigger = 91U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Trigger = 92U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer1Trigger = 93U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Trigger = 94U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Trigger = 95U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Trigger = 96U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Trigger = 97U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer1Trigger = 98U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer1Trigger = 99U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer1Trigger = 100U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer1Trigger = 105U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer1Trigger = 106U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer1Trigger = 107U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer1Trigger = 108U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer1Trigger = 109U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer1Trigger = 110U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer1Trigger = 111U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer1Trigger = 112U + (TIMER1TRIGIN << PMUX_SHIFT), + + /*!< TIMER2 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer2Trigger = 1U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Trigger = 2U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Trigger = 3U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Trigger = 4U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Trigger = 5U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Trigger = 6U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Trigger = 7U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Trigger = 8U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Trigger = 9U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Trigger = 10U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Trigger = 11U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Trigger = 12U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Trigger = 13U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Trigger = 14U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Trigger = 15U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Trigger = 16U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Trigger = 17U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Trigger = 18U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Trigger = 19U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Trigger = 20U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Trigger = 21U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer2Trigger = 22U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer2Trigger = 23U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer2Trigger = 24U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer2Trigger = 25U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer2Trigger = 26U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer2Trigger = 27U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer2Trigger = 28U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer2Trigger = 29U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Trigger = 30U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Trigger = 31U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer2Trigger = 32U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer2Trigger = 33U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer2Trigger = 34U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer2Trigger = 35U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer2Trigger = 36U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer2Trigger = 37U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer2Trigger = 40U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer2Trigger = 41U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer2Trigger = 42U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer2Trigger = 43U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Trigger = 44U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Trigger = 45U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Trigger = 46U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer2Trigger = 47U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Trigger = 48U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Trigger = 49U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer2Trigger = 50U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer2Trigger = 51U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer2Trigger = 52U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Trigger = 53U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer2Trigger = 54U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Trigger = 55U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Trigger = 56U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Trigger = 57U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Trigger = 58U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Trigger = 59U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Trigger = 60U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Trigger = 61U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Trigger = 62U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Trigger = 63U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Trigger = 64U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Trigger = 65U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Trigger = 66U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Trigger = 67U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Trigger = 68U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Trigger = 69U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Trigger = 70U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer2Trigger = 71U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer2Trigger = 72U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer2Trigger = 73U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer2Trigger = 74U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer2Trigger = 75U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer2Trigger = 76U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer2Trigger = 77U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer2Trigger = 78U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer2Trigger = 79U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer2Trigger = 80U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer2Trigger = 81U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer2Trigger = 82U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer2Trigger = 83U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer2Trigger = 84U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer2Trigger = 85U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer2Trigger = 86U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer2Trigger = 87U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer2Trigger = 88U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer2Trigger = 89U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Trigger = 90U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Trigger = 91U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Trigger = 92U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer2Trigger = 93U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Trigger = 94U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Trigger = 95U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Trigger = 96U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Trigger = 97U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer2Trigger = 98U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer2Trigger = 99U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer2Trigger = 100U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer2Trigger = 105U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer2Trigger = 106U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer2Trigger = 107U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer2Trigger = 108U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer2Trigger = 109U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer2Trigger = 110U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer2Trigger = 111U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer2Trigger = 112U + (TIMER2TRIGIN << PMUX_SHIFT), + + /*!< TIMER3 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer3Trigger = 1U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Trigger = 2U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Trigger = 3U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Trigger = 4U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Trigger = 5U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Trigger = 6U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Trigger = 7U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Trigger = 8U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Trigger = 9U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Trigger = 10U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Trigger = 11U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Trigger = 12U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Trigger = 13U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Trigger = 14U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Trigger = 15U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Trigger = 16U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Trigger = 17U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Trigger = 18U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Trigger = 19U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Trigger = 20U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Trigger = 21U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer3Trigger = 22U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer3Trigger = 23U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer3Trigger = 24U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer3Trigger = 25U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer3Trigger = 26U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer3Trigger = 27U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer3Trigger = 28U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer3Trigger = 29U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Trigger = 30U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Trigger = 31U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer3Trigger = 32U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer3Trigger = 33U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer3Trigger = 34U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer3Trigger = 35U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer3Trigger = 36U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer3Trigger = 37U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer3Trigger = 40U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer3Trigger = 41U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer3Trigger = 42U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer3Trigger = 43U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Trigger = 44U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Trigger = 45U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Trigger = 46U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer3Trigger = 47U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Trigger = 48U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Trigger = 49U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer3Trigger = 50U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer3Trigger = 51U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer3Trigger = 52U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Trigger = 53U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer3Trigger = 54U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Trigger = 55U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Trigger = 56U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Trigger = 57U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Trigger = 58U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Trigger = 59U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Trigger = 60U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Trigger = 61U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Trigger = 62U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Trigger = 63U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Trigger = 64U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Trigger = 65U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Trigger = 66U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Trigger = 67U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Trigger = 68U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Trigger = 69U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Trigger = 70U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer3Trigger = 71U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer3Trigger = 72U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer3Trigger = 73U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer3Trigger = 74U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer3Trigger = 75U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer3Trigger = 76U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer3Trigger = 77U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer3Trigger = 78U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer3Trigger = 79U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer3Trigger = 80U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer3Trigger = 81U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer3Trigger = 82U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer3Trigger = 83U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer3Trigger = 84U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer3Trigger = 85U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer3Trigger = 86U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer3Trigger = 87U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer3Trigger = 88U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer3Trigger = 89U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Trigger = 90U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Trigger = 91U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Trigger = 92U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer3Trigger = 93U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Trigger = 94U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Trigger = 95U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Trigger = 96U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Trigger = 97U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer3Trigger = 98U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer3Trigger = 99U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer3Trigger = 100U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer3Trigger = 105U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer3Trigger = 106U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer3Trigger = 107U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer3Trigger = 108U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer3Trigger = 109U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer3Trigger = 110U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer3Trigger = 111U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer3Trigger = 112U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToTimer3Trigger = 113U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToTimer3Trigger = 114U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToTimer3Trigger = 115U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToTimer3Trigger = 116U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToTimer3Trigger = 117U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToTimer3Trigger = 118U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToTimer3Trigger = 119U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToTimer3Trigger = 120U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToTimer3Trigger = 121U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToTimer3Trigger = 122U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToTimer3Trigger = 123U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToTimer3Trigger = 124U + (TIMER3TRIGIN << PMUX_SHIFT), + + /*!< TIMER4 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer4Trigger = 1U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Trigger = 2U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Trigger = 3U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Trigger = 4U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Trigger = 5U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Trigger = 6U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Trigger = 7U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Trigger = 8U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Trigger = 9U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Trigger = 10U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Trigger = 11U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Trigger = 12U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Trigger = 13U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Trigger = 14U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Trigger = 15U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Trigger = 16U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Trigger = 17U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Trigger = 18U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Trigger = 19U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Trigger = 20U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Trigger = 21U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer4Trigger = 22U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer4Trigger = 23U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer4Trigger = 24U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer4Trigger = 25U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer4Trigger = 26U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer4Trigger = 27U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer4Trigger = 28U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer4Trigger = 29U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Trigger = 30U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Trigger = 31U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer4Trigger = 32U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer4Trigger = 33U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer4Trigger = 34U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer4Trigger = 35U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer4Trigger = 36U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer4Trigger = 37U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer4Trigger = 40U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer4Trigger = 41U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer4Trigger = 42U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer4Trigger = 43U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Trigger = 44U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Trigger = 45U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Trigger = 46U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer4Trigger = 47U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Trigger = 48U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Trigger = 49U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer4Trigger = 50U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer4Trigger = 51U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer4Trigger = 52U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Trigger = 53U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer4Trigger = 54U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Trigger = 55U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Trigger = 56U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Trigger = 57U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Trigger = 58U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Trigger = 59U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Trigger = 60U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Trigger = 61U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Trigger = 62U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Trigger = 63U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Trigger = 64U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Trigger = 65U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Trigger = 66U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Trigger = 67U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Trigger = 68U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Trigger = 69U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Trigger = 70U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer4Trigger = 71U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer4Trigger = 72U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer4Trigger = 73U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer4Trigger = 74U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer4Trigger = 75U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer4Trigger = 76U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer4Trigger = 77U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer4Trigger = 78U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer4Trigger = 79U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer4Trigger = 80U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer4Trigger = 81U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer4Trigger = 82U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer4Trigger = 83U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer4Trigger = 84U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer4Trigger = 85U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer4Trigger = 86U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer4Trigger = 87U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer4Trigger = 88U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer4Trigger = 89U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Trigger = 90U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Trigger = 91U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Trigger = 92U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer4Trigger = 93U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Trigger = 94U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Trigger = 95U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Trigger = 96U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Trigger = 97U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer4Trigger = 98U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer4Trigger = 99U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer4Trigger = 100U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer4Trigger = 105U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer4Trigger = 106U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer4Trigger = 107U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer4Trigger = 108U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer4Trigger = 109U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer4Trigger = 110U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer4Trigger = 111U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer4Trigger = 112U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToTimer4Trigger = 113U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToTimer4Trigger = 114U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToTimer4Trigger = 115U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToTimer4Trigger = 116U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToTimer4Trigger = 117U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToTimer4Trigger = 118U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToTimer4Trigger = 119U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToTimer4Trigger = 120U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToTimer4Trigger = 121U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToTimer4Trigger = 122U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToTimer4Trigger = 123U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToTimer4Trigger = 124U + (TIMER4TRIGIN << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_ClkInToFreqmeasRef = 1U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc12MToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FroHfDivToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Clk16K1ToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_SlowClkToFreqmeasRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasRef = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFreqmeasRef = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFreqmeasRef = 10u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasRef = 11u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasRef = 12u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasRef = 13u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasRef = 14u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasRef = 15u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasRef = 16u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFreqmeasRef = 17u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFreqmeasRef = 18u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFreqmeasRef = 32u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFreqmeasRef = 33u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFreqmeasRef = 34u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFreqmeasRef = 35u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFreqmeasRef = 36u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFreqmeasRef = 37u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFreqmeasRef = 38u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFreqmeasRef = 39u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFreqmeasRef = 40u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFreqmeasRef = 41u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_ClkInToFreqmeasTar = 1U + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc12MToFreqmeasTar = 2u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FroHfDivToFreqmeasTar = 3u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Clk16K1ToFreqmeasTar = 5u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_SlowClkToFreqmeasTar = 6u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasTar = 7u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasTar = 8u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFreqmeasTar = 9u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFreqmeasTar = 10u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasTar = 11u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasTar = 12u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasTar = 13u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasTar = 14u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasTar = 15u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasTar = 16u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFreqmeasTar = 17u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFreqmeasTar = 18u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFreqmeasTar = 32u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFreqmeasTar = 33u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFreqmeasTar = 34u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFreqmeasTar = 35u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFreqmeasTar = 36u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFreqmeasTar = 37u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFreqmeasTar = 38u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFreqmeasTar = 39u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFreqmeasTar = 40u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFreqmeasTar = 41u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + + /*!< Cmp0 Trigger. */ + kINPUTMUX_Aoi0Out0ToCmp0Trigger = 2U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToCmp0Trigger = 3U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToCmp0Trigger = 4U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToCmp0Trigger = 5U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToCmp0Trigger = 6U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToCmp0Trigger = 7U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp0Trigger = 8U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToCmp0Trigger = 9U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToCmp0Trigger = 10U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToCmp0Trigger = 11U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToCmp0Trigger = 12U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToCmp0Trigger = 13U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp0Trigger = 14U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToCmp0Trigger = 16U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToCmp0Trigger = 17U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToCmp0Trigger = 18U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToCmp0Trigger = 19U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToCmp0Trigger = 20U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToCmp0Trigger = 21U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToCmp0Trigger = 22U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToCmp0Trigger = 23U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToCmp0Trigger = 24U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp0Trigger = 27U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp0Trigger = 28U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToCmp0Trigger = 29U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToCmp0Trigger = 30U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToCmp0Trigger = 31U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToCmp0Trigger = 32U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToCmp0Trigger = 33U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToCmp0Trigger = 34U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToCmp0Trigger = 39U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp0Trigger = 40U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp0Trigger = 41U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp0Trigger = 42U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToCmp0Trigger = 47U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToCmp0Trigger = 48U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToCmp0Trigger = 49U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToCmp0Trigger = 50U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToCmp0Trigger = 51U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToCmp0Trigger = 52U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToCmp0Trigger = 53U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToCmp0Trigger = 54U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToCmp0Trigger = 55U + (CMP0_TRIG_REG << PMUX_SHIFT), + + /*!< Cmp1 Trigger. */ + kINPUTMUX_Aoi0Out0ToCmp1Trigger = 2U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToCmp1Trigger = 3U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToCmp1Trigger = 4U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToCmp1Trigger = 5U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToCmp1Trigger = 6U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToCmp1Trigger = 7U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp1Trigger = 8U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToCmp1Trigger = 9U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToCmp1Trigger = 10U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToCmp1Trigger = 11U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToCmp1Trigger = 12U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToCmp1Trigger = 13U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp1Trigger = 14U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToCmp1Trigger = 16U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToCmp1Trigger = 17U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToCmp1Trigger = 18U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToCmp1Trigger = 19U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToCmp1Trigger = 20U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToCmp1Trigger = 21U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToCmp1Trigger = 22U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToCmp1Trigger = 23U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToCmp1Trigger = 24U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp1Trigger = 27U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp1Trigger = 28U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToCmp1Trigger = 29U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToCmp1Trigger = 30U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToCmp1Trigger = 31U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToCmp1Trigger = 32U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToCmp1Trigger = 33U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToCmp1Trigger = 34U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToCmp1Trigger = 39U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp1Trigger = 40U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp1Trigger = 41U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp1Trigger = 42U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToCmp1Trigger = 47U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToCmp1Trigger = 48U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToCmp1Trigger = 49U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToCmp1Trigger = 50U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToCmp1Trigger = 51U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToCmp1Trigger = 52U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToCmp1Trigger = 53U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToCmp1Trigger = 54U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToCmp1Trigger = 55U + (CMP1_TRIG_REG << PMUX_SHIFT), + + /*!< Cmp2 Trigger. */ + kINPUTMUX_Aoi0Out0ToCmp2Trigger = 2U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToCmp2Trigger = 3U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToCmp2Trigger = 4U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToCmp2Trigger = 5U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToCmp2Trigger = 6U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToCmp2Trigger = 7U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp2Trigger = 8U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToCmp2Trigger = 9U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToCmp2Trigger = 10U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToCmp2Trigger = 11U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToCmp2Trigger = 12U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToCmp2Trigger = 13U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp2Trigger = 14U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToCmp2Trigger = 16U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToCmp2Trigger = 17U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToCmp2Trigger = 18U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToCmp2Trigger = 19U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToCmp2Trigger = 20U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToCmp2Trigger = 21U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToCmp2Trigger = 22U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToCmp2Trigger = 23U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToCmp2Trigger = 24U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToCmp2Trigger = 25U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToCmp2Trigger = 26U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp2Trigger = 27U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp2Trigger = 28U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToCmp2Trigger = 29U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToCmp2Trigger = 30U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToCmp2Trigger = 31U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToCmp2Trigger = 32U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToCmp2Trigger = 33U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToCmp2Trigger = 34U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToCmp2Trigger = 39U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp2Trigger = 40U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp2Trigger = 41U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp2Trigger = 42U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToCmp2Trigger = 47U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToCmp2Trigger = 48U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToCmp2Trigger = 49U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToCmp2Trigger = 50U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToCmp2Trigger = 51U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToCmp2Trigger = 52U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToCmp2Trigger = 53U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToCmp2Trigger = 54U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToCmp2Trigger = 55U + (CMP2_TRIG_REG << PMUX_SHIFT), + + /*!< Adc0 Trigger. */ + kINPUTMUX_ArmTxevToAdc0Trigger = 1U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc0Trigger = 2U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc0Trigger = 3U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc0Trigger = 4U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc0Trigger = 5U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc0Trigger = 6U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc0Trigger = 7U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAdc0Trigger = 7U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc0Trigger = 9U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc0Trigger = 10U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc0Trigger = 11U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc0Trigger = 12U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc0Trigger = 13U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc0Trigger = 14U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc0Trigger = 15U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc0Trigger = 17U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc0Trigger = 18U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc0Trigger = 19U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc0Trigger = 20U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc0Trigger = 21U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc0Trigger = 22U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc0Trigger = 23U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAdc0Trigger = 24U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAdc0Trigger = 25U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc0Trigger = 26U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc0Trigger = 27U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc0Trigger = 28U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc0Trigger = 29U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc0Trigger = 30U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc0Trigger = 31U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc0Trigger = 33U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc0Trigger = 34U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc0Trigger = 35U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc0Trigger = 36U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc0Trigger = 37U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc0Trigger = 38U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc0Trigger = 39U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc0Trigger = 40U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc0Trigger = 41U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc0Trigger = 42U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc0Trigger = 43U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc0Trigger = 44U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc0Trigger = 45U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc0Trigger = 46U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc0Trigger = 47U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc0Trigger = 48U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc0Trigger = 49U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc0Trigger = 50U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc0Trigger = 51U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc0Trigger = 52U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc0Trigger = 53U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc0Trigger = 54U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc0Trigger = 55U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAdc0Trigger = 56U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAdc0Trigger = 57U + (ADC0_TRIG0_REG << PMUX_SHIFT), + + /*!< Adc1 Trigger. */ + kINPUTMUX_ArmTxevToAdc1Trigger = 1U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc1Trigger = 2U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc1Trigger = 3U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc1Trigger = 4U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc1Trigger = 5U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc1Trigger = 6U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc1Trigger = 7U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAdc1Trigger = 7U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc1Trigger = 9U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc1Trigger = 10U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc1Trigger = 11U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc1Trigger = 12U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc1Trigger = 13U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc1Trigger = 14U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc1Trigger = 15U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc1Trigger = 17U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc1Trigger = 18U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc1Trigger = 19U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc1Trigger = 20U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc1Trigger = 21U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc1Trigger = 22U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc1Trigger = 23U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAdc1Trigger = 24U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAdc1Trigger = 25U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc1Trigger = 26U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc1Trigger = 27U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc1Trigger = 28U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc1Trigger = 29U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc1Trigger = 30U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc1Trigger = 31U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc1Trigger = 33U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc1Trigger = 34U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc1Trigger = 35U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc1Trigger = 36U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc1Trigger = 37U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc1Trigger = 38U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc1Trigger = 39U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc1Trigger = 40U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc1Trigger = 41U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc1Trigger = 42U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc1Trigger = 43U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc1Trigger = 44U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc1Trigger = 45U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc1Trigger = 46U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc1Trigger = 47U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc1Trigger = 48U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc1Trigger = 49U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc1Trigger = 50U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc1Trigger = 51U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc1Trigger = 52U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc1Trigger = 53U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc1Trigger = 54U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc1Trigger = 55U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAdc1Trigger = 56U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAdc1Trigger = 57U + (ADC1_TRIG0_REG << PMUX_SHIFT), + + /*!< Adc2 Trigger. */ + kINPUTMUX_ArmTxevToAdc2Trigger = 1U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc2Trigger = 2U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc2Trigger = 3U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc2Trigger = 4U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc2Trigger = 5U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc2Trigger = 6U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc2Trigger = 7U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAdc2Trigger = 7U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc2Trigger = 9U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc2Trigger = 10U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc2Trigger = 11U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc2Trigger = 12U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc2Trigger = 13U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc2Trigger = 14U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc2Trigger = 15U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc2Trigger = 17U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc2Trigger = 18U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc2Trigger = 19U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc2Trigger = 20U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc2Trigger = 21U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc2Trigger = 22U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc2Trigger = 23U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAdc2Trigger = 24U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAdc2Trigger = 25U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc2Trigger = 26U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc2Trigger = 27U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc2Trigger = 28U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc2Trigger = 29U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc2Trigger = 30U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc2Trigger = 31U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc2Trigger = 33U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc2Trigger = 34U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc2Trigger = 35U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc2Trigger = 36U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc2Trigger = 37U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc2Trigger = 38U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc2Trigger = 39U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc2Trigger = 40U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc2Trigger = 41U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc2Trigger = 42U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc2Trigger = 43U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc2Trigger = 44U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc2Trigger = 45U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc2Trigger = 46U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc2Trigger = 47U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc2Trigger = 48U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc2Trigger = 49U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc2Trigger = 50U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc2Trigger = 51U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc2Trigger = 52U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc2Trigger = 53U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc2Trigger = 54U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc2Trigger = 55U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAdc2Trigger = 56U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAdc2Trigger = 57U + (ADC2_TRIG0_REG << PMUX_SHIFT), + + /*!< Adc3 Trigger. */ + kINPUTMUX_ArmTxevToAdc3Trigger = 1U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc3Trigger = 2U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc3Trigger = 3U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc3Trigger = 4U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc3Trigger = 5U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc3Trigger = 6U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc3Trigger = 7U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAdc3Trigger = 7U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc3Trigger = 9U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc3Trigger = 10U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc3Trigger = 11U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc3Trigger = 12U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc3Trigger = 13U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc3Trigger = 14U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc3Trigger = 15U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc3Trigger = 17U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc3Trigger = 18U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc3Trigger = 19U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc3Trigger = 20U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc3Trigger = 21U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc3Trigger = 22U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc3Trigger = 23U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAdc3Trigger = 24U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAdc3Trigger = 25U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc3Trigger = 26U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc3Trigger = 27U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc3Trigger = 28U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc3Trigger = 29U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc3Trigger = 30U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc3Trigger = 31U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc3Trigger = 33U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc3Trigger = 34U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc3Trigger = 35U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc3Trigger = 36U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc3Trigger = 37U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc3Trigger = 38U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc3Trigger = 39U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc3Trigger = 40U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc3Trigger = 41U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc3Trigger = 42U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc3Trigger = 43U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc3Trigger = 44U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc3Trigger = 45U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc3Trigger = 46U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc3Trigger = 47U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc3Trigger = 48U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc3Trigger = 49U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc3Trigger = 50U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc3Trigger = 51U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc3Trigger = 52U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc3Trigger = 53U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc3Trigger = 54U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc3Trigger = 55U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAdc3Trigger = 56U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAdc3Trigger = 57U + (ADC3_TRIG0_REG << PMUX_SHIFT), + + /*!< Dac0 Trigger. */ + kINPUTMUX_ArmTxevToDac0Trigger = 1U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToDac0Trigger = 2U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToDac0Trigger = 3U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToDac0Trigger = 4U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToDac0Trigger = 5U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToDac0Trigger = 6U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToDac0Trigger = 7U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToDac0Trigger = 8U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDac0Trigger = 9U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDac0Trigger = 10U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDac0Trigger = 11U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToDac0Trigger = 12U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDac0Trigger = 13U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDac0Trigger = 14U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToDac0Trigger = 15U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToDac0Trigger = 18U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToDac0Trigger = 19U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToDac0Trigger = 20U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToDac0Trigger = 21U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToDac0Trigger = 26U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToDac0Trigger = 27U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToDac0Trigger = 28U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToDac0Trigger = 29U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToDac0Trigger = 30U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToDac0Trigger = 31U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToDac0Trigger = 33U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToDac0Trigger = 34U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToDac0Trigger = 35U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToDac0Trigger = 36U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToDac0Trigger = 37U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToDac0Trigger = 38U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToDac0Trigger = 39U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToDac0Trigger = 40U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDac0Trigger = 41U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToDac0Trigger = 42U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDac0Trigger = 43U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDac0Trigger = 44U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToDac0Trigger = 50U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToDac0Trigger = 51U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToDac0Trigger = 52U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToDac0Trigger = 55U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToDac0Trigger = 57U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToDac0Trigger = 58U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToDac0Trigger = 59U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToDac0Trigger = 60U + (DAC0_TRIG0_REG << PMUX_SHIFT), + + /*!< Qdc0 Trigger. */ + kINPUTMUX_ArmTxevToQdc0Trigger = 1U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Trigger = 2U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Trigger = 3U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Trigger = 4U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Trigger = 5U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Trigger = 6U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Trigger = 7U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Trigger = 8U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Trigger = 9U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Trigger = 10U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Trigger = 11U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Trigger = 12U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Trigger = 13U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Trigger = 14U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Trigger = 16U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Trigger = 17U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Trigger = 18U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Trigger = 19U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Trigger = 20U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Trigger = 21U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Trigger = 22U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Trigger = 23U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Trigger = 24U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Trigger = 25U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Trigger = 26U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Trigger = 27U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Trigger = 28U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Trigger = 29U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Trigger = 30U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Trigger = 31U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Trigger = 32U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Trigger = 33U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Trigger = 34U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Trigger = 35U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Trigger = 36U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Trigger = 37U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Trigger = 38U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Trigger = 39U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Trigger = 40U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Trigger = 41U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Trigger = 42U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Trigger = 43U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Trigger = 44U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Trigger = 49U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Trigger = 50U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Trigger = 51U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Trigger = 52U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Trigger = 62U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Trigger = 63U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Trigger = 64U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Trigger = 65U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Trigger = 66U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Trigger = 67U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Trigger = 68U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Trigger = 69U + (QDC0_TRIG_REG << PMUX_SHIFT), + + /*!< Qdc0 Home. */ + kINPUTMUX_ArmTxevToQdc0Home = 1U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Home = 2U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Home = 3U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Home = 4U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Home = 5U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Home = 6U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Home = 7U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Home = 8U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Home = 9U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Home = 10U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Home = 11U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Home = 12U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Home = 13U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Home = 14U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Home = 16U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Home = 17U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Home = 18U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Home = 19U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Home = 20U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Home = 21U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Home = 22U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Home = 23U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Home = 24U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Home = 25U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Home = 26U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Home = 27U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Home = 28U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Home = 29U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Home = 30U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Home = 31U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Home = 32U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Home = 33U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Home = 34U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Home = 35U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Home = 36U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Home = 37U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Home = 38U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Home = 39U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Home = 40U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Home = 41U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Home = 42U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Home = 43U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Home = 44U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Home = 49U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Home = 50U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Home = 51U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Home = 52U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Home = 62U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Home = 63U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Home = 64U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Home = 65U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Home = 66U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Home = 67U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Home = 68U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Home = 69U + (QDC0_HOME_REG << PMUX_SHIFT), + + /*!< Qdc0 Index. */ + kINPUTMUX_ArmTxevToQdc0Index = 1U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Index = 2U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Index = 3U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Index = 4U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Index = 5U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Index = 6U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Index = 7U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Index = 8U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Index = 9U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Index = 10U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Index = 11U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Index = 12U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Index = 13U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Index = 14U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Index = 16U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Index = 17U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Index = 18U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Index = 19U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Index = 20U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Index = 21U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Index = 22U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Index = 23U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Index = 24U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Index = 25U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Index = 26U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Index = 27U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Index = 28U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Index = 29U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Index = 30U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Index = 31U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Index = 32U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Index = 33U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Index = 34U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Index = 35U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Index = 36U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Index = 37U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Index = 38U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Index = 39U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Index = 40U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Index = 41U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Index = 42U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Index = 43U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Index = 44U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Index = 49U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Index = 50U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Index = 51U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Index = 52U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Index = 62U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Index = 63U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Index = 64U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Index = 65U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Index = 66U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Index = 67U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Index = 68U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Index = 69U + (QDC0_INDEX_REG << PMUX_SHIFT), + + /*!< Qdc0 Phaseb. */ + kINPUTMUX_ArmTxevToQdc0Phaseb = 1U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Phaseb = 2U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Phaseb = 3U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Phaseb = 4U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Phaseb = 5U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phaseb = 6U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phaseb = 7U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Phaseb = 8U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Phaseb = 9U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phaseb = 10U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Phaseb = 11U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phaseb = 12U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Phaseb = 13U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phaseb = 14U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phaseb = 16U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phaseb = 17U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phaseb = 18U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phaseb = 19U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phaseb = 20U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phaseb = 21U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Phaseb = 22U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Phaseb = 23U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phaseb = 24U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phaseb = 25U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phaseb = 26U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phaseb = 27U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phaseb = 28U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phaseb = 29U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phaseb = 30U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phaseb = 31U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phaseb = 32U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phaseb = 33U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Phaseb = 34U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Phaseb = 35U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phaseb = 36U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phaseb = 37U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phaseb = 38U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phaseb = 39U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phaseb = 40U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Phaseb = 41U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Phaseb = 42U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Phaseb = 43U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Phaseb = 44U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Phaseb = 49U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Phaseb = 50U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Phaseb = 51U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Phaseb = 52U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phaseb = 62U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phaseb = 63U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phaseb = 64U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phaseb = 65U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phaseb = 66U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phaseb = 67U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Phaseb = 68U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Phaseb = 69U + (QDC0_PHASEB_REG << PMUX_SHIFT), + + /*!< Qdc0 Phasea. */ + kINPUTMUX_ArmTxevToQdc0Phasea = 1U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Phasea = 2U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Phasea = 3U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Phasea = 4U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Phasea = 5U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phasea = 6U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phasea = 7U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Phasea = 8U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Phasea = 9U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phasea = 10U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Phasea = 11U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phasea = 12U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Phasea = 13U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phasea = 14U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phasea = 16U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phasea = 17U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phasea = 18U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phasea = 19U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phasea = 20U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phasea = 21U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Phasea = 22U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Phasea = 23U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phasea = 24U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phasea = 25U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phasea = 26U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phasea = 27U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phasea = 28U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phasea = 29U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phasea = 30U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phasea = 31U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phasea = 32U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phasea = 33U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Phasea = 34U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Phasea = 35U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phasea = 36U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phasea = 37U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phasea = 38U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phasea = 39U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phasea = 40U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Phasea = 41U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Phasea = 42U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Phasea = 43U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Phasea = 44U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Phasea = 49U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Phasea = 50U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Phasea = 51U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Phasea = 52U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phasea = 62U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phasea = 63U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phasea = 64U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phasea = 65U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phasea = 66U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phasea = 67U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Phasea = 68U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Phasea = 69U + (QDC0_PHASEA_REG << PMUX_SHIFT), + + /*!< Qdc0 Icap1-3. */ + kINPUTMUX_ArmTxevToQdc0Icap1 = 1U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Icap1 = 2U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Icap1 = 3U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Icap1 = 4U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Icap1 = 5U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Icap1 = 6U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Icap1 = 7U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Icap1 = 8U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Icap1 = 9U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Icap1 = 10U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Icap1 = 11U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Icap1 = 12U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Icap1 = 13U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Icap1 = 14U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Icap1 = 16U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Icap1 = 17U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Icap1 = 18U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Icap1 = 19U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Icap1 = 20U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Icap1 = 21U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Icap1 = 22U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Icap1 = 23U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Icap1 = 24U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Icap1 = 25U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Icap1 = 26U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Icap1 = 27U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Icap1 = 28U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Icap1 = 29U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Icap1 = 30U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Icap1 = 31U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Icap1 = 32U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Icap1 = 33U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Icap1 = 34U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Icap1 = 35U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Icap1 = 36U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Icap1 = 37U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Icap1 = 38U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Icap1 = 39U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Icap1 = 40U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Icap1 = 41U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Icap1 = 42U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Icap1 = 43U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Icap1 = 44U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Icap1 = 49U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Icap1 = 50U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Icap1 = 51U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Icap1 = 52U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Icap1 = 62U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Icap1 = 63U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Icap1 = 64U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Icap1 = 65U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Icap1 = 66U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Icap1 = 67U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Icap1 = 68U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Icap1 = 69U + (QDC0_ICAP0_REG << PMUX_SHIFT), + + /*!< Qdc1 Trigger. */ + kINPUTMUX_ArmTxevToQdc1Trigger = 1U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Trigger = 2U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Trigger = 3U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Trigger = 4U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Trigger = 5U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Trigger = 6U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Trigger = 7U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Trigger = 8U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Trigger = 9U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Trigger = 10U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Trigger = 11U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Trigger = 12U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Trigger = 13U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Trigger = 14U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Trigger = 16U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Trigger = 17U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Trigger = 18U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Trigger = 19U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Trigger = 20U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Trigger = 21U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Trigger = 22U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Trigger = 23U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Trigger = 24U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Trigger = 25U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Trigger = 26U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Trigger = 27U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Trigger = 28U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Trigger = 29U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Trigger = 30U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Trigger = 31U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Trigger = 32U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Trigger = 33U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Trigger = 34U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Trigger = 35U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Trigger = 36U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Trigger = 37U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Trigger = 38U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Trigger = 39U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Trigger = 40U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Trigger = 41U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Trigger = 42U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Trigger = 43U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Trigger = 44U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Trigger = 49U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Trigger = 50U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Trigger = 51U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Trigger = 52U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Trigger = 62U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Trigger = 63U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Trigger = 64U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Trigger = 65U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Trigger = 66U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Trigger = 67U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Trigger = 68U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Trigger = 69U + (QDC1_TRIG_REG << PMUX_SHIFT), + + /*!< Qdc1 Home. */ + kINPUTMUX_ArmTxevToQdc1Home = 1U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Home = 2U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Home = 3U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Home = 4U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Home = 5U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Home = 6U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Home = 7U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Home = 8U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Home = 9U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Home = 10U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Home = 11U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Home = 12U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Home = 13U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Home = 14U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Home = 16U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Home = 17U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Home = 18U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Home = 19U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Home = 20U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Home = 21U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Home = 22U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Home = 23U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Home = 24U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Home = 25U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Home = 26U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Home = 27U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Home = 28U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Home = 29U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Home = 30U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Home = 31U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Home = 32U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Home = 33U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Home = 34U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Home = 35U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Home = 36U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Home = 37U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Home = 38U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Home = 39U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Home = 40U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Home = 41U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Home = 42U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Home = 43U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Home = 44U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Home = 49U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Home = 50U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Home = 51U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Home = 52U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Home = 62U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Home = 63U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Home = 64U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Home = 65U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Home = 66U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Home = 67U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Home = 68U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Home = 69U + (QDC1_HOME_REG << PMUX_SHIFT), + + /*!< Qdc1 Index. */ + kINPUTMUX_ArmTxevToQdc1Index = 1U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Index = 2U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Index = 3U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Index = 4U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Index = 5U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Index = 6U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Index = 7U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Index = 8U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Index = 9U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Index = 10U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Index = 11U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Index = 12U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Index = 13U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Index = 14U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Index = 16U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Index = 17U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Index = 18U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Index = 19U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Index = 20U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Index = 21U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Index = 22U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Index = 23U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Index = 24U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Index = 25U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Index = 26U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Index = 27U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Index = 28U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Index = 29U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Index = 30U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Index = 31U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Index = 32U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Index = 33U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Index = 34U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Index = 35U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Index = 36U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Index = 37U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Index = 38U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Index = 39U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Index = 40U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Index = 41U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Index = 42U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Index = 43U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Index = 44U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Index = 49U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Index = 50U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Index = 51U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Index = 52U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Index = 62U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Index = 63U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Index = 64U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Index = 65U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Index = 66U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Index = 67U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Index = 68U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Index = 69U + (QDC1_INDEX_REG << PMUX_SHIFT), + + /*!< Qdc1 Phaseb. */ + kINPUTMUX_ArmTxevToQdc1Phaseb = 1U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Phaseb = 2U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Phaseb = 3U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Phaseb = 4U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Phaseb = 5U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phaseb = 6U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phaseb = 7U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Phaseb = 8U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Phaseb = 9U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phaseb = 10U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Phaseb = 11U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phaseb = 12U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Phaseb = 13U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phaseb = 14U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phaseb = 16U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phaseb = 17U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phaseb = 18U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phaseb = 19U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phaseb = 20U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phaseb = 21U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Phaseb = 22U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Phaseb = 23U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phaseb = 24U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phaseb = 25U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phaseb = 26U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phaseb = 27U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phaseb = 28U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phaseb = 29U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phaseb = 30U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phaseb = 31U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phaseb = 32U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phaseb = 33U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Phaseb = 34U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Phaseb = 35U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phaseb = 36U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phaseb = 37U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phaseb = 38U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phaseb = 39U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phaseb = 40U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Phaseb = 41U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Phaseb = 42U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Phaseb = 43U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Phaseb = 44U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Phaseb = 49U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Phaseb = 50U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Phaseb = 51U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Phaseb = 52U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phaseb = 62U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phaseb = 63U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phaseb = 64U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phaseb = 65U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phaseb = 66U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phaseb = 67U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Phaseb = 68U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Phaseb = 69U + (QDC1_PHASEB_REG << PMUX_SHIFT), + + /*!< Qdc1 Phasea. */ + kINPUTMUX_ArmTxevToQdc1Phasea = 1U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Phasea = 2U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Phasea = 3U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Phasea = 4U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Phasea = 5U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phasea = 6U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phasea = 7U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Phasea = 8U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Phasea = 9U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phasea = 10U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Phasea = 11U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phasea = 12U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Phasea = 13U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phasea = 14U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phasea = 16U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phasea = 17U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phasea = 18U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phasea = 19U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phasea = 20U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phasea = 21U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Phasea = 22U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Phasea = 23U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phasea = 24U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phasea = 25U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phasea = 26U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phasea = 27U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phasea = 28U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phasea = 29U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phasea = 30U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phasea = 31U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phasea = 32U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phasea = 33U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Phasea = 34U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Phasea = 35U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phasea = 36U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phasea = 37U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phasea = 38U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phasea = 39U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phasea = 40U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Phasea = 41U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Phasea = 42U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Phasea = 43U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Phasea = 44U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Phasea = 49U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Phasea = 50U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Phasea = 51U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Phasea = 52U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phasea = 62U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phasea = 63U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phasea = 64U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phasea = 65U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phasea = 66U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phasea = 67U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Phasea = 68U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Phasea = 69U + (QDC1_PHASEA_REG << PMUX_SHIFT), + + /*!< Qdc1 Icap1-3. */ + kINPUTMUX_ArmTxevToQdc1Icap1 = 1U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Icap1 = 2U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Icap1 = 3U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Icap1 = 4U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Icap1 = 5U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Icap1 = 6U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Icap1 = 7U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Icap1 = 8U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Icap1 = 9U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Icap1 = 10U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Icap1 = 11U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Icap1 = 12U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Icap1 = 13U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Icap1 = 14U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Icap1 = 16U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Icap1 = 17U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Icap1 = 18U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Icap1 = 19U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Icap1 = 20U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Icap1 = 21U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Icap1 = 22U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Icap1 = 23U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Icap1 = 24U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Icap1 = 25U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Icap1 = 26U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Icap1 = 27U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Icap1 = 28U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Icap1 = 29U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Icap1 = 30U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Icap1 = 31U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Icap1 = 32U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Icap1 = 33U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Icap1 = 34U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Icap1 = 35U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Icap1 = 36U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Icap1 = 37U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Icap1 = 38U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Icap1 = 39U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Icap1 = 40U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Icap1 = 41U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Icap1 = 42U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Icap1 = 43U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Icap1 = 44U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Icap1 = 49U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Icap1 = 50U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Icap1 = 51U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Icap1 = 52U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Icap1 = 62U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Icap1 = 63U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Icap1 = 64U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Icap1 = 65U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Icap1 = 66U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Icap1 = 67U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Icap1 = 68U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Icap1 = 69U + (QDC1_ICAP0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTA0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm0Exta0 = 1U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Exta0 = 2U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Exta0 = 3U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Exta0 = 4U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Exta0 = 5U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0Exta0 = 6U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0Exta0 = 7U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm0Exta0 = 8U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Exta0 = 9U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Exta0 = 10U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Exta0 = 11U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Exta0 = 12U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Exta0 = 13U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Exta0 = 14U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Exta0 = 15U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Exta0 = 16U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Exta0 = 17U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Exta0 = 18U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Exta0 = 19U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0Exta0 = 20U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0Exta0 = 21U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0Exta0 = 22U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0Exta0 = 23U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0Exta0 = 24U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0Exta0 = 25U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0Exta0 = 26U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0Exta0 = 27U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0Exta0 = 28U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0Exta0 = 29U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm0Exta0 = 30U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm0Exta0 = 31U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Exta0 = 32U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Exta0 = 33U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Exta0 = 34U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Exta0 = 35U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Exta0 = 36U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Exta0 = 37U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Exta0 = 38U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Exta0 = 39U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Exta0 = 40U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Exta0 = 45U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Exta0 = 46U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Exta0 = 47U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Exta0 = 48U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Exta0 = 49U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Exta0 = 50U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Exta0 = 51U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Exta0 = 52U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Exta0 = 53U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Exta0 = 54U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Exta0 = 55U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Exta0 = 56U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Exta0 = 57U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Exta0 = 58U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Exta0 = 59U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm0Exta0 = 60U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm0Exta0 = 61U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTA1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm1Exta1 = 1U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Exta1 = 2U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Exta1 = 3U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Exta1 = 4U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Exta1 = 5U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1Exta1 = 6U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1Exta1 = 7U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm1Exta1 = 8U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Exta1 = 9U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Exta1 = 10U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Exta1 = 11U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Exta1 = 12U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Exta1 = 13U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Exta1 = 14U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Exta1 = 15U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Exta1 = 16U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Exta1 = 17U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Exta1 = 18U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Exta1 = 19U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1Exta1 = 20U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1Exta1 = 21U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1Exta1 = 22U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1Exta1 = 23U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1Exta1 = 24U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1Exta1 = 25U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1Exta1 = 26U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1Exta1 = 27U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1Exta1 = 28U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1Exta1 = 29U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm1Exta1 = 30U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm1Exta1 = 31U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Exta1 = 32U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Exta1 = 33U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Exta1 = 34U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Exta1 = 35U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Exta1 = 36U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Exta1 = 37U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Exta1 = 38U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Exta1 = 39U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Exta1 = 40U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Exta1 = 45U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Exta1 = 46U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Exta1 = 47U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Exta1 = 48U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Exta1 = 49U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Exta1 = 50U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Exta1 = 51U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Exta1 = 52U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Exta1 = 53U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Exta1 = 54U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Exta1 = 55U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Exta1 = 56U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Exta1 = 57U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Exta1 = 58U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Exta1 = 59U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm1Exta1 = 60U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm1Exta1 = 61U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTA2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm2Exta2 = 1U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Exta2 = 2U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Exta2 = 3U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Exta2 = 4U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Exta2 = 5U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2Exta2 = 6U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2Exta2 = 7U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm2Exta2 = 8U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Exta2 = 9U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Exta2 = 10U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Exta2 = 11U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Exta2 = 12U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Exta2 = 13U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Exta2 = 14U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Exta2 = 15U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Exta2 = 16U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Exta2 = 17U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Exta2 = 18U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Exta2 = 19U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2Exta2 = 20U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2Exta2 = 21U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2Exta2 = 22U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2Exta2 = 23U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2Exta2 = 24U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2Exta2 = 25U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2Exta2 = 26U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2Exta2 = 27U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2Exta2 = 28U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2Exta2 = 29U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm2Exta2 = 30U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm2Exta2 = 31U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Exta2 = 32U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Exta2 = 33U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Exta2 = 34U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Exta2 = 35U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Exta2 = 36U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Exta2 = 37U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Exta2 = 38U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Exta2 = 39U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Exta2 = 40U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Exta2 = 45U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Exta2 = 46U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Exta2 = 47U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Exta2 = 48U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Exta2 = 49U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Exta2 = 50U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Exta2 = 51U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Exta2 = 52U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Exta2 = 53U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Exta2 = 54U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Exta2 = 55U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Exta2 = 56U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Exta2 = 57U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Exta2 = 58U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Exta2 = 59U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm2Exta2 = 60U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm2Exta2 = 61U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTA3 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm3Exta3 = 1U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm3Exta3 = 2U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm3Exta3 = 3U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm3Exta3 = 4U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm3Exta3 = 5U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3Exta3 = 6U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3Exta3 = 7U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm3Exta3 = 8U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm3Exta3 = 9U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3Exta3 = 10U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm3Exta3 = 11U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3Exta3 = 12U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm3Exta3 = 13U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3Exta3 = 14U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm3Exta3 = 15U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm3Exta3 = 16U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm3Exta3 = 17U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm3Exta3 = 18U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm3Exta3 = 19U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3Exta3 = 20U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3Exta3 = 21U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3Exta3 = 22U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3Exta3 = 23U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3Exta3 = 24U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3Exta3 = 25U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3Exta3 = 26U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3Exta3 = 27U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3Exta3 = 28U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3Exta3 = 29U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm3Exta3 = 30U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm3Exta3 = 31U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm3Exta3 = 32U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm3Exta3 = 33U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3Exta3 = 34U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3Exta3 = 35U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm3Exta3 = 36U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm3Exta3 = 37U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm3Exta3 = 38U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm3Exta3 = 39U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm3Exta3 = 40U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm3Exta3 = 45U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm3Exta3 = 46U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm3Exta3 = 47U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm3Exta3 = 48U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm3Exta3 = 49U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm3Exta3 = 50U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm3Exta3 = 51U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm3Exta3 = 52U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm3Exta3 = 53U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm3Exta3 = 54U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm3Exta3 = 55U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm3Exta3 = 56U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm3Exta3 = 57U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm3Exta3 = 58U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm3Exta3 = 59U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm3Exta3 = 60U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm3Exta3 = 61U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTSYNC0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm0Extsync0 = 1U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Extsync0 = 2U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Extsync0 = 3U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Extsync0 = 4U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Extsync0 = 5U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0Extsync0 = 6U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0Extsync0 = 7U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm0Extsync0 = 8U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Extsync0 = 9U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Extsync0 = 10U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Extsync0 = 11U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Extsync0 = 12U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Extsync0 = 13U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Extsync0 = 14U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Extsync0 = 15U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Extsync0 = 16U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Extsync0 = 17U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Extsync0 = 18U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Extsync0 = 19U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0Extsync0 = 20U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0Extsync0 = 21U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0Extsync0 = 22U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0Extsync0 = 23U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0Extsync0 = 24U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0Extsync0 = 25U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0Extsync0 = 26U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0Extsync0 = 27U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0Extsync0 = 28U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0Extsync0 = 29U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm0Extsync0 = 30U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm0Extsync0 = 31U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Extsync0 = 32U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Extsync0 = 33U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Extsync0 = 34U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Extsync0 = 35U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Extsync0 = 36U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Extsync0 = 37U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Extsync0 = 38U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Extsync0 = 39U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Extsync0 = 40U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Extsync0 = 45U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Extsync0 = 46U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Extsync0 = 47U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Extsync0 = 48U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Extsync0 = 49U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Extsync0 = 50U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Extsync0 = 51U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Extsync0 = 52U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Extsync0 = 53U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Extsync0 = 54U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Extsync0 = 55U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Extsync0 = 56U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Extsync0 = 57U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Extsync0 = 58U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Extsync0 = 59U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm0Extsync0 = 60U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm0Extsync0 = 61U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTSYNC1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm1Extsync1 = 1U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Extsync1 = 2U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Extsync1 = 3U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Extsync1 = 4U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Extsync1 = 5U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1Extsync1 = 6U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1Extsync1 = 7U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm1Extsync1 = 8U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Extsync1 = 9U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Extsync1 = 10U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Extsync1 = 11U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Extsync1 = 12U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Extsync1 = 13U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Extsync1 = 14U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Extsync1 = 15U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Extsync1 = 16U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Extsync1 = 17U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Extsync1 = 18U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Extsync1 = 19U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1Extsync1 = 20U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1Extsync1 = 21U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1Extsync1 = 22U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1Extsync1 = 23U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1Extsync1 = 24U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1Extsync1 = 25U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1Extsync1 = 26U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1Extsync1 = 27U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1Extsync1 = 28U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1Extsync1 = 29U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm1Extsync1 = 30U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm1Extsync1 = 31U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Extsync1 = 32U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Extsync1 = 33U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Extsync1 = 34U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Extsync1 = 35U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Extsync1 = 36U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Extsync1 = 37U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Extsync1 = 38U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Extsync1 = 39U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Extsync1 = 40U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Extsync1 = 45U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Extsync1 = 46U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Extsync1 = 47U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Extsync1 = 48U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Extsync1 = 49U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Extsync1 = 50U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Extsync1 = 51U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Extsync1 = 52U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Extsync1 = 53U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Extsync1 = 54U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Extsync1 = 55U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Extsync1 = 56U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Extsync1 = 57U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Extsync1 = 58U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Extsync1 = 59U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm1Extsync1 = 60U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm1Extsync1 = 61U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm2Extsync2 = 1U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Extsync2 = 2U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Extsync2 = 3U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Extsync2 = 4U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Extsync2 = 5U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2Extsync2 = 6U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2Extsync2 = 7U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm2Extsync2 = 8U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Extsync2 = 9U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Extsync2 = 10U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Extsync2 = 11U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Extsync2 = 12U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Extsync2 = 13U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Extsync2 = 14U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Extsync2 = 15U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Extsync2 = 16U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Extsync2 = 17U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Extsync2 = 18U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Extsync2 = 19U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2Extsync2 = 20U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2Extsync2 = 21U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2Extsync2 = 22U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2Extsync2 = 23U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2Extsync2 = 24U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2Extsync2 = 25U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2Extsync2 = 26U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2Extsync2 = 27U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2Extsync2 = 28U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2Extsync2 = 29U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm2Extsync2 = 30U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm2Extsync2 = 31U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Extsync2 = 32U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Extsync2 = 33U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Extsync2 = 34U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Extsync2 = 35U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Extsync2 = 36U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Extsync2 = 37U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Extsync2 = 38U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Extsync2 = 39U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Extsync2 = 40U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Extsync2 = 45U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Extsync2 = 46U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Extsync2 = 47U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Extsync2 = 48U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Extsync2 = 49U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Extsync2 = 50U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Extsync2 = 51U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Extsync2 = 52U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Extsync2 = 53U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Extsync2 = 54U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Extsync2 = 55U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Extsync2 = 56U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Extsync2 = 57U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Extsync2 = 58U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Extsync2 = 59U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm2Extsync2 = 60U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm2Extsync2 = 61U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTSYNC3 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm3Extsync3 = 1U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm3Extsync3 = 2U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm3Extsync3 = 3U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm3Extsync3 = 4U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm3Extsync3 = 5U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3Extsync3 = 6U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3Extsync3 = 7U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm3Extsync3 = 8U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm3Extsync3 = 9U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3Extsync3 = 10U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm3Extsync3 = 11U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3Extsync3 = 12U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm3Extsync3 = 13U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3Extsync3 = 14U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm3Extsync3 = 15U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm3Extsync3 = 16U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm3Extsync3 = 17U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm3Extsync3 = 18U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm3Extsync3 = 19U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3Extsync3 = 20U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3Extsync3 = 21U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3Extsync3 = 22U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3Extsync3 = 23U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3Extsync3 = 24U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3Extsync3 = 25U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3Extsync3 = 26U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3Extsync3 = 27U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3Extsync3 = 28U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3Extsync3 = 29U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm3Extsync3 = 30U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm3Extsync3 = 31U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm3Extsync3 = 32U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm3Extsync3 = 33U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3Extsync3 = 34U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3Extsync3 = 35U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm3Extsync3 = 36U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm3Extsync3 = 37U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm3Extsync3 = 38U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm3Extsync3 = 39U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm3Extsync3 = 40U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm3Extsync3 = 45U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm3Extsync3 = 46U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm3Extsync3 = 47U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm3Extsync3 = 48U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm3Extsync3 = 49U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm3Extsync3 = 50U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm3Extsync3 = 51U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm3Extsync3 = 52U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm3Extsync3 = 53U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm3Extsync3 = 54U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm3Extsync3 = 55U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm3Extsync3 = 56U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm3Extsync3 = 57U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm3Extsync3 = 58U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm3Extsync3 = 59U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm3Extsync3 = 60U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm3Extsync3 = 61U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Fault = 1U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Fault = 2U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Fault = 3U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Fault = 4U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Fault = 5U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault = 6U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault = 7U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Fault = 8U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Fault = 9U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault = 10U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Fault = 11U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault = 12U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Fault = 13U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault = 14U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Fault = 15U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Fault = 16U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Fault = 17U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Fault = 18U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Fault = 19U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault = 20U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault = 21U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault = 22U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault = 23U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault = 24U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault = 25U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault = 26U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault = 27U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault = 28U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault = 29U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Fault = 30U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Fault = 31U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Fault = 32U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Fault = 33U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault = 34U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault = 35U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Fault = 36U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Fault = 37U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Fault = 38U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Fault = 39U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Fault = 40U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Fault = 45U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Fault = 46U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Fault = 47U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Fault = 48U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Fault = 49U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Fault = 50U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Fault = 51U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Fault = 52U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Fault = 53U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Fault = 54U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Fault = 55U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Fault = 56U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Fault = 57U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Fault = 58U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Fault = 59U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Fault = 60U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Fault = 61U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FORCE input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Force = 1U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Force = 2U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Force = 3U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Force = 4U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Force = 5U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Force = 6U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Force = 7U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Force = 8U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Force = 9U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Force = 10U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Force = 11U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Force = 12U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Force = 13U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Force = 14U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Force = 15U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Force = 16U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Force = 17U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Force = 18U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Force = 19U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Force = 20U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Force = 21U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Force = 22U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Force = 23U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Force = 24U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Force = 25U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Force = 26U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Force = 27U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Force = 28U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Force = 29U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Force = 30U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Force = 31U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Force = 32U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Force = 33U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Force = 34U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Force = 35U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Force = 36U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Force = 37U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Force = 38U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Force = 39U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Force = 40U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Force = 45U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Force = 46U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Force = 47U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Force = 48U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Force = 49U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Force = 50U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Force = 51U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Force = 52U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Force = 53U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Force = 54U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Force = 55U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Force = 56U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Force = 57U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Force = 58U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Force = 59U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Force = 60U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Force = 61U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTA0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm0Exta0 = 1U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm0Exta0 = 2U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm0Exta0 = 3U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm0Exta0 = 4U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm0Exta0 = 5U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0Exta0 = 6U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0Exta0 = 7U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm0Exta0 = 8U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm0Exta0 = 9U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Exta0 = 10U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm0Exta0 = 11U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Exta0 = 12U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm0Exta0 = 13U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Exta0 = 14U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm0Exta0 = 15U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm0Exta0 = 16U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm0Exta0 = 17U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm0Exta0 = 18U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm0Exta0 = 19U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0Exta0 = 20U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0Exta0 = 21U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0Exta0 = 22U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0Exta0 = 23U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0Exta0 = 24U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0Exta0 = 25U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0Exta0 = 26U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0Exta0 = 27U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0Exta0 = 28U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0Exta0 = 29U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm0Exta0 = 30U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm0Exta0 = 31U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm0Exta0 = 32U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm0Exta0 = 33U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Exta0 = 34U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Exta0 = 35U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm0Exta0 = 36U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm0Exta0 = 37U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm0Exta0 = 38U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm0Exta0 = 39U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm0Exta0 = 40U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm0Exta0 = 45U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm0Exta0 = 46U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm0Exta0 = 47U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm0Exta0 = 48U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm0Exta0 = 49U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm0Exta0 = 50U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm0Exta0 = 51U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm0Exta0 = 52U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm0Exta0 = 53U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm0Exta0 = 54U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm0Exta0 = 55U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm0Exta0 = 56U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm0Exta0 = 57U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm0Exta0 = 58U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm0Exta0 = 59U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm0Exta0 = 60U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm0Exta0 = 61U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTA1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm1Exta1 = 1U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm1Exta1 = 2U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm1Exta1 = 3U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm1Exta1 = 4U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm1Exta1 = 5U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1Exta1 = 6U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1Exta1 = 7U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm1Exta1 = 8U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm1Exta1 = 9U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Exta1 = 10U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm1Exta1 = 11U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Exta1 = 12U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm1Exta1 = 13U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Exta1 = 14U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm1Exta1 = 15U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm1Exta1 = 16U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm1Exta1 = 17U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm1Exta1 = 18U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm1Exta1 = 19U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1Exta1 = 20U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1Exta1 = 21U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1Exta1 = 22U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1Exta1 = 23U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1Exta1 = 24U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1Exta1 = 25U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1Exta1 = 26U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1Exta1 = 27U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1Exta1 = 28U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1Exta1 = 29U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm1Exta1 = 30U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm1Exta1 = 31U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm1Exta1 = 32U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm1Exta1 = 33U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Exta1 = 34U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Exta1 = 35U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm1Exta1 = 36U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm1Exta1 = 37U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm1Exta1 = 38U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm1Exta1 = 39U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm1Exta1 = 40U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm1Exta1 = 45U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm1Exta1 = 46U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm1Exta1 = 47U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm1Exta1 = 48U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm1Exta1 = 49U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm1Exta1 = 50U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm1Exta1 = 51U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm1Exta1 = 52U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm1Exta1 = 53U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm1Exta1 = 54U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm1Exta1 = 55U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm1Exta1 = 56U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm1Exta1 = 57U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm1Exta1 = 58U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm1Exta1 = 59U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm1Exta1 = 60U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm1Exta1 = 61U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTA2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm2Exta2 = 1U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm2Exta2 = 2U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm2Exta2 = 3U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm2Exta2 = 4U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm2Exta2 = 5U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2Exta2 = 6U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2Exta2 = 7U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm2Exta2 = 8U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm2Exta2 = 9U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Exta2 = 10U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm2Exta2 = 11U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Exta2 = 12U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm2Exta2 = 13U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Exta2 = 14U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm2Exta2 = 15U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm2Exta2 = 16U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm2Exta2 = 17U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm2Exta2 = 18U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm2Exta2 = 19U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2Exta2 = 20U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2Exta2 = 21U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2Exta2 = 22U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2Exta2 = 23U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2Exta2 = 24U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2Exta2 = 25U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2Exta2 = 26U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2Exta2 = 27U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2Exta2 = 28U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2Exta2 = 29U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm2Exta2 = 30U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm2Exta2 = 31U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm2Exta2 = 32U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm2Exta2 = 33U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Exta2 = 34U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Exta2 = 35U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm2Exta2 = 36U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm2Exta2 = 37U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm2Exta2 = 38U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm2Exta2 = 39U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm2Exta2 = 40U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm2Exta2 = 45U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm2Exta2 = 46U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm2Exta2 = 47U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm2Exta2 = 48U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm2Exta2 = 49U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm2Exta2 = 50U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm2Exta2 = 51U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm2Exta2 = 52U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm2Exta2 = 53U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm2Exta2 = 54U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm2Exta2 = 55U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm2Exta2 = 56U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm2Exta2 = 57U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm2Exta2 = 58U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm2Exta2 = 59U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm2Exta2 = 60U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm2Exta2 = 61U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTA3 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm3Exta3 = 1U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm3Exta3 = 2U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm3Exta3 = 3U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm3Exta3 = 4U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm3Exta3 = 5U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3Exta3 = 6U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3Exta3 = 7U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm3Exta3 = 8U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm3Exta3 = 9U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Exta3 = 10U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm3Exta3 = 11U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Exta3 = 12U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm3Exta3 = 13U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Exta3 = 14U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm3Exta3 = 15U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm3Exta3 = 16U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm3Exta3 = 17U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm3Exta3 = 18U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm3Exta3 = 19U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3Exta3 = 20U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3Exta3 = 21U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3Exta3 = 22U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3Exta3 = 23U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3Exta3 = 24U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3Exta3 = 25U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3Exta3 = 26U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3Exta3 = 27U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3Exta3 = 28U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3Exta3 = 29U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm3Exta3 = 30U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm3Exta3 = 31U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm3Exta3 = 32U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm3Exta3 = 33U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3Exta3 = 34U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3Exta3 = 35U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm3Exta3 = 36U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm3Exta3 = 37U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm3Exta3 = 38U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm3Exta3 = 39U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm3Exta3 = 40U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm3Exta3 = 45U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm3Exta3 = 46U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm3Exta3 = 47U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm3Exta3 = 48U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm3Exta3 = 49U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm3Exta3 = 50U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm3Exta3 = 51U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm3Exta3 = 52U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm3Exta3 = 53U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm3Exta3 = 54U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm3Exta3 = 55U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm3Exta3 = 56U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm3Exta3 = 57U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm3Exta3 = 58U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm3Exta3 = 59U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm3Exta3 = 60U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm3Exta3 = 61U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTSYNC0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm0Extsync0 = 1U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm0Extsync0 = 2U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm0Extsync0 = 3U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm0Extsync0 = 4U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm0Extsync0 = 5U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0Extsync0 = 6U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0Extsync0 = 7U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm0Extsync0 = 8U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm0Extsync0 = 9U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Extsync0 = 10U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm0Extsync0 = 11U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Extsync0 = 12U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm0Extsync0 = 13U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Extsync0 = 14U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm0Extsync0 = 15U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm0Extsync0 = 16U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm0Extsync0 = 17U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm0Extsync0 = 18U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm0Extsync0 = 19U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0Extsync0 = 20U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0Extsync0 = 21U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0Extsync0 = 22U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0Extsync0 = 23U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0Extsync0 = 24U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0Extsync0 = 25U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0Extsync0 = 26U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0Extsync0 = 27U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0Extsync0 = 28U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0Extsync0 = 29U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm0Extsync0 = 30U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm0Extsync0 = 31U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm0Extsync0 = 32U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm0Extsync0 = 33U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Extsync0 = 34U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Extsync0 = 35U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm0Extsync0 = 36U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm0Extsync0 = 37U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm0Extsync0 = 38U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm0Extsync0 = 39U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm0Extsync0 = 40U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm0Extsync0 = 45U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm0Extsync0 = 46U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm0Extsync0 = 47U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm0Extsync0 = 48U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm0Extsync0 = 49U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm0Extsync0 = 50U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm0Extsync0 = 51U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm0Extsync0 = 52U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm0Extsync0 = 53U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm0Extsync0 = 54U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm0Extsync0 = 55U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm0Extsync0 = 56U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm0Extsync0 = 57U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm0Extsync0 = 58U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm0Extsync0 = 59U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm0Extsync0 = 60U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm0Extsync0 = 61U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTSYNC1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm1Extsync1 = 1U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm1Extsync1 = 2U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm1Extsync1 = 3U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm1Extsync1 = 4U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm1Extsync1 = 5U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1Extsync1 = 6U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1Extsync1 = 7U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm1Extsync1 = 8U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm1Extsync1 = 9U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Extsync1 = 10U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm1Extsync1 = 11U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Extsync1 = 12U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm1Extsync1 = 13U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Extsync1 = 14U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm1Extsync1 = 15U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm1Extsync1 = 16U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm1Extsync1 = 17U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm1Extsync1 = 18U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm1Extsync1 = 19U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1Extsync1 = 20U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1Extsync1 = 21U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1Extsync1 = 22U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1Extsync1 = 23U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1Extsync1 = 24U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1Extsync1 = 25U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1Extsync1 = 26U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1Extsync1 = 27U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1Extsync1 = 28U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1Extsync1 = 29U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm1Extsync1 = 30U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm1Extsync1 = 31U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm1Extsync1 = 32U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm1Extsync1 = 33U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Extsync1 = 34U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Extsync1 = 35U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm1Extsync1 = 36U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm1Extsync1 = 37U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm1Extsync1 = 38U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm1Extsync1 = 39U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm1Extsync1 = 40U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm1Extsync1 = 45U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm1Extsync1 = 46U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm1Extsync1 = 47U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm1Extsync1 = 48U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm1Extsync1 = 49U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm1Extsync1 = 50U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm1Extsync1 = 51U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm1Extsync1 = 52U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm1Extsync1 = 53U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm1Extsync1 = 54U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm1Extsync1 = 55U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm1Extsync1 = 56U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm1Extsync1 = 57U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm1Extsync1 = 58U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm1Extsync1 = 59U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm1Extsync1 = 60U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm1Extsync1 = 61U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm2Extsync2 = 1U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm2Extsync2 = 2U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm2Extsync2 = 3U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm2Extsync2 = 4U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm2Extsync2 = 5U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2Extsync2 = 6U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2Extsync2 = 7U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm2Extsync2 = 8U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm2Extsync2 = 9U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Extsync2 = 10U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm2Extsync2 = 11U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Extsync2 = 12U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm2Extsync2 = 13U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Extsync2 = 14U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm2Extsync2 = 15U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm2Extsync2 = 16U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm2Extsync2 = 17U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm2Extsync2 = 18U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm2Extsync2 = 19U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2Extsync2 = 20U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2Extsync2 = 21U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2Extsync2 = 22U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2Extsync2 = 23U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2Extsync2 = 24U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2Extsync2 = 25U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2Extsync2 = 26U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2Extsync2 = 27U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2Extsync2 = 28U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2Extsync2 = 29U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm2Extsync2 = 30U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm2Extsync2 = 31U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm2Extsync2 = 32U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm2Extsync2 = 33U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Extsync2 = 34U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Extsync2 = 35U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm2Extsync2 = 36U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm2Extsync2 = 37U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm2Extsync2 = 38U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm2Extsync2 = 39U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm2Extsync2 = 40U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm2Extsync2 = 45U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm2Extsync2 = 46U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm2Extsync2 = 47U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm2Extsync2 = 48U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm2Extsync2 = 49U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm2Extsync2 = 50U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm2Extsync2 = 51U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm2Extsync2 = 52U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm2Extsync2 = 53U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm2Extsync2 = 54U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm2Extsync2 = 55U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm2Extsync2 = 56U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm2Extsync2 = 57U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm2Extsync2 = 58U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm2Extsync2 = 59U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm2Extsync2 = 60U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm2Extsync2 = 61U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTSYNC3 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm3Extsync3 = 1U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm3Extsync3 = 2U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm3Extsync3 = 3U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm3Extsync3 = 4U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm3Extsync3 = 5U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3Extsync3 = 6U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3Extsync3 = 7U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm3Extsync3 = 8U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm3Extsync3 = 9U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Extsync3 = 10U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm3Extsync3 = 11U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Extsync3 = 12U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm3Extsync3 = 13U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Extsync3 = 14U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm3Extsync3 = 15U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm3Extsync3 = 16U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm3Extsync3 = 17U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm3Extsync3 = 18U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm3Extsync3 = 19U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3Extsync3 = 20U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3Extsync3 = 21U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3Extsync3 = 22U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3Extsync3 = 23U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3Extsync3 = 24U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3Extsync3 = 25U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3Extsync3 = 26U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3Extsync3 = 27U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3Extsync3 = 28U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3Extsync3 = 29U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm3Extsync3 = 30U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm3Extsync3 = 31U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm3Extsync3 = 32U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm3Extsync3 = 33U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3Extsync3 = 34U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3Extsync3 = 35U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm3Extsync3 = 36U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm3Extsync3 = 37U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm3Extsync3 = 38U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm3Extsync3 = 39U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm3Extsync3 = 40U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm3Extsync3 = 45U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm3Extsync3 = 46U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm3Extsync3 = 47U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm3Extsync3 = 48U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm3Extsync3 = 49U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm3Extsync3 = 50U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm3Extsync3 = 51U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm3Extsync3 = 52U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm3Extsync3 = 53U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm3Extsync3 = 54U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm3Extsync3 = 55U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm3Extsync3 = 56U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm3Extsync3 = 57U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm3Extsync3 = 58U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm3Extsync3 = 59U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm3Extsync3 = 60U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm3Extsync3 = 61U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Fault = 1U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Fault = 2U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Fault = 3U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Fault = 4U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Fault = 5U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault = 6U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault = 7U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Fault = 8U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Fault = 9U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault = 10U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Fault = 11U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault = 12U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Fault = 13U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault = 14U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Fault = 15U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Fault = 16U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Fault = 17U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Fault = 18U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Fault = 19U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault = 20U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault = 21U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault = 22U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault = 23U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault = 24U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault = 25U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault = 26U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault = 27U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault = 28U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault = 29U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Fault = 30U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Fault = 31U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Fault = 32U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Fault = 33U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault = 34U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault = 35U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Fault = 36U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Fault = 37U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Fault = 38U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Fault = 39U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Fault = 40U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Fault = 45U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Fault = 46U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Fault = 47U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Fault = 48U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Fault = 49U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Fault = 50U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Fault = 51U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Fault = 52U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Fault = 53U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Fault = 54U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Fault = 55U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Fault = 56U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Fault = 57U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Fault = 58U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Fault = 59U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Fault = 60U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Fault = 61U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FORCE input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Force = 1U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Force = 2U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Force = 3U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Force = 4U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Force = 5U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Force = 6U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Force = 7U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Force = 8U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Force = 9U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Force = 10U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Force = 11U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Force = 12U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Force = 13U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Force = 14U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Force = 15U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Force = 16U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Force = 17U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Force = 18U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Force = 19U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Force = 20U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Force = 21U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Force = 22U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Force = 23U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Force = 24U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Force = 25U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Force = 26U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Force = 27U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Force = 28U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Force = 29U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Force = 30U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Force = 31U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Force = 32U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Force = 33U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Force = 34U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Force = 35U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Force = 36U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Force = 37U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Force = 38U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Force = 39U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Force = 40U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Force = 45U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Force = 46U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Force = 47U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Force = 48U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Force = 49U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Force = 50U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Force = 51U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Force = 52U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Force = 53U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Force = 54U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Force = 55U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Force = 56U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Force = 57U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Force = 58U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Force = 59U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Force = 60U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Force = 61U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + + /*!< PWM0 external clock trigger. */ + kINPUTMUX_Clk16K1ToPwm0ExtClk = 1U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ClkInToPwm0ExtClk = 2U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm0ExtClk = 3U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm0ExtClk = 4U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm0ExtClk = 5U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn7ToPwm0ExtClk = 6U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm0ExtClk = 7U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm0ExtClk = 8U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + + /*!< PWM1 external clock trigger. */ + kINPUTMUX_Clk16K1ToPwm1ExtClk = 1U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ClkInToPwm1ExtClk = 2U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm1ExtClk = 3U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm1ExtClk = 4U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm1ExtClk = 5U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn7ToPwm1ExtClk = 6U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm1ExtClk = 7U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm1ExtClk = 8U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + + /*!< AOI0 trigger input connections. */ + kINPUTMUX_Adc0Tcomp0ToAoi0Mux = 1U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAoi0Mux = 2U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAoi0Mux = 3U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAoi0Mux = 4U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAoi0Mux = 5U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAoi0Mux = 6U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAoi0Mux = 7U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAoi0Mux = 8U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAoi0Mux = 9U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToAoi0Mux = 10U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAoi0Mux = 11U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAoi0Mux = 12U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAoi0Mux = 13U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToAoi0Mux = 14U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAoi0Mux = 15U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAoi0Mux = 16U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAoi0Mux = 17U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToAoi0Mux = 18U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAoi0Mux = 19U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAoi0Mux = 20U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToAoi0Mux = 22U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToAoi0Mux = 23U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToAoi0Mux = 24U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToAoi0Mux = 25U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatchToAoi0Mux = 26U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAoi0Mux = 27U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAoi0Mux = 28U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAoi0Mux = 29U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAoi0Mux = 30U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAoi0Mux = 31U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAoi0Mux = 32U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAoi0Mux = 33U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAoi0Mux = 34U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToAoi0Mux = 35U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToAoi0Mux = 36U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToAoi0Mux = 37U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToAoi0Mux = 38U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToAoi0Mux = 39U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToAoi0Mux = 40U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToAoi0Mux = 41U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToAoi0Mux = 42U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToAoi0Mux = 43U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToAoi0Mux = 44U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToAoi0Mux = 45U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToAoi0Mux = 46U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAoi0Mux = 47U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAoi0Mux = 48U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAoi0Mux = 49U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAoi0Mux = 50U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAoi0Mux = 51U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAoi0Mux = 52U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAoi0Mux = 53U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAoi0Mux = 54U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAoi0Mux = 55U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAoi0Mux = 56U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAoi0Mux = 57U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAoi0Mux = 58U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAoi0Mux = 59U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAoi0Mux = 60U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAoi0Mux = 61U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToAoi0Mux = 62U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAoi0Mux = 63U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAoi0Mux = 64U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAoi0Mux = 65U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAoi0Mux = 66U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAoi0Mux = 67U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToAoi0Mux = 68U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToAoi0Mux = 69U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToAoi0Mux = 70U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToAoi0Mux = 71U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatchToAoi0Mux = 72U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAoi0Mux = 73U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAoi0Mux = 74U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAoi0Mux = 75U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAoi0Mux = 76U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAoi0Mux = 77U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAoi0Mux = 78U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAoi0Mux = 79U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAoi0Mux = 80U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0AOutToAoi0Mux = 81U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0BOutToAoi0Mux = 82U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1AOutToAoi0Mux = 83U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1BOutToAoi0Mux = 84U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2AOutToAoi0Mux = 85U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2BOutToAoi0Mux = 86U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3AOutToAoi0Mux = 87U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3BOutToAoi0Mux = 88U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToAoi0Mux = 89U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToAoi0Mux = 90U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToAoi0Mux = 91U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToAoi0Mux = 92U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToAoi0Mux = 93U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToAoi0Mux = 94U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToAoi0Mux = 95U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToAoi0Mux = 96U + (AOI0_MUX_REG << PMUX_SHIFT), + + /*!< AOI1 trigger input connections. */ + kINPUTMUX_Adc0Tcomp0ToAoi1Mux = 1U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAoi1Mux = 2U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAoi1Mux = 3U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAoi1Mux = 4U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAoi1Mux = 5U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAoi1Mux = 6U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAoi1Mux = 6U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAoi1Mux = 8U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAoi1Mux = 9U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToAoi1Mux = 10U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAoi1Mux = 11U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAoi1Mux = 12U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAoi1Mux = 13U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToAoi1Mux = 14U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAoi1Mux = 15U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAoi1Mux = 16U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAoi1Mux = 17U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToAoi1Mux = 18U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAoi1Mux = 19U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAoi1Mux = 20U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToAoi1Mux = 22U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToAoi1Mux = 23U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToAoi1Mux = 24U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToAoi1Mux = 25U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatchToAoi1Mux = 26U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAoi1Mux = 27U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAoi1Mux = 28U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAoi1Mux = 29U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAoi1Mux = 30U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAoi1Mux = 31U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAoi1Mux = 32U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAoi1Mux = 33U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAoi1Mux = 34U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToAoi1Mux = 35U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToAoi1Mux = 36U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToAoi1Mux = 37U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToAoi1Mux = 38U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToAoi1Mux = 39U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToAoi1Mux = 40U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToAoi1Mux = 41U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToAoi1Mux = 42U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToAoi1Mux = 43U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToAoi1Mux = 44U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToAoi1Mux = 45U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToAoi1Mux = 46U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAoi1Mux = 47U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAoi1Mux = 48U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAoi1Mux = 49U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAoi1Mux = 50U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAoi1Mux = 51U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAoi1Mux = 52U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAoi1Mux = 53U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAoi1Mux = 54U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAoi1Mux = 55U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAoi1Mux = 56U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAoi1Mux = 57U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAoi1Mux = 58U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAoi1Mux = 59U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAoi1Mux = 60U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAoi1Mux = 61U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToAoi1Mux = 62U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAoi1Mux = 63U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAoi1Mux = 64U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAoi1Mux = 65U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAoi1Mux = 66U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAoi1Mux = 67U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToAoi1Mux = 68U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToAoi1Mux = 69U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToAoi1Mux = 70U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToAoi1Mux = 71U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatchToAoi1Mux = 72U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAoi1Mux = 73U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAoi1Mux = 74U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAoi1Mux = 75U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAoi1Mux = 76U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAoi1Mux = 77U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAoi1Mux = 78U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAoi1Mux = 79U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAoi1Mux = 80U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0AOutToAoi1Mux = 81U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0BOutToAoi1Mux = 82U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1AOutToAoi1Mux = 83U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1BOutToAoi1Mux = 84U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2AOutToAoi1Mux = 85U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2BOutToAoi1Mux = 86U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3AOutToAoi1Mux = 87U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3BOutToAoi1Mux = 88U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToAoi1Mux = 89U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToAoi1Mux = 90U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToAoi1Mux = 91U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToAoi1Mux = 92U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToAoi1Mux = 93U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToAoi1Mux = 94U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToAoi1Mux = 95U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToAoi1Mux = 96U + (AOI1_MUX_REG << PMUX_SHIFT), + + /*!< USB-FS trigger input connections. */ + kINPUTMUX_Lpuart0TrgTxdataToUsbfsTrigger = 1U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1TrgTxdataToUsbfsTrigger = 2U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2TrgTxdataToUsbfsTrigger = 3U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3TrgTxdataToUsbfsTrigger = 4U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4TrgTxdataToUsbfsTrigger = 5U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart5TrgTxdataToUsbfsTrigger = 6U + (USBFS_TRIG_REG << PMUX_SHIFT), + + /*!< EXT trigger connections. */ + kINPUTMUX_Aoi0Out0ToExtTrigger = 2U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToExtTrigger = 3U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToExtTrigger = 4U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToExtTrigger = 5U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToExtTrigger = 6U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToExtTrigger = 7U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToExtTrigger = 8U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0ToExtTrigger = 9U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1ToExtTrigger = 10U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2ToExtTrigger = 11U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3ToExtTrigger = 12U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4ToExtTrigger = 13U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToExtTrigger = 14U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToExtTrigger = 15U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToExtTrigger = 16U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToExtTrigger = 17U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart5ToExtTrigger = 18U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Rtc1HZClkToExtTrigger = 19U + (EXT_TRIG0_REG << PMUX_SHIFT), + + /*!< LPI2C0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c0Trigger = 2U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c0Trigger = 3U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c0Trigger = 4U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c0Trigger = 5U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c0Trigger = 6U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c0Trigger = 7U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpi2c0Trigger = 8U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c0Trigger = 9U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c0Trigger = 10U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c0Trigger = 11U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c0Trigger = 12U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c0Trigger = 13U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c0Trigger = 14U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c0Trigger = 15U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c0Trigger = 17U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c0Trigger = 18U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c0Trigger = 19U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c0Trigger = 20U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c0Trigger = 21U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c0Trigger = 22U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c0Trigger = 23U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c0Trigger = 24U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c0Trigger = 25U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c0Trigger = 26U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c0Trigger = 27U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c0Trigger = 28U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c0Trigger = 29U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c0Trigger = 30U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c0Trigger = 31U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c0Trigger = 32U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c0Trigger = 33U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c0Trigger = 34U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c0Trigger = 35U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c0Trigger = 36U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c0Trigger = 37U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c0Trigger = 38U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c0Trigger = 39U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c0Trigger = 40U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c0Trigger = 41U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c0Trigger = 42U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + + /*!< LPI2C1 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c1Trigger = 2U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c1Trigger = 3U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c1Trigger = 4U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c1Trigger = 5U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c1Trigger = 6U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c1Trigger = 7U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpi2c1Trigger = 8U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c1Trigger = 9U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c1Trigger = 10U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c1Trigger = 11U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c1Trigger = 12U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c1Trigger = 13U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c1Trigger = 14U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c1Trigger = 15U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c1Trigger = 17U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c1Trigger = 18U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c1Trigger = 19U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c1Trigger = 20U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c1Trigger = 21U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c1Trigger = 22U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c1Trigger = 23U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c1Trigger = 24U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c1Trigger = 25U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c1Trigger = 26U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c1Trigger = 27U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c1Trigger = 28U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c1Trigger = 29U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c1Trigger = 30U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c1Trigger = 31U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c1Trigger = 32U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c1Trigger = 33U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c1Trigger = 34U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c1Trigger = 35U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c1Trigger = 36U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c1Trigger = 37U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c1Trigger = 38U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c1Trigger = 39U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c1Trigger = 40U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c1Trigger = 41U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c1Trigger = 42U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + + /*!< LPI2C2 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c2Trigger = 2U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c2Trigger = 3U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c2Trigger = 4U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c2Trigger = 5U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c2Trigger = 6U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c2Trigger = 7U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpi2c2Trigger = 8U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c2Trigger = 9U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c2Trigger = 10U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c2Trigger = 11U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c2Trigger = 12U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c2Trigger = 13U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c2Trigger = 14U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c2Trigger = 15U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c2Trigger = 17U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c2Trigger = 18U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c2Trigger = 19U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c2Trigger = 20U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c2Trigger = 21U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c2Trigger = 22U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c2Trigger = 23U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c2Trigger = 24U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c2Trigger = 25U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c2Trigger = 26U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c2Trigger = 27U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c2Trigger = 28U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c2Trigger = 29U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c2Trigger = 30U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c2Trigger = 31U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c2Trigger = 32U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c2Trigger = 33U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c2Trigger = 34U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c2Trigger = 35U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c2Trigger = 36U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c2Trigger = 37U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c2Trigger = 38U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c2Trigger = 39U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c2Trigger = 40U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c2Trigger = 41U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c2Trigger = 42U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + + /*!< LPI2C3 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c3Trigger = 2U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c3Trigger = 3U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c3Trigger = 4U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c3Trigger = 5U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c3Trigger = 6U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c3Trigger = 7U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpi2c3Trigger = 8U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c3Trigger = 9U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c3Trigger = 10U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c3Trigger = 11U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c3Trigger = 12U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c3Trigger = 13U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c3Trigger = 14U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c3Trigger = 15U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c3Trigger = 17U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c3Trigger = 18U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c3Trigger = 19U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c3Trigger = 20U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c3Trigger = 21U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c3Trigger = 22U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c3Trigger = 23U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c3Trigger = 24U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c3Trigger = 25U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c3Trigger = 26U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c3Trigger = 27U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c3Trigger = 28U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c3Trigger = 29U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c3Trigger = 30U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c3Trigger = 31U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c3Trigger = 32U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c3Trigger = 33U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c3Trigger = 34U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c3Trigger = 35U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c3Trigger = 36U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c3Trigger = 37U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c3Trigger = 38U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c3Trigger = 39U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c3Trigger = 40U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c3Trigger = 41U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c3Trigger = 42U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + + /*!< LPSPI0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpspi0Trigger = 2U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpspi0Trigger = 3U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpspi0Trigger = 4U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpspi0Trigger = 5U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpspi0Trigger = 6U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpspi0Trigger = 7U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpspi0Trigger = 8U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpspi0Trigger = 9U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpspi0Trigger = 10U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpspi0Trigger = 11U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpspi0Trigger = 12U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpspi0Trigger = 13U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpspi0Trigger = 14U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpspi0Trigger = 15U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpspi0Trigger = 17U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpspi0Trigger = 18U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpspi0Trigger = 19U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpspi0Trigger = 20U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpspi0Trigger = 21U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpspi0Trigger = 22U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpspi0Trigger = 23U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpspi0Trigger = 24U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpspi0Trigger = 25U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpspi0Trigger = 26U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpspi0Trigger = 27U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpspi0Trigger = 28U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpspi0Trigger = 29U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpspi0Trigger = 30U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpspi0Trigger = 31U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpspi0Trigger = 32U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpspi0Trigger = 33U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpspi0Trigger = 34U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpspi0Trigger = 35U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpspi0Trigger = 36U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpspi0Trigger = 37U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpspi0Trigger = 38U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpspi0Trigger = 39U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpspi0Trigger = 40U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpspi0Trigger = 41U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpspi0Trigger = 42U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + + /*!< LPSPI1 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpspi1Trigger = 2U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpspi1Trigger = 3U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpspi1Trigger = 4U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpspi1Trigger = 5U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpspi1Trigger = 6U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpspi1Trigger = 7U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpspi1Trigger = 7U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpspi1Trigger = 9U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpspi1Trigger = 10U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpspi1Trigger = 11U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpspi1Trigger = 12U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpspi1Trigger = 13U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpspi1Trigger = 14U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpspi1Trigger = 15U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpspi1Trigger = 17U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpspi1Trigger = 18U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpspi1Trigger = 19U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpspi1Trigger = 20U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpspi1Trigger = 21U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpspi1Trigger = 22U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpspi1Trigger = 23U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpspi1Trigger = 24U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpspi1Trigger = 25U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpspi1Trigger = 26U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpspi1Trigger = 27U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpspi1Trigger = 28U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpspi1Trigger = 29U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpspi1Trigger = 30U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpspi1Trigger = 31U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpspi1Trigger = 32U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpspi1Trigger = 33U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpspi1Trigger = 34U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpspi1Trigger = 35U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpspi1Trigger = 36U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpspi1Trigger = 37U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpspi1Trigger = 38U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpspi1Trigger = 39U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpspi1Trigger = 40U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpspi1Trigger = 41U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpspi1Trigger = 42U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart0Trigger = 2U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart0Trigger = 3U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart0Trigger = 4U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart0Trigger = 5U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart0Trigger = 6U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart0Trigger = 7U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart0Trigger = 7U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart0Trigger = 9U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart0Trigger = 10U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart0Trigger = 11U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart0Trigger = 12U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart0Trigger = 13U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart0Trigger = 14U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart0Trigger = 15U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart0Trigger = 17U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart0Trigger = 18U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart0Trigger = 19U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart0Trigger = 20U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart0Trigger = 21U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart0Trigger = 22U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart0Trigger = 23U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart0Trigger = 24U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart0Trigger = 25U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart0Trigger = 26U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart0Trigger = 27U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart0Trigger = 28U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart0Trigger = 29U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart0Trigger = 30U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart0Trigger = 31U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart0Trigger = 32U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart0Trigger = 33U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart0Trigger = 34U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart0Trigger = 35U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart0Trigger = 36U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart0Trigger = 37U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart0Trigger = 38U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart0Trigger = 39U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart0Trigger = 40U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart0Trigger = 41U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart0Trigger = 42U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart0Trigger = 43U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart0Trigger = 44U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart0Trigger = 45U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart0Trigger = 46U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart0Trigger = 47U + (LPUART0_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART1 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart1Trigger = 2U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart1Trigger = 3U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart1Trigger = 4U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart1Trigger = 5U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart1Trigger = 6U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart1Trigger = 7U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart1Trigger = 8U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart1Trigger = 9U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart1Trigger = 10U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart1Trigger = 11U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart1Trigger = 12U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart1Trigger = 13U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart1Trigger = 14U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart1Trigger = 15U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart1Trigger = 17U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart1Trigger = 18U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart1Trigger = 19U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart1Trigger = 20U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart1Trigger = 21U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart1Trigger = 22U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart1Trigger = 23U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart1Trigger = 24U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart1Trigger = 25U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart1Trigger = 26U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart1Trigger = 27U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart1Trigger = 28U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart1Trigger = 29U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart1Trigger = 30U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart1Trigger = 31U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart1Trigger = 32U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart1Trigger = 33U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart1Trigger = 34U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart1Trigger = 35U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart1Trigger = 36U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart1Trigger = 37U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart1Trigger = 38U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart1Trigger = 39U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart1Trigger = 40U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart1Trigger = 41U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart1Trigger = 42U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart1Trigger = 43U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart1Trigger = 44U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart1Trigger = 45U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart1Trigger = 46U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart1Trigger = 47U + (LPUART1_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART2 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart2Trigger = 2U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart2Trigger = 3U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart2Trigger = 4U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart2Trigger = 5U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart2Trigger = 6U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart2Trigger = 7U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart2Trigger = 8U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart2Trigger = 9U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart2Trigger = 10U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart2Trigger = 11U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart2Trigger = 12U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart2Trigger = 13U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart2Trigger = 14U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart2Trigger = 15U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart2Trigger = 17U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart2Trigger = 18U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart2Trigger = 19U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart2Trigger = 20U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart2Trigger = 21U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart2Trigger = 22U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart2Trigger = 23U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart2Trigger = 24U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart2Trigger = 25U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart2Trigger = 26U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart2Trigger = 27U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart2Trigger = 28U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart2Trigger = 29U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart2Trigger = 30U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart2Trigger = 31U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart2Trigger = 32U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart2Trigger = 33U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart2Trigger = 34U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart2Trigger = 35U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart2Trigger = 36U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart2Trigger = 37U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart2Trigger = 38U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart2Trigger = 39U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart2Trigger = 40U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart2Trigger = 41U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart2Trigger = 42U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart2Trigger = 43U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart2Trigger = 44U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart2Trigger = 45U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart2Trigger = 46U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart2Trigger = 47U + (LPUART2_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART3 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart3Trigger = 2U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart3Trigger = 3U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart3Trigger = 4U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart3Trigger = 5U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart3Trigger = 6U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart3Trigger = 7U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart3Trigger = 8U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart3Trigger = 9U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart3Trigger = 10U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart3Trigger = 11U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart3Trigger = 12U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart3Trigger = 13U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart3Trigger = 14U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart3Trigger = 15U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart3Trigger = 17U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart3Trigger = 18U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart3Trigger = 19U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart3Trigger = 20U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart3Trigger = 21U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart3Trigger = 22U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart3Trigger = 23U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart3Trigger = 24U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart3Trigger = 25U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart3Trigger = 26U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart3Trigger = 27U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart3Trigger = 28U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart3Trigger = 29U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart3Trigger = 30U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart3Trigger = 31U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart3Trigger = 32U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart3Trigger = 33U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart3Trigger = 34U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart3Trigger = 35U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart3Trigger = 36U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart3Trigger = 37U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart3Trigger = 38U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart3Trigger = 39U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart3Trigger = 40U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart3Trigger = 41U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart3Trigger = 42U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart3Trigger = 43U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart3Trigger = 44U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart3Trigger = 45U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart3Trigger = 46U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart3Trigger = 47U + (LPUART3_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART4 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart4Trigger = 2U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart4Trigger = 3U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart4Trigger = 4U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart4Trigger = 5U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart4Trigger = 6U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart4Trigger = 7U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart4Trigger = 8U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart4Trigger = 9U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart4Trigger = 10U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart4Trigger = 11U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart4Trigger = 12U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart4Trigger = 13U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart4Trigger = 14U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart4Trigger = 15U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart4Trigger = 17U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart4Trigger = 18U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart4Trigger = 19U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart4Trigger = 20U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart4Trigger = 21U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart4Trigger = 22U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart4Trigger = 23U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart4Trigger = 24U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart4Trigger = 25U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart4Trigger = 26U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart4Trigger = 27U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart4Trigger = 28U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart4Trigger = 29U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart4Trigger = 30U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart4Trigger = 31U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart4Trigger = 32U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart4Trigger = 33U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart4Trigger = 34U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart4Trigger = 35U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart4Trigger = 36U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart4Trigger = 37U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart4Trigger = 38U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart4Trigger = 39U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart4Trigger = 40U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart4Trigger = 41U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart4Trigger = 42U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart4Trigger = 43U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart4Trigger = 44U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart4Trigger = 45U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart4Trigger = 46U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart4Trigger = 47U + (LPUART4_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART5 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart5Trigger = 2U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart5Trigger = 3U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart5Trigger = 4U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart5Trigger = 5U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart5Trigger = 6U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart5Trigger = 7U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart5Trigger = 8U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart5Trigger = 9U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart5Trigger = 10U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart5Trigger = 11U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart5Trigger = 12U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart5Trigger = 13U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart5Trigger = 14U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart5Trigger = 15U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart5Trigger = 17U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart5Trigger = 18U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart5Trigger = 19U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart5Trigger = 20U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart5Trigger = 21U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart5Trigger = 22U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart5Trigger = 23U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart5Trigger = 24U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart5Trigger = 25U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart5Trigger = 26U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart5Trigger = 27U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart5Trigger = 28U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart5Trigger = 29U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart5Trigger = 30U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart5Trigger = 31U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart5Trigger = 32U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart5Trigger = 33U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart5Trigger = 34U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart5Trigger = 35U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart5Trigger = 36U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart5Trigger = 37U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart5Trigger = 38U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart5Trigger = 39U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart5Trigger = 40U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart5Trigger = 41U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart5Trigger = 42U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart5Trigger = 43U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart5Trigger = 44U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart5Trigger = 45U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart5Trigger = 46U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart5Trigger = 47U + (LPUART5_TRIG_REG << PMUX_SHIFT), + + /*!< Flexio trigger0 input connections. */ + kINPUTMUX_Aoi0Out0ToFlexioTrigger = 1U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexioTrigger = 2U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexioTrigger = 3U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexioTrigger = 4U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexioTrigger = 5U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexioTrigger = 6U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexioTrigger = 7U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexioTrigger = 8U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexioTrigger = 9U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexioTrigger = 10U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexioTrigger = 11U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexioTrigger = 12U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexioTrigger = 13U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexioTrigger = 14U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexioTrigger = 15U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexioTrigger = 16U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexioTrigger = 17U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexioTrigger = 18U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexioTrigger = 20U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexioTrigger = 21U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexioTrigger = 22U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexioTrigger = 23U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexioTrigger = 24U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexioTrigger = 25U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexioTrigger = 26U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexioTrigger = 27U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexioTrigger = 28U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexioTrigger = 29U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexioTrigger = 30U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexioTrigger = 31U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexioTrigger = 32U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexioTrigger = 33U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexioTrigger = 34U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexioTrigger = 35U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexioTrigger = 36U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexioTrigger = 37U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToFlexioTrigger = 38U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToFlexioTrigger = 39U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToFlexioTrigger = 40U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToFlexioTrigger = 41U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToFlexioTrigger = 42U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToFlexioTrigger = 43U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToFlexioTrigger = 44U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToFlexioTrigger = 45U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToFlexioTrigger = 46U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToFlexioTrigger = 47U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToFlexioTrigger = 48U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToFlexioTrigger = 49U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToFlexioTrigger = 50U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToFlexioTrigger = 51U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToFlexioTrigger = 52U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToFlexioTrigger = 53U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToFlexioTrigger = 54U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToFlexioTrigger = 55U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToFlexioTrigger = 56U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToFlexioTrigger = 57U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToFlexioTrigger = 58U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToFlexioTrigger = 59U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToFlexioTrigger = 60U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexioTrigger = 61U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexioTrigger = 62U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexioTrigger = 63U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexioTrigger = 64U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexioTrigger = 65U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexioTrigger = 66U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexioTrigger = 67U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexioTrigger = 68U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexioTrigger = 69U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexioTrigger = 70U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexioTrigger = 71U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexioTrigger = 72U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexioTrigger = 73U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexioTrigger = 74U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexioTrigger = 75U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexioTrigger = 76U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToFlexioTrigger = 77U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToFlexioTrigger = 78U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToFlexioTrigger = 79U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToFlexioTrigger = 80U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + + /*!< SMARTDMA0 trigger input connections. */ + kINPUTMUX_GpioP0_16ToSmartdma0Trigger = (1U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP0_17ToSmartdma0Trigger = (2U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_8ToSmartdma0Trigger = (3U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_9ToSmartdma0Trigger = (4U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_10ToSmartdma0Trigger = (5U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_11ToSmartdma0Trigger = (6U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_12ToSmartdma0Trigger = (7U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_13ToSmartdma0Trigger = (8U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_0ToSmartdma0Trigger = (9U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_1ToSmartdma0Trigger = (10U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_2ToSmartdma0Trigger = (11U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_3ToSmartdma0Trigger = (12U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_6ToSmartdma0Trigger = (13U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_8ToSmartdma0Trigger = (14U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_9ToSmartdma0Trigger = (15U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_10ToSmartdma0Trigger = (16U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_11ToSmartdma0Trigger = (17U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_12ToSmartdma0Trigger = (18U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrigToSmartdma0Trigger = (19U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrigToSmartdma0Trigger = (20U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrigToSmartdma0Trigger = (21U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrigToSmartdma0Trigger = (22U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrigToSmartdma0Trigger = (23U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSmartdma0Trigger = (24U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToSmartdma0Trigger = (25U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToSmartdma0Trigger = (26U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_DmaIrqToSmartdma0Trigger = (27U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_MauIrqToSmartdma0Trigger = (28U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuIrqToSmartdma0Trigger = (29U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToSmartdma0Trigger = (30U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToSmartdma0Trigger = (31U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToSmartdma0Trigger = (32U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToSmartdma0Trigger = (33U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToSmartdma0Trigger = (34U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToSmartdma0Trigger = (35U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToSmartdma0Trigger = (36U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToSmartdma0Trigger = (37U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToSmartdma0Trigger = (38U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToSmartdma0Trigger = (39U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_OstimerIrqToSmartdma0Trigger = (40U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0IrqToSmartdma0Trigger = (41U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1IrqToSmartdma0Trigger = (42U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0IrqToSmartdma0Trigger = (43U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1IrqToSmartdma0Trigger = (44U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_RtcAlarmIrqToSmartdma0Trigger = (45U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Rtc1hzIrqToSmartdma0Trigger = (46U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_UtickIrqToSmartdma0Trigger = (47U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WdtIrqToSmartdma0Trigger = (48U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WakeupTimerIrqToSmartdma0Trigger = (49U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Can0IrqToSmartdma0Trigger = (50U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Can1IrqToSmartdma0Trigger = (51U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioIrqToSmartdma0Trigger = (52U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioShifer0dmareqToSmartdma0Trigger = (53U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioShifer1dmareqToSmartdma0Trigger = (54U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioShifer2dmareqToSmartdma0Trigger = (55U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioShifer3dmareqToSmartdma0Trigger = (56U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_I3c0IrqToSmartdma0Trigger = (57U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c0IrqToSmartdma0Trigger = (58U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c1IrqToSmartdma0Trigger = (59U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi0IrqToSmartdma0Trigger = (60U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi1IrqToSmartdma0Trigger = (61U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0IrqToSmartdma0Trigger = (62U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1IrqToSmartdma0Trigger = (63U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2IrqToSmartdma0Trigger = (64U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3IrqToSmartdma0Trigger = (65U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Usb0SofToSmartdma0Trigger = (66U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToSmartdma0Trigger = (68U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToSmartdma0Trigger = (69U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc2IrqToSmartdma0Trigger = (70U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc3IrqToSmartdma0Trigger = (71U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0IrqToSmartdma0Trigger = (72U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1IrqToSmartdma0Trigger = (73U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2IrqToSmartdma0Trigger = (74U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToSmartdma0Trigger = (75U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToSmartdma0Trigger = (76U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToSmartdma0Trigger = (77U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Dac0IrqToSmartdma0Trigger = (78U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_SlcdIrqToSmartdma0Trigger = (79U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), +} inputmux_connection_t; + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_reset.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_reset.c new file mode 100644 index 000000000..23823aa33 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_reset.c @@ -0,0 +1,152 @@ +/* + * Copyright 2025, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#define GET_REG_INDEX(x) ((uint32_t)(((uint32_t)(x) & 0xFF00U) >> 8)) +#define GET_BIT_INDEX(x) ((uint32_t)((uint32_t)(x) & 0x00FFU)) + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + uint32_t regIndex = GET_REG_INDEX(peripheral); + uint32_t bitPos = GET_BIT_INDEX(peripheral); + uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + + if (peripheral == NotAvail_RSTn) + { + return; + } + + assert(bitPos < 32u); + assert(regIndex < 3u); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + /* reset register is in MRCC */ + /* set bit */ + if (regIndex == 0U) + { + MRCC0->MRCC_GLB_RST0_SET = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + } + else if (regIndex == 1U) + { + MRCC0->MRCC_GLB_RST1_SET = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST1); + } + else if (regIndex == 2U) + { + MRCC0->MRCC_GLB_RST2_SET = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST2); + } + else + { + /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */ + } + /* wait until it reads 0b1 */ + while (0u == ((*pResetCtrl) & bitMask)) + { + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + uint32_t regIndex = GET_REG_INDEX(peripheral); + uint32_t bitPos = GET_BIT_INDEX(peripheral); + uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + + assert(bitPos < 32u); + assert(regIndex < 3u); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + /* reset register is in MRCC */ + /* clear bit */ + if (regIndex == 0U) + { + MRCC0->MRCC_GLB_RST0_CLR = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + } + else if (regIndex == 1U) + { + MRCC0->MRCC_GLB_RST1_CLR = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST1); + } + else if (regIndex == 2U) + { + MRCC0->MRCC_GLB_RST2_CLR = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST2); + } + else + { + /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */ + } + /* wait until it reads 0b0 */ + while (bitMask == ((*pResetCtrl) & bitMask)) + { + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_ClearPeripheralReset(peripheral); + RESET_SetPeripheralReset(peripheral); +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_reset.h new file mode 100644 index 000000000..39fbbe7ad --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_reset.h @@ -0,0 +1,313 @@ +/* + * Copyright 2025, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.4.0 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kINPUTMUX0_RST_SHIFT_RSTn = ((0U << 8U) | 0U), /*!< INPUTMUX0 reset control */ + kI3C0_RST_SHIFT_RSTn = ((0U << 8U) | 1U), /*!< I3C0 reset control */ + kCTIMER0_RST_SHIFT_RSTn = ((0U << 8U) | 2U), /*!< CTIMER0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = ((0U << 8U) | 3U), /*!< CTIMER1 reset control */ + kCTIMER2_RST_SHIFT_RSTn = ((0U << 8U) | 4U), /*!< CTIMER2 reset control */ + kCTIMER3_RST_SHIFT_RSTn = ((0U << 8U) | 5U), /*!< CTIMER3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = ((0U << 8U) | 6U), /*!< CTIMER4 reset control */ + kFREQME_RST_SHIFT_RSTn = ((0U << 8U) | 7U), /*!< FREQME reset control */ + kUTICK0_RST_SHIFT_RSTn = ((0U << 8U) | 8U), /*!< UTICK0 reset control */ + kSMART_DMA_RST_SHIFT_RSTn = ((0U << 8U) | 10U), /*!< SMARTDMA0 reset control */ + kDMA0_RST_SHIFT_RSTn = ((0U << 8U) | 11U), /*!< DMA0 reset control */ + kAOI0_RST_SHIFT_RSTn = ((0U << 8U) | 12U), /*!< AOI0 reset control */ + kCRC0_RST_SHIFT_RSTn = ((0U << 8U) | 13U), /*!< CRC0 reset control */ + kEIM0_RST_SHIFT_RSTn = ((0U << 8U) | 14U), /*!< EIM0 reset control */ + kERM0_RST_SHIFT_RSTn = ((0U << 8U) | 15U), /*!< ERM0 reset control */ + kAOI1_RST_SHIFT_RSTn = ((0U << 8U) | 17U), /*!< AOI1 reset control */ + kFLEXIO0_RST_SHIFT_RSTn = ((0U << 8U) | 18U), /*!< FLEXIO0 reset control */ + kLPI2C0_RST_SHIFT_RSTn = ((0U << 8U) | 19U), /*!< LPI2C0 reset control */ + kLPI2C1_RST_SHIFT_RSTn = ((0U << 8U) | 20U), /*!< LPI2C1 reset control */ + kLPSPI0_RST_SHIFT_RSTn = ((0U << 8U) | 21U), /*!< LPSPI0 reset control */ + kLPSPI1_RST_SHIFT_RSTn = ((0U << 8U) | 22U), /*!< LPSPI1 reset control */ + kLPUART0_RST_SHIFT_RSTn = ((0U << 8U) | 23U), /*!< LPUART0 reset control */ + kLPUART1_RST_SHIFT_RSTn = ((0U << 8U) | 24U), /*!< LPUART1 reset control */ + kLPUART2_RST_SHIFT_RSTn = ((0U << 8U) | 25U), /*!< LPUART2 reset control */ + kLPUART3_RST_SHIFT_RSTn = ((0U << 8U) | 26U), /*!< LPUART3 reset control */ + kLPUART4_RST_SHIFT_RSTn = ((0U << 8U) | 27U), /*!< LPUART4 reset control */ + kUSB0_RST_SHIFT_RSTn = ((0U << 8U) | 28U), /*!< USB0 reset control */ + kQDC0_RST_SHIFT_RSTn = ((0U << 8U) | 29U), /*!< QDC0 reset control */ + kQDC1_RST_SHIFT_RSTn = ((0U << 8U) | 30U), /*!< QDC1 reset control */ + kFLEXPWM0_RST_SHIFT_RSTn = ((0U << 8U) | 31U), /*!< FLEXPWM0 reset control */ + kFLEXPWM1_RST_SHIFT_RSTn = ((1U << 8U) | 0U), /*!< FLEXPWM1 reset control */ + kOSTIMER0_RST_SHIFT_RSTn = ((1U << 8U) | 1U), /*!< OSTIMER0 reset control */ + kADC0_RST_SHIFT_RSTn = ((1U << 8U) | 2U), /*!< ADC0 reset control */ + kADC1_RST_SHIFT_RSTn = ((1U << 8U) | 3U), /*!< ADC1 reset control */ + kCMP1_RST_SHIFT_RSTn = ((1U << 8U) | 5U), /*!< CMP1 reset control */ + kCMP2_RST_SHIFT_RSTn = ((1U << 8U) | 6U), /*!< CMP2 reset control */ + kDAC0_RST_SHIFT_RSTn = ((1U << 8U) | 7U), /*!< DAC0 reset control */ + kOPAMP0_RST_SHIFT_RSTn = ((1U << 8U) | 8U), /*!< OPAMP0 reset control */ + kOPAMP1_RST_SHIFT_RSTn = ((1U << 8U) | 9U), /*!< OPAMP1 reset control */ + kOPAMP2_RST_SHIFT_RSTn = ((1U << 8U) | 10U), /*!< OPAMP2 reset control */ + kOPAMP3_RST_SHIFT_RSTn = ((1U << 8U) | 11U), /*!< OPAMP3 reset control */ + kPORT0_RST_SHIFT_RSTn = ((1U << 8U) | 12U), /*!< PORT0 reset control */ + kPORT1_RST_SHIFT_RSTn = ((1U << 8U) | 13U), /*!< PORT1 reset control */ + kPORT2_RST_SHIFT_RSTn = ((1U << 8U) | 14U), /*!< PORT2 reset control */ + kPORT3_RST_SHIFT_RSTn = ((1U << 8U) | 15U), /*!< PORT3 reset control */ + kPORT4_RST_SHIFT_RSTn = ((1U << 8U) | 16U), /*!< PORT4 reset control */ + kSLCD0_RST_SHIFT_RSTn = ((1U << 8U) | 17U), /*!< SLCD0 reset control */ + kFLEXCAN0_RST_SHIFT_RSTn = ((1U << 8U) | 18U), /*!< FLEXCAN0 reset control */ + kFLEXCAN1_RST_SHIFT_RSTn = ((1U << 8U) | 19U), /*!< FLEXCAN1 reset control */ + kLPI2C2_RST_SHIFT_RSTn = ((1U << 8U) | 20U), /*!< LPI2C2 reset control */ + kLPI2C3_RST_SHIFT_RSTn = ((1U << 8U) | 21U), /*!< LPI2C3 reset control */ + kLPUART5_RST_SHIFT_RSTn = ((1U << 8U) | 22U), /*!< LPUART5 reset control */ + kPKC0_RST_SHIFT_RSTn = ((1U << 8U) | 24U), /*!< PKC0 reset control */ + kTRNG0_RST_SHIFT_RSTn = ((1U << 8U) | 26U), /*!< TRNG0 reset control */ + kADC2_RST_SHIFT_RSTn = ((1U << 8U) | 28U), /*!< ADC2 reset control */ + kADC3_RST_SHIFT_RSTn = ((1U << 8U) | 29U), /*!< ADC3 reset control */ + kGPIO0_RST_SHIFT_RSTn = ((2U << 8U) | 4U), /*!< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = ((2U << 8U) | 5U), /*!< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = ((2U << 8U) | 6U), /*!< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = ((2U << 8U) | 7U), /*!< GPIO3 reset control */ + kGPIO4_RST_SHIFT_RSTn = ((2U << 8U) | 8U), /*!< GPIO4 reset control */ + kMAU0_RST_SHIFT_RSTn = ((2U << 8U) | 9U), /*!< MAU0 reset control */ + NotAvail_RSTn = (0xFFFFU), /*!< No reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +/*! @brief Reset bits for AOI peripheral */ +#define AOI_RSTS \ + { \ + kAOI0_RST_SHIFT_RSTn, kAOI1_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for ADC peripheral */ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn, kADC2_RST_SHIFT_RSTn, kADC3_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for CRC peripheral */ +#define CRC_RSTS \ + { \ + kCRC0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for CTIMER peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for DAC peripheral */ +#define DAC_RSTS_N \ + { \ + kDAC0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for DMA peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for EIM peripheral */ +#define EIM_RSTS_N \ + { \ + kEIM0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for ERM peripheral */ +#define ERM_RSTS_N \ + { \ + kERM0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for EQDC peripheral */ +#define EQDC_RSTS \ + { \ + kQDC0_RST_SHIFT_RSTn, kQDC1_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for FLEXCAN peripheral */ +#define FLEXCAN_RSTS_N \ + { \ + kFLEXCAN0_RST_SHIFT_RSTn, kFLEXCAN1_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for FLEXIO peripheral */ +#define FLEXIO_RSTS_N \ + { \ + kFLEXIO0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for FLEXPWM peripheral */ +#define FLEXPWM_RSTS_N \ + { \ + kFLEXPWM0_RST_SHIFT_RSTn, kFLEXPWM1_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for FREQME peripheral */ +#define FREQME_RSTS_N \ + { \ + kFREQME_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for GPIO peripheral */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for I3C peripheral */ +#define I3C_RSTS \ + { \ + kI3C0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for INPUTMUX peripheral */ +#define INPUTMUX_RSTS \ + { \ + kINPUTMUX0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for LPUART peripheral */ +#define LPUART_RSTS \ + { \ + kLPUART0_RST_SHIFT_RSTn, kLPUART1_RST_SHIFT_RSTn, kLPUART2_RST_SHIFT_RSTn, kLPUART3_RST_SHIFT_RSTn, \ + kLPUART4_RST_SHIFT_RSTn, kLPUART5_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for LPSPI peripheral */ +#define LPSPI_RSTS \ + { \ + kLPSPI0_RST_SHIFT_RSTn, kLPSPI1_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for LPI2C peripheral */ +#define LPI2C_RSTS \ + { \ + kLPI2C0_RST_SHIFT_RSTn, kLPI2C1_RST_SHIFT_RSTn, kLPI2C2_RST_SHIFT_RSTn, kLPI2C3_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for LPCMP peripheral */ +#define LPCMP_RSTS \ + { \ + NotAvail_RSTn, kCMP1_RST_SHIFT_RSTn, kCMP2_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for MAU peripheral */ +#define MAU_RSTS \ + { \ + kMAU0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for OPAMP peripheral */ +#define OPAMP_RSTS \ + { \ + kOPAMP0_RST_SHIFT_RSTn, kOPAMP1_RST_SHIFT_RSTn, kOPAMP2_RST_SHIFT_RSTn, kOPAMP3_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for OSTIMER peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for PORT peripheral */ +#define PORT_RSTS_N \ + { \ + kPORT0_RST_SHIFT_RSTn, kPORT1_RST_SHIFT_RSTn, kPORT2_RST_SHIFT_RSTn, kPORT3_RST_SHIFT_RSTn, \ + kPORT4_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for PKC peripheral */ +#define PKC_RSTS \ + { \ + kPKC0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for SLCD peripheral */ +#define SLCD_RSTS \ + { \ + kSLCD0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for SMARTDMA peripheral */ +#define SMARTDMA_RSTS \ + { \ + kSMART_DMA_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for TRNG peripheral */ +#define TRNG_RSTS \ + { \ + kTRNG0_RST_SHIFT_RSTn \ + } +/*! @brief Reset bits for UTICK peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK0_RST_SHIFT_RSTn \ + } + +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Release peripheral module. + * + * Release peripheral module. + * + * @param peripheral Peripheral to release. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_trdc_soc.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_trdc_soc.h new file mode 100644 index 000000000..a9a826088 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/drivers/fsl_trdc_soc.h @@ -0,0 +1,60 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_TRDC_SOC_H_ +#define _FSL_TRDC_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup trdc_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.trdc_soc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.0. */ +#define FSL_TRDC_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK 0x000003FFUL +#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK 0x001F0000UL +#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT 16U +#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(x) & 0xFUL) << 8U) +#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x) (((uint32_t)(x) & 0x1UL) << 16U) + +/*!@brief TRDC feature */ +#define FSL_FEATURE_TRDC_DOMAIN_COUNT 1 + +/*!@brief TRDC base address convert macro */ +#define TRDC_MBC_COUNT 1 +#define TRDC_MBC_OFFSET(x) 0x0000 /* MBC register offset in TRDC_Type structure. */ +#define TRDC_MBC_ARRAY_STEP 0U /* Offset between two MBC control block, useless if there is only one. */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_TRDC_SOC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/startup_MCXA266.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/startup_MCXA266.c index bda5fe33e..cda519231 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/startup_MCXA266.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/startup_MCXA266.c @@ -1,7 +1,7 @@ //***************************************************************************** // MCXA266 startup code // -// Version : 290725 +// Version : 300725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/startup_MCXA266.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/startup_MCXA266.cpp index bda5fe33e..cda519231 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/startup_MCXA266.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/startup_MCXA266.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MCXA266 startup code // -// Version : 290725 +// Version : 300725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/system_MCXA266.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/system_MCXA266.c index ef7934446..6a60689a6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/system_MCXA266.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/system_MCXA266.c @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/system_MCXA266.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/system_MCXA266.h index 7abe44453..3a1eee51a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/system_MCXA266.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/system_MCXA266.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/variable.cmake index 83a92f4c1..2957b8db6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA266/variable.cmake @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -8,7 +8,7 @@ include(${SdkRootDirPath}/devices/MCX/variable.cmake) mcux_set_variable(device MCXA266) mcux_set_variable(device_root devices) mcux_set_variable(soc_series MCXA) -mcux_set_variable(soc_periph periph2) +mcux_set_variable(soc_periph periph5) mcux_set_variable(core_id_suffix_name "") mcux_set_variable(multicore_foldername .) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/CMakeLists.txt new file mode 100644 index 000000000..086d5f991 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA344/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343.h new file mode 100644 index 000000000..53641b659 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343.h @@ -0,0 +1,92 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1_DraftC +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA343 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXA343.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXA343 + * + * CMSIS Peripheral Access Layer for MCXA343 + */ + +#if !defined(MCXA343_H_) /* Check if memory map has not been already included */ +#define MCXA343_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LPCMP.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MAU.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA343_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_COMMON.h new file mode 100644 index 000000000..fba2dc3ef --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_COMMON.h @@ -0,0 +1,849 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1_DraftC +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA343 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXA343_COMMON.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXA343 + * + * CMSIS Peripheral Access Layer for MCXA343 + */ + +#if !defined(MCXA343_COMMON_H_) +#define MCXA343_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + Reserved33_IRQn = 17, /**< Reserved interrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + Reserved36_IRQn = 20, /**< Reserved interrupt */ + Reserved37_IRQn = 21, /**< Reserved interrupt */ + Reserved38_IRQn = 22, /**< Reserved interrupt */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + Reserved40_IRQn = 24, /**< Reserved interrupt */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + Reserved51_IRQn = 35, /**< Reserved interrupt */ + Reserved52_IRQn = 36, /**< Reserved interrupt */ + Reserved53_IRQn = 37, /**< Reserved interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + Reserved58_IRQn = 42, /**< Reserved interrupt */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + Reserved72_IRQn = 56, /**< Reserved interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + CMP2_IRQn = 66, /**< Comparator 2 interrupt */ + Reserved83_IRQn = 67, /**< Reserved interrupt */ + Reserved84_IRQn = 68, /**< Reserved interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + Reserved92_IRQn = 76, /**< Reserved interrupt */ + Reserved93_IRQn = 77, /**< Reserved interrupt */ + Reserved94_IRQn = 78, /**< Reserved interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + Reserved105_IRQn = 89, /**< Reserved interrupt */ + Reserved106_IRQn = 90, /**< Reserved interrupt */ + Reserved107_IRQn = 91, /**< Reserved interrupt */ + Reserved108_IRQn = 92, /**< Reserved interrupt */ + Reserved109_IRQn = 93, /**< Reserved interrupt */ + Reserved110_IRQn = 94, /**< Reserved interrupt */ + Reserved111_IRQn = 95, /**< Reserved interrupt */ + Reserved112_IRQn = 96, /**< Reserved interrupt */ + Reserved113_IRQn = 97, /**< Reserved interrupt */ + Reserved114_IRQn = 98, /**< Reserved interrupt */ + Reserved115_IRQn = 99, /**< Reserved interrupt */ + Reserved116_IRQn = 100, /**< Reserved interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + Reserved121_IRQn = 105, /**< Reserved interrupt */ + Reserved122_IRQn = 106, /**< Reserved interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + Reserved125_IRQn = 109, /**< Reserved interrupt */ + Reserved126_IRQn = 110, /**< Reserved interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + Reserved128_IRQn = 112, /**< Reserved interrupt */ + Reserved129_IRQn = 113, /**< Reserved interrupt */ + Reserved130_IRQn = 114, /**< Reserved interrupt */ + Reserved131_IRQn = 115, /**< Reserved interrupt */ + Reserved132_IRQn = 116, /**< Reserved interrupt */ + Reserved133_IRQn = 117, /**< Reserved interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + Reserved137_IRQn = 121 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA343.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA343_SERIES +#define MCXA343_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA343_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x400B3000u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((LPCMP_Type *)CMP2_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn } + +/* MAU - Peripheral instance base addresses */ +/** Peripheral MAU0 base address */ +#define MAU0_BASE (0x40108000u) +/** Peripheral MAU0 base pointer */ +#define MAU0 ((MAU_Type *)MAU0_BASE) +/** Array initializer of MAU peripheral base addresses */ +#define MAU_BASE_ADDRS { MAU0_BASE } +/** Array initializer of MAU peripheral base pointers */ +#define MAU_BASE_PTRS { MAU0 } +/** Interrupt vectors for the MAU peripheral type */ +#define MAU_IRQS { MAU_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Peripheral OPAMP1 base address */ +#define OPAMP1_BASE (0x400B8000u) +/** Peripheral OPAMP1 base pointer */ +#define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) +/** Peripheral OPAMP2 base address */ +#define OPAMP2_BASE (0x400B9000u) +/** Peripheral OPAMP2 base pointer */ +#define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA343_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_features.h new file mode 100644 index 000000000..f6ece5588 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/MCXA343_features.h @@ -0,0 +1,898 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA343_FEATURES_H_ +#define _MCXA343_FEATURES_H_ + +/* SOC module features */ + +#if defined(CPU_MCXA343VFM) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (2) + /* @brief CDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_CDOG_COUNT (1) + /* @brief CMC availability on the SoC. */ + #define FSL_FEATURE_SOC_CMC_COUNT (1) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief CTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_CTIMER_COUNT (3) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief EIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EIM_COUNT (1) + /* @brief EQDC availability on the SoC. */ + #define FSL_FEATURE_SOC_EQDC_COUNT (2) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FREQME availability on the SoC. */ + #define FSL_FEATURE_SOC_FREQME_COUNT (1) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief SPC availability on the SoC. */ + #define FSL_FEATURE_SOC_SPC_COUNT (1) + /* @brief INPUTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) + /* @brief LPADC availability on the SoC. */ + #define FSL_FEATURE_SOC_LPADC_COUNT (2) + /* @brief LPCMP availability on the SoC. */ + #define FSL_FEATURE_SOC_LPCMP_COUNT (3) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (2) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (2) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (4) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (1) + /* @brief OSTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (2) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (1) + /* @brief SMARTDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) + /* @brief SYSCON availability on the SoC. */ + #define FSL_FEATURE_SOC_SYSCON_COUNT (1) + /* @brief UTICK availability on the SoC. */ + #define FSL_FEATURE_SOC_UTICK_COUNT (1) + /* @brief WAKETIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) + /* @brief WWDT availability on the SoC. */ + #define FSL_FEATURE_SOC_WWDT_COUNT (1) + /* @brief WUU availability on the SoC. */ + #define FSL_FEATURE_SOC_WUU_COUNT (1) +#elif defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (2) + /* @brief CDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_CDOG_COUNT (1) + /* @brief CMC availability on the SoC. */ + #define FSL_FEATURE_SOC_CMC_COUNT (1) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief CTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_CTIMER_COUNT (3) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief EIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EIM_COUNT (1) + /* @brief EQDC availability on the SoC. */ + #define FSL_FEATURE_SOC_EQDC_COUNT (2) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FREQME availability on the SoC. */ + #define FSL_FEATURE_SOC_FREQME_COUNT (1) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief SPC availability on the SoC. */ + #define FSL_FEATURE_SOC_SPC_COUNT (1) + /* @brief INPUTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) + /* @brief LPADC availability on the SoC. */ + #define FSL_FEATURE_SOC_LPADC_COUNT (2) + /* @brief LPCMP availability on the SoC. */ + #define FSL_FEATURE_SOC_LPCMP_COUNT (3) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (2) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (2) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (4) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (3) + /* @brief OSTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (2) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (1) + /* @brief SMARTDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) + /* @brief SYSCON availability on the SoC. */ + #define FSL_FEATURE_SOC_SYSCON_COUNT (1) + /* @brief UTICK availability on the SoC. */ + #define FSL_FEATURE_SOC_UTICK_COUNT (1) + /* @brief WAKETIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) + /* @brief WWDT availability on the SoC. */ + #define FSL_FEATURE_SOC_WWDT_COUNT (1) + /* @brief WUU availability on the SoC. */ + #define FSL_FEATURE_SOC_WUU_COUNT (1) +#endif + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MAU module features */ + +/* @brief Indirect operation is in low address. */ +#define FSL_FEATURE_MAU_INDIRECT_IS_LOW_ADDR (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (0) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (122880) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA343_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/fsl_device_registers.h new file mode 100644 index 000000000..696bf9656 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.c new file mode 100644 index 000000000..ea271db1a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.c @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA343 startup code +// +// Version : 060825 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void Reserved33_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void Reserved40_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void Reserved51_IRQHandler(void); +WEAK void Reserved52_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void Reserved58_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void Reserved83_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void Reserved93_IRQHandler(void); +WEAK void Reserved94_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void Reserved125_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved51_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved83_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved93_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved94_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA343 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + Reserved33_IRQHandler, // 33 : Reserved interrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + Reserved39_IRQHandler, // 39 : Reserved interrupt + Reserved40_IRQHandler, // 40 : Reserved interrupt + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + Reserved51_IRQHandler, // 51 : Reserved interrupt + Reserved52_IRQHandler, // 52 : Reserved interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + Reserved58_IRQHandler, // 58 : Reserved interrupt + Reserved59_IRQHandler, // 59 : Reserved interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + Reserved83_IRQHandler, // 83 : Reserved interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + Reserved93_IRQHandler, // 93 : Reserved interrupt + Reserved94_IRQHandler, // 94 : Reserved interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + Reserved125_IRQHandler, // 125: Reserved interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void Reserved33_IRQHandler(void) +{ + Reserved33_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ + Reserved39_DriverIRQHandler(); +} + +WEAK void Reserved40_IRQHandler(void) +{ + Reserved40_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void Reserved51_IRQHandler(void) +{ + Reserved51_DriverIRQHandler(); +} + +WEAK void Reserved52_IRQHandler(void) +{ + Reserved52_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void Reserved58_IRQHandler(void) +{ + Reserved58_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ + Reserved59_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void Reserved83_IRQHandler(void) +{ + Reserved83_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void Reserved93_IRQHandler(void) +{ + Reserved93_DriverIRQHandler(); +} + +WEAK void Reserved94_IRQHandler(void) +{ + Reserved94_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void Reserved125_IRQHandler(void) +{ + Reserved125_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.cpp new file mode 100644 index 000000000..ea271db1a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/startup_MCXA343.cpp @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA343 startup code +// +// Version : 060825 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void Reserved33_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void Reserved40_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void Reserved51_IRQHandler(void); +WEAK void Reserved52_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void Reserved58_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void Reserved83_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void Reserved93_IRQHandler(void); +WEAK void Reserved94_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void Reserved125_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved51_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved83_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved93_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved94_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA343 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + Reserved33_IRQHandler, // 33 : Reserved interrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + Reserved39_IRQHandler, // 39 : Reserved interrupt + Reserved40_IRQHandler, // 40 : Reserved interrupt + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + Reserved51_IRQHandler, // 51 : Reserved interrupt + Reserved52_IRQHandler, // 52 : Reserved interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + Reserved58_IRQHandler, // 58 : Reserved interrupt + Reserved59_IRQHandler, // 59 : Reserved interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + Reserved83_IRQHandler, // 83 : Reserved interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + Reserved93_IRQHandler, // 93 : Reserved interrupt + Reserved94_IRQHandler, // 94 : Reserved interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + Reserved125_IRQHandler, // 125: Reserved interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void Reserved33_IRQHandler(void) +{ + Reserved33_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ + Reserved39_DriverIRQHandler(); +} + +WEAK void Reserved40_IRQHandler(void) +{ + Reserved40_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void Reserved51_IRQHandler(void) +{ + Reserved51_DriverIRQHandler(); +} + +WEAK void Reserved52_IRQHandler(void) +{ + Reserved52_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void Reserved58_IRQHandler(void) +{ + Reserved58_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ + Reserved59_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void Reserved83_IRQHandler(void) +{ + Reserved83_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void Reserved93_IRQHandler(void) +{ + Reserved93_DriverIRQHandler(); +} + +WEAK void Reserved94_IRQHandler(void) +{ + Reserved94_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void Reserved125_IRQHandler(void) +{ + Reserved125_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.c new file mode 100644 index 000000000..7f9a2612b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.c @@ -0,0 +1,115 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1_DraftC +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXA343 + * @version 2.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXA343 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.h new file mode 100644 index 000000000..d67b6167d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/system_MCXA343.h @@ -0,0 +1,116 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1_DraftC +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXA343 + * @version 2.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXA343 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA343_H_ +#define _SYSTEM_MCXA343_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA343_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/variable.cmake new file mode 100644 index 000000000..92559a402 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA343/variable.cmake @@ -0,0 +1,14 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA343) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph3) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/CMakeLists.txt new file mode 100644 index 000000000..086d5f991 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA344/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344.h new file mode 100644 index 000000000..f17f4589a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344.h @@ -0,0 +1,92 @@ +/* +** ################################################################### +** Processors: MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1_DraftC +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA344 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXA344.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXA344 + * + * CMSIS Peripheral Access Layer for MCXA344 + */ + +#if !defined(MCXA344_H_) /* Check if memory map has not been already included */ +#define MCXA344_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LPCMP.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MAU.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA344_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_COMMON.h new file mode 100644 index 000000000..6d81a9e20 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_COMMON.h @@ -0,0 +1,849 @@ +/* +** ################################################################### +** Processors: MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1_DraftC +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA344 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXA344_COMMON.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXA344 + * + * CMSIS Peripheral Access Layer for MCXA344 + */ + +#if !defined(MCXA344_COMMON_H_) +#define MCXA344_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + Reserved33_IRQn = 17, /**< Reserved interrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + Reserved36_IRQn = 20, /**< Reserved interrupt */ + Reserved37_IRQn = 21, /**< Reserved interrupt */ + Reserved38_IRQn = 22, /**< Reserved interrupt */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + Reserved40_IRQn = 24, /**< Reserved interrupt */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + Reserved51_IRQn = 35, /**< Reserved interrupt */ + Reserved52_IRQn = 36, /**< Reserved interrupt */ + Reserved53_IRQn = 37, /**< Reserved interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + Reserved58_IRQn = 42, /**< Reserved interrupt */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + Reserved72_IRQn = 56, /**< Reserved interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + CMP2_IRQn = 66, /**< Comparator 2 interrupt */ + Reserved83_IRQn = 67, /**< Reserved interrupt */ + Reserved84_IRQn = 68, /**< Reserved interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + Reserved92_IRQn = 76, /**< Reserved interrupt */ + Reserved93_IRQn = 77, /**< Reserved interrupt */ + Reserved94_IRQn = 78, /**< Reserved interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + Reserved105_IRQn = 89, /**< Reserved interrupt */ + Reserved106_IRQn = 90, /**< Reserved interrupt */ + Reserved107_IRQn = 91, /**< Reserved interrupt */ + Reserved108_IRQn = 92, /**< Reserved interrupt */ + Reserved109_IRQn = 93, /**< Reserved interrupt */ + Reserved110_IRQn = 94, /**< Reserved interrupt */ + Reserved111_IRQn = 95, /**< Reserved interrupt */ + Reserved112_IRQn = 96, /**< Reserved interrupt */ + Reserved113_IRQn = 97, /**< Reserved interrupt */ + Reserved114_IRQn = 98, /**< Reserved interrupt */ + Reserved115_IRQn = 99, /**< Reserved interrupt */ + Reserved116_IRQn = 100, /**< Reserved interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + Reserved121_IRQn = 105, /**< Reserved interrupt */ + Reserved122_IRQn = 106, /**< Reserved interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + Reserved125_IRQn = 109, /**< Reserved interrupt */ + Reserved126_IRQn = 110, /**< Reserved interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + Reserved128_IRQn = 112, /**< Reserved interrupt */ + Reserved129_IRQn = 113, /**< Reserved interrupt */ + Reserved130_IRQn = 114, /**< Reserved interrupt */ + Reserved131_IRQn = 115, /**< Reserved interrupt */ + Reserved132_IRQn = 116, /**< Reserved interrupt */ + Reserved133_IRQn = 117, /**< Reserved interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + Reserved137_IRQn = 121 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA344.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA344_SERIES +#define MCXA344_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA344_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x400B3000u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((LPCMP_Type *)CMP2_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn } + +/* MAU - Peripheral instance base addresses */ +/** Peripheral MAU0 base address */ +#define MAU0_BASE (0x40108000u) +/** Peripheral MAU0 base pointer */ +#define MAU0 ((MAU_Type *)MAU0_BASE) +/** Array initializer of MAU peripheral base addresses */ +#define MAU_BASE_ADDRS { MAU0_BASE } +/** Array initializer of MAU peripheral base pointers */ +#define MAU_BASE_PTRS { MAU0 } +/** Interrupt vectors for the MAU peripheral type */ +#define MAU_IRQS { MAU_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Peripheral OPAMP1 base address */ +#define OPAMP1_BASE (0x400B8000u) +/** Peripheral OPAMP1 base pointer */ +#define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) +/** Peripheral OPAMP2 base address */ +#define OPAMP2_BASE (0x400B9000u) +/** Peripheral OPAMP2 base pointer */ +#define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA344_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_features.h new file mode 100644 index 000000000..224dbf782 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/MCXA344_features.h @@ -0,0 +1,898 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA344_FEATURES_H_ +#define _MCXA344_FEATURES_H_ + +/* SOC module features */ + +#if defined(CPU_MCXA344VFM) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (2) + /* @brief CDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_CDOG_COUNT (1) + /* @brief CMC availability on the SoC. */ + #define FSL_FEATURE_SOC_CMC_COUNT (1) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief CTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_CTIMER_COUNT (3) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief EIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EIM_COUNT (1) + /* @brief EQDC availability on the SoC. */ + #define FSL_FEATURE_SOC_EQDC_COUNT (2) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FREQME availability on the SoC. */ + #define FSL_FEATURE_SOC_FREQME_COUNT (1) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief SPC availability on the SoC. */ + #define FSL_FEATURE_SOC_SPC_COUNT (1) + /* @brief INPUTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) + /* @brief LPADC availability on the SoC. */ + #define FSL_FEATURE_SOC_LPADC_COUNT (2) + /* @brief LPCMP availability on the SoC. */ + #define FSL_FEATURE_SOC_LPCMP_COUNT (3) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (2) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (2) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (4) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (1) + /* @brief OSTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (2) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (1) + /* @brief SMARTDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) + /* @brief SYSCON availability on the SoC. */ + #define FSL_FEATURE_SOC_SYSCON_COUNT (1) + /* @brief UTICK availability on the SoC. */ + #define FSL_FEATURE_SOC_UTICK_COUNT (1) + /* @brief WAKETIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) + /* @brief WWDT availability on the SoC. */ + #define FSL_FEATURE_SOC_WWDT_COUNT (1) + /* @brief WUU availability on the SoC. */ + #define FSL_FEATURE_SOC_WUU_COUNT (1) +#elif defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (2) + /* @brief CDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_CDOG_COUNT (1) + /* @brief CMC availability on the SoC. */ + #define FSL_FEATURE_SOC_CMC_COUNT (1) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief CTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_CTIMER_COUNT (3) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief EIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EIM_COUNT (1) + /* @brief EQDC availability on the SoC. */ + #define FSL_FEATURE_SOC_EQDC_COUNT (2) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FREQME availability on the SoC. */ + #define FSL_FEATURE_SOC_FREQME_COUNT (1) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief SPC availability on the SoC. */ + #define FSL_FEATURE_SOC_SPC_COUNT (1) + /* @brief INPUTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) + /* @brief LPADC availability on the SoC. */ + #define FSL_FEATURE_SOC_LPADC_COUNT (2) + /* @brief LPCMP availability on the SoC. */ + #define FSL_FEATURE_SOC_LPCMP_COUNT (3) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (2) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (2) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (4) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (3) + /* @brief OSTIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (2) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (1) + /* @brief SMARTDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) + /* @brief SYSCON availability on the SoC. */ + #define FSL_FEATURE_SOC_SYSCON_COUNT (1) + /* @brief UTICK availability on the SoC. */ + #define FSL_FEATURE_SOC_UTICK_COUNT (1) + /* @brief WAKETIMER availability on the SoC. */ + #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) + /* @brief WWDT availability on the SoC. */ + #define FSL_FEATURE_SOC_WWDT_COUNT (1) + /* @brief WUU availability on the SoC. */ + #define FSL_FEATURE_SOC_WUU_COUNT (1) +#endif + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MAU module features */ + +/* @brief Indirect operation is in low address. */ +#define FSL_FEATURE_MAU_INDIRECT_IS_LOW_ADDR (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (0) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (253952) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA344_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/CMakeLists.txt new file mode 100644 index 000000000..bca941a9d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/CMakeLists.txt @@ -0,0 +1,35 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +mcux_add_cmakelists(${SdkRootDirPath}/devices/MCX/MCXA/MCXA153/drivers/romapi) + +if (CONFIG_MCUX_COMPONENT_driver.clock) + mcux_component_version(2.0.0) + mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) + mcux_add_include( INCLUDES . ) +endif() + +if (CONFIG_MCUX_COMPONENT_driver.edma_soc) + mcux_component_version(2.0.0) + mcux_add_source( SOURCES fsl_edma_soc.c fsl_edma_soc.h ) + mcux_add_include( INCLUDES . ) +endif() + +if (CONFIG_MCUX_COMPONENT_driver.inputmux_connections) + mcux_component_version(2.0.0) + mcux_add_source( SOURCES fsl_inputmux_connections.h ) + mcux_add_include( INCLUDES . ) +endif() + +if (CONFIG_MCUX_COMPONENT_driver.reset) + mcux_component_version(2.4.0) + mcux_add_source( SOURCES fsl_reset.c fsl_reset.h ) + mcux_add_include( INCLUDES . ) +endif() + +if (CONFIG_MCUX_COMPONENT_driver.trdc_soc) + mcux_component_version(2.0.0) + mcux_add_source( SOURCES fsl_trdc_soc.h ) + mcux_add_include( INCLUDES . ) +endif() diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/ChangeLogKSDK.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/ChangeLogKSDK.txt new file mode 100644 index 000000000..74aa93d45 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/ChangeLogKSDK.txt @@ -0,0 +1,15 @@ +/*! +@page driver_log Driver Change Log +@section clock CLOCK + The current CLOCK driver version is 2.0.0. + + - 2.0.0 + - Initial version. + +@section reset RESET + The current RESET driver version is 2.0.0. + + - 2.0.0 + - Initial version. + +*/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.c new file mode 100644 index 000000000..bae45612b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.c @@ -0,0 +1,1285 @@ +/* + * Copyright 2023, NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +volatile static uint32_t s_Ext_Clk_Freq = 16000000U; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Get FRO 12M Clk */ +static uint32_t CLOCK_GetFro12MFreq(void); +/* Get LF FRO_DIV Clk */ +static uint32_t CLOCK_GetFroLfDivFreq(void); +/* Get CLK 1M Clk */ +static uint32_t CLOCK_GetClk1MFreq(void); +/* Get HF FRO Clk */ +static uint32_t CLOCK_GetFroHfFreq(void); +/* Get HF FRO_DIV Clk */ +static uint32_t CLOCK_GetFroHfDivFreq(void); +/* Get CLK 45M Clk */ +static uint32_t CLOCK_GetClk45MFreq(void); +/* Get CLK 16K Clk */ +static uint32_t CLOCK_GetClk16KFreq(uint8_t id); +/* Get EXT OSC Clk */ +static uint32_t CLOCK_GetExtClkFreq(void); +/* Get Main_Clk */ +uint32_t CLOCK_GetMainClk(void); +/* Get FRO_16K */ +static uint32_t CLOCK_GetFRO16KFreq(void); + +/* Check if DIV is halt */ +static inline bool CLOCK_IsDivHalt(uint32_t div_value) +{ + if (0U != (div_value & (1UL << 30U))) + { + return true; + } + else + { + return false; + } +} + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); + const uint32_t clk_sel = CLK_ATTACH_CLK_SEL(connection); + + if (kNONE_to_NONE != connection) + { + CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual + * source value in the register and combine the offset to obtain an actual + * attach id. + * value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection) +{ + const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); + uint32_t actual_sel = 0U; + uint32_t clock_attach_id = 0U; + + if (kNONE_to_NONE == connection) + { + return kNONE_to_NONE; + } + + actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); + clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); + + return (clock_attach_id_t)clock_attach_id; +} + +/* Set the clock selection value */ +void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value) +{ + volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name); + assert(sel_name <= kCLOCK_SelMax); + + if (sel_name == kCLOCK_SelSCGSCS) + { + SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); + while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) + { + } + } + else + { + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + *pClkCtrl = value; + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; + } +} + +/* Get the clock selection value */ +uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name) +{ + volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name); + uint32_t actual_sel = 0U; + assert(sel_name <= kCLOCK_SelMax); + + if (sel_name == kCLOCK_SelSCGSCS) + { + actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); + } + else + { + actual_sel = *pClkCtrl; + } + + return actual_sel; +} + +/* Set the clock divider value */ +void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value) +{ + volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name); + assert(div_name <= kCLOCK_DivMax); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + /* halt and reset clock dividers */ + *pDivCtrl = 0x3UL << 29U; + + if (value == 0U) /*!< halt */ + { + *pDivCtrl |= (1UL << 30U); + } + else + { + *pDivCtrl = (value - 1U); + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/* Get the clock divider value */ +uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name) +{ + volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name); + assert(div_name <= kCLOCK_DivMax); + + if (((*pDivCtrl) & (1UL << 30U)) != 0U) + { + return 0; + } + else + { + return ((*pDivCtrl & 0xFFU) + 1U); + } +} + +/* Halt the clock divider value */ +void CLOCK_HaltClockDiv(clock_div_name_t div_name) +{ + volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name); + assert(div_name <= kCLOCK_DivMax); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + *pDivCtrl |= (1UL << 30U); + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/* Initialize the FROHF to given frequency (45,60,90,180) */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq) +{ + uint8_t freq_select = 0x0U; + switch (iFreq) + { + case 45000000U: + freq_select = 1U; + break; + case 60000000U: + freq_select = 3U; + break; + case 90000000U: + freq_select = 5U; + break; + case 180000000U: + freq_select = 7U; + break; + default: + freq_select = 0xFU; + break; + } + + if (0xFU == freq_select) + { + return kStatus_Fail; + } + + /* Set FIRC frequency */ + SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); + + /* Unlock FIRCCSR */ + SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; + + /* Enable CLK 45 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; + /* Enable FIRC HF clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; + /* Enable FIRC */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; + + /* Lock FIRCCSR */ + SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; + + /* Wait for FIRC clock to be valid. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) + { + } + + return kStatus_Success; +} + +/* Initialize the FRO12M. */ +status_t CLOCK_SetupFRO12MClocking(void) +{ + /* Unlock SIRCCSR */ + SCG0->SIRCCSR &= ~SCG_SIRCCSR_LK_MASK; + + /* Enable FRO12M clock for peripheral use */ + SCG0->SIRCCSR |= SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK; + + /* Lock SIRCCSR */ + SCG0->SIRCCSR |= SCG_SIRCCSR_LK_MASK; + + /* Wait for SIRC clock to be valid. */ + while ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0U) + { + } + + /* Release FROLFDIV */ + SYSCON->FROLFDIV &= ~SYSCON_FROLFDIV_HALT_MASK; + + return kStatus_Success; +} + +/*! + * brief Initialize the FRO16K. + * This function turns on FRO16K. + * return returns success or fail status. + */ +status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask) +{ + /* Enable clk_16k */ + VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; + VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; + + /* Enable clk_16k output clock to corresponding modules according to the + * enable_mask. */ + VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(((uint32_t)clk_16k_enable_mask)); + + return kStatus_Success; +} + +/*! + * brief Initialize the external osc clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 8000000U) && (iFreq < 16000000U)) + { + range = 0U; + } + else if ((iFreq >= 16000000U) && (iFreq < 25000000U)) + { + range = 1U; + } + else if ((iFreq >= 25000000U) && (iFreq < 40000000U)) + { + range = 2U; + } + else if ((iFreq >= 40000000U) && (iFreq <= 50000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source(internal crystal oscillator) and Configure SOSC range */ + SCG0->SOSCCFG = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/*! + * @brief Initialize the external reference clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq) +{ + if (iFreq > 50000000U) + { + return kStatus_InvalidArgument; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (external reference clock)*/ + SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK; + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq = 0U; + + switch (clockName) + { + case kCLOCK_MainClk: /* MAIN_CLK */ + freq = CLOCK_GetMainClk(); + break; + case kCLOCK_CoreSysClk: /* Core/system clock(CPU_CLK) */ + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_SYSTEM_CLK: /* AHB clock */ + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: /* Bus clock */ + freq = (CLOCK_GetCoreSysClkFreq() >> 1); + break; + case kCLOCK_ExtClk: /* External Clock */ + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_FroHf: /* FROHF */ + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_FroHfDiv: /* Divided by FROHF */ + freq = CLOCK_GetFroHfDivFreq(); + break; + case kCLOCK_Clk45M: /* CLK_45M */ + freq = CLOCK_GetClk45MFreq(); + break; + case kCLOCK_Fro12M: /* FRO12M */ + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_Fro12MDiv: /* FRO_LF_DIV */ + freq = CLOCK_GetFro12MFreq() / ((SYSCON->FROLFDIV & 0xfU) + 1U); + break; + case kCLOCK_Clk1M: /* CLK1M */ + freq = CLOCK_GetClk1MFreq(); + break; + case kCLOCK_Fro16K: /* FRO16K */ + freq = CLOCK_GetFRO16KFreq(); + break; + case kCLOCK_Clk16K0: /* CLK16K[0] */ + freq = CLOCK_GetClk16KFreq(0); + break; + case kCLOCK_Clk16K1: /* CLK16K[1] */ + freq = CLOCK_GetClk16KFreq(1); + break; + case kCLOCK_SLOW_CLK: /* SYSTEM_CLK divided by 6 */ + freq = (CLOCK_GetCoreSysClkFreq() / 6); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) != 0U) ? 12000000U : 0U; +} + +/* Get CLK 1M Clk */ +/*! brief Return Frequency of CLK 1MHz + * return Frequency of CLK 1MHz + */ +static uint32_t CLOCK_GetClk1MFreq(void) +{ + return 1000000U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfFreq(void) +{ + uint32_t freq; + + if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || + ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) + { + freq = 0U; + } + + switch ((SCG0->FIRCCFG & SCG_FIRCCFG_FREQ_SEL_MASK) >> SCG_FIRCCFG_FREQ_SEL_SHIFT) + { + case 1U: + freq = 45000000U; + break; + case 3U: + freq = 60000000U; + break; + case 5U: + freq = 90000000U; + break; + case 7U: + freq = 180000000U; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get HF FRO DIV Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfDivFreq(void) +{ + return CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & SYSCON_FROHFDIV_DIV_MASK) + 1U); +} + +/* Get LF FRO DIV Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroLfDivFreq(void) +{ + return CLOCK_GetFro12MFreq() / ((SYSCON->FROLFDIV & SYSCON_FROLFDIV_DIV_MASK) + 1U); +} + +/* Get CLK_45M frequency */ +/*! brief Return Frequency of CLK 45MHz + * return Frequency of CLK 45MHz + */ +static uint32_t CLOCK_GetClk45MFreq(void) +{ + if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) == 0U) + { + return 0U; + } + else + { + return 45000000U; + } +} + +/*! brief Return Frequency of FRO16K + * return Frequency of FRO_16K + */ +static uint32_t CLOCK_GetFRO16KFreq(void) +{ + return ((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) ? 16000U : 0U; +} +/* Get CLK 16K Clk */ +/*! brief Return Frequency of CLK 16KHz + * return Frequency of CLK 16KHz + */ +static uint32_t CLOCK_GetClk16KFreq(uint8_t id) +{ + return (((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) && + ((VBAT0->FROCLKE & VBAT_FROCLKE_CLKE((((uint32_t)id) << 1U))) != 0U)) ? + 16000U : + 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) != 0U) ? s_Ext_Clk_Freq : 0U; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetMainClk(void) +{ + uint32_t freq = 0U; + + switch ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 1U: + freq = CLOCK_GetExtClkFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetClk16KFreq(1); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! brief Return Frequency of core + * return Frequency of the core + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + return CLOCK_GetMainClk() / ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) + 1U); +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_CTIMER0_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_CTIMER1_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER1_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_CTIMER2_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER2_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_CTIMER0_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 4U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/* Get LPI2C Clk */ +/*! brief Return Frequency of LPI2C functional Clock + * return Frequency of LPI2C functional Clock + */ +uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_LPI2C0_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_LPI2C1_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C1_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_LPI2C0_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of LPSPI Clock + * return Frequency of LPSPI Clock + */ +uint32_t CLOCK_GetLpspiClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKSEL) : (MRCC0->MRCC_LPSPI1_CLKSEL); + uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKDIV) : (MRCC0->MRCC_LPSPI1_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of LPUART Clock + * return Frequency of LPUART Clock + */ +uint32_t CLOCK_GetLpuartClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_LPUART0_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART0_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_LPUART1_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART1_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_LPUART2_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART2_CLKDIV; + break; + case 3U: + clksel = MRCC0->MRCC_LPUART3_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART3_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_LPUART0_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART0_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 4U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of LPTMR Clock + * return Frequency of LPTMR Clock + */ +uint32_t CLOCK_GetLptmrClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_LPTMR0_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_LPTMR0_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of OSTIMER + * return Frequency of OSTIMER Clock + */ +uint32_t CLOCK_GetOstimerClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_OSTIMER0_CLKSEL); + + switch (clksel) + { + case 0U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + uint32_t clksel = MRCC0->MRCC_ADC_CLKSEL; + uint32_t clkdiv = MRCC0->MRCC_ADC_CLKDIV; + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of CMP Function Clock + * return Frequency of CMP Function. + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_CMP0_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP0_FUNC_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_CMP1_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP1_FUNC_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_CMP2_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP2_FUNC_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_CMP0_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP0_FUNC_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of CMP Round Robin Clock + * return Frequency of CMP Round Robin. + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_CMP0_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP0_RR_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_CMP1_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP1_RR_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_CMP2_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP2_RR_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_CMP0_RR_CLKSEL; + clkdiv = MRCC0->MRCC_CMP0_RR_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFroLfDivFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of Trace Clock + * return Frequency of Trace. + */ +uint32_t CLOCK_GetTraceClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_DBG_TRACE_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_DBG_TRACE_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetClk1MFreq(); + break; + case 2U: + freq = CLOCK_GetClk16KFreq(1); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of CLKOUT Clock + * return Frequency of CLKOUT. + */ +uint32_t CLOCK_GetClkoutClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_CLKOUT_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_CLKOUT_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 6U: + freq = CLOCK_GetFreq(kCLOCK_SLOW_CLK); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of WWDT Clock + * return Frequency of WWDT. + */ +uint32_t CLOCK_GetWwdtClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clkdiv = (MRCC0->MRCC_WWDT0_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + freq = CLOCK_GetClk1MFreq(); + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of FlexCAN FCLK + * return Frequency of FlexCAN FCLK. + */ +uint32_t CLOCK_GetFlexcanClkFreq(void) +{ + uint32_t freq = 0U; + + uint32_t clksel = MRCC0->MRCC_FLEXCAN0_CLKSEL; + uint32_t clkdiv = MRCC0->MRCC_FLEXCAN0_CLKDIV; + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfDivFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config) +{ + SCG0->SIRCTCFG = SCG_SIRCTCFG_TRIMDIV(config.trimDiv) | SCG_SIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_SircTrimNonUpdate == config.trimMode) + { + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.cltrim); + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.ccotrim); + } + + /* Set trim mode. */ + SCG0->SIRCCSR = + (SCG0->SIRCCSR & ~(SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK)) | (uint32_t)config.trimMode; + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0U) + { + return (status_t)kStatus_Fail; + } + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCERR_MASK) == SCG_SIRCCSR_SIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_TRIM_LOCK_MASK) == 0U) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the + * error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SOSCCSR; + + reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SOSCCSR = reg; +} + +/*! + * @brief Set the additional number of wait-states added to account for the + * ratio of system clock period to flash access time during full speed power + * mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode) +{ + uint32_t num_wait_states_added = 3UL; /* Default 3 additional wait states */ + switch ((uint32_t)mode) + { + case (uint32_t)kMD_Mode: + { + if (system_freq_hz > 45000000U) + { + return kStatus_Fail; + } + else if (system_freq_hz > 22500000U) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case (uint32_t)kOD_Mode: + { + if (system_freq_hz > 180000000U) + { + return kStatus_Fail; + } + else if (system_freq_hz > 90000000U) + { + num_wait_states_added = 4U; + } + else if (system_freq_hz > 60000000U) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000U) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + default: + num_wait_states_added = 0U; + break; + } + + /* additional wait-states are added */ + FMU0->FCTRL = (FMU0->FCTRL & ~FMU_FCTRL_RWSC_MASK) | FMU_FCTRL_RWSC(num_wait_states_added); + + return kStatus_Success; +} \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.h new file mode 100644 index 000000000..a472032e5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_clock.h @@ -0,0 +1,790 @@ +/* + * Copyright 2023, NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.0.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real + * application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000U) +#endif + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ +#define CLK_GATE_REG_OFFSET(value) (((uint32_t)(value)) >> 16U) +#define CLK_GATE_BIT_SHIFT(value) (((uint32_t)(value)) & 0x0000FFFFU) + +#define REG_PWM0SUBCTL (250U) +#define REG_PWM1SUBCTL (240U) + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_InputMux = ((0x00U << 16U) | (0U)), /*!< Clock gate name: INPUTMUX0 */ + kCLOCK_GateINPUTMUX0 = ((0x00U << 16U) | (0U)), /*!< Clock gate name: INPUTMUX0 */ + kCLOCK_GateCTIMER0 = ((0x00U << 16U) | (2U)), /*!< Clock gate name: CTIMER0 */ + kCLOCK_GateCTIMER1 = ((0x00U << 16U) | (3U)), /*!< Clock gate name: CTIMER1 */ + kCLOCK_GateCTIMER2 = ((0x00U << 16U) | (4U)), /*!< Clock gate name: CTIMER2 */ + kCLOCK_GateFREQME = ((0x00U << 16U) | (7U)), /*!< Clock gate name: FREQME */ + kCLOCK_GateUTICK0 = ((0x00U << 16U) | (8U)), /*!< Clock gate name: UTICK0 */ + kCLOCK_GateWWDT0 = ((0x00U << 16U) | (9U)), /*!< Clock gate name: WWDT0 */ + kCLOCK_Smartdma = ((0x00U << 16U) | (10U)), /*!< Clock gate name: SMARTDMA0 */ + kCLOCK_GateDMA0 = ((0x00U << 16U) | (11U)), /*!< Clock gate name: DMA0 */ + kCLOCK_GateAOI0 = ((0x00U << 16U) | (12U)), /*!< Clock gate name: AOI0 */ + kCLOCK_GateCRC0 = ((0x00U << 16U) | (13U)), /*!< Clock gate name: CRC0 */ + kCLOCK_Crc0 = ((0x00U << 16U) | (13U)), /*!< Clock gate name: CRC0 */ + kCLOCK_GateEIM0 = ((0x00U << 16U) | (14U)), /*!< Clock gate name: EIM0 */ + kCLOCK_GateERM0 = ((0x00U << 16U) | (15U)), /*!< Clock gate name: ERM0 */ + kCLOCK_GateFMC = ((0x00U << 16U) | (16U)), /*!< Clock gate name: FMC */ + kCLOCK_GateAOI1 = ((0x00U << 16U) | (17U)), /*!< Clock gate name: AOI1 */ + kCLOCK_GateLPI2C0 = ((0x00U << 16U) | (19U)), /*!< Clock gate name: LPI2C0 */ + kCLOCK_GateLPI2C1 = ((0x00U << 16U) | (20U)), /*!< Clock gate name: LPI2C1 */ + kCLOCK_GateLPSPI0 = ((0x00U << 16U) | (21U)), /*!< Clock gate name: LPSPI0 */ + kCLOCK_GateLPSPI1 = ((0x00U << 16U) | (22U)), /*!< Clock gate name: LPSPI1 */ + kCLOCK_GateLPUART0 = ((0x00U << 16U) | (23U)), /*!< Clock gate name: LPUART0 */ + kCLOCK_GateLPUART1 = ((0x00U << 16U) | (24U)), /*!< Clock gate name: LPUART1 */ + kCLOCK_GateLPUART2 = ((0x00U << 16U) | (25U)), /*!< Clock gate name: LPUART2 */ + kCLOCK_GateLPUART3 = ((0x00U << 16U) | (26U)), /*!< Clock gate name: LPUART3 */ + kCLOCK_GateQDC0 = ((0x00U << 16U) | (29U)), /*!< Clock gate name: QDC0 */ + kCLOCK_GateQDC1 = ((0x00U << 16U) | (30U)), /*!< Clock gate name: QDC1 */ + kCLOCK_GateFLEXPWM0 = ((0x00U << 16U) | (31U)), /*!< Clock gate name: FLEXPWM0 */ + kCLOCK_GateFLEXPWM1 = ((0x10U << 16U) | (0U)), /*!< Clock gate name: FLEXPWM1 */ + kCLOCK_GateOSTIMER0 = ((0x10U << 16U) | (1U)), /*!< Clock gate name: OSTIMER0 */ + kCLOCK_GateADC0 = ((0x10U << 16U) | (2U)), /*!< Clock gate name: ADC0 */ + kCLOCK_GateADC1 = ((0x10U << 16U) | (3U)), /*!< Clock gate name: ADC1 */ + kCLOCK_GateCMP0 = ((0x10U << 16U) | (4U)), /*!< Clock gate name: CMP0 */ + kCLOCK_GateCMP1 = ((0x10U << 16U) | (5U)), /*!< Clock gate name: CMP1 */ + kCLOCK_GateCMP2 = ((0x10U << 16U) | (6U)), /*!< Clock gate name: CMP2 */ + kCLOCK_GateOPAMP0 = ((0x10U << 16U) | (8U)), /*!< Clock gate name: OPAMP0 */ + kCLOCK_GateOPAMP1 = ((0x10U << 16U) | (9U)), /*!< Clock gate name: OPAMP1 */ + kCLOCK_GateOPAMP2 = ((0x10U << 16U) | (10U)), /*!< Clock gate name: OPAMP2 */ + kCLOCK_GatePORT0 = ((0x10U << 16U) | (12U)), /*!< Clock gate name: PORT0 */ + kCLOCK_GatePORT1 = ((0x10U << 16U) | (13U)), /*!< Clock gate name: PORT1 */ + kCLOCK_GatePORT2 = ((0x10U << 16U) | (14U)), /*!< Clock gate name: PORT2 */ + kCLOCK_GatePORT3 = ((0x10U << 16U) | (15U)), /*!< Clock gate name: PORT3 */ + kCLOCK_GatePORT4 = ((0x10U << 16U) | (16U)), /*!< Clock gate name: PORT4 */ + kCLOCK_GateFLEXCAN0 = ((0x10U << 16U) | (18U)), /*!< Clock gate name: FLEXCAN0 */ + kCLOCK_GateRAMA = ((0x20U << 16U) | (1U)), /*!< Clock gate name: RAMA */ + kCLOCK_GateRAMB = ((0x20U << 16U) | (2U)), /*!< Clock gate name: RAMB */ + kCLOCK_GateRAMC = ((0x20U << 16U) | (3U)), /*!< Clock gate name: RAMC */ + kCLOCK_GateGPIO0 = ((0x20U << 16U) | (4U)), /*!< Clock gate name: GPIO0 */ + kCLOCK_GateGPIO1 = ((0x20U << 16U) | (5U)), /*!< Clock gate name: GPIO1 */ + kCLOCK_GateGPIO2 = ((0x20U << 16U) | (6U)), /*!< Clock gate name: GPIO2 */ + kCLOCK_GateGPIO3 = ((0x20U << 16U) | (7U)), /*!< Clock gate name: GPIO3 */ + kCLOCK_GateGPIO4 = ((0x20U << 16U) | (8U)), /*!< Clock gate name: GPIO4 */ + kCLOCK_GateMAU0 = ((0x20U << 16U) | (9U)), /*!< Clock gate name: MAU0 */ + kCLOCK_GateROMC = ((0x20U << 16U) | (10U)), /*!< Clock gate name: ROMC */ + kCLOCK_GatePWM0SM0 = ((REG_PWM0SUBCTL << 16U) | (0U)), /*!< Clock gate name: PWM0 SM0 */ + kCLOCK_GatePWM0SM1 = ((REG_PWM0SUBCTL << 16U) | (1U)), /*!< Clock gate name: PWM0 SM1 */ + kCLOCK_GatePWM0SM2 = ((REG_PWM0SUBCTL << 16U) | (2U)), /*!< Clock gate name: PWM0 SM2 */ + kCLOCK_GatePWM0SM3 = ((REG_PWM0SUBCTL << 16U) | (3U)), /*!< Clock gate name: PWM0 SM3 */ + kCLOCK_GatePWM1SM0 = ((REG_PWM1SUBCTL << 16U) | (0U)), /*!< Clock gate name: PWM1 SM0 */ + kCLOCK_GatePWM1SM1 = ((REG_PWM1SUBCTL << 16U) | (1U)), /*!< Clock gate name: PWM1 SM1 */ + kCLOCK_GatePWM1SM2 = ((REG_PWM1SUBCTL << 16U) | (2U)), /*!< Clock gate name: PWM1 SM2 */ + kCLOCK_GatePWM1SM3 = ((REG_PWM1SUBCTL << 16U) | (3U)), /*!< Clock gate name: PWM1 SM3 */ + kCLOCK_GateNotAvail = (0xFFFFFFFFU), /*!< Clock gate name: None */ +} clock_ip_name_t; + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS {kCLOCK_GateAOI0, kCLOCK_GateAOI1} +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS {kCLOCK_GateCRC0} +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS {kCLOCK_GateCTIMER0, kCLOCK_GateCTIMER1, kCLOCK_GateCTIMER2} +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS {kCLOCK_GateDMA0} +/*! @brief Clock gate name array for EDMA. */ +#define EDMA_CLOCKS {kCLOCK_GateDMA0} +/*! @brief Clock ip name array for ERM. */ +#define ERM_CLOCKS {kCLOCK_GateERM0} +/*! @brief Clock ip name array for EIM. */ +#define EIM_CLOCKS {kCLOCK_GateEIM0} +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS {kCLOCK_GateFLEXCAN0} +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS {kCLOCK_GateFREQME} +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS {kCLOCK_GateGPIO0, kCLOCK_GateGPIO1, kCLOCK_GateGPIO2, kCLOCK_GateGPIO3, kCLOCK_GateGPIO4} +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS {kCLOCK_GateINPUTMUX0} +/*! @brief Clock ip name array for GPIO. */ +#define LPCMP_CLOCKS {kCLOCK_GateCMP0, kCLOCK_GateCMP1, kCLOCK_GateCMP2} +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS {kCLOCK_GateADC0, kCLOCK_GateADC1} +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS {kCLOCK_GateLPUART0, kCLOCK_GateLPUART1, kCLOCK_GateLPUART2, kCLOCK_GateLPUART3} +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS {kCLOCK_GateLPI2C0, kCLOCK_GateLPI2C1} +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS {kCLOCK_GateLPSPI0, kCLOCK_GateLPSPI1} +/*! @brief Clock ip name array for MAU. */ +#define MAU_CLOCKS {kCLOCK_GateMAU0} +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS {kCLOCK_GateOSTIMER0} +/*! @brief Clock ip name array for OPAMP. */ +#define OPAMP_CLOCKS {kCLOCK_GateOPAMP0, kCLOCK_GateOPAMP1, kCLOCK_GateOPAMP2} +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_GatePWM0SM0, kCLOCK_GatePWM0SM1, kCLOCK_GatePWM0SM2, kCLOCK_GatePWM0SM3}, \ + { \ + kCLOCK_GatePWM1SM0, kCLOCK_GatePWM1SM1, kCLOCK_GatePWM1SM2, kCLOCK_GatePWM1SM3 \ + } \ + } +/*! @brief Clock ip name array for PORT. */ +#define PORT_CLOCKS {kCLOCK_GatePORT0, kCLOCK_GatePORT1, kCLOCK_GatePORT2, kCLOCK_GatePORT3, kCLOCK_GatePORT4 \ } +/*! @brief Clock ip name array for QDC. */ +#define QDC_CLOCKS {kCLOCK_GateQDC0, kCLOCK_GateQDC1} +/*! @brief Clock ip name array for SMARTDMA. */ +#define SMARTDMA_CLOCKS {kCLOCK_Smartdma} +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS {kCLOCK_GateUTICK0} +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS {kCLOCK_GateWWDT0} + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_MainClk, /*!< MAIN_CLK */ + kCLOCK_CoreSysClk, /*!< Core/system clock(CPU_CLK) */ + kCLOCK_SYSTEM_CLK, /*!< SYSTEM clock/AHB_BUS */ + kCLOCK_BusClk, /*!< SYSTEM clock divided by 2 */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_FroHf, /*!< FRO192 */ + kCLOCK_FroHfDiv, /*!< Divided by FRO192 */ + kCLOCK_Clk45M, /*!< CLK45M */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_Fro12MDiv, /*!< FRO12MDiv */ + kCLOCK_Clk1M, /*!< CLK1M */ + kCLOCK_Fro16K, /*!< FRO16K */ + kCLOCK_Clk16K0, /*!< CLK16K[0] */ + kCLOCK_Clk16K1, /*!< CLK16K[1] */ + kCLOCK_SLOW_CLK, /*!< SYSTEM_CLK divided by 6 */ +} clock_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while + * 24bits are valuable starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_REG_OFFSET(value) (((uint32_t)(value)) >> 16U) +#define CLK_ATTACH_CLK_SEL(value) (((uint32_t)(value)) & 0x0000FFFFU) +#define CLK_ATTACH_MUX(reg, sel) ((((uint32_t)(reg)) << 16U) | (sel)) + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_select_name +{ + kCLOCK_SelCTIMER0 = (0x0A0U), /*!< CTIMER0 clock selection */ + kCLOCK_SelCTIMER1 = (0x0A8U), /*!< CTIMER1 clock selection */ + kCLOCK_SelCTIMER2 = (0x0B0U), /*!< CTIMER2 clock selection */ + kCLOCK_SelLPI2C0 = (0x0C0U), /*!< LPI2C0 clock selection */ + kCLOCK_SelLPI2C1 = (0x0C8U), /*!< LPI2C1 clock selection */ + kCLOCK_SelLPSPI0 = (0x0D0U), /*!< LPSPI0 clock selection */ + kCLOCK_SelLPSPI1 = (0x0D8U), /*!< LPSPI1 clock selection */ + kCLOCK_SelLPUART0 = (0x0E0U), /*!< LPUART0 clock selection */ + kCLOCK_SelLPUART1 = (0x0E8U), /*!< LPUART1 clock selection */ + kCLOCK_SelLPUART2 = (0x0F0U), /*!< LPUART2 clock selection */ + kCLOCK_SelLPUART3 = (0x0F8U), /*!< LPUART3 clock selection */ + kCLOCK_SelLPTMR0 = (0x100U), /*!< LPTMR0 clock selection */ + kCLOCK_SelOSTIMER0 = (0x108U), /*!< OSTIMER0 clock selection */ + kCLOCK_SelADC = (0x110U), /*!< ADC clock selection */ + kCLOCK_SelCMP0_RR = (0x120U), /*!< CMP0_RR clock selection */ + kCLOCK_SelCMP1_RR = (0x130U), /*!< CMP1_RR clock selection */ + kCLOCK_SelCMP2_RR = (0x140U), /*!< CMP2_RR clock selection */ + kCLOCK_SelFLEXCAN0 = (0x148U), /*!< FLEXCAN0 clock selection */ + kCLOCK_SelTRACE = (0x150U), /*!< TRACE clock selection */ + kCLOCK_SelCLKOUT = (0x158U), /*!< CLKOUT clock selection */ + kCLOCK_SelSCGSCS = (0x200U), /*!< SCG SCS clock selection */ + kCLOCK_SelMax = (0x200U), /*!< MAX clock selection */ +} clock_select_name_t; + +/*! + * @brief The enumerator of clock attach Id. + */ +typedef enum _clock_attach_id +{ + kCLK_IN_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 1U), /*!< Attach clk_in to MAIN_CLK. */ + kFRO12M_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 2U), /*!< Attach FRO_12M to MAIN_CLK. */ + kFRO_HF_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 3U), /*!< Attach FRO_HF to MAIN_CLK. */ + kCLK_16K_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 4U), /*!< Attach CLK_16K[1] to MAIN_CLK. */ + kNONE_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 7U), /*!< Attach NONE to MAIN_CLK. */ + + kFRO_LF_DIV_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 0U), /*!< Attach FRO_LF_DIV to CTIMER0. */ + kFRO_HF_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 1U), /*!< Attach FRO_HF to CTIMER0. */ + kCLK_IN_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 3U), /*!< Attach CLK_IN to CTIMER0. */ + kCLK_16K_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 4U), /*!< Attach CLK_16K to CTIMER0. */ + kCLK_1M_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 5U), /*!< Attach CLK_1M to CTIMER0. */ + kNONE_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 7U), /*!< Attach NONE to CTIMER0. */ + + kFRO_LF_DIV_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 0U), /*!< Attach FRO_LF_DIV to CTIMER1. */ + kFRO_HF_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 1U), /*!< Attach FRO_HF to CTIMER1. */ + kCLK_IN_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 3U), /*!< Attach CLK_IN to CTIMER1. */ + kCLK_16K_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 4U), /*!< Attach CLK_16K to CTIMER1. */ + kCLK_1M_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 5U), /*!< Attach CLK_1M to CTIMER1. */ + kNONE_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 7U), /*!< Attach NONE to CTIMER1. */ + + kFRO_LF_DIV_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 0U), /*!< Attach FRO_LF_DIV to CTIMER2. */ + kFRO_HF_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 1U), /*!< Attach FRO_HF to CTIMER2. */ + kCLK_IN_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 3U), /*!< Attach CLK_IN to CTIMER2. */ + kCLK_16K_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 4U), /*!< Attach CLK_16K to CTIMER2. */ + kCLK_1M_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 5U), /*!< Attach CLK_1M to CTIMER2. */ + kNONE_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 7U), /*!< Attach NONE to CTIMER2. */ + + kFRO_HF_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 1U), /*!< Attach FRO_HF to FLEXCAN0.*/ + kFRO_HF_DIV_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 2U), /*!< Attach FRO_HF_DIV to FLEXCAN0.*/ + kCLK_IN_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 3U), /*!< Attach CLK_IN to FLEXCAN0. */ + kNONE_to_FLEXCAN0 = CLK_ATTACH_MUX(kCLOCK_SelFLEXCAN0, 7U), /*!< Attach NONE to FLEXCAN0. */ + + kFRO_LF_DIV_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 0U), /*!< Attach FRO_LF_DIV to LPI2C0. */ + kFRO_HF_DIV_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 2U), /*!< Attach FRO_HF_DIV to LPI2C0. */ + kCLK_IN_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 3U), /*!< Attach CLK_IN to LPI2C0. */ + kCLK_1M_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 5U), /*!< Attach CLK_1M to LPI2C0. */ + kNONE_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 7U), /*!< Attach NONE to LPI2C0. */ + + kFRO_LF_DIV_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 0U), /*!< Attach FRO_LF_DIV to LPI2C1. */ + kFRO_HF_DIV_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 2U), /*!< Attach FRO_HF_DIV to LPI2C1. */ + kCLK_IN_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 3U), /*!< Attach CLK_IN to LPI2C1. */ + kCLK_1M_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 5U), /*!< Attach CLK_1M to LPI2C1. */ + kNONE_to_LPI2C1 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C1, 7U), /*!< Attach NONE to LPI2C1. */ + + kFRO_LF_DIV_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 0U), /*!< Attach FRO_LF_DIV to LPSPI0. */ + kFRO_HF_DIV_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 2U), /*!< Attach FRO_HF_DIV to LPSPI0. */ + kCLK_IN_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 3U), /*!< Attach CLK_IN to LPSPI0. */ + kCLK_1M_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 5U), /*!< Attach CLK_1M to LPSPI0. */ + kNONE_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 7U), /*!< Attach NONE to LPSPI0. */ + + kFRO_LF_DIV_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 0U), /*!< Attach FRO_LF_DIV to LPSPI1. */ + kFRO_HF_DIV_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 2U), /*!< Attach FRO_HF_DIV to LPSPI1. */ + kCLK_IN_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 3U), /*!< Attach CLK_IN to LPSPI1. */ + kCLK_1M_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 5U), /*!< Attach CLK_1M to LPSPI1. */ + kNONE_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 7U), /*!< Attach NONE to LPSPI1. */ + + kFRO_LF_DIV_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 0U), /*!< Attach FRO_LF_DIV to LPUART0. */ + kFRO_HF_DIV_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 2U), /*!< Attach FRO_HF_DIV to LPUART0. */ + kCLK_IN_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 3U), /*!< Attach CLK_IN to LPUART0. */ + kCLK_16K_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 4U), /*!< Attach CLK_16K to LPUART0. */ + kCLK_1M_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 5U), /*!< Attach CLK_1M to LPUART0. */ + kNONE_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 7U), /*!< Attach NONE to LPUART0. */ + + kFRO_LF_DIV_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 0U), /*!< Attach FRO_LF_DIV to LPUART1. */ + kFRO_HF_DIV_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 2U), /*!< Attach FRO_HF_DIV to LPUART1. */ + kCLK_IN_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 3U), /*!< Attach CLK_IN to LPUART1. */ + kCLK_16K_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 4U), /*!< Attach CLK_16K to LPUART1. */ + kCLK_1M_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 5U), /*!< Attach CLK_1M to LPUART1. */ + kNONE_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 7U), /*!< Attach NONE to LPUART1. */ + + kFRO_LF_DIV_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 0U), /*!< Attach FRO_LF_DIV to LPUART2. */ + kFRO_HF_DIV_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 2U), /*!< Attach FRO_HF_DIV to LPUART2. */ + kCLK_IN_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 3U), /*!< Attach CLK_IN to LPUART2. */ + kCLK_16K_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 4U), /*!< Attach CLK_16K to LPUART2. */ + kCLK_1M_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 5U), /*!< Attach CLK_1M to LPUART2. */ + kNONE_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 7U), /*!< Attach NONE to LPUART2. */ + + kFRO_LF_DIV_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 0U), /*!< Attach FRO_LF_DIV to LPUART2. */ + kFRO_HF_DIV_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 2U), /*!< Attach FRO_HF_DIV to LPUART2. */ + kCLK_IN_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 3U), /*!< Attach CLK_IN to LPUART2. */ + kCLK_16K_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 4U), /*!< Attach CLK_16K to LPUART2. */ + kCLK_1M_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 5U), /*!< Attach CLK_1M to LPUART2. */ + kNONE_to_LPUART3 = CLK_ATTACH_MUX(kCLOCK_SelLPUART3, 7U), /*!< Attach NONE to LPUART2. */ + + kFRO_LF_DIV_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 0U), /*!< Attach FRO_LF_DIV to LPTMR0. */ + kFRO_HF_DIV_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 2U), /*!< Attach FRO_HF_DIV to LPTMR0. */ + kCLK_IN_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 3U), /*!< Attach CLK_IN to LPTMR0. */ + kCLK_1M_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 5U), /*!< Attach CLK_1M to LPTMR0. */ + kNONE_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 7U), /*!< Attach NONE to LPTMR0. */ + + kCLK_16K_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 0U), /*!< Attach FRO16K to OSTIMER0. */ + kCLK_1M_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 2U), /*!< Attach CLK_1M to OSTIMER0. */ + kNONE_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 3U), /*!< Attach NONE to OSTIMER0. */ + + kFRO_LF_DIV_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 0U), /*!< Attach FRO_LF_DIV to ADC. */ + kFRO_HF_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 1U), /*!< Attach FRO_HF to ADC. */ + kCLK_IN_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 3U), /*!< Attach CLK_IN to ADC. */ + kCLK_1M_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 5U), /*!< Attach CLK_1M to ADC. */ + kNONE_to_ADC = CLK_ATTACH_MUX(kCLOCK_SelADC, 7U), /*!< Attach NONE to ADC. */ + + kFRO_LF_DIV_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 0U), /*!< Attach FRO_LF_DIV to CMP0. */ + kFRO_HF_DIV_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 2U), /*!< Attach FRO_HF_DIV to CMP0. */ + kCLK_IN_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 3U), /*!< Attach CLK_IN to CMP0. */ + kCLK_1M_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 5U), /*!< Attach CLK_1M to CMP0. */ + kNONE_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 7U), /*!< Attach NONE to CMP0. */ + + kFRO_LF_DIV_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 0U), /*!< Attach FRO_LF_DIV to CMP1. */ + kFRO_HF_DIV_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 2U), /*!< Attach FRO_HF_DIV to CMP1. */ + kCLK_IN_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 3U), /*!< Attach CLK_IN to CMP1. */ + kCLK_1M_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 5U), /*!< Attach CLK_1M to CMP1. */ + kNONE_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 7U), /*!< Attach NONE to CMP1. */ + + kFRO_LF_DIV_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 0U), /*!< Attach FRO_LF_DIV to CMP2. */ + kFRO_HF_DIV_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 2U), /*!< Attach FRO_HF_DIV to CMP2. */ + kCLK_IN_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 3U), /*!< Attach CLK_IN to CMP2. */ + kCLK_1M_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 5U), /*!< Attach CLK_1M to CMP2. */ + kNONE_to_CMP2 = CLK_ATTACH_MUX(kCLOCK_SelCMP2_RR, 7U), /*!< Attach NONE to CMP2. */ + + kCPU_CLK_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 0U), /*!< Attach CPU_CLK to TRACE. */ + kCLK_1M_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 1U), /*!< Attach CLK_1M to TRACE. */ + kCLK_16K_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 2U), /*!< Attach CLK_16K to TRACE. */ + kNONE_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 3U), /*!< Attach NONE to TRACE. */ + + kFRO12M_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 0U), /*!< Attach FRO12M to CLKOUT. */ + kFRO_HF_DIV_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 1U), /*!< Attach FRO_HF_DIV to CLKOUT. */ + kCLK_IN_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 2U), /*!< Attach CLK_IN to CLKOUT. */ + kCLK_16K_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 3U), /*!< Attach CLK_16K to CLKOUT. */ + kSLOW_CLK_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 6U), /*!< Attach SLOW_CLK to CLKOUT. */ + kNONE_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 7U), /*!< Attach NONE to CLKOUT. */ + + kNONE_to_NONE = (0xFFFFFFFFU), /*!< Attach NONE to NONE. */ + +} clock_attach_id_t; + +/*! @brief Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivCTIMER0 = (0x0A4U), /*!< CTIMER0 clock divider */ + kCLOCK_DivCTIMER1 = (0x0ACU), /*!< CTIMER1 clock divider */ + kCLOCK_DivCTIMER2 = (0x0B4U), /*!< CTIMER2 clock divider */ + kCLOCK_DivWWDT0 = (0x0BCU), /*!< WWDT0 clock divider */ + kCLOCK_DivLPI2C0 = (0x0C4U), /*!< LPI2C0 clock divider */ + kCLOCK_DivLPI2C1 = (0x0CCU), /*!< LPI2C1 clock divider */ + kCLOCK_DivLPSPI0 = (0x0D4U), /*!< LPSPI0 clock divider */ + kCLOCK_DivLPSPI1 = (0x0DCU), /*!< LPSPI1 clock divider */ + kCLOCK_DivLPUART0 = (0x0E4U), /*!< LPUART0 clock divider */ + kCLOCK_DivLPUART1 = (0x0ECU), /*!< LPUART1 clock divider */ + kCLOCK_DivLPUART2 = (0x0F4U), /*!< LPUART2 clock divider */ + kCLOCK_DivLPUART3 = (0x0FCU), /*!< LPUART3 clock divider */ + kCLOCK_DivLPTMR0 = (0x104U), /*!< LPTMR0 clock divider */ + kCLOCK_DivADC = (0x114U), /*!< ADC clock divider */ + kCLOCK_DivCMP0_FUNC = (0x11CU), /*!< CMP0_FUNC clock divider */ + kCLOCK_DivCMP0_RR = (0x124U), /*!< CMP0_RR clock divider */ + kCLOCK_DivCMP1_FUNC = (0x12CU), /*!< CMP1_FUNC clock divider */ + kCLOCK_DivCMP1_RR = (0x134U), /*!< CMP1_RR clock divider */ + kCLOCK_DivCMP2_FUNC = (0x13CU), /*!< CMP2_FUNC clock divider */ + kCLOCK_DivCMP2_RR = (0x144U), /*!< CMP2_RR clock divider */ + kCLOCK_DivFLEXCAN0 = (0x14CU), /*!< FLEXCAN0 clock divider */ + kCLOCK_DivTRACE = (0x154U), /*!< DBG_TRACE clock divider */ + kCLOCK_DivCLKOUT = (0x15CU), /*!< CLKOUT clock divider */ + kCLOCK_DivSLOWCLK = (0x378U), /*!< SLOWCLK clock divider */ + kCLOCK_DivBUSCLK = (0x37CU), /*!< BUSCLK clock divider */ + kCLOCK_DivAHBCLK = (0x380U), /*!< AHBCLK clock divider */ + kCLOCK_DivFRO_HF = (0x388U), /*!< FROHF clock divider */ + kCLOCK_DivFRO_LF = (0x38CU), /*!< FROLF clock divider */ + kCLOCK_DivMax = (0x38CU) /*!< Max clock divider */ +} clock_div_name_t; + +/*! + * @brief firc trim source. + */ +typedef enum _clke_16k +{ + kCLKE_16K_SYSTEM = VBAT_FROCLKE_CLKE(1U), /*!< To VSYS domain. */ + kCLKE_16K_COREMAIN = VBAT_FROCLKE_CLKE(2U) /*!< To VDD_CORE domain. */ +} clke_16k_t; + +/*! + * @brief SCG status return codes. + */ +enum _scg_status +{ + kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), /*!< Clock is busy. */ + kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */ +}; + +/*! + * @brief sirc trim mode. + */ +typedef enum _sirc_trim_mode +{ + kSCG_SircTrimNonUpdate = SCG_SIRCCSR_SIRCTREN_MASK, + /*!< Trim enable but not enable trim value update. In this mode, the + trim value is fixed to the initialized value which is defined by + trimCoar and trimFine in configure structure \ref sirc_trim_mode_t.*/ + + kSCG_SircTrimUpdate = SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK + /*!< Trim enable and trim value update enable. In this mode, the trim + value is auto update. */ + +} sirc_trim_mode_t; + +/*! + * @brief sirc trim source. + */ +typedef enum _sirc_trim_src +{ + kNoTrimSrc = 0, /*!< No external tirm source. */ + kSCG_SircTrimSrcSysOsc = 2U /*!< System OSC. */ +} sirc_trim_src_t; + +/*! + * @brief sirc trim configuration. + */ +typedef struct _sirc_trim_config +{ + sirc_trim_mode_t trimMode; /*!< Trim mode. */ + sirc_trim_src_t trimSrc; /*!< Trim source. */ + uint16_t trimDiv; /*!< Divider of SOSC. */ + uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is + kSCG_TrimUpdate. */ + uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is + kSCG_TrimUpdate. */ +} sirc_trim_config_t; + +/*! + * @brief SCG system OSC monitor mode. + */ +typedef enum _scg_sosc_monitor_mode +{ + kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC + error is detected. */ + kSCG_SysOscMonitorReset = + SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */ +} scg_sosc_monitor_mode_t; + +/*! + * @brief The active run mode (voltage level). + */ +typedef enum _run_mode +{ + kMD_Mode, /*!< Mid voltage (1.0 V). */ + kOD_Mode, /*!< Overdrive voltage (1.2 V). */ +} run_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); + uint32_t bit_shift = CLK_GATE_BIT_SHIFT(clk); + volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); + + if (clk == kCLOCK_GateNotAvail) + { + return; + } + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + if (reg_offset == REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL |= (1UL << bit_shift); + MRCC0->MRCC_GLB_CC0_SET = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK; + } + else if (reg_offset == REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL |= (1UL << bit_shift); + MRCC0->MRCC_GLB_CC1_SET = MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK; + } + else + { + *pClkCtrl = (1UL << bit_shift); + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); + uint32_t bit_shift = CLK_GATE_BIT_SHIFT(clk); + volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); + + if (clk == kCLOCK_GateNotAvail) + { + return; + } + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + if (reg_offset == REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL &= ~(1UL << bit_shift); + + if (0U == (SYSCON->PWM0SUBCTL & 0xFU)) + { + MRCC0->MRCC_GLB_CC0_CLR = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK; + } + } + else if (reg_offset == REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL &= ~(1UL << bit_shift); + + if (0U == (SYSCON->PWM1SUBCTL & 0xFU)) + { + MRCC0->MRCC_GLB_CC1_CLR = MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK; + } + } + else + { + *pClkCtrl = (1UL << bit_shift); + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + */ +void CLOCK_AttachClk(clock_attach_id_t connection); + +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual + * source value in the register and combine the offset to obtain an actual + * attach id. + * @param connection : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection); + +/** + * @brief Set the clock select value. + * This fuction set the peripheral clock select value. + * @param sel_name : Clock select. + * @param value : value to be set. + */ +void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value); + +/** + * @brief Get the clock select value. + * This fuction get the peripheral clock select value. + * @param sel_name : Clock select. + * @return Clock source value. + */ +uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name); + +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param value : Value to be divided + */ +void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value); + +/** + * @brief Get peripheral clock dividers. + * @param div_name : Clock divider name + * @return peripheral clock dividers + */ +uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name); + +/** + * @brief Halt peripheral clock dividers. + * @param div_name : Clock divider name + */ +void CLOCK_HaltClockDiv(clock_div_name_t div_name); + +/** + * @brief Initialize the FROHF to given frequency (48,64,96,192). + * This function turns on FIRC and select the given frequency as the source of + * fro_hf + * @param iFreq : Desired frequency. + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq); + +/** + * @brief Initialize the FRO12M. + * This function turns on FRO12M. + * @return returns success or fail status. + */ +status_t CLOCK_SetupFRO12MClocking(void); + +/** + * @brief Initialize the FRO16K. + * This function turns on FRO16K. + * @param clk_16k_enable_mask: 0-3 + * 0b00: disable both clk_16k0 and clk_16k1 + * 0b01: only enable clk_16k0 + * 0b10: only enable clk_16k1 + * 0b11: enable both clk_16k0 and clk_16k1 + * @return returns success or fail status. + */ +status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask); + +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); + +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! @brief Return Frequency of core + * @return Frequency of the core + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPI2C0 functional Clock + * @return Frequency of LPI2C0 functional Clock + */ +uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPSPI functional Clock + * @return Frequency of LPSPI functional Clock + */ +uint32_t CLOCK_GetLpspiClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPUART functional Clock + * @return Frequency of LPUART functional Clock + */ +uint32_t CLOCK_GetLpuartClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPTMR functional Clock + * @return Frequency of LPTMR functional Clock + */ +uint32_t CLOCK_GetLptmrClkFreq(void); + +/*! @brief Return Frequency of OSTIMER + * @return Frequency of OSTIMER Clock + */ +uint32_t CLOCK_GetOstimerClkFreq(void); + +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id); + +/*! @brief Return Frequency of CMP Function Clock + * @return Frequency of CMP Function. + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id); + +/*! @brief Return Frequency of CMP Round Robin Clock + * @return Frequency of CMP Round Robin. + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id); + +/*! @brief Return Frequency of Trace Clock + * @return Frequency of Trace. + */ +uint32_t CLOCK_GetTraceClkFreq(void); + +/*! @brief Return Frequency of CLKOUT Clock + * @return Frequency of CLKOUT. + */ +uint32_t CLOCK_GetClkoutClkFreq(void); + +/*! brief Return Frequency of WWDT Clock + * return Frequency of WWDT. + */ +uint32_t CLOCK_GetWwdtClkFreq(void); + +/*! @brief Return Frequency of FlexCAN FCLK + * @return Frequency of FlexCAN FCLK. + */ +uint32_t CLOCK_GetFlexcanClkFreq(void); + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config); + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the + * error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode); + +/*! + * @brief Set the additional number of wait-states added to account for the + * ratio of system clock period to flash access time during full speed power + * mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.c new file mode 100644 index 000000000..79b9eb8a0 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.c @@ -0,0 +1,111 @@ +/* + * Copyright 2022 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma_soc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma_soc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +extern void DMA_CH0_DriverIRQHandler(void); +extern void DMA_CH1_DriverIRQHandler(void); +extern void DMA_CH2_DriverIRQHandler(void); +extern void DMA_CH3_DriverIRQHandler(void); +extern void DMA_CH4_DriverIRQHandler(void); +extern void DMA_CH5_DriverIRQHandler(void); +extern void DMA_CH6_DriverIRQHandler(void); +extern void DMA_CH7_DriverIRQHandler(void); +extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief DMA instance 0, channel 0 IRQ handler. + * + */ +void DMA_CH0_DriverIRQHandler(void) +{ + /* Instance 0 channel 0 */ + EDMA_DriverIRQHandler(0U, 0U); +} + +/*! + * brief DMA instance 0, channel 1 IRQ handler. + * + */ +void DMA_CH1_DriverIRQHandler(void) +{ + /* Instance 0 channel 1 */ + EDMA_DriverIRQHandler(0U, 1U); +} + +/*! + * brief DMA instance 0, channel 2 IRQ handler. + * + */ +void DMA_CH2_DriverIRQHandler(void) +{ + /* Instance 0 channel 2 */ + EDMA_DriverIRQHandler(0U, 2U); +} + +/*! + * brief DMA instance 0, channel 3 IRQ handler. + * + */ +void DMA_CH3_DriverIRQHandler(void) +{ + /* Instance 0 channel 3 */ + EDMA_DriverIRQHandler(0U, 3U); +} + +/*! + * brief DMA instance 0, channel 4 IRQ handler. + * + */ +void DMA_CH4_DriverIRQHandler(void) +{ + /* Instance 0 channel 4 */ + EDMA_DriverIRQHandler(0U, 4U); +} +/*! + * brief DMA instance 0, channel 5 IRQ handler. + * + */ +void DMA_CH5_DriverIRQHandler(void) +{ + /* Instance 0 channel 5 */ + EDMA_DriverIRQHandler(0U, 5U); +} + +/*! + * brief DMA instance 0, channel 6 IRQ handler. + * + */ +void DMA_CH6_DriverIRQHandler(void) +{ + /* Instance 0 channel 6 */ + EDMA_DriverIRQHandler(0U, 6U); +} + +/*! + * brief DMA instance 0, channel 7 IRQ handler. + * + */ +void DMA_CH7_DriverIRQHandler(void) +{ + /* Instance 0 channel 7 */ + EDMA_DriverIRQHandler(0U, 7U); +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.h new file mode 100644 index 000000000..de424c359 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_edma_soc.h @@ -0,0 +1,60 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_EDMA_SOC_H_ +#define _FSL_EDMA_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.0. */ +#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*!@brief DMA IP version */ +#define FSL_EDMA_SOC_IP_DMA3 (1) +#define FSL_EDMA_SOC_IP_DMA4 (0) + +/*!@brief DMA base table */ +#define EDMA_BASE_PTRS {DMA0} + +#define EDMA_CHN_IRQS \ + { \ + { \ + DMA_CH0_IRQn, DMA_CH1_IRQn, DMA_CH2_IRQn, DMA_CH3_IRQn, DMA_CH4_IRQn, DMA_CH5_IRQn, DMA_CH6_IRQn, \ + DMA_CH7_IRQn \ + } \ + } + +/*!@brief EDMA base address convert macro */ +#define EDMA_CHANNEL_OFFSET 0x1000U +#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U) + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_EDMA_SOC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_inputmux_connections.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_inputmux_connections.h new file mode 100644 index 000000000..86907a0e3 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_inputmux_connections.h @@ -0,0 +1,4647 @@ +/* + * Copyright 2023 , NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief INPUTMUX_CONNECTION driver version 2.0.0. */ +#define FSL_INPUTMUX_CONNECTION_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define INPUTMUX_GpioPortPinToPintsel(port, pin) ((pin) + (PINTSEL_PMUX_ID << PMUX_SHIFT)) + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define TIMER0CAPTSEL0 (0x020U) +#define TIMER0TRIGIN (0x030U) +#define TIMER1CAPTSEL0 (0x040U) +#define TIMER1TRIGIN (0x050U) +#define TIMER2CAPTSEL0 (0x060U) +#define TIMER2TRIGIN (0x070U) +#define SMARTDMA0_TRIG0_REG (0x0A0U) +#define FREQMEAS_REF_REG (0x180U) +#define FREQMEAS_TAR_REG (0x184U) +#define TIMER3CAPTSEL0 (0x1A0U) +#define TIMER3TRIGIN (0x1B0U) +#define TIMER4CAPTSEL0 (0x1C0U) +#define TIMER4TRIGIN (0x1D0U) +#define AOI1_MUX_REG (0x200U) +#define CMP0_TRIG_REG (0x260U) +#define ADC0_TRIG0_REG (0x280U) +#define ADC2_TRIG0_REG (0x2A0U) +#define ADC1_TRIG0_REG (0x2C0U) +#define ADC3_TRIG0_REG (0x2E0U) +#define DAC0_TRIG0_REG (0x300U) +#define QDC0_TRIG_REG (0x360U) +#define QDC0_HOME_REG (0x364U) +#define QDC0_INDEX_REG (0x368U) +#define QDC0_PHASEB_REG (0x36CU) +#define QDC0_PHASEA_REG (0x370U) +#define QDC0_ICAP0_REG (0x370U) +#define QDC1_TRIG_REG (0x380U) +#define QDC1_HOME_REG (0x384U) +#define QDC1_INDEX_REG (0x388U) +#define QDC1_PHASEB_REG (0x38CU) +#define QDC1_PHASEA_REG (0x390U) +#define QDC1_ICAP0_REG (0x390U) +#define FlexPWM0_SM0_EXTA0_REG (0x3A0U) +#define FlexPWM0_SM0_EXTSYNC0_REG (0x3A4U) +#define FlexPWM0_SM1_EXTA1_REG (0x3A8U) +#define FlexPWM0_SM1_EXTSYNC1_REG (0x3ACU) +#define FlexPWM0_SM2_EXTA2_REG (0x3B0U) +#define FlexPWM0_SM2_EXTSYNC2_REG (0x3B4U) +#define FlexPWM0_SM3_EXTA3_REG (0x3B8U) +#define FlexPWM0_SM3_EXTSYNC3_REG (0x3BCU) +#define FlexPWM0_FAULT_REG (0x3C0U) +#define FlexPWM0_FORCE_REG (0x3D0U) +#define FlexPWM1_SM0_EXTA0_REG (0x3E0U) +#define FlexPWM1_SM0_EXTSYNC0_REG (0x3E4U) +#define FlexPWM1_SM1_EXTA1_REG (0x3E8U) +#define FlexPWM1_SM1_EXTSYNC1_REG (0x3ECU) +#define FlexPWM1_SM2_EXTA2_REG (0x3F0U) +#define FlexPWM1_SM2_EXTSYNC2_REG (0x3F4U) +#define FlexPWM1_SM3_EXTA3_REG (0x3F8U) +#define FlexPWM1_SM3_EXTSYNC3_REG (0x3FCU) +#define FlexPWM1_FAULT_REG (0x400U) +#define FlexPWM1_FORCE_REG (0x410U) +#define PWM0_EXT_CLK_REG (0x420U) +#define PWM1_EXT_CLK_REG (0x424U) +#define AOI0_MUX_REG (0x440U) +#define USBFS_TRIG_REG (0x480U) +#define EXT_TRIG0_REG (0x4C0U) +#define CMP1_TRIG_REG (0x4E0U) +#define CMP2_TRIG_REG (0x500U) +#define LPI2C2_TRIG_REG (0x540U) +#define LPI2C3_TRIG_REG (0x560U) +#define LPI2C0_TRIG_REG (0x5A0U) +#define LPI2C1_TRIG_REG (0x5C0U) +#define LPSPI0_TRIG_REG (0x5E0U) +#define LPSPI1_TRIG_REG (0x600U) +#define LPUART0_TRIG_REG (0x620U) +#define LPUART1_TRIG_REG (0x640U) +#define LPUART2_TRIG_REG (0x660U) +#define LPUART3_TRIG_REG (0x680U) +#define LPUART4_TRIG_REG (0x6A0U) +#define LPUART5_TRIG_REG (0x6C0U) +#define FLEXIO_TRIG0_REG (0x6E0U) +#define PMUX_SHIFT (20U) + +typedef enum _inputmux_index_t +{ + kINPUTMUX_INDEX_CTIMER0CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER0CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER0CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER0CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER3CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER3CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER3CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER3CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER4CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER4CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER4CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER4CAPTSEL3 = 3U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL5 = 5U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_SMARTDMA_TRIGSEL7 = 7U, + kINPUTMUX_INDEX_ADC0_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_ADC0_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_ADC0_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_ADC0_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_ADC1_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_ADC1_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_ADC1_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_ADC1_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_ADC2_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_ADC2_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_ADC2_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_ADC2_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_ADC3_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_ADC3_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_ADC3_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_ADC3_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_QDC0_ICAPSEL1 = 1U, + kINPUTMUX_INDEX_QDC0_ICAPSEL2 = 2U, + kINPUTMUX_INDEX_QDC0_ICAPSEL3 = 3U, + kINPUTMUX_INDEX_QDC1_ICAPSEL1 = 1U, + kINPUTMUX_INDEX_QDC1_ICAPSEL2 = 2U, + kINPUTMUX_INDEX_QDC1_ICAPSEL3 = 3U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL0 = 0U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL1 = 1U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL2 = 2U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL3 = 3U, + kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL0 = 0U, + kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL1 = 1U, + kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL2 = 2U, + kINPUTMUX_INDEX_FLEXPWM1_FAULTSEL3 = 3U, + kINPUTMUX_INDEX_AOI0_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_AOI0_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_AOI0_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_AOI0_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_AOI0_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_AOI0_TRIGSEL5 = 5U, + kINPUTMUX_INDEX_AOI0_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_AOI0_TRIGSEL7 = 7U, + kINPUTMUX_INDEX_AOI0_TRIGSEL8 = 8U, + kINPUTMUX_INDEX_AOI0_TRIGSEL9 = 9U, + kINPUTMUX_INDEX_AOI0_TRIGSEL10 = 10U, + kINPUTMUX_INDEX_AOI0_TRIGSEL11 = 11U, + kINPUTMUX_INDEX_AOI0_TRIGSEL12 = 12U, + kINPUTMUX_INDEX_AOI0_TRIGSEL13 = 13U, + kINPUTMUX_INDEX_AOI0_TRIGSEL14 = 14U, + kINPUTMUX_INDEX_AOI0_TRIGSEL15 = 15U, + kINPUTMUX_INDEX_AOI1_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_AOI1_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_AOI1_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_AOI1_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_AOI1_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_AOI1_TRIGSEL5 = 5U, + kINPUTMUX_INDEX_AOI1_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_AOI1_TRIGSEL7 = 7U, + kINPUTMUX_INDEX_AOI1_TRIGSEL8 = 8U, + kINPUTMUX_INDEX_AOI1_TRIGSEL9 = 9U, + kINPUTMUX_INDEX_AOI1_TRIGSEL10 = 10U, + kINPUTMUX_INDEX_AOI1_TRIGSEL11 = 11U, + kINPUTMUX_INDEX_AOI1_TRIGSEL12 = 12U, + kINPUTMUX_INDEX_AOI1_TRIGSEL13 = 13U, + kINPUTMUX_INDEX_AOI1_TRIGSEL14 = 14U, + kINPUTMUX_INDEX_AOI1_TRIGSEL15 = 15U, + kINPUTMUX_INDEX_EXT_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_EXT_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_EXT_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_EXT_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_EXT_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_EXT_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_EXT_TRIGSEL7 = 7U, + kINPUTMUX_INDEX_FLEXIO_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_FLEXIO_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_FLEXIO_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_FLEXIO_TRIGSEL3 = 3U +} inputmux_index_t; + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer0Captsel = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer0Captsel = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer0Captsel = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer0Captsel = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer0Captsel = 29U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Captsel = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Captsel = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer0Captsel = 32U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer0Captsel = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer0Captsel = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer0Captsel = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer0Captsel = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer0Captsel = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer0Captsel = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer0Captsel = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer0Captsel = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer0Captsel = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Captsel = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Captsel = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Captsel = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer0Captsel = 47U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Captsel = 48U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Captsel = 49U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer0Captsel = 50U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer0Captsel = 51U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer0Captsel = 52U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Captsel = 53U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer0Captsel = 54U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Captsel = 55U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Captsel = 56U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Captsel = 57U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Captsel = 58U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Captsel = 59U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Captsel = 60U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Captsel = 61U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Captsel = 62U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Captsel = 63U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Captsel = 64U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Captsel = 65U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Captsel = 66U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Captsel = 67U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Captsel = 68U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Captsel = 69U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Captsel = 70U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer0Captsel = 71U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer0Captsel = 72U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer0Captsel = 73U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer0Captsel = 74U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer0Captsel = 75U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer0Captsel = 76U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer0Captsel = 77U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer0Captsel = 78U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer0Captsel = 79U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer0Captsel = 80U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer0Captsel = 81U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer0Captsel = 82U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer0Captsel = 83U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer0Captsel = 84U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer0Captsel = 85U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer0Captsel = 86U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer0Captsel = 87U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer0Captsel = 88U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer0Captsel = 89U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Captsel = 90U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Captsel = 91U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Captsel = 92U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer0Captsel = 93U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Captsel = 94U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Captsel = 95U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Captsel = 96U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Captsel = 97U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer0Captsel = 98U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer0Captsel = 99U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer0Captsel = 100U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer0Captsel = 105U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer0Captsel = 106U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer0Captsel = 107U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer0Captsel = 108U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer0Captsel = 109U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer0Captsel = 110U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer0Captsel = 111U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer0Captsel = 112U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer1Captsel = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer1Captsel = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer1Captsel = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer1Captsel = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer1Captsel = 29U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Captsel = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Captsel = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer1Captsel = 32U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer1Captsel = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer1Captsel = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer1Captsel = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer1Captsel = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer1Captsel = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer1Captsel = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer1Captsel = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer1Captsel = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer1Captsel = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Captsel = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Captsel = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Captsel = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer1Captsel = 47U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Captsel = 48U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Captsel = 49U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer1Captsel = 50U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer1Captsel = 51U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer1Captsel = 52U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Captsel = 53U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer1Captsel = 54U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Captsel = 55U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Captsel = 56U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Captsel = 57U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Captsel = 58U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Captsel = 59U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Captsel = 60U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Captsel = 61U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Captsel = 62U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Captsel = 63U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Captsel = 64U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Captsel = 65U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Captsel = 66U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Captsel = 67U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Captsel = 68U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Captsel = 69U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Captsel = 70U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer1Captsel = 71U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer1Captsel = 72U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer1Captsel = 73U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer1Captsel = 74U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer1Captsel = 75U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer1Captsel = 76U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer1Captsel = 77U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer1Captsel = 78U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer1Captsel = 79U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer1Captsel = 80U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer1Captsel = 81U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer1Captsel = 82U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer1Captsel = 83U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer1Captsel = 84U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer1Captsel = 85U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer1Captsel = 86U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer1Captsel = 87U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer1Captsel = 88U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer1Captsel = 89U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Captsel = 90U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Captsel = 91U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Captsel = 92U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer1Captsel = 93U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Captsel = 94U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Captsel = 95U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Captsel = 96U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Captsel = 97U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer1Captsel = 98U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer1Captsel = 99U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer1Captsel = 100U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer1Captsel = 105U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer1Captsel = 106U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer1Captsel = 107U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer1Captsel = 108U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer1Captsel = 109U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer1Captsel = 110U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer1Captsel = 111U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer1Captsel = 112U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer2Captsel = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer2Captsel = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer2Captsel = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer2Captsel = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer2Captsel = 29U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Captsel = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Captsel = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer2Captsel = 32U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer2Captsel = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer2Captsel = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer2Captsel = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer2Captsel = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer2Captsel = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer2Captsel = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer2Captsel = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer2Captsel = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer2Captsel = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Captsel = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Captsel = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Captsel = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer2Captsel = 47U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Captsel = 48U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Captsel = 49U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer2Captsel = 50U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer2Captsel = 51U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer2Captsel = 52U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Captsel = 53U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer2Captsel = 54U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Captsel = 55U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Captsel = 56U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Captsel = 57U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Captsel = 58U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Captsel = 59U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Captsel = 60U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Captsel = 61U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Captsel = 62U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Captsel = 63U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Captsel = 64U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Captsel = 65U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Captsel = 66U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Captsel = 67U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Captsel = 68U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Captsel = 69U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Captsel = 70U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer2Captsel = 71U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer2Captsel = 72U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer2Captsel = 73U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer2Captsel = 74U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer2Captsel = 75U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer2Captsel = 76U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer2Captsel = 77U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer2Captsel = 78U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer2Captsel = 79U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer2Captsel = 80U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer2Captsel = 81U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer2Captsel = 82U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer2Captsel = 83U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer2Captsel = 84U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer2Captsel = 85U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer2Captsel = 86U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer2Captsel = 87U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer2Captsel = 88U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer2Captsel = 89U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Captsel = 90U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Captsel = 91U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Captsel = 92U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer2Captsel = 93U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Captsel = 94U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Captsel = 95U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Captsel = 96U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Captsel = 97U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer2Captsel = 98U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer2Captsel = 99U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer2Captsel = 100U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer2Captsel = 105U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer2Captsel = 106U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer2Captsel = 107U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer2Captsel = 108U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer2Captsel = 109U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer2Captsel = 110U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer2Captsel = 111U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer2Captsel = 112U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer3Captsel = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer3Captsel = 26U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer3Captsel = 27U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer3Captsel = 28U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer3Captsel = 29U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Captsel = 30U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Captsel = 31U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer3Captsel = 32U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer3Captsel = 33U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer3Captsel = 34U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer3Captsel = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer3Captsel = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer3Captsel = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer3Captsel = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer3Captsel = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer3Captsel = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer3Captsel = 43U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Captsel = 44U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Captsel = 45U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Captsel = 46U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer3Captsel = 47U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Captsel = 48U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Captsel = 49U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer3Captsel = 50U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer3Captsel = 51U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer3Captsel = 52U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Captsel = 53U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer3Captsel = 54U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Captsel = 55U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Captsel = 56U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Captsel = 57U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Captsel = 58U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Captsel = 59U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Captsel = 60U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Captsel = 61U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Captsel = 62U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Captsel = 63U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Captsel = 64U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Captsel = 65U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Captsel = 66U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Captsel = 67U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Captsel = 68U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Captsel = 69U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Captsel = 70U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer3Captsel = 71U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer3Captsel = 72U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer3Captsel = 73U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer3Captsel = 74U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer3Captsel = 75U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer3Captsel = 76U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer3Captsel = 77U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer3Captsel = 78U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer3Captsel = 79U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer3Captsel = 80U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer3Captsel = 81U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer3Captsel = 82U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer3Captsel = 83U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer3Captsel = 84U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer3Captsel = 85U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer3Captsel = 86U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer3Captsel = 87U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer3Captsel = 88U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer3Captsel = 89U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Captsel = 90U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Captsel = 91U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Captsel = 92U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer3Captsel = 93U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Captsel = 94U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Captsel = 95U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Captsel = 96U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Captsel = 97U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer3Captsel = 98U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer3Captsel = 99U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer3Captsel = 100U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer3Captsel = 105U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer3Captsel = 106U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer3Captsel = 107U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer3Captsel = 108U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer3Captsel = 109U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer3Captsel = 110U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer3Captsel = 111U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer3Captsel = 112U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToTimer3Captsel = 113U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToTimer3Captsel = 114U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToTimer3Captsel = 115U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToTimer3Captsel = 116U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToTimer3Captsel = 117U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToTimer3Captsel = 118U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToTimer3Captsel = 119U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToTimer3Captsel = 120U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToTimer3Captsel = 121U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToTimer3Captsel = 122U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToTimer3Captsel = 123U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToTimer3Captsel = 124U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer4Captsel = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer4Captsel = 26U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer4Captsel = 27U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer4Captsel = 28U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer4Captsel = 29U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Captsel = 30U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Captsel = 31U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer4Captsel = 32U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer4Captsel = 33U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer4Captsel = 34U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer4Captsel = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer4Captsel = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer4Captsel = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer4Captsel = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer4Captsel = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer4Captsel = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer4Captsel = 43U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Captsel = 44U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Captsel = 45U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Captsel = 46U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer4Captsel = 47U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Captsel = 48U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Captsel = 49U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer4Captsel = 50U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer4Captsel = 51U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer4Captsel = 52U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Captsel = 53U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer4Captsel = 54U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Captsel = 55U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Captsel = 56U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Captsel = 57U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Captsel = 58U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Captsel = 59U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Captsel = 60U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Captsel = 61U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Captsel = 62U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Captsel = 63U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Captsel = 64U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Captsel = 65U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Captsel = 66U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Captsel = 67U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Captsel = 68U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Captsel = 69U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Captsel = 70U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer4Captsel = 71U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer4Captsel = 72U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer4Captsel = 73U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer4Captsel = 74U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer4Captsel = 75U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer4Captsel = 76U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer4Captsel = 77U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer4Captsel = 78U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer4Captsel = 79U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer4Captsel = 80U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer4Captsel = 81U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer4Captsel = 82U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer4Captsel = 83U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer4Captsel = 84U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer4Captsel = 85U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer4Captsel = 86U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer4Captsel = 87U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer4Captsel = 88U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer4Captsel = 89U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Captsel = 90U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Captsel = 91U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Captsel = 92U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer4Captsel = 93U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Captsel = 94U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Captsel = 95U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Captsel = 96U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Captsel = 97U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer4Captsel = 98U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer4Captsel = 99U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer4Captsel = 100U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer4Captsel = 105U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer4Captsel = 106U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer4Captsel = 107U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer4Captsel = 108U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer4Captsel = 109U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer4Captsel = 110U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer4Captsel = 111U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer4Captsel = 112U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToTimer4Captsel = 113U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToTimer4Captsel = 114U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToTimer4Captsel = 115U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToTimer4Captsel = 116U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToTimer4Captsel = 117U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToTimer4Captsel = 118U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToTimer4Captsel = 119U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToTimer4Captsel = 120U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToTimer4Captsel = 121U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToTimer4Captsel = 122U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToTimer4Captsel = 123U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToTimer4Captsel = 124U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER0 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer0Trigger = 1U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Trigger = 2U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Trigger = 3U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Trigger = 4U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Trigger = 5U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Trigger = 6U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Trigger = 7U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Trigger = 8U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Trigger = 9U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Trigger = 10U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Trigger = 11U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Trigger = 12U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Trigger = 13U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Trigger = 14U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Trigger = 15U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Trigger = 16U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Trigger = 17U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Trigger = 18U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Trigger = 19U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Trigger = 20U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Trigger = 21U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer0Trigger = 22U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer0Trigger = 23U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer0Trigger = 24U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer0Trigger = 25U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer0Trigger = 26U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer0Trigger = 27U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer0Trigger = 28U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer0Trigger = 29U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Trigger = 30U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Trigger = 31U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer0Trigger = 32U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer0Trigger = 33U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer0Trigger = 34U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer0Trigger = 35U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer0Trigger = 36U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer0Trigger = 37U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer0Trigger = 40U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer0Trigger = 41U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer0Trigger = 42U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer0Trigger = 43U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Trigger = 44U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Trigger = 45U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Trigger = 46U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer0Trigger = 47U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Trigger = 48U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Trigger = 49U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer0Trigger = 50U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer0Trigger = 51U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer0Trigger = 52U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Trigger = 53U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer0Trigger = 54U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Trigger = 55U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Trigger = 56U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Trigger = 57U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Trigger = 58U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Trigger = 59U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Trigger = 60U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Trigger = 61U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Trigger = 62U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Trigger = 63U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Trigger = 64U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Trigger = 65U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Trigger = 66U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Trigger = 67U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Trigger = 68U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Trigger = 69U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Trigger = 70U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer0Trigger = 71U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer0Trigger = 72U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer0Trigger = 73U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer0Trigger = 74U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer0Trigger = 75U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer0Trigger = 76U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer0Trigger = 77U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer0Trigger = 78U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer0Trigger = 79U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer0Trigger = 80U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer0Trigger = 81U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer0Trigger = 82U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer0Trigger = 83U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer0Trigger = 84U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer0Trigger = 85U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer0Trigger = 86U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer0Trigger = 87U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer0Trigger = 88U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer0Trigger = 89U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Trigger = 90U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Trigger = 91U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Trigger = 92U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer0Trigger = 93U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Trigger = 94U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Trigger = 95U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Trigger = 96U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Trigger = 97U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer0Trigger = 98U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer0Trigger = 99U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer0Trigger = 100U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer0Trigger = 105U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer0Trigger = 106U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer0Trigger = 107U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer0Trigger = 108U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer0Trigger = 109U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer0Trigger = 110U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer0Trigger = 111U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer0Trigger = 112U + (TIMER0TRIGIN << PMUX_SHIFT), + + /*!< TIMER1 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer1Trigger = 1U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Trigger = 2U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Trigger = 3U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Trigger = 4U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Trigger = 5U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Trigger = 6U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Trigger = 7U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Trigger = 8U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Trigger = 9U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Trigger = 10U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Trigger = 11U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Trigger = 12U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Trigger = 13U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Trigger = 14U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Trigger = 15U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Trigger = 16U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Trigger = 17U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Trigger = 18U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Trigger = 19U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Trigger = 20U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Trigger = 21U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer1Trigger = 22U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer1Trigger = 23U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer1Trigger = 24U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer1Trigger = 25U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer1Trigger = 26U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer1Trigger = 27U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer1Trigger = 28U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer1Trigger = 29U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Trigger = 30U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Trigger = 31U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer1Trigger = 32U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer1Trigger = 33U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer1Trigger = 34U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer1Trigger = 35U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer1Trigger = 36U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer1Trigger = 37U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer1Trigger = 40U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer1Trigger = 41U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer1Trigger = 42U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer1Trigger = 43U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Trigger = 44U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Trigger = 45U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Trigger = 46U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer1Trigger = 47U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Trigger = 48U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Trigger = 49U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer1Trigger = 50U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer1Trigger = 51U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer1Trigger = 52U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Trigger = 53U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer1Trigger = 54U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Trigger = 55U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Trigger = 56U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Trigger = 57U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Trigger = 58U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Trigger = 59U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Trigger = 60U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Trigger = 61U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Trigger = 62U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Trigger = 63U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Trigger = 64U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Trigger = 65U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Trigger = 66U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Trigger = 67U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Trigger = 68U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Trigger = 69U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Trigger = 70U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer1Trigger = 71U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer1Trigger = 72U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer1Trigger = 73U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer1Trigger = 74U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer1Trigger = 75U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer1Trigger = 76U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer1Trigger = 77U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer1Trigger = 78U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer1Trigger = 79U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer1Trigger = 80U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer1Trigger = 81U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer1Trigger = 82U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer1Trigger = 83U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer1Trigger = 84U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer1Trigger = 85U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer1Trigger = 86U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer1Trigger = 87U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer1Trigger = 88U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer1Trigger = 89U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Trigger = 90U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Trigger = 91U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Trigger = 92U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer1Trigger = 93U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Trigger = 94U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Trigger = 95U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Trigger = 96U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Trigger = 97U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer1Trigger = 98U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer1Trigger = 99U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer1Trigger = 100U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer1Trigger = 105U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer1Trigger = 106U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer1Trigger = 107U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer1Trigger = 108U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer1Trigger = 109U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer1Trigger = 110U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer1Trigger = 111U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer1Trigger = 112U + (TIMER1TRIGIN << PMUX_SHIFT), + + /*!< TIMER2 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer2Trigger = 1U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Trigger = 2U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Trigger = 3U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Trigger = 4U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Trigger = 5U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Trigger = 6U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Trigger = 7U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Trigger = 8U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Trigger = 9U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Trigger = 10U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Trigger = 11U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Trigger = 12U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Trigger = 13U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Trigger = 14U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Trigger = 15U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Trigger = 16U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Trigger = 17U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Trigger = 18U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Trigger = 19U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Trigger = 20U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Trigger = 21U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer2Trigger = 22U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer2Trigger = 23U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer2Trigger = 24U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer2Trigger = 25U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer2Trigger = 26U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer2Trigger = 27U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer2Trigger = 28U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer2Trigger = 29U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Trigger = 30U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Trigger = 31U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer2Trigger = 32U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer2Trigger = 33U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer2Trigger = 34U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer2Trigger = 35U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer2Trigger = 36U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer2Trigger = 37U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer2Trigger = 40U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer2Trigger = 41U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer2Trigger = 42U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer2Trigger = 43U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Trigger = 44U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Trigger = 45U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Trigger = 46U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer2Trigger = 47U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Trigger = 48U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Trigger = 49U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer2Trigger = 50U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer2Trigger = 51U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer2Trigger = 52U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Trigger = 53U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer2Trigger = 54U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Trigger = 55U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Trigger = 56U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Trigger = 57U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Trigger = 58U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Trigger = 59U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Trigger = 60U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Trigger = 61U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Trigger = 62U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Trigger = 63U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Trigger = 64U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Trigger = 65U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Trigger = 66U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Trigger = 67U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Trigger = 68U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Trigger = 69U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Trigger = 70U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer2Trigger = 71U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer2Trigger = 72U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer2Trigger = 73U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer2Trigger = 74U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer2Trigger = 75U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer2Trigger = 76U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer2Trigger = 77U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer2Trigger = 78U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer2Trigger = 79U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer2Trigger = 80U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer2Trigger = 81U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer2Trigger = 82U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer2Trigger = 83U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer2Trigger = 84U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer2Trigger = 85U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer2Trigger = 86U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer2Trigger = 87U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer2Trigger = 88U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer2Trigger = 89U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Trigger = 90U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Trigger = 91U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Trigger = 92U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer2Trigger = 93U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Trigger = 94U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Trigger = 95U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Trigger = 96U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Trigger = 97U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer2Trigger = 98U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer2Trigger = 99U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer2Trigger = 100U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer2Trigger = 105U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer2Trigger = 106U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer2Trigger = 107U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer2Trigger = 108U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer2Trigger = 109U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer2Trigger = 110U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer2Trigger = 111U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer2Trigger = 112U + (TIMER2TRIGIN << PMUX_SHIFT), + + /*!< TIMER3 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer3Trigger = 1U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Trigger = 2U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Trigger = 3U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Trigger = 4U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Trigger = 5U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Trigger = 6U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Trigger = 7U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Trigger = 8U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Trigger = 9U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Trigger = 10U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Trigger = 11U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Trigger = 12U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Trigger = 13U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Trigger = 14U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Trigger = 15U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Trigger = 16U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Trigger = 17U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Trigger = 18U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Trigger = 19U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Trigger = 20U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Trigger = 21U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer3Trigger = 22U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer3Trigger = 23U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer3Trigger = 24U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer3Trigger = 25U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer3Trigger = 26U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer3Trigger = 27U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer3Trigger = 28U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer3Trigger = 29U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Trigger = 30U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Trigger = 31U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer3Trigger = 32U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer3Trigger = 33U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer3Trigger = 34U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer3Trigger = 35U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer3Trigger = 36U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer3Trigger = 37U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer3Trigger = 40U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer3Trigger = 41U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer3Trigger = 42U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer3Trigger = 43U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Trigger = 44U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Trigger = 45U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Trigger = 46U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer3Trigger = 47U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Trigger = 48U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Trigger = 49U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer3Trigger = 50U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer3Trigger = 51U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer3Trigger = 52U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Trigger = 53U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer3Trigger = 54U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Trigger = 55U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Trigger = 56U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Trigger = 57U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Trigger = 58U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Trigger = 59U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Trigger = 60U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Trigger = 61U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Trigger = 62U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Trigger = 63U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Trigger = 64U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Trigger = 65U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Trigger = 66U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Trigger = 67U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Trigger = 68U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Trigger = 69U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Trigger = 70U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer3Trigger = 71U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer3Trigger = 72U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer3Trigger = 73U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer3Trigger = 74U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer3Trigger = 75U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer3Trigger = 76U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer3Trigger = 77U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer3Trigger = 78U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer3Trigger = 79U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer3Trigger = 80U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer3Trigger = 81U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer3Trigger = 82U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer3Trigger = 83U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer3Trigger = 84U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer3Trigger = 85U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer3Trigger = 86U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer3Trigger = 87U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer3Trigger = 88U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer3Trigger = 89U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Trigger = 90U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Trigger = 91U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Trigger = 92U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer3Trigger = 93U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Trigger = 94U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Trigger = 95U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Trigger = 96U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Trigger = 97U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer3Trigger = 98U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer3Trigger = 99U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer3Trigger = 100U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer3Trigger = 105U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer3Trigger = 106U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer3Trigger = 107U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer3Trigger = 108U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer3Trigger = 109U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer3Trigger = 110U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer3Trigger = 111U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer3Trigger = 112U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToTimer3Trigger = 113U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToTimer3Trigger = 114U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToTimer3Trigger = 115U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToTimer3Trigger = 116U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToTimer3Trigger = 117U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToTimer3Trigger = 118U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToTimer3Trigger = 119U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToTimer3Trigger = 120U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToTimer3Trigger = 121U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToTimer3Trigger = 122U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToTimer3Trigger = 123U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToTimer3Trigger = 124U + (TIMER3TRIGIN << PMUX_SHIFT), + + /*!< TIMER4 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer4Trigger = 1U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Trigger = 2U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Trigger = 3U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Trigger = 4U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Trigger = 5U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Trigger = 6U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Trigger = 7U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Trigger = 8U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Trigger = 9U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Trigger = 10U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Trigger = 11U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Trigger = 12U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Trigger = 13U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Trigger = 14U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Trigger = 15U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Trigger = 16U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Trigger = 17U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Trigger = 18U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Trigger = 19U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Trigger = 20U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Trigger = 21U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer4Trigger = 22U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer4Trigger = 23U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer4Trigger = 24U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer4Trigger = 25U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer4Trigger = 26U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer4Trigger = 27U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer4Trigger = 28U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer4Trigger = 29U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Trigger = 30U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Trigger = 31U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToTimer4Trigger = 32U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer4Trigger = 33U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer4Trigger = 34U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer4Trigger = 35U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer4Trigger = 36U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer4Trigger = 37U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer4Trigger = 40U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer4Trigger = 41U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer4Trigger = 42U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer4Trigger = 43U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Trigger = 44U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Trigger = 45U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Trigger = 46U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToTimer4Trigger = 47U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Trigger = 48U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Trigger = 49U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToTimer4Trigger = 50U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToTimer4Trigger = 51U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer4Trigger = 52U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Trigger = 53U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer4Trigger = 54U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Trigger = 55U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Trigger = 56U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Trigger = 57U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Trigger = 58U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Trigger = 59U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Trigger = 60U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Trigger = 61U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Trigger = 62U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Trigger = 63U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Trigger = 64U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Trigger = 65U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Trigger = 66U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Trigger = 67U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Trigger = 68U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Trigger = 69U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Trigger = 70U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer4Trigger = 71U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer4Trigger = 72U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer4Trigger = 73U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer4Trigger = 74U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer4Trigger = 75U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer4Trigger = 76U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer4Trigger = 77U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer4Trigger = 78U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer4Trigger = 79U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer4Trigger = 80U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer4Trigger = 81U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer4Trigger = 82U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer4Trigger = 83U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer4Trigger = 84U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer4Trigger = 85U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer4Trigger = 86U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer4Trigger = 87U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer4Trigger = 88U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer4Trigger = 89U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Trigger = 90U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Trigger = 91U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Trigger = 92U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToTimer4Trigger = 93U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Trigger = 94U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Trigger = 95U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Trigger = 96U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Trigger = 97U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceivedDataWordToTimer4Trigger = 98U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5TransmittedDataWordToTimer4Trigger = 99U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart5ReceiveLineIdleToTimer4Trigger = 100U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToTimer4Trigger = 105U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToTimer4Trigger = 106U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToTimer4Trigger = 107U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToTimer4Trigger = 108U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToTimer4Trigger = 109U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToTimer4Trigger = 110U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToTimer4Trigger = 111U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToTimer4Trigger = 112U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToTimer4Trigger = 113U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToTimer4Trigger = 114U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToTimer4Trigger = 115U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToTimer4Trigger = 116U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToTimer4Trigger = 117U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToTimer4Trigger = 118U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToTimer4Trigger = 119U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToTimer4Trigger = 120U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToTimer4Trigger = 121U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToTimer4Trigger = 122U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToTimer4Trigger = 123U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToTimer4Trigger = 124U + (TIMER4TRIGIN << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_ClkInToFreqmeasRef = 1U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc12MToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FroHfDivToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Clk16K1ToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_SlowClkToFreqmeasRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasRef = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFreqmeasRef = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFreqmeasRef = 10u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasRef = 11u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasRef = 12u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasRef = 13u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasRef = 14u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasRef = 15u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasRef = 16u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFreqmeasRef = 17u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFreqmeasRef = 18u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFreqmeasRef = 32u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFreqmeasRef = 33u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFreqmeasRef = 34u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFreqmeasRef = 35u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFreqmeasRef = 36u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFreqmeasRef = 37u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFreqmeasRef = 38u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFreqmeasRef = 39u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFreqmeasRef = 40u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFreqmeasRef = 41u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_ClkInToFreqmeasTar = 1U + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc12MToFreqmeasTar = 2u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FroHfDivToFreqmeasTar = 3u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Clk16K1ToFreqmeasTar = 5u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_SlowClkToFreqmeasTar = 6u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasTar = 7u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasTar = 8u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFreqmeasTar = 9u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFreqmeasTar = 10u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasTar = 11u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasTar = 12u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasTar = 13u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasTar = 14u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasTar = 15u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasTar = 16u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFreqmeasTar = 17u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFreqmeasTar = 18u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFreqmeasTar = 32u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFreqmeasTar = 33u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFreqmeasTar = 34u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFreqmeasTar = 35u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFreqmeasTar = 36u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFreqmeasTar = 37u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFreqmeasTar = 38u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFreqmeasTar = 39u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFreqmeasTar = 40u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFreqmeasTar = 41u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + + /*!< Cmp0 Trigger. */ + kINPUTMUX_Aoi0Out0ToCmp0Trigger = 2U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToCmp0Trigger = 3U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToCmp0Trigger = 4U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToCmp0Trigger = 5U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToCmp0Trigger = 6U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToCmp0Trigger = 7U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp0Trigger = 8U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToCmp0Trigger = 9U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToCmp0Trigger = 10U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToCmp0Trigger = 11U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToCmp0Trigger = 12U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToCmp0Trigger = 13U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp0Trigger = 14U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToCmp0Trigger = 16U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToCmp0Trigger = 17U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToCmp0Trigger = 18U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToCmp0Trigger = 19U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToCmp0Trigger = 20U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToCmp0Trigger = 21U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToCmp0Trigger = 22U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToCmp0Trigger = 23U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToCmp0Trigger = 24U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp0Trigger = 27U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp0Trigger = 28U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToCmp0Trigger = 29U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToCmp0Trigger = 30U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToCmp0Trigger = 31U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToCmp0Trigger = 32U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToCmp0Trigger = 33U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToCmp0Trigger = 34U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToCmp0Trigger = 39U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp0Trigger = 40U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp0Trigger = 41U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp0Trigger = 42U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToCmp0Trigger = 47U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToCmp0Trigger = 48U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToCmp0Trigger = 49U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToCmp0Trigger = 50U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToCmp0Trigger = 51U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToCmp0Trigger = 52U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToCmp0Trigger = 53U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToCmp0Trigger = 54U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToCmp0Trigger = 55U + (CMP0_TRIG_REG << PMUX_SHIFT), + + /*!< Cmp1 Trigger. */ + kINPUTMUX_Aoi0Out0ToCmp1Trigger = 2U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToCmp1Trigger = 3U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToCmp1Trigger = 4U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToCmp1Trigger = 5U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToCmp1Trigger = 6U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToCmp1Trigger = 7U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp1Trigger = 8U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToCmp1Trigger = 9U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToCmp1Trigger = 10U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToCmp1Trigger = 11U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToCmp1Trigger = 12U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToCmp1Trigger = 13U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp1Trigger = 14U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToCmp1Trigger = 16U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToCmp1Trigger = 17U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToCmp1Trigger = 18U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToCmp1Trigger = 19U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToCmp1Trigger = 20U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToCmp1Trigger = 21U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToCmp1Trigger = 22U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToCmp1Trigger = 23U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToCmp1Trigger = 24U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp1Trigger = 27U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp1Trigger = 28U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToCmp1Trigger = 29U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToCmp1Trigger = 30U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToCmp1Trigger = 31U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToCmp1Trigger = 32U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToCmp1Trigger = 33U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToCmp1Trigger = 34U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToCmp1Trigger = 39U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp1Trigger = 40U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp1Trigger = 41U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp1Trigger = 42U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToCmp1Trigger = 47U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToCmp1Trigger = 48U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToCmp1Trigger = 49U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToCmp1Trigger = 50U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToCmp1Trigger = 51U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToCmp1Trigger = 52U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToCmp1Trigger = 53U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToCmp1Trigger = 54U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToCmp1Trigger = 55U + (CMP1_TRIG_REG << PMUX_SHIFT), + + /*!< Cmp2 Trigger. */ + kINPUTMUX_Aoi0Out0ToCmp2Trigger = 2U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToCmp2Trigger = 3U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToCmp2Trigger = 4U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToCmp2Trigger = 5U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToCmp2Trigger = 6U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToCmp2Trigger = 7U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp2Trigger = 8U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToCmp2Trigger = 9U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToCmp2Trigger = 10U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToCmp2Trigger = 11U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToCmp2Trigger = 12U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToCmp2Trigger = 13U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp2Trigger = 14U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToCmp2Trigger = 16U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToCmp2Trigger = 17U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToCmp2Trigger = 18U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToCmp2Trigger = 19U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToCmp2Trigger = 20U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToCmp2Trigger = 21U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToCmp2Trigger = 22U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToCmp2Trigger = 23U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToCmp2Trigger = 24U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToCmp2Trigger = 25U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToCmp2Trigger = 26U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp2Trigger = 27U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp2Trigger = 28U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToCmp2Trigger = 29U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToCmp2Trigger = 30U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToCmp2Trigger = 31U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToCmp2Trigger = 32U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToCmp2Trigger = 33U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToCmp2Trigger = 34U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToCmp2Trigger = 39U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp2Trigger = 40U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp2Trigger = 41U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp2Trigger = 42U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToCmp2Trigger = 47U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToCmp2Trigger = 48U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToCmp2Trigger = 49U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToCmp2Trigger = 50U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToCmp2Trigger = 51U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToCmp2Trigger = 52U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToCmp2Trigger = 53U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToCmp2Trigger = 54U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToCmp2Trigger = 55U + (CMP2_TRIG_REG << PMUX_SHIFT), + + /*!< Adc0 Trigger. */ + kINPUTMUX_ArmTxevToAdc0Trigger = 1U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc0Trigger = 2U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc0Trigger = 3U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc0Trigger = 4U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc0Trigger = 5U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc0Trigger = 6U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc0Trigger = 7U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAdc0Trigger = 7U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc0Trigger = 9U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc0Trigger = 10U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc0Trigger = 11U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc0Trigger = 12U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc0Trigger = 13U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc0Trigger = 14U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc0Trigger = 15U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc0Trigger = 17U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc0Trigger = 18U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc0Trigger = 19U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc0Trigger = 20U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc0Trigger = 21U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc0Trigger = 22U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc0Trigger = 23U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAdc0Trigger = 24U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAdc0Trigger = 25U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc0Trigger = 26U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc0Trigger = 27U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc0Trigger = 28U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc0Trigger = 29U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc0Trigger = 30U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc0Trigger = 31U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc0Trigger = 33U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc0Trigger = 34U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc0Trigger = 35U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc0Trigger = 36U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc0Trigger = 37U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc0Trigger = 38U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc0Trigger = 39U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc0Trigger = 40U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc0Trigger = 41U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc0Trigger = 42U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc0Trigger = 43U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc0Trigger = 44U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc0Trigger = 45U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc0Trigger = 46U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc0Trigger = 47U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc0Trigger = 48U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc0Trigger = 49U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc0Trigger = 50U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc0Trigger = 51U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc0Trigger = 52U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc0Trigger = 53U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc0Trigger = 54U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc0Trigger = 55U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAdc0Trigger = 56U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAdc0Trigger = 57U + (ADC0_TRIG0_REG << PMUX_SHIFT), + + /*!< Adc1 Trigger. */ + kINPUTMUX_ArmTxevToAdc1Trigger = 1U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc1Trigger = 2U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc1Trigger = 3U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc1Trigger = 4U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc1Trigger = 5U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc1Trigger = 6U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc1Trigger = 7U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAdc1Trigger = 7U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc1Trigger = 9U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc1Trigger = 10U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc1Trigger = 11U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc1Trigger = 12U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc1Trigger = 13U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc1Trigger = 14U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc1Trigger = 15U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc1Trigger = 17U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc1Trigger = 18U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc1Trigger = 19U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc1Trigger = 20U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc1Trigger = 21U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc1Trigger = 22U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc1Trigger = 23U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAdc1Trigger = 24U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAdc1Trigger = 25U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc1Trigger = 26U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc1Trigger = 27U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc1Trigger = 28U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc1Trigger = 29U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc1Trigger = 30U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc1Trigger = 31U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc1Trigger = 33U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc1Trigger = 34U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc1Trigger = 35U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc1Trigger = 36U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc1Trigger = 37U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc1Trigger = 38U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc1Trigger = 39U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc1Trigger = 40U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc1Trigger = 41U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc1Trigger = 42U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc1Trigger = 43U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc1Trigger = 44U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc1Trigger = 45U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc1Trigger = 46U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc1Trigger = 47U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc1Trigger = 48U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc1Trigger = 49U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc1Trigger = 50U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc1Trigger = 51U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc1Trigger = 52U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc1Trigger = 53U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc1Trigger = 54U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc1Trigger = 55U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAdc1Trigger = 56U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAdc1Trigger = 57U + (ADC1_TRIG0_REG << PMUX_SHIFT), + + /*!< Adc2 Trigger. */ + kINPUTMUX_ArmTxevToAdc2Trigger = 1U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc2Trigger = 2U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc2Trigger = 3U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc2Trigger = 4U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc2Trigger = 5U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc2Trigger = 6U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc2Trigger = 7U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAdc2Trigger = 7U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc2Trigger = 9U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc2Trigger = 10U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc2Trigger = 11U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc2Trigger = 12U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc2Trigger = 13U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc2Trigger = 14U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc2Trigger = 15U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc2Trigger = 17U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc2Trigger = 18U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc2Trigger = 19U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc2Trigger = 20U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc2Trigger = 21U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc2Trigger = 22U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc2Trigger = 23U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAdc2Trigger = 24U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAdc2Trigger = 25U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc2Trigger = 26U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc2Trigger = 27U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc2Trigger = 28U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc2Trigger = 29U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc2Trigger = 30U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc2Trigger = 31U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc2Trigger = 33U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc2Trigger = 34U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc2Trigger = 35U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc2Trigger = 36U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc2Trigger = 37U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc2Trigger = 38U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc2Trigger = 39U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc2Trigger = 40U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc2Trigger = 41U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc2Trigger = 42U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc2Trigger = 43U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc2Trigger = 44U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc2Trigger = 45U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc2Trigger = 46U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc2Trigger = 47U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc2Trigger = 48U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc2Trigger = 49U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc2Trigger = 50U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc2Trigger = 51U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc2Trigger = 52U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc2Trigger = 53U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc2Trigger = 54U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc2Trigger = 55U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAdc2Trigger = 56U + (ADC2_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAdc2Trigger = 57U + (ADC2_TRIG0_REG << PMUX_SHIFT), + + /*!< Adc3 Trigger. */ + kINPUTMUX_ArmTxevToAdc3Trigger = 1U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc3Trigger = 2U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc3Trigger = 3U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc3Trigger = 4U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc3Trigger = 5U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc3Trigger = 6U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc3Trigger = 7U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAdc3Trigger = 7U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc3Trigger = 9U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc3Trigger = 10U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc3Trigger = 11U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc3Trigger = 12U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc3Trigger = 13U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc3Trigger = 14U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc3Trigger = 15U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc3Trigger = 17U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc3Trigger = 18U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc3Trigger = 19U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc3Trigger = 20U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc3Trigger = 21U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc3Trigger = 22U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc3Trigger = 23U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAdc3Trigger = 24U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAdc3Trigger = 25U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc3Trigger = 26U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc3Trigger = 27U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc3Trigger = 28U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc3Trigger = 29U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc3Trigger = 30U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc3Trigger = 31U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc3Trigger = 33U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc3Trigger = 34U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc3Trigger = 35U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc3Trigger = 36U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc3Trigger = 37U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc3Trigger = 38U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc3Trigger = 39U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc3Trigger = 40U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc3Trigger = 41U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc3Trigger = 42U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc3Trigger = 43U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc3Trigger = 44U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc3Trigger = 45U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc3Trigger = 46U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc3Trigger = 47U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc3Trigger = 48U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc3Trigger = 49U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc3Trigger = 50U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc3Trigger = 51U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc3Trigger = 52U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc3Trigger = 53U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc3Trigger = 54U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc3Trigger = 55U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAdc3Trigger = 56U + (ADC3_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAdc3Trigger = 57U + (ADC3_TRIG0_REG << PMUX_SHIFT), + + /*!< Dac0 Trigger. */ + kINPUTMUX_ArmTxevToDac0Trigger = 1U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToDac0Trigger = 2U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToDac0Trigger = 3U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToDac0Trigger = 4U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToDac0Trigger = 5U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToDac0Trigger = 6U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToDac0Trigger = 7U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToDac0Trigger = 8U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDac0Trigger = 9U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDac0Trigger = 10U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDac0Trigger = 11U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToDac0Trigger = 12U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDac0Trigger = 13U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDac0Trigger = 14U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToDac0Trigger = 15U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToDac0Trigger = 18U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToDac0Trigger = 19U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToDac0Trigger = 20U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToDac0Trigger = 21U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToDac0Trigger = 26U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToDac0Trigger = 27U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToDac0Trigger = 28U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToDac0Trigger = 29U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToDac0Trigger = 30U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToDac0Trigger = 31U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToDac0Trigger = 33U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToDac0Trigger = 34U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToDac0Trigger = 35U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToDac0Trigger = 36U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToDac0Trigger = 37U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToDac0Trigger = 38U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToDac0Trigger = 39U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToDac0Trigger = 40U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDac0Trigger = 41U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToDac0Trigger = 42U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDac0Trigger = 43U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDac0Trigger = 44U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToDac0Trigger = 50U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToDac0Trigger = 51U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToDac0Trigger = 52U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToDac0Trigger = 55U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToDac0Trigger = 57U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToDac0Trigger = 58U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToDac0Trigger = 59U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToDac0Trigger = 60U + (DAC0_TRIG0_REG << PMUX_SHIFT), + + /*!< Qdc0 Trigger. */ + kINPUTMUX_ArmTxevToQdc0Trigger = 1U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Trigger = 2U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Trigger = 3U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Trigger = 4U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Trigger = 5U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Trigger = 6U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Trigger = 7U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Trigger = 8U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Trigger = 9U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Trigger = 10U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Trigger = 11U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Trigger = 12U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Trigger = 13U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Trigger = 14U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Trigger = 16U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Trigger = 17U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Trigger = 18U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Trigger = 19U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Trigger = 20U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Trigger = 21U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Trigger = 22U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Trigger = 23U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Trigger = 24U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Trigger = 25U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Trigger = 26U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Trigger = 27U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Trigger = 28U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Trigger = 29U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Trigger = 30U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Trigger = 31U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Trigger = 32U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Trigger = 33U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Trigger = 34U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Trigger = 35U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Trigger = 36U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Trigger = 37U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Trigger = 38U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Trigger = 39U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Trigger = 40U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Trigger = 41U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Trigger = 42U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Trigger = 43U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Trigger = 44U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Trigger = 49U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Trigger = 50U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Trigger = 51U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Trigger = 52U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Trigger = 62U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Trigger = 63U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Trigger = 64U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Trigger = 65U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Trigger = 66U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Trigger = 67U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Trigger = 68U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Trigger = 69U + (QDC0_TRIG_REG << PMUX_SHIFT), + + /*!< Qdc0 Home. */ + kINPUTMUX_ArmTxevToQdc0Home = 1U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Home = 2U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Home = 3U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Home = 4U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Home = 5U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Home = 6U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Home = 7U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Home = 8U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Home = 9U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Home = 10U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Home = 11U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Home = 12U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Home = 13U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Home = 14U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Home = 16U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Home = 17U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Home = 18U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Home = 19U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Home = 20U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Home = 21U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Home = 22U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Home = 23U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Home = 24U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Home = 25U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Home = 26U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Home = 27U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Home = 28U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Home = 29U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Home = 30U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Home = 31U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Home = 32U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Home = 33U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Home = 34U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Home = 35U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Home = 36U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Home = 37U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Home = 38U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Home = 39U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Home = 40U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Home = 41U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Home = 42U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Home = 43U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Home = 44U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Home = 49U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Home = 50U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Home = 51U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Home = 52U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Home = 62U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Home = 63U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Home = 64U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Home = 65U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Home = 66U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Home = 67U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Home = 68U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Home = 69U + (QDC0_HOME_REG << PMUX_SHIFT), + + /*!< Qdc0 Index. */ + kINPUTMUX_ArmTxevToQdc0Index = 1U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Index = 2U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Index = 3U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Index = 4U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Index = 5U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Index = 6U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Index = 7U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Index = 8U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Index = 9U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Index = 10U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Index = 11U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Index = 12U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Index = 13U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Index = 14U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Index = 16U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Index = 17U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Index = 18U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Index = 19U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Index = 20U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Index = 21U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Index = 22U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Index = 23U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Index = 24U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Index = 25U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Index = 26U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Index = 27U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Index = 28U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Index = 29U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Index = 30U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Index = 31U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Index = 32U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Index = 33U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Index = 34U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Index = 35U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Index = 36U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Index = 37U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Index = 38U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Index = 39U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Index = 40U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Index = 41U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Index = 42U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Index = 43U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Index = 44U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Index = 49U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Index = 50U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Index = 51U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Index = 52U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Index = 62U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Index = 63U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Index = 64U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Index = 65U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Index = 66U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Index = 67U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Index = 68U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Index = 69U + (QDC0_INDEX_REG << PMUX_SHIFT), + + /*!< Qdc0 Phaseb. */ + kINPUTMUX_ArmTxevToQdc0Phaseb = 1U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Phaseb = 2U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Phaseb = 3U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Phaseb = 4U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Phaseb = 5U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phaseb = 6U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phaseb = 7U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Phaseb = 8U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Phaseb = 9U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phaseb = 10U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Phaseb = 11U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phaseb = 12U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Phaseb = 13U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phaseb = 14U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phaseb = 16U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phaseb = 17U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phaseb = 18U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phaseb = 19U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phaseb = 20U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phaseb = 21U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Phaseb = 22U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Phaseb = 23U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phaseb = 24U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phaseb = 25U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phaseb = 26U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phaseb = 27U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phaseb = 28U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phaseb = 29U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phaseb = 30U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phaseb = 31U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phaseb = 32U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phaseb = 33U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Phaseb = 34U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Phaseb = 35U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phaseb = 36U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phaseb = 37U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phaseb = 38U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phaseb = 39U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phaseb = 40U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Phaseb = 41U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Phaseb = 42U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Phaseb = 43U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Phaseb = 44U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Phaseb = 49U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Phaseb = 50U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Phaseb = 51U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Phaseb = 52U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phaseb = 62U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phaseb = 63U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phaseb = 64U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phaseb = 65U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phaseb = 66U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phaseb = 67U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Phaseb = 68U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Phaseb = 69U + (QDC0_PHASEB_REG << PMUX_SHIFT), + + /*!< Qdc0 Phasea. */ + kINPUTMUX_ArmTxevToQdc0Phasea = 1U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Phasea = 2U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Phasea = 3U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Phasea = 4U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Phasea = 5U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phasea = 6U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phasea = 7U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Phasea = 8U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Phasea = 9U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phasea = 10U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Phasea = 11U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phasea = 12U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Phasea = 13U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phasea = 14U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phasea = 16U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phasea = 17U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phasea = 18U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phasea = 19U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phasea = 20U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phasea = 21U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Phasea = 22U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Phasea = 23U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phasea = 24U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phasea = 25U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phasea = 26U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phasea = 27U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phasea = 28U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phasea = 29U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phasea = 30U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phasea = 31U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phasea = 32U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phasea = 33U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Phasea = 34U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Phasea = 35U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phasea = 36U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phasea = 37U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phasea = 38U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phasea = 39U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phasea = 40U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Phasea = 41U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Phasea = 42U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Phasea = 43U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Phasea = 44U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Phasea = 49U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Phasea = 50U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Phasea = 51U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Phasea = 52U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phasea = 62U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phasea = 63U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phasea = 64U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phasea = 65U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phasea = 66U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phasea = 67U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Phasea = 68U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Phasea = 69U + (QDC0_PHASEA_REG << PMUX_SHIFT), + + /*!< Qdc0 Icap1-3. */ + kINPUTMUX_ArmTxevToQdc0Icap1 = 1U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Icap1 = 2U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Icap1 = 3U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Icap1 = 4U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Icap1 = 5U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Icap1 = 6U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Icap1 = 7U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Icap1 = 8U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Icap1 = 9U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Icap1 = 10U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Icap1 = 11U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Icap1 = 12U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Icap1 = 13U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Icap1 = 14U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Icap1 = 16U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Icap1 = 17U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Icap1 = 18U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Icap1 = 19U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Icap1 = 20U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Icap1 = 21U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc0Icap1 = 22U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc0Icap1 = 23U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Icap1 = 24U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Icap1 = 25U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Icap1 = 26U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Icap1 = 27U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Icap1 = 28U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Icap1 = 29U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Icap1 = 30U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Icap1 = 31U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Icap1 = 32U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Icap1 = 33U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Icap1 = 34U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Icap1 = 35U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Icap1 = 36U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Icap1 = 37U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Icap1 = 38U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Icap1 = 39U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Icap1 = 40U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Icap1 = 41U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Icap1 = 42U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Icap1 = 43U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Icap1 = 44U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Icap1 = 49U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Icap1 = 50U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Icap1 = 51U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Icap1 = 52U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Icap1 = 62U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Icap1 = 63U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Icap1 = 64U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Icap1 = 65U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Icap1 = 66U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Icap1 = 67U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc0Icap1 = 68U + (QDC0_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc0Icap1 = 69U + (QDC0_ICAP0_REG << PMUX_SHIFT), + + /*!< Qdc1 Trigger. */ + kINPUTMUX_ArmTxevToQdc1Trigger = 1U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Trigger = 2U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Trigger = 3U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Trigger = 4U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Trigger = 5U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Trigger = 6U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Trigger = 7U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Trigger = 8U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Trigger = 9U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Trigger = 10U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Trigger = 11U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Trigger = 12U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Trigger = 13U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Trigger = 14U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Trigger = 16U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Trigger = 17U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Trigger = 18U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Trigger = 19U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Trigger = 20U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Trigger = 21U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Trigger = 22U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Trigger = 23U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Trigger = 24U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Trigger = 25U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Trigger = 26U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Trigger = 27U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Trigger = 28U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Trigger = 29U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Trigger = 30U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Trigger = 31U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Trigger = 32U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Trigger = 33U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Trigger = 34U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Trigger = 35U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Trigger = 36U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Trigger = 37U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Trigger = 38U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Trigger = 39U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Trigger = 40U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Trigger = 41U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Trigger = 42U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Trigger = 43U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Trigger = 44U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Trigger = 49U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Trigger = 50U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Trigger = 51U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Trigger = 52U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Trigger = 62U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Trigger = 63U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Trigger = 64U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Trigger = 65U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Trigger = 66U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Trigger = 67U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Trigger = 68U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Trigger = 69U + (QDC1_TRIG_REG << PMUX_SHIFT), + + /*!< Qdc1 Home. */ + kINPUTMUX_ArmTxevToQdc1Home = 1U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Home = 2U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Home = 3U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Home = 4U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Home = 5U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Home = 6U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Home = 7U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Home = 8U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Home = 9U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Home = 10U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Home = 11U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Home = 12U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Home = 13U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Home = 14U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Home = 16U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Home = 17U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Home = 18U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Home = 19U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Home = 20U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Home = 21U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Home = 22U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Home = 23U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Home = 24U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Home = 25U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Home = 26U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Home = 27U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Home = 28U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Home = 29U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Home = 30U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Home = 31U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Home = 32U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Home = 33U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Home = 34U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Home = 35U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Home = 36U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Home = 37U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Home = 38U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Home = 39U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Home = 40U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Home = 41U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Home = 42U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Home = 43U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Home = 44U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Home = 49U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Home = 50U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Home = 51U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Home = 52U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Home = 62U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Home = 63U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Home = 64U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Home = 65U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Home = 66U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Home = 67U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Home = 68U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Home = 69U + (QDC1_HOME_REG << PMUX_SHIFT), + + /*!< Qdc1 Index. */ + kINPUTMUX_ArmTxevToQdc1Index = 1U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Index = 2U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Index = 3U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Index = 4U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Index = 5U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Index = 6U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Index = 7U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Index = 8U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Index = 9U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Index = 10U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Index = 11U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Index = 12U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Index = 13U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Index = 14U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Index = 16U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Index = 17U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Index = 18U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Index = 19U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Index = 20U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Index = 21U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Index = 22U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Index = 23U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Index = 24U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Index = 25U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Index = 26U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Index = 27U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Index = 28U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Index = 29U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Index = 30U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Index = 31U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Index = 32U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Index = 33U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Index = 34U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Index = 35U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Index = 36U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Index = 37U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Index = 38U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Index = 39U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Index = 40U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Index = 41U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Index = 42U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Index = 43U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Index = 44U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Index = 49U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Index = 50U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Index = 51U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Index = 52U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Index = 62U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Index = 63U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Index = 64U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Index = 65U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Index = 66U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Index = 67U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Index = 68U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Index = 69U + (QDC1_INDEX_REG << PMUX_SHIFT), + + /*!< Qdc1 Phaseb. */ + kINPUTMUX_ArmTxevToQdc1Phaseb = 1U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Phaseb = 2U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Phaseb = 3U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Phaseb = 4U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Phaseb = 5U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phaseb = 6U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phaseb = 7U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Phaseb = 8U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Phaseb = 9U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phaseb = 10U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Phaseb = 11U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phaseb = 12U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Phaseb = 13U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phaseb = 14U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phaseb = 16U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phaseb = 17U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phaseb = 18U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phaseb = 19U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phaseb = 20U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phaseb = 21U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Phaseb = 22U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Phaseb = 23U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phaseb = 24U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phaseb = 25U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phaseb = 26U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phaseb = 27U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phaseb = 28U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phaseb = 29U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phaseb = 30U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phaseb = 31U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phaseb = 32U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phaseb = 33U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Phaseb = 34U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Phaseb = 35U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phaseb = 36U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phaseb = 37U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phaseb = 38U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phaseb = 39U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phaseb = 40U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Phaseb = 41U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Phaseb = 42U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Phaseb = 43U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Phaseb = 44U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Phaseb = 49U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Phaseb = 50U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Phaseb = 51U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Phaseb = 52U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phaseb = 62U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phaseb = 63U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phaseb = 64U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phaseb = 65U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phaseb = 66U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phaseb = 67U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Phaseb = 68U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Phaseb = 69U + (QDC1_PHASEB_REG << PMUX_SHIFT), + + /*!< Qdc1 Phasea. */ + kINPUTMUX_ArmTxevToQdc1Phasea = 1U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Phasea = 2U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Phasea = 3U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Phasea = 4U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Phasea = 5U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phasea = 6U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phasea = 7U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Phasea = 8U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Phasea = 9U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phasea = 10U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Phasea = 11U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phasea = 12U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Phasea = 13U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phasea = 14U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phasea = 16U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phasea = 17U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phasea = 18U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phasea = 19U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phasea = 20U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phasea = 21U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Phasea = 22U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Phasea = 23U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phasea = 24U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phasea = 25U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phasea = 26U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phasea = 27U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phasea = 28U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phasea = 29U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phasea = 30U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phasea = 31U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phasea = 32U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phasea = 33U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Phasea = 34U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Phasea = 35U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phasea = 36U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phasea = 37U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phasea = 38U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phasea = 39U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phasea = 40U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Phasea = 41U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Phasea = 42U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Phasea = 43U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Phasea = 44U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Phasea = 49U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Phasea = 50U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Phasea = 51U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Phasea = 52U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phasea = 62U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phasea = 63U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phasea = 64U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phasea = 65U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phasea = 66U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phasea = 67U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Phasea = 68U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Phasea = 69U + (QDC1_PHASEA_REG << PMUX_SHIFT), + + /*!< Qdc1 Icap1-3. */ + kINPUTMUX_ArmTxevToQdc1Icap1 = 1U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Icap1 = 2U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Icap1 = 3U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Icap1 = 4U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Icap1 = 5U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Icap1 = 6U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Icap1 = 7U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Icap1 = 8U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Icap1 = 9U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Icap1 = 10U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Icap1 = 11U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Icap1 = 12U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Icap1 = 13U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Icap1 = 14U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Icap1 = 16U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Icap1 = 17U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Icap1 = 18U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Icap1 = 19U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Icap1 = 20U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Icap1 = 21U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToQdc1Icap1 = 22U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToQdc1Icap1 = 23U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Icap1 = 24U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Icap1 = 25U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Icap1 = 26U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Icap1 = 27U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Icap1 = 28U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Icap1 = 29U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Icap1 = 30U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Icap1 = 31U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Icap1 = 32U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Icap1 = 33U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Icap1 = 34U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Icap1 = 35U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Icap1 = 36U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Icap1 = 37U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Icap1 = 38U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Icap1 = 39U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Icap1 = 40U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Icap1 = 41U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Icap1 = 42U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Icap1 = 43U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Icap1 = 44U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Icap1 = 49U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Icap1 = 50U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Icap1 = 51U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Icap1 = 52U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Icap1 = 62U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Icap1 = 63U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Icap1 = 64U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Icap1 = 65U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Icap1 = 66U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Icap1 = 67U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToQdc1Icap1 = 68U + (QDC1_ICAP0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToQdc1Icap1 = 69U + (QDC1_ICAP0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTA0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm0Exta0 = 1U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Exta0 = 2U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Exta0 = 3U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Exta0 = 4U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Exta0 = 5U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0Exta0 = 6U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0Exta0 = 7U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm0Exta0 = 8U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Exta0 = 9U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Exta0 = 10U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Exta0 = 11U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Exta0 = 12U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Exta0 = 13U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Exta0 = 14U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Exta0 = 15U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Exta0 = 16U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Exta0 = 17U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Exta0 = 18U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Exta0 = 19U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0Exta0 = 20U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0Exta0 = 21U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0Exta0 = 22U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0Exta0 = 23U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0Exta0 = 24U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0Exta0 = 25U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0Exta0 = 26U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0Exta0 = 27U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0Exta0 = 28U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0Exta0 = 29U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm0Exta0 = 30U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm0Exta0 = 31U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Exta0 = 32U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Exta0 = 33U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Exta0 = 34U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Exta0 = 35U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Exta0 = 36U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Exta0 = 37U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Exta0 = 38U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Exta0 = 39U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Exta0 = 40U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Exta0 = 45U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Exta0 = 46U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Exta0 = 47U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Exta0 = 48U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Exta0 = 49U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Exta0 = 50U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Exta0 = 51U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Exta0 = 52U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Exta0 = 53U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Exta0 = 54U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Exta0 = 55U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Exta0 = 56U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Exta0 = 57U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Exta0 = 58U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Exta0 = 59U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm0Exta0 = 60U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm0Exta0 = 61U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTA1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm1Exta1 = 1U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Exta1 = 2U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Exta1 = 3U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Exta1 = 4U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Exta1 = 5U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1Exta1 = 6U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1Exta1 = 7U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm1Exta1 = 8U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Exta1 = 9U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Exta1 = 10U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Exta1 = 11U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Exta1 = 12U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Exta1 = 13U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Exta1 = 14U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Exta1 = 15U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Exta1 = 16U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Exta1 = 17U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Exta1 = 18U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Exta1 = 19U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1Exta1 = 20U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1Exta1 = 21U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1Exta1 = 22U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1Exta1 = 23U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1Exta1 = 24U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1Exta1 = 25U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1Exta1 = 26U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1Exta1 = 27U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1Exta1 = 28U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1Exta1 = 29U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm1Exta1 = 30U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm1Exta1 = 31U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Exta1 = 32U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Exta1 = 33U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Exta1 = 34U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Exta1 = 35U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Exta1 = 36U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Exta1 = 37U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Exta1 = 38U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Exta1 = 39U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Exta1 = 40U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Exta1 = 45U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Exta1 = 46U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Exta1 = 47U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Exta1 = 48U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Exta1 = 49U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Exta1 = 50U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Exta1 = 51U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Exta1 = 52U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Exta1 = 53U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Exta1 = 54U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Exta1 = 55U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Exta1 = 56U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Exta1 = 57U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Exta1 = 58U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Exta1 = 59U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm1Exta1 = 60U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm1Exta1 = 61U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTA2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm2Exta2 = 1U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Exta2 = 2U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Exta2 = 3U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Exta2 = 4U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Exta2 = 5U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2Exta2 = 6U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2Exta2 = 7U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm2Exta2 = 8U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Exta2 = 9U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Exta2 = 10U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Exta2 = 11U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Exta2 = 12U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Exta2 = 13U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Exta2 = 14U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Exta2 = 15U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Exta2 = 16U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Exta2 = 17U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Exta2 = 18U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Exta2 = 19U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2Exta2 = 20U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2Exta2 = 21U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2Exta2 = 22U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2Exta2 = 23U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2Exta2 = 24U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2Exta2 = 25U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2Exta2 = 26U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2Exta2 = 27U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2Exta2 = 28U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2Exta2 = 29U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm2Exta2 = 30U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm2Exta2 = 31U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Exta2 = 32U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Exta2 = 33U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Exta2 = 34U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Exta2 = 35U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Exta2 = 36U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Exta2 = 37U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Exta2 = 38U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Exta2 = 39U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Exta2 = 40U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Exta2 = 45U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Exta2 = 46U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Exta2 = 47U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Exta2 = 48U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Exta2 = 49U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Exta2 = 50U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Exta2 = 51U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Exta2 = 52U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Exta2 = 53U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Exta2 = 54U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Exta2 = 55U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Exta2 = 56U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Exta2 = 57U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Exta2 = 58U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Exta2 = 59U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm2Exta2 = 60U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm2Exta2 = 61U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTA3 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm3Exta3 = 1U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm3Exta3 = 2U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm3Exta3 = 3U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm3Exta3 = 4U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm3Exta3 = 5U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3Exta3 = 6U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3Exta3 = 7U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm3Exta3 = 8U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm3Exta3 = 9U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3Exta3 = 10U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm3Exta3 = 11U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3Exta3 = 12U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm3Exta3 = 13U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3Exta3 = 14U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm3Exta3 = 15U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm3Exta3 = 16U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm3Exta3 = 17U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm3Exta3 = 18U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm3Exta3 = 19U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3Exta3 = 20U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3Exta3 = 21U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3Exta3 = 22U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3Exta3 = 23U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3Exta3 = 24U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3Exta3 = 25U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3Exta3 = 26U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3Exta3 = 27U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3Exta3 = 28U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3Exta3 = 29U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm3Exta3 = 30U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm3Exta3 = 31U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm3Exta3 = 32U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm3Exta3 = 33U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3Exta3 = 34U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3Exta3 = 35U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm3Exta3 = 36U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm3Exta3 = 37U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm3Exta3 = 38U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm3Exta3 = 39U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm3Exta3 = 40U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm3Exta3 = 45U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm3Exta3 = 46U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm3Exta3 = 47U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm3Exta3 = 48U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm3Exta3 = 49U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm3Exta3 = 50U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm3Exta3 = 51U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm3Exta3 = 52U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm3Exta3 = 53U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm3Exta3 = 54U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm3Exta3 = 55U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm3Exta3 = 56U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm3Exta3 = 57U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm3Exta3 = 58U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm3Exta3 = 59U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm3Exta3 = 60U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm3Exta3 = 61U + (FlexPWM0_SM3_EXTA3_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTSYNC0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm0Extsync0 = 1U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Extsync0 = 2U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Extsync0 = 3U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Extsync0 = 4U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Extsync0 = 5U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0Extsync0 = 6U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0Extsync0 = 7U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm0Extsync0 = 8U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Extsync0 = 9U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Extsync0 = 10U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Extsync0 = 11U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Extsync0 = 12U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Extsync0 = 13U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Extsync0 = 14U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Extsync0 = 15U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Extsync0 = 16U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Extsync0 = 17U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Extsync0 = 18U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Extsync0 = 19U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0Extsync0 = 20U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0Extsync0 = 21U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0Extsync0 = 22U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0Extsync0 = 23U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0Extsync0 = 24U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0Extsync0 = 25U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0Extsync0 = 26U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0Extsync0 = 27U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0Extsync0 = 28U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0Extsync0 = 29U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm0Extsync0 = 30U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm0Extsync0 = 31U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Extsync0 = 32U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Extsync0 = 33U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Extsync0 = 34U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Extsync0 = 35U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Extsync0 = 36U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Extsync0 = 37U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Extsync0 = 38U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Extsync0 = 39U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Extsync0 = 40U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Extsync0 = 45U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Extsync0 = 46U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Extsync0 = 47U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Extsync0 = 48U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Extsync0 = 49U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Extsync0 = 50U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Extsync0 = 51U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Extsync0 = 52U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Extsync0 = 53U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Extsync0 = 54U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Extsync0 = 55U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Extsync0 = 56U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Extsync0 = 57U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Extsync0 = 58U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Extsync0 = 59U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm0Extsync0 = 60U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm0Extsync0 = 61U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTSYNC1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm1Extsync1 = 1U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Extsync1 = 2U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Extsync1 = 3U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Extsync1 = 4U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Extsync1 = 5U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1Extsync1 = 6U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1Extsync1 = 7U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm1Extsync1 = 8U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Extsync1 = 9U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Extsync1 = 10U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Extsync1 = 11U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Extsync1 = 12U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Extsync1 = 13U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Extsync1 = 14U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Extsync1 = 15U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Extsync1 = 16U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Extsync1 = 17U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Extsync1 = 18U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Extsync1 = 19U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1Extsync1 = 20U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1Extsync1 = 21U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1Extsync1 = 22U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1Extsync1 = 23U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1Extsync1 = 24U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1Extsync1 = 25U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1Extsync1 = 26U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1Extsync1 = 27U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1Extsync1 = 28U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1Extsync1 = 29U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm1Extsync1 = 30U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm1Extsync1 = 31U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Extsync1 = 32U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Extsync1 = 33U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Extsync1 = 34U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Extsync1 = 35U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Extsync1 = 36U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Extsync1 = 37U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Extsync1 = 38U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Extsync1 = 39U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Extsync1 = 40U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Extsync1 = 45U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Extsync1 = 46U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Extsync1 = 47U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Extsync1 = 48U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Extsync1 = 49U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Extsync1 = 50U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Extsync1 = 51U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Extsync1 = 52U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Extsync1 = 53U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Extsync1 = 54U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Extsync1 = 55U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Extsync1 = 56U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Extsync1 = 57U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Extsync1 = 58U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Extsync1 = 59U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm1Extsync1 = 60U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm1Extsync1 = 61U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm2Extsync2 = 1U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Extsync2 = 2U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Extsync2 = 3U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Extsync2 = 4U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Extsync2 = 5U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2Extsync2 = 6U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2Extsync2 = 7U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm2Extsync2 = 8U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Extsync2 = 9U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Extsync2 = 10U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Extsync2 = 11U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Extsync2 = 12U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Extsync2 = 13U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Extsync2 = 14U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Extsync2 = 15U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Extsync2 = 16U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Extsync2 = 17U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Extsync2 = 18U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Extsync2 = 19U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2Extsync2 = 20U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2Extsync2 = 21U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2Extsync2 = 22U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2Extsync2 = 23U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2Extsync2 = 24U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2Extsync2 = 25U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2Extsync2 = 26U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2Extsync2 = 27U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2Extsync2 = 28U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2Extsync2 = 29U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm2Extsync2 = 30U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm2Extsync2 = 31U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Extsync2 = 32U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Extsync2 = 33U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Extsync2 = 34U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Extsync2 = 35U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Extsync2 = 36U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Extsync2 = 37U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Extsync2 = 38U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Extsync2 = 39U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Extsync2 = 40U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Extsync2 = 45U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Extsync2 = 46U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Extsync2 = 47U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Extsync2 = 48U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Extsync2 = 49U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Extsync2 = 50U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Extsync2 = 51U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Extsync2 = 52U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Extsync2 = 53U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Extsync2 = 54U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Extsync2 = 55U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Extsync2 = 56U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Extsync2 = 57U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Extsync2 = 58U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Extsync2 = 59U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm2Extsync2 = 60U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm2Extsync2 = 61U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTSYNC3 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm3Extsync3 = 1U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm3Extsync3 = 2U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm3Extsync3 = 3U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm3Extsync3 = 4U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm3Extsync3 = 5U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3Extsync3 = 6U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3Extsync3 = 7U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Sm3Extsync3 = 8U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm3Extsync3 = 9U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3Extsync3 = 10U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm3Extsync3 = 11U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3Extsync3 = 12U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm3Extsync3 = 13U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3Extsync3 = 14U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm3Extsync3 = 15U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm3Extsync3 = 16U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm3Extsync3 = 17U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm3Extsync3 = 18U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm3Extsync3 = 19U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3Extsync3 = 20U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3Extsync3 = 21U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3Extsync3 = 22U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3Extsync3 = 23U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3Extsync3 = 24U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3Extsync3 = 25U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3Extsync3 = 26U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3Extsync3 = 27U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3Extsync3 = 28U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3Extsync3 = 29U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm3Extsync3 = 30U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm3Extsync3 = 31U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm3Extsync3 = 32U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm3Extsync3 = 33U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3Extsync3 = 34U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3Extsync3 = 35U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm3Extsync3 = 36U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm3Extsync3 = 37U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm3Extsync3 = 38U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm3Extsync3 = 39U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm3Extsync3 = 40U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm3Extsync3 = 45U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm3Extsync3 = 46U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm3Extsync3 = 47U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm3Extsync3 = 48U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm3Extsync3 = 49U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm3Extsync3 = 50U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm3Extsync3 = 51U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm3Extsync3 = 52U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm3Extsync3 = 53U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm3Extsync3 = 54U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm3Extsync3 = 55U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm3Extsync3 = 56U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm3Extsync3 = 57U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm3Extsync3 = 58U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm3Extsync3 = 59U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Sm3Extsync3 = 60U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Sm3Extsync3 = 61U + (FlexPWM0_SM3_EXTSYNC3_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Fault = 1U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Fault = 2U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Fault = 3U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Fault = 4U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Fault = 5U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault = 6U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault = 7U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Fault = 8U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Fault = 9U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault = 10U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Fault = 11U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault = 12U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Fault = 13U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault = 14U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Fault = 15U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Fault = 16U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Fault = 17U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Fault = 18U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Fault = 19U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault = 20U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault = 21U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault = 22U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault = 23U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault = 24U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault = 25U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault = 26U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault = 27U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault = 28U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault = 29U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Fault = 30U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Fault = 31U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Fault = 32U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Fault = 33U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault = 34U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault = 35U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Fault = 36U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Fault = 37U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Fault = 38U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Fault = 39U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Fault = 40U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Fault = 45U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Fault = 46U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Fault = 47U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Fault = 48U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Fault = 49U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Fault = 50U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Fault = 51U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Fault = 52U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Fault = 53U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Fault = 54U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Fault = 55U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Fault = 56U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Fault = 57U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Fault = 58U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Fault = 59U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Fault = 60U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Fault = 61U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FORCE input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Force = 1U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Force = 2U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Force = 3U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Force = 4U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Force = 5U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Force = 6U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Force = 7U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm0Force = 8U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Force = 9U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Force = 10U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Force = 11U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Force = 12U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Force = 13U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Force = 14U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Force = 15U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Force = 16U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Force = 17U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Force = 18U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Force = 19U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Force = 20U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Force = 21U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Force = 22U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Force = 23U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Force = 24U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Force = 25U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Force = 26U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Force = 27U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Force = 28U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Force = 29U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Force = 30U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Force = 31U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Force = 32U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Force = 33U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Force = 34U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Force = 35U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Force = 36U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Force = 37U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Force = 38U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Force = 39U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Force = 40U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Force = 45U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Force = 46U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Force = 47U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Force = 48U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Force = 49U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Force = 50U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Force = 51U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Force = 52U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Force = 53U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Force = 54U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Force = 55U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Force = 56U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Force = 57U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Force = 58U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Force = 59U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexPwm0Force = 60U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToFlexPwm0Force = 61U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTA0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm0Exta0 = 1U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm0Exta0 = 2U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm0Exta0 = 3U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm0Exta0 = 4U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm0Exta0 = 5U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0Exta0 = 6U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0Exta0 = 7U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm0Exta0 = 8U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm0Exta0 = 9U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Exta0 = 10U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm0Exta0 = 11U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Exta0 = 12U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm0Exta0 = 13U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Exta0 = 14U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm0Exta0 = 15U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm0Exta0 = 16U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm0Exta0 = 17U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm0Exta0 = 18U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm0Exta0 = 19U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0Exta0 = 20U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0Exta0 = 21U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0Exta0 = 22U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0Exta0 = 23U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0Exta0 = 24U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0Exta0 = 25U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0Exta0 = 26U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0Exta0 = 27U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0Exta0 = 28U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0Exta0 = 29U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm0Exta0 = 30U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm0Exta0 = 31U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm0Exta0 = 32U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm0Exta0 = 33U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Exta0 = 34U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Exta0 = 35U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm0Exta0 = 36U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm0Exta0 = 37U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm0Exta0 = 38U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm0Exta0 = 39U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm0Exta0 = 40U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm0Exta0 = 45U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm0Exta0 = 46U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm0Exta0 = 47U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm0Exta0 = 48U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm0Exta0 = 49U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm0Exta0 = 50U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm0Exta0 = 51U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm0Exta0 = 52U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm0Exta0 = 53U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm0Exta0 = 54U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm0Exta0 = 55U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm0Exta0 = 56U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm0Exta0 = 57U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm0Exta0 = 58U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm0Exta0 = 59U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm0Exta0 = 60U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm0Exta0 = 61U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTA1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm1Exta1 = 1U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm1Exta1 = 2U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm1Exta1 = 3U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm1Exta1 = 4U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm1Exta1 = 5U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1Exta1 = 6U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1Exta1 = 7U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm1Exta1 = 8U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm1Exta1 = 9U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Exta1 = 10U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm1Exta1 = 11U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Exta1 = 12U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm1Exta1 = 13U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Exta1 = 14U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm1Exta1 = 15U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm1Exta1 = 16U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm1Exta1 = 17U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm1Exta1 = 18U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm1Exta1 = 19U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1Exta1 = 20U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1Exta1 = 21U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1Exta1 = 22U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1Exta1 = 23U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1Exta1 = 24U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1Exta1 = 25U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1Exta1 = 26U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1Exta1 = 27U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1Exta1 = 28U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1Exta1 = 29U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm1Exta1 = 30U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm1Exta1 = 31U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm1Exta1 = 32U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm1Exta1 = 33U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Exta1 = 34U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Exta1 = 35U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm1Exta1 = 36U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm1Exta1 = 37U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm1Exta1 = 38U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm1Exta1 = 39U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm1Exta1 = 40U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm1Exta1 = 45U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm1Exta1 = 46U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm1Exta1 = 47U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm1Exta1 = 48U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm1Exta1 = 49U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm1Exta1 = 50U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm1Exta1 = 51U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm1Exta1 = 52U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm1Exta1 = 53U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm1Exta1 = 54U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm1Exta1 = 55U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm1Exta1 = 56U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm1Exta1 = 57U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm1Exta1 = 58U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm1Exta1 = 59U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm1Exta1 = 60U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm1Exta1 = 61U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTA2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm2Exta2 = 1U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm2Exta2 = 2U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm2Exta2 = 3U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm2Exta2 = 4U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm2Exta2 = 5U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2Exta2 = 6U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2Exta2 = 7U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm2Exta2 = 8U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm2Exta2 = 9U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Exta2 = 10U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm2Exta2 = 11U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Exta2 = 12U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm2Exta2 = 13U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Exta2 = 14U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm2Exta2 = 15U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm2Exta2 = 16U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm2Exta2 = 17U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm2Exta2 = 18U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm2Exta2 = 19U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2Exta2 = 20U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2Exta2 = 21U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2Exta2 = 22U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2Exta2 = 23U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2Exta2 = 24U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2Exta2 = 25U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2Exta2 = 26U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2Exta2 = 27U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2Exta2 = 28U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2Exta2 = 29U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm2Exta2 = 30U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm2Exta2 = 31U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm2Exta2 = 32U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm2Exta2 = 33U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Exta2 = 34U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Exta2 = 35U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm2Exta2 = 36U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm2Exta2 = 37U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm2Exta2 = 38U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm2Exta2 = 39U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm2Exta2 = 40U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm2Exta2 = 45U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm2Exta2 = 46U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm2Exta2 = 47U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm2Exta2 = 48U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm2Exta2 = 49U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm2Exta2 = 50U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm2Exta2 = 51U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm2Exta2 = 52U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm2Exta2 = 53U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm2Exta2 = 54U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm2Exta2 = 55U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm2Exta2 = 56U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm2Exta2 = 57U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm2Exta2 = 58U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm2Exta2 = 59U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm2Exta2 = 60U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm2Exta2 = 61U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTA3 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm3Exta3 = 1U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm3Exta3 = 2U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm3Exta3 = 3U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm3Exta3 = 4U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm3Exta3 = 5U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3Exta3 = 6U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3Exta3 = 7U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm3Exta3 = 8U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm3Exta3 = 9U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Exta3 = 10U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm3Exta3 = 11U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Exta3 = 12U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm3Exta3 = 13U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Exta3 = 14U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm3Exta3 = 15U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm3Exta3 = 16U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm3Exta3 = 17U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm3Exta3 = 18U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm3Exta3 = 19U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3Exta3 = 20U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3Exta3 = 21U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3Exta3 = 22U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3Exta3 = 23U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3Exta3 = 24U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3Exta3 = 25U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3Exta3 = 26U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3Exta3 = 27U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3Exta3 = 28U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3Exta3 = 29U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm3Exta3 = 30U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm3Exta3 = 31U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm3Exta3 = 32U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm3Exta3 = 33U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3Exta3 = 34U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3Exta3 = 35U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm3Exta3 = 36U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm3Exta3 = 37U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm3Exta3 = 38U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm3Exta3 = 39U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm3Exta3 = 40U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm3Exta3 = 45U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm3Exta3 = 46U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm3Exta3 = 47U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm3Exta3 = 48U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm3Exta3 = 49U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm3Exta3 = 50U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm3Exta3 = 51U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm3Exta3 = 52U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm3Exta3 = 53U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm3Exta3 = 54U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm3Exta3 = 55U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm3Exta3 = 56U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm3Exta3 = 57U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm3Exta3 = 58U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm3Exta3 = 59U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm3Exta3 = 60U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm3Exta3 = 61U + (FlexPWM1_SM3_EXTA3_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTSYNC0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm0Extsync0 = 1U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm0Extsync0 = 2U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm0Extsync0 = 3U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm0Extsync0 = 4U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm0Extsync0 = 5U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0Extsync0 = 6U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0Extsync0 = 7U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm0Extsync0 = 8U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm0Extsync0 = 9U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Extsync0 = 10U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm0Extsync0 = 11U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Extsync0 = 12U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm0Extsync0 = 13U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Extsync0 = 14U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm0Extsync0 = 15U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm0Extsync0 = 16U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm0Extsync0 = 17U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm0Extsync0 = 18U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm0Extsync0 = 19U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0Extsync0 = 20U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0Extsync0 = 21U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0Extsync0 = 22U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0Extsync0 = 23U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0Extsync0 = 24U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0Extsync0 = 25U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0Extsync0 = 26U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0Extsync0 = 27U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0Extsync0 = 28U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0Extsync0 = 29U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm0Extsync0 = 30U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm0Extsync0 = 31U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm0Extsync0 = 32U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm0Extsync0 = 33U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Extsync0 = 34U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Extsync0 = 35U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm0Extsync0 = 36U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm0Extsync0 = 37U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm0Extsync0 = 38U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm0Extsync0 = 39U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm0Extsync0 = 40U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm0Extsync0 = 45U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm0Extsync0 = 46U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm0Extsync0 = 47U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm0Extsync0 = 48U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm0Extsync0 = 49U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm0Extsync0 = 50U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm0Extsync0 = 51U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm0Extsync0 = 52U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm0Extsync0 = 53U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm0Extsync0 = 54U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm0Extsync0 = 55U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm0Extsync0 = 56U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm0Extsync0 = 57U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm0Extsync0 = 58U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm0Extsync0 = 59U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm0Extsync0 = 60U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm0Extsync0 = 61U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTSYNC1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm1Extsync1 = 1U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm1Extsync1 = 2U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm1Extsync1 = 3U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm1Extsync1 = 4U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm1Extsync1 = 5U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1Extsync1 = 6U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1Extsync1 = 7U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm1Extsync1 = 8U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm1Extsync1 = 9U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Extsync1 = 10U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm1Extsync1 = 11U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Extsync1 = 12U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm1Extsync1 = 13U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Extsync1 = 14U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm1Extsync1 = 15U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm1Extsync1 = 16U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm1Extsync1 = 17U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm1Extsync1 = 18U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm1Extsync1 = 19U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1Extsync1 = 20U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1Extsync1 = 21U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1Extsync1 = 22U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1Extsync1 = 23U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1Extsync1 = 24U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1Extsync1 = 25U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1Extsync1 = 26U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1Extsync1 = 27U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1Extsync1 = 28U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1Extsync1 = 29U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm1Extsync1 = 30U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm1Extsync1 = 31U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm1Extsync1 = 32U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm1Extsync1 = 33U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Extsync1 = 34U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Extsync1 = 35U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm1Extsync1 = 36U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm1Extsync1 = 37U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm1Extsync1 = 38U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm1Extsync1 = 39U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm1Extsync1 = 40U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm1Extsync1 = 45U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm1Extsync1 = 46U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm1Extsync1 = 47U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm1Extsync1 = 48U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm1Extsync1 = 49U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm1Extsync1 = 50U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm1Extsync1 = 51U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm1Extsync1 = 52U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm1Extsync1 = 53U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm1Extsync1 = 54U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm1Extsync1 = 55U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm1Extsync1 = 56U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm1Extsync1 = 57U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm1Extsync1 = 58U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm1Extsync1 = 59U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm1Extsync1 = 60U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm1Extsync1 = 61U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm2Extsync2 = 1U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm2Extsync2 = 2U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm2Extsync2 = 3U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm2Extsync2 = 4U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm2Extsync2 = 5U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2Extsync2 = 6U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2Extsync2 = 7U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm2Extsync2 = 8U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm2Extsync2 = 9U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Extsync2 = 10U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm2Extsync2 = 11U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Extsync2 = 12U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm2Extsync2 = 13U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Extsync2 = 14U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm2Extsync2 = 15U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm2Extsync2 = 16U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm2Extsync2 = 17U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm2Extsync2 = 18U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm2Extsync2 = 19U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2Extsync2 = 20U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2Extsync2 = 21U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2Extsync2 = 22U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2Extsync2 = 23U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2Extsync2 = 24U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2Extsync2 = 25U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2Extsync2 = 26U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2Extsync2 = 27U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2Extsync2 = 28U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2Extsync2 = 29U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm2Extsync2 = 30U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm2Extsync2 = 31U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm2Extsync2 = 32U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm2Extsync2 = 33U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Extsync2 = 34U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Extsync2 = 35U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm2Extsync2 = 36U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm2Extsync2 = 37U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm2Extsync2 = 38U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm2Extsync2 = 39U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm2Extsync2 = 40U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm2Extsync2 = 45U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm2Extsync2 = 46U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm2Extsync2 = 47U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm2Extsync2 = 48U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm2Extsync2 = 49U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm2Extsync2 = 50U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm2Extsync2 = 51U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm2Extsync2 = 52U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm2Extsync2 = 53U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm2Extsync2 = 54U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm2Extsync2 = 55U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm2Extsync2 = 56U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm2Extsync2 = 57U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm2Extsync2 = 58U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm2Extsync2 = 59U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm2Extsync2 = 60U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm2Extsync2 = 61U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTSYNC3 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm3Extsync3 = 1U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm3Extsync3 = 2U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm3Extsync3 = 3U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm3Extsync3 = 4U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm3Extsync3 = 5U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3Extsync3 = 6U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3Extsync3 = 7U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Sm3Extsync3 = 8U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm3Extsync3 = 9U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Extsync3 = 10U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm3Extsync3 = 11U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Extsync3 = 12U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm3Extsync3 = 13U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Extsync3 = 14U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm3Extsync3 = 15U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm3Extsync3 = 16U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm3Extsync3 = 17U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm3Extsync3 = 18U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm3Extsync3 = 19U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3Extsync3 = 20U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3Extsync3 = 21U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3Extsync3 = 22U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3Extsync3 = 23U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3Extsync3 = 24U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3Extsync3 = 25U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3Extsync3 = 26U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3Extsync3 = 27U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3Extsync3 = 28U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3Extsync3 = 29U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm3Extsync3 = 30U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm3Extsync3 = 31U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm3Extsync3 = 32U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm3Extsync3 = 33U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3Extsync3 = 34U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3Extsync3 = 35U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm3Extsync3 = 36U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm3Extsync3 = 37U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm3Extsync3 = 38U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm3Extsync3 = 39U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm3Extsync3 = 40U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm3Extsync3 = 45U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm3Extsync3 = 46U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm3Extsync3 = 47U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm3Extsync3 = 48U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm3Extsync3 = 49U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm3Extsync3 = 50U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm3Extsync3 = 51U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm3Extsync3 = 52U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm3Extsync3 = 53U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm3Extsync3 = 54U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm3Extsync3 = 55U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm3Extsync3 = 56U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm3Extsync3 = 57U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm3Extsync3 = 58U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm3Extsync3 = 59U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Sm3Extsync3 = 60U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Sm3Extsync3 = 61U + (FlexPWM1_SM3_EXTSYNC3_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Fault = 1U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Fault = 2U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Fault = 3U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Fault = 4U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Fault = 5U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault = 6U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault = 7U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Fault = 8U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Fault = 9U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault = 10U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Fault = 11U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault = 12U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Fault = 13U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault = 14U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Fault = 15U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Fault = 16U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Fault = 17U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Fault = 18U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Fault = 19U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault = 20U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault = 21U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault = 22U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault = 23U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault = 24U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault = 25U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault = 26U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault = 27U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault = 28U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault = 29U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Fault = 30U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Fault = 31U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Fault = 32U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Fault = 33U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault = 34U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault = 35U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Fault = 36U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Fault = 37U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Fault = 38U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Fault = 39U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Fault = 40U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Fault = 45U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Fault = 46U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Fault = 47U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Fault = 48U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Fault = 49U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Fault = 50U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Fault = 51U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Fault = 52U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Fault = 53U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Fault = 54U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Fault = 55U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Fault = 56U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Fault = 57U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Fault = 58U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Fault = 59U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Fault = 60U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Fault = 61U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FORCE input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Force = 1U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Force = 2U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Force = 3U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Force = 4U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Force = 5U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Force = 6U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Force = 7U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexPwm1Force = 8U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Force = 9U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Force = 10U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Force = 11U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Force = 12U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Force = 13U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Force = 14U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Force = 15U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Force = 16U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Force = 17U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Force = 18U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Force = 19U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Force = 20U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Force = 21U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Force = 22U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Force = 23U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Force = 24U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Force = 25U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Force = 26U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Force = 27U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Force = 28U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Force = 29U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Force = 30U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Force = 31U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Force = 32U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Force = 33U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Force = 34U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Force = 35U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Force = 36U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Force = 37U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Force = 38U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Force = 39U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Force = 40U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Force = 45U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Force = 46U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Force = 47U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Force = 48U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Force = 49U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Force = 50U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Force = 51U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Force = 52U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Force = 53U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Force = 54U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Force = 55U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Force = 56U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Force = 57U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Force = 58U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Force = 59U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexPwm1Force = 60U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToFlexPwm1Force = 61U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + + /*!< PWM0 external clock trigger. */ + kINPUTMUX_Clk16K1ToPwm0ExtClk = 1U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ClkInToPwm0ExtClk = 2U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm0ExtClk = 3U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm0ExtClk = 4U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm0ExtClk = 5U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn7ToPwm0ExtClk = 6U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm0ExtClk = 7U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm0ExtClk = 8U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + + /*!< PWM1 external clock trigger. */ + kINPUTMUX_Clk16K1ToPwm1ExtClk = 1U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ClkInToPwm1ExtClk = 2U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm1ExtClk = 3U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm1ExtClk = 4U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm1ExtClk = 5U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn7ToPwm1ExtClk = 6U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm1ExtClk = 7U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm1ExtClk = 8U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + + /*!< AOI0 trigger input connections. */ + kINPUTMUX_Adc0Tcomp0ToAoi0Mux = 1U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAoi0Mux = 2U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAoi0Mux = 3U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAoi0Mux = 4U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAoi0Mux = 5U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAoi0Mux = 6U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAoi0Mux = 7U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAoi0Mux = 8U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAoi0Mux = 9U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToAoi0Mux = 10U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAoi0Mux = 11U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAoi0Mux = 12U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAoi0Mux = 13U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToAoi0Mux = 14U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAoi0Mux = 15U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAoi0Mux = 16U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAoi0Mux = 17U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToAoi0Mux = 18U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAoi0Mux = 19U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAoi0Mux = 20U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToAoi0Mux = 22U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToAoi0Mux = 23U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToAoi0Mux = 24U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToAoi0Mux = 25U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatchToAoi0Mux = 26U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAoi0Mux = 27U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAoi0Mux = 28U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAoi0Mux = 29U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAoi0Mux = 30U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAoi0Mux = 31U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAoi0Mux = 32U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAoi0Mux = 33U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAoi0Mux = 34U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToAoi0Mux = 35U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToAoi0Mux = 36U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToAoi0Mux = 37U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToAoi0Mux = 38U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToAoi0Mux = 39U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToAoi0Mux = 40U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToAoi0Mux = 41U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToAoi0Mux = 42U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToAoi0Mux = 43U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToAoi0Mux = 44U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToAoi0Mux = 45U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToAoi0Mux = 46U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAoi0Mux = 47U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAoi0Mux = 48U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAoi0Mux = 49U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAoi0Mux = 50U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAoi0Mux = 51U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAoi0Mux = 52U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAoi0Mux = 53U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAoi0Mux = 54U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAoi0Mux = 55U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAoi0Mux = 56U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAoi0Mux = 57U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAoi0Mux = 58U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAoi0Mux = 59U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAoi0Mux = 60U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAoi0Mux = 61U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToAoi0Mux = 62U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAoi0Mux = 63U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAoi0Mux = 64U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAoi0Mux = 65U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAoi0Mux = 66U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAoi0Mux = 67U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToAoi0Mux = 68U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToAoi0Mux = 69U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToAoi0Mux = 70U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToAoi0Mux = 71U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatchToAoi0Mux = 72U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAoi0Mux = 73U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAoi0Mux = 74U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAoi0Mux = 75U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAoi0Mux = 76U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAoi0Mux = 77U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAoi0Mux = 78U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAoi0Mux = 79U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAoi0Mux = 80U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0AOutToAoi0Mux = 81U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0BOutToAoi0Mux = 82U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1AOutToAoi0Mux = 83U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1BOutToAoi0Mux = 84U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2AOutToAoi0Mux = 85U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2BOutToAoi0Mux = 86U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3AOutToAoi0Mux = 87U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3BOutToAoi0Mux = 88U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToAoi0Mux = 89U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToAoi0Mux = 90U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToAoi0Mux = 91U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToAoi0Mux = 92U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToAoi0Mux = 93U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToAoi0Mux = 94U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToAoi0Mux = 95U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToAoi0Mux = 96U + (AOI0_MUX_REG << PMUX_SHIFT), + + /*!< AOI1 trigger input connections. */ + kINPUTMUX_Adc0Tcomp0ToAoi1Mux = 1U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAoi1Mux = 2U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAoi1Mux = 3U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAoi1Mux = 4U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAoi1Mux = 5U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAoi1Mux = 6U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToAoi1Mux = 6U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAoi1Mux = 8U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAoi1Mux = 9U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToAoi1Mux = 10U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAoi1Mux = 11U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAoi1Mux = 12U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAoi1Mux = 13U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToAoi1Mux = 14U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAoi1Mux = 15U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAoi1Mux = 16U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAoi1Mux = 17U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToAoi1Mux = 18U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAoi1Mux = 19U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAoi1Mux = 20U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToAoi1Mux = 22U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToAoi1Mux = 23U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToAoi1Mux = 24U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToAoi1Mux = 25U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatchToAoi1Mux = 26U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAoi1Mux = 27U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAoi1Mux = 28U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAoi1Mux = 29U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAoi1Mux = 30U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAoi1Mux = 31U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAoi1Mux = 32U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToAoi1Mux = 33U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAoi1Mux = 34U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToAoi1Mux = 35U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToAoi1Mux = 36U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToAoi1Mux = 37U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToAoi1Mux = 38U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToAoi1Mux = 39U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToAoi1Mux = 40U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToAoi1Mux = 41U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToAoi1Mux = 42U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToAoi1Mux = 43U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToAoi1Mux = 44U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToAoi1Mux = 45U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToAoi1Mux = 46U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAoi1Mux = 47U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAoi1Mux = 48U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAoi1Mux = 49U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAoi1Mux = 50U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAoi1Mux = 51U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAoi1Mux = 52U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAoi1Mux = 53U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAoi1Mux = 54U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAoi1Mux = 55U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAoi1Mux = 56U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAoi1Mux = 57U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAoi1Mux = 58U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAoi1Mux = 59U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAoi1Mux = 60U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAoi1Mux = 61U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToAoi1Mux = 62U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAoi1Mux = 63U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAoi1Mux = 64U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAoi1Mux = 65U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAoi1Mux = 66U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAoi1Mux = 67U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToAoi1Mux = 68U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToAoi1Mux = 69U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToAoi1Mux = 70U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToAoi1Mux = 71U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatchToAoi1Mux = 72U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAoi1Mux = 73U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAoi1Mux = 74U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAoi1Mux = 75U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAoi1Mux = 76U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAoi1Mux = 77U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAoi1Mux = 78U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToAoi1Mux = 79U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig1ToAoi1Mux = 80U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0AOutToAoi1Mux = 81U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0BOutToAoi1Mux = 82U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1AOutToAoi1Mux = 83U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1BOutToAoi1Mux = 84U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2AOutToAoi1Mux = 85U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2BOutToAoi1Mux = 86U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3AOutToAoi1Mux = 87U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3BOutToAoi1Mux = 88U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp0ToAoi1Mux = 89U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp1ToAoi1Mux = 90U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp2ToAoi1Mux = 91U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc2Tcomp3ToAoi1Mux = 92U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp0ToAoi1Mux = 93U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp1ToAoi1Mux = 94U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp2ToAoi1Mux = 95U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc3Tcomp3ToAoi1Mux = 96U + (AOI0_MUX_REG << PMUX_SHIFT), + + /*!< USB-FS trigger input connections. */ + kINPUTMUX_Lpuart0TrgTxdataToUsbfsTrigger = 1U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1TrgTxdataToUsbfsTrigger = 2U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2TrgTxdataToUsbfsTrigger = 3U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3TrgTxdataToUsbfsTrigger = 4U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4TrgTxdataToUsbfsTrigger = 5U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart5TrgTxdataToUsbfsTrigger = 6U + (USBFS_TRIG_REG << PMUX_SHIFT), + + /*!< EXT trigger connections. */ + kINPUTMUX_Aoi0Out0ToExtTrigger = 2U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToExtTrigger = 3U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToExtTrigger = 4U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToExtTrigger = 5U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToExtTrigger = 6U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToExtTrigger = 7U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToExtTrigger = 8U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0ToExtTrigger = 9U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1ToExtTrigger = 10U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2ToExtTrigger = 11U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3ToExtTrigger = 12U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4ToExtTrigger = 13U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToExtTrigger = 14U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToExtTrigger = 15U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToExtTrigger = 16U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToExtTrigger = 17U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart5ToExtTrigger = 18U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Rtc1HZClkToExtTrigger = 19U + (EXT_TRIG0_REG << PMUX_SHIFT), + + /*!< LPI2C0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c0Trigger = 2U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c0Trigger = 3U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c0Trigger = 4U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c0Trigger = 5U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c0Trigger = 6U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c0Trigger = 7U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpi2c0Trigger = 8U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c0Trigger = 9U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c0Trigger = 10U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c0Trigger = 11U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c0Trigger = 12U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c0Trigger = 13U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c0Trigger = 14U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c0Trigger = 15U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c0Trigger = 17U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c0Trigger = 18U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c0Trigger = 19U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c0Trigger = 20U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c0Trigger = 21U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c0Trigger = 22U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c0Trigger = 23U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c0Trigger = 24U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c0Trigger = 25U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c0Trigger = 26U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c0Trigger = 27U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c0Trigger = 28U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c0Trigger = 29U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c0Trigger = 30U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c0Trigger = 31U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c0Trigger = 32U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c0Trigger = 33U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c0Trigger = 34U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c0Trigger = 35U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c0Trigger = 36U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c0Trigger = 37U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c0Trigger = 38U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c0Trigger = 39U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c0Trigger = 40U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c0Trigger = 41U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c0Trigger = 42U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + + /*!< LPI2C1 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c1Trigger = 2U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c1Trigger = 3U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c1Trigger = 4U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c1Trigger = 5U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c1Trigger = 6U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c1Trigger = 7U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpi2c1Trigger = 8U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c1Trigger = 9U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c1Trigger = 10U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c1Trigger = 11U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c1Trigger = 12U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c1Trigger = 13U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c1Trigger = 14U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c1Trigger = 15U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c1Trigger = 17U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c1Trigger = 18U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c1Trigger = 19U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c1Trigger = 20U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c1Trigger = 21U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c1Trigger = 22U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c1Trigger = 23U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c1Trigger = 24U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c1Trigger = 25U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c1Trigger = 26U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c1Trigger = 27U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c1Trigger = 28U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c1Trigger = 29U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c1Trigger = 30U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c1Trigger = 31U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c1Trigger = 32U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c1Trigger = 33U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c1Trigger = 34U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c1Trigger = 35U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c1Trigger = 36U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c1Trigger = 37U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c1Trigger = 38U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c1Trigger = 39U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c1Trigger = 40U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c1Trigger = 41U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c1Trigger = 42U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + + /*!< LPI2C2 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c2Trigger = 2U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c2Trigger = 3U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c2Trigger = 4U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c2Trigger = 5U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c2Trigger = 6U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c2Trigger = 7U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpi2c2Trigger = 8U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c2Trigger = 9U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c2Trigger = 10U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c2Trigger = 11U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c2Trigger = 12U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c2Trigger = 13U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c2Trigger = 14U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c2Trigger = 15U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c2Trigger = 17U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c2Trigger = 18U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c2Trigger = 19U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c2Trigger = 20U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c2Trigger = 21U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c2Trigger = 22U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c2Trigger = 23U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c2Trigger = 24U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c2Trigger = 25U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c2Trigger = 26U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c2Trigger = 27U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c2Trigger = 28U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c2Trigger = 29U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c2Trigger = 30U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c2Trigger = 31U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c2Trigger = 32U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c2Trigger = 33U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c2Trigger = 34U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c2Trigger = 35U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c2Trigger = 36U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c2Trigger = 37U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c2Trigger = 38U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c2Trigger = 39U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c2Trigger = 40U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c2Trigger = 41U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c2Trigger = 42U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + + /*!< LPI2C3 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c3Trigger = 2U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c3Trigger = 3U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c3Trigger = 4U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c3Trigger = 5U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c3Trigger = 6U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c3Trigger = 7U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpi2c3Trigger = 8U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c3Trigger = 9U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c3Trigger = 10U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c3Trigger = 11U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c3Trigger = 12U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c3Trigger = 13U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c3Trigger = 14U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c3Trigger = 15U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c3Trigger = 17U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c3Trigger = 18U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c3Trigger = 19U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c3Trigger = 20U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c3Trigger = 21U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c3Trigger = 22U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c3Trigger = 23U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c3Trigger = 24U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c3Trigger = 25U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c3Trigger = 26U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c3Trigger = 27U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c3Trigger = 28U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c3Trigger = 29U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c3Trigger = 30U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c3Trigger = 31U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c3Trigger = 32U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c3Trigger = 33U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c3Trigger = 34U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c3Trigger = 35U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c3Trigger = 36U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c3Trigger = 37U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c3Trigger = 38U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c3Trigger = 39U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c3Trigger = 40U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c3Trigger = 41U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c3Trigger = 42U + (LPI2C3_TRIG_REG << PMUX_SHIFT), + + /*!< LPSPI0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpspi0Trigger = 2U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpspi0Trigger = 3U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpspi0Trigger = 4U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpspi0Trigger = 5U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpspi0Trigger = 6U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpspi0Trigger = 7U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpspi0Trigger = 8U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpspi0Trigger = 9U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpspi0Trigger = 10U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpspi0Trigger = 11U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpspi0Trigger = 12U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpspi0Trigger = 13U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpspi0Trigger = 14U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpspi0Trigger = 15U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpspi0Trigger = 17U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpspi0Trigger = 18U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpspi0Trigger = 19U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpspi0Trigger = 20U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpspi0Trigger = 21U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpspi0Trigger = 22U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpspi0Trigger = 23U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpspi0Trigger = 24U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpspi0Trigger = 25U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpspi0Trigger = 26U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpspi0Trigger = 27U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpspi0Trigger = 28U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpspi0Trigger = 29U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpspi0Trigger = 30U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpspi0Trigger = 31U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpspi0Trigger = 32U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpspi0Trigger = 33U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpspi0Trigger = 34U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpspi0Trigger = 35U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpspi0Trigger = 36U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpspi0Trigger = 37U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpspi0Trigger = 38U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpspi0Trigger = 39U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpspi0Trigger = 40U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpspi0Trigger = 41U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpspi0Trigger = 42U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + + /*!< LPSPI1 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpspi1Trigger = 2U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpspi1Trigger = 3U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpspi1Trigger = 4U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpspi1Trigger = 5U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpspi1Trigger = 6U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpspi1Trigger = 7U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpspi1Trigger = 7U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpspi1Trigger = 9U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpspi1Trigger = 10U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpspi1Trigger = 11U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpspi1Trigger = 12U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpspi1Trigger = 13U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpspi1Trigger = 14U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpspi1Trigger = 15U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpspi1Trigger = 17U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpspi1Trigger = 18U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpspi1Trigger = 19U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpspi1Trigger = 20U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpspi1Trigger = 21U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpspi1Trigger = 22U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpspi1Trigger = 23U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpspi1Trigger = 24U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpspi1Trigger = 25U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpspi1Trigger = 26U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpspi1Trigger = 27U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpspi1Trigger = 28U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpspi1Trigger = 29U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpspi1Trigger = 30U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpspi1Trigger = 31U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpspi1Trigger = 32U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpspi1Trigger = 33U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpspi1Trigger = 34U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpspi1Trigger = 35U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpspi1Trigger = 36U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpspi1Trigger = 37U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpspi1Trigger = 38U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpspi1Trigger = 39U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpspi1Trigger = 40U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpspi1Trigger = 41U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpspi1Trigger = 42U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart0Trigger = 2U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart0Trigger = 3U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart0Trigger = 4U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart0Trigger = 5U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart0Trigger = 6U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart0Trigger = 7U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart0Trigger = 7U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart0Trigger = 9U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart0Trigger = 10U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart0Trigger = 11U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart0Trigger = 12U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart0Trigger = 13U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart0Trigger = 14U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart0Trigger = 15U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart0Trigger = 17U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart0Trigger = 18U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart0Trigger = 19U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart0Trigger = 20U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart0Trigger = 21U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart0Trigger = 22U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart0Trigger = 23U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart0Trigger = 24U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart0Trigger = 25U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart0Trigger = 26U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart0Trigger = 27U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart0Trigger = 28U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart0Trigger = 29U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart0Trigger = 30U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart0Trigger = 31U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart0Trigger = 32U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart0Trigger = 33U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart0Trigger = 34U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart0Trigger = 35U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart0Trigger = 36U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart0Trigger = 37U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart0Trigger = 38U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart0Trigger = 39U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart0Trigger = 40U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart0Trigger = 41U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart0Trigger = 42U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart0Trigger = 43U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart0Trigger = 44U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart0Trigger = 45U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart0Trigger = 46U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart0Trigger = 47U + (LPUART0_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART1 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart1Trigger = 2U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart1Trigger = 3U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart1Trigger = 4U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart1Trigger = 5U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart1Trigger = 6U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart1Trigger = 7U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart1Trigger = 8U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart1Trigger = 9U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart1Trigger = 10U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart1Trigger = 11U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart1Trigger = 12U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart1Trigger = 13U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart1Trigger = 14U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart1Trigger = 15U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart1Trigger = 17U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart1Trigger = 18U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart1Trigger = 19U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart1Trigger = 20U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart1Trigger = 21U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart1Trigger = 22U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart1Trigger = 23U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart1Trigger = 24U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart1Trigger = 25U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart1Trigger = 26U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart1Trigger = 27U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart1Trigger = 28U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart1Trigger = 29U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart1Trigger = 30U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart1Trigger = 31U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart1Trigger = 32U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart1Trigger = 33U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart1Trigger = 34U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart1Trigger = 35U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart1Trigger = 36U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart1Trigger = 37U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart1Trigger = 38U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart1Trigger = 39U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart1Trigger = 40U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart1Trigger = 41U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart1Trigger = 42U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart1Trigger = 43U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart1Trigger = 44U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart1Trigger = 45U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart1Trigger = 46U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart1Trigger = 47U + (LPUART1_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART2 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart2Trigger = 2U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart2Trigger = 3U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart2Trigger = 4U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart2Trigger = 5U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart2Trigger = 6U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart2Trigger = 7U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart2Trigger = 8U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart2Trigger = 9U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart2Trigger = 10U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart2Trigger = 11U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart2Trigger = 12U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart2Trigger = 13U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart2Trigger = 14U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart2Trigger = 15U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart2Trigger = 17U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart2Trigger = 18U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart2Trigger = 19U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart2Trigger = 20U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart2Trigger = 21U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart2Trigger = 22U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart2Trigger = 23U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart2Trigger = 24U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart2Trigger = 25U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart2Trigger = 26U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart2Trigger = 27U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart2Trigger = 28U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart2Trigger = 29U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart2Trigger = 30U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart2Trigger = 31U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart2Trigger = 32U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart2Trigger = 33U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart2Trigger = 34U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart2Trigger = 35U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart2Trigger = 36U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart2Trigger = 37U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart2Trigger = 38U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart2Trigger = 39U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart2Trigger = 40U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart2Trigger = 41U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart2Trigger = 42U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart2Trigger = 43U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart2Trigger = 44U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart2Trigger = 45U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart2Trigger = 46U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart2Trigger = 47U + (LPUART2_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART3 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart3Trigger = 2U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart3Trigger = 3U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart3Trigger = 4U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart3Trigger = 5U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart3Trigger = 6U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart3Trigger = 7U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart3Trigger = 8U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart3Trigger = 9U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart3Trigger = 10U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart3Trigger = 11U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart3Trigger = 12U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart3Trigger = 13U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart3Trigger = 14U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart3Trigger = 15U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart3Trigger = 17U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart3Trigger = 18U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart3Trigger = 19U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart3Trigger = 20U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart3Trigger = 21U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart3Trigger = 22U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart3Trigger = 23U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart3Trigger = 24U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart3Trigger = 25U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart3Trigger = 26U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart3Trigger = 27U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart3Trigger = 28U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart3Trigger = 29U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart3Trigger = 30U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart3Trigger = 31U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart3Trigger = 32U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart3Trigger = 33U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart3Trigger = 34U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart3Trigger = 35U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart3Trigger = 36U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart3Trigger = 37U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart3Trigger = 38U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart3Trigger = 39U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart3Trigger = 40U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart3Trigger = 41U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart3Trigger = 42U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart3Trigger = 43U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart3Trigger = 44U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart3Trigger = 45U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart3Trigger = 46U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart3Trigger = 47U + (LPUART3_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART4 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart4Trigger = 2U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart4Trigger = 3U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart4Trigger = 4U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart4Trigger = 5U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart4Trigger = 6U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart4Trigger = 7U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart4Trigger = 8U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart4Trigger = 9U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart4Trigger = 10U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart4Trigger = 11U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart4Trigger = 12U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart4Trigger = 13U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart4Trigger = 14U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart4Trigger = 15U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart4Trigger = 17U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart4Trigger = 18U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart4Trigger = 19U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart4Trigger = 20U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart4Trigger = 21U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart4Trigger = 22U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart4Trigger = 23U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart4Trigger = 24U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart4Trigger = 25U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart4Trigger = 26U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart4Trigger = 27U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart4Trigger = 28U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart4Trigger = 29U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart4Trigger = 30U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart4Trigger = 31U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart4Trigger = 32U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart4Trigger = 33U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart4Trigger = 34U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart4Trigger = 35U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart4Trigger = 36U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart4Trigger = 37U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart4Trigger = 38U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart4Trigger = 39U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart4Trigger = 40U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart4Trigger = 41U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart4Trigger = 42U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart4Trigger = 43U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart4Trigger = 44U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart4Trigger = 45U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart4Trigger = 46U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart4Trigger = 47U + (LPUART4_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART5 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart5Trigger = 2U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart5Trigger = 3U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart5Trigger = 4U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart5Trigger = 5U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart5Trigger = 6U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart5Trigger = 7U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToLpuart5Trigger = 8U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart5Trigger = 9U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart5Trigger = 10U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart5Trigger = 11U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart5Trigger = 12U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart5Trigger = 13U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart5Trigger = 14U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart5Trigger = 15U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart5Trigger = 17U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart5Trigger = 18U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart5Trigger = 19U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart5Trigger = 20U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart5Trigger = 21U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart5Trigger = 22U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart5Trigger = 23U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart5Trigger = 24U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart5Trigger = 25U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart5Trigger = 26U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart5Trigger = 27U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart5Trigger = 28U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart5Trigger = 29U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart5Trigger = 30U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart5Trigger = 31U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart5Trigger = 32U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart5Trigger = 33U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart5Trigger = 34U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart5Trigger = 35U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart5Trigger = 36U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart5Trigger = 37U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart5Trigger = 38U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart5Trigger = 39U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart5Trigger = 40U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart5Trigger = 41U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart5Trigger = 42U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart5Trigger = 43U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart5Trigger = 44U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart5Trigger = 45U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart5Trigger = 46U + (LPUART5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart5Trigger = 47U + (LPUART5_TRIG_REG << PMUX_SHIFT), + + /*!< Flexio trigger0 input connections. */ + kINPUTMUX_Aoi0Out0ToFlexioTrigger = 1U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexioTrigger = 2U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexioTrigger = 3U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexioTrigger = 4U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexioTrigger = 5U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexioTrigger = 6U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexioTrigger = 7U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexioTrigger = 8U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexioTrigger = 9U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexioTrigger = 10U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToFlexioTrigger = 11U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexioTrigger = 12U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexioTrigger = 13U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexioTrigger = 14U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexioTrigger = 15U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexioTrigger = 16U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexioTrigger = 17U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexioTrigger = 18U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexioTrigger = 20U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexioTrigger = 21U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexioTrigger = 22U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig0ToFlexioTrigger = 23U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexioTrigger = 24U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexioTrigger = 25U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexioTrigger = 26U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexioTrigger = 27U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexioTrigger = 28U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexioTrigger = 29U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexioTrigger = 30U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexioTrigger = 31U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexioTrigger = 32U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexioTrigger = 33U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexioTrigger = 34U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexioTrigger = 35U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexioTrigger = 36U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexioTrigger = 37U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToFlexioTrigger = 38U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToFlexioTrigger = 39U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToFlexioTrigger = 40U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToFlexioTrigger = 41U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToFlexioTrigger = 42U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToFlexioTrigger = 43U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToFlexioTrigger = 44U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToFlexioTrigger = 45U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToFlexioTrigger = 46U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToFlexioTrigger = 47U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToFlexioTrigger = 48U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToFlexioTrigger = 49U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToFlexioTrigger = 50U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToFlexioTrigger = 51U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToFlexioTrigger = 52U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToFlexioTrigger = 53U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToFlexioTrigger = 54U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToFlexioTrigger = 55U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToFlexioTrigger = 56U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToFlexioTrigger = 57U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToFlexioTrigger = 58U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToFlexioTrigger = 59U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToFlexioTrigger = 60U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexioTrigger = 61U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexioTrigger = 62U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexioTrigger = 63U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexioTrigger = 64U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexioTrigger = 65U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexioTrigger = 66U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexioTrigger = 67U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexioTrigger = 68U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexioTrigger = 69U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexioTrigger = 70U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexioTrigger = 71U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexioTrigger = 72U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexioTrigger = 73U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexioTrigger = 74U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexioTrigger = 75U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm3OutTrig0ToFlexioTrigger = 75U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToFlexioTrigger = 77U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToFlexioTrigger = 78U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToFlexioTrigger = 79U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToFlexioTrigger = 80U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + + /*!< SMARTDMA0 trigger input connections. */ + kINPUTMUX_GpioP0_16ToSmartdma0Trigger = (1U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP0_17ToSmartdma0Trigger = (2U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_8ToSmartdma0Trigger = (3U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_9ToSmartdma0Trigger = (4U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_10ToSmartdma0Trigger = (5U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_11ToSmartdma0Trigger = (6U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_12ToSmartdma0Trigger = (7U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP1_13ToSmartdma0Trigger = (8U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_0ToSmartdma0Trigger = (9U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_1ToSmartdma0Trigger = (10U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_2ToSmartdma0Trigger = (11U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_3ToSmartdma0Trigger = (12U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP2_6ToSmartdma0Trigger = (13U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_8ToSmartdma0Trigger = (14U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_9ToSmartdma0Trigger = (15U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_10ToSmartdma0Trigger = (16U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_11ToSmartdma0Trigger = (17U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioP3_12ToSmartdma0Trigger = (18U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrigToSmartdma0Trigger = (19U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrigToSmartdma0Trigger = (20U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrigToSmartdma0Trigger = (21U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrigToSmartdma0Trigger = (22U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrigToSmartdma0Trigger = (23U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSmartdma0Trigger = (24U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToSmartdma0Trigger = (25U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToSmartdma0Trigger = (26U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_DmaIrqToSmartdma0Trigger = (27U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_MauIrqToSmartdma0Trigger = (28U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuIrqToSmartdma0Trigger = (29U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToSmartdma0Trigger = (30U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToSmartdma0Trigger = (31U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToSmartdma0Trigger = (32U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToSmartdma0Trigger = (33U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToSmartdma0Trigger = (34U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToSmartdma0Trigger = (35U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToSmartdma0Trigger = (36U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToSmartdma0Trigger = (37U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToSmartdma0Trigger = (38U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToSmartdma0Trigger = (39U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_OstimerIrqToSmartdma0Trigger = (40U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0IrqToSmartdma0Trigger = (41U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1IrqToSmartdma0Trigger = (42U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0IrqToSmartdma0Trigger = (43U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1IrqToSmartdma0Trigger = (44U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_RtcAlarmIrqToSmartdma0Trigger = (45U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Rtc1hzIrqToSmartdma0Trigger = (46U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_UtickIrqToSmartdma0Trigger = (47U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WdtIrqToSmartdma0Trigger = (48U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WakeupTimerIrqToSmartdma0Trigger = (49U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Can0IrqToSmartdma0Trigger = (50U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Can1IrqToSmartdma0Trigger = (51U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioIrqToSmartdma0Trigger = (52U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioShifer0dmareqToSmartdma0Trigger = (53U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioShifer1dmareqToSmartdma0Trigger = (54U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioShifer2dmareqToSmartdma0Trigger = (55U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioShifer3dmareqToSmartdma0Trigger = (56U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_I3c0IrqToSmartdma0Trigger = (57U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c0IrqToSmartdma0Trigger = (58U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c1IrqToSmartdma0Trigger = (59U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi0IrqToSmartdma0Trigger = (60U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi1IrqToSmartdma0Trigger = (61U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0IrqToSmartdma0Trigger = (62U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1IrqToSmartdma0Trigger = (63U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2IrqToSmartdma0Trigger = (64U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3IrqToSmartdma0Trigger = (65U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Usb0SofToSmartdma0Trigger = (66U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToSmartdma0Trigger = (68U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToSmartdma0Trigger = (69U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc2IrqToSmartdma0Trigger = (70U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc3IrqToSmartdma0Trigger = (71U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0IrqToSmartdma0Trigger = (72U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1IrqToSmartdma0Trigger = (73U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2IrqToSmartdma0Trigger = (74U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToSmartdma0Trigger = (75U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToSmartdma0Trigger = (76U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToSmartdma0Trigger = (77U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Dac0IrqToSmartdma0Trigger = (78U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_SlcdIrqToSmartdma0Trigger = (79U) + (SMARTDMA0_TRIG0_REG << PMUX_SHIFT), +} inputmux_connection_t; + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.c new file mode 100644 index 000000000..7f9bea99c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.c @@ -0,0 +1,151 @@ +/* + * Copyright 2023, NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_reset.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#define GET_REG_INDEX(x) ((uint32_t)(((uint32_t)(x) & 0xFF00U) >> 8)) +#define GET_BIT_INDEX(x) ((uint32_t)((uint32_t)(x) & 0x00FFU)) + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains + * encoding of reset register and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + uint32_t regIndex = GET_REG_INDEX(peripheral); + uint32_t bitPos = GET_BIT_INDEX(peripheral); + uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + + if (peripheral == NotAvail_RSTn) + { + return; + } + + assert(bitPos < 32u); + assert(regIndex < 3u); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + /* reset register is in MRCC */ + /* set bit */ + if (regIndex == 0U) + { + MRCC0->MRCC_GLB_RST0_SET = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + } + else if (regIndex == 1U) + { + MRCC0->MRCC_GLB_RST1_SET = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST1); + } + else if (regIndex == 2U) + { + MRCC0->MRCC_GLB_RST2_SET = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST2); + } + else + { + /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */ + } + /* wait until it reads 0b1 */ + while (0u == ((*pResetCtrl) & bitMask)) + { + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains + * encoding of reset register and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + uint32_t regIndex = GET_REG_INDEX(peripheral); + uint32_t bitPos = GET_BIT_INDEX(peripheral); + uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + + assert(bitPos < 32u); + assert(regIndex < 3u); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + /* reset register is in MRCC */ + /* clear bit */ + if (regIndex == 0U) + { + MRCC0->MRCC_GLB_RST0_CLR = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + } + else if (regIndex == 1U) + { + MRCC0->MRCC_GLB_RST1_CLR = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST1); + } + else if (regIndex == 2U) + { + MRCC0->MRCC_GLB_RST2_CLR = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST2); + } + else + { + /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */ + } + /* wait until it reads 0b0 */ + while (bitMask == ((*pResetCtrl) & bitMask)) + { + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of + * reset register and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_ClearPeripheralReset(peripheral); + RESET_SetPeripheralReset(peripheral); +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.h new file mode 100644 index 000000000..98ba7f28d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_reset.h @@ -0,0 +1,201 @@ +/* + * Copyright 2023, NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include "fsl_device_registers.h" +#include +#include +#include +#include + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.4.0 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in + * PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kINPUTMUX0_RST_SHIFT_RSTn = ((0U << 8U) | 0U), /*!< INPUTMUX0 reset control */ + kCTIMER0_RST_SHIFT_RSTn = ((0U << 8U) | 2U), /*!< CTIMER0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = ((0U << 8U) | 3U), /*!< CTIMER1 reset control */ + kCTIMER2_RST_SHIFT_RSTn = ((0U << 8U) | 4U), /*!< CTIMER2 reset control */ + kFREQME_RST_SHIFT_RSTn = ((0U << 8U) | 7U), /*!< FREQME reset control */ + kUTICK0_RST_SHIFT_RSTn = ((0U << 8U) | 8U), /*!< UTICK0 reset control */ + kSMART_DMA_RST_SHIFT_RSTn = ((0U << 8U) | 10U), /*!< SMARTDMA0 reset control */ + kDMA0_RST_SHIFT_RSTn = ((0U << 8U) | 11U), /*!< DMA0 reset control */ + kAOI0_RST_SHIFT_RSTn = ((0U << 8U) | 12U), /*!< AOI0 reset control */ + kCRC0_RST_SHIFT_RSTn = ((0U << 8U) | 13U), /*!< CRC0 reset control */ + kEIM0_RST_SHIFT_RSTn = ((0U << 8U) | 14U), /*!< EIM0 reset control */ + kERM0_RST_SHIFT_RSTn = ((0U << 8U) | 15U), /*!< ERM0 reset control */ + kAOI1_RST_SHIFT_RSTn = ((0U << 8U) | 17U), /*!< AOI1 reset control */ + kLPI2C0_RST_SHIFT_RSTn = ((0U << 8U) | 19U), /*!< LPI2C0 reset control */ + kLPI2C1_RST_SHIFT_RSTn = ((0U << 8U) | 20U), /*!< LPI2C1 reset control */ + kLPSPI0_RST_SHIFT_RSTn = ((0U << 8U) | 21U), /*!< LPSPI0 reset control */ + kLPSPI1_RST_SHIFT_RSTn = ((0U << 8U) | 22U), /*!< LPSPI1 reset control */ + kLPUART0_RST_SHIFT_RSTn = ((0U << 8U) | 23U), /*!< LPUART0 reset control */ + kLPUART1_RST_SHIFT_RSTn = ((0U << 8U) | 24U), /*!< LPUART1 reset control */ + kLPUART2_RST_SHIFT_RSTn = ((0U << 8U) | 25U), /*!< LPUART2 reset control */ + kLPUART3_RST_SHIFT_RSTn = ((0U << 8U) | 26U), /*!< LPUART3 reset control */ + kQDC0_RST_SHIFT_RSTn = ((0U << 8U) | 29U), /*!< QDC0 reset control */ + kQDC1_RST_SHIFT_RSTn = ((0U << 8U) | 30U), /*!< QDC1 reset control */ + kFLEXPWM0_RST_SHIFT_RSTn = ((0U << 8U) | 31U), /*!< FLEXPWM0 reset control */ + kFLEXPWM1_RST_SHIFT_RSTn = ((1U << 8U) | 0U), /*!< FLEXPWM1 reset control */ + kOSTIMER0_RST_SHIFT_RSTn = ((1U << 8U) | 1U), /*!< OSTIMER0 reset control */ + kADC0_RST_SHIFT_RSTn = ((1U << 8U) | 2U), /*!< ADC0 reset control */ + kADC1_RST_SHIFT_RSTn = ((1U << 8U) | 3U), /*!< ADC1 reset control */ + kCMP1_RST_SHIFT_RSTn = ((1U << 8U) | 5U), /*!< CMP1 reset control */ + kCMP2_RST_SHIFT_RSTn = ((1U << 8U) | 6U), /*!< CMP2 reset control */ + kOPAMP0_RST_SHIFT_RSTn = ((1U << 8U) | 8U), /*!< OPAMP0 reset control */ + kOPAMP1_RST_SHIFT_RSTn = ((1U << 8U) | 9U), /*!< OPAMP1 reset control */ + kOPAMP2_RST_SHIFT_RSTn = ((1U << 8U) | 10U), /*!< OPAMP2 reset control */ + kPORT0_RST_SHIFT_RSTn = ((1U << 8U) | 12U), /*!< PORT0 reset control */ + kPORT1_RST_SHIFT_RSTn = ((1U << 8U) | 13U), /*!< PORT1 reset control */ + kPORT2_RST_SHIFT_RSTn = ((1U << 8U) | 14U), /*!< PORT2 reset control */ + kPORT3_RST_SHIFT_RSTn = ((1U << 8U) | 15U), /*!< PORT3 reset control */ + kPORT4_RST_SHIFT_RSTn = ((1U << 8U) | 16U), /*!< PORT4 reset control */ + kFLEXCAN0_RST_SHIFT_RSTn = ((1U << 8U) | 18U), /*!< FLEXCAN0 reset control */ + kGPIO0_RST_SHIFT_RSTn = ((2U << 8U) | 4U), /*!< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = ((2U << 8U) | 5U), /*!< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = ((2U << 8U) | 6U), /*!< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = ((2U << 8U) | 7U), /*!< GPIO3 reset control */ + kGPIO4_RST_SHIFT_RSTn = ((2U << 8U) | 8U), /*!< GPIO4 reset control */ + kMAU0_RST_SHIFT_RSTn = ((2U << 8U) | 9U), /*!< MAU0 reset control */ + NotAvail_RSTn = (0xFFFFU), /*!< No reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +/*! @brief Reset bits for AOI peripheral */ +#define AOI_RSTS {kAOI0_RST_SHIFT_RSTn, kAOI1_RST_SHIFT_RSTn} +/*! @brief Reset bits for ADC peripheral */ +#define ADC_RSTS {kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn} +/*! @brief Reset bits for CRC peripheral */ +#define CRC_RSTS {kCRC0_RST_SHIFT_RSTn} +/*! @brief Reset bits for CTIMER peripheral */ +#define CTIMER_RSTS {kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn} +/*! @brief Reset bits for DMA peripheral */ +#define DMA_RSTS_N {kDMA0_RST_SHIFT_RSTn} +/*! @brief Reset bits for EIM peripheral */ +#define EIM_RSTS_N {kEIM0_RST_SHIFT_RSTn} +/*! @brief Reset bits for ERM peripheral */ +#define ERM_RSTS_N {kERM0_RST_SHIFT_RSTn} +/*! @brief Reset bits for EQDC peripheral */ +#define EQDC_RSTS {kQDC0_RST_SHIFT_RSTn, kQDC1_RST_SHIFT_RSTn} +/*! @brief Reset bits for FLEXCAN peripheral */ +#define FLEXCAN_RSTS_N {kFLEXCAN0_RST_SHIFT_RSTn} +/*! @brief Reset bits for FLEXPWM peripheral */ +#define FLEXPWM_RSTS_N {kFLEXPWM0_RST_SHIFT_RSTn, kFLEXPWM1_RST_SHIFT_RSTn} +/*! @brief Reset bits for FREQME peripheral */ +#define FREQME_RSTS_N {kFREQME_RST_SHIFT_RSTn} +/*! @brief Reset bits for GPIO peripheral */ +#define GPIO_RSTS_N \ + {kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, kGPIO4_RST_SHIFT_RSTn} +/*! @brief Reset bits for INPUTMUX peripheral */ +#define INPUTMUX_RSTS {kINPUTMUX0_RST_SHIFT_RSTn} +/*! @brief Reset bits for LPUART peripheral */ +#define LPUART_RSTS \ + { \ + kLPUART0_RST_SHIFT_RSTn, \ + kLPUART1_RST_SHIFT_RSTn, \ + kLPUART2_RST_SHIFT_RSTn, \ + kLPUART3_RST_SHIFT_RSTn, \ + } +/*! @brief Reset bits for LPSPI peripheral */ +#define LPSPI_RSTS {kLPSPI0_RST_SHIFT_RSTn, kLPSPI1_RST_SHIFT_RSTn} +/*! @brief Reset bits for LPI2C peripheral */ +#define LPI2C_RSTS {kLPI2C0_RST_SHIFT_RSTn, kLPI2C1_RST_SHIFT_RSTn} +/*! @brief Reset bits for LPCMP peripheral */ +#define LPCMP_RSTS {NotAvail_RSTn, kCMP1_RST_SHIFT_RSTn, kCMP2_RST_SHIFT_RSTn} +/*! @brief Reset bits for MAU peripheral */ +#define MAU_RSTS {kMAU0_RST_SHIFT_RSTn} +/*! @brief Reset bits for OPAMP peripheral */ +#define OPAMP_RSTS {kOPAMP0_RST_SHIFT_RSTn, kOPAMP1_RST_SHIFT_RSTn, kOPAMP2_RST_SHIFT_RSTn} +/*! @brief Reset bits for OSTIMER peripheral */ +#define OSTIMER_RSTS {kOSTIMER0_RST_SHIFT_RSTn} +/*! @brief Reset bits for PORT peripheral */ +#define PORT_RSTS_N \ + {kPORT0_RST_SHIFT_RSTn, kPORT1_RST_SHIFT_RSTn, kPORT2_RST_SHIFT_RSTn, kPORT3_RST_SHIFT_RSTn, kPORT4_RST_SHIFT_RSTn} +/*! @brief Reset bits for SMARTDMA peripheral */ +#define SMARTDMA_RSTS {kSMART_DMA_RST_SHIFT_RSTn} +/*! @brief Reset bits for UTICK peripheral */ +#define UTICK_RSTS {kUTICK0_RST_SHIFT_RSTn} + +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains + * encoding of reset register and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains + * encoding of reset register and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of + * reset register and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Release peripheral module. + * + * Release peripheral module. + * + * @param peripheral Peripheral to release. The enum argument contains encoding + * of reset register and reset bit position in the reset register. + */ +static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_trdc_soc.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_trdc_soc.h new file mode 100644 index 000000000..aa4194892 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/drivers/fsl_trdc_soc.h @@ -0,0 +1,62 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_TRDC_SOC_H_ +#define _FSL_TRDC_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup trdc_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.trdc_soc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.0. */ +#define FSL_TRDC_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK 0x000003FFUL +#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK 0x001F0000UL +#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT 16U +#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(x) & 0xFUL) << 8U) +#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x) (((uint32_t)(x) & 0x1UL) << 16U) + +/*!@brief TRDC feature */ +#define FSL_FEATURE_TRDC_DOMAIN_COUNT 1 + +/*!@brief TRDC base address convert macro */ +#define TRDC_MBC_COUNT 1 +/*!@brief MBC register offset in TRDC_Type structure. */ +#define TRDC_MBC_OFFSET(x) 0x0000 +/*!@brief Offset between two MBC control block, useless if there is only one. */ +#define TRDC_MBC_ARRAY_STEP 0U + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_TRDC_SOC_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/fsl_device_registers.h new file mode 100644 index 000000000..895514b60 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.c new file mode 100644 index 000000000..ecb65b35a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.c @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA344 startup code +// +// Version : 060825 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void Reserved33_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void Reserved40_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void Reserved51_IRQHandler(void); +WEAK void Reserved52_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void Reserved58_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void Reserved83_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void Reserved93_IRQHandler(void); +WEAK void Reserved94_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void Reserved125_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved51_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved83_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved93_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved94_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA344 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + Reserved33_IRQHandler, // 33 : Reserved interrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + Reserved39_IRQHandler, // 39 : Reserved interrupt + Reserved40_IRQHandler, // 40 : Reserved interrupt + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + Reserved51_IRQHandler, // 51 : Reserved interrupt + Reserved52_IRQHandler, // 52 : Reserved interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + Reserved58_IRQHandler, // 58 : Reserved interrupt + Reserved59_IRQHandler, // 59 : Reserved interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + Reserved83_IRQHandler, // 83 : Reserved interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + Reserved93_IRQHandler, // 93 : Reserved interrupt + Reserved94_IRQHandler, // 94 : Reserved interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + Reserved125_IRQHandler, // 125: Reserved interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void Reserved33_IRQHandler(void) +{ + Reserved33_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ + Reserved39_DriverIRQHandler(); +} + +WEAK void Reserved40_IRQHandler(void) +{ + Reserved40_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void Reserved51_IRQHandler(void) +{ + Reserved51_DriverIRQHandler(); +} + +WEAK void Reserved52_IRQHandler(void) +{ + Reserved52_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void Reserved58_IRQHandler(void) +{ + Reserved58_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ + Reserved59_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void Reserved83_IRQHandler(void) +{ + Reserved83_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void Reserved93_IRQHandler(void) +{ + Reserved93_DriverIRQHandler(); +} + +WEAK void Reserved94_IRQHandler(void) +{ + Reserved94_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void Reserved125_IRQHandler(void) +{ + Reserved125_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.cpp new file mode 100644 index 000000000..ecb65b35a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/startup_MCXA344.cpp @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA344 startup code +// +// Version : 060825 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void Reserved33_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void Reserved40_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void Reserved51_IRQHandler(void); +WEAK void Reserved52_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void Reserved58_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void Reserved83_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void Reserved93_IRQHandler(void); +WEAK void Reserved94_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void Reserved111_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void Reserved125_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void Reserved132_IRQHandler(void); +WEAK void Reserved133_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved51_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved83_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved93_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved94_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved111_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved132_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved133_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA344 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + Reserved33_IRQHandler, // 33 : Reserved interrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + Reserved39_IRQHandler, // 39 : Reserved interrupt + Reserved40_IRQHandler, // 40 : Reserved interrupt + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + Reserved51_IRQHandler, // 51 : Reserved interrupt + Reserved52_IRQHandler, // 52 : Reserved interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + Reserved58_IRQHandler, // 58 : Reserved interrupt + Reserved59_IRQHandler, // 59 : Reserved interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + Reserved83_IRQHandler, // 83 : Reserved interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + Reserved93_IRQHandler, // 93 : Reserved interrupt + Reserved94_IRQHandler, // 94 : Reserved interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + Reserved111_IRQHandler, // 111: Reserved interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + Reserved125_IRQHandler, // 125: Reserved interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + Reserved132_IRQHandler, // 132: Reserved interrupt + Reserved133_IRQHandler, // 133: Reserved interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void Reserved33_IRQHandler(void) +{ + Reserved33_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ + Reserved39_DriverIRQHandler(); +} + +WEAK void Reserved40_IRQHandler(void) +{ + Reserved40_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void Reserved51_IRQHandler(void) +{ + Reserved51_DriverIRQHandler(); +} + +WEAK void Reserved52_IRQHandler(void) +{ + Reserved52_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void Reserved58_IRQHandler(void) +{ + Reserved58_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ + Reserved59_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void Reserved83_IRQHandler(void) +{ + Reserved83_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void Reserved93_IRQHandler(void) +{ + Reserved93_DriverIRQHandler(); +} + +WEAK void Reserved94_IRQHandler(void) +{ + Reserved94_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void Reserved111_IRQHandler(void) +{ + Reserved111_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void Reserved125_IRQHandler(void) +{ + Reserved125_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void Reserved132_IRQHandler(void) +{ + Reserved132_DriverIRQHandler(); +} + +WEAK void Reserved133_IRQHandler(void) +{ + Reserved133_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.c new file mode 100644 index 000000000..1564064ca --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.c @@ -0,0 +1,115 @@ +/* +** ################################################################### +** Processors: MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1_DraftC +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXA344 + * @version 2.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXA344 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.h new file mode 100644 index 000000000..efb3dd9d9 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/system_MCXA344.h @@ -0,0 +1,116 @@ +/* +** ################################################################### +** Processors: MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1_DraftC +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXA344 + * @version 2.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXA344 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA344_H_ +#define _SYSTEM_MCXA344_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA344_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/variable.cmake new file mode 100644 index 000000000..b5f6656d0 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA344/variable.cmake @@ -0,0 +1,14 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA344) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph3) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/CMakeLists.txt index d394a2184..92e7d0489 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345.h index dfeb37bcf..703872249 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA345 @@ -53,6 +53,7 @@ #include "PERI_CRC.h" #include "PERI_CTIMER.h" #include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" #include "PERI_DMA.h" #include "PERI_EIM.h" #include "PERI_EQDC.h" @@ -81,7 +82,6 @@ #include "PERI_SPC.h" #include "PERI_SYSCON.h" #include "PERI_TRDC.h" -#include "PERI_UDF.h" #include "PERI_UTICK.h" #include "PERI_VBAT.h" #include "PERI_WAKETIMER.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345_COMMON.h index 9d401fb0d..4642e89fd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA345 @@ -97,7 +97,7 @@ typedef enum IRQn { MBC0_IRQn = 14, /**< MBC secure violation interrupt */ SCG0_IRQn = 15, /**< System Clock Generator interrupt */ SPC0_IRQn = 16, /**< System Power Controller interrupt */ - Reserved33_IRQn = 17, /**< Reserved interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ Reserved36_IRQn = 20, /**< Reserved interrupt */ @@ -161,7 +161,7 @@ typedef enum IRQn { LPUART5_IRQn = 95, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ MAU_IRQn = 107, /**< MAU interrupt */ SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ - Reserved125_IRQn = 109, /**< Reserved interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ Reserved126_IRQn = 110, /**< Reserved interrupt */ Reserved127_IRQn = 111, /**< Reserved interrupt */ Reserved129_IRQn = 113, /**< Reserved interrupt */ @@ -268,12 +268,16 @@ typedef enum IRQn { #define CDOG0_BASE (0x40100000u) /** Peripheral CDOG0 base pointer */ #define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) /** Array initializer of CDOG peripheral base addresses */ -#define CDOG_BASE_ADDRS { CDOG0_BASE } +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } /** Array initializer of CDOG peripheral base pointers */ -#define CDOG_BASE_PTRS { CDOG0 } +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } /** Interrupt vectors for the CDOG peripheral type */ -#define CDOG_IRQS { CDOG0_IRQn } +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } /* CMC - Peripheral instance base addresses */ /** Peripheral CMC base address */ @@ -333,6 +337,16 @@ typedef enum IRQn { /** Array initializer of DEBUGMAILBOX peripheral base pointers */ #define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + /* DMA - Peripheral instance base addresses */ /** Peripheral DMA0 base address */ #define DMA0_BASE (0x40080000u) @@ -412,6 +426,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ @@ -749,16 +765,6 @@ typedef enum IRQn { #define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} -/* UDF - Peripheral instance base addresses */ -/** Peripheral UDF0 base address */ -#define UDF0_BASE (0x400ED000u) -/** Peripheral UDF0 base pointer */ -#define UDF0 ((UDF_Type *)UDF0_BASE) -/** Array initializer of UDF peripheral base addresses */ -#define UDF_BASE_ADDRS { UDF0_BASE } -/** Array initializer of UDF peripheral base pointers */ -#define UDF_BASE_PTRS { UDF0 } - /* UTICK - Peripheral instance base addresses */ /** Peripheral UTICK0 base address */ #define UTICK0_BASE (0x4000B000u) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345_features.h index 144e4bc25..7bc436b4c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/MCXA345_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-26 -** Build: b250522 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -25,141 +25,72 @@ /* SOC module features */ -#if defined(CPU_MCXA345VLH) - /* @brief AOI availability on the SoC. */ - #define FSL_FEATURE_SOC_AOI_COUNT (2) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (1) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (1) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EQDC availability on the SoC. */ - #define FSL_FEATURE_SOC_EQDC_COUNT (2) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (5) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (4) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (1) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (4) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (2) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (1) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (6) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (5) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief WAKETIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (1) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#elif defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN) - /* @brief AOI availability on the SoC. */ - #define FSL_FEATURE_SOC_AOI_COUNT (2) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (1) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (1) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EQDC availability on the SoC. */ - #define FSL_FEATURE_SOC_EQDC_COUNT (2) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (5) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (4) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (1) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (4) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (2) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (1) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (6) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (4) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (5) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief WAKETIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (1) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#endif +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (4) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (4) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) /* LPADC module features */ @@ -325,6 +256,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -503,6 +438,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -624,8 +561,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -668,6 +603,14 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MAU module features */ + +/* No feature definitions */ /* TRDC module features */ @@ -758,10 +701,56 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) /* SPC module features */ @@ -822,6 +811,8 @@ #define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) /* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ #define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (0) /* SysTick module features */ @@ -832,7 +823,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -854,8 +845,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA345_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/startup_MCXA345.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/startup_MCXA345.c index 7d42cd90a..ef397f5ea 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/startup_MCXA345.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/startup_MCXA345.c @@ -1,7 +1,7 @@ //***************************************************************************** // MCXA345 startup code // -// Version : 100625 +// Version : 300725 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -105,7 +105,7 @@ WEAK void GLIKEY0_IRQHandler(void); WEAK void MBC0_IRQHandler(void); WEAK void SCG0_IRQHandler(void); WEAK void SPC0_IRQHandler(void); -WEAK void Reserved33_IRQHandler(void); +WEAK void TDET_IRQHandler(void); WEAK void WUU0_IRQHandler(void); WEAK void CAN0_IRQHandler(void); WEAK void Reserved36_IRQHandler(void); @@ -197,7 +197,7 @@ WEAK void Reserved121_IRQHandler(void); WEAK void Reserved122_IRQHandler(void); WEAK void MAU_IRQHandler(void); WEAK void SMARTDMA_IRQHandler(void); -WEAK void Reserved125_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); WEAK void Reserved126_IRQHandler(void); WEAK void Reserved127_IRQHandler(void); WEAK void Reserved128_IRQHandler(void); @@ -233,7 +233,7 @@ void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -325,7 +325,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -460,7 +460,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) MBC0_IRQHandler, // 30 : MBC secure violation interrupt SCG0_IRQHandler, // 31 : System Clock Generator interrupt SPC0_IRQHandler, // 32 : System Power Controller interrupt - Reserved33_IRQHandler, // 33 : Reserved interrupt + TDET_IRQHandler, // 33 : TDET interrrupt WUU0_IRQHandler, // 34 : Wake Up Unit interrupt CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt Reserved36_IRQHandler, // 36 : Reserved interrupt @@ -552,7 +552,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) Reserved122_IRQHandler, // 122: Reserved interrupt MAU_IRQHandler, // 123: MAU interrupt SMARTDMA_IRQHandler, // 124: SmartDMA interrupt - Reserved125_IRQHandler, // 125: Reserved interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt Reserved126_IRQHandler, // 126: Reserved interrupt Reserved127_IRQHandler, // 127: Reserved interrupt Reserved128_IRQHandler, // 128: Reserved interrupt @@ -935,9 +935,9 @@ WEAK void SPC0_IRQHandler(void) SPC0_DriverIRQHandler(); } -WEAK void Reserved33_IRQHandler(void) +WEAK void TDET_IRQHandler(void) { - Reserved33_DriverIRQHandler(); + TDET_DriverIRQHandler(); } WEAK void WUU0_IRQHandler(void) @@ -1395,9 +1395,9 @@ WEAK void SMARTDMA_IRQHandler(void) SMARTDMA_DriverIRQHandler(); } -WEAK void Reserved125_IRQHandler(void) +WEAK void CDOG1_IRQHandler(void) { - Reserved125_DriverIRQHandler(); + CDOG1_DriverIRQHandler(); } WEAK void Reserved126_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/startup_MCXA345.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/startup_MCXA345.cpp index 7d42cd90a..ef397f5ea 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/startup_MCXA345.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/startup_MCXA345.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MCXA345 startup code // -// Version : 100625 +// Version : 300725 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -105,7 +105,7 @@ WEAK void GLIKEY0_IRQHandler(void); WEAK void MBC0_IRQHandler(void); WEAK void SCG0_IRQHandler(void); WEAK void SPC0_IRQHandler(void); -WEAK void Reserved33_IRQHandler(void); +WEAK void TDET_IRQHandler(void); WEAK void WUU0_IRQHandler(void); WEAK void CAN0_IRQHandler(void); WEAK void Reserved36_IRQHandler(void); @@ -197,7 +197,7 @@ WEAK void Reserved121_IRQHandler(void); WEAK void Reserved122_IRQHandler(void); WEAK void MAU_IRQHandler(void); WEAK void SMARTDMA_IRQHandler(void); -WEAK void Reserved125_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); WEAK void Reserved126_IRQHandler(void); WEAK void Reserved127_IRQHandler(void); WEAK void Reserved128_IRQHandler(void); @@ -233,7 +233,7 @@ void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -325,7 +325,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -460,7 +460,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) MBC0_IRQHandler, // 30 : MBC secure violation interrupt SCG0_IRQHandler, // 31 : System Clock Generator interrupt SPC0_IRQHandler, // 32 : System Power Controller interrupt - Reserved33_IRQHandler, // 33 : Reserved interrupt + TDET_IRQHandler, // 33 : TDET interrrupt WUU0_IRQHandler, // 34 : Wake Up Unit interrupt CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt Reserved36_IRQHandler, // 36 : Reserved interrupt @@ -552,7 +552,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) Reserved122_IRQHandler, // 122: Reserved interrupt MAU_IRQHandler, // 123: MAU interrupt SMARTDMA_IRQHandler, // 124: SmartDMA interrupt - Reserved125_IRQHandler, // 125: Reserved interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt Reserved126_IRQHandler, // 126: Reserved interrupt Reserved127_IRQHandler, // 127: Reserved interrupt Reserved128_IRQHandler, // 128: Reserved interrupt @@ -935,9 +935,9 @@ WEAK void SPC0_IRQHandler(void) SPC0_DriverIRQHandler(); } -WEAK void Reserved33_IRQHandler(void) +WEAK void TDET_IRQHandler(void) { - Reserved33_DriverIRQHandler(); + TDET_DriverIRQHandler(); } WEAK void WUU0_IRQHandler(void) @@ -1395,9 +1395,9 @@ WEAK void SMARTDMA_IRQHandler(void) SMARTDMA_DriverIRQHandler(); } -WEAK void Reserved125_IRQHandler(void) +WEAK void CDOG1_IRQHandler(void) { - Reserved125_DriverIRQHandler(); + CDOG1_DriverIRQHandler(); } WEAK void Reserved126_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/system_MCXA345.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/system_MCXA345.c index feaa1c9ce..5d22d6839 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/system_MCXA345.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/system_MCXA345.c @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250516 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/system_MCXA345.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/system_MCXA345.h index ce60e2b6e..47b36f454 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/system_MCXA345.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/system_MCXA345.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250516 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/variable.cmake index de584972d..db6af289a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA345/variable.cmake @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/CMakeLists.txt index d394a2184..92e7d0489 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346.h index 63ccf98e1..4ad27a1ac 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA346 @@ -53,6 +53,7 @@ #include "PERI_CRC.h" #include "PERI_CTIMER.h" #include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" #include "PERI_DMA.h" #include "PERI_EIM.h" #include "PERI_EQDC.h" @@ -81,7 +82,6 @@ #include "PERI_SPC.h" #include "PERI_SYSCON.h" #include "PERI_TRDC.h" -#include "PERI_UDF.h" #include "PERI_UTICK.h" #include "PERI_VBAT.h" #include "PERI_WAKETIMER.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346_COMMON.h index 35964de4a..c0b4fd65a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA346 @@ -97,7 +97,7 @@ typedef enum IRQn { MBC0_IRQn = 14, /**< MBC secure violation interrupt */ SCG0_IRQn = 15, /**< System Clock Generator interrupt */ SPC0_IRQn = 16, /**< System Power Controller interrupt */ - Reserved33_IRQn = 17, /**< Reserved interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ Reserved36_IRQn = 20, /**< Reserved interrupt */ @@ -161,7 +161,7 @@ typedef enum IRQn { LPUART5_IRQn = 95, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ MAU_IRQn = 107, /**< MAU interrupt */ SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ - Reserved125_IRQn = 109, /**< Reserved interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ Reserved126_IRQn = 110, /**< Reserved interrupt */ Reserved127_IRQn = 111, /**< Reserved interrupt */ Reserved129_IRQn = 113, /**< Reserved interrupt */ @@ -268,12 +268,16 @@ typedef enum IRQn { #define CDOG0_BASE (0x40100000u) /** Peripheral CDOG0 base pointer */ #define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) /** Array initializer of CDOG peripheral base addresses */ -#define CDOG_BASE_ADDRS { CDOG0_BASE } +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } /** Array initializer of CDOG peripheral base pointers */ -#define CDOG_BASE_PTRS { CDOG0 } +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } /** Interrupt vectors for the CDOG peripheral type */ -#define CDOG_IRQS { CDOG0_IRQn } +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } /* CMC - Peripheral instance base addresses */ /** Peripheral CMC base address */ @@ -333,6 +337,16 @@ typedef enum IRQn { /** Array initializer of DEBUGMAILBOX peripheral base pointers */ #define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + /* DMA - Peripheral instance base addresses */ /** Peripheral DMA0 base address */ #define DMA0_BASE (0x40080000u) @@ -412,6 +426,8 @@ typedef enum IRQn { #define FREQME_BASE_ADDRS { FREQME0_BASE } /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ /** Peripheral GLIKEY0 base address */ @@ -749,16 +765,6 @@ typedef enum IRQn { #define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} -/* UDF - Peripheral instance base addresses */ -/** Peripheral UDF0 base address */ -#define UDF0_BASE (0x400ED000u) -/** Peripheral UDF0 base pointer */ -#define UDF0 ((UDF_Type *)UDF0_BASE) -/** Array initializer of UDF peripheral base addresses */ -#define UDF_BASE_ADDRS { UDF0_BASE } -/** Array initializer of UDF peripheral base pointers */ -#define UDF_BASE_PTRS { UDF0 } - /* UTICK - Peripheral instance base addresses */ /** Peripheral UTICK0 base address */ #define UTICK0_BASE (0x4000B000u) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346_features.h index 500d38e82..f0018425d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/MCXA346_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-26 -** Build: b250522 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -25,141 +25,72 @@ /* SOC module features */ -#if defined(CPU_MCXA346VLH) - /* @brief AOI availability on the SoC. */ - #define FSL_FEATURE_SOC_AOI_COUNT (2) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (1) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (1) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EQDC availability on the SoC. */ - #define FSL_FEATURE_SOC_EQDC_COUNT (2) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (5) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (4) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (1) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (4) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (2) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (1) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (6) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (5) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief WAKETIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (1) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#elif defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN) - /* @brief AOI availability on the SoC. */ - #define FSL_FEATURE_SOC_AOI_COUNT (2) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (1) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (1) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EQDC availability on the SoC. */ - #define FSL_FEATURE_SOC_EQDC_COUNT (2) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (5) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (4) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (1) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (4) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (2) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (1) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (6) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (4) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (5) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief WAKETIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (1) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#endif +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (4) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (4) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) /* LPADC module features */ @@ -325,6 +256,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -503,6 +438,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -624,8 +561,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -668,6 +603,14 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MAU module features */ + +/* No feature definitions */ /* TRDC module features */ @@ -758,10 +701,56 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) /* SPC module features */ @@ -822,6 +811,8 @@ #define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) /* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ #define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (0) /* SysTick module features */ @@ -832,7 +823,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -854,8 +845,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA346_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/CMakeLists.txt index 5ecd450fc..6837e437b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -6,7 +6,7 @@ mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA153/drivers/romapi) if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.0.0) + mcux_component_version(2.0.1) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) mcux_add_include( INCLUDES . ) endif() diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_clock.c index 32d6f5b48..cb5000b77 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_clock.c @@ -1,5 +1,5 @@ /* - * Copyright 2023, NXP + * Copyright 2025, NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -14,6 +14,12 @@ #define FSL_COMPONENT_ID "platform.drivers.clock" #endif +#define IFR1_ADDR (0x01100000U) +#define IFR1_VAL_180M_TRIM *((volatile uint32_t *)(IFR1_ADDR + 0x870U)) +#if FSL_FEATURE_FIRC_SUPPORT_240M +#define IFR1_VAL_240M_TRIM *((volatile uint32_t *)(IFR1_ADDR + 0x874U)) +#endif + #define NVALMAX (0x100U) #define PVALMAX (0x20U) #define MVALMAX (0x10000U) @@ -272,24 +278,45 @@ void CLOCK_HaltClockDiv(clock_div_name_t div_name) SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; } -/* Initialize the FROHF to given frequency (45,60,90,180) */ +/* Initialize the FROHF to given frequency (45,60,90,180) + * (80,120,240) are only supported for 240M part */ status_t CLOCK_SetupFROHFClocking(uint32_t iFreq) { - uint8_t freq_select = 0x0U; + uint8_t freq_select = 0x0U; + uint8_t need_switch_frohf = 0x0U; + uint32_t trim_value = 0x0U; switch (iFreq) { case 45000000U: freq_select = 1U; + trim_value = IFR1_VAL_180M_TRIM; break; case 60000000U: freq_select = 3U; + trim_value = IFR1_VAL_180M_TRIM; break; case 90000000U: freq_select = 5U; + trim_value = IFR1_VAL_180M_TRIM; break; case 180000000U: freq_select = 7U; + trim_value = IFR1_VAL_180M_TRIM; + break; +#if FSL_FEATURE_FIRC_SUPPORT_240M + case 80000000U: + freq_select = 3U; + trim_value = IFR1_VAL_240M_TRIM; + break; + case 120000000U: + freq_select = 5U; + trim_value = IFR1_VAL_240M_TRIM; + break; + case 240000000U: + freq_select = 7U; + trim_value = IFR1_VAL_240M_TRIM; break; +#endif default: freq_select = 0xFU; break; @@ -300,6 +327,27 @@ status_t CLOCK_SetupFROHFClocking(uint32_t iFreq) return kStatus_Fail; } + /* Check if the trim value is valid */ + if (trim_value == 0xFFFFFFFFU) + { + return kStatus_Fail; + } + + /* Switch to FRO LF is FRO HF is in use */ + if (0x3U == ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)) + { + need_switch_frohf = 1; + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); + } + + /* Load trim value from IFR */ + if (SCG0->FIRCTRIM != trim_value) + { + SCG0->TRIM_LOCK = 0x5A5A0001U; + SCG0->FIRCTRIM = trim_value; + SCG0->TRIM_LOCK = 0x5A5A0000U; + } + /* Set FIRC frequency */ SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); @@ -316,9 +364,15 @@ status_t CLOCK_SetupFROHFClocking(uint32_t iFreq) /* Lock FIRCCSR */ SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; - /* Wait for FIRC clock to be valid. */ - while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) + /* Wait for FIRC clock to be stable. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCACC_MASK) == 0U) + { + } + + /* Switch back to FRO HF */ + if (1 == need_switch_frohf) { + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); } return kStatus_Success; @@ -560,34 +614,45 @@ static uint32_t CLOCK_GetClk1MFreq(void) */ static uint32_t CLOCK_GetFroHfFreq(void) { - uint32_t freq; + uint8_t div; if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) { - freq = 0U; + div = 0U; } switch ((SCG0->FIRCCFG & SCG_FIRCCFG_FREQ_SEL_MASK) >> SCG_FIRCCFG_FREQ_SEL_SHIFT) { case 1U: - freq = 45000000U; + div = 4U; break; case 3U: - freq = 60000000U; + div = 3U; break; case 5U: - freq = 90000000U; + div = 2U; break; case 7U: - freq = 180000000U; + div = 1U; break; default: - freq = 0U; + div = 0U; break; } - return freq; +#if FSL_FEATURE_FIRC_SUPPORT_240M + if (SCG0->FIRCTRIM == IFR1_VAL_180M_TRIM) + { + return (div != 0U) ? (180000000U / div) : 0U; + } + else + { + return (div != 0U) ? (240000000U / div) : 0U; + } +#else + return (div != 0U) ? (180000000U / div) : 0U; +#endif } /* Get HF FRO DIV Clk */ @@ -1323,41 +1388,8 @@ uint32_t CLOCK_GetClkoutClkFreq(void) return freq / ((clkdiv & 0xFFU) + 1U); } -/*! brief Return Frequency of Systick Clock - * return Frequency of Systick. - */ -uint32_t CLOCK_GetSystickClkFreq(void) -{ - uint32_t freq = 0U; - uint32_t clksel = (MRCC0->MRCC_SYSTICK_CLKSEL); - uint32_t clkdiv = (MRCC0->MRCC_SYSTICK_CLKDIV); - - if (true == CLOCK_IsDivHalt(clkdiv)) - { - return 0; - } - - switch (clksel) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetClk1MFreq(); - break; - case 2U: - freq = CLOCK_GetClk16KFreq(1); - break; - default: - freq = 0U; - break; - } - - return freq / ((clkdiv & 0xFFU) + 1U); -} - -/*! brief Return Frequency of Systick Clock - * return Frequency of Systick. +/*! brief Return Frequency of WWDT Clock + * return Frequency of WWDT. */ uint32_t CLOCK_GetWwdtClkFreq(void) { diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_clock.h index bcb9516b6..8e47ed72f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2023, NXP + * Copyright 2025, NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.0.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief CLOCK driver version 2.0.1. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @brief Configure whether driver controls clock @@ -52,8 +52,12 @@ /* Definition for delay API in clock driver, users can redefine it to the real application. */ #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#if FSL_FEATURE_FIRC_SUPPORT_240M +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (240000000U) +#else #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000U) #endif +#endif /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ /*------------------------------------------------------------------------------ @@ -273,14 +277,14 @@ typedef enum _clock_ip_name } \ } /*! @brief Clock ip name array for PKC. */ -#define PKC_CLOCKS \ - { \ - kCLOCK_GatePKC0 \ \ +#define PKC_CLOCKS \ + { \ + kCLOCK_GatePKC0 \ } /*! @brief Clock ip name array for PORT. */ -#define PORT_CLOCKS \ - { \ - kCLOCK_GatePORT0, kCLOCK_GatePORT1, kCLOCK_GatePORT2, kCLOCK_GatePORT3, kCLOCK_GatePORT4 \ \ +#define PORT_CLOCKS \ + { \ + kCLOCK_GatePORT0, kCLOCK_GatePORT1, kCLOCK_GatePORT2, kCLOCK_GatePORT3, kCLOCK_GatePORT4 \ } /*! @brief Clock ip name array for QDC. */ #define QDC_CLOCKS \ @@ -298,8 +302,8 @@ typedef enum _clock_ip_name kCLOCK_GateSLCD0 \ } /*! @brief Clock ip name array for SMARTDMA. */ -#define SMARTDMA_CLOCKS \ - { \ +#define SMARTDMA_CLOCKS \ + { \ kCLOCK_Smartdma \ } /*! @brief Clock ip name array for TDET. */ @@ -394,7 +398,6 @@ typedef enum _clock_select_name kCLOCK_SelLPUART5 = (0x1A0U), /*!< LPUART5 clock selection */ kCLOCK_SelTRACE = (0x1A8U), /*!< TRACE clock selection */ kCLOCK_SelCLKOUT = (0x1B0U), /*!< CLKOUT clock selection */ - kCLOCK_SelSYSTICK = (0x1B8U), /*!< SYSTICK clock selection */ kCLOCK_SelSCGSCS = (0x200U), /*!< SCG SCS clock selection */ kCLOCK_SelMax = (0x200U), /*!< MAX clock selection */ } clock_select_name_t; @@ -631,11 +634,6 @@ typedef enum _clock_attach_id kSLOW_CLK_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 6U), /*!< Attach SLOW_CLK to CLKOUT. */ kNONE_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 7U), /*!< Attach NONE to CLKOUT. */ - kCPU_CLK_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 0U), /*!< Attach CPU_CLK to SYSTICK. */ - kCLK_1M_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 1U), /*!< Attach CLK_1M to SYSTICK. */ - kCLK_16K_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 2U), /*!< Attach CLK_16K to SYSTICK. */ - kNONE_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 3U), /*!< Attach NONE to SYSTICK. */ - kNONE_to_NONE = (0xFFFFFFFFU), /*!< Attach NONE to NONE. */ } clock_attach_id_t; @@ -677,7 +675,6 @@ typedef enum _clock_div_name kCLOCK_DivLPUART5 = (0x1A4U), /*!< LPUART5 clock divider */ kCLOCK_DivTRACE = (0x1ACU), /*!< DBG_TRACE clock divider */ kCLOCK_DivCLKOUT = (0x1B4U), /*!< CLKOUT clock divider */ - kCLOCK_DivSYSTICK = (0x1BCU), /*!< SYSTICK clock divider */ kCLOCK_DivSLOWCLK = (0x378U), /*!< SLOWCLK clock divider */ kCLOCK_DivBUSCLK = (0x37CU), /*!< BUSCLK clock divider */ kCLOCK_DivAHBCLK = (0x380U), /*!< AHBCLK clock divider */ @@ -917,7 +914,7 @@ uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name); void CLOCK_HaltClockDiv(clock_div_name_t div_name); /** - * @brief Initialize the FROHF to given frequency (48,64,96,192). + * @brief Initialize the FROHF to given frequency. * This function turns on FIRC and select the given frequency as the source of fro_hf * @param iFreq : Desired frequency. * @return returns success or fail status. @@ -1032,13 +1029,8 @@ uint32_t CLOCK_GetTraceClkFreq(void); */ uint32_t CLOCK_GetClkoutClkFreq(void); -/*! @brief Return Frequency of Systick Clock - * @return Frequency of Systick. - */ -uint32_t CLOCK_GetSystickClkFreq(void); - -/*! brief Return Frequency of Systick Clock - * return Frequency of Systick. +/*! brief Return Frequency of WWDT Clock + * return Frequency of WWDT. */ uint32_t CLOCK_GetWwdtClkFreq(void); diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_edma_soc.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_edma_soc.c index f32c9e0e1..97635fbfb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_edma_soc.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_edma_soc.c @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2025 NXP * All rights reserved. * * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_edma_soc.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_edma_soc.h index 7090fdc6f..b28b39789 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_edma_soc.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_edma_soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_inputmux_connections.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_inputmux_connections.h index cdeb22180..cee5b5ea6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_inputmux_connections.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_inputmux_connections.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 , NXP + * Copyright 2025 , NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -3756,7 +3756,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm0Sm2OutTrig0ToAoi0Mux = 31U + (AOI0_MUX_REG << PMUX_SHIFT), kINPUTMUX_Pwm0Sm2OutTrig1ToAoi0Mux = 32U + (AOI0_MUX_REG << PMUX_SHIFT), kINPUTMUX_Pwm0Sm3OutTrig0ToAoi0Mux = 33U + (AOI0_MUX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm0Sm3OutTrig1ToAoi0Mux = 33U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm3OutTrig1ToAoi0Mux = 34U + (AOI0_MUX_REG << PMUX_SHIFT), kINPUTMUX_TrigIn0ToAoi0Mux = 35U + (AOI0_MUX_REG << PMUX_SHIFT), kINPUTMUX_TrigIn1ToAoi0Mux = 36U + (AOI0_MUX_REG << PMUX_SHIFT), kINPUTMUX_TrigIn2ToAoi0Mux = 37U + (AOI0_MUX_REG << PMUX_SHIFT), diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_reset.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_reset.c index dfedecf74..23823aa33 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_reset.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_reset.c @@ -1,5 +1,5 @@ /* - * Copyright 2023, NXP + * Copyright 2025, NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_reset.h index a858bc2bb..39fbbe7ad 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_reset.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_reset.h @@ -1,5 +1,5 @@ /* - * Copyright 2023, NXP + * Copyright 2025, NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -239,7 +239,7 @@ typedef enum _SYSCON_RSTn /*! @brief Reset bits for SMARTDMA peripheral */ #define SMARTDMA_RSTS \ { \ - kSMARTDMA0_RST_SHIFT_RSTn \ + kSMART_DMA_RST_SHIFT_RSTn \ } /*! @brief Reset bits for TRNG peripheral */ #define TRNG_RSTS \ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_trdc_soc.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_trdc_soc.h index 1fb294022..a9a826088 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_trdc_soc.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/drivers/fsl_trdc_soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/startup_MCXA346.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/startup_MCXA346.c index a96376f92..2d8dd90e3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/startup_MCXA346.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/startup_MCXA346.c @@ -1,7 +1,7 @@ //***************************************************************************** // MCXA346 startup code // -// Version : 100625 +// Version : 300725 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -105,7 +105,7 @@ WEAK void GLIKEY0_IRQHandler(void); WEAK void MBC0_IRQHandler(void); WEAK void SCG0_IRQHandler(void); WEAK void SPC0_IRQHandler(void); -WEAK void Reserved33_IRQHandler(void); +WEAK void TDET_IRQHandler(void); WEAK void WUU0_IRQHandler(void); WEAK void CAN0_IRQHandler(void); WEAK void Reserved36_IRQHandler(void); @@ -197,7 +197,7 @@ WEAK void Reserved121_IRQHandler(void); WEAK void Reserved122_IRQHandler(void); WEAK void MAU_IRQHandler(void); WEAK void SMARTDMA_IRQHandler(void); -WEAK void Reserved125_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); WEAK void Reserved126_IRQHandler(void); WEAK void Reserved127_IRQHandler(void); WEAK void Reserved128_IRQHandler(void); @@ -233,7 +233,7 @@ void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -325,7 +325,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -460,7 +460,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) MBC0_IRQHandler, // 30 : MBC secure violation interrupt SCG0_IRQHandler, // 31 : System Clock Generator interrupt SPC0_IRQHandler, // 32 : System Power Controller interrupt - Reserved33_IRQHandler, // 33 : Reserved interrupt + TDET_IRQHandler, // 33 : TDET interrrupt WUU0_IRQHandler, // 34 : Wake Up Unit interrupt CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt Reserved36_IRQHandler, // 36 : Reserved interrupt @@ -552,7 +552,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) Reserved122_IRQHandler, // 122: Reserved interrupt MAU_IRQHandler, // 123: MAU interrupt SMARTDMA_IRQHandler, // 124: SmartDMA interrupt - Reserved125_IRQHandler, // 125: Reserved interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt Reserved126_IRQHandler, // 126: Reserved interrupt Reserved127_IRQHandler, // 127: Reserved interrupt Reserved128_IRQHandler, // 128: Reserved interrupt @@ -935,9 +935,9 @@ WEAK void SPC0_IRQHandler(void) SPC0_DriverIRQHandler(); } -WEAK void Reserved33_IRQHandler(void) +WEAK void TDET_IRQHandler(void) { - Reserved33_DriverIRQHandler(); + TDET_DriverIRQHandler(); } WEAK void WUU0_IRQHandler(void) @@ -1395,9 +1395,9 @@ WEAK void SMARTDMA_IRQHandler(void) SMARTDMA_DriverIRQHandler(); } -WEAK void Reserved125_IRQHandler(void) +WEAK void CDOG1_IRQHandler(void) { - Reserved125_DriverIRQHandler(); + CDOG1_DriverIRQHandler(); } WEAK void Reserved126_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/startup_MCXA346.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/startup_MCXA346.cpp index a96376f92..2d8dd90e3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/startup_MCXA346.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/startup_MCXA346.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MCXA346 startup code // -// Version : 100625 +// Version : 300725 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -105,7 +105,7 @@ WEAK void GLIKEY0_IRQHandler(void); WEAK void MBC0_IRQHandler(void); WEAK void SCG0_IRQHandler(void); WEAK void SPC0_IRQHandler(void); -WEAK void Reserved33_IRQHandler(void); +WEAK void TDET_IRQHandler(void); WEAK void WUU0_IRQHandler(void); WEAK void CAN0_IRQHandler(void); WEAK void Reserved36_IRQHandler(void); @@ -197,7 +197,7 @@ WEAK void Reserved121_IRQHandler(void); WEAK void Reserved122_IRQHandler(void); WEAK void MAU_IRQHandler(void); WEAK void SMARTDMA_IRQHandler(void); -WEAK void Reserved125_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); WEAK void Reserved126_IRQHandler(void); WEAK void Reserved127_IRQHandler(void); WEAK void Reserved128_IRQHandler(void); @@ -233,7 +233,7 @@ void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved33_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -325,7 +325,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved125_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -460,7 +460,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) MBC0_IRQHandler, // 30 : MBC secure violation interrupt SCG0_IRQHandler, // 31 : System Clock Generator interrupt SPC0_IRQHandler, // 32 : System Power Controller interrupt - Reserved33_IRQHandler, // 33 : Reserved interrupt + TDET_IRQHandler, // 33 : TDET interrrupt WUU0_IRQHandler, // 34 : Wake Up Unit interrupt CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt Reserved36_IRQHandler, // 36 : Reserved interrupt @@ -552,7 +552,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) Reserved122_IRQHandler, // 122: Reserved interrupt MAU_IRQHandler, // 123: MAU interrupt SMARTDMA_IRQHandler, // 124: SmartDMA interrupt - Reserved125_IRQHandler, // 125: Reserved interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt Reserved126_IRQHandler, // 126: Reserved interrupt Reserved127_IRQHandler, // 127: Reserved interrupt Reserved128_IRQHandler, // 128: Reserved interrupt @@ -935,9 +935,9 @@ WEAK void SPC0_IRQHandler(void) SPC0_DriverIRQHandler(); } -WEAK void Reserved33_IRQHandler(void) +WEAK void TDET_IRQHandler(void) { - Reserved33_DriverIRQHandler(); + TDET_DriverIRQHandler(); } WEAK void WUU0_IRQHandler(void) @@ -1395,9 +1395,9 @@ WEAK void SMARTDMA_IRQHandler(void) SMARTDMA_DriverIRQHandler(); } -WEAK void Reserved125_IRQHandler(void) +WEAK void CDOG1_IRQHandler(void) { - Reserved125_DriverIRQHandler(); + CDOG1_DriverIRQHandler(); } WEAK void Reserved126_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/system_MCXA346.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/system_MCXA346.c index 40854c2ff..4abe8927b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/system_MCXA346.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/system_MCXA346.c @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250516 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/system_MCXA346.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/system_MCXA346.h index 12996ccf0..658cfa108 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/system_MCXA346.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/system_MCXA346.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250516 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/variable.cmake index 69c4c1304..d89589bbc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA346/variable.cmake @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/CMakeLists.txt new file mode 100644 index 000000000..92e7d0489 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA346/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/MCXA355.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/MCXA355.h new file mode 100644 index 000000000..1c3b33d42 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/MCXA355.h @@ -0,0 +1,91 @@ +/* +** ################################################################### +** Processors: MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA355 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA355.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA355 + * + * CMSIS Peripheral Access Layer for MCXA355 + */ + +#if !defined(MCXA355_H_) /* Check if memory map has not been already included */ +#define MCXA355_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MAU.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA355_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/MCXA355_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/MCXA355_COMMON.h new file mode 100644 index 000000000..a682a8843 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/MCXA355_COMMON.h @@ -0,0 +1,876 @@ +/* +** ################################################################### +** Processors: MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA355 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA355_COMMON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA355 + * + * CMSIS Peripheral Access Layer for MCXA355 + */ + +#if !defined(MCXA355_COMMON_H_) +#define MCXA355_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + Reserved36_IRQn = 20, /**< Reserved interrupt */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + Reserved40_IRQn = 24, /**< Reserved interrupt */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit 4 interrupt */ + Reserved52_IRQn = 36, /**< Reserved interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + CMP2_IRQn = 66, /**< Comparator 2 interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit 3 interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + LPUART5_IRQn = 95, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ + Reserved126_IRQn = 110, /**< Reserved interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + Reserved129_IRQn = 113, /**< Reserved interrupt */ + Reserved130_IRQn = 114, /**< Reserved interrupt */ + ADC2_IRQn = 116, /**< Analog-to-Digital Converter 2 interrupt */ + ADC3_IRQn = 117, /**< Analog-to-Digital Converter 3 interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + Reserved137_IRQn = 121 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA355.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA355_SERIES +#define MCXA355_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA355_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Peripheral ADC2 base address */ +#define ADC2_BASE (0x400F0000u) +/** Peripheral ADC2 base pointer */ +#define ADC2 ((ADC_Type *)ADC2_BASE) +/** Peripheral ADC3 base address */ +#define ADC3_BASE (0x400F1000u) +/** Peripheral ADC3 base pointer */ +#define ADC3 ((ADC_Type *)ADC3_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE, ADC2_BASE, ADC3_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1, ADC2, ADC3 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn, ADC2_IRQn, ADC3_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x400B3000u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((LPCMP_Type *)CMP2_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x400DA000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } + +/* MAU - Peripheral instance base addresses */ +/** Peripheral MAU0 base address */ +#define MAU0_BASE (0x40108000u) +/** Peripheral MAU0 base pointer */ +#define MAU0 ((MAU_Type *)MAU0_BASE) +/** Array initializer of MAU peripheral base addresses */ +#define MAU_BASE_ADDRS { MAU0_BASE } +/** Array initializer of MAU peripheral base pointers */ +#define MAU_BASE_PTRS { MAU0 } +/** Interrupt vectors for the MAU peripheral type */ +#define MAU_IRQS { MAU_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Peripheral OPAMP1 base address */ +#define OPAMP1_BASE (0x400B8000u) +/** Peripheral OPAMP1 base pointer */ +#define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) +/** Peripheral OPAMP2 base address */ +#define OPAMP2_BASE (0x400B9000u) +/** Peripheral OPAMP2 base pointer */ +#define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) +/** Peripheral OPAMP3 base address */ +#define OPAMP3_BASE (0x400BA000u) +/** Peripheral OPAMP3 base pointer */ +#define OPAMP3 ((OPAMP_Type *)OPAMP3_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE, OPAMP3_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2, OPAMP3 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA355_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/MCXA355_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/MCXA355_features.h new file mode 100644 index 000000000..e28f52723 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/MCXA355_features.h @@ -0,0 +1,858 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA355_FEATURES_H_ +#define _MCXA355_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (4) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (4) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MAU module features */ + +/* No feature definitions */ + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (516096) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA355_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/fsl_device_registers.h new file mode 100644 index 000000000..62e13f5cc --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/startup_MCXA355.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/startup_MCXA355.c new file mode 100644 index 000000000..a53430e01 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/startup_MCXA355.c @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA355 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void Reserved40_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void Reserved52_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void ADC3_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC2_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA355 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + Reserved39_IRQHandler, // 39 : Reserved interrupt + Reserved40_IRQHandler, // 40 : Reserved interrupt + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + Reserved52_IRQHandler, // 52 : Reserved interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + ADC2_IRQHandler, // 132: Analog-to-Digital Converter 2 interrupt + ADC3_IRQHandler, // 133: Analog-to-Digital Converter 3 interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ + Reserved39_DriverIRQHandler(); +} + +WEAK void Reserved40_IRQHandler(void) +{ + Reserved40_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void Reserved52_IRQHandler(void) +{ + Reserved52_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ + ADC2_DriverIRQHandler(); +} + +WEAK void ADC3_IRQHandler(void) +{ + ADC3_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/startup_MCXA355.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/startup_MCXA355.cpp new file mode 100644 index 000000000..a53430e01 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/startup_MCXA355.cpp @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA355 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void Reserved40_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void Reserved52_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void ADC3_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC2_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA355 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + Reserved39_IRQHandler, // 39 : Reserved interrupt + Reserved40_IRQHandler, // 40 : Reserved interrupt + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + Reserved52_IRQHandler, // 52 : Reserved interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + ADC2_IRQHandler, // 132: Analog-to-Digital Converter 2 interrupt + ADC3_IRQHandler, // 133: Analog-to-Digital Converter 3 interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ + Reserved39_DriverIRQHandler(); +} + +WEAK void Reserved40_IRQHandler(void) +{ + Reserved40_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void Reserved52_IRQHandler(void) +{ + Reserved52_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ + ADC2_DriverIRQHandler(); +} + +WEAK void ADC3_IRQHandler(void) +{ + ADC3_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/system_MCXA355.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/system_MCXA355.c new file mode 100644 index 000000000..c0a84ab07 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/system_MCXA355.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA355 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA355 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/system_MCXA355.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/system_MCXA355.h new file mode 100644 index 000000000..9efb9b40c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/system_MCXA355.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA355 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA355 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA355_H_ +#define _SYSTEM_MCXA355_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA355_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/variable.cmake new file mode 100644 index 000000000..6c90fb433 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA355/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA355) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph2) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/CMakeLists.txt new file mode 100644 index 000000000..92e7d0489 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA346/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/MCXA356.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/MCXA356.h new file mode 100644 index 000000000..a362f9e3d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/MCXA356.h @@ -0,0 +1,91 @@ +/* +** ################################################################### +** Processors: MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA356 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA356.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA356 + * + * CMSIS Peripheral Access Layer for MCXA356 + */ + +#if !defined(MCXA356_H_) /* Check if memory map has not been already included */ +#define MCXA356_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MAU.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA356_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/MCXA356_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/MCXA356_COMMON.h new file mode 100644 index 000000000..647967b18 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/MCXA356_COMMON.h @@ -0,0 +1,876 @@ +/* +** ################################################################### +** Processors: MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA356 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA356_COMMON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA356 + * + * CMSIS Peripheral Access Layer for MCXA356 + */ + +#if !defined(MCXA356_COMMON_H_) +#define MCXA356_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + Reserved36_IRQn = 20, /**< Reserved interrupt */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + Reserved40_IRQn = 24, /**< Reserved interrupt */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit 4 interrupt */ + Reserved52_IRQn = 36, /**< Reserved interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + CMP2_IRQn = 66, /**< Comparator 2 interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit 3 interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + LPUART5_IRQn = 95, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ + Reserved126_IRQn = 110, /**< Reserved interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + Reserved129_IRQn = 113, /**< Reserved interrupt */ + Reserved130_IRQn = 114, /**< Reserved interrupt */ + ADC2_IRQn = 116, /**< Analog-to-Digital Converter 2 interrupt */ + ADC3_IRQn = 117, /**< Analog-to-Digital Converter 3 interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + Reserved137_IRQn = 121 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA356.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA356_SERIES +#define MCXA356_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA356_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Peripheral ADC2 base address */ +#define ADC2_BASE (0x400F0000u) +/** Peripheral ADC2 base pointer */ +#define ADC2 ((ADC_Type *)ADC2_BASE) +/** Peripheral ADC3 base address */ +#define ADC3_BASE (0x400F1000u) +/** Peripheral ADC3 base pointer */ +#define ADC3 ((ADC_Type *)ADC3_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE, ADC2_BASE, ADC3_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1, ADC2, ADC3 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn, ADC2_IRQn, ADC3_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x400B3000u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((LPCMP_Type *)CMP2_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x400DA000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } + +/* MAU - Peripheral instance base addresses */ +/** Peripheral MAU0 base address */ +#define MAU0_BASE (0x40108000u) +/** Peripheral MAU0 base pointer */ +#define MAU0 ((MAU_Type *)MAU0_BASE) +/** Array initializer of MAU peripheral base addresses */ +#define MAU_BASE_ADDRS { MAU0_BASE } +/** Array initializer of MAU peripheral base pointers */ +#define MAU_BASE_PTRS { MAU0 } +/** Interrupt vectors for the MAU peripheral type */ +#define MAU_IRQS { MAU_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Peripheral OPAMP1 base address */ +#define OPAMP1_BASE (0x400B8000u) +/** Peripheral OPAMP1 base pointer */ +#define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) +/** Peripheral OPAMP2 base address */ +#define OPAMP2_BASE (0x400B9000u) +/** Peripheral OPAMP2 base pointer */ +#define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) +/** Peripheral OPAMP3 base address */ +#define OPAMP3_BASE (0x400BA000u) +/** Peripheral OPAMP3 base pointer */ +#define OPAMP3 ((OPAMP_Type *)OPAMP3_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE, OPAMP3_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2, OPAMP3 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA356_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/MCXA356_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/MCXA356_features.h new file mode 100644 index 000000000..fa7c5a7a1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/MCXA356_features.h @@ -0,0 +1,858 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA356_FEATURES_H_ +#define _MCXA356_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (4) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (4) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MAU module features */ + +/* No feature definitions */ + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1040384) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA356_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/fsl_device_registers.h new file mode 100644 index 000000000..334cbe26c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/startup_MCXA356.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/startup_MCXA356.c new file mode 100644 index 000000000..16b395f43 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/startup_MCXA356.c @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA356 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void Reserved40_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void Reserved52_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void ADC3_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC2_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA356 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + Reserved39_IRQHandler, // 39 : Reserved interrupt + Reserved40_IRQHandler, // 40 : Reserved interrupt + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + Reserved52_IRQHandler, // 52 : Reserved interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + ADC2_IRQHandler, // 132: Analog-to-Digital Converter 2 interrupt + ADC3_IRQHandler, // 133: Analog-to-Digital Converter 3 interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ + Reserved39_DriverIRQHandler(); +} + +WEAK void Reserved40_IRQHandler(void) +{ + Reserved40_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void Reserved52_IRQHandler(void) +{ + Reserved52_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ + ADC2_DriverIRQHandler(); +} + +WEAK void ADC3_IRQHandler(void) +{ + ADC3_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/startup_MCXA356.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/startup_MCXA356.cpp new file mode 100644 index 000000000..16b395f43 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/startup_MCXA356.cpp @@ -0,0 +1,1464 @@ +//***************************************************************************** +// MCXA356 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved36_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void Reserved40_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void Reserved52_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void Reserved126_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void Reserved129_IRQHandler(void); +WEAK void Reserved130_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void ADC3_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved36_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved39_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved40_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved52_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved126_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved127_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved129_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved130_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC2_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA356 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + Reserved36_IRQHandler, // 36 : Reserved interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + Reserved39_IRQHandler, // 39 : Reserved interrupt + Reserved40_IRQHandler, // 40 : Reserved interrupt + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + Reserved52_IRQHandler, // 52 : Reserved interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + Reserved126_IRQHandler, // 126: Reserved interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + Reserved129_IRQHandler, // 129: Reserved interrupt + Reserved130_IRQHandler, // 130: Reserved interrupt + Reserved131_IRQHandler, // 131: Reserved interrupt + ADC2_IRQHandler, // 132: Analog-to-Digital Converter 2 interrupt + ADC3_IRQHandler, // 133: Analog-to-Digital Converter 3 interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void Reserved36_IRQHandler(void) +{ + Reserved36_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ + Reserved39_DriverIRQHandler(); +} + +WEAK void Reserved40_IRQHandler(void) +{ + Reserved40_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void Reserved52_IRQHandler(void) +{ + Reserved52_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void Reserved126_IRQHandler(void) +{ + Reserved126_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ + Reserved127_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void Reserved129_IRQHandler(void) +{ + Reserved129_DriverIRQHandler(); +} + +WEAK void Reserved130_IRQHandler(void) +{ + Reserved130_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ + ADC2_DriverIRQHandler(); +} + +WEAK void ADC3_IRQHandler(void) +{ + ADC3_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/system_MCXA356.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/system_MCXA356.c new file mode 100644 index 000000000..ae4e165be --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/system_MCXA356.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA356 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA356 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/system_MCXA356.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/system_MCXA356.h new file mode 100644 index 000000000..ab0e192f9 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/system_MCXA356.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA356 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA356 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA356_H_ +#define _SYSTEM_MCXA356_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA356_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/variable.cmake new file mode 100644 index 000000000..0ba7ce8b3 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA356/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA356) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph2) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/CMakeLists.txt new file mode 100644 index 000000000..92e7d0489 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_cstartup.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXA/MCXA346/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/MCXA365.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/MCXA365.h new file mode 100644 index 000000000..5f7d18784 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/MCXA365.h @@ -0,0 +1,99 @@ +/* +** ################################################################### +** Processors: MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA365 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA365.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA365 + * + * CMSIS Peripheral Access Layer for MCXA365 + */ + +#if !defined(MCXA365_H_) /* Check if memory map has not been already included */ +#define MCXA365_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AOI.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DEBUGMAILBOX.h" +#include "PERI_DIGTMP.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EQDC.h" +#include "PERI_ERM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FMC.h" +#include "PERI_FMU.h" +#include "PERI_FREQME.h" +#include "PERI_GLIKEY.h" +#include "PERI_GPIO.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_LCD.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_MAU.h" +#include "PERI_MRCC.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_SCG.h" +#include "PERI_SGI.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_TRDC.h" +#include "PERI_TRNG.h" +#include "PERI_UDF.h" +#include "PERI_USB.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_WAKETIMER.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXA365_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/MCXA365_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/MCXA365_COMMON.h new file mode 100644 index 000000000..b7ab0440f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/MCXA365_COMMON.h @@ -0,0 +1,972 @@ +/* +** ################################################################### +** Processors: MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA365 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA365_COMMON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MCXA365 + * + * CMSIS Peripheral Access Layer for MCXA365 + */ + +#if !defined(MCXA365_COMMON_H_) +#define MCXA365_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 138 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + TDET_IRQn = 17, /**< TDET interrrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + CAN1_IRQn = 20, /**< Controller Area Network 1 interrupt */ + FLEXIO_IRQn = 23, /**< Flexible Input/Output interrupt */ + I3C0_IRQn = 24, /**< Improved Inter Integrated Circuit interrupt 0 */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit 0 interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit 1 interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface 0 interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface 1 interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit 0 interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit 1 interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit 2 interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit 3 interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit 4 interrupt */ + USB0_IRQn = 36, /**< Universal Serial Bus - Full Speed interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 49, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + EQDC0_COMPARE_IRQn = 50, /**< Compare */ + EQDC0_HOME_IRQn = 51, /**< Home */ + EQDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + EQDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter 0 interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter 1 interrupt */ + CMP0_IRQn = 64, /**< Comparator 0 interrupt */ + CMP1_IRQn = 65, /**< Comparator 1 interrupt */ + CMP2_IRQn = 66, /**< Comparator 2 interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit 3 interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 84, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + EQDC1_COMPARE_IRQn = 85, /**< Compare */ + EQDC1_HOME_IRQn = 86, /**< Home */ + EQDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + EQDC1_INDEX_IRQn = 88, /**< Index / Roll Over / Roll Under */ + LPUART5_IRQn = 95, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + MAU_IRQn = 107, /**< MAU interrupt */ + SMARTDMA_IRQn = 108, /**< SmartDMA interrupt */ + CDOG1_IRQn = 109, /**< Code Watchdog Timer 1 interrupt */ + PKC_IRQn = 110, /**< PKC interrupt */ + SGI_IRQn = 111, /**< SGI interrupt */ + TRNG0_IRQn = 113, /**< True Random Number Generator interrupt */ + SECURE_ERR_IRQn = 114, /**< Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. */ + ADC2_IRQn = 116, /**< Analog-to-Digital Converter 2 interrupt */ + ADC3_IRQn = 117, /**< Analog-to-Digital Converter 3 interrupt */ + RTC_IRQn = 119, /**< RTC alarm interrupt */ + RTC_1HZ_IRQn = 120, /**< RTC 1Hz interrupt */ + LCD_IRQn = 121 /**< SLCD frame start interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA365.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXA365_SERIES +#define MCXA365_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXA365_features.h" + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Peripheral ADC2 base address */ +#define ADC2_BASE (0x400F0000u) +/** Peripheral ADC2 base pointer */ +#define ADC2 ((ADC_Type *)ADC2_BASE) +/** Peripheral ADC3 base address */ +#define ADC3_BASE (0x400F1000u) +/** Peripheral ADC3 base pointer */ +#define ADC3 ((ADC_Type *)ADC3_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE, ADC2_BASE, ADC3_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1, ADC2, ADC3 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn, ADC2_IRQn, ADC3_IRQn } + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x400D0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0, CAN1 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn, CAN1_IRQn } + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG0 base address */ +#define CDOG0_BASE (0x40100000u) +/** Peripheral CDOG0 base pointer */ +#define CDOG0 ((CDOG_Type *)CDOG0_BASE) +/** Peripheral CDOG1 base address */ +#define CDOG1_BASE (0x40107000u) +/** Peripheral CDOG1 base pointer */ +#define CDOG1 ((CDOG_Type *)CDOG1_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG0, CDOG1 } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/* DIGTMP - Peripheral instance base addresses */ +/** Peripheral TDET0 base address */ +#define TDET0_BASE (0x400E9000u) +/** Peripheral TDET0 base pointer */ +#define TDET0 ((DIGTMP_Type *)TDET0_BASE) +/** Array initializer of DIGTMP peripheral base addresses */ +#define DIGTMP_BASE_ADDRS { TDET0_BASE } +/** Array initializer of DIGTMP peripheral base pointers */ +#define DIGTMP_BASE_PTRS { TDET0 } + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral EQDC0 base address */ +#define EQDC0_BASE (0x400A7000u) +/** Peripheral EQDC0 base pointer */ +#define EQDC0 ((EQDC_Type *)EQDC0_BASE) +/** Peripheral EQDC1 base address */ +#define EQDC1_BASE (0x400A8000u) +/** Peripheral EQDC1 base pointer */ +#define EQDC1 ((EQDC_Type *)EQDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { EQDC0_BASE, EQDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { EQDC0, EQDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { EQDC0_COMPARE_IRQn, EQDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { EQDC0_HOME_IRQn, EQDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { EQDC0_INDEX_IRQn, EQDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { EQDC0_WATCHDOG_IRQn, EQDC1_WATCHDOG_IRQn } + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO0 base address */ +#define FLEXIO0_BASE (0x40099000u) +/** Peripheral FLEXIO0 base pointer */ +#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO0 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C0 base address */ +#define I3C0_BASE (0x40002000u) +/** Peripheral I3C0 base pointer */ +#define I3C0 ((I3C_Type *)I3C0_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { I3C0_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { I3C0 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/* LCD - Peripheral instance base addresses */ +/** Peripheral LCD0 base address */ +#define LCD0_BASE (0x400C2000u) +/** Peripheral LCD0 base pointer */ +#define LCD0 ((LCD_Type *)LCD0_BASE) +/** Array initializer of LCD peripheral base addresses */ +#define LCD_BASE_ADDRS { LCD0_BASE } +/** Array initializer of LCD peripheral base pointers */ +#define LCD_BASE_PTRS { LCD0 } +/** Interrupt vectors for the LCD peripheral type */ +#define LCD_IRQS { LCD_IRQn } +/* Backward compatibility */ +#define LCD_WFOVERLAY_WFACCESS8BIT_WF8B_COUNT LCD_WF_ACCESS_WF8BIT_WF8B_COUNT +#define LCD_WFOVERLAY_WFACCESS32BIT_WF_COUNT LCD_WF_ACCESS_WF32BIT_WF_COUNT + + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x400B3000u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((LPCMP_Type *)CMP2_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x400DA000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn } + +/* MAU - Peripheral instance base addresses */ +/** Peripheral MAU0 base address */ +#define MAU0_BASE (0x40108000u) +/** Peripheral MAU0 base pointer */ +#define MAU0 ((MAU_Type *)MAU0_BASE) +/** Array initializer of MAU peripheral base addresses */ +#define MAU_BASE_ADDRS { MAU0_BASE } +/** Array initializer of MAU peripheral base pointers */ +#define MAU_BASE_PTRS { MAU0 } +/** Interrupt vectors for the MAU peripheral type */ +#define MAU_IRQS { MAU_IRQn } + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Peripheral OPAMP1 base address */ +#define OPAMP1_BASE (0x400B8000u) +/** Peripheral OPAMP1 base pointer */ +#define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) +/** Peripheral OPAMP2 base address */ +#define OPAMP2_BASE (0x400B9000u) +/** Peripheral OPAMP2 base pointer */ +#define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) +/** Peripheral OPAMP3 base address */ +#define OPAMP3_BASE (0x400BA000u) +/** Peripheral OPAMP3 base pointer */ +#define OPAMP3 ((OPAMP_Type *)OPAMP3_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE, OPAMP3_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2, OPAMP3 } + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* PKC - Peripheral instance base addresses */ +/** Peripheral PKC0 base address */ +#define PKC0_BASE (0x400EA000u) +/** Peripheral PKC0 base pointer */ +#define PKC0 ((PKC_Type *)PKC0_BASE) +/** Array initializer of PKC peripheral base addresses */ +#define PKC_BASE_ADDRS { PKC0_BASE } +/** Array initializer of PKC peripheral base pointers */ +#define PKC_BASE_PTRS { PKC0 } + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC0 base address */ +#define RTC0_BASE (0x400EE000u) +/** Peripheral RTC0 base pointer */ +#define RTC0 ((RTC_Type *)RTC0_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC0_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC0 } + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/* SGI - Peripheral instance base addresses */ +/** Peripheral SGI0 base address */ +#define SGI0_BASE (0x400EB000u) +/** Peripheral SGI0 base pointer */ +#define SGI0 ((SGI_Type *)SGI0_BASE) +/** Array initializer of SGI peripheral base addresses */ +#define SGI_BASE_ADDRS { SGI0_BASE } +/** Array initializer of SGI peripheral base pointers */ +#define SGI_BASE_PTRS { SGI0 } + +/* SMARTDMA - Peripheral instance base addresses */ +/** Peripheral SMARTDMA0 base address */ +#define SMARTDMA0_BASE (0x4000E000u) +/** Peripheral SMARTDMA0 base pointer */ +#define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) +/** Array initializer of SMARTDMA peripheral base addresses */ +#define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } +/** Array initializer of SMARTDMA peripheral base pointers */ +#define SMARTDMA_BASE_PTRS { SMARTDMA0 } + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TRNG - Peripheral instance base addresses */ +/** Peripheral TRNG0 base address */ +#define TRNG0_BASE (0x400EC000u) +/** Peripheral TRNG0 base pointer */ +#define TRNG0 ((TRNG_Type *)TRNG0_BASE) +/** Array initializer of TRNG peripheral base addresses */ +#define TRNG_BASE_ADDRS { TRNG0_BASE } +/** Array initializer of TRNG peripheral base pointers */ +#define TRNG_BASE_PTRS { TRNG0 } + +/* UDF - Peripheral instance base addresses */ +/** Peripheral UDF0 base address */ +#define UDF0_BASE (0x400ED000u) +/** Peripheral UDF0 base pointer */ +#define UDF0 ((UDF_Type *)UDF0_BASE) +/** Array initializer of UDF peripheral base addresses */ +#define UDF_BASE_ADDRS { UDF0_BASE } +/** Array initializer of UDF peripheral base pointers */ +#define UDF_BASE_PTRS { UDF0 } + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x400A4000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA365_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/MCXA365_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/MCXA365_features.h new file mode 100644 index 000000000..474dc4e84 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/MCXA365_features.h @@ -0,0 +1,995 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-03-26 +** Build: b250814 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** +** ################################################################### +*/ + +#ifndef _MCXA365_FEATURES_H_ +#define _MCXA365_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (4) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (4) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (1) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (0) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x01100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* SLCD module features */ + +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MAU module features */ + +/* No feature definitions */ + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (0) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (0) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (0) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (0) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (0) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (0) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) +/* @brief Has Power Request Status Flag */ +#define FSL_FEATURE_MCX_SPC_HAS_PD_STATUS_PWR_REQ_STATUS_BIT (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (516096) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief ROMAPI tree address */ +#define FSL_FEATURE_ROMAPI_BASE (0x03005FE0U) +/* @brief ROMAPI support IFR function */ +#define FSL_FEATURE_ROMAPI_IFR (0) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (0) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (0) +/* @brief FIRC support 240M */ +#define FSL_FEATURE_FIRC_SUPPORT_240M (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRNG module features */ + +/* @brief TRNG does not support SCR4L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (0) +/* @brief TRNG does not support SCR5L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (0) +/* @brief TRNG does not support SCR6L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) +/* @brief TRNG does not support PKRMAX. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (0) +/* @brief TRNG does not support SAMP mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) +/* @brief TRNG does not support ACC. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) +/* @brief TRNG does not support SBLIM. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (0) +/* @brief TRNG supports reset control. */ +#define FSL_FEATURE_TRNG_HAS_RSTCTL (0) +/* @brief TRNG does not support FOR_CLK mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1) +/* @brief TRNG has two oscillators. */ +#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXA365_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/fsl_device_registers.h new file mode 100644 index 000000000..5fdfff645 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/startup_MCXA365.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/startup_MCXA365.c new file mode 100644 index 000000000..8d4dbec49 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/startup_MCXA365.c @@ -0,0 +1,1472 @@ +//***************************************************************************** +// MCXA365 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void SGI_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void TRNG0_IRQHandler(void); +WEAK void SECURE_ERR_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void ADC3_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); +WEAK void LCD_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void PKC_DriverIRQHandler(void) ALIAS(DefaultISR); +void SGI_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void TRNG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SECURE_ERR_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC2_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); +void LCD_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA365 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 36 : Controller Area Network 1 interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + PKC_IRQHandler, // 126: PKC interrupt + SGI_IRQHandler, // 127: SGI interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + TRNG0_IRQHandler, // 129: True Random Number Generator interrupt + SECURE_ERR_IRQHandler, // 130: Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. + Reserved131_IRQHandler, // 131: Reserved interrupt + ADC2_IRQHandler, // 132: Analog-to-Digital Converter 2 interrupt + ADC3_IRQHandler, // 133: Analog-to-Digital Converter 3 interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt + LCD_IRQHandler, // 137: SLCD frame start interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ + CAN1_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ + PKC_DriverIRQHandler(); +} + +WEAK void SGI_IRQHandler(void) +{ + SGI_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void TRNG0_IRQHandler(void) +{ + TRNG0_DriverIRQHandler(); +} + +WEAK void SECURE_ERR_IRQHandler(void) +{ + SECURE_ERR_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ + ADC2_DriverIRQHandler(); +} + +WEAK void ADC3_IRQHandler(void) +{ + ADC3_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +WEAK void LCD_IRQHandler(void) +{ + LCD_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/startup_MCXA365.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/startup_MCXA365.cpp new file mode 100644 index 000000000..8d4dbec49 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/startup_MCXA365.cpp @@ -0,0 +1,1472 @@ +//***************************************************************************** +// MCXA365 startup code +// +// Version : 300725 +//***************************************************************************** +// +// Copyright 2016-2025 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** +#include + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("Og") +#endif //(__GNUC__) +#endif //(DEBUG) + +#if defined(__cplusplus) +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { +extern void __libc_init_array(void); +} +#endif //(__REDLIB__) +#endif //(__MCUXPRESSO) +#endif //(__cplusplus) + +#define WEAK __attribute__((weak)) +#if defined(__MCUXPRESSO) +#define WEAK_AV __attribute__((weak, section(".after_vectors"))) +#else +#define WEAK_AV __attribute__((weak)) +#endif //(__MCUXPRESSO) +#define ALIAS(f) __attribute__((weak, alias(#f))) + +//***************************************************************************** +#if defined(__cplusplus) +extern "C" { +#endif //(__cplusplus) + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +extern void SystemInit(void); + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** +#if defined(__MCUXPRESSO) +void ResetISR(void); +#else +void Reset_Handler(void); +#endif //(__MCUXPRESSO) +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void DefaultISR(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void); +WEAK void CMC_IRQHandler(void); +WEAK void DMA_CH0_IRQHandler(void); +WEAK void DMA_CH1_IRQHandler(void); +WEAK void DMA_CH2_IRQHandler(void); +WEAK void DMA_CH3_IRQHandler(void); +WEAK void DMA_CH4_IRQHandler(void); +WEAK void DMA_CH5_IRQHandler(void); +WEAK void DMA_CH6_IRQHandler(void); +WEAK void DMA_CH7_IRQHandler(void); +WEAK void ERM0_SINGLE_BIT_IRQHandler(void); +WEAK void ERM0_MULTI_BIT_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void GLIKEY0_IRQHandler(void); +WEAK void MBC0_IRQHandler(void); +WEAK void SCG0_IRQHandler(void); +WEAK void SPC0_IRQHandler(void); +WEAK void TDET_IRQHandler(void); +WEAK void WUU0_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved37_IRQHandler(void); +WEAK void Reserved38_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void LPI2C0_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPSPI0_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void LPUART0_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void Reserved53_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void EQDC0_COMPARE_IRQHandler(void); +WEAK void EQDC0_HOME_IRQHandler(void); +WEAK void EQDC0_WATCHDOG_IRQHandler(void); +WEAK void EQDC0_INDEX_IRQHandler(void); +WEAK void FREQME0_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void Reserved72_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void WAKETIMER0_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void CMP0_IRQHandler(void); +WEAK void CMP1_IRQHandler(void); +WEAK void CMP2_IRQHandler(void); +WEAK void DAC0_IRQHandler(void); +WEAK void Reserved84_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void GPIO0_IRQHandler(void); +WEAK void GPIO1_IRQHandler(void); +WEAK void GPIO2_IRQHandler(void); +WEAK void GPIO3_IRQHandler(void); +WEAK void GPIO4_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void EQDC1_COMPARE_IRQHandler(void); +WEAK void EQDC1_HOME_IRQHandler(void); +WEAK void EQDC1_WATCHDOG_IRQHandler(void); +WEAK void EQDC1_INDEX_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void Reserved109_IRQHandler(void); +WEAK void Reserved110_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void Reserved112_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void Reserved114_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void Reserved116_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void Reserved121_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void MAU_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void SGI_IRQHandler(void); +WEAK void Reserved128_IRQHandler(void); +WEAK void TRNG0_IRQHandler(void); +WEAK void SECURE_ERR_IRQHandler(void); +WEAK void Reserved131_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void ADC3_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void RTC_1HZ_IRQHandler(void); +WEAK void LCD_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the DefaultISR, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void Reserved16_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMC_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH3_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH4_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH5_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH6_DriverIRQHandler(void) ALIAS(DefaultISR); +void DMA_CH7_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_SINGLE_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void ERM0_MULTI_BIT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FMU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GLIKEY0_DriverIRQHandler(void) ALIAS(DefaultISR); +void MBC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SCG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SPC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void TDET_DriverIRQHandler(void) ALIAS(DefaultISR); +void WUU0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CAN1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved37_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved38_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); +void I3C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved41_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPSPI1_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved46_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART1_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART3_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART4_DriverIRQHandler(void) ALIAS(DefaultISR); +void USB0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved53_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER2_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER3_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTIMER4_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC0_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void FREQME0_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPTMR0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); +void OS_EVENT_DriverIRQHandler(void) ALIAS(DefaultISR); +void WAKETIMER0_DriverIRQHandler(void) ALIAS(DefaultISR); +void UTICK0_DriverIRQHandler(void) ALIAS(DefaultISR); +void WWDT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved77_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP1_DriverIRQHandler(void) ALIAS(DefaultISR); +void CMP2_DriverIRQHandler(void) ALIAS(DefaultISR); +void DAC0_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved84_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved85_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved86_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO0_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO1_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO2_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO3_DriverIRQHandler(void) ALIAS(DefaultISR); +void GPIO4_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved92_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C2_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPI2C3_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(DefaultISR); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_COMPARE_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_HOME_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_WATCHDOG_DriverIRQHandler(void) ALIAS(DefaultISR); +void EQDC1_INDEX_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved105_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved106_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved107_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved108_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved109_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved110_DriverIRQHandler(void) ALIAS(DefaultISR); +void LPUART5_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved112_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved113_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved114_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved115_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved116_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved117_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved118_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved119_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved120_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); +void MAU_DriverIRQHandler(void) ALIAS(DefaultISR); +void SMARTDMA_DriverIRQHandler(void) ALIAS(DefaultISR); +void CDOG1_DriverIRQHandler(void) ALIAS(DefaultISR); +void PKC_DriverIRQHandler(void) ALIAS(DefaultISR); +void SGI_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved128_DriverIRQHandler(void) ALIAS(DefaultISR); +void TRNG0_DriverIRQHandler(void) ALIAS(DefaultISR); +void SECURE_ERR_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved131_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC2_DriverIRQHandler(void) ALIAS(DefaultISR); +void ADC3_DriverIRQHandler(void) ALIAS(DefaultISR); +void Reserved134_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_DriverIRQHandler(void) ALIAS(DefaultISR); +void RTC_1HZ_DriverIRQHandler(void) ALIAS(DefaultISR); +void LCD_DriverIRQHandler(void) ALIAS(DefaultISR); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined(__MCUXPRESSO) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) +extern void __iar_program_start(void); +#elif defined(__GNUC__) +#if defined(__REDLIB__) +extern void __main(void); +#else +extern void _start(void); +#endif //(__REDLIB__) +#else +#error Unsupported toolchain! +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// External declaration for the pointer from the Linker Script +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; +#define _vStackTop Image$$ARM_LIB_STACK$$ZI$$Limit +#define _vStackBase Image$$ARM_LIB_STACK$$ZI$$Base +#elif defined(__MCUXPRESSO) +extern void _vStackTop(void); +extern void _vStackBase(void); +#define Reset_Handler ResetISR // To be compatible with other compilers +#elif defined(__ICCARM__) +#pragma segment = "CSTACK" +#define _vStackTop __section_end("CSTACK") +#define _vStackBase __section_begin("CSTACK") +#elif defined(__GNUC__) +extern uint32_t __StackTop[]; +extern uint32_t __StackLimit[]; + +#define _vStackTop __StackTop +#define _vStackBase __StackLimit + +extern uint32_t __etext[]; +extern uint32_t __data_start__[]; +extern uint32_t __data_end__[]; + +extern uint32_t __bss_start__[]; +extern uint32_t __bss_end__[]; +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + +//***************************************************************************** +#if defined(__cplusplus) +} // extern "C" +#endif //(__cplusplus) +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void (*const __Vectors[])(void); +#define __vector_table __Vectors +__attribute__((used, section(".isr_vector"))) void (*const __Vectors[])(void) = { +#elif defined(__MCUXPRESSO) +extern void (*const g_pfnVectors[])(void); +extern void *__Vectors __attribute__((alias("g_pfnVectors"))); +#define __vector_table g_pfnVectors +__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { +#elif defined(__ICCARM__) +extern void (*const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); +__attribute__((used, section(".intvec"))) void (*const __vector_table[])(void) = { +#elif defined(__GNUC__) +extern void (*const __isr_vector[])(void); +#define __vector_table __isr_vector +__attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) = { +#else +#error Unsupported toolchain! +#endif //(__CC_ARM) || (__ARMCC_VERSION) + // Core Level - CM33 + (void (*)())((uint32_t)_vStackTop), // The initial stack pointer + Reset_Handler, // The reset handler + + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXA365 + Reserved16_IRQHandler, // 16 : Reserved interrupt + CMC_IRQHandler, // 17 : Core Mode Controller interrupt + DMA_CH0_IRQHandler, // 18 : DMA3_0_CH0 error or transfer complete + DMA_CH1_IRQHandler, // 19 : DMA3_0_CH1 error or transfer complete + DMA_CH2_IRQHandler, // 20 : DMA3_0_CH2 error or transfer complete + DMA_CH3_IRQHandler, // 21 : DMA3_0_CH3 error or transfer complete + DMA_CH4_IRQHandler, // 22 : DMA3_0_CH4 error or transfer complete + DMA_CH5_IRQHandler, // 23 : DMA3_0_CH5 error or transfer complete + DMA_CH6_IRQHandler, // 24 : DMA3_0_CH6 error or transfer complete + DMA_CH7_IRQHandler, // 25 : DMA3_0_CH7 error or transfer complete + ERM0_SINGLE_BIT_IRQHandler, // 26 : ERM Single Bit error interrupt + ERM0_MULTI_BIT_IRQHandler, // 27 : ERM Multi Bit error interrupt + FMU0_IRQHandler, // 28 : Flash Management Unit interrupt + GLIKEY0_IRQHandler, // 29 : GLIKEY Interrupt + MBC0_IRQHandler, // 30 : MBC secure violation interrupt + SCG0_IRQHandler, // 31 : System Clock Generator interrupt + SPC0_IRQHandler, // 32 : System Power Controller interrupt + TDET_IRQHandler, // 33 : TDET interrrupt + WUU0_IRQHandler, // 34 : Wake Up Unit interrupt + CAN0_IRQHandler, // 35 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 36 : Controller Area Network 1 interrupt + Reserved37_IRQHandler, // 37 : Reserved interrupt + Reserved38_IRQHandler, // 38 : Reserved interrupt + FLEXIO_IRQHandler, // 39 : Flexible Input/Output interrupt + I3C0_IRQHandler, // 40 : Improved Inter Integrated Circuit interrupt 0 + Reserved41_IRQHandler, // 41 : Reserved interrupt + LPI2C0_IRQHandler, // 42 : Low-Power Inter Integrated Circuit 0 interrupt + LPI2C1_IRQHandler, // 43 : Low-Power Inter Integrated Circuit 1 interrupt + LPSPI0_IRQHandler, // 44 : Low-Power Serial Peripheral Interface 0 interrupt + LPSPI1_IRQHandler, // 45 : Low-Power Serial Peripheral Interface 1 interrupt + Reserved46_IRQHandler, // 46 : Reserved interrupt + LPUART0_IRQHandler, // 47 : Low-Power Universal Asynchronous Receive/Transmit 0 interrupt + LPUART1_IRQHandler, // 48 : Low-Power Universal Asynchronous Receive/Transmit 1 interrupt + LPUART2_IRQHandler, // 49 : Low-Power Universal Asynchronous Receive/Transmit 2 interrupt + LPUART3_IRQHandler, // 50 : Low-Power Universal Asynchronous Receive/Transmit 3 interrupt + LPUART4_IRQHandler, // 51 : Low-Power Universal Asynchronous Receive/Transmit 4 interrupt + USB0_IRQHandler, // 52 : Universal Serial Bus - Full Speed interrupt + Reserved53_IRQHandler, // 53 : Reserved interrupt + CDOG0_IRQHandler, // 54 : Code Watchdog Timer 0 interrupt + CTIMER0_IRQHandler, // 55 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 56 : Standard counter/timer 1 interrupt + CTIMER2_IRQHandler, // 57 : Standard counter/timer 2 interrupt + CTIMER3_IRQHandler, // 58 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 59 : Standard counter/timer 4 interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 60 : FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 61 : FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 62 : FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 63 : FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 64 : FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 65 : FlexPWM0 Submodule 3 capture/compare/reload interrupt + EQDC0_COMPARE_IRQHandler, // 66 : Compare + EQDC0_HOME_IRQHandler, // 67 : Home + EQDC0_WATCHDOG_IRQHandler, // 68 : Watchdog / Simultaneous A and B Change + EQDC0_INDEX_IRQHandler, // 69 : Index / Roll Over / Roll Under + FREQME0_IRQHandler, // 70 : Frequency Measurement interrupt + LPTMR0_IRQHandler, // 71 : Low Power Timer 0 interrupt + Reserved72_IRQHandler, // 72 : Reserved interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + WAKETIMER0_IRQHandler, // 74 : Wake Timer Interrupt + UTICK0_IRQHandler, // 75 : Micro-Tick Timer interrupt + WWDT0_IRQHandler, // 76 : Windowed Watchdog Timer 0 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + ADC0_IRQHandler, // 78 : Analog-to-Digital Converter 0 interrupt + ADC1_IRQHandler, // 79 : Analog-to-Digital Converter 1 interrupt + CMP0_IRQHandler, // 80 : Comparator 0 interrupt + CMP1_IRQHandler, // 81 : Comparator 1 interrupt + CMP2_IRQHandler, // 82 : Comparator 2 interrupt + DAC0_IRQHandler, // 83 : Digital-to-Analog Converter 0 - General Purpose interrupt + Reserved84_IRQHandler, // 84 : Reserved interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + GPIO0_IRQHandler, // 87 : General Purpose Input/Output interrupt 0 + GPIO1_IRQHandler, // 88 : General Purpose Input/Output interrupt 1 + GPIO2_IRQHandler, // 89 : General Purpose Input/Output interrupt 2 + GPIO3_IRQHandler, // 90 : General Purpose Input/Output interrupt 3 + GPIO4_IRQHandler, // 91 : General Purpose Input/Output interrupt 4 + Reserved92_IRQHandler, // 92 : Reserved interrupt + LPI2C2_IRQHandler, // 93 : Low-Power Inter Integrated Circuit 2 interrupt + LPI2C3_IRQHandler, // 94 : Low-Power Inter Integrated Circuit 3 interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 95 : FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 96 : FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 97 : FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 98 : FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 99 : FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 100: FlexPWM1 Submodule 3 capture/compare/reload interrupt + EQDC1_COMPARE_IRQHandler, // 101: Compare + EQDC1_HOME_IRQHandler, // 102: Home + EQDC1_WATCHDOG_IRQHandler, // 103: Watchdog / Simultaneous A and B Change + EQDC1_INDEX_IRQHandler, // 104: Index / Roll Over / Roll Under + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + Reserved109_IRQHandler, // 109: Reserved interrupt + Reserved110_IRQHandler, // 110: Reserved interrupt + LPUART5_IRQHandler, // 111: Low-Power Universal Asynchronous Receive/Transmit interrupt + Reserved112_IRQHandler, // 112: Reserved interrupt + Reserved113_IRQHandler, // 113: Reserved interrupt + Reserved114_IRQHandler, // 114: Reserved interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + Reserved116_IRQHandler, // 116: Reserved interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + Reserved121_IRQHandler, // 121: Reserved interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + MAU_IRQHandler, // 123: MAU interrupt + SMARTDMA_IRQHandler, // 124: SmartDMA interrupt + CDOG1_IRQHandler, // 125: Code Watchdog Timer 1 interrupt + PKC_IRQHandler, // 126: PKC interrupt + SGI_IRQHandler, // 127: SGI interrupt + Reserved128_IRQHandler, // 128: Reserved interrupt + TRNG0_IRQHandler, // 129: True Random Number Generator interrupt + SECURE_ERR_IRQHandler, // 130: Secure IP Error interrupt. It OR SGI, PKC, TRNG error together. + Reserved131_IRQHandler, // 131: Reserved interrupt + ADC2_IRQHandler, // 132: Analog-to-Digital Converter 2 interrupt + ADC3_IRQHandler, // 133: Analog-to-Digital Converter 3 interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + RTC_IRQHandler, // 135: RTC alarm interrupt + RTC_1HZ_IRQHandler, // 136: RTC 1Hz interrupt + LCD_IRQHandler, // 137: SLCD frame start interrupt +}; /* End of __vector_table */ + +#if defined(__MCUXPRESSO) +#if defined(ENABLE_RAM_VECTOR_TABLE) +extern void *__VECTOR_TABLE __attribute__((alias("g_pfnVectors"))); +void (*__VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128))); +unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors); +#endif //(ENABLE_RAM_VECTOR_TABLE) + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart, + unsigned int start, + unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int *pulSrc = (unsigned int *)romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len) +{ + unsigned int *pulDest = (unsigned int *)start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; +#endif //(__MCUXPRESSO) + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +__attribute__ ((used, section("InRoot$$Sections"))) +__attribute__ ((naked)) +#elif defined(__MCUXPRESSO) +__attribute__ ((naked, section(".after_vectors.reset"))) +#elif defined(__ICCARM__) +__stackless +#elif defined(__GNUC__) +__attribute__ ((naked)) +#endif //(__CC_ARM) || (__ARMCC_VERSION) +void Reset_Handler(void) +{ + // Disable interrupts + __asm volatile("cpsid i"); + // Config VTOR & MSP register + __asm volatile( + "LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(__vector_table), "r"(_vStackBase) + : "r0", "r1"); + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + __asm volatile( + "LDR R0, =SystemInit \n" + "BLX R0 \n" + "cpsie i \n" + "LDR R0, =__main \n" + "BX R0 \n"); +#elif defined(__MCUXPRESSO) + SystemInit(); + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) + { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) + { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if defined(__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif //(__cplusplus) + + // Reenable interrupts + __asm volatile("cpsie i"); + +#if defined(__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif //(__REDLIB__) +#elif defined(__ICCARM__) + SystemInit(); + // Reenable interrupts + __asm volatile("cpsie i"); + + __iar_program_start(); +#elif defined(__GNUC__) +#if !defined(__NO_SYSTEM_INIT) + SystemInit(); +#endif //(__NO_SYSTEM_INIT) + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * 1. __etext/_data_start__/__data_end__ + * Note: All must be aligned to 4 bytes boundary. + */ + uint32_t *pDataSrc, *pDataDest; + + pDataSrc = (uint32_t *)__etext; + pDataDest = (uint32_t *)__data_start__; + while (pDataDest < __data_end__) + { + *pDataDest++ = *pDataSrc++; + } +#if defined(__STARTUP_CLEAR_BSS) + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + pDataDest = (uint32_t *)__bss_start__; + while (pDataDest < __bss_end__) + { + *pDataDest++ = 0U; + } +#endif //(__STARTUP_CLEAR_BSS) + + __asm volatile("cpsie i"); + +#if !defined(__START) +#if defined(__REDLIB__) +#define __START __main +#else +#define __START _start +#endif //(__REDLIB__) +#endif //(__START) + + __START(); + +#endif //(__GNUC__) + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // +#if !defined(__ARMCC_VERSION) && !defined(__CC_ARM) + while (1) + { + ; + } +#endif //!(__ARMCC_VERSION) && !(__CC_ARM) +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void HardFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void MemManage_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void BusFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void UsageFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SecureFault_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SVC_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void DebugMon_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void PendSV_Handler(void) +{ + while (1) + { + } +} + +WEAK_AV void SysTick_Handler(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void DefaultISR(void) +{ + while (1) + { + } +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or DefaultISR() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void Reserved16_IRQHandler(void) +{ + Reserved16_DriverIRQHandler(); +} + +WEAK void CMC_IRQHandler(void) +{ + CMC_DriverIRQHandler(); +} + +WEAK void DMA_CH0_IRQHandler(void) +{ + DMA_CH0_DriverIRQHandler(); +} + +WEAK void DMA_CH1_IRQHandler(void) +{ + DMA_CH1_DriverIRQHandler(); +} + +WEAK void DMA_CH2_IRQHandler(void) +{ + DMA_CH2_DriverIRQHandler(); +} + +WEAK void DMA_CH3_IRQHandler(void) +{ + DMA_CH3_DriverIRQHandler(); +} + +WEAK void DMA_CH4_IRQHandler(void) +{ + DMA_CH4_DriverIRQHandler(); +} + +WEAK void DMA_CH5_IRQHandler(void) +{ + DMA_CH5_DriverIRQHandler(); +} + +WEAK void DMA_CH6_IRQHandler(void) +{ + DMA_CH6_DriverIRQHandler(); +} + +WEAK void DMA_CH7_IRQHandler(void) +{ + DMA_CH7_DriverIRQHandler(); +} + +WEAK void ERM0_SINGLE_BIT_IRQHandler(void) +{ + ERM0_SINGLE_BIT_DriverIRQHandler(); +} + +WEAK void ERM0_MULTI_BIT_IRQHandler(void) +{ + ERM0_MULTI_BIT_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ + FMU0_DriverIRQHandler(); +} + +WEAK void GLIKEY0_IRQHandler(void) +{ + GLIKEY0_DriverIRQHandler(); +} + +WEAK void MBC0_IRQHandler(void) +{ + MBC0_DriverIRQHandler(); +} + +WEAK void SCG0_IRQHandler(void) +{ + SCG0_DriverIRQHandler(); +} + +WEAK void SPC0_IRQHandler(void) +{ + SPC0_DriverIRQHandler(); +} + +WEAK void TDET_IRQHandler(void) +{ + TDET_DriverIRQHandler(); +} + +WEAK void WUU0_IRQHandler(void) +{ + WUU0_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ + CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ + CAN1_DriverIRQHandler(); +} + +WEAK void Reserved37_IRQHandler(void) +{ + Reserved37_DriverIRQHandler(); +} + +WEAK void Reserved38_IRQHandler(void) +{ + Reserved38_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ + FLEXIO_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ + I3C0_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ + Reserved41_DriverIRQHandler(); +} + +WEAK void LPI2C0_IRQHandler(void) +{ + LPI2C0_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ + LPI2C1_DriverIRQHandler(); +} + +WEAK void LPSPI0_IRQHandler(void) +{ + LPSPI0_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ + LPSPI1_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ + Reserved46_DriverIRQHandler(); +} + +WEAK void LPUART0_IRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ + USB0_DriverIRQHandler(); +} + +WEAK void Reserved53_IRQHandler(void) +{ + Reserved53_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ + CDOG0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ + CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ + CTIMER1_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ + CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ + CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ + CTIMER4_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ + FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC0_COMPARE_IRQHandler(void) +{ + EQDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC0_HOME_IRQHandler(void) +{ + EQDC0_HOME_DriverIRQHandler(); +} + +WEAK void EQDC0_WATCHDOG_IRQHandler(void) +{ + EQDC0_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC0_INDEX_IRQHandler(void) +{ + EQDC0_INDEX_DriverIRQHandler(); +} + +WEAK void FREQME0_IRQHandler(void) +{ + FREQME0_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ + LPTMR0_DriverIRQHandler(); +} + +WEAK void Reserved72_IRQHandler(void) +{ + Reserved72_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ + OS_EVENT_DriverIRQHandler(); +} + +WEAK void WAKETIMER0_IRQHandler(void) +{ + WAKETIMER0_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ + UTICK0_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ + WWDT0_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ + Reserved77_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ + ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ + ADC1_DriverIRQHandler(); +} + +WEAK void CMP0_IRQHandler(void) +{ + CMP0_DriverIRQHandler(); +} + +WEAK void CMP1_IRQHandler(void) +{ + CMP1_DriverIRQHandler(); +} + +WEAK void CMP2_IRQHandler(void) +{ + CMP2_DriverIRQHandler(); +} + +WEAK void DAC0_IRQHandler(void) +{ + DAC0_DriverIRQHandler(); +} + +WEAK void Reserved84_IRQHandler(void) +{ + Reserved84_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ + Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ + Reserved86_DriverIRQHandler(); +} + +WEAK void GPIO0_IRQHandler(void) +{ + GPIO0_DriverIRQHandler(); +} + +WEAK void GPIO1_IRQHandler(void) +{ + GPIO1_DriverIRQHandler(); +} + +WEAK void GPIO2_IRQHandler(void) +{ + GPIO2_DriverIRQHandler(); +} + +WEAK void GPIO3_IRQHandler(void) +{ + GPIO3_DriverIRQHandler(); +} + +WEAK void GPIO4_IRQHandler(void) +{ + GPIO4_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ + Reserved92_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ + LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ + LPI2C3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ + FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ + FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ + FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void EQDC1_COMPARE_IRQHandler(void) +{ + EQDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void EQDC1_HOME_IRQHandler(void) +{ + EQDC1_HOME_DriverIRQHandler(); +} + +WEAK void EQDC1_WATCHDOG_IRQHandler(void) +{ + EQDC1_WATCHDOG_DriverIRQHandler(); +} + +WEAK void EQDC1_INDEX_IRQHandler(void) +{ + EQDC1_INDEX_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ + Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ + Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ + Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ + Reserved108_DriverIRQHandler(); +} + +WEAK void Reserved109_IRQHandler(void) +{ + Reserved109_DriverIRQHandler(); +} + +WEAK void Reserved110_IRQHandler(void) +{ + Reserved110_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} + +WEAK void Reserved112_IRQHandler(void) +{ + Reserved112_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ + Reserved113_DriverIRQHandler(); +} + +WEAK void Reserved114_IRQHandler(void) +{ + Reserved114_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ + Reserved115_DriverIRQHandler(); +} + +WEAK void Reserved116_IRQHandler(void) +{ + Reserved116_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ + Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ + Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ + Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ + Reserved120_DriverIRQHandler(); +} + +WEAK void Reserved121_IRQHandler(void) +{ + Reserved121_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ + Reserved122_DriverIRQHandler(); +} + +WEAK void MAU_IRQHandler(void) +{ + MAU_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ + CDOG1_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ + PKC_DriverIRQHandler(); +} + +WEAK void SGI_IRQHandler(void) +{ + SGI_DriverIRQHandler(); +} + +WEAK void Reserved128_IRQHandler(void) +{ + Reserved128_DriverIRQHandler(); +} + +WEAK void TRNG0_IRQHandler(void) +{ + TRNG0_DriverIRQHandler(); +} + +WEAK void SECURE_ERR_IRQHandler(void) +{ + SECURE_ERR_DriverIRQHandler(); +} + +WEAK void Reserved131_IRQHandler(void) +{ + Reserved131_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ + ADC2_DriverIRQHandler(); +} + +WEAK void ADC3_IRQHandler(void) +{ + ADC3_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ + Reserved134_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ + RTC_DriverIRQHandler(); +} + +WEAK void RTC_1HZ_IRQHandler(void) +{ + RTC_1HZ_DriverIRQHandler(); +} + +WEAK void LCD_IRQHandler(void) +{ + LCD_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined(DEBUG) +#if defined(__GNUC__) +#pragma GCC pop_options +#endif //(__GNUC__) +#endif //(DEBUG) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/system_MCXA365.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/system_MCXA365.c new file mode 100644 index 000000000..b22aa6d58 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/system_MCXA365.c @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA365 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA365 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + /* Enables flash speculation */ + SYSCON->NVM_CTRL &= ~(SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK | SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK); + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/system_MCXA365.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/system_MCXA365.h new file mode 100644 index 000000000..198ff4206 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/system_MCXA365.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** Processors: MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN +** +** Compilers: +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXAP144M180FS6_RM_Rev.1 +** Version: rev. 1.0, 2024-11-21 +** Build: b250730 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file MCXA365 + * @version 1.0 + * @date 2024-11-21 + * @brief Device specific configuration file for MCXA365 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA365_H_ +#define _SYSTEM_MCXA365_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ + +#ifndef CLK_CLK_IN +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ +#endif /* CLK_CLK_IN */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA365_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/variable.cmake new file mode 100644 index 000000000..f6f91888e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA365/variable.cmake @@ -0,0 +1,15 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXA365) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXA) +mcux_set_variable(soc_periph periph2) +mcux_set_variable(core_id_suffix_name "") +mcux_set_variable(multicore_foldername .) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/CMakeLists.txt index d394a2184..92e7d0489 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366.h index b68aa1664..896fc86fe 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA366 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366_COMMON.h index 9a69f1893..069b98700 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXA366 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366_features.h index 0883d1cf6..890226dcf 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/MCXA366_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-26 -** Build: b250725 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -270,6 +270,8 @@ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) /* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -481,6 +483,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* FMU module features */ @@ -786,10 +790,56 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (0) /* SPC module features */ @@ -910,7 +960,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -932,8 +982,14 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXA366_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/startup_MCXA366.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/startup_MCXA366.c index a41d09aa9..5bffd739d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/startup_MCXA366.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/startup_MCXA366.c @@ -1,7 +1,7 @@ //***************************************************************************** // MCXA366 startup code // -// Version : 290725 +// Version : 300725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/startup_MCXA366.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/startup_MCXA366.cpp index a41d09aa9..5bffd739d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/startup_MCXA366.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/startup_MCXA366.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MCXA366 startup code // -// Version : 290725 +// Version : 300725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/system_MCXA366.c b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/system_MCXA366.c index 8a2d8ad20..def17b0a7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/system_MCXA366.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/system_MCXA366.c @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/system_MCXA366.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/system_MCXA366.h index 668a4f7ca..261a81a09 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/system_MCXA366.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/system_MCXA366.h @@ -13,7 +13,7 @@ ** ** Reference manual: MCXAP144M180FS6_RM_Rev.1 ** Version: rev. 1.0, 2024-11-21 -** Build: b250520 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/variable.cmake index de1411cbb..28f1140b4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/variable.cmake +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/MCXA366/variable.cmake @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2025 NXP # All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_ADC.h index f66907cad..f4226427b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_ADC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC @@ -49,12 +57,16 @@ #if !defined(PERI_ADC_H_) #define PERI_ADC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_AOI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_AOI.h index c2f80c801..205aaa9c6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_AOI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_AOI.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for AOI @@ -49,12 +57,16 @@ #if !defined(PERI_AOI_H_) #define PERI_AOI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CAN.h index c8005efe8..3e2f8a25d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CAN.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN @@ -49,12 +57,16 @@ #if !defined(PERI_CAN_H_) #define PERI_CAN_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CDOG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CDOG.h index 9b23daeb5..61a911a48 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CDOG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CDOG.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for CDOG @@ -49,12 +57,16 @@ #if !defined(PERI_CDOG_H_) #define PERI_CDOG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CMC.h index 27dd1031b..934167860 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CMC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMC @@ -49,12 +57,16 @@ #if !defined(PERI_CMC_H_) #define PERI_CMC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CRC.h index b9f339084..a92c731f7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CRC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC @@ -49,12 +57,16 @@ #if !defined(PERI_CRC_H_) #define PERI_CRC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CTIMER.h index cf1c51cbe..1a56c0328 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CTIMER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_CTIMER.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for CTIMER @@ -49,12 +57,16 @@ #if !defined(PERI_CTIMER_H_) #define PERI_CTIMER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DEBUGMAILBOX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DEBUGMAILBOX.h index 1a8832aa1..a84f4e1e7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DEBUGMAILBOX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DEBUGMAILBOX.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for DEBUGMAILBOX @@ -49,12 +57,16 @@ #if !defined(PERI_DEBUGMAILBOX_H_) #define PERI_DEBUGMAILBOX_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DIGTMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DIGTMP.h index e7d88ec9c..1a5eb8972 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DIGTMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DIGTMP.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for DIGTMP @@ -49,12 +57,16 @@ #if !defined(PERI_DIGTMP_H_) #define PERI_DIGTMP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DMA.h index 31934ebfe..85866d086 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_DMA.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250902 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -49,12 +57,16 @@ #if !defined(PERI_DMA_H_) #define PERI_DMA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else @@ -141,6 +153,7 @@ typedef enum _dma_request_source kDma0RequestMuxAdc1FifoRequest = 52U, /**< ADC1 FIFO request */ kDma0RequestMuxHsCmp0DmaRequest = 53U, /**< CMP0 DMA_request */ kDma0RequestMuxHsCmp1DmaRequest = 54U, /**< CMP1 DMA_request */ + kDma0RequestMuxHsCmp2DmaRequest = 55U, /**< CMP2 DMA_request */ kDma0RequestMuxDac0FifoRequest = 56U, /**< DAC0 FIFO request */ kDma0RequestMuxGpio0PinEventRequest0 = 60U, /**< GPIO0 Pin event request 0 */ kDma0RequestMuxGpio1PinEventRequest0 = 61U, /**< GPIO1 Pin event request 0 */ @@ -164,10 +177,11 @@ typedef enum _dma_request_source kDma0RequestMuxFlexCan1DmaRequest = 87U, /**< CAN1 DMA request */ kDma0RequestLPUART5Rx = 102U, /**< LPUART5 Receive request */ kDma0RequestLPUART5Tx = 103U, /**< LPUART5 Transmit request */ + kDma0RequestMuxMau0 = 115U, /**< MAU0 DMA request */ kDma0RequestSGI0Datain = 119U, /**< SGI0 DATAIN request */ kDma0RequestSGI0Dataout = 120U, /**< SGI0 DATOUT request */ - kDma0RequestMuxHsCmp2DmaRequest = 55U, /**< CMP2 DMA_request */ - kDma0RequestMuxMau0 = 115U, /**< MAU0 DMA request */ + kDma0RequestMuxAdc2FifoRequest = 123U, /**< ADC2 FIFO request */ + kDma0RequestMuxAdc3FifoRequest = 124U, /**< ADC3 FIFO request */ } dma_request_source_t; /* @} */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_EIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_EIM.h index 2defef058..7cec881c4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_EIM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_EIM.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for EIM @@ -49,12 +57,16 @@ #if !defined(PERI_EIM_H_) #define PERI_EIM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_EQDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_EQDC.h index 033ea5f94..c63c5908d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_EQDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_EQDC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for EQDC @@ -49,12 +57,16 @@ #if !defined(PERI_EQDC_H_) #define PERI_EQDC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_ERM.h index 25d3ec3a5..0df2925eb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_ERM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_ERM.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for ERM @@ -49,12 +57,16 @@ #if !defined(PERI_ERM_H_) #define PERI_ERM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FLEXIO.h index e583b8657..af5faa858 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FLEXIO.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO @@ -49,12 +57,16 @@ #if !defined(PERI_FLEXIO_H_) #define PERI_FLEXIO_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FMC.h index 2ebbe8409..976402664 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FMC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMC @@ -49,12 +57,16 @@ #if !defined(PERI_FMC_H_) #define PERI_FMC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FMU.h index 763940a7b..95e5248f6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FMU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FMU.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMU @@ -49,12 +57,16 @@ #if !defined(PERI_FMU_H_) #define PERI_FMU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FREQME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FREQME.h index de5c60016..b43f1808b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FREQME.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_FREQME.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for FREQME @@ -49,12 +57,16 @@ #if !defined(PERI_FREQME_H_) #define PERI_FREQME_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_GLIKEY.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_GLIKEY.h index 25471f422..c1e8c0af4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_GLIKEY.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_GLIKEY.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for GLIKEY @@ -49,12 +57,16 @@ #if !defined(PERI_GLIKEY_H_) #define PERI_GLIKEY_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_GPIO.h index 9f4f1b6b7..c9aaaefbc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_GPIO.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO @@ -49,12 +57,16 @@ #if !defined(PERI_GPIO_H_) #define PERI_GPIO_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_I3C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_I3C.h index 3627db046..2abea9ee8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_I3C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_I3C.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for I3C @@ -49,12 +57,16 @@ #if !defined(PERI_I3C_H_) #define PERI_I3C_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_INPUTMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_INPUTMUX.h index 908f73f43..fe0b2867e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_INPUTMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_INPUTMUX.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for INPUTMUX @@ -49,12 +57,16 @@ #if !defined(PERI_INPUTMUX_H_) #define PERI_INPUTMUX_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LCD.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LCD.h index 4c769391f..183680b04 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LCD.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LCD.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for LCD @@ -49,12 +57,16 @@ #if !defined(PERI_LCD_H_) #define PERI_LCD_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPCMP.h index a9f4252d5..6f2205bf8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPCMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPCMP.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPCMP @@ -49,12 +57,16 @@ #if !defined(PERI_LPCMP_H_) #define PERI_LPCMP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPDAC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPDAC.h index cbab79d6f..8c563235e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPDAC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPDAC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPDAC @@ -49,12 +57,16 @@ #if !defined(PERI_LPDAC_H_) #define PERI_LPDAC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPI2C.h index f92291d07..1010a7724 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPI2C.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -49,12 +57,16 @@ #if !defined(PERI_LPI2C_H_) #define PERI_LPI2C_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPSPI.h index e22120191..e15eaa76f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPSPI.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI @@ -49,12 +57,16 @@ #if !defined(PERI_LPSPI_H_) #define PERI_LPSPI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPTMR.h index f3f82f123..a69464f7b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPTMR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPTMR.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPTMR @@ -49,12 +57,16 @@ #if !defined(PERI_LPTMR_H_) #define PERI_LPTMR_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPUART.h index b8d13ac7d..4ff91d0e5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_LPUART.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART @@ -49,12 +57,16 @@ #if !defined(PERI_LPUART_H_) #define PERI_LPUART_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_MAU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_MAU.h index 7594f1f80..c4999c641 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_MAU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_MAU.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for MAU @@ -49,12 +57,16 @@ #if !defined(PERI_MAU_H_) #define PERI_MAU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_MRCC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_MRCC.h index 707ce7614..dedd6992f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_MRCC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_MRCC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for MRCC @@ -49,12 +57,16 @@ #if !defined(PERI_MRCC_H_) #define PERI_MRCC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_OPAMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_OPAMP.h index 441cb7190..d8fd68134 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_OPAMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_OPAMP.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for OPAMP @@ -49,12 +57,16 @@ #if !defined(PERI_OPAMP_H_) #define PERI_OPAMP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_OSTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_OSTIMER.h index 73113d433..7d43620f2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_OSTIMER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_OSTIMER.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSTIMER @@ -49,12 +57,16 @@ #if !defined(PERI_OSTIMER_H_) #define PERI_OSTIMER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PKC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PKC.h index 4fe5748e9..8e2caa831 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PKC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PKC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for PKC @@ -49,12 +57,16 @@ #if !defined(PERI_PKC_H_) #define PERI_PKC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PORT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PORT.h index 3228640c0..d6a5c0d9a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PORT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PORT.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for PORT @@ -49,12 +57,16 @@ #if !defined(PERI_PORT_H_) #define PERI_PORT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PWM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PWM.h index f08cbe3ca..3a3c59fa3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PWM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_PWM.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for PWM @@ -49,12 +57,16 @@ #if !defined(PERI_PWM_H_) #define PERI_PWM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_RTC.h index bace0b8b1..c8d0697b6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_RTC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -49,12 +57,16 @@ #if !defined(PERI_RTC_H_) #define PERI_RTC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SCG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SCG.h index 947f2b698..d7c8dc9f8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SCG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SCG.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for SCG @@ -49,12 +57,16 @@ #if !defined(PERI_SCG_H_) #define PERI_SCG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else @@ -604,8 +616,11 @@ typedef struct { #define SCG_FIRCCFG_FREQ_SEL_SHIFT (1U) /*! FREQ_SEL - Frequency select * 0b001..45 MHz FIRC clock selected, divided from 180 MHz + * 0b010..80MHz FIRC clock selected * 0b011..60 MHz FIRC clock selected + * 0b100..120MHz FIRC clock selected * 0b101..90 MHz FIRC clock selected + * 0b110..240MHz FIRC clock selected * 0b111..180 MHz FIRC clock selected */ #define SCG_FIRCCFG_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_FREQ_SEL_SHIFT)) & SCG_FIRCCFG_FREQ_SEL_MASK) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SGI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SGI.h index 514cefb16..29805da33 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SGI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SGI.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for SGI @@ -49,12 +57,16 @@ #if !defined(PERI_SGI_H_) #define PERI_SGI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SMARTDMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SMARTDMA.h index 6f8c2ab84..569ce7fe9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SMARTDMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SMARTDMA.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for SMARTDMA @@ -49,12 +57,16 @@ #if !defined(PERI_SMARTDMA_H_) #define PERI_SMARTDMA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SPC.h index c9b248974..1e2679503 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SPC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SPC.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPC @@ -49,12 +57,16 @@ #if !defined(PERI_SPC_H_) #define PERI_SPC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SYSCON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SYSCON.h index c88a75f0c..ad855b85c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SYSCON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_SYSCON.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON @@ -49,12 +57,16 @@ #if !defined(PERI_SYSCON_H_) #define PERI_SYSCON_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_TRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_TRDC.h index 0a983a066..53c494f80 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_TRDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_TRDC.h @@ -1,11 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -13,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250417 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC @@ -50,12 +57,16 @@ #if !defined(PERI_TRDC_H_) #define PERI_TRDC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_TRNG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_TRNG.h index a99ebe58d..8981bf0ef 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_TRNG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_TRNG.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRNG @@ -49,12 +57,16 @@ #if !defined(PERI_TRNG_H_) #define PERI_TRNG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_UDF.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_UDF.h index a67d7d0fe..4b415bce6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_UDF.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_UDF.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for UDF @@ -49,12 +57,16 @@ #if !defined(PERI_UDF_H_) #define PERI_UDF_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_USB.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_USB.h index 36c5ed563..5683c51ab 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_USB.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB @@ -49,12 +57,16 @@ #if !defined(PERI_USB_H_) #define PERI_USB_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_UTICK.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_UTICK.h index 3d4d33bde..e078ea723 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_UTICK.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_UTICK.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for UTICK @@ -49,12 +57,16 @@ #if !defined(PERI_UTICK_H_) #define PERI_UTICK_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_VBAT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_VBAT.h index 795afe9c8..c45306ca0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_VBAT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_VBAT.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for VBAT @@ -49,12 +57,16 @@ #if !defined(PERI_VBAT_H_) #define PERI_VBAT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WAKETIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WAKETIMER.h index 6996ac36b..75628e4d9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WAKETIMER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WAKETIMER.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for WAKETIMER @@ -49,12 +57,16 @@ #if !defined(PERI_WAKETIMER_H_) #define PERI_WAKETIMER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WUU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WUU.h index 72bd7ce27..3a299236a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WUU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WUU.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for WUU @@ -49,12 +57,16 @@ #if !defined(PERI_WUU_H_) #define PERI_WUU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WWDT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WWDT.h index e81a89eca..210ac6be4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WWDT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph2/PERI_WWDT.h @@ -1,10 +1,6 @@ /* ** ################################################################### -** Processors: MCXA266VLH -** MCXA266VLL -** MCXA266VLQ -** MCXA266VPN -** MCXA345VLH +** Processors: MCXA345VLH ** MCXA345VLL ** MCXA345VLQ ** MCXA345VPN @@ -12,13 +8,25 @@ ** MCXA346VLL ** MCXA346VLQ ** MCXA346VPN +** MCXA355VLH +** MCXA355VLL +** MCXA355VLQ +** MCXA355VPN +** MCXA356VLH +** MCXA356VLL +** MCXA356VLQ +** MCXA356VPN +** MCXA365VLH +** MCXA365VLL +** MCXA365VLQ +** MCXA365VPN ** MCXA366VLH ** MCXA366VLL ** MCXA366VLQ ** MCXA366VPN ** ** Version: rev. 1.0, 2024-11-21 -** Build: b250729 +** Build: b250804 ** ** Abstract: ** CMSIS Peripheral Access Layer for WWDT @@ -49,12 +57,16 @@ #if !defined(PERI_WWDT_H_) #define PERI_WWDT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) -#include "MCXA266_COMMON.h" -#elif (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) +#if (defined(CPU_MCXA345VLH) || defined(CPU_MCXA345VLL) || defined(CPU_MCXA345VLQ) || defined(CPU_MCXA345VPN)) #include "MCXA345_COMMON.h" #elif (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN)) #include "MCXA346_COMMON.h" +#elif (defined(CPU_MCXA355VLH) || defined(CPU_MCXA355VLL) || defined(CPU_MCXA355VLQ) || defined(CPU_MCXA355VPN)) +#include "MCXA355_COMMON.h" +#elif (defined(CPU_MCXA356VLH) || defined(CPU_MCXA356VLL) || defined(CPU_MCXA356VLQ) || defined(CPU_MCXA356VPN)) +#include "MCXA356_COMMON.h" +#elif (defined(CPU_MCXA365VLH) || defined(CPU_MCXA365VLL) || defined(CPU_MCXA365VLQ) || defined(CPU_MCXA365VPN)) +#include "MCXA365_COMMON.h" #elif (defined(CPU_MCXA366VLH) || defined(CPU_MCXA366VLL) || defined(CPU_MCXA366VLQ) || defined(CPU_MCXA366VPN)) #include "MCXA366_COMMON.h" #else diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ADC.h new file mode 100644 index 000000000..371328eb9 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ADC.h @@ -0,0 +1,1018 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for ADC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_ADC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for ADC + * + * CMSIS Peripheral Access Layer for ADC + */ + +#if !defined(PERI_ADC_H_) +#define PERI_ADC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Size of Registers Arrays */ +#define ADC_TCTRL_COUNT 4u +#define ADC_GCC_COUNT 1u +#define ADC_GCR_COUNT 1u +#define ADC_CMD_COUNT 7u +#define ADC_CV_COUNT 7u +#define ADC_CAL_GAR_COUNT 34u + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[4]; + __IO uint32_t HSTRIM; /**< High Speed Trim Register, offset: 0x48 */ + uint8_t RESERVED_4[84]; + __IO uint32_t TCTRL[ADC_TCTRL_COUNT]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[48]; + __IO uint32_t FCTRL; /**< FIFO Control Register, offset: 0xE0 */ + uint8_t RESERVED_6[12]; + __I uint32_t GCC[ADC_GCC_COUNT]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + uint8_t RESERVED_7[4]; + __IO uint32_t GCR[ADC_GCR_COUNT]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + uint8_t RESERVED_8[4]; + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[ADC_CMD_COUNT]; + uint8_t RESERVED_9[200]; + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[228]; + __I uint32_t RESFIFO; /**< Data Result FIFO Register, offset: 0x300 */ + uint8_t RESERVED_11[252]; + __IO uint32_t CAL_GAR[ADC_CAL_GAR_COUNT]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_12[2928]; + __IO uint32_t CFG2; /**< Configuration 2 Register, offset: 0xFF8 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID[DIFFEN] = 1b). + * 0b1..Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID[DIFFEN] = 1b). + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock Implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultaneous single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 2 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in low power mode. + * 0b1..ADC is disabled in low power mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for hardware calibration has been made + * 0b1..A request for hardware calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Offset Calibration Request + * 0b0..No request for offset calibration has been made + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_CALHS_MASK (0x40U) +#define ADC_CTRL_CALHS_SHIFT (6U) +/*! CALHS - High Speed Mode Trim Request + * 0b0..No request for high speed mode trim has been made + * 0b1..Request for high speed mode trim has been made + */ +#define ADC_CTRL_CALHS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALHS_SHIFT)) & ADC_CTRL_CALHS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0xF0000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b0000..Single conversion. + * 0b0001..2 conversions averaged. + * 0b0010..4 conversions averaged. + * 0b0011..8 conversions averaged. + * 0b0100..16 conversions averaged. + * 0b0101..32 conversions averaged. + * 0b0110..64 conversions averaged. + * 0b0111..128 conversions averaged. + * 0b1000..256 conversions averaged. + * 0b1001..512 conversions averaged. + * 0b1010..1024 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0x30000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b00..Command (sequence) associated with Trigger 0 currently being executed. + * 0b01..Command (sequence) associated with Trigger 1 currently being executed. + * 0b10..Command (sequence) associated with Trigger 2 currently being executed. + * 0b11..Command (sequence) associated with Trigger 3 currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0x7000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b000..No command is currently in progress. + * 0b001..Command 1 currently being executed. + * 0b010..Command 2 currently being executed. + * 0b011-0b111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000..Trigger completion interrupts are disabled. + * 0b0001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0011-0b1110..Associated trigger completion interrupts are enabled. + * 0b1111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) +/*! @} */ + +/*! @name CFG - Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC Trigger Priority Control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11.. + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x20U) +#define ADC_CFG_PWRSEL_SHIFT (5U) +/*! PWRSEL - Power Configuration Select + * 0b0..Low power + * 0b1..High power + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately + * once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has + * passed. After this initial delay expires the analog remains pre-enabled and no additional delays are + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software Trigger 0 Event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software Trigger 1 Event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software Trigger 2 Event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software Trigger 3 Event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0001..Trigger 0 has been interrupted by a high priority exception. + * 0b0010..Trigger 1 has been interrupted by a high priority exception. + * 0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts. + * 0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts. + * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_MASK (0x3FFU) +#define ADC_OFSTRIM_OFSTRIM_SHIFT (0U) +/*! OFSTRIM - Trim for Offset */ +#define ADC_OFSTRIM_OFSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK) +/*! @} */ + +/*! @name HSTRIM - High Speed Trim Register */ +/*! @{ */ + +#define ADC_HSTRIM_HSTRIM_MASK (0x1FU) +#define ADC_HSTRIM_HSTRIM_SHIFT (0U) +/*! HSTRIM - Trim for High Speed Conversions */ +#define ADC_HSTRIM_HSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_HSTRIM_HSTRIM_SHIFT)) & ADC_HSTRIM_HSTRIM_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger Enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_TPRI_MASK (0x300U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger Priority Setting + * 0b00..Set to highest priority, Level 1 + * 0b01-0b10..Set to corresponding priority level + * 0b11..Set to lowest priority, Level 4 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger Delay Select */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TSYNC_MASK (0x800000U) +#define ADC_TCTRL_TSYNC_SHIFT (23U) +/*! TSYNC - Trigger Synchronous Select */ +#define ADC_TCTRL_TSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TSYNC_SHIFT)) & ADC_TCTRL_TSYNC_MASK) + +#define ADC_TCTRL_TCMD_MASK (0x7000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger Command Select + * 0b000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b001..CMD1 is executed + * 0b010-0b110..Corresponding CMD is executed + * 0b111..CMD7 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0xFU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO Counter */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0x70000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark Level Selection */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set. + * 0b1..The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR]. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0x1FFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The GCALR value is invalid. + * 0b1..The GCALR value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/*! @name CMDL - Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b00000..Select CH0A. + * 0b00001..Select CH1A. + * 0b00010..Select CH2A. + * 0b00011..Select CH3A. + * 0b00100-0b11101..Select corresponding channel CHnA. + * 0b11110..Select CH30A. + * 0b11111..Select CH31A. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01-0b11..Reserved. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select Resolution of Conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion. + * 0b1..High resolution. Single-ended 16-bit conversion. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (7U) + +/*! @name CMDH - Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for Trigger Assertion before Execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3.5 ADCK cycles. + * 0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time. + * 0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time. + * 0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time. + * 0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time. + * 0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time. + * 0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time. + * 0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0xF000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b0000..Single conversion. + * 0b0001..2 conversions averaged. + * 0b0010..4 conversions averaged. + * 0b0011..8 conversions averaged. + * 0b0100..16 conversions averaged. + * 0b0101..32 conversions averaged. + * 0b0110..64 conversions averaged. + * 0b0111..128 conversions averaged. + * 0b1000..256 conversions averaged. + * 0b1001..512 conversions averaged. + * 0b1010..1024 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0x7000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b001..Select CMD1 command buffer register as next command. + * 0b010-0b110..Select corresponding CMD command buffer register as next command + * 0b111..Select CMD7 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (7U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/*! @name RESFIFO - Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data Result */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0x30000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b00..Trigger source 0 initiated this conversion. + * 0b01..Trigger source 1 initiated this conversion. + * 0b10..Trigger source 2 initiated this conversion. + * 0b11..Trigger source 3 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop Count Value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0x7000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior + * to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b001..CMD1 buffer used as control settings for this conversion. + * 0b010-0b110..Corresponding command buffer used as control settings for this conversion. + * 0b111..CMD7 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO Entry is Valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration 2 Register */ +/*! @{ */ + +#define ADC_CFG2_JLEFT_MASK (0x100U) +#define ADC_CFG2_JLEFT_SHIFT (8U) +/*! JLEFT - Justified Left Enable register */ +#define ADC_CFG2_JLEFT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_JLEFT_SHIFT)) & ADC_CFG2_JLEFT_MASK) + +#define ADC_CFG2_HS_MASK (0x200U) +#define ADC_CFG2_HS_SHIFT (9U) +/*! HS - High Speed Enable register + * 0b0..High speed conversion mode disabled + * 0b1..High speed conversion mode enabled + */ +#define ADC_CFG2_HS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HS_SHIFT)) & ADC_CFG2_HS_MASK) + +#define ADC_CFG2_HSEXTRA_MASK (0x400U) +#define ADC_CFG2_HSEXTRA_SHIFT (10U) +/*! HSEXTRA - High Speed Extra register + * 0b0..No extra cycle added + * 0b1..Extra cycle added + */ +#define ADC_CFG2_HSEXTRA(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HSEXTRA_SHIFT)) & ADC_CFG2_HSEXTRA_MASK) + +#define ADC_CFG2_TUNE_MASK (0x3000U) +#define ADC_CFG2_TUNE_SHIFT (12U) +/*! TUNE - Tune Mode register */ +#define ADC_CFG2_TUNE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_TUNE_SHIFT)) & ADC_CFG2_TUNE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + +/* Backward compatibility */ +#define ADC_CTRL_RSTFIFO_MASK ADC_CTRL_RSTFIFO0_MASK +#define ADC_CTRL_RSTFIFO_SHIFT ADC_CTRL_RSTFIFO0_SHIFT +#define ADC_CTRL_RSTFIFO(x) ADC_CTRL_RSTFIFO0(x) +#define ADC_STAT_RDY_MASK ADC_STAT_RDY0_MASK +#define ADC_STAT_RDY_SHIFT ADC_STAT_RDY0_SHIFT +#define ADC_STAT_RDY(x) ADC_STAT_RDY0(x) +#define ADC_STAT_FOF_MASK ADC_STAT_FOF0_MASK +#define ADC_STAT_FOF_SHIFT ADC_STAT_FOF0_SHIFT +#define ADC_STAT_FOF(x) ADC_STAT_FOF0(x) +#define ADC_IE_FWMIE_MASK ADC_IE_FWMIE0_MASK +#define ADC_IE_FWMIE_SHIFT ADC_IE_FWMIE0_SHIFT +#define ADC_IE_FWMIE(x) ADC_IE_FWMIE0(x) +#define ADC_IE_FOFIE_MASK ADC_IE_FOFIE0_MASK +#define ADC_IE_FOFIE_SHIFT ADC_IE_FOFIE0_SHIFT +#define ADC_IE_FOFIE(x) ADC_IE_FOFIE0(x) +#define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK +#define ADC_DE_FWMDE_SHIFT ADC_DE_FWMDE0_SHIFT +#define ADC_DE_FWMDE(x) ADC_DE_FWMDE0(x) + + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_ADC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_AOI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_AOI.h new file mode 100644 index 000000000..8e4698ff5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_AOI.h @@ -0,0 +1,322 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for AOI +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_AOI.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for AOI + * + * CMSIS Peripheral Access Layer for AOI + */ + +#if !defined(PERI_AOI_H_) +#define PERI_AOI_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- AOI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer + * @{ + */ + +/** AOI - Size of Registers Arrays */ +#define AOI_BFCRT_COUNT 4u + +/** AOI - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3, array offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3, array offset: 0x2, array step: 0x4 */ + } BFCRT[AOI_BFCRT_COUNT]; +} AOI_Type; + +/* ---------------------------------------------------------------------------- + -- AOI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Register_Masks AOI Register Masks + * @{ + */ + +/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3 */ +/*! @{ */ + +#define AOI_BFCRT01_PT1_DC_MASK (0x3U) +#define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product Term 1, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) + +#define AOI_BFCRT01_PT1_CC_MASK (0xCU) +#define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product Term 1, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) + +#define AOI_BFCRT01_PT1_BC_MASK (0x30U) +#define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product Term 1, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) + +#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) +#define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product Term 1, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input A to become 1 + */ +#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) + +#define AOI_BFCRT01_PT0_DC_MASK (0x300U) +#define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product Term 0, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) + +#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) +#define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product Term 0, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) + +#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) +#define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product Term 0, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) + +#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) +#define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product Term 0, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input A to become 1 + */ +#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT01 */ +#define AOI_BFCRT01_COUNT (4U) + +/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3 */ +/*! @{ */ + +#define AOI_BFCRT23_PT3_DC_MASK (0x3U) +#define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product Term 3, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) + +#define AOI_BFCRT23_PT3_CC_MASK (0xCU) +#define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product Term 3, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) + +#define AOI_BFCRT23_PT3_BC_MASK (0x30U) +#define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product Term 3, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) + +#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) +#define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product Term 3, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input to become 1 + */ +#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) + +#define AOI_BFCRT23_PT2_DC_MASK (0x300U) +#define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product Term 2, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) + +#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) +#define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product Term 2, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) + +#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) +#define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product Term 2, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) + +#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) +#define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product Term 2, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input A to become 1 + */ +#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT23 */ +#define AOI_BFCRT23_COUNT (4U) + + +/*! + * @} + */ /* end of group AOI_Register_Masks */ + + +/*! + * @} + */ /* end of group AOI_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_AOI_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CAN.h new file mode 100644 index 000000000..e75c799b4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CAN.h @@ -0,0 +1,2255 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for CAN +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_CAN.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for CAN + * + * CMSIS Peripheral Access Layer for CAN + */ + +#if !defined(PERI_CAN_H_) +#define PERI_CAN_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Size of Registers Arrays */ +#define CAN_MB_SIZE_MB_8B_GROUP_MB_8B_WORD_8B_COUNT 2u +#define CAN_MB_SIZE_MB_8B_GROUP_MB_8B_COUNT 32u +#define CAN_MB_SIZE_MB_16B_GROUP_MB_16B_WORD_16B_COUNT 4u +#define CAN_MB_SIZE_MB_16B_GROUP_MB_16B_COUNT 21u +#define CAN_MB_SIZE_MB_32B_GROUP_MB_32B_WORD_32B_COUNT 8u +#define CAN_MB_SIZE_MB_32B_GROUP_MB_32B_COUNT 12u +#define CAN_MB_SIZE_MB_64B_GROUP_MB_64B_WORD_64B_COUNT 16u +#define CAN_MB_SIZE_MB_64B_GROUP_MB_64B_COUNT 7u +#define CAN_MB_SIZE_MB_GROUP_MB_COUNT 32u +#define CAN_RXIMR_COUNT 32u +#define CAN_WMB_COUNT 4u +#define CAN_ERFFEL_COUNT 32u + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ + uint8_t RESERVED_3[8]; + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ + uint8_t RESERVED_4[44]; + union { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD[CAN_MB_SIZE_MB_8B_GROUP_MB_8B_WORD_8B_COUNT]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ + } MB_8B[CAN_MB_SIZE_MB_8B_GROUP_MB_8B_COUNT]; + struct { /* offset: 0x80, array step: 0x18 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */ + __IO uint32_t WORD[CAN_MB_SIZE_MB_16B_GROUP_MB_16B_WORD_16B_COUNT]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ + } MB_16B[CAN_MB_SIZE_MB_16B_GROUP_MB_16B_COUNT]; + struct { /* offset: 0x80, array step: 0x28 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */ + __IO uint32_t WORD[CAN_MB_SIZE_MB_32B_GROUP_MB_32B_WORD_32B_COUNT]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ + } MB_32B[CAN_MB_SIZE_MB_32B_GROUP_MB_32B_COUNT]; + struct { /* offset: 0x80, array step: 0x48 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */ + __IO uint32_t WORD[CAN_MB_SIZE_MB_64B_GROUP_MB_64B_WORD_64B_COUNT]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ + } MB_64B[CAN_MB_SIZE_MB_64B_GROUP_MB_64B_COUNT]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[CAN_MB_SIZE_MB_GROUP_MB_COUNT]; + }; + uint8_t RESERVED_5[1536]; + __IO uint32_t RXIMR[CAN_RXIMR_COUNT]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_6[512]; + __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1, offset: 0xB00 */ + __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2, offset: 0xB04 */ + __IO uint32_t WU_MTC; /**< Pretended Networking Wake-Up Match, offset: 0xB08 */ + __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1, offset: 0xB0C */ + __IO uint32_t FLT_DLC; /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */ + __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */ + __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */ + __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */ + __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */ + __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */ + uint8_t RESERVED_7[24]; + struct { /* offset: 0xB40, array step: 0x10 */ + __I uint32_t CS; /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */ + __I uint32_t ID; /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */ + __I uint32_t D03; /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */ + __I uint32_t D47; /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ + } WMB[CAN_WMB_COUNT]; + uint8_t RESERVED_8[112]; + __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ + __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ + __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ + uint8_t RESERVED_9[9192]; + __IO uint32_t ERFFEL[CAN_ERFFEL_COUNT]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration */ +/*! @{ */ + +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +/*! MAXMB - Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) + +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A: One full ID (standard and extended) per ID filter table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. + * 0b11..Format D: All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) + +#define CAN_MCR_FDEN_MASK (0x800U) +#define CAN_MCR_FDEN_SHIFT (11U) +/*! FDEN - CAN FD Operation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) + +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) + +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) + +#define CAN_MCR_PNET_EN_MASK (0x4000U) +#define CAN_MCR_PNET_EN_SHIFT (14U) +/*! PNET_EN - Pretended Networking Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) + +#define CAN_MCR_DMA_MASK (0x8000U) +#define CAN_MCR_DMA_SHIFT (15U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) + +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) + +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) + +#define CAN_MCR_DOZE_MASK (0x40000U) +#define CAN_MCR_DOZE_SHIFT (18U) +/*! DOZE - Doze Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) + +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) + +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) + +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) + +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self-Wake-Up Feature + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) + +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV - Supervisor Mode + * 0b0..User mode + * 0b1..Supervisor mode + */ +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) + +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) + +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b0..No reset + * 0b1..Soft reset affects reset registers + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) + +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) + +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode. + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) + +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) + +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) + +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) + +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +/*! PROPSEG - Propagation Segment */ +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) + +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) + +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) + +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) + +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) + +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b0..One sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two + * preceding samples. A majority rule is used. + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) + +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) + +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) + +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) + +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) + +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) + +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +/*! PSEG2 - Phase Segment 2 */ +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) + +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +/*! PSEG1 - Phase Segment 1 */ +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) + +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +/*! RJW - Resync Jump Width */ +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) + +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +/*! PRESDIV - Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free-Running Timer */ +/*! @{ */ + +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer Value */ +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - RX Message Buffers Global Mask */ +/*! @{ */ + +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Global Mask for RX Message Buffers */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Receive 14 Mask */ +/*! @{ */ + +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - RX Buffer 14 Mask Bits */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Receive 15 Mask */ +/*! @{ */ + +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - RX Buffer 15 Mask Bits */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter */ +/*! @{ */ + +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +/*! TXERRCNT - Transmit Error Counter */ +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) + +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +/*! RXERRCNT - Receive Error Counter */ +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ +#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) + +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ +#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 */ +/*! @{ */ + +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-up Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) + +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates setting of any error flag in the Error and Status register. + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) + +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt Flag + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) + +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) + +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus Off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) + +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b0..Not transmitting + * 0b1..Transmitting + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) + +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) + +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - RX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) + +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..TXERRCNT is 96 or greater. + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) + +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) + +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) + +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) + +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) + +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) + +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) + +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) + +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) + +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) +#define CAN_ESR1_BOFFDONEINT_SHIFT (19U) +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence + * 0b1..FlexCAN module has completed Bus Off process. + */ +#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) + +#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) +#define CAN_ESR1_ERRINT_FAST_SHIFT (20U) +/*! ERRINT_FAST - Fast Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. + */ +#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) + +#define CAN_ESR1_ERROVR_MASK (0x200000U) +#define CAN_ESR1_ERROVR_SHIFT (21U) +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun + */ +#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) + +#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) +#define CAN_ESR1_STFERR_FAST_SHIFT (26U) +/*! STFERR_FAST - Fast Stuffing Error Flag + * 0b0..No such occurrence. + * 0b1..A stuffing error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) + +#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) +#define CAN_ESR1_FRMERR_FAST_SHIFT (27U) +/*! FRMERR_FAST - Fast Form Error Flag + * 0b0..No such occurrence. + * 0b1..A form error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) + +#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) +#define CAN_ESR1_CRCERR_FAST_SHIFT (28U) +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) + +#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) +#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) +/*! BIT0ERR_FAST - Fast Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) + +#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) +#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) +/*! BIT1ERR_FAST - Fast Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 */ +/*! @{ */ + +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUF31TO0M_SHIFT (0U) +/*! BUF31TO0M - Buffer MBi Mask */ +#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 */ +/*! @{ */ + +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. + */ +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) + +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) + +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) + +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) + +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) + +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_PES_MASK (0x1U) +#define CAN_CTRL2_PES_SHIFT (0U) +/*! PES - Payload Byte and Bit Order Selection + * 0b0..Big-endian + * 0b1..Little-endian + */ +#define CAN_CTRL2_PES(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PES_SHIFT)) & CAN_CTRL2_PES_MASK) + +#define CAN_CTRL2_ASD_MASK (0x2U) +#define CAN_CTRL2_ASD_SHIFT (1U) +/*! ASD - ACK Suppression Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_ASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ASD_SHIFT)) & CAN_CTRL2_ASD_MASK) + +#define CAN_CTRL2_EDFLTDIS_MASK (0x800U) +#define CAN_CTRL2_EDFLTDIS_SHIFT (11U) +/*! EDFLTDIS - Edge Filter Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) + +#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) +#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) +/*! ISOCANFDEN - ISO CAN FD Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) + +#define CAN_CTRL2_BTE_MASK (0x2000U) +#define CAN_CTRL2_BTE_SHIFT (13U) +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) + +#define CAN_CTRL2_PREXCEN_MASK (0x4000U) +#define CAN_CTRL2_PREXCEN_SHIFT (14U) +/*! PREXCEN - Protocol Exception Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) + +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) + +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b0..Generated + * 0b1..Stored + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) + +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) + +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +/*! TASD - Transmission Arbitration Start Delay */ +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) + +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +/*! RFFN - Number of Legacy Receive FIFO Filters */ +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) + +#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) +#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) +/*! BOFFDONEMSK - Bus Off Done Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) + +#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) +#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 */ +/*! @{ */ + +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) + +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b0..Invalid + * 0b1..Valid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) + +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +/*! LPTM - Lowest Priority TX Message Buffer */ +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - Cyclic Redundancy Check */ +/*! @{ */ + +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +/*! TXCRC - Transmitted CRC value */ +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) + +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +/*! MBCRC - CRC Message Buffer */ +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ +/*! @{ */ + +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy RX FIFO Global Mask Bits */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Legacy RX FIFO Information */ +/*! @{ */ + +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +/*! IDHIT - Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CBT - CAN Bit Timing */ +/*! @{ */ + +#define CAN_CBT_EPSEG2_MASK (0x1FU) +#define CAN_CBT_EPSEG2_SHIFT (0U) +/*! EPSEG2 - Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) + +#define CAN_CBT_EPSEG1_MASK (0x3E0U) +#define CAN_CBT_EPSEG1_SHIFT (5U) +/*! EPSEG1 - Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) + +#define CAN_CBT_EPROPSEG_MASK (0xFC00U) +#define CAN_CBT_EPROPSEG_SHIFT (10U) +/*! EPROPSEG - Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) + +#define CAN_CBT_ERJW_MASK (0x1F0000U) +#define CAN_CBT_ERJW_SHIFT (16U) +/*! ERJW - Extended Resync Jump Width */ +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) + +#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) +#define CAN_CBT_EPRESDIV_SHIFT (21U) +/*! EPRESDIV - Extended Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) + +#define CAN_CBT_BTF_MASK (0x80000000U) +#define CAN_CBT_BTF_SHIFT (31U) +/*! BTF - Bit Timing Format Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB8B (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B2 (2U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB16B (21U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B2 (4U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB32B (12U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B2 (8U) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */ +/*! @{ */ + +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running + * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field + * appears on the CAN bus. + */ +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) + +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +/*! DLC - Length of the data to be stored/transmitted. */ +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) + +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) + +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) + +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) + +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by + * the FlexCAN module itself, as part of the message buffer matching and arbitration process. + */ +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +#define CAN_CS_ESI_MASK (0x20000000U) +#define CAN_CS_ESI_SHIFT (29U) +/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) + +#define CAN_CS_BRS_MASK (0x40000000U) +#define CAN_CS_BRS_SHIFT (30U) +/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) + +#define CAN_CS_EDL_MASK (0x80000000U) +#define CAN_CS_EDL_SHIFT (31U) +/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. + * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + */ +#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB64B (7U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */ +/*! @{ */ + +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +/*! EXT - Contains extended (LOW word) identifier of message buffer. */ +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) + +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) + +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only + * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular + * ID to define the transmission priority. + */ +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB64B (7U) + +/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */ +/*! @{ */ + +#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) + +#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) + +#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_11_SHIFT (0U) +/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) + +#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_15_SHIFT (0U) +/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) + +#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_19_SHIFT (0U) +/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) + +#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_23_SHIFT (0U) +/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) + +#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_27_SHIFT (0U) +/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) + +#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_31_SHIFT (0U) +/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) + +#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_35_SHIFT (0U) +/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) + +#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_39_SHIFT (0U) +/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) + +#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_43_SHIFT (0U) +/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) + +#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_47_SHIFT (0U) +/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) + +#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_51_SHIFT (0U) +/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) + +#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_55_SHIFT (0U) +/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) + +#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_59_SHIFT (0U) +/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) + +#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_63_SHIFT (0U) +/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) + +#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) + +#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) + +#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_10_SHIFT (8U) +/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) + +#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_14_SHIFT (8U) +/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) + +#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_18_SHIFT (8U) +/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) + +#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_22_SHIFT (8U) +/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) + +#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_26_SHIFT (8U) +/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) + +#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_30_SHIFT (8U) +/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) + +#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_34_SHIFT (8U) +/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) + +#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_38_SHIFT (8U) +/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) + +#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_42_SHIFT (8U) +/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) + +#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_46_SHIFT (8U) +/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) + +#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_50_SHIFT (8U) +/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) + +#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_54_SHIFT (8U) +/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) + +#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_58_SHIFT (8U) +/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) + +#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_62_SHIFT (8U) +/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) + +#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) + +#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) + +#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_9_SHIFT (16U) +/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) + +#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_13_SHIFT (16U) +/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) + +#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_17_SHIFT (16U) +/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) + +#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_21_SHIFT (16U) +/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) + +#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_25_SHIFT (16U) +/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) + +#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_29_SHIFT (16U) +/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) + +#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_33_SHIFT (16U) +/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) + +#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_37_SHIFT (16U) +/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) + +#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_41_SHIFT (16U) +/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) + +#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_45_SHIFT (16U) +/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) + +#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_49_SHIFT (16U) +/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) + +#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_53_SHIFT (16U) +/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) + +#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_57_SHIFT (16U) +/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) + +#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_61_SHIFT (16U) +/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) + +#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) + +#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) + +#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_8_SHIFT (24U) +/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) + +#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_12_SHIFT (24U) +/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) + +#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_16_SHIFT (24U) +/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) + +#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_20_SHIFT (24U) +/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) + +#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_24_SHIFT (24U) +/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) + +#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_28_SHIFT (24U) +/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) + +#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_32_SHIFT (24U) +/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) + +#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_36_SHIFT (24U) +/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) + +#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_40_SHIFT (24U) +/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) + +#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_44_SHIFT (24U) +/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) + +#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_48_SHIFT (24U) +/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) + +#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_52_SHIFT (24U) +/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) + +#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_56_SHIFT (24U) +/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) + +#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_60_SHIFT (24U) +/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) +/*! @} */ + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B (7U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B2 (16U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (32U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */ +/*! @{ */ + +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) + +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) + +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) + +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (32U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */ +/*! @{ */ + +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) + +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) + +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) + +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (32U) + +/*! @name RXIMR - Receive Individual Mask */ +/*! @{ */ + +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/*! @name CTRL1_PN - Pretended Networking Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PN_FCS_MASK (0x3U) +#define CAN_CTRL1_PN_FCS_SHIFT (0U) +/*! FCS - Filtering Combination Selection + * 0b00..Message ID filtering only + * 0b01..Message ID filtering and payload filtering + * 0b10..Message ID filtering occurring a specified number of times + * 0b11..Message ID filtering and payload filtering a specified number of times + */ +#define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK) + +#define CAN_CTRL1_PN_IDFS_MASK (0xCU) +#define CAN_CTRL1_PN_IDFS_SHIFT (2U) +/*! IDFS - ID Filtering Selection + * 0b00..Match ID contents to an exact target value + * 0b01..Match an ID value greater than or equal to a specified target value + * 0b10..Match an ID value smaller than or equal to a specified target value + * 0b11..Match an ID value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) + +#define CAN_CTRL1_PN_PLFS_MASK (0x30U) +#define CAN_CTRL1_PN_PLFS_SHIFT (4U) +/*! PLFS - Payload Filtering Selection + * 0b00..Match payload contents to an exact target value + * 0b01..Match a payload value greater than or equal to a specified target value + * 0b10..Match a payload value smaller than or equal to a specified target value + * 0b11..Match upon a payload value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) + +#define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) +#define CAN_CTRL1_PN_NMATCH_SHIFT (8U) +/*! NMATCH - Number of Messages Matching the Same Filtering Criteria + * 0b00000001..Once + * 0b00000010..Twice + * 0b11111111..255 times + */ +#define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) + +#define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) +#define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) +/*! WUMF_MSK - Wake-up by Matching Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) + +#define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) +#define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) +/*! WTOF_MSK - Wake-up by Timeout Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) +/*! @} */ + +/*! @name CTRL2_PN - Pretended Networking Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) +#define CAN_CTRL2_PN_MATCHTO_SHIFT (0U) +/*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */ +#define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) +/*! @} */ + +/*! @name WU_MTC - Pretended Networking Wake-Up Match */ +/*! @{ */ + +#define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) +#define CAN_WU_MTC_MCOUNTER_SHIFT (8U) +/*! MCOUNTER - Number of Matches in Pretended Networking */ +#define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) + +#define CAN_WU_MTC_WUMF_MASK (0x10000U) +#define CAN_WU_MTC_WUMF_SHIFT (16U) +/*! WUMF - Wake-up by Match Flag + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) + +#define CAN_WU_MTC_WTOF_MASK (0x20000U) +#define CAN_WU_MTC_WTOF_SHIFT (17U) +/*! WTOF - Wake-up by Timeout Flag Bit + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) +/*! @} */ + +/*! @name FLT_ID1 - Pretended Networking ID Filter 1 */ +/*! @{ */ + +#define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID1_FLT_ID1_SHIFT (0U) +/*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */ +#define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK) + +#define CAN_FLT_ID1_FLT_RTR_MASK (0x20000000U) +#define CAN_FLT_ID1_FLT_RTR_SHIFT (29U) +/*! FLT_RTR - Remote Transmission Request Filter + * 0b0..Reject remote frame (accept data frame) + * 0b1..Accept remote frame + */ +#define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK) + +#define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) +#define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) +/*! FLT_IDE - ID Extended Filter + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) +/*! @} */ + +/*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */ +/*! @{ */ + +#define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) +#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT (0U) +/*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK) + +#define CAN_FLT_DLC_FLT_DLC_LO_MASK (0xF0000U) +#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT (16U) +/*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) +/*! @} */ + +/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */ +/*! @{ */ + +#define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL1_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data byte 3 */ +#define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) + +#define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL1_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data byte 2 */ +#define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) + +#define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL1_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data byte 1 */ +#define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) + +#define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL1_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data byte 0 */ +#define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL1_HI - Pretended Networking Payload High Filter 1 */ +/*! @{ */ + +#define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL1_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data byte 7 */ +#define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) + +#define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL1_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data byte 6 */ +#define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) + +#define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL1_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data byte 5 */ +#define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) + +#define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL1_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data byte 4 */ +#define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */ +/*! @{ */ + +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) +/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */ +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) + +#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) +#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) +/*! RTR_MSK - Remote Transmission Request Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) + +#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) +#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) +/*! IDE_MSK - ID Extended Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name WMB_CS - Wake-Up Message Buffer */ +/*! @{ */ + +#define CAN_WMB_CS_DLC_MASK (0xF0000U) +#define CAN_WMB_CS_DLC_SHIFT (16U) +/*! DLC - Length of Data in Bytes */ +#define CAN_WMB_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK) + +#define CAN_WMB_CS_RTR_MASK (0x100000U) +#define CAN_WMB_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request + * 0b0..Data + * 0b1..Remote + */ +#define CAN_WMB_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK) + +#define CAN_WMB_CS_IDE_MASK (0x200000U) +#define CAN_WMB_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended Bit + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_WMB_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK) + +#define CAN_WMB_CS_SRR_MASK (0x400000U) +#define CAN_WMB_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request + * 0b0..Dominant + * 0b1..Recessive + */ +#define CAN_WMB_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK) +/*! @} */ + +/* The count of CAN_WMB_CS */ +#define CAN_WMB_CS_COUNT (4U) + +/*! @name WMB_ID - Wake-Up Message Buffer for ID */ +/*! @{ */ + +#define CAN_WMB_ID_ID_MASK (0x1FFFFFFFU) +#define CAN_WMB_ID_ID_SHIFT (0U) +/*! ID - Received ID in Pretended Networking Mode */ +#define CAN_WMB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK) +/*! @} */ + +/* The count of CAN_WMB_ID */ +#define CAN_WMB_ID_COUNT (4U) + +/*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */ +/*! @{ */ + +#define CAN_WMB_D03_Data_byte_3_MASK (0xFFU) +#define CAN_WMB_D03_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_WMB_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK) + +#define CAN_WMB_D03_Data_byte_2_MASK (0xFF00U) +#define CAN_WMB_D03_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_WMB_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK) + +#define CAN_WMB_D03_Data_byte_1_MASK (0xFF0000U) +#define CAN_WMB_D03_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_WMB_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK) + +#define CAN_WMB_D03_Data_byte_0_MASK (0xFF000000U) +#define CAN_WMB_D03_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_WMB_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK) +/*! @} */ + +/* The count of CAN_WMB_D03 */ +#define CAN_WMB_D03_COUNT (4U) + +/*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */ +/*! @{ */ + +#define CAN_WMB_D47_Data_byte_7_MASK (0xFFU) +#define CAN_WMB_D47_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_WMB_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK) + +#define CAN_WMB_D47_Data_byte_6_MASK (0xFF00U) +#define CAN_WMB_D47_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_WMB_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK) + +#define CAN_WMB_D47_Data_byte_5_MASK (0xFF0000U) +#define CAN_WMB_D47_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_WMB_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK) + +#define CAN_WMB_D47_Data_byte_4_MASK (0xFF000000U) +#define CAN_WMB_D47_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_WMB_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK) +/*! @} */ + +/* The count of CAN_WMB_D47 */ +#define CAN_WMB_D47_COUNT (4U) + +/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ +/*! @{ */ + +#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) +#define CAN_EPRS_ENPRESDIV_SHIFT (0U) +/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ +#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) + +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) +#define CAN_EPRS_EDPRESDIV_SHIFT (16U) +/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ +#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) +/*! @} */ + +/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ +/*! @{ */ + +#define CAN_ENCBT_NTSEG1_MASK (0xFFU) +#define CAN_ENCBT_NTSEG1_SHIFT (0U) +/*! NTSEG1 - Nominal Time Segment 1 */ +#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) + +#define CAN_ENCBT_NTSEG2_MASK (0x7F000U) +#define CAN_ENCBT_NTSEG2_SHIFT (12U) +/*! NTSEG2 - Nominal Time Segment 2 */ +#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) + +#define CAN_ENCBT_NRJW_MASK (0x1FC00000U) +#define CAN_ENCBT_NRJW_SHIFT (22U) +/*! NRJW - Nominal Resynchronization Jump Width */ +#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) +/*! @} */ + +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ +/*! @{ */ + +#define CAN_EDCBT_DTSEG1_MASK (0x1FU) +#define CAN_EDCBT_DTSEG1_SHIFT (0U) +/*! DTSEG1 - Data Phase Segment 1 */ +#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) + +#define CAN_EDCBT_DTSEG2_MASK (0xF000U) +#define CAN_EDCBT_DTSEG2_SHIFT (12U) +/*! DTSEG2 - Data Phase Time Segment 2 */ +#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) + +#define CAN_EDCBT_DRJW_MASK (0x3C00000U) +#define CAN_EDCBT_DRJW_SHIFT (22U) +/*! DRJW - Data Phase Resynchronization Jump Width */ +#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) +/*! @} */ + +/*! @name ETDC - Enhanced Transceiver Delay Compensation */ +/*! @{ */ + +#define CAN_ETDC_ETDCVAL_MASK (0xFFU) +#define CAN_ETDC_ETDCVAL_SHIFT (0U) +/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ +#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) + +#define CAN_ETDC_ETDCFAIL_MASK (0x8000U) +#define CAN_ETDC_ETDCFAIL_SHIFT (15U) +/*! ETDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) + +#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) +#define CAN_ETDC_ETDCOFF_SHIFT (16U) +/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ +#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) + +#define CAN_ETDC_TDMDIS_MASK (0x40000000U) +#define CAN_ETDC_TDMDIS_SHIFT (30U) +/*! TDMDIS - Transceiver Delay Measurement Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) + +#define CAN_ETDC_ETDCEN_MASK (0x80000000U) +#define CAN_ETDC_ETDCEN_SHIFT (31U) +/*! ETDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) +/*! @} */ + +/*! @name FDCTRL - CAN FD Control */ +/*! @{ */ + +#define CAN_FDCTRL_TDCVAL_MASK (0x3FU) +#define CAN_FDCTRL_TDCVAL_SHIFT (0U) +/*! TDCVAL - Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) + +#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) +#define CAN_FDCTRL_TDCOFF_SHIFT (8U) +/*! TDCOFF - Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + +#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) +#define CAN_FDCTRL_TDCFAIL_SHIFT (14U) +/*! TDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) + +#define CAN_FDCTRL_TDCEN_MASK (0x8000U) +#define CAN_FDCTRL_TDCEN_SHIFT (15U) +/*! TDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) + +#define CAN_FDCTRL_MBDSR0_MASK (0x30000U) +#define CAN_FDCTRL_MBDSR0_SHIFT (16U) +/*! MBDSR0 - Message Buffer Data Size for Region 0 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + +#define CAN_FDCTRL_FDRATE_MASK (0x80000000U) +#define CAN_FDCTRL_FDRATE_SHIFT (31U) +/*! FDRATE - Bit Rate Switch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) +/*! @} */ + +/*! @name FDCBT - CAN FD Bit Timing */ +/*! @{ */ + +#define CAN_FDCBT_FPSEG2_MASK (0x7U) +#define CAN_FDCBT_FPSEG2_SHIFT (0U) +/*! FPSEG2 - Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + +#define CAN_FDCBT_FPSEG1_MASK (0xE0U) +#define CAN_FDCBT_FPSEG1_SHIFT (5U) +/*! FPSEG1 - Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + +#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) +#define CAN_FDCBT_FPROPSEG_SHIFT (10U) +/*! FPROPSEG - Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + +#define CAN_FDCBT_FRJW_MASK (0x70000U) +#define CAN_FDCBT_FRJW_SHIFT (16U) +/*! FRJW - Fast Resync Jump Width */ +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) +#define CAN_FDCBT_FPRESDIV_SHIFT (20U) +/*! FPRESDIV - Fast Prescaler Division Factor */ +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) +/*! @} */ + +/*! @name FDCRC - CAN FD CRC */ +/*! @{ */ + +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) +#define CAN_FDCRC_FD_TXCRC_SHIFT (0U) +/*! FD_TXCRC - Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24U) +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) +/*! @} */ + +/*! @name ERFCR - Enhanced RX FIFO Control */ +/*! @{ */ + +#define CAN_ERFCR_ERFWM_MASK (0x1FU) +#define CAN_ERFCR_ERFWM_SHIFT (0U) +/*! ERFWM - Enhanced RX FIFO Watermark */ +#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) + +#define CAN_ERFCR_NFE_MASK (0x3F00U) +#define CAN_ERFCR_NFE_SHIFT (8U) +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ +#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) + +#define CAN_ERFCR_NEXIF_MASK (0x7F0000U) +#define CAN_ERFCR_NEXIF_SHIFT (16U) +/*! NEXIF - Number of Extended ID Filter Elements */ +#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) + +#define CAN_ERFCR_DMALW_MASK (0x7C000000U) +#define CAN_ERFCR_DMALW_SHIFT (26U) +/*! DMALW - DMA Last Word */ +#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) + +#define CAN_ERFCR_ERFEN_MASK (0x80000000U) +#define CAN_ERFCR_ERFEN_SHIFT (31U) +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) +/*! @} */ + +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ +/*! @{ */ + +#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) +#define CAN_ERFIER_ERFDAIE_SHIFT (28U) +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) + +#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) +#define CAN_ERFIER_ERFWMIIE_SHIFT (29U) +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) + +#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) +#define CAN_ERFIER_ERFOVFIE_SHIFT (30U) +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) + +#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) +#define CAN_ERFIER_ERFUFWIE_SHIFT (31U) +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) +/*! @} */ + +/*! @name ERFSR - Enhanced RX FIFO Status */ +/*! @{ */ + +#define CAN_ERFSR_ERFEL_MASK (0x3FU) +#define CAN_ERFSR_ERFEL_SHIFT (0U) +/*! ERFEL - Enhanced RX FIFO Elements */ +#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) + +#define CAN_ERFSR_ERFF_MASK (0x10000U) +#define CAN_ERFSR_ERFF_SHIFT (16U) +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) + +#define CAN_ERFSR_ERFE_MASK (0x20000U) +#define CAN_ERFSR_ERFE_SHIFT (17U) +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) + +#define CAN_ERFSR_ERFCLR_MASK (0x8000000U) +#define CAN_ERFSR_ERFCLR_SHIFT (27U) +/*! ERFCLR - Enhanced RX FIFO Clear + * 0b0..No effect + * 0b1..Clear enhanced RX FIFO content + */ +#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) + +#define CAN_ERFSR_ERFDA_MASK (0x10000000U) +#define CAN_ERFSR_ERFDA_SHIFT (28U) +/*! ERFDA - Enhanced RX FIFO Data Available Flag + * 0b0..No such occurrence + * 0b1..At least one message stored in Enhanced RX FIFO + */ +#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) + +#define CAN_ERFSR_ERFWMI_MASK (0x20000000U) +#define CAN_ERFSR_ERFWMI_SHIFT (29U) +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag + * 0b0..No such occurrence + * 0b1..Number of messages in FIFO is greater than the watermark + */ +#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) + +#define CAN_ERFSR_ERFOVF_MASK (0x40000000U) +#define CAN_ERFSR_ERFOVF_SHIFT (30U) +/*! ERFOVF - Enhanced RX FIFO Overflow Flag + * 0b0..No such occurrence + * 0b1..Overflow + */ +#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) + +#define CAN_ERFSR_ERFUFW_MASK (0x80000000U) +#define CAN_ERFSR_ERFUFW_SHIFT (31U) +/*! ERFUFW - Enhanced RX FIFO Underflow Flag + * 0b0..No such occurrence + * 0b1..Underflow + */ +#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) +/*! @} */ + +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ +/*! @{ */ + +#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) +#define CAN_ERFFEL_FEL_SHIFT (0U) +/*! FEL - Filter Element Bits */ +#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CAN_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CDOG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CDOG.h new file mode 100644 index 000000000..0b03de7e9 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CDOG.h @@ -0,0 +1,472 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for CDOG +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_CDOG.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for CDOG + * + * CMSIS Peripheral Access Layer for CDOG + */ + +#if !defined(PERI_CDOG_H_) +#define PERI_CDOG_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer + * @{ + */ + +/** CDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ + __IO uint32_t RELOAD; /**< Instruction Timer Reload Register, offset: 0x4 */ + __I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Status 1 Register, offset: 0x10 */ + __I uint32_t STATUS2; /**< Status 2 Register, offset: 0x14 */ + __IO uint32_t FLAGS; /**< Flags Register, offset: 0x18 */ + __IO uint32_t PERSISTENT; /**< Persistent Data Storage Register, offset: 0x1C */ + __O uint32_t START; /**< START Command Register, offset: 0x20 */ + __O uint32_t STOP; /**< STOP Command Register, offset: 0x24 */ + __O uint32_t RESTART; /**< RESTART Command Register, offset: 0x28 */ + __O uint32_t ADD; /**< ADD Command Register, offset: 0x2C */ + __O uint32_t ADD1; /**< ADD1 Command Register, offset: 0x30 */ + __O uint32_t ADD16; /**< ADD16 Command Register, offset: 0x34 */ + __O uint32_t ADD256; /**< ADD256 Command Register, offset: 0x38 */ + __O uint32_t SUB; /**< SUB Command Register, offset: 0x3C */ + __O uint32_t SUB1; /**< SUB1 Command Register, offset: 0x40 */ + __O uint32_t SUB16; /**< SUB16 Command Register, offset: 0x44 */ + __O uint32_t SUB256; /**< SUB256 Command Register, offset: 0x48 */ + __O uint32_t ASSERT16; /**< ASSERT16 Command Register, offset: 0x4C */ +} CDOG_Type; + +/* ---------------------------------------------------------------------------- + -- CDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Register_Masks CDOG Register Masks + * @{ + */ + +/*! @name CONTROL - Control Register */ +/*! @{ */ + +#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) +#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - Lock control + * 0b01..Locked + * 0b10..Unlocked + */ +#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) + +#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) +#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) +/*! TIMEOUT_CTRL - TIMEOUT fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) + +#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) +#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) +/*! MISCOMPARE_CTRL - MISCOMPARE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) + +#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) +#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) +/*! SEQUENCE_CTRL - SEQUENCE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) + +#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) +#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) +/*! STATE_CTRL - STATE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) + +#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) +#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) +/*! ADDRESS_CTRL - ADDRESS fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) + +#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) +#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) +/*! IRQ_PAUSE - IRQ pause control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) + +#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) +#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) +/*! DEBUG_HALT_CTRL - DEBUG_HALT control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) +/*! @} */ + +/*! @name RELOAD - Instruction Timer Reload Register */ +/*! @{ */ + +#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) +#define CDOG_RELOAD_RLOAD_SHIFT (0U) +/*! RLOAD - Instruction Timer reload value */ +#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) +/*! @} */ + +/*! @name INSTRUCTION_TIMER - Instruction Timer Register */ +/*! @{ */ + +#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) +#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) +/*! INSTIM - Current value of the Instruction Timer */ +#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) +/*! @} */ + +/*! @name STATUS - Status 1 Register */ +/*! @{ */ + +#define CDOG_STATUS_NUMTOF_MASK (0xFFU) +#define CDOG_STATUS_NUMTOF_SHIFT (0U) +/*! NUMTOF - Number of TIMEOUT faults (FLAGS[TIMEOUT_FLAG]) since the last POR */ +#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) + +#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) +#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) +/*! NUMMISCOMPF - Number of MISCOMPARE faults (FLAGS[MISCOMPARE_FLAG]) since the last POR */ +#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) + +#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) +#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) +/*! NUMILSEQF - Number of SEQUENCE faults (FLAGS[SEQUENCE_FLAG]) since the last POR */ +#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) + +#define CDOG_STATUS_CURST_MASK (0xF0000000U) +#define CDOG_STATUS_CURST_SHIFT (28U) +/*! CURST - Current State */ +#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) +/*! @} */ + +/*! @name STATUS2 - Status 2 Register */ +/*! @{ */ + +#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) +#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) +/*! NUMCNTF - Number of CONTROL faults (FLAGS[CONTROL_FLAG]) since the last POR */ +#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) + +#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) +#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) +/*! NUMILLSTF - Number of STATE faults (FLAGS[STATE_FLAG]) since the last POR */ +#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) + +#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) +#define CDOG_STATUS2_NUMILLA_SHIFT (16U) +/*! NUMILLA - Number of ADDRESS faults (FLAGS[ADDR_FLAG]) since the last POR */ +#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) +/*! @} */ + +/*! @name FLAGS - Flags Register */ +/*! @{ */ + +#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) +#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) +/*! TO_FLAG - TIMEOUT fault flag + * 0b0..A TIMEOUT fault has not occurred + * 0b1..A TIMEOUT fault has occurred + */ +#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) + +#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) +#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) +/*! MISCOM_FLAG - MISCOMPARE fault flag + * 0b0..A MISCOMPARE fault has not occurred + * 0b1..A MISCOMPARE fault has occurred + */ +#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) + +#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) +#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) +/*! SEQ_FLAG - SEQUENCE fault flag + * 0b0..A SEQUENCE fault has not occurred + * 0b1..A SEQUENCE fault has occurred + */ +#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) + +#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) +#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) +/*! CNT_FLAG - CONTROL fault flag + * 0b0..A CONTROL fault has not occurred + * 0b1..A CONTROL fault has occurred + */ +#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) + +#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) +#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) +/*! STATE_FLAG - STATE fault flag + * 0b0..A STATE fault has not occurred + * 0b1..A STATE fault has occurred + */ +#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) + +#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) +#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) +/*! ADDR_FLAG - ADDRESS fault flag + * 0b0..An ADDRESS fault has not occurred + * 0b1..An ADDRESS fault has occurred + */ +#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) + +#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) +#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) +/*! POR_FLAG - Power-on reset flag + * 0b0..A Power-on reset event has not occurred + * 0b1..A Power-on reset event has occurred + */ +#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) +/*! @} */ + +/*! @name PERSISTENT - Persistent Data Storage Register */ +/*! @{ */ + +#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) +#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) +/*! PERSIS - Persistent Storage */ +#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) +/*! @} */ + +/*! @name START - START Command Register */ +/*! @{ */ + +#define CDOG_START_STRT_MASK (0xFFFFFFFFU) +#define CDOG_START_STRT_SHIFT (0U) +/*! STRT - Start command */ +#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) +/*! @} */ + +/*! @name STOP - STOP Command Register */ +/*! @{ */ + +#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) +#define CDOG_STOP_STP_SHIFT (0U) +/*! STP - Stop command */ +#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) +/*! @} */ + +/*! @name RESTART - RESTART Command Register */ +/*! @{ */ + +#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) +#define CDOG_RESTART_RSTRT_SHIFT (0U) +/*! RSTRT - Restart command */ +#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) +/*! @} */ + +/*! @name ADD - ADD Command Register */ +/*! @{ */ + +#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) +#define CDOG_ADD_AD_SHIFT (0U) +/*! AD - ADD Write Value */ +#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) +/*! @} */ + +/*! @name ADD1 - ADD1 Command Register */ +/*! @{ */ + +#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) +#define CDOG_ADD1_AD1_SHIFT (0U) +/*! AD1 - ADD 1 */ +#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) +/*! @} */ + +/*! @name ADD16 - ADD16 Command Register */ +/*! @{ */ + +#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) +#define CDOG_ADD16_AD16_SHIFT (0U) +/*! AD16 - ADD 16 */ +#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) +/*! @} */ + +/*! @name ADD256 - ADD256 Command Register */ +/*! @{ */ + +#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) +#define CDOG_ADD256_AD256_SHIFT (0U) +/*! AD256 - ADD 256 */ +#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) +/*! @} */ + +/*! @name SUB - SUB Command Register */ +/*! @{ */ + +#define CDOG_SUB_SB_MASK (0xFFFFFFFFU) +#define CDOG_SUB_SB_SHIFT (0U) +/*! SB - Subtract Write Value */ +#define CDOG_SUB_SB(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK) +/*! @} */ + +/*! @name SUB1 - SUB1 Command Register */ +/*! @{ */ + +#define CDOG_SUB1_SB1_MASK (0xFFFFFFFFU) +#define CDOG_SUB1_SB1_SHIFT (0U) +/*! SB1 - Subtract 1 */ +#define CDOG_SUB1_SB1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK) +/*! @} */ + +/*! @name SUB16 - SUB16 Command Register */ +/*! @{ */ + +#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) +#define CDOG_SUB16_SB16_SHIFT (0U) +/*! SB16 - Subtract 16 */ +#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) +/*! @} */ + +/*! @name SUB256 - SUB256 Command Register */ +/*! @{ */ + +#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) +#define CDOG_SUB256_SB256_SHIFT (0U) +/*! SB256 - Subtract 256 */ +#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) +/*! @} */ + +/*! @name ASSERT16 - ASSERT16 Command Register */ +/*! @{ */ + +#define CDOG_ASSERT16_AST16_MASK (0xFFFFFFFFU) +#define CDOG_ASSERT16_AST16_SHIFT (0U) +/*! AST16 - ASSERT16 Command */ +#define CDOG_ASSERT16_AST16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CDOG_Register_Masks */ + + +/*! + * @} + */ /* end of group CDOG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CDOG_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CMC.h new file mode 100644 index 000000000..7ddcee0ac --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CMC.h @@ -0,0 +1,767 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for CMC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_CMC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for CMC + * + * CMSIS Peripheral Access Layer for CMC + */ + +#if !defined(PERI_CMC_H_) +#define PERI_CMC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer + * @{ + */ + +/** CMC - Size of Registers Arrays */ +#define CMC_PMCTRL_COUNT 1u +#define CMC_MR_COUNT 1u +#define CMC_FM_COUNT 1u + +/** CMC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CKCTRL; /**< Clock Control, offset: 0x10 */ + __IO uint32_t CKSTAT; /**< Clock Status, offset: 0x14 */ + __IO uint32_t PMPROT; /**< Power Mode Protection, offset: 0x18 */ + __IO uint32_t GPMCTRL; /**< Global Power Mode Control, offset: 0x1C */ + __IO uint32_t PMCTRL[CMC_PMCTRL_COUNT]; /**< Power Mode Control, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[92]; + __I uint32_t SRS; /**< System Reset Status, offset: 0x80 */ + __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x84 */ + __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x88 */ + __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x8C */ + __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x90 */ + uint8_t RESERVED_2[12]; + __IO uint32_t MR[CMC_MR_COUNT]; /**< Mode, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t FM[CMC_FM_COUNT]; /**< Force Mode, array offset: 0xB0, array step: 0x4 */ + uint8_t RESERVED_4[44]; + __IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */ + uint8_t RESERVED_5[44]; + __IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DBGCTL; /**< Debug Control, offset: 0x120 */ +} CMC_Type; + +/* ---------------------------------------------------------------------------- + -- CMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Register_Masks CMC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define CMC_VERID_FEATURE_MASK (0xFFFFU) +#define CMC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define CMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK) + +#define CMC_VERID_MINOR_MASK (0xFF0000U) +#define CMC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define CMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK) + +#define CMC_VERID_MAJOR_MASK (0xFF000000U) +#define CMC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define CMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CKCTRL - Clock Control */ +/*! @{ */ + +#define CMC_CKCTRL_CKMODE_MASK (0xFU) +#define CMC_CKCTRL_CKMODE_SHIFT (0U) +/*! CKMODE - Clocking Mode + * 0b0000..Core clock is on + * 0b0001..Core clock is off + * 0b1111..Core, platform, and peripheral clocks are off, and core enters Low-Power mode + */ +#define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK) + +#define CMC_CKCTRL_LOCK_MASK (0x80000000U) +#define CMC_CKCTRL_LOCK_SHIFT (31U) +/*! LOCK - Lock + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_CKCTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK) +/*! @} */ + +/*! @name CKSTAT - Clock Status */ +/*! @{ */ + +#define CMC_CKSTAT_CKMODE_MASK (0xFU) +#define CMC_CKSTAT_CKMODE_SHIFT (0U) +/*! CKMODE - Low Power Status + * 0b0000..Core clock is on + * 0b0001..Core clock is off + * 0b1111..Core, platform, and peripheral clocks are off, and core enters Low-Power mode + */ +#define CMC_CKSTAT_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK) + +#define CMC_CKSTAT_WAKEUP_MASK (0xFF00U) +#define CMC_CKSTAT_WAKEUP_SHIFT (8U) +/*! WAKEUP - Wake-up Source */ +#define CMC_CKSTAT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK) + +#define CMC_CKSTAT_VALID_MASK (0x80000000U) +#define CMC_CKSTAT_VALID_SHIFT (31U) +/*! VALID - Clock Status Valid + * 0b0..Core clock not gated + * 0b1..Core clock was gated due to Low-Power mode entry + */ +#define CMC_CKSTAT_VALID(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK) +/*! @} */ + +/*! @name PMPROT - Power Mode Protection */ +/*! @{ */ + +#define CMC_PMPROT_LPMODE_MASK (0xFU) +#define CMC_PMPROT_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Not allowed + * 0b0001..Allowed + * 0b0010..Allowed + * 0b0011..Allowed + * 0b0100..Allowed + * 0b0101..Allowed + * 0b0110..Allowed + * 0b0111..Allowed + * 0b1000..Allowed + * 0b1001..Allowed + * 0b1010..Allowed + * 0b1011..Allowed + * 0b1100..Allowed + * 0b1101..Allowed + * 0b1110..Allowed + * 0b1111..Allowed + */ +#define CMC_PMPROT_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK) + +#define CMC_PMPROT_LOCK_MASK (0x80000000U) +#define CMC_PMPROT_LOCK_SHIFT (31U) +/*! LOCK - Lock Register + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_PMPROT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK) +/*! @} */ + +/*! @name GPMCTRL - Global Power Mode Control */ +/*! @{ */ + +#define CMC_GPMCTRL_LPMODE_MASK (0xFU) +#define CMC_GPMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode */ +#define CMC_GPMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK) +/*! @} */ + +/*! @name PMCTRL - Power Mode Control */ +/*! @{ */ + +#define CMC_PMCTRL_LPMODE_MASK (0xFU) +#define CMC_PMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Active/Sleep + * 0b0001..Deep Sleep + * 0b0011..Power Down + * 0b0111..Reserved + * 0b1111..Deep-Power Down + */ +#define CMC_PMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK) +/*! @} */ + +/*! @name SRS - System Reset Status */ +/*! @{ */ + +#define CMC_SRS_WAKEUP_MASK (0x1U) +#define CMC_SRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK) + +#define CMC_SRS_POR_MASK (0x2U) +#define CMC_SRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK) + +#define CMC_SRS_VD_MASK (0x4U) +#define CMC_SRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK) + +#define CMC_SRS_WARM_MASK (0x10U) +#define CMC_SRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK) + +#define CMC_SRS_FATAL_MASK (0x20U) +#define CMC_SRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK) + +#define CMC_SRS_PIN_MASK (0x100U) +#define CMC_SRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK) + +#define CMC_SRS_DAP_MASK (0x200U) +#define CMC_SRS_DAP_SHIFT (9U) +/*! DAP - Debug Access Port Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK) + +#define CMC_SRS_RSTACK_MASK (0x400U) +#define CMC_SRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK) + +#define CMC_SRS_LPACK_MASK (0x800U) +#define CMC_SRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK) + +#define CMC_SRS_SCG_MASK (0x1000U) +#define CMC_SRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK) + +#define CMC_SRS_WWDT0_MASK (0x2000U) +#define CMC_SRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK) + +#define CMC_SRS_SW_MASK (0x4000U) +#define CMC_SRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK) + +#define CMC_SRS_LOCKUP_MASK (0x8000U) +#define CMC_SRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK) + +#define CMC_SRS_CDOG0_MASK (0x4000000U) +#define CMC_SRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK) + +#define CMC_SRS_JTAG_MASK (0x10000000U) +#define CMC_SRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK) +/*! @} */ + +/*! @name RPC - Reset Pin Control */ +/*! @{ */ + +#define CMC_RPC_FILTCFG_MASK (0x1FU) +#define CMC_RPC_FILTCFG_SHIFT (0U) +/*! FILTCFG - Reset Filter Configuration */ +#define CMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK) + +#define CMC_RPC_FILTEN_MASK (0x100U) +#define CMC_RPC_FILTEN_SHIFT (8U) +/*! FILTEN - Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK) + +#define CMC_RPC_LPFEN_MASK (0x200U) +#define CMC_RPC_LPFEN_SHIFT (9U) +/*! LPFEN - Low-Power Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK) +/*! @} */ + +/*! @name SSRS - Sticky System Reset Status */ +/*! @{ */ + +#define CMC_SSRS_WAKEUP_MASK (0x1U) +#define CMC_SSRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK) + +#define CMC_SSRS_POR_MASK (0x2U) +#define CMC_SSRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK) + +#define CMC_SSRS_VD_MASK (0x4U) +#define CMC_SSRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK) + +#define CMC_SSRS_WARM_MASK (0x10U) +#define CMC_SSRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK) + +#define CMC_SSRS_FATAL_MASK (0x20U) +#define CMC_SSRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK) + +#define CMC_SSRS_PIN_MASK (0x100U) +#define CMC_SSRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK) + +#define CMC_SSRS_DAP_MASK (0x200U) +#define CMC_SSRS_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK) + +#define CMC_SSRS_RSTACK_MASK (0x400U) +#define CMC_SSRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK) + +#define CMC_SSRS_LPACK_MASK (0x800U) +#define CMC_SSRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK) + +#define CMC_SSRS_SCG_MASK (0x1000U) +#define CMC_SSRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK) + +#define CMC_SSRS_WWDT0_MASK (0x2000U) +#define CMC_SSRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK) + +#define CMC_SSRS_SW_MASK (0x4000U) +#define CMC_SSRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK) + +#define CMC_SSRS_LOCKUP_MASK (0x8000U) +#define CMC_SSRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK) + +#define CMC_SSRS_CDOG0_MASK (0x4000000U) +#define CMC_SSRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK) + +#define CMC_SSRS_JTAG_MASK (0x10000000U) +#define CMC_SSRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK) +/*! @} */ + +/*! @name SRIE - System Reset Interrupt Enable */ +/*! @{ */ + +#define CMC_SRIE_PIN_MASK (0x100U) +#define CMC_SRIE_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK) + +#define CMC_SRIE_DAP_MASK (0x200U) +#define CMC_SRIE_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK) + +#define CMC_SRIE_LPACK_MASK (0x800U) +#define CMC_SRIE_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK) + +#define CMC_SRIE_SCG_MASK (0x1000U) +#define CMC_SRIE_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK) + +#define CMC_SRIE_WWDT0_MASK (0x2000U) +#define CMC_SRIE_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK) + +#define CMC_SRIE_SW_MASK (0x4000U) +#define CMC_SRIE_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK) + +#define CMC_SRIE_LOCKUP_MASK (0x8000U) +#define CMC_SRIE_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK) + +#define CMC_SRIE_CDOG0_MASK (0x4000000U) +#define CMC_SRIE_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK) +/*! @} */ + +/*! @name SRIF - System Reset Interrupt Flag */ +/*! @{ */ + +#define CMC_SRIF_PIN_MASK (0x100U) +#define CMC_SRIF_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK) + +#define CMC_SRIF_DAP_MASK (0x200U) +#define CMC_SRIF_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK) + +#define CMC_SRIF_LPACK_MASK (0x800U) +#define CMC_SRIF_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK) + +#define CMC_SRIF_WWDT0_MASK (0x2000U) +#define CMC_SRIF_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK) + +#define CMC_SRIF_SW_MASK (0x4000U) +#define CMC_SRIF_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK) + +#define CMC_SRIF_LOCKUP_MASK (0x8000U) +#define CMC_SRIF_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK) + +#define CMC_SRIF_CDOG0_MASK (0x4000000U) +#define CMC_SRIF_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK) +/*! @} */ + +/*! @name MR - Mode */ +/*! @{ */ + +#define CMC_MR_ISPMODE_n_MASK (0x1U) +#define CMC_MR_ISPMODE_n_SHIFT (0U) +/*! ISPMODE_n - In System Programming Mode */ +#define CMC_MR_ISPMODE_n(x) (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK) +/*! @} */ + +/*! @name FM - Force Mode */ +/*! @{ */ + +#define CMC_FM_FORCECFG_MASK (0x1U) +#define CMC_FM_FORCECFG_SHIFT (0U) +/*! FORCECFG - Boot Configuration + * 0b0..No effect + * 0b1..Asserts + */ +#define CMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK) +/*! @} */ + +/*! @name FLASHCR - Flash Control */ +/*! @{ */ + +#define CMC_FLASHCR_FLASHDIS_MASK (0x1U) +#define CMC_FLASHCR_FLASHDIS_SHIFT (0U) +/*! FLASHDIS - Flash Disable + * 0b0..No effect + * 0b1..Flash memory is disabled + */ +#define CMC_FLASHCR_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK) + +#define CMC_FLASHCR_FLASHDOZE_MASK (0x2U) +#define CMC_FLASHCR_FLASHDOZE_SHIFT (1U) +/*! FLASHDOZE - Flash Doze + * 0b0..No effect + * 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0) + */ +#define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK) + +#define CMC_FLASHCR_FLASHWAKE_MASK (0x4U) +#define CMC_FLASHCR_FLASHWAKE_SHIFT (2U) +/*! FLASHWAKE - Flash Wake + * 0b0..No effect + * 0b1..Flash memory is not disabled during flash memory accesses + */ +#define CMC_FLASHCR_FLASHWAKE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHWAKE_SHIFT)) & CMC_FLASHCR_FLASHWAKE_MASK) +/*! @} */ + +/*! @name CORECTL - Core Control */ +/*! @{ */ + +#define CMC_CORECTL_NPIE_MASK (0x1U) +#define CMC_CORECTL_NPIE_SHIFT (0U) +/*! NPIE - Non-maskable Pin Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_CORECTL_NPIE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK) +/*! @} */ + +/*! @name DBGCTL - Debug Control */ +/*! @{ */ + +#define CMC_DBGCTL_SOD_MASK (0x1U) +#define CMC_DBGCTL_SOD_SHIFT (0U) +/*! SOD - Sleep Or Debug + * 0b0..Remains enabled + * 0b1..Disabled + */ +#define CMC_DBGCTL_SOD(x) (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMC_Register_Masks */ + + +/*! + * @} + */ /* end of group CMC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CMC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CRC.h new file mode 100644 index 000000000..7050db666 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CRC.h @@ -0,0 +1,404 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for CRC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_CRC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for CRC + * + * CMSIS Peripheral Access Layer for CRC + */ + +#if !defined(PERI_CRC_H_) +#define PERI_CRC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ + } ACCESS8BIT; + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< Data, offset: 0x0 */ + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ + } GPOLY_ACCESS8BIT; + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< Polynomial, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ + } CTRL_ACCESS8BIT; + __IO uint32_t CTRL; /**< Control, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATALL - CRC_DATALL register */ +/*! @{ */ + +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) +/*! @} */ + +/*! @name DATALU - CRC_DATALU register */ +/*! @{ */ + +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) +/*! @} */ + +/*! @name DATAHL - CRC_DATAHL register */ +/*! @{ */ + +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) +/*! @} */ + +/*! @name DATAHU - CRC_DATAHU register */ +/*! @{ */ + +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) +/*! @} */ + +/*! @name DATAL - CRC_DATAL register */ +/*! @{ */ + +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) +/*! @} */ + +/*! @name DATAH - CRC_DATAH register */ +/*! @{ */ + +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +/*! LL - Lower Part of Low Byte */ +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) + +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +/*! LU - Upper Part of Low Byte */ +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) + +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +/*! HL - Lower Part of High Byte */ +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) + +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +/*! HU - Upper Part of High Byte */ +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) +/*! @} */ + +/*! @name GPOLYLL - CRC_GPOLYLL register */ +/*! @{ */ + +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) +/*! @} */ + +/*! @name GPOLYLU - CRC_GPOLYLU register */ +/*! @{ */ + +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) +/*! @} */ + +/*! @name GPOLYHL - CRC_GPOLYHL register */ +/*! @{ */ + +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) +/*! @} */ + +/*! @name GPOLYHU - CRC_GPOLYHU register */ +/*! @{ */ + +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) +/*! @} */ + +/*! @name GPOLYL - CRC_GPOLYL register */ +/*! @{ */ + +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) +/*! @} */ + +/*! @name GPOLYH - CRC_GPOLYH register */ +/*! @{ */ + +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) +/*! @} */ + +/*! @name GPOLY - Polynomial */ +/*! @{ */ + +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +/*! LOW - Low Half-Word */ +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) + +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +/*! HIGH - High Half-Word */ +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) +/*! @} */ + +/*! @name CTRLHU - CRC_CTRLHU register */ +/*! @{ */ + +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) + +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) + +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) + +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) + +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) + +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) + +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) + +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) + +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CRC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CTIMER.h new file mode 100644 index 000000000..6a59e86ec --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_CTIMER.h @@ -0,0 +1,681 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for CTIMER +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_CTIMER.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for CTIMER + * + * CMSIS Peripheral Access Layer for CTIMER + */ + +#if !defined(PERI_CTIMER_H_) +#define PERI_CTIMER_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Size of Registers Arrays */ +#define CTIMER_MR_COUNT 4u +#define CTIMER_CR_COUNT 4u +#define CTIMER_MSR_COUNT 4u + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt, offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control, offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control, offset: 0x14 */ + __IO uint32_t MR[CTIMER_MR_COUNT]; /**< Match, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control, offset: 0x28 */ + __I uint32_t CR[CTIMER_CR_COUNT]; /**< Capture, array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match, offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control, offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control, offset: 0x74 */ + __IO uint32_t MSR[CTIMER_MSR_COUNT]; /**< Match Shadow, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt Flag for Match Channel 0 Event */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt Flag for Match Channel 1 Event */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt Flag for Match Channel 2 Event */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt Flag for Match Channel 3 Event */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt Flag for Capture Channel 0 Event */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt Flag for Capture Channel 1 Event */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt Flag for Capture Channel 2 Event */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt Flag for Capture Channel 3 Event */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) + +#define CTIMER_TCR_AGCEN_MASK (0x10U) +#define CTIMER_TCR_AGCEN_SHIFT (4U) +/*! AGCEN - Allow Global Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK) + +#define CTIMER_TCR_ATCEN_MASK (0x20U) +#define CTIMER_TCR_ATCEN_SHIFT (5U) +/*! ATCEN - Allow Trigger Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer Counter Value */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale Reload Value */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale Counter Value */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer Counter Match Value */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/*! @name CCR - Capture Control */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate Interrupt on Channel 0 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate Interrupt on Channel 1 Capture Event + * 0b0..Does not generates + * 0b1..Generates + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate Interrupt on Channel 2 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate Interrupt on Channel 3 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer Counter Capture Value */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/*! @name EMR - External Match */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter Timer Mode + * 0b00..Timer mode + * 0b01..Counter mode rising edge + * 0b10..Counter mode falling edge + * 0b11..Counter mode dual edge + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select + * 0b00..Channel 0, CAPn[0] for CTIMERn + * 0b01..Channel 1, CAPn[1] for CTIMERn + * 0b10..Channel 2, CAPn[2] for CTIMERn + * 0b11..Channel 3, CAPn[3] for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Capture Channel Enable */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge Select + * 0b000..Capture channel 0 rising edge + * 0b001..Capture channel 0 falling edge + * 0b010..Capture channel 1 rising edge + * 0b011..Capture channel 1 falling edge + * 0b100..Capture channel 2 rising edge + * 0b101..Capture channel 2 falling edge + * 0b110..Capture channel 3 rising edge + * 0b111..Capture channel 3 falling edge + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM Mode Enable for Channel 0 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM Mode Enable for Channel 1 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM Mode Enable for Channel 2 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM Mode Enable for Channel 3 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow */ +/*! @{ */ + +#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) +/*! MATCH_SHADOW - Timer Counter Match Shadow Value */ +#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CTIMER_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DEBUGMAILBOX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DEBUGMAILBOX.h new file mode 100644 index 000000000..d1171b770 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DEBUGMAILBOX.h @@ -0,0 +1,225 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for DEBUGMAILBOX +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_DEBUGMAILBOX.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for DEBUGMAILBOX + * + * CMSIS Peripheral Access Layer for DEBUGMAILBOX + */ + +#if !defined(PERI_DEBUGMAILBOX_H_) +#define PERI_DEBUGMAILBOX_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- DEBUGMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEBUGMAILBOX_Peripheral_Access_Layer DEBUGMAILBOX Peripheral Access Layer + * @{ + */ + +/** DEBUGMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< Command and Status Word, offset: 0x0 */ + __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification, offset: 0xFC */ +} DEBUGMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DEBUGMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEBUGMAILBOX_Register_Masks DEBUGMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - Command and Status Word */ +/*! @{ */ + +#define DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Resynchronization Request + * 0b0..No request + * 0b1..Request for resynchronization + */ +#define DEBUGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DEBUGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request Pending + * 0b0..No request pending + * 0b1..Request for resynchronization pending + */ +#define DEBUGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGMAILBOX_CSW_REQ_PENDING_MASK) + +#define DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - DBGMB Overrun Error + * 0b0..No overrun + * 0b1..Overrun occurred + */ +#define DEBUGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB Overrun Error + * 0b0..No overrun + * 0b1..Overrun occurred + */ +#define DEBUGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DEBUGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset + * 0b0..No effect + * 0b1..Reset + */ +#define DEBUGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGMAILBOX_CSW_SOFT_RESET_MASK) + +#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Chip Reset Request + * 0b0..No effect + * 0b1..Reset + */ +#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - Request Value */ +/*! @{ */ + +#define DEBUGMAILBOX_REQUEST_REQUEST_MASK (0xFFFFFFFFU) +#define DEBUGMAILBOX_REQUEST_REQUEST_SHIFT (0U) +/*! REQUEST - Request Value */ +#define DEBUGMAILBOX_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGMAILBOX_REQUEST_REQUEST_MASK) +/*! @} */ + +/*! @name RETURN - Return Value */ +/*! @{ */ + +#define DEBUGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DEBUGMAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - Return Value */ +#define DEBUGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_RETURN_RET_SHIFT)) & DEBUGMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define DEBUGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DEBUGMAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification Value */ +#define DEBUGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_ID_ID_SHIFT)) & DEBUGMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DEBUGMAILBOX_Register_Masks */ + + +/*! + * @} + */ /* end of group DEBUGMAILBOX_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_DEBUGMAILBOX_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DMA.h new file mode 100644 index 000000000..86a643cbd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_DMA.h @@ -0,0 +1,1035 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for DMA +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_DMA.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for DMA + * + * CMSIS Peripheral Access Layer for DMA + */ + +#if !defined(PERI_DMA_H_) +#define PERI_DMA_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +#if !defined(DMA_REQUEST_SOURCE_T_) +#define DMA_REQUEST_SOURCE_T_ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestDisabled = 0U, /**< Disabled */ + kDma0RequestWUU0 = 1U, /**< WUU Wake up event */ + kDma0RequestMuxFlexCan0DmaRequest = 2U, /**< CAN0 DMA request */ + kDma0RequestLPI2C0Rx = 11U, /**< LPI2C0 Receive request */ + kDma0RequestLPI2C0Tx = 12U, /**< LPI2C0 Transmit request */ + kDma0RequestLPI2C1Rx = 13U, /**< LPI2C1 Receive request */ + kDma0RequestLPI2C1Tx = 14U, /**< LPI2C1 Transmit request */ + kDma0RequestLPSPI0Rx = 15U, /**< LPSPI0 Receive request */ + kDma0RequestLPSPI0Tx = 16U, /**< LPSPI0 Transmit request */ + kDma0RequestLPSPI1Rx = 17U, /**< LPSPI1 Receive request */ + kDma0RequestLPSPI1Tx = 18U, /**< LPSPI1 Transmit request */ + kDma0RequestLPUART0Rx = 21U, /**< LPUART0 Receive request */ + kDma0RequestLPUART0Tx = 22U, /**< LPUART0 Transmit request */ + kDma0RequestLPUART1Rx = 23U, /**< LPUART1 Receive request */ + kDma0RequestLPUART1Tx = 24U, /**< LPUART1 Transmit request */ + kDma0RequestLPUART2Rx = 25U, /**< LPUART2 Receive request */ + kDma0RequestLPUART2Tx = 26U, /**< LPUART2 Transmit request */ + kDma0RequestLPUART3Rx = 27U, /**< LPUART3 Receive request */ + kDma0RequestLPUART3Tx = 28U, /**< LPUART3 Transmit request */ + kDma0RequestMuxCtimer0M0 = 31U, /**< CTIMER0 Match channel 0 request */ + kDma0RequestMuxCtimer0M1 = 32U, /**< CTIMER0 Match channel 1 request */ + kDma0RequestMuxCtimer1M0 = 33U, /**< CTIMER1 Match channel 0 request */ + kDma0RequestMuxCtimer1M1 = 34U, /**< CTIMER1 Match channel 1 request */ + kDma0RequestMuxCtimer2M0 = 35U, /**< CTIMER2 Match channel 0 request */ + kDma0RequestMuxCtimer2M1 = 36U, /**< CTIMER2 Match channel 1 request */ + kDma0RequestMuxFlexPWM0ReqCapt0 = 41U, /**< FlexPWM0 capture0 request */ + kDma0RequestMuxFlexPWM0ReqCapt1 = 42U, /**< FlexPWM0 capture1 request */ + kDma0RequestMuxFlexPWM0ReqCapt2 = 43U, /**< FlexPWM0 capture2 request */ + kDma0RequestMuxFlexPWM0ReqCapt3 = 44U, /**< FlexPWM0 capture3 request */ + kDma0RequestMuxFlexPWM0ReqVal0 = 45U, /**< FlexPWM0 value0 request */ + kDma0RequestMuxFlexPWM0ReqVal1 = 46U, /**< FlexPWM0 value1 request */ + kDma0RequestMuxFlexPWM0ReqVal2 = 47U, /**< FlexPWM0 value2 request */ + kDma0RequestMuxFlexPWM0ReqVal3 = 48U, /**< FlexPWM0 value3 request */ + kDma0RequestMuxLptmr0 = 49U, /**< LPTMR0 Counter match event */ + kDma0RequestMuxAdc0FifoRequest = 51U, /**< ADC0 FIFO request */ + kDma0RequestMuxAdc1FifoRequest = 52U, /**< ADC1 FIFO request */ + kDma0RequestMuxHsCmp0DmaRequest = 53U, /**< CMP0 DMA_request */ + kDma0RequestMuxHsCmp1DmaRequest = 54U, /**< CMP1 DMA_request */ + kDma0RequestMuxGpio0PinEventRequest0 = 60U, /**< GPIO0 Pin event request 0 */ + kDma0RequestMuxGpio1PinEventRequest0 = 61U, /**< GPIO1 Pin event request 0 */ + kDma0RequestMuxGpio2PinEventRequest0 = 62U, /**< GPIO2 Pin event request 0 */ + kDma0RequestMuxGpio3PinEventRequest0 = 63U, /**< GPIO3 Pin event request 0 */ + kDma0RequestMuxGpio4PinEventRequest0 = 64U, /**< GPIO4 Pin event request 0 */ + kDma0RequestMuxEqdc0 = 65U, /**< EQDC0 DMA request for new buffered value */ + kDma0RequestMuxEqdc1 = 66U, /**< EQDC1 DMA request for new buffered value */ + kDma0RequestMuxFlexPWM1ReqCapt0 = 79U, /**< FlexPWM1 capture0 request */ + kDma0RequestMuxFlexPWM1ReqCapt1 = 80U, /**< FlexPWM1 capture1 request */ + kDma0RequestMuxFlexPWM1ReqCapt2 = 81U, /**< FlexPWM1 capture2 request */ + kDma0RequestMuxFlexPWM1ReqCapt3 = 82U, /**< FlexPWM1 capture3 request */ + kDma0RequestMuxFlexPWM1ReqVal0 = 83U, /**< FlexPWM1 value0 request */ + kDma0RequestMuxFlexPWM1ReqVal1 = 84U, /**< FlexPWM1 value1 request */ + kDma0RequestMuxFlexPWM1ReqVal2 = 85U, /**< FlexPWM1 value2 request */ + kDma0RequestMuxFlexPWM1ReqVal3 = 86U, /**< FlexPWM1 value2 request */ + kDma0RequestMuxHsCmp2DmaRequest = 55U, /**< CMP2 DMA_request */ +} dma_request_source_t; + +/* @} */ +#endif /* DMA_REQUEST_SOURCE_T_ */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Size of Registers Arrays */ +#define DMA_MP_GRPRI_COUNT 8u +#define DMA_CH_COUNT 8u + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ + __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ + __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ + __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ + uint8_t RESERVED_0[240]; + __IO uint32_t CH_GRPRI[DMA_MP_GRPRI_COUNT]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[3808]; + struct { /* offset: 0x1000, array step: 0x1000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */ + uint8_t RESERVED_0[8]; + __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */ + __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */ + __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */ + union { /* offset: 0x1028, array step: 0x1000 */ + __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */ + __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */ + }; + __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */ + __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */ + __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */ + union { /* offset: 0x1036, array step: 0x1000 */ + __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */ + __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */ + }; + __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */ + __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */ + union { /* offset: 0x103E, array step: 0x1000 */ + __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */ + __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */ + }; + uint8_t RESERVED_1[4032]; + } CH[DMA_CH_COUNT]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name MP_CSR - Management Page Control */ +/*! @{ */ + +#define DMA_MP_CSR_EDBG_MASK (0x2U) +#define DMA_MP_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode disabled + * 0b1..Debug mode is enabled. + */ +#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) + +#define DMA_MP_CSR_ERCA_MASK (0x4U) +#define DMA_MP_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round-robin channel arbitration disabled + * 0b1..Round-robin channel arbitration enabled + */ +#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) + +#define DMA_MP_CSR_HAE_MASK (0x10U) +#define DMA_MP_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT field to be set to 1 + */ +#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) + +#define DMA_MP_CSR_HALT_MASK (0x20U) +#define DMA_MP_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels + */ +#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) + +#define DMA_MP_CSR_GCLC_MASK (0x40U) +#define DMA_MP_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking disabled for all channels + * 0b1..Channel linking available and controlled by each channel's link settings + */ +#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) + +#define DMA_MP_CSR_GMRC_MASK (0x80U) +#define DMA_MP_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Initiator ID Replication Control + * 0b0..Initiator ID replication disabled for all channels + * 0b1..Initiator ID replication available and controlled by each channel's CHn_SBR[EMI] setting + */ +#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) + +#define DMA_MP_CSR_ECX_MASK (0x100U) +#define DMA_MP_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer With Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) + +#define DMA_MP_CSR_CX_MASK (0x200U) +#define DMA_MP_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) + +#define DMA_MP_CSR_ACTIVE_ID_MASK (0x7000000U) +#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active Channel ID */ +#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) + +#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_MP_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle + * 0b1..eDMA is executing a channel + */ +#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name MP_ES - Management Page Error Status */ +/*! @{ */ + +#define DMA_MP_ES_DBE_MASK (0x1U) +#define DMA_MP_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was a bus error on a destination write + */ +#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) + +#define DMA_MP_ES_SBE_MASK (0x2U) +#define DMA_MP_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was a bus error on a source read + */ +#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) + +#define DMA_MP_ES_SGE_MASK (0x4U) +#define DMA_MP_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) + +#define DMA_MP_ES_NCE_MASK (0x8U) +#define DMA_MP_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) + +#define DMA_MP_ES_DOE_MASK (0x10U) +#define DMA_MP_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) + +#define DMA_MP_ES_DAE_MASK (0x20U) +#define DMA_MP_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) + +#define DMA_MP_ES_SOE_MASK (0x40U) +#define DMA_MP_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) + +#define DMA_MP_ES_SAE_MASK (0x80U) +#define DMA_MP_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) + +#define DMA_MP_ES_ECX_MASK (0x100U) +#define DMA_MP_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) + +#define DMA_MP_ES_ERRCHN_MASK (0x7000000U) +#define DMA_MP_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) + +#define DMA_MP_ES_VLD_MASK (0x80000000U) +#define DMA_MP_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No CHn_ES[ERR] fields are set to 1 + * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared + */ +#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) +/*! @} */ + +/*! @name MP_INT - Management Page Interrupt Request Status */ +/*! @{ */ + +#define DMA_MP_INT_INT_MASK (0xFFU) +#define DMA_MP_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request Status */ +#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) +/*! @} */ + +/*! @name MP_HRS - Management Page Hardware Request Status */ +/*! @{ */ + +#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) +#define DMA_MP_HRS_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status */ +#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group */ +/*! @{ */ + +#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) +#define DMA_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration Group For Channel n */ +#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA_CH_GRPRI */ +#define DMA_CH_GRPRI_COUNT (8U) + +/*! @name CH_CSR - Channel Control and Status */ +/*! @{ */ + +#define DMA_CH_CSR_ERQ_MASK (0x1U) +#define DMA_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..DMA hardware request signal for corresponding channel disabled + * 0b1..DMA hardware request signal for corresponding channel enabled + */ +#define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) + +#define DMA_CH_CSR_EARQ_MASK (0x2U) +#define DMA_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel + * 0b1..Enable asynchronous DMA request for the channel + */ +#define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) + +#define DMA_CH_CSR_EEI_MASK (0x4U) +#define DMA_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..Error signal for corresponding channel does not generate error interrupt + * 0b1..Assertion of error signal for corresponding channel generates error interrupt request + */ +#define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) + +#define DMA_CH_CSR_EBW_MASK (0x8U) +#define DMA_CH_CSR_EBW_SHIFT (3U) +/*! EBW - Enable Buffered Writes + * 0b0..Buffered writes on system bus disabled + * 0b1..Buffered writes on system bus enabled + */ +#define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK) + +#define DMA_CH_CSR_DONE_MASK (0x40000000U) +#define DMA_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) + +#define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of DMA_CH_CSR */ +#define DMA_CH_CSR_COUNT (8U) + +/*! @name CH_ES - Channel Error Status */ +/*! @{ */ + +#define DMA_CH_ES_DBE_MASK (0x1U) +#define DMA_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was bus error on destination write + */ +#define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) + +#define DMA_CH_ES_SBE_MASK (0x2U) +#define DMA_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was bus error on source read + */ +#define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) + +#define DMA_CH_ES_SGE_MASK (0x4U) +#define DMA_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) + +#define DMA_CH_ES_NCE_MASK (0x8U) +#define DMA_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields + */ +#define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) + +#define DMA_CH_ES_DOE_MASK (0x10U) +#define DMA_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) + +#define DMA_CH_ES_DAE_MASK (0x20U) +#define DMA_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) + +#define DMA_CH_ES_SOE_MASK (0x40U) +#define DMA_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) + +#define DMA_CH_ES_SAE_MASK (0x80U) +#define DMA_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) + +#define DMA_CH_ES_ERR_MASK (0x80000000U) +#define DMA_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of DMA_CH_ES */ +#define DMA_CH_ES_COUNT (8U) + +/*! @name CH_INT - Channel Interrupt Status */ +/*! @{ */ + +#define DMA_CH_INT_INT_MASK (0x1U) +#define DMA_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..Interrupt request for corresponding channel cleared + * 0b1..Interrupt request for corresponding channel active + */ +#define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) +/*! @} */ + +/* The count of DMA_CH_INT */ +#define DMA_CH_INT_COUNT (8U) + +/*! @name CH_SBR - Channel System Bus */ +/*! @{ */ + +#define DMA_CH_SBR_MID_MASK (0xFU) +#define DMA_CH_SBR_MID_SHIFT (0U) +/*! MID - Initiator ID */ +#define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) + +#define DMA_CH_SBR_PAL_MASK (0x8000U) +#define DMA_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) + +#define DMA_CH_SBR_EMI_MASK (0x10000U) +#define DMA_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Initiator ID Replication + * 0b0..Initiator ID replication is disabled + * 0b1..Initiator ID replication is enabled + */ +#define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) +/*! @} */ + +/* The count of DMA_CH_SBR */ +#define DMA_CH_SBR_COUNT (8U) + +/*! @name CH_PRI - Channel Priority */ +/*! @{ */ + +#define DMA_CH_PRI_APL_MASK (0x7U) +#define DMA_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) + +#define DMA_CH_PRI_DPA_MASK (0x40000000U) +#define DMA_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel can suspend a lower-priority channel + * 0b1..Channel cannot suspend any other channel, regardless of channel priority + */ +#define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) + +#define DMA_CH_PRI_ECP_MASK (0x80000000U) +#define DMA_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel cannot be suspended by a higher-priority channel's service request + * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request + */ +#define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of DMA_CH_PRI */ +#define DMA_CH_PRI_COUNT (8U) + +/*! @name CH_MUX - Channel Multiplexor Configuration */ +/*! @{ */ + +#define DMA_CH_MUX_SRC_MASK (0x7FU) +#define DMA_CH_MUX_SRC_SHIFT (0U) +/*! SRC - Service Request Source */ +#define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK) +/*! @} */ + +/* The count of DMA_CH_MUX */ +#define DMA_CH_MUX_COUNT (8U) + +/*! @name TCD_SADDR - TCD Source Address */ +/*! @{ */ + +#define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_SADDR */ +#define DMA_TCD_SADDR_COUNT (8U) + +/*! @name TCD_SOFF - TCD Signed Source Address Offset */ +/*! @{ */ + +#define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source Address Signed Offset */ +#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_SOFF */ +#define DMA_TCD_SOFF_COUNT (8U) + +/*! @name TCD_ATTR - TCD Transfer Attributes */ +/*! @{ */ + +#define DMA_TCD_ATTR_DSIZE_MASK (0x7U) +#define DMA_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination Data Transfer Size */ +#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) + +#define DMA_TCD_ATTR_DMOD_MASK (0xF8U) +#define DMA_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo */ +#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) + +#define DMA_TCD_ATTR_SSIZE_MASK (0x700U) +#define DMA_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source Data Transfer Size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110.. + * 0b111.. + */ +#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) + +#define DMA_TCD_ATTR_SMOD_MASK (0xF800U) +#define DMA_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature disabled + */ +#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_TCD_ATTR */ +#define DMA_TCD_ATTR_COUNT (8U) + +/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFNO */ +#define DMA_TCD_NBYTES_MLOFFNO_COUNT (8U) + +/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFYES */ +#define DMA_TCD_NBYTES_MLOFFYES_COUNT (8U) + +/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ +/*! @{ */ + +#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of DMA_TCD_SLAST_SDA */ +#define DMA_TCD_SLAST_SDA_COUNT (8U) + +/*! @name TCD_DADDR - TCD Destination Address */ +/*! @{ */ + +#define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_DADDR */ +#define DMA_TCD_DADDR_COUNT (8U) + +/*! @name TCD_DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ + +#define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_DOFF */ +#define DMA_TCD_DOFF_COUNT (8U) + +/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) + +#define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKNO */ +#define DMA_TCD_CITER_ELINKNO_COUNT (8U) + +/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) + +#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0xE00U) +#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) + +#define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKYES */ +#define DMA_TCD_CITER_ELINKYES_COUNT (8U) + +/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ +/*! @{ */ + +#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ +#define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of DMA_TCD_DLAST_SGA */ +#define DMA_TCD_DLAST_SGA_COUNT (8U) + +/*! @name TCD_CSR - TCD Control and Status */ +/*! @{ */ + +#define DMA_TCD_CSR_START_MASK (0x1U) +#define DMA_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..Channel not explicitly started + * 0b1..Channel explicitly started via a software-initiated service request + */ +#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) + +#define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) +#define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable Interrupt If Major count complete + * 0b0..End-of-major loop interrupt disabled + * 0b1..End-of-major loop interrupt enabled + */ +#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) + +#define DMA_TCD_CSR_INTHALF_MASK (0x4U) +#define DMA_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable Interrupt If Major Counter Half-complete + * 0b0..Halfway point interrupt disabled + * 0b1..Halfway point interrupt enabled + */ +#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) + +#define DMA_TCD_CSR_DREQ_MASK (0x8U) +#define DMA_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..No operation + * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests + */ +#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) + +#define DMA_TCD_CSR_ESG_MASK (0x10U) +#define DMA_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..Current channel's TCD is normal format + * 0b1..Current channel's TCD specifies scatter/gather format. + */ +#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) + +#define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) +#define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable Link When Major Loop Complete + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) + +#define DMA_TCD_CSR_EEOP_MASK (0x40U) +#define DMA_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable End-Of-Packet Processing + * 0b0..End-of-packet operation disabled + * 0b1..End-of-packet hardware input signal enabled + */ +#define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) + +#define DMA_TCD_CSR_ESDA_MASK (0x80U) +#define DMA_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable Store Destination Address + * 0b0..Ability to store destination address to system memory disabled + * 0b1..Ability to store destination address to system memory enabled + */ +#define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) + +#define DMA_TCD_CSR_MAJORLINKCH_MASK (0x700U) +#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number */ +#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) + +#define DMA_TCD_CSR_BWC_MASK (0xC000U) +#define DMA_TCD_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01.. + * 0b10..eDMA engine stalls for 4 cycles after each R/W + * 0b11..eDMA engine stalls for 8 cycles after each R/W + */ +#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_TCD_CSR */ +#define DMA_TCD_CSR_COUNT (8U) + +/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) + +#define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKNO */ +#define DMA_TCD_BITER_ELINKNO_COUNT (8U) + +/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) + +#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0xE00U) +#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) + +#define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKYES */ +#define DMA_TCD_BITER_ELINKYES_COUNT (8U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_DMA_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EIM.h new file mode 100644 index 000000000..b7e86397a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EIM.h @@ -0,0 +1,254 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for EIM +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_EIM.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for EIM + * + * CMSIS Peripheral Access Layer for EIM + */ + +#if !defined(PERI_EIM_H_) +#define PERI_EIM_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +#if !defined(EIM_MEMORY_CHANNEL_T_) +#define EIM_MEMORY_CHANNEL_T_ +/*! + * @addtogroup eim_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_memory_channel + * + * Defines the structure for the EIM resource collections. + */ + +typedef enum _eim_memory_channel +{ + kEIM_MemoryChannelRAMA0 = 0U, /**< Memory RAMA0 */ +} eim_memory_channel_t; + +/* @} */ +#endif /* EIM_MEMORY_CHANNEL_T_ */ + +#if !defined(EIM_ERROR_INJECTION_CHANNEL_ENABLE_T_) +#define EIM_ERROR_INJECTION_CHANNEL_ENABLE_T_ +/*! + * @addtogroup eim_error_injection_channel_enable + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_error_injection_channel_enable + * + * Defines the structure for the EIM error injection resource collections. + */ + +typedef enum _eim_error_injection_channel_enable +{ + kEIM_MemoryChannelRAMAEnable = 0x80000000U, /**< Memory channel 0(RAMA0) error injection enable */ +} eim_error_injection_channel_enable_t; + +/* @} */ +#endif /* EIM_ERROR_INJECTION_CHANNEL_ENABLE_T_ */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ + __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ + uint8_t RESERVED_0[248]; + __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ + __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name EIMCR - Error Injection Module Configuration Register */ +/*! @{ */ + +#define EIM_EIMCR_GEIEN_MASK (0x1U) +#define EIM_EIMCR_GEIEN_SHIFT (0U) +/*! GEIEN - Global Error Injection Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) +/*! @} */ + +/*! @name EICHEN - Error Injection Channel Enable register */ +/*! @{ */ + +#define EIM_EICHEN_EICH0EN_MASK (0x80000000U) +#define EIM_EICHEN_EICH0EN_SHIFT (31U) +/*! EICH0EN - Error Injection Channel 0 Enable + * 0b0..Error injection is disabled on Error Injection Channel 0 + * 0b1..Error injection is enabled on Error Injection Channel 0 + */ +#define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) +/*! @} */ + +/*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ +/*! @{ */ + +#define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ +/*! @{ */ + +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Field */ +#define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_EIM_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EQDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EQDC.h new file mode 100644 index 000000000..f3fee6ae0 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_EQDC.h @@ -0,0 +1,1013 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for EQDC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_EQDC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for EQDC + * + * CMSIS Peripheral Access Layer for EQDC + */ + +#if !defined(PERI_EQDC_H_) +#define PERI_EQDC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- EQDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EQDC_Peripheral_Access_Layer EQDC Peripheral Access Layer + * @{ + */ + +/** EQDC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x2 */ + __IO uint16_t FILT; /**< Input Filter Register, offset: 0x4 */ + __I uint16_t LASTEDGE; /**< Last Edge Time Register, offset: 0x6 */ + __I uint16_t POSDPER; /**< Position Difference Period Counter Register, offset: 0x8 */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer Register, offset: 0xA */ + __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xC */ + __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0xE */ + __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x10 */ + __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x12 */ + __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x14 */ + __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x16 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold Register, offset: 0x18 */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold Register, offset: 0x1A */ + __I uint16_t REVH; /**< Revolution Hold Register, offset: 0x1C */ + __IO uint16_t REV; /**< Revolution Counter Register, offset: 0x1E */ + __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x20 */ + __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x22 */ + __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x24 */ + __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x26 */ + __IO uint16_t UCOMP0; /**< Upper Position Compare Register 0, offset: 0x28 */ + __IO uint16_t LCOMP0; /**< Lower Position Compare Register 0, offset: 0x2A */ + union { /* offset: 0x2C */ + __O uint16_t UCOMP1; /**< Upper Position Compare 1, offset: 0x2C */ + __I uint16_t UPOSH1; /**< Upper Position Holder Register 1, offset: 0x2C */ + }; + union { /* offset: 0x2E */ + __O uint16_t LCOMP1; /**< Lower Position Compare 1, offset: 0x2E */ + __I uint16_t LPOSH1; /**< Lower Position Holder Register 1, offset: 0x2E */ + }; + union { /* offset: 0x30 */ + __O uint16_t UCOMP2; /**< Upper Position Compare 2, offset: 0x30 */ + __I uint16_t UPOSH2; /**< Upper Position Holder Register 3, offset: 0x30 */ + }; + union { /* offset: 0x32 */ + __O uint16_t LCOMP2; /**< Lower Position Compare 2, offset: 0x32 */ + __I uint16_t LPOSH2; /**< Lower Position Holder Register 2, offset: 0x32 */ + }; + union { /* offset: 0x34 */ + __O uint16_t UCOMP3; /**< Upper Position Compare 3, offset: 0x34 */ + __I uint16_t UPOSH3; /**< Upper Position Holder Register 3, offset: 0x34 */ + }; + union { /* offset: 0x36 */ + __O uint16_t LCOMP3; /**< Lower Position Compare 3, offset: 0x36 */ + __I uint16_t LPOSH3; /**< Lower Position Holder Register 3, offset: 0x36 */ + }; + __IO uint16_t INTCTRL; /**< Interrupt Control Register, offset: 0x38 */ + __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x3A */ + __IO uint16_t IMR; /**< Input Monitor Register, offset: 0x3C */ + __IO uint16_t TST; /**< Test Register, offset: 0x3E */ + uint8_t RESERVED_0[16]; + __I uint16_t UVERID; /**< Upper VERID, offset: 0x50 */ + __I uint16_t LVERID; /**< Lower VERID, offset: 0x52 */ +} EQDC_Type; + +/* ---------------------------------------------------------------------------- + -- EQDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EQDC_Register_Masks EQDC Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define EQDC_CTRL_LDOK_MASK (0x1U) +#define EQDC_CTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0..No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers) + * 0b1..Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2[LDMOD]. + */ +#define EQDC_CTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_LDOK_SHIFT)) & EQDC_CTRL_LDOK_MASK) + +#define EQDC_CTRL_DMAEN_MASK (0x2U) +#define EQDC_CTRL_DMAEN_SHIFT (1U) +/*! DMAEN - DMA Enable + * 0b0..DMA is disabled + * 0b1..DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare + * registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and + * modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. + * After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be + * loaded into inner-set which in turn triggers DMA again. + */ +#define EQDC_CTRL_DMAEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_DMAEN_SHIFT)) & EQDC_CTRL_DMAEN_MASK) + +#define EQDC_CTRL_WDE_MASK (0x4U) +#define EQDC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDE_SHIFT)) & EQDC_CTRL_WDE_MASK) + +#define EQDC_CTRL_WDIE_MASK (0x8U) +#define EQDC_CTRL_WDIE_SHIFT (3U) +/*! WDIE - Watchdog Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_WDIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIE_SHIFT)) & EQDC_CTRL_WDIE_MASK) + +#define EQDC_CTRL_WDIRQ_MASK (0x10U) +#define EQDC_CTRL_WDIRQ_SHIFT (4U) +/*! WDIRQ - Watchdog Timeout Interrupt Request + * 0b0..No Watchdog timeout interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ +#define EQDC_CTRL_WDIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIRQ_SHIFT)) & EQDC_CTRL_WDIRQ_MASK) + +#define EQDC_CTRL_XNE_MASK (0x20U) +#define EQDC_CTRL_XNE_SHIFT (5U) +/*! XNE - Select Positive/Negative Edge of INDEX/PRESET Pulse + * 0b0..Use positive edge of INDEX/PRESET pulse + * 0b1..Use negative edge of INDEX/PRESET pulse + */ +#define EQDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XNE_SHIFT)) & EQDC_CTRL_XNE_MASK) + +#define EQDC_CTRL_XIP_MASK (0x40U) +#define EQDC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..INDEX pulse does not initialize the position counter + * 0b1..INDEX pulse initializes the position counter + */ +#define EQDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIP_SHIFT)) & EQDC_CTRL_XIP_MASK) + +#define EQDC_CTRL_XIE_MASK (0x80U) +#define EQDC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX/PRESET Pulse Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIE_SHIFT)) & EQDC_CTRL_XIE_MASK) + +#define EQDC_CTRL_XIRQ_MASK (0x100U) +#define EQDC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX/PRESET Pulse Interrupt Request + * 0b0..INDEX/PRESET pulse has not occurred + * 0b1..INDEX/PRESET pulse has occurred + */ +#define EQDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIRQ_SHIFT)) & EQDC_CTRL_XIRQ_MASK) + +#define EQDC_CTRL_PH1_MASK (0x200U) +#define EQDC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Single Phase Mode + * 0b0..Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + * 0b1..Single phase mode, bypass the quadrature decoder, refer to CTRL2[CMODE] description + */ +#define EQDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_PH1_SHIFT)) & EQDC_CTRL_PH1_MASK) + +#define EQDC_CTRL_REV_MASK (0x400U) +#define EQDC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT + * 0b1..Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD + */ +#define EQDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_REV_SHIFT)) & EQDC_CTRL_REV_MASK) + +#define EQDC_CTRL_SWIP_MASK (0x800U) +#define EQDC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define EQDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_SWIP_SHIFT)) & EQDC_CTRL_SWIP_MASK) + +#define EQDC_CTRL_HNE_MASK (0x1000U) +#define EQDC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME/ENABLE Input + * 0b0..When CTRL[OPMODE] = 0,use HOME positive edge to trigger initialization of position counters. When + * CTRL[OPMODE] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters + * 0b1..When CTRL[OPMODE] = 0,use HOME negative edge to trigger initialization of position counters. When + * CTRL[OPMODE] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters + */ +#define EQDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HNE_SHIFT)) & EQDC_CTRL_HNE_MASK) + +#define EQDC_CTRL_HIP_MASK (0x2000U) +#define EQDC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counter UPOS/LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define EQDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIP_SHIFT)) & EQDC_CTRL_HIP_MASK) + +#define EQDC_CTRL_HIE_MASK (0x4000U) +#define EQDC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME/ENABLE Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIE_SHIFT)) & EQDC_CTRL_HIE_MASK) + +#define EQDC_CTRL_HIRQ_MASK (0x8000U) +#define EQDC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME/ENABLE Signal Transition Interrupt Request + * 0b0..No transition on the HOME/ENABLE signal has occurred + * 0b1..A transition on the HOME/ENABLE signal has occurred + */ +#define EQDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIRQ_SHIFT)) & EQDC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define EQDC_CTRL2_UPDHLD_MASK (0x1U) +#define EQDC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers */ +#define EQDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDHLD_SHIFT)) & EQDC_CTRL2_UPDHLD_MASK) + +#define EQDC_CTRL2_UPDPOS_MASK (0x2U) +#define EQDC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers */ +#define EQDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDPOS_SHIFT)) & EQDC_CTRL2_UPDPOS_MASK) + +#define EQDC_CTRL2_OPMODE_MASK (0x4U) +#define EQDC_CTRL2_OPMODE_SHIFT (2U) +/*! OPMODE - Operation Mode Select + * 0b0..Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME. + * 0b1..Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In + * this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, + * when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising + * edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization + * also need referring to bit CTRL[REV]). + */ +#define EQDC_CTRL2_OPMODE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OPMODE_SHIFT)) & EQDC_CTRL2_OPMODE_MASK) + +#define EQDC_CTRL2_LDMOD_MASK (0x8U) +#define EQDC_CTRL2_LDMOD_SHIFT (3U) +/*! LDMOD - Buffered Register Load (Update) Mode Select + * 0b0..Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set. + * 0b1..Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set. + */ +#define EQDC_CTRL2_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_LDMOD_SHIFT)) & EQDC_CTRL2_LDMOD_MASK) + +#define EQDC_CTRL2_REVMOD_MASK (0x100U) +#define EQDC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV) + */ +#define EQDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_REVMOD_SHIFT)) & EQDC_CTRL2_REVMOD_MASK) + +#define EQDC_CTRL2_OUTCTL_MASK (0x200U) +#define EQDC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POS_MATCH[x](x range is 0-3) is asserted when the Position Counter is equal to according compare value + * (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value + * (UCOMPx/LCOMPx)(x range is 0-3) + * 0b1..All POS_MATCH[x](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read + */ +#define EQDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OUTCTL_SHIFT)) & EQDC_CTRL2_OUTCTL_MASK) + +#define EQDC_CTRL2_PMEN_MASK (0x400U) +#define EQDC_CTRL2_PMEN_SHIFT (10U) +/*! PMEN - Period measurement function enable + * 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read. + * 0b1..Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read. + */ +#define EQDC_CTRL2_PMEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_PMEN_SHIFT)) & EQDC_CTRL2_PMEN_MASK) + +#define EQDC_CTRL2_EMIP_MASK (0x800U) +#define EQDC_CTRL2_EMIP_SHIFT (11U) +/*! EMIP - Enables/disables the position counter to be initialized by Index Event Edge Mark + * 0b0..disables the position counter to be initialized by Index Event Edge Mark + * 0b1..enables the position counter to be initialized by Index Event Edge Mark. + */ +#define EQDC_CTRL2_EMIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_EMIP_SHIFT)) & EQDC_CTRL2_EMIP_MASK) + +#define EQDC_CTRL2_INITPOS_MASK (0x1000U) +#define EQDC_CTRL2_INITPOS_SHIFT (12U) +/*! INITPOS - Initial Position Register + * 0b0..Don't initialize position counter on rising edge of TRIGGER + * 0b1..Initialize position counter on rising edge of TRIGGER + */ +#define EQDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_INITPOS_SHIFT)) & EQDC_CTRL2_INITPOS_MASK) + +#define EQDC_CTRL2_ONCE_MASK (0x2000U) +#define EQDC_CTRL2_ONCE_SHIFT (13U) +/*! ONCE - Count Once + * 0b0..Position counter counts repeatedly + * 0b1..Position counter counts until roll-over or roll-under, then stop. + */ +#define EQDC_CTRL2_ONCE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_ONCE_SHIFT)) & EQDC_CTRL2_ONCE_MASK) + +#define EQDC_CTRL2_CMODE_MASK (0xC000U) +#define EQDC_CTRL2_CMODE_SHIFT (14U) +/*! CMODE - Counting Mode */ +#define EQDC_CTRL2_CMODE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_CMODE_SHIFT)) & EQDC_CTRL2_CMODE_MASK) +/*! @} */ + +/*! @name FILT - Input Filter Register */ +/*! @{ */ + +#define EQDC_FILT_FILT_PER_MASK (0xFFU) +#define EQDC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define EQDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_PER_SHIFT)) & EQDC_FILT_FILT_PER_MASK) + +#define EQDC_FILT_FILT_CNT_MASK (0x700U) +#define EQDC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define EQDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CNT_SHIFT)) & EQDC_FILT_FILT_CNT_MASK) + +#define EQDC_FILT_FILT_CS_MASK (0x800U) +#define EQDC_FILT_FILT_CS_SHIFT (11U) +/*! FILT_CS - Filter Clock Source selection + * 0b0..Peripheral Clock + * 0b1..Prescaled peripheral clock by PRSC + */ +#define EQDC_FILT_FILT_CS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CS_SHIFT)) & EQDC_FILT_FILT_CS_MASK) + +#define EQDC_FILT_PRSC_MASK (0xF000U) +#define EQDC_FILT_PRSC_SHIFT (12U) +/*! PRSC - Prescaler */ +#define EQDC_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_PRSC_SHIFT)) & EQDC_FILT_PRSC_MASK) +/*! @} */ + +/*! @name LASTEDGE - Last Edge Time Register */ +/*! @{ */ + +#define EQDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define EQDC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter */ +#define EQDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGE_LASTEDGE_SHIFT)) & EQDC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter Register */ +/*! @{ */ + +#define EQDC_POSDPER_POSDPER_MASK (0xFFFFU) +#define EQDC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period */ +#define EQDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPER_POSDPER_SHIFT)) & EQDC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer Register */ +/*! @{ */ + +#define EQDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define EQDC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer */ +#define EQDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERBFR_POSDPERBFR_SHIFT)) & EQDC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ + +#define EQDC_UPOS_POS_MASK (0xFFFFU) +#define EQDC_UPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define EQDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOS_POS_SHIFT)) & EQDC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ + +#define EQDC_LPOS_POS_MASK (0xFFFFU) +#define EQDC_LPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define EQDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOS_POS_SHIFT)) & EQDC_LPOS_POS_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter Register */ +/*! @{ */ + +#define EQDC_POSD_POSD_MASK (0xFFFFU) +#define EQDC_POSD_POSD_SHIFT (0U) +/*! POSD - POSD */ +#define EQDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSD_POSD_SHIFT)) & EQDC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ + +#define EQDC_POSDH_POSDH_MASK (0xFFFFU) +#define EQDC_POSDH_POSDH_SHIFT (0U) +/*! POSDH - POSDH */ +#define EQDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDH_POSDH_SHIFT)) & EQDC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ + +#define EQDC_UPOSH_POSH_MASK (0xFFFFU) +#define EQDC_UPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define EQDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH_POSH_SHIFT)) & EQDC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ + +#define EQDC_LPOSH_LPOSH_MASK (0xFFFFU) +#define EQDC_LPOSH_LPOSH_SHIFT (0U) +/*! LPOSH - POSH */ +#define EQDC_LPOSH_LPOSH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH_LPOSH_SHIFT)) & EQDC_LPOSH_LPOSH_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold Register */ +/*! @{ */ + +#define EQDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define EQDC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold */ +#define EQDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGEH_LASTEDGEH_SHIFT)) & EQDC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold Register */ +/*! @{ */ + +#define EQDC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define EQDC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold */ +#define EQDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERH_POSDPERH_SHIFT)) & EQDC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold Register */ +/*! @{ */ + +#define EQDC_REVH_REVH_MASK (0xFFFFU) +#define EQDC_REVH_REVH_SHIFT (0U) +/*! REVH - REVH */ +#define EQDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_REVH_REVH_SHIFT)) & EQDC_REVH_REVH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter Register */ +/*! @{ */ + +#define EQDC_REV_REV_MASK (0xFFFFU) +#define EQDC_REV_REV_SHIFT (0U) +/*! REV - REV */ +#define EQDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << EQDC_REV_REV_SHIFT)) & EQDC_REV_REV_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization Register */ +/*! @{ */ + +#define EQDC_UINIT_INIT_MASK (0xFFFFU) +#define EQDC_UINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define EQDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UINIT_INIT_SHIFT)) & EQDC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization Register */ +/*! @{ */ + +#define EQDC_LINIT_INIT_MASK (0xFFFFU) +#define EQDC_LINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define EQDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LINIT_INIT_SHIFT)) & EQDC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus Register */ +/*! @{ */ + +#define EQDC_UMOD_MOD_MASK (0xFFFFU) +#define EQDC_UMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define EQDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UMOD_MOD_SHIFT)) & EQDC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus Register */ +/*! @{ */ + +#define EQDC_LMOD_MOD_MASK (0xFFFFU) +#define EQDC_LMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define EQDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LMOD_MOD_SHIFT)) & EQDC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP0 - Upper Position Compare Register 0 */ +/*! @{ */ + +#define EQDC_UCOMP0_UCOMP0_MASK (0xFFFFU) +#define EQDC_UCOMP0_UCOMP0_SHIFT (0U) +/*! UCOMP0 - UCOMP0 */ +#define EQDC_UCOMP0_UCOMP0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP0_UCOMP0_SHIFT)) & EQDC_UCOMP0_UCOMP0_MASK) +/*! @} */ + +/*! @name LCOMP0 - Lower Position Compare Register 0 */ +/*! @{ */ + +#define EQDC_LCOMP0_LCOMP0_MASK (0xFFFFU) +#define EQDC_LCOMP0_LCOMP0_SHIFT (0U) +/*! LCOMP0 - LCOMP0 */ +#define EQDC_LCOMP0_LCOMP0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP0_LCOMP0_SHIFT)) & EQDC_LCOMP0_LCOMP0_MASK) +/*! @} */ + +/*! @name UCOMP1 - Upper Position Compare 1 */ +/*! @{ */ + +#define EQDC_UCOMP1_UCOMP1_MASK (0xFFFFU) +#define EQDC_UCOMP1_UCOMP1_SHIFT (0U) +/*! UCOMP1 - UCOMP1 */ +#define EQDC_UCOMP1_UCOMP1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP1_UCOMP1_SHIFT)) & EQDC_UCOMP1_UCOMP1_MASK) +/*! @} */ + +/*! @name UPOSH1 - Upper Position Holder Register 1 */ +/*! @{ */ + +#define EQDC_UPOSH1_UPOSH1_MASK (0xFFFFU) +#define EQDC_UPOSH1_UPOSH1_SHIFT (0U) +/*! UPOSH1 - UPOSH1 */ +#define EQDC_UPOSH1_UPOSH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH1_UPOSH1_SHIFT)) & EQDC_UPOSH1_UPOSH1_MASK) +/*! @} */ + +/*! @name LCOMP1 - Lower Position Compare 1 */ +/*! @{ */ + +#define EQDC_LCOMP1_LCOMP1_MASK (0xFFFFU) +#define EQDC_LCOMP1_LCOMP1_SHIFT (0U) +/*! LCOMP1 - LCOMP1 */ +#define EQDC_LCOMP1_LCOMP1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP1_LCOMP1_SHIFT)) & EQDC_LCOMP1_LCOMP1_MASK) +/*! @} */ + +/*! @name LPOSH1 - Lower Position Holder Register 1 */ +/*! @{ */ + +#define EQDC_LPOSH1_LPOSH1_MASK (0xFFFFU) +#define EQDC_LPOSH1_LPOSH1_SHIFT (0U) +/*! LPOSH1 - LPOSH1 */ +#define EQDC_LPOSH1_LPOSH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH1_LPOSH1_SHIFT)) & EQDC_LPOSH1_LPOSH1_MASK) +/*! @} */ + +/*! @name UCOMP2 - Upper Position Compare 2 */ +/*! @{ */ + +#define EQDC_UCOMP2_UCOMP2_MASK (0xFFFFU) +#define EQDC_UCOMP2_UCOMP2_SHIFT (0U) +/*! UCOMP2 - UCOMP2 */ +#define EQDC_UCOMP2_UCOMP2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP2_UCOMP2_SHIFT)) & EQDC_UCOMP2_UCOMP2_MASK) +/*! @} */ + +/*! @name UPOSH2 - Upper Position Holder Register 3 */ +/*! @{ */ + +#define EQDC_UPOSH2_UPOSH2_MASK (0xFFFFU) +#define EQDC_UPOSH2_UPOSH2_SHIFT (0U) +/*! UPOSH2 - UPOSH2 */ +#define EQDC_UPOSH2_UPOSH2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH2_UPOSH2_SHIFT)) & EQDC_UPOSH2_UPOSH2_MASK) +/*! @} */ + +/*! @name LCOMP2 - Lower Position Compare 2 */ +/*! @{ */ + +#define EQDC_LCOMP2_LCOMP2_MASK (0xFFFFU) +#define EQDC_LCOMP2_LCOMP2_SHIFT (0U) +/*! LCOMP2 - LCOMP2 */ +#define EQDC_LCOMP2_LCOMP2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP2_LCOMP2_SHIFT)) & EQDC_LCOMP2_LCOMP2_MASK) +/*! @} */ + +/*! @name LPOSH2 - Lower Position Holder Register 2 */ +/*! @{ */ + +#define EQDC_LPOSH2_LPOSH2_MASK (0xFFFFU) +#define EQDC_LPOSH2_LPOSH2_SHIFT (0U) +/*! LPOSH2 - LPOSH2 */ +#define EQDC_LPOSH2_LPOSH2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH2_LPOSH2_SHIFT)) & EQDC_LPOSH2_LPOSH2_MASK) +/*! @} */ + +/*! @name UCOMP3 - Upper Position Compare 3 */ +/*! @{ */ + +#define EQDC_UCOMP3_UCOMP3_MASK (0xFFFFU) +#define EQDC_UCOMP3_UCOMP3_SHIFT (0U) +/*! UCOMP3 - UCOMP3 */ +#define EQDC_UCOMP3_UCOMP3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP3_UCOMP3_SHIFT)) & EQDC_UCOMP3_UCOMP3_MASK) +/*! @} */ + +/*! @name UPOSH3 - Upper Position Holder Register 3 */ +/*! @{ */ + +#define EQDC_UPOSH3_UPOSH3_MASK (0xFFFFU) +#define EQDC_UPOSH3_UPOSH3_SHIFT (0U) +/*! UPOSH3 - UPOSH3 */ +#define EQDC_UPOSH3_UPOSH3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH3_UPOSH3_SHIFT)) & EQDC_UPOSH3_UPOSH3_MASK) +/*! @} */ + +/*! @name LCOMP3 - Lower Position Compare 3 */ +/*! @{ */ + +#define EQDC_LCOMP3_LCOMP3_MASK (0xFFFFU) +#define EQDC_LCOMP3_LCOMP3_SHIFT (0U) +/*! LCOMP3 - LCOMP3 */ +#define EQDC_LCOMP3_LCOMP3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP3_LCOMP3_SHIFT)) & EQDC_LCOMP3_LCOMP3_MASK) +/*! @} */ + +/*! @name LPOSH3 - Lower Position Holder Register 3 */ +/*! @{ */ + +#define EQDC_LPOSH3_LPOSH3_MASK (0xFFFFU) +#define EQDC_LPOSH3_LPOSH3_SHIFT (0U) +/*! LPOSH3 - LPOSH3 */ +#define EQDC_LPOSH3_LPOSH3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH3_LPOSH3_SHIFT)) & EQDC_LPOSH3_LPOSH3_MASK) +/*! @} */ + +/*! @name INTCTRL - Interrupt Control Register */ +/*! @{ */ + +#define EQDC_INTCTRL_SABIE_MASK (0x1U) +#define EQDC_INTCTRL_SABIE_SHIFT (0U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_SABIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIE_SHIFT)) & EQDC_INTCTRL_SABIE_MASK) + +#define EQDC_INTCTRL_SABIRQ_MASK (0x2U) +#define EQDC_INTCTRL_SABIRQ_SHIFT (1U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred + */ +#define EQDC_INTCTRL_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIRQ_SHIFT)) & EQDC_INTCTRL_SABIRQ_MASK) + +#define EQDC_INTCTRL_DIRIE_MASK (0x4U) +#define EQDC_INTCTRL_DIRIE_SHIFT (2U) +/*! DIRIE - Count direction change interrupt enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_DIRIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIE_SHIFT)) & EQDC_INTCTRL_DIRIE_MASK) + +#define EQDC_INTCTRL_DIRIRQ_MASK (0x8U) +#define EQDC_INTCTRL_DIRIRQ_SHIFT (3U) +/*! DIRIRQ - Count direction change interrupt + * 0b0..Count direction unchanged + * 0b1..Count direction changed + */ +#define EQDC_INTCTRL_DIRIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIRQ_SHIFT)) & EQDC_INTCTRL_DIRIRQ_MASK) + +#define EQDC_INTCTRL_RUIE_MASK (0x10U) +#define EQDC_INTCTRL_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_RUIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIE_SHIFT)) & EQDC_INTCTRL_RUIE_MASK) + +#define EQDC_INTCTRL_RUIRQ_MASK (0x20U) +#define EQDC_INTCTRL_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define EQDC_INTCTRL_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIRQ_SHIFT)) & EQDC_INTCTRL_RUIRQ_MASK) + +#define EQDC_INTCTRL_ROIE_MASK (0x40U) +#define EQDC_INTCTRL_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_ROIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIE_SHIFT)) & EQDC_INTCTRL_ROIE_MASK) + +#define EQDC_INTCTRL_ROIRQ_MASK (0x80U) +#define EQDC_INTCTRL_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ +#define EQDC_INTCTRL_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIRQ_SHIFT)) & EQDC_INTCTRL_ROIRQ_MASK) + +#define EQDC_INTCTRL_CMP0IE_MASK (0x100U) +#define EQDC_INTCTRL_CMP0IE_SHIFT (8U) +/*! CMP0IE - Compare 0 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP0IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IE_SHIFT)) & EQDC_INTCTRL_CMP0IE_MASK) + +#define EQDC_INTCTRL_CMP0IRQ_MASK (0x200U) +#define EQDC_INTCTRL_CMP0IRQ_SHIFT (9U) +/*! CMP0IRQ - Compare 0 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP0 value) + * 0b1..COMP match has occurred (the position counter matches the COMP0 value) + */ +#define EQDC_INTCTRL_CMP0IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IRQ_SHIFT)) & EQDC_INTCTRL_CMP0IRQ_MASK) + +#define EQDC_INTCTRL_CMP1IE_MASK (0x400U) +#define EQDC_INTCTRL_CMP1IE_SHIFT (10U) +/*! CMP1IE - Compare1 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP1IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IE_SHIFT)) & EQDC_INTCTRL_CMP1IE_MASK) + +#define EQDC_INTCTRL_CMP1IRQ_MASK (0x800U) +#define EQDC_INTCTRL_CMP1IRQ_SHIFT (11U) +/*! CMP1IRQ - Compare1 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP1 value) + * 0b1..COMP1 match has occurred (the position counter matches the COMP1 value) + */ +#define EQDC_INTCTRL_CMP1IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IRQ_SHIFT)) & EQDC_INTCTRL_CMP1IRQ_MASK) + +#define EQDC_INTCTRL_CMP2IE_MASK (0x1000U) +#define EQDC_INTCTRL_CMP2IE_SHIFT (12U) +/*! CMP2IE - Compare2 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP2IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IE_SHIFT)) & EQDC_INTCTRL_CMP2IE_MASK) + +#define EQDC_INTCTRL_CMP2IRQ_MASK (0x2000U) +#define EQDC_INTCTRL_CMP2IRQ_SHIFT (13U) +/*! CMP2IRQ - Compare2 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP2 value) + * 0b1..COMP2 match has occurred (the position counter matches the COMP2 value) + */ +#define EQDC_INTCTRL_CMP2IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IRQ_SHIFT)) & EQDC_INTCTRL_CMP2IRQ_MASK) + +#define EQDC_INTCTRL_CMP3IE_MASK (0x4000U) +#define EQDC_INTCTRL_CMP3IE_SHIFT (14U) +/*! CMP3IE - Compare3 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP3IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IE_SHIFT)) & EQDC_INTCTRL_CMP3IE_MASK) + +#define EQDC_INTCTRL_CMP3IRQ_MASK (0x8000U) +#define EQDC_INTCTRL_CMP3IRQ_SHIFT (15U) +/*! CMP3IRQ - Compare3 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP3 value) + * 0b1..COMP3 match has occurred (the position counter matches the COMP3 value) + */ +#define EQDC_INTCTRL_CMP3IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IRQ_SHIFT)) & EQDC_INTCTRL_CMP3IRQ_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ + +#define EQDC_WTR_WDOG_MASK (0xFFFFU) +#define EQDC_WTR_WDOG_SHIFT (0U) +/*! WDOG - WDOG */ +#define EQDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << EQDC_WTR_WDOG_SHIFT)) & EQDC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor Register */ +/*! @{ */ + +#define EQDC_IMR_HOME_ENABLE_MASK (0x1U) +#define EQDC_IMR_HOME_ENABLE_SHIFT (0U) +/*! HOME_ENABLE - HOME_ENABLE */ +#define EQDC_IMR_HOME_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_HOME_ENABLE_SHIFT)) & EQDC_IMR_HOME_ENABLE_MASK) + +#define EQDC_IMR_INDEX_PRESET_MASK (0x2U) +#define EQDC_IMR_INDEX_PRESET_SHIFT (1U) +/*! INDEX_PRESET - INDEX_PRESET */ +#define EQDC_IMR_INDEX_PRESET(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_INDEX_PRESET_SHIFT)) & EQDC_IMR_INDEX_PRESET_MASK) + +#define EQDC_IMR_PHB_MASK (0x4U) +#define EQDC_IMR_PHB_SHIFT (2U) +/*! PHB - PHB */ +#define EQDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHB_SHIFT)) & EQDC_IMR_PHB_MASK) + +#define EQDC_IMR_PHA_MASK (0x8U) +#define EQDC_IMR_PHA_SHIFT (3U) +/*! PHA - PHA */ +#define EQDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHA_SHIFT)) & EQDC_IMR_PHA_MASK) + +#define EQDC_IMR_FHOM_ENA_MASK (0x10U) +#define EQDC_IMR_FHOM_ENA_SHIFT (4U) +/*! FHOM_ENA - filter operation on HOME/ENABLE input */ +#define EQDC_IMR_FHOM_ENA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FHOM_ENA_SHIFT)) & EQDC_IMR_FHOM_ENA_MASK) + +#define EQDC_IMR_FIND_PRE_MASK (0x20U) +#define EQDC_IMR_FIND_PRE_SHIFT (5U) +/*! FIND_PRE - filter operation on INDEX/PRESET input */ +#define EQDC_IMR_FIND_PRE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FIND_PRE_SHIFT)) & EQDC_IMR_FIND_PRE_MASK) + +#define EQDC_IMR_FPHB_MASK (0x40U) +#define EQDC_IMR_FPHB_SHIFT (6U) +/*! FPHB - filter operation on PHASEB input */ +#define EQDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHB_SHIFT)) & EQDC_IMR_FPHB_MASK) + +#define EQDC_IMR_FPHA_MASK (0x80U) +#define EQDC_IMR_FPHA_SHIFT (7U) +/*! FPHA - filter operation on PHASEA input */ +#define EQDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHA_SHIFT)) & EQDC_IMR_FPHA_MASK) + +#define EQDC_IMR_CMPF0_MASK (0x100U) +#define EQDC_IMR_CMPF0_SHIFT (8U) +/*! CMPF0 - Position Compare 0 Flag Output + * 0b0..When the position counter is less than value of COMP0 register + * 0b1..When the position counter is greater or equal than value of COMP0 register + */ +#define EQDC_IMR_CMPF0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMPF0_SHIFT)) & EQDC_IMR_CMPF0_MASK) + +#define EQDC_IMR_CMP1F_MASK (0x200U) +#define EQDC_IMR_CMP1F_SHIFT (9U) +/*! CMP1F - Position Compare1 Flag Output + * 0b0..When the position counter is less than value of COMP1 register + * 0b1..When the position counter is greater or equal than value of COMP1 register + */ +#define EQDC_IMR_CMP1F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP1F_SHIFT)) & EQDC_IMR_CMP1F_MASK) + +#define EQDC_IMR_CMP2F_MASK (0x400U) +#define EQDC_IMR_CMP2F_SHIFT (10U) +/*! CMP2F - Position Compare2 Flag Output + * 0b0..When the position counter is less than value of COMP2 register + * 0b1..When the position counter is greater or equal than value of COMP2 register + */ +#define EQDC_IMR_CMP2F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP2F_SHIFT)) & EQDC_IMR_CMP2F_MASK) + +#define EQDC_IMR_CMP3F_MASK (0x800U) +#define EQDC_IMR_CMP3F_SHIFT (11U) +/*! CMP3F - Position Compare3 Flag Output + * 0b0..When the position counter value is less than value of COMP3 register + * 0b1..When the position counter is greater or equal than value of COMP3 register + */ +#define EQDC_IMR_CMP3F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP3F_SHIFT)) & EQDC_IMR_CMP3F_MASK) + +#define EQDC_IMR_DIRH_MASK (0x4000U) +#define EQDC_IMR_DIRH_SHIFT (14U) +/*! DIRH - Count Direction Flag Hold */ +#define EQDC_IMR_DIRH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIRH_SHIFT)) & EQDC_IMR_DIRH_MASK) + +#define EQDC_IMR_DIR_MASK (0x8000U) +#define EQDC_IMR_DIR_SHIFT (15U) +/*! DIR - Count Direction Flag Output + * 0b0..Current count was in the down direction + * 0b1..Current count was in the up direction + */ +#define EQDC_IMR_DIR(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIR_SHIFT)) & EQDC_IMR_DIR_MASK) +/*! @} */ + +/*! @name TST - Test Register */ +/*! @{ */ + +#define EQDC_TST_TEST_COUNT_MASK (0xFFU) +#define EQDC_TST_TEST_COUNT_SHIFT (0U) +/*! TEST_COUNT - TEST_COUNT */ +#define EQDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_COUNT_SHIFT)) & EQDC_TST_TEST_COUNT_MASK) + +#define EQDC_TST_TEST_PERIOD_MASK (0x1F00U) +#define EQDC_TST_TEST_PERIOD_SHIFT (8U) +/*! TEST_PERIOD - TEST_PERIOD */ +#define EQDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_PERIOD_SHIFT)) & EQDC_TST_TEST_PERIOD_MASK) + +#define EQDC_TST_QDN_MASK (0x2000U) +#define EQDC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Generates a positive quadrature decoder signal + * 0b1..Generates a negative quadrature decoder signal + */ +#define EQDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_QDN_SHIFT)) & EQDC_TST_QDN_MASK) + +#define EQDC_TST_TCE_MASK (0x4000U) +#define EQDC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TCE_SHIFT)) & EQDC_TST_TCE_MASK) + +#define EQDC_TST_TEN_MASK (0x8000U) +#define EQDC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEN_SHIFT)) & EQDC_TST_TEN_MASK) +/*! @} */ + +/*! @name UVERID - Upper VERID */ +/*! @{ */ + +#define EQDC_UVERID_UVERID_MASK (0xFFFFU) +#define EQDC_UVERID_UVERID_SHIFT (0U) +/*! UVERID - UVERID */ +#define EQDC_UVERID_UVERID(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UVERID_UVERID_SHIFT)) & EQDC_UVERID_UVERID_MASK) +/*! @} */ + +/*! @name LVERID - Lower VERID */ +/*! @{ */ + +#define EQDC_LVERID_LVERID_MASK (0xFFFFU) +#define EQDC_LVERID_LVERID_SHIFT (0U) +/*! LVERID - LVERID */ +#define EQDC_LVERID_LVERID(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LVERID_LVERID_SHIFT)) & EQDC_LVERID_LVERID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EQDC_Register_Masks */ + + +/*! + * @} + */ /* end of group EQDC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_EQDC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ERM.h new file mode 100644 index 000000000..5d288ec86 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_ERM.h @@ -0,0 +1,300 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for ERM +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_ERM.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for ERM + * + * CMSIS Peripheral Access Layer for ERM + */ + +#if !defined(PERI_ERM_H_) +#define PERI_ERM_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +#if !defined(ERM_MEMORY_CHANNEL_T_) +#define ERM_MEMORY_CHANNEL_T_ +/*! + * @addtogroup erm_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the erm_memory_channel + * + * Defines the structure for the ERM resource collections. + */ + +typedef enum _erm_memory_channel +{ + kERM_MemoryChannelRAMA0 = 0U, /**< Memory RAMA0 */ + kERM_MemoryChannelFLASH = 1U, /**< Memory FLASH */ +} erm_memory_channel_t; + +/* @} */ +#endif /* ERM_MEMORY_CHANNEL_T_ */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ERM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer + * @{ + */ + +/** ERM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ + uint8_t RESERVED_1[236]; + __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */ + __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */ + __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ +} ERM_Type; + +/* ---------------------------------------------------------------------------- + -- ERM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Register_Masks ERM Register Masks + * @{ + */ + +/*! @name CR0 - ERM Configuration Register 0 */ +/*! @{ */ + +#define ERM_CR0_ENCIE1_MASK (0x4000000U) +#define ERM_CR0_ENCIE1_SHIFT (26U) +/*! ENCIE1 - ENCIE1 + * 0b0..Interrupt notification of Memory 1 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 1 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) + +#define ERM_CR0_ESCIE1_MASK (0x8000000U) +#define ERM_CR0_ESCIE1_SHIFT (27U) +/*! ESCIE1 - ESCIE1 + * 0b0..Interrupt notification of Memory 1 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 1 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) + +#define ERM_CR0_ENCIE0_MASK (0x40000000U) +#define ERM_CR0_ENCIE0_SHIFT (30U) +/*! ENCIE0 - ENCIE0 + * 0b0..Interrupt notification of Memory 0 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 0 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) + +#define ERM_CR0_ESCIE0_MASK (0x80000000U) +#define ERM_CR0_ESCIE0_SHIFT (31U) +/*! ESCIE0 - ESCIE0 + * 0b0..Interrupt notification of Memory 0 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 0 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) +/*! @} */ + +/*! @name SR0 - ERM Status Register 0 */ +/*! @{ */ + +#define ERM_SR0_NCE1_MASK (0x4000000U) +#define ERM_SR0_NCE1_SHIFT (26U) +/*! NCE1 - NCE1 + * 0b0..No non-correctable error event on Memory 1 detected. + * 0b1..Non-correctable error event on Memory 1 detected. + */ +#define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) + +#define ERM_SR0_SBC1_MASK (0x8000000U) +#define ERM_SR0_SBC1_SHIFT (27U) +/*! SBC1 - SBC1 + * 0b0..No single-bit correction event on Memory 1 detected. + * 0b1..Single-bit correction event on Memory 1 detected. + */ +#define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) + +#define ERM_SR0_NCE0_MASK (0x40000000U) +#define ERM_SR0_NCE0_SHIFT (30U) +/*! NCE0 - NCE0 + * 0b0..No non-correctable error event on Memory 0 detected. + * 0b1..Non-correctable error event on Memory 0 detected. + */ +#define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) + +#define ERM_SR0_SBC0_MASK (0x80000000U) +#define ERM_SR0_SBC0_SHIFT (31U) +/*! SBC0 - SBC0 + * 0b0..No single-bit correction event on Memory 0 detected. + * 0b1..Single-bit correction event on Memory 0 detected. + */ +#define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) +/*! @} */ + +/*! @name EAR0 - ERM Memory 0 Error Address Register */ +/*! @{ */ + +#define ERM_EAR0_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR0_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK) +/*! @} */ + +/*! @name SYN0 - ERM Memory 0 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN0_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN0_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ERM_Register_Masks */ + + +/*! + * @} + */ /* end of group ERM_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_ERM_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMC.h new file mode 100644 index 000000000..6b6c47464 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMC.h @@ -0,0 +1,264 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for FMC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_FMC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for FMC + * + * CMSIS Peripheral Access Layer for FMC + */ + +#if !defined(PERI_FMC_H_) +#define PERI_FMC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t REMAP; /**< Data Remap, offset: 0x20 */ + uint8_t RESERVED_1[988]; + __IO uint32_t FCCR; /**< Flash Cache Control Register, offset: 0x400 */ + __IO uint32_t FCAR; /**< Flash Cache Access Register, offset: 0x404 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FCTG; /**< Flash Cache Tag, offset: 0x40C */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCLN0; /**< Flash Cache Line Num0, offset: 0x420 */ + __IO uint32_t FCLN1; /**< Flash Cache Line Num1, offset: 0x424 */ + __IO uint32_t FCLN2; /**< Flash Cache Line Num2, offset: 0x428 */ + __IO uint32_t FCLN3; /**< Flash Cache Line Num3, offset: 0x42C */ +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/*! @name REMAP - Data Remap */ +/*! @{ */ + +#define FMC_REMAP_REMAPLK_MASK (0x1U) +#define FMC_REMAP_REMAPLK_SHIFT (0U) +/*! REMAPLK - Remap Lock Enable + * 0b0..Lock disabled: can write to REMAP + * 0b1..Lock enabled: cannot write to REMAP + */ +#define FMC_REMAP_REMAPLK(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_REMAPLK_SHIFT)) & FMC_REMAP_REMAPLK_MASK) + +#define FMC_REMAP_LIM_MASK (0x7F0000U) +#define FMC_REMAP_LIM_SHIFT (16U) +/*! LIM - LIM Remapping Address */ +#define FMC_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIM_SHIFT)) & FMC_REMAP_LIM_MASK) + +#define FMC_REMAP_LIMDP_MASK (0x7F000000U) +#define FMC_REMAP_LIMDP_SHIFT (24U) +/*! LIMDP - LIMDP Remapping Address */ +#define FMC_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIMDP_SHIFT)) & FMC_REMAP_LIMDP_MASK) +/*! @} */ + +/*! @name FCCR - Flash Cache Control Register */ +/*! @{ */ + +#define FMC_FCCR_WAY_LOCK_MASK (0xFU) +#define FMC_FCCR_WAY_LOCK_SHIFT (0U) +/*! WAY_LOCK - Cache Way Lock */ +#define FMC_FCCR_WAY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCCR_WAY_LOCK_SHIFT)) & FMC_FCCR_WAY_LOCK_MASK) + +#define FMC_FCCR_LOCK_MASK (0x80000000U) +#define FMC_FCCR_LOCK_SHIFT (31U) +/*! LOCK - Lock Flash Cache Control + * 0b0..allows access and use of flash cache program model. + * 0b1..blocks all flash cache peripheral accesses and Lock program model till next reset - the flash cache will + * continue to operate as configured before being locked, but no changes to the flash cache control are + * possible until the next reset and all reads of flash cache program model registers return zeros. FCCR: Support + * read, Write invalid. FCAR/FCTG/FCLN0/FCLN1/FCLN2/FCLN3: Read returns zeros, Write invalid. + */ +#define FMC_FCCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCCR_LOCK_SHIFT)) & FMC_FCCR_LOCK_MASK) +/*! @} */ + +/*! @name FCAR - Flash Cache Access Register */ +/*! @{ */ + +#define FMC_FCAR_CACHES_WAY_NUM_MASK (0x3U) +#define FMC_FCAR_CACHES_WAY_NUM_SHIFT (0U) +/*! CACHES_WAY_NUM - Flash Cache Way Number */ +#define FMC_FCAR_CACHES_WAY_NUM(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCAR_CACHES_WAY_NUM_SHIFT)) & FMC_FCAR_CACHES_WAY_NUM_MASK) + +#define FMC_FCAR_CACHES_SET_NUM_MASK (0x10U) +#define FMC_FCAR_CACHES_SET_NUM_SHIFT (4U) +/*! CACHES_SET_NUM - Flash Cache Set Number */ +#define FMC_FCAR_CACHES_SET_NUM(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCAR_CACHES_SET_NUM_SHIFT)) & FMC_FCAR_CACHES_SET_NUM_MASK) + +#define FMC_FCAR_TYPE_MASK (0xC0000000U) +#define FMC_FCAR_TYPE_SHIFT (30U) +/*! TYPE - Operation of cache type */ +#define FMC_FCAR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCAR_TYPE_SHIFT)) & FMC_FCAR_TYPE_MASK) +/*! @} */ + +/*! @name FCTG - Flash Cache Tag */ +/*! @{ */ + +#define FMC_FCTG_VALID_MASK (0x1U) +#define FMC_FCTG_VALID_SHIFT (0U) +/*! VALID - Flash Cache Tag Valid Bit */ +#define FMC_FCTG_VALID(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTG_VALID_SHIFT)) & FMC_FCTG_VALID_MASK) + +#define FMC_FCTG_ADDESS_MASK (0xFFFFC0U) +#define FMC_FCTG_ADDESS_SHIFT (6U) +/*! ADDESS - Flash Cache Tag Address Bit[23:6] */ +#define FMC_FCTG_ADDESS(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTG_ADDESS_SHIFT)) & FMC_FCTG_ADDESS_MASK) +/*! @} */ + +/*! @name FCLN0 - Flash Cache Line Num0 */ +/*! @{ */ + +#define FMC_FCLN0_DATAWxSyLM_MASK (0xFFFFFFFFU) +#define FMC_FCLN0_DATAWxSyLM_SHIFT (0U) +/*! DATAWxSyLM - The lowermost word (bits [31:0]) of Flash Cache Line Data */ +#define FMC_FCLN0_DATAWxSyLM(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCLN0_DATAWxSyLM_SHIFT)) & FMC_FCLN0_DATAWxSyLM_MASK) +/*! @} */ + +/*! @name FCLN1 - Flash Cache Line Num1 */ +/*! @{ */ + +#define FMC_FCLN1_DATAWxSyML_MASK (0xFFFFFFFFU) +#define FMC_FCLN1_DATAWxSyML_SHIFT (0U) +/*! DATAWxSyML - The mid-lower word (bits [63:32]) of Flash Cache Line Data */ +#define FMC_FCLN1_DATAWxSyML(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCLN1_DATAWxSyML_SHIFT)) & FMC_FCLN1_DATAWxSyML_MASK) +/*! @} */ + +/*! @name FCLN2 - Flash Cache Line Num2 */ +/*! @{ */ + +#define FMC_FCLN2_DATAWxSyMU_MASK (0xFFFFFFFFU) +#define FMC_FCLN2_DATAWxSyMU_SHIFT (0U) +/*! DATAWxSyMU - The mid-upper word (bits [95:64]) of Flash Cache Line Data */ +#define FMC_FCLN2_DATAWxSyMU(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCLN2_DATAWxSyMU_SHIFT)) & FMC_FCLN2_DATAWxSyMU_MASK) +/*! @} */ + +/*! @name FCLN3 - Flash Cache Line Num3 */ +/*! @{ */ + +#define FMC_FCLN3_DATAWxSyUM_MASK (0xFFFFFFFFU) +#define FMC_FCLN3_DATAWxSyUM_SHIFT (0U) +/*! DATAWxSyUM - The uppermost word (bits [127:96]) of Flash Cache Line Data */ +#define FMC_FCLN3_DATAWxSyUM(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCLN3_DATAWxSyUM_SHIFT)) & FMC_FCLN3_DATAWxSyUM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMC_Register_Masks */ + + +/*! + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FMC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMU.h new file mode 100644 index 000000000..a6e51be6a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FMU.h @@ -0,0 +1,345 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for FMU +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_FMU.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for FMU + * + * CMSIS Peripheral Access Layer for FMU + */ + +#if !defined(PERI_FMU_H_) +#define PERI_FMU_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer + * @{ + */ + +/** FMU - Size of Registers Arrays */ +#define FMU_FCCOB_COUNT 8u + +/** FMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FCCOB[FMU_FCCOB_COUNT]; /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */ +} FMU_Type; + +/* ---------------------------------------------------------------------------- + -- FMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Register_Masks FMU Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMU_FSTAT_FAIL_MASK (0x1U) +#define FMU_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMU_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK) + +#define FMU_FSTAT_CMDABT_MASK (0x4U) +#define FMU_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMU_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK) + +#define FMU_FSTAT_PVIOL_MASK (0x10U) +#define FMU_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMU_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK) + +#define FMU_FSTAT_ACCERR_MASK (0x20U) +#define FMU_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMU_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK) + +#define FMU_FSTAT_CWSABT_MASK (0x40U) +#define FMU_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMU_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK) + +#define FMU_FSTAT_CCIF_MASK (0x80U) +#define FMU_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command, initialization, or power mode recovery in progress + * 0b1..Flash command, initialization, or power mode recovery has completed + */ +#define FMU_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK) + +#define FMU_FSTAT_CMDPRT_MASK (0x300U) +#define FMU_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command protection level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMU_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK) + +#define FMU_FSTAT_CMDP_MASK (0x800U) +#define FMU_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command protection status flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMU_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK) + +#define FMU_FSTAT_CMDDID_MASK (0xF000U) +#define FMU_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command domain ID */ +#define FMU_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK) + +#define FMU_FSTAT_DFDIF_MASK (0x10000U) +#define FMU_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access + */ +#define FMU_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK) + +#define FMU_FSTAT_SALV_USED_MASK (0x20000U) +#define FMU_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMU_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK) + +#define FMU_FSTAT_PEWEN_MASK (0x3000000U) +#define FMU_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMU_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK) + +#define FMU_FSTAT_PERDY_MASK (0x80000000U) +#define FMU_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program-Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation not stalled + * 0b1..Program or sector erase command operation ready to execute + */ +#define FMU_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMU_FCNFG_CCIE_MASK (0x80U) +#define FMU_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled + */ +#define FMU_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK) + +#define FMU_FCNFG_ERSREQ_MASK (0x100U) +#define FMU_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMU_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK) + +#define FMU_FCNFG_DFDIE_MASK (0x10000U) +#define FMU_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled + */ +#define FMU_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK) + +#define FMU_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMU_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK) + +#define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMU_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMU_FCTRL_RWSC_MASK (0xFU) +#define FMU_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control */ +#define FMU_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK) + +#define FMU_FCTRL_LSACTIVE_MASK (0x100U) +#define FMU_FCTRL_LSACTIVE_SHIFT (8U) +/*! LSACTIVE - Low speed active mode + * 0b0..Full speed active mode requested + * 0b1..Low speed active mode requested + */ +#define FMU_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_LSACTIVE_SHIFT)) & FMU_FCTRL_LSACTIVE_MASK) + +#define FMU_FCTRL_FDFD_MASK (0x10000U) +#define FMU_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt + * request is generated if the DFDIE bit is set. + */ +#define FMU_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK) + +#define FMU_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMU_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMU_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FCCOB - Flash Common Command Object Registers */ +/*! @{ */ + +#define FMU_FCCOB_CCOBn_MASK (0xFFFFFFFFU) +#define FMU_FCCOB_CCOBn_SHIFT (0U) +/*! CCOBn - CCOBn */ +#define FMU_FCCOB_CCOBn(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMU_Register_Masks */ + + +/*! + * @} + */ /* end of group FMU_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FMU_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FREQME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FREQME.h new file mode 100644 index 000000000..84fb636db --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_FREQME.h @@ -0,0 +1,336 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for FREQME +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_FREQME.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for FREQME + * + * CMSIS Peripheral Access Layer for FREQME + */ + +#if !defined(PERI_FREQME_H_) +#define PERI_FREQME_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FREQME Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer + * @{ + */ + +/** FREQME - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + __I uint32_t CTRL_R; /**< Control (in Read mode), offset: 0x0 */ + __O uint32_t CTRL_W; /**< Control (in Write mode), offset: 0x0 */ + }; + __IO uint32_t CTRLSTAT; /**< Control Status, offset: 0x4 */ + __IO uint32_t MIN; /**< Minimum, offset: 0x8 */ + __IO uint32_t MAX; /**< Maximum, offset: 0xC */ +} FREQME_Type; + +/* ---------------------------------------------------------------------------- + -- FREQME Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Register_Masks FREQME Register Masks + * @{ + */ + +/*! @name CTRL_R - Control (in Read mode) */ +/*! @{ */ + +#define FREQME_CTRL_R_RESULT_MASK (0x7FFFFFFFU) +#define FREQME_CTRL_R_RESULT_SHIFT (0U) +#define FREQME_CTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK) + +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Complete + * 0b1..In progress + */ +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRL_W - Control (in Write mode) */ +/*! @{ */ + +#define FREQME_CTRL_W_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRL_W_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Clock Scaling Factor */ +#define FREQME_CTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK) + +#define FREQME_CTRL_W_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRL_W_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Width Measurement Mode Select + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK) + +#define FREQME_CTRL_W_PULSE_POL_MASK (0x200U) +#define FREQME_CTRL_W_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK) + +#define FREQME_CTRL_W_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRL_W_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Terminates measurement + * 0b1..Initiates measurement + */ +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRLSTAT - Control Status */ +/*! @{ */ + +#define FREQME_CTRLSTAT_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRLSTAT_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Scale */ +#define FREQME_CTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK) + +#define FREQME_CTRLSTAT_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRLSTAT_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Mode + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK) + +#define FREQME_CTRLSTAT_PULSE_POL_MASK (0x200U) +#define FREQME_CTRLSTAT_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_STAT_MASK (0x1000000U) +#define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT (24U) +/*! LT_MIN_STAT - Less Than Minimum Results Status + * 0b0..Greater than MIN[MIN_VALUE] + * 0b1..Less than MIN[MIN_VALUE] + */ +#define FREQME_CTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_STAT_MASK (0x2000000U) +#define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT (25U) +/*! GT_MAX_STAT - Greater Than Maximum Result Status + * 0b0..Less than MAX[MAX_VALUE] + * 0b1..Greater than MAX[MAX_VALUE] + */ +#define FREQME_CTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U) +#define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT (26U) +/*! RESULT_READY_STAT - Result Ready Status + * 0b0..Not complete + * 0b1..Complete + */ +#define FREQME_CTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK) + +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement in Progress Status + * 0b0..Not in progress + * 0b1..In progress + */ +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name MIN - Minimum */ +/*! @{ */ + +#define FREQME_MIN_MIN_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MIN_MIN_VALUE_SHIFT (0U) +/*! MIN_VALUE - Minimum Value */ +#define FREQME_MIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK) +/*! @} */ + +/*! @name MAX - Maximum */ +/*! @{ */ + +#define FREQME_MAX_MAX_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MAX_MAX_VALUE_SHIFT (0U) +/*! MAX_VALUE - Maximum Value */ +#define FREQME_MAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FREQME_Register_Masks */ + + +/*! + * @} + */ /* end of group FREQME_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FREQME_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GLIKEY.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GLIKEY.h new file mode 100644 index 000000000..cc7da88d3 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GLIKEY.h @@ -0,0 +1,322 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for GLIKEY +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_GLIKEY.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for GLIKEY + * + * CMSIS Peripheral Access Layer for GLIKEY + */ + +#if !defined(PERI_GLIKEY_H_) +#define PERI_GLIKEY_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- GLIKEY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GLIKEY_Peripheral_Access_Layer GLIKEY Peripheral Access Layer + * @{ + */ + +/** GLIKEY - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL_0; /**< Control Register 0 SFR, offset: 0x0 */ + __IO uint32_t CTRL_1; /**< Control Register 1 SFR, offset: 0x4 */ + __IO uint32_t INTR_CTRL; /**< Interrupt Control, offset: 0x8 */ + __I uint32_t STATUS; /**< Status, offset: 0xC */ + uint8_t RESERVED_0[236]; + __I uint32_t VERSION; /**< IP Version, offset: 0xFC */ +} GLIKEY_Type; + +/* ---------------------------------------------------------------------------- + -- GLIKEY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GLIKEY_Register_Masks GLIKEY Register Masks + * @{ + */ + +/*! @name CTRL_0 - Control Register 0 SFR */ +/*! @{ */ + +#define GLIKEY_CTRL_0_WRITE_INDEX_MASK (0xFFU) +#define GLIKEY_CTRL_0_WRITE_INDEX_SHIFT (0U) +/*! WRITE_INDEX - Write Index */ +#define GLIKEY_CTRL_0_WRITE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WRITE_INDEX_SHIFT)) & GLIKEY_CTRL_0_WRITE_INDEX_MASK) + +#define GLIKEY_CTRL_0_RESERVED15_MASK (0xFF00U) +#define GLIKEY_CTRL_0_RESERVED15_SHIFT (8U) +/*! RESERVED15 - Reserved for Future Use */ +#define GLIKEY_CTRL_0_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED15_SHIFT)) & GLIKEY_CTRL_0_RESERVED15_MASK) + +#define GLIKEY_CTRL_0_WR_EN_0_MASK (0x30000U) +#define GLIKEY_CTRL_0_WR_EN_0_SHIFT (16U) +/*! WR_EN_0 - Write Enable 0 */ +#define GLIKEY_CTRL_0_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WR_EN_0_SHIFT)) & GLIKEY_CTRL_0_WR_EN_0_MASK) + +#define GLIKEY_CTRL_0_SFT_RST_MASK (0x40000U) +#define GLIKEY_CTRL_0_SFT_RST_SHIFT (18U) +/*! SFT_RST - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0 + * 0b0..No effect + * 0b1..Triggers the soft reset + */ +#define GLIKEY_CTRL_0_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_SFT_RST_SHIFT)) & GLIKEY_CTRL_0_SFT_RST_MASK) + +#define GLIKEY_CTRL_0_RESERVED31_MASK (0xFFF80000U) +#define GLIKEY_CTRL_0_RESERVED31_SHIFT (19U) +/*! RESERVED31 - Reserved for Future Use */ +#define GLIKEY_CTRL_0_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED31_SHIFT)) & GLIKEY_CTRL_0_RESERVED31_MASK) +/*! @} */ + +/*! @name CTRL_1 - Control Register 1 SFR */ +/*! @{ */ + +#define GLIKEY_CTRL_1_READ_INDEX_MASK (0xFFU) +#define GLIKEY_CTRL_1_READ_INDEX_SHIFT (0U) +/*! READ_INDEX - Index status, Writing an index value to this register will request the block to return the lock status of this index. */ +#define GLIKEY_CTRL_1_READ_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_READ_INDEX_SHIFT)) & GLIKEY_CTRL_1_READ_INDEX_MASK) + +#define GLIKEY_CTRL_1_RESERVED15_MASK (0xFF00U) +#define GLIKEY_CTRL_1_RESERVED15_SHIFT (8U) +/*! RESERVED15 - Reserved for Future Use */ +#define GLIKEY_CTRL_1_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED15_SHIFT)) & GLIKEY_CTRL_1_RESERVED15_MASK) + +#define GLIKEY_CTRL_1_WR_EN_1_MASK (0x30000U) +#define GLIKEY_CTRL_1_WR_EN_1_SHIFT (16U) +/*! WR_EN_1 - Write Enable One */ +#define GLIKEY_CTRL_1_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_WR_EN_1_SHIFT)) & GLIKEY_CTRL_1_WR_EN_1_MASK) + +#define GLIKEY_CTRL_1_SFR_LOCK_MASK (0x3C0000U) +#define GLIKEY_CTRL_1_SFR_LOCK_SHIFT (18U) +/*! SFR_LOCK - LOCK register for GLIKEY */ +#define GLIKEY_CTRL_1_SFR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_SFR_LOCK_SHIFT)) & GLIKEY_CTRL_1_SFR_LOCK_MASK) + +#define GLIKEY_CTRL_1_RESERVED31_MASK (0xFFC00000U) +#define GLIKEY_CTRL_1_RESERVED31_SHIFT (22U) +/*! RESERVED31 - Reserved for Future Use */ +#define GLIKEY_CTRL_1_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED31_SHIFT)) & GLIKEY_CTRL_1_RESERVED31_MASK) +/*! @} */ + +/*! @name INTR_CTRL - Interrupt Control */ +/*! @{ */ + +#define GLIKEY_INTR_CTRL_INT_EN_MASK (0x1U) +#define GLIKEY_INTR_CTRL_INT_EN_SHIFT (0U) +/*! INT_EN - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port */ +#define GLIKEY_INTR_CTRL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_EN_SHIFT)) & GLIKEY_INTR_CTRL_INT_EN_MASK) + +#define GLIKEY_INTR_CTRL_INT_CLR_MASK (0x2U) +#define GLIKEY_INTR_CTRL_INT_CLR_SHIFT (1U) +/*! INT_CLR - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0 */ +#define GLIKEY_INTR_CTRL_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_CLR_SHIFT)) & GLIKEY_INTR_CTRL_INT_CLR_MASK) + +#define GLIKEY_INTR_CTRL_INT_SET_MASK (0x4U) +#define GLIKEY_INTR_CTRL_INT_SET_SHIFT (2U) +/*! INT_SET - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0 + * 0b0..No effect + * 0b1..Triggers interrupt + */ +#define GLIKEY_INTR_CTRL_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_SET_SHIFT)) & GLIKEY_INTR_CTRL_INT_SET_MASK) + +#define GLIKEY_INTR_CTRL_RESERVED31_MASK (0xFFFFFFF8U) +#define GLIKEY_INTR_CTRL_RESERVED31_SHIFT (3U) +/*! RESERVED31 - Reserved for Future Use */ +#define GLIKEY_INTR_CTRL_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_RESERVED31_SHIFT)) & GLIKEY_INTR_CTRL_RESERVED31_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define GLIKEY_STATUS_INT_STATUS_MASK (0x1U) +#define GLIKEY_STATUS_INT_STATUS_SHIFT (0U) +/*! INT_STATUS - Interrupt Status. + * 0b0..No effect + * 0b1..Triggers interrupt + */ +#define GLIKEY_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_INT_STATUS_SHIFT)) & GLIKEY_STATUS_INT_STATUS_MASK) + +#define GLIKEY_STATUS_LOCK_STATUS_MASK (0x2U) +#define GLIKEY_STATUS_LOCK_STATUS_SHIFT (1U) +/*! LOCK_STATUS - Provides the current lock status of indexes. + * 0b0..Current read index is not locked + * 0b1..Current read index is locked + */ +#define GLIKEY_STATUS_LOCK_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_LOCK_STATUS_SHIFT)) & GLIKEY_STATUS_LOCK_STATUS_MASK) + +#define GLIKEY_STATUS_ERROR_STATUS_MASK (0x1CU) +#define GLIKEY_STATUS_ERROR_STATUS_SHIFT (2U) +/*! ERROR_STATUS - Status of the Error + * 0b000..No error + * 0b001..FSM error has occurred + * 0b010..Write index out of the bound (OOB) error + * 0b011..Write index OOB and FSM error + * 0b100..Read index OOB error + * 0b110..Write index and read index OOB error + * 0b111..Read index OOB, write index OOB, and FSM error + */ +#define GLIKEY_STATUS_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_ERROR_STATUS_SHIFT)) & GLIKEY_STATUS_ERROR_STATUS_MASK) + +#define GLIKEY_STATUS_RESERVED18_MASK (0x7FFE0U) +#define GLIKEY_STATUS_RESERVED18_SHIFT (5U) +/*! RESERVED18 - Reserved for Future Use */ +#define GLIKEY_STATUS_RESERVED18(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_RESERVED18_SHIFT)) & GLIKEY_STATUS_RESERVED18_MASK) + +#define GLIKEY_STATUS_FSM_STATE_MASK (0xFFF80000U) +#define GLIKEY_STATUS_FSM_STATE_SHIFT (19U) +/*! FSM_STATE - Status of FSM */ +#define GLIKEY_STATUS_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_FSM_STATE_SHIFT)) & GLIKEY_STATUS_FSM_STATE_MASK) +/*! @} */ + +/*! @name VERSION - IP Version */ +/*! @{ */ + +#define GLIKEY_VERSION_RESERVED3_MASK (0xFU) +#define GLIKEY_VERSION_RESERVED3_SHIFT (0U) +/*! Reserved3 - Reserved */ +#define GLIKEY_VERSION_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED3_SHIFT)) & GLIKEY_VERSION_RESERVED3_MASK) + +#define GLIKEY_VERSION_RESERVED7_MASK (0xF0U) +#define GLIKEY_VERSION_RESERVED7_SHIFT (4U) +/*! Reserved7 - Reserved */ +#define GLIKEY_VERSION_RESERVED7(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED7_SHIFT)) & GLIKEY_VERSION_RESERVED7_MASK) + +#define GLIKEY_VERSION_RESERVED11_MASK (0xF00U) +#define GLIKEY_VERSION_RESERVED11_SHIFT (8U) +/*! Reserved11 - Reserved */ +#define GLIKEY_VERSION_RESERVED11(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED11_SHIFT)) & GLIKEY_VERSION_RESERVED11_MASK) + +#define GLIKEY_VERSION_RESERVED15_MASK (0xF000U) +#define GLIKEY_VERSION_RESERVED15_SHIFT (12U) +/*! Reserved15 - Reserved */ +#define GLIKEY_VERSION_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED15_SHIFT)) & GLIKEY_VERSION_RESERVED15_MASK) + +#define GLIKEY_VERSION_MILESTONE_MASK (0x30000U) +#define GLIKEY_VERSION_MILESTONE_SHIFT (16U) +/*! MILESTONE - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO. */ +#define GLIKEY_VERSION_MILESTONE(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_MILESTONE_SHIFT)) & GLIKEY_VERSION_MILESTONE_MASK) + +#define GLIKEY_VERSION_FSM_CONFIG_MASK (0x40000U) +#define GLIKEY_VERSION_FSM_CONFIG_SHIFT (18U) +/*! FSM_CONFIG - 0:4 step, 1:8 step */ +#define GLIKEY_VERSION_FSM_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_FSM_CONFIG_SHIFT)) & GLIKEY_VERSION_FSM_CONFIG_MASK) + +#define GLIKEY_VERSION_INDEX_CONFIG_MASK (0x7F80000U) +#define GLIKEY_VERSION_INDEX_CONFIG_SHIFT (19U) +/*! INDEX_CONFIG - Configured number of addressable indexes */ +#define GLIKEY_VERSION_INDEX_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_INDEX_CONFIG_SHIFT)) & GLIKEY_VERSION_INDEX_CONFIG_MASK) + +#define GLIKEY_VERSION_RESERVED31_MASK (0xF8000000U) +#define GLIKEY_VERSION_RESERVED31_SHIFT (27U) +/*! Reserved31 - Reserved for Future Use */ +#define GLIKEY_VERSION_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED31_SHIFT)) & GLIKEY_VERSION_RESERVED31_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GLIKEY_Register_Masks */ + + +/*! + * @} + */ /* end of group GLIKEY_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_GLIKEY_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GPIO.h new file mode 100644 index 000000000..2cdbc3981 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_GPIO.h @@ -0,0 +1,2662 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for GPIO +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_GPIO.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for GPIO + * + * CMSIS Peripheral Access Layer for GPIO + */ + +#if !defined(PERI_GPIO_H_) +#define PERI_GPIO_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Size of Registers Arrays */ +#define GPIO_PDR_COUNT 32u +#define GPIO_ICR_COUNT 32u +#define GPIO_ISFR_COUNT 1u + +/** GPIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[56]; + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __IO uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __IO uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __IO uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint8_t PDR[GPIO_PDR_COUNT]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[GPIO_ICR_COUNT]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __IO uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __IO uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ + uint8_t RESERVED_2[24]; + __IO uint32_t ISFR[GPIO_ISFR_COUNT]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define GPIO_VERID_FEATURE_MASK (0xFFFFU) +#define GPIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented + */ +#define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK) + +#define GPIO_VERID_MINOR_MASK (0xFF0000U) +#define GPIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define GPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK) + +#define GPIO_VERID_MAJOR_MASK (0xFF000000U) +#define GPIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define GPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define GPIO_PARAM_IRQNUM_MASK (0xFU) +#define GPIO_PARAM_IRQNUM_SHIFT (0U) +/*! IRQNUM - Interrupt Number */ +#define GPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK) +/*! @} */ + +/*! @name PDOR - Port Data Output */ +/*! @{ */ + +#define GPIO_PDOR_PDO0_MASK (0x1U) +#define GPIO_PDOR_PDO0_SHIFT (0U) +/*! PDO0 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK) + +#define GPIO_PDOR_PDO1_MASK (0x2U) +#define GPIO_PDOR_PDO1_SHIFT (1U) +/*! PDO1 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK) + +#define GPIO_PDOR_PDO2_MASK (0x4U) +#define GPIO_PDOR_PDO2_SHIFT (2U) +/*! PDO2 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK) + +#define GPIO_PDOR_PDO3_MASK (0x8U) +#define GPIO_PDOR_PDO3_SHIFT (3U) +/*! PDO3 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK) + +#define GPIO_PDOR_PDO4_MASK (0x10U) +#define GPIO_PDOR_PDO4_SHIFT (4U) +/*! PDO4 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK) + +#define GPIO_PDOR_PDO5_MASK (0x20U) +#define GPIO_PDOR_PDO5_SHIFT (5U) +/*! PDO5 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK) + +#define GPIO_PDOR_PDO6_MASK (0x40U) +#define GPIO_PDOR_PDO6_SHIFT (6U) +/*! PDO6 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK) + +#define GPIO_PDOR_PDO7_MASK (0x80U) +#define GPIO_PDOR_PDO7_SHIFT (7U) +/*! PDO7 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK) + +#define GPIO_PDOR_PDO8_MASK (0x100U) +#define GPIO_PDOR_PDO8_SHIFT (8U) +/*! PDO8 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK) + +#define GPIO_PDOR_PDO9_MASK (0x200U) +#define GPIO_PDOR_PDO9_SHIFT (9U) +/*! PDO9 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK) + +#define GPIO_PDOR_PDO10_MASK (0x400U) +#define GPIO_PDOR_PDO10_SHIFT (10U) +/*! PDO10 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK) + +#define GPIO_PDOR_PDO11_MASK (0x800U) +#define GPIO_PDOR_PDO11_SHIFT (11U) +/*! PDO11 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK) + +#define GPIO_PDOR_PDO12_MASK (0x1000U) +#define GPIO_PDOR_PDO12_SHIFT (12U) +/*! PDO12 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK) + +#define GPIO_PDOR_PDO13_MASK (0x2000U) +#define GPIO_PDOR_PDO13_SHIFT (13U) +/*! PDO13 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK) + +#define GPIO_PDOR_PDO14_MASK (0x4000U) +#define GPIO_PDOR_PDO14_SHIFT (14U) +/*! PDO14 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK) + +#define GPIO_PDOR_PDO15_MASK (0x8000U) +#define GPIO_PDOR_PDO15_SHIFT (15U) +/*! PDO15 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK) + +#define GPIO_PDOR_PDO16_MASK (0x10000U) +#define GPIO_PDOR_PDO16_SHIFT (16U) +/*! PDO16 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK) + +#define GPIO_PDOR_PDO17_MASK (0x20000U) +#define GPIO_PDOR_PDO17_SHIFT (17U) +/*! PDO17 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK) + +#define GPIO_PDOR_PDO18_MASK (0x40000U) +#define GPIO_PDOR_PDO18_SHIFT (18U) +/*! PDO18 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK) + +#define GPIO_PDOR_PDO19_MASK (0x80000U) +#define GPIO_PDOR_PDO19_SHIFT (19U) +/*! PDO19 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK) + +#define GPIO_PDOR_PDO20_MASK (0x100000U) +#define GPIO_PDOR_PDO20_SHIFT (20U) +/*! PDO20 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK) + +#define GPIO_PDOR_PDO21_MASK (0x200000U) +#define GPIO_PDOR_PDO21_SHIFT (21U) +/*! PDO21 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK) + +#define GPIO_PDOR_PDO22_MASK (0x400000U) +#define GPIO_PDOR_PDO22_SHIFT (22U) +/*! PDO22 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK) + +#define GPIO_PDOR_PDO23_MASK (0x800000U) +#define GPIO_PDOR_PDO23_SHIFT (23U) +/*! PDO23 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK) + +#define GPIO_PDOR_PDO24_MASK (0x1000000U) +#define GPIO_PDOR_PDO24_SHIFT (24U) +/*! PDO24 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK) + +#define GPIO_PDOR_PDO25_MASK (0x2000000U) +#define GPIO_PDOR_PDO25_SHIFT (25U) +/*! PDO25 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK) + +#define GPIO_PDOR_PDO26_MASK (0x4000000U) +#define GPIO_PDOR_PDO26_SHIFT (26U) +/*! PDO26 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK) + +#define GPIO_PDOR_PDO27_MASK (0x8000000U) +#define GPIO_PDOR_PDO27_SHIFT (27U) +/*! PDO27 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK) + +#define GPIO_PDOR_PDO28_MASK (0x10000000U) +#define GPIO_PDOR_PDO28_SHIFT (28U) +/*! PDO28 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK) + +#define GPIO_PDOR_PDO29_MASK (0x20000000U) +#define GPIO_PDOR_PDO29_SHIFT (29U) +/*! PDO29 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK) + +#define GPIO_PDOR_PDO30_MASK (0x40000000U) +#define GPIO_PDOR_PDO30_SHIFT (30U) +/*! PDO30 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK) + +#define GPIO_PDOR_PDO31_MASK (0x80000000U) +#define GPIO_PDOR_PDO31_SHIFT (31U) +/*! PDO31 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK) +/*! @} */ + +/*! @name PSOR - Port Set Output */ +/*! @{ */ + +#define GPIO_PSOR_PTSO0_MASK (0x1U) +#define GPIO_PSOR_PTSO0_SHIFT (0U) +/*! PTSO0 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK) + +#define GPIO_PSOR_PTSO1_MASK (0x2U) +#define GPIO_PSOR_PTSO1_SHIFT (1U) +/*! PTSO1 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK) + +#define GPIO_PSOR_PTSO2_MASK (0x4U) +#define GPIO_PSOR_PTSO2_SHIFT (2U) +/*! PTSO2 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK) + +#define GPIO_PSOR_PTSO3_MASK (0x8U) +#define GPIO_PSOR_PTSO3_SHIFT (3U) +/*! PTSO3 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK) + +#define GPIO_PSOR_PTSO4_MASK (0x10U) +#define GPIO_PSOR_PTSO4_SHIFT (4U) +/*! PTSO4 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK) + +#define GPIO_PSOR_PTSO5_MASK (0x20U) +#define GPIO_PSOR_PTSO5_SHIFT (5U) +/*! PTSO5 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK) + +#define GPIO_PSOR_PTSO6_MASK (0x40U) +#define GPIO_PSOR_PTSO6_SHIFT (6U) +/*! PTSO6 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK) + +#define GPIO_PSOR_PTSO7_MASK (0x80U) +#define GPIO_PSOR_PTSO7_SHIFT (7U) +/*! PTSO7 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK) + +#define GPIO_PSOR_PTSO8_MASK (0x100U) +#define GPIO_PSOR_PTSO8_SHIFT (8U) +/*! PTSO8 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK) + +#define GPIO_PSOR_PTSO9_MASK (0x200U) +#define GPIO_PSOR_PTSO9_SHIFT (9U) +/*! PTSO9 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK) + +#define GPIO_PSOR_PTSO10_MASK (0x400U) +#define GPIO_PSOR_PTSO10_SHIFT (10U) +/*! PTSO10 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK) + +#define GPIO_PSOR_PTSO11_MASK (0x800U) +#define GPIO_PSOR_PTSO11_SHIFT (11U) +/*! PTSO11 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK) + +#define GPIO_PSOR_PTSO12_MASK (0x1000U) +#define GPIO_PSOR_PTSO12_SHIFT (12U) +/*! PTSO12 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK) + +#define GPIO_PSOR_PTSO13_MASK (0x2000U) +#define GPIO_PSOR_PTSO13_SHIFT (13U) +/*! PTSO13 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK) + +#define GPIO_PSOR_PTSO14_MASK (0x4000U) +#define GPIO_PSOR_PTSO14_SHIFT (14U) +/*! PTSO14 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK) + +#define GPIO_PSOR_PTSO15_MASK (0x8000U) +#define GPIO_PSOR_PTSO15_SHIFT (15U) +/*! PTSO15 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK) + +#define GPIO_PSOR_PTSO16_MASK (0x10000U) +#define GPIO_PSOR_PTSO16_SHIFT (16U) +/*! PTSO16 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK) + +#define GPIO_PSOR_PTSO17_MASK (0x20000U) +#define GPIO_PSOR_PTSO17_SHIFT (17U) +/*! PTSO17 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK) + +#define GPIO_PSOR_PTSO18_MASK (0x40000U) +#define GPIO_PSOR_PTSO18_SHIFT (18U) +/*! PTSO18 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK) + +#define GPIO_PSOR_PTSO19_MASK (0x80000U) +#define GPIO_PSOR_PTSO19_SHIFT (19U) +/*! PTSO19 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK) + +#define GPIO_PSOR_PTSO20_MASK (0x100000U) +#define GPIO_PSOR_PTSO20_SHIFT (20U) +/*! PTSO20 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK) + +#define GPIO_PSOR_PTSO21_MASK (0x200000U) +#define GPIO_PSOR_PTSO21_SHIFT (21U) +/*! PTSO21 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK) + +#define GPIO_PSOR_PTSO22_MASK (0x400000U) +#define GPIO_PSOR_PTSO22_SHIFT (22U) +/*! PTSO22 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK) + +#define GPIO_PSOR_PTSO23_MASK (0x800000U) +#define GPIO_PSOR_PTSO23_SHIFT (23U) +/*! PTSO23 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK) + +#define GPIO_PSOR_PTSO24_MASK (0x1000000U) +#define GPIO_PSOR_PTSO24_SHIFT (24U) +/*! PTSO24 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK) + +#define GPIO_PSOR_PTSO25_MASK (0x2000000U) +#define GPIO_PSOR_PTSO25_SHIFT (25U) +/*! PTSO25 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK) + +#define GPIO_PSOR_PTSO26_MASK (0x4000000U) +#define GPIO_PSOR_PTSO26_SHIFT (26U) +/*! PTSO26 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK) + +#define GPIO_PSOR_PTSO27_MASK (0x8000000U) +#define GPIO_PSOR_PTSO27_SHIFT (27U) +/*! PTSO27 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK) + +#define GPIO_PSOR_PTSO28_MASK (0x10000000U) +#define GPIO_PSOR_PTSO28_SHIFT (28U) +/*! PTSO28 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK) + +#define GPIO_PSOR_PTSO29_MASK (0x20000000U) +#define GPIO_PSOR_PTSO29_SHIFT (29U) +/*! PTSO29 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK) + +#define GPIO_PSOR_PTSO30_MASK (0x40000000U) +#define GPIO_PSOR_PTSO30_SHIFT (30U) +/*! PTSO30 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK) + +#define GPIO_PSOR_PTSO31_MASK (0x80000000U) +#define GPIO_PSOR_PTSO31_SHIFT (31U) +/*! PTSO31 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK) +/*! @} */ + +/*! @name PCOR - Port Clear Output */ +/*! @{ */ + +#define GPIO_PCOR_PTCO0_MASK (0x1U) +#define GPIO_PCOR_PTCO0_SHIFT (0U) +/*! PTCO0 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK) + +#define GPIO_PCOR_PTCO1_MASK (0x2U) +#define GPIO_PCOR_PTCO1_SHIFT (1U) +/*! PTCO1 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK) + +#define GPIO_PCOR_PTCO2_MASK (0x4U) +#define GPIO_PCOR_PTCO2_SHIFT (2U) +/*! PTCO2 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK) + +#define GPIO_PCOR_PTCO3_MASK (0x8U) +#define GPIO_PCOR_PTCO3_SHIFT (3U) +/*! PTCO3 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK) + +#define GPIO_PCOR_PTCO4_MASK (0x10U) +#define GPIO_PCOR_PTCO4_SHIFT (4U) +/*! PTCO4 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK) + +#define GPIO_PCOR_PTCO5_MASK (0x20U) +#define GPIO_PCOR_PTCO5_SHIFT (5U) +/*! PTCO5 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK) + +#define GPIO_PCOR_PTCO6_MASK (0x40U) +#define GPIO_PCOR_PTCO6_SHIFT (6U) +/*! PTCO6 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK) + +#define GPIO_PCOR_PTCO7_MASK (0x80U) +#define GPIO_PCOR_PTCO7_SHIFT (7U) +/*! PTCO7 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK) + +#define GPIO_PCOR_PTCO8_MASK (0x100U) +#define GPIO_PCOR_PTCO8_SHIFT (8U) +/*! PTCO8 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK) + +#define GPIO_PCOR_PTCO9_MASK (0x200U) +#define GPIO_PCOR_PTCO9_SHIFT (9U) +/*! PTCO9 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK) + +#define GPIO_PCOR_PTCO10_MASK (0x400U) +#define GPIO_PCOR_PTCO10_SHIFT (10U) +/*! PTCO10 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK) + +#define GPIO_PCOR_PTCO11_MASK (0x800U) +#define GPIO_PCOR_PTCO11_SHIFT (11U) +/*! PTCO11 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK) + +#define GPIO_PCOR_PTCO12_MASK (0x1000U) +#define GPIO_PCOR_PTCO12_SHIFT (12U) +/*! PTCO12 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK) + +#define GPIO_PCOR_PTCO13_MASK (0x2000U) +#define GPIO_PCOR_PTCO13_SHIFT (13U) +/*! PTCO13 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK) + +#define GPIO_PCOR_PTCO14_MASK (0x4000U) +#define GPIO_PCOR_PTCO14_SHIFT (14U) +/*! PTCO14 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK) + +#define GPIO_PCOR_PTCO15_MASK (0x8000U) +#define GPIO_PCOR_PTCO15_SHIFT (15U) +/*! PTCO15 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK) + +#define GPIO_PCOR_PTCO16_MASK (0x10000U) +#define GPIO_PCOR_PTCO16_SHIFT (16U) +/*! PTCO16 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK) + +#define GPIO_PCOR_PTCO17_MASK (0x20000U) +#define GPIO_PCOR_PTCO17_SHIFT (17U) +/*! PTCO17 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK) + +#define GPIO_PCOR_PTCO18_MASK (0x40000U) +#define GPIO_PCOR_PTCO18_SHIFT (18U) +/*! PTCO18 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK) + +#define GPIO_PCOR_PTCO19_MASK (0x80000U) +#define GPIO_PCOR_PTCO19_SHIFT (19U) +/*! PTCO19 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK) + +#define GPIO_PCOR_PTCO20_MASK (0x100000U) +#define GPIO_PCOR_PTCO20_SHIFT (20U) +/*! PTCO20 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK) + +#define GPIO_PCOR_PTCO21_MASK (0x200000U) +#define GPIO_PCOR_PTCO21_SHIFT (21U) +/*! PTCO21 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK) + +#define GPIO_PCOR_PTCO22_MASK (0x400000U) +#define GPIO_PCOR_PTCO22_SHIFT (22U) +/*! PTCO22 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK) + +#define GPIO_PCOR_PTCO23_MASK (0x800000U) +#define GPIO_PCOR_PTCO23_SHIFT (23U) +/*! PTCO23 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK) + +#define GPIO_PCOR_PTCO24_MASK (0x1000000U) +#define GPIO_PCOR_PTCO24_SHIFT (24U) +/*! PTCO24 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK) + +#define GPIO_PCOR_PTCO25_MASK (0x2000000U) +#define GPIO_PCOR_PTCO25_SHIFT (25U) +/*! PTCO25 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK) + +#define GPIO_PCOR_PTCO26_MASK (0x4000000U) +#define GPIO_PCOR_PTCO26_SHIFT (26U) +/*! PTCO26 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK) + +#define GPIO_PCOR_PTCO27_MASK (0x8000000U) +#define GPIO_PCOR_PTCO27_SHIFT (27U) +/*! PTCO27 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK) + +#define GPIO_PCOR_PTCO28_MASK (0x10000000U) +#define GPIO_PCOR_PTCO28_SHIFT (28U) +/*! PTCO28 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK) + +#define GPIO_PCOR_PTCO29_MASK (0x20000000U) +#define GPIO_PCOR_PTCO29_SHIFT (29U) +/*! PTCO29 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK) + +#define GPIO_PCOR_PTCO30_MASK (0x40000000U) +#define GPIO_PCOR_PTCO30_SHIFT (30U) +/*! PTCO30 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK) + +#define GPIO_PCOR_PTCO31_MASK (0x80000000U) +#define GPIO_PCOR_PTCO31_SHIFT (31U) +/*! PTCO31 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK) +/*! @} */ + +/*! @name PTOR - Port Toggle Output */ +/*! @{ */ + +#define GPIO_PTOR_PTTO0_MASK (0x1U) +#define GPIO_PTOR_PTTO0_SHIFT (0U) +/*! PTTO0 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK) + +#define GPIO_PTOR_PTTO1_MASK (0x2U) +#define GPIO_PTOR_PTTO1_SHIFT (1U) +/*! PTTO1 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK) + +#define GPIO_PTOR_PTTO2_MASK (0x4U) +#define GPIO_PTOR_PTTO2_SHIFT (2U) +/*! PTTO2 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK) + +#define GPIO_PTOR_PTTO3_MASK (0x8U) +#define GPIO_PTOR_PTTO3_SHIFT (3U) +/*! PTTO3 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK) + +#define GPIO_PTOR_PTTO4_MASK (0x10U) +#define GPIO_PTOR_PTTO4_SHIFT (4U) +/*! PTTO4 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK) + +#define GPIO_PTOR_PTTO5_MASK (0x20U) +#define GPIO_PTOR_PTTO5_SHIFT (5U) +/*! PTTO5 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK) + +#define GPIO_PTOR_PTTO6_MASK (0x40U) +#define GPIO_PTOR_PTTO6_SHIFT (6U) +/*! PTTO6 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK) + +#define GPIO_PTOR_PTTO7_MASK (0x80U) +#define GPIO_PTOR_PTTO7_SHIFT (7U) +/*! PTTO7 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK) + +#define GPIO_PTOR_PTTO8_MASK (0x100U) +#define GPIO_PTOR_PTTO8_SHIFT (8U) +/*! PTTO8 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK) + +#define GPIO_PTOR_PTTO9_MASK (0x200U) +#define GPIO_PTOR_PTTO9_SHIFT (9U) +/*! PTTO9 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK) + +#define GPIO_PTOR_PTTO10_MASK (0x400U) +#define GPIO_PTOR_PTTO10_SHIFT (10U) +/*! PTTO10 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK) + +#define GPIO_PTOR_PTTO11_MASK (0x800U) +#define GPIO_PTOR_PTTO11_SHIFT (11U) +/*! PTTO11 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK) + +#define GPIO_PTOR_PTTO12_MASK (0x1000U) +#define GPIO_PTOR_PTTO12_SHIFT (12U) +/*! PTTO12 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK) + +#define GPIO_PTOR_PTTO13_MASK (0x2000U) +#define GPIO_PTOR_PTTO13_SHIFT (13U) +/*! PTTO13 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK) + +#define GPIO_PTOR_PTTO14_MASK (0x4000U) +#define GPIO_PTOR_PTTO14_SHIFT (14U) +/*! PTTO14 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK) + +#define GPIO_PTOR_PTTO15_MASK (0x8000U) +#define GPIO_PTOR_PTTO15_SHIFT (15U) +/*! PTTO15 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK) + +#define GPIO_PTOR_PTTO16_MASK (0x10000U) +#define GPIO_PTOR_PTTO16_SHIFT (16U) +/*! PTTO16 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK) + +#define GPIO_PTOR_PTTO17_MASK (0x20000U) +#define GPIO_PTOR_PTTO17_SHIFT (17U) +/*! PTTO17 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK) + +#define GPIO_PTOR_PTTO18_MASK (0x40000U) +#define GPIO_PTOR_PTTO18_SHIFT (18U) +/*! PTTO18 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK) + +#define GPIO_PTOR_PTTO19_MASK (0x80000U) +#define GPIO_PTOR_PTTO19_SHIFT (19U) +/*! PTTO19 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK) + +#define GPIO_PTOR_PTTO20_MASK (0x100000U) +#define GPIO_PTOR_PTTO20_SHIFT (20U) +/*! PTTO20 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK) + +#define GPIO_PTOR_PTTO21_MASK (0x200000U) +#define GPIO_PTOR_PTTO21_SHIFT (21U) +/*! PTTO21 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK) + +#define GPIO_PTOR_PTTO22_MASK (0x400000U) +#define GPIO_PTOR_PTTO22_SHIFT (22U) +/*! PTTO22 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK) + +#define GPIO_PTOR_PTTO23_MASK (0x800000U) +#define GPIO_PTOR_PTTO23_SHIFT (23U) +/*! PTTO23 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK) + +#define GPIO_PTOR_PTTO24_MASK (0x1000000U) +#define GPIO_PTOR_PTTO24_SHIFT (24U) +/*! PTTO24 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK) + +#define GPIO_PTOR_PTTO25_MASK (0x2000000U) +#define GPIO_PTOR_PTTO25_SHIFT (25U) +/*! PTTO25 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK) + +#define GPIO_PTOR_PTTO26_MASK (0x4000000U) +#define GPIO_PTOR_PTTO26_SHIFT (26U) +/*! PTTO26 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK) + +#define GPIO_PTOR_PTTO27_MASK (0x8000000U) +#define GPIO_PTOR_PTTO27_SHIFT (27U) +/*! PTTO27 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK) + +#define GPIO_PTOR_PTTO28_MASK (0x10000000U) +#define GPIO_PTOR_PTTO28_SHIFT (28U) +/*! PTTO28 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK) + +#define GPIO_PTOR_PTTO29_MASK (0x20000000U) +#define GPIO_PTOR_PTTO29_SHIFT (29U) +/*! PTTO29 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK) + +#define GPIO_PTOR_PTTO30_MASK (0x40000000U) +#define GPIO_PTOR_PTTO30_SHIFT (30U) +/*! PTTO30 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK) + +#define GPIO_PTOR_PTTO31_MASK (0x80000000U) +#define GPIO_PTOR_PTTO31_SHIFT (31U) +/*! PTTO31 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK) +/*! @} */ + +/*! @name PDIR - Port Data Input */ +/*! @{ */ + +#define GPIO_PDIR_PDI0_MASK (0x1U) +#define GPIO_PDIR_PDI0_SHIFT (0U) +/*! PDI0 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK) + +#define GPIO_PDIR_PDI1_MASK (0x2U) +#define GPIO_PDIR_PDI1_SHIFT (1U) +/*! PDI1 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK) + +#define GPIO_PDIR_PDI2_MASK (0x4U) +#define GPIO_PDIR_PDI2_SHIFT (2U) +/*! PDI2 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK) + +#define GPIO_PDIR_PDI3_MASK (0x8U) +#define GPIO_PDIR_PDI3_SHIFT (3U) +/*! PDI3 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK) + +#define GPIO_PDIR_PDI4_MASK (0x10U) +#define GPIO_PDIR_PDI4_SHIFT (4U) +/*! PDI4 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK) + +#define GPIO_PDIR_PDI5_MASK (0x20U) +#define GPIO_PDIR_PDI5_SHIFT (5U) +/*! PDI5 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK) + +#define GPIO_PDIR_PDI6_MASK (0x40U) +#define GPIO_PDIR_PDI6_SHIFT (6U) +/*! PDI6 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK) + +#define GPIO_PDIR_PDI7_MASK (0x80U) +#define GPIO_PDIR_PDI7_SHIFT (7U) +/*! PDI7 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK) + +#define GPIO_PDIR_PDI8_MASK (0x100U) +#define GPIO_PDIR_PDI8_SHIFT (8U) +/*! PDI8 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK) + +#define GPIO_PDIR_PDI9_MASK (0x200U) +#define GPIO_PDIR_PDI9_SHIFT (9U) +/*! PDI9 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK) + +#define GPIO_PDIR_PDI10_MASK (0x400U) +#define GPIO_PDIR_PDI10_SHIFT (10U) +/*! PDI10 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK) + +#define GPIO_PDIR_PDI11_MASK (0x800U) +#define GPIO_PDIR_PDI11_SHIFT (11U) +/*! PDI11 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK) + +#define GPIO_PDIR_PDI12_MASK (0x1000U) +#define GPIO_PDIR_PDI12_SHIFT (12U) +/*! PDI12 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK) + +#define GPIO_PDIR_PDI13_MASK (0x2000U) +#define GPIO_PDIR_PDI13_SHIFT (13U) +/*! PDI13 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK) + +#define GPIO_PDIR_PDI14_MASK (0x4000U) +#define GPIO_PDIR_PDI14_SHIFT (14U) +/*! PDI14 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK) + +#define GPIO_PDIR_PDI15_MASK (0x8000U) +#define GPIO_PDIR_PDI15_SHIFT (15U) +/*! PDI15 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK) + +#define GPIO_PDIR_PDI16_MASK (0x10000U) +#define GPIO_PDIR_PDI16_SHIFT (16U) +/*! PDI16 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK) + +#define GPIO_PDIR_PDI17_MASK (0x20000U) +#define GPIO_PDIR_PDI17_SHIFT (17U) +/*! PDI17 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK) + +#define GPIO_PDIR_PDI18_MASK (0x40000U) +#define GPIO_PDIR_PDI18_SHIFT (18U) +/*! PDI18 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK) + +#define GPIO_PDIR_PDI19_MASK (0x80000U) +#define GPIO_PDIR_PDI19_SHIFT (19U) +/*! PDI19 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK) + +#define GPIO_PDIR_PDI20_MASK (0x100000U) +#define GPIO_PDIR_PDI20_SHIFT (20U) +/*! PDI20 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK) + +#define GPIO_PDIR_PDI21_MASK (0x200000U) +#define GPIO_PDIR_PDI21_SHIFT (21U) +/*! PDI21 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK) + +#define GPIO_PDIR_PDI22_MASK (0x400000U) +#define GPIO_PDIR_PDI22_SHIFT (22U) +/*! PDI22 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK) + +#define GPIO_PDIR_PDI23_MASK (0x800000U) +#define GPIO_PDIR_PDI23_SHIFT (23U) +/*! PDI23 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK) + +#define GPIO_PDIR_PDI24_MASK (0x1000000U) +#define GPIO_PDIR_PDI24_SHIFT (24U) +/*! PDI24 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK) + +#define GPIO_PDIR_PDI25_MASK (0x2000000U) +#define GPIO_PDIR_PDI25_SHIFT (25U) +/*! PDI25 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK) + +#define GPIO_PDIR_PDI26_MASK (0x4000000U) +#define GPIO_PDIR_PDI26_SHIFT (26U) +/*! PDI26 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK) + +#define GPIO_PDIR_PDI27_MASK (0x8000000U) +#define GPIO_PDIR_PDI27_SHIFT (27U) +/*! PDI27 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK) + +#define GPIO_PDIR_PDI28_MASK (0x10000000U) +#define GPIO_PDIR_PDI28_SHIFT (28U) +/*! PDI28 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK) + +#define GPIO_PDIR_PDI29_MASK (0x20000000U) +#define GPIO_PDIR_PDI29_SHIFT (29U) +/*! PDI29 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK) + +#define GPIO_PDIR_PDI30_MASK (0x40000000U) +#define GPIO_PDIR_PDI30_SHIFT (30U) +/*! PDI30 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK) + +#define GPIO_PDIR_PDI31_MASK (0x80000000U) +#define GPIO_PDIR_PDI31_SHIFT (31U) +/*! PDI31 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK) +/*! @} */ + +/*! @name PDDR - Port Data Direction */ +/*! @{ */ + +#define GPIO_PDDR_PDD0_MASK (0x1U) +#define GPIO_PDDR_PDD0_SHIFT (0U) +/*! PDD0 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK) + +#define GPIO_PDDR_PDD1_MASK (0x2U) +#define GPIO_PDDR_PDD1_SHIFT (1U) +/*! PDD1 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK) + +#define GPIO_PDDR_PDD2_MASK (0x4U) +#define GPIO_PDDR_PDD2_SHIFT (2U) +/*! PDD2 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK) + +#define GPIO_PDDR_PDD3_MASK (0x8U) +#define GPIO_PDDR_PDD3_SHIFT (3U) +/*! PDD3 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK) + +#define GPIO_PDDR_PDD4_MASK (0x10U) +#define GPIO_PDDR_PDD4_SHIFT (4U) +/*! PDD4 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK) + +#define GPIO_PDDR_PDD5_MASK (0x20U) +#define GPIO_PDDR_PDD5_SHIFT (5U) +/*! PDD5 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK) + +#define GPIO_PDDR_PDD6_MASK (0x40U) +#define GPIO_PDDR_PDD6_SHIFT (6U) +/*! PDD6 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK) + +#define GPIO_PDDR_PDD7_MASK (0x80U) +#define GPIO_PDDR_PDD7_SHIFT (7U) +/*! PDD7 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK) + +#define GPIO_PDDR_PDD8_MASK (0x100U) +#define GPIO_PDDR_PDD8_SHIFT (8U) +/*! PDD8 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK) + +#define GPIO_PDDR_PDD9_MASK (0x200U) +#define GPIO_PDDR_PDD9_SHIFT (9U) +/*! PDD9 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK) + +#define GPIO_PDDR_PDD10_MASK (0x400U) +#define GPIO_PDDR_PDD10_SHIFT (10U) +/*! PDD10 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK) + +#define GPIO_PDDR_PDD11_MASK (0x800U) +#define GPIO_PDDR_PDD11_SHIFT (11U) +/*! PDD11 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK) + +#define GPIO_PDDR_PDD12_MASK (0x1000U) +#define GPIO_PDDR_PDD12_SHIFT (12U) +/*! PDD12 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK) + +#define GPIO_PDDR_PDD13_MASK (0x2000U) +#define GPIO_PDDR_PDD13_SHIFT (13U) +/*! PDD13 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK) + +#define GPIO_PDDR_PDD14_MASK (0x4000U) +#define GPIO_PDDR_PDD14_SHIFT (14U) +/*! PDD14 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK) + +#define GPIO_PDDR_PDD15_MASK (0x8000U) +#define GPIO_PDDR_PDD15_SHIFT (15U) +/*! PDD15 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK) + +#define GPIO_PDDR_PDD16_MASK (0x10000U) +#define GPIO_PDDR_PDD16_SHIFT (16U) +/*! PDD16 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK) + +#define GPIO_PDDR_PDD17_MASK (0x20000U) +#define GPIO_PDDR_PDD17_SHIFT (17U) +/*! PDD17 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK) + +#define GPIO_PDDR_PDD18_MASK (0x40000U) +#define GPIO_PDDR_PDD18_SHIFT (18U) +/*! PDD18 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK) + +#define GPIO_PDDR_PDD19_MASK (0x80000U) +#define GPIO_PDDR_PDD19_SHIFT (19U) +/*! PDD19 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK) + +#define GPIO_PDDR_PDD20_MASK (0x100000U) +#define GPIO_PDDR_PDD20_SHIFT (20U) +/*! PDD20 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK) + +#define GPIO_PDDR_PDD21_MASK (0x200000U) +#define GPIO_PDDR_PDD21_SHIFT (21U) +/*! PDD21 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK) + +#define GPIO_PDDR_PDD22_MASK (0x400000U) +#define GPIO_PDDR_PDD22_SHIFT (22U) +/*! PDD22 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK) + +#define GPIO_PDDR_PDD23_MASK (0x800000U) +#define GPIO_PDDR_PDD23_SHIFT (23U) +/*! PDD23 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK) + +#define GPIO_PDDR_PDD24_MASK (0x1000000U) +#define GPIO_PDDR_PDD24_SHIFT (24U) +/*! PDD24 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK) + +#define GPIO_PDDR_PDD25_MASK (0x2000000U) +#define GPIO_PDDR_PDD25_SHIFT (25U) +/*! PDD25 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK) + +#define GPIO_PDDR_PDD26_MASK (0x4000000U) +#define GPIO_PDDR_PDD26_SHIFT (26U) +/*! PDD26 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK) + +#define GPIO_PDDR_PDD27_MASK (0x8000000U) +#define GPIO_PDDR_PDD27_SHIFT (27U) +/*! PDD27 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK) + +#define GPIO_PDDR_PDD28_MASK (0x10000000U) +#define GPIO_PDDR_PDD28_SHIFT (28U) +/*! PDD28 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK) + +#define GPIO_PDDR_PDD29_MASK (0x20000000U) +#define GPIO_PDDR_PDD29_SHIFT (29U) +/*! PDD29 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK) + +#define GPIO_PDDR_PDD30_MASK (0x40000000U) +#define GPIO_PDDR_PDD30_SHIFT (30U) +/*! PDD30 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK) + +#define GPIO_PDDR_PDD31_MASK (0x80000000U) +#define GPIO_PDDR_PDD31_SHIFT (31U) +/*! PDD31 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK) +/*! @} */ + +/*! @name PIDR - Port Input Disable */ +/*! @{ */ + +#define GPIO_PIDR_PID0_MASK (0x1U) +#define GPIO_PIDR_PID0_SHIFT (0U) +/*! PID0 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK) + +#define GPIO_PIDR_PID1_MASK (0x2U) +#define GPIO_PIDR_PID1_SHIFT (1U) +/*! PID1 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK) + +#define GPIO_PIDR_PID2_MASK (0x4U) +#define GPIO_PIDR_PID2_SHIFT (2U) +/*! PID2 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK) + +#define GPIO_PIDR_PID3_MASK (0x8U) +#define GPIO_PIDR_PID3_SHIFT (3U) +/*! PID3 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK) + +#define GPIO_PIDR_PID4_MASK (0x10U) +#define GPIO_PIDR_PID4_SHIFT (4U) +/*! PID4 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK) + +#define GPIO_PIDR_PID5_MASK (0x20U) +#define GPIO_PIDR_PID5_SHIFT (5U) +/*! PID5 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK) + +#define GPIO_PIDR_PID6_MASK (0x40U) +#define GPIO_PIDR_PID6_SHIFT (6U) +/*! PID6 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK) + +#define GPIO_PIDR_PID7_MASK (0x80U) +#define GPIO_PIDR_PID7_SHIFT (7U) +/*! PID7 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK) + +#define GPIO_PIDR_PID8_MASK (0x100U) +#define GPIO_PIDR_PID8_SHIFT (8U) +/*! PID8 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK) + +#define GPIO_PIDR_PID9_MASK (0x200U) +#define GPIO_PIDR_PID9_SHIFT (9U) +/*! PID9 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK) + +#define GPIO_PIDR_PID10_MASK (0x400U) +#define GPIO_PIDR_PID10_SHIFT (10U) +/*! PID10 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK) + +#define GPIO_PIDR_PID11_MASK (0x800U) +#define GPIO_PIDR_PID11_SHIFT (11U) +/*! PID11 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK) + +#define GPIO_PIDR_PID12_MASK (0x1000U) +#define GPIO_PIDR_PID12_SHIFT (12U) +/*! PID12 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK) + +#define GPIO_PIDR_PID13_MASK (0x2000U) +#define GPIO_PIDR_PID13_SHIFT (13U) +/*! PID13 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK) + +#define GPIO_PIDR_PID14_MASK (0x4000U) +#define GPIO_PIDR_PID14_SHIFT (14U) +/*! PID14 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK) + +#define GPIO_PIDR_PID15_MASK (0x8000U) +#define GPIO_PIDR_PID15_SHIFT (15U) +/*! PID15 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK) + +#define GPIO_PIDR_PID16_MASK (0x10000U) +#define GPIO_PIDR_PID16_SHIFT (16U) +/*! PID16 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK) + +#define GPIO_PIDR_PID17_MASK (0x20000U) +#define GPIO_PIDR_PID17_SHIFT (17U) +/*! PID17 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK) + +#define GPIO_PIDR_PID18_MASK (0x40000U) +#define GPIO_PIDR_PID18_SHIFT (18U) +/*! PID18 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK) + +#define GPIO_PIDR_PID19_MASK (0x80000U) +#define GPIO_PIDR_PID19_SHIFT (19U) +/*! PID19 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK) + +#define GPIO_PIDR_PID20_MASK (0x100000U) +#define GPIO_PIDR_PID20_SHIFT (20U) +/*! PID20 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK) + +#define GPIO_PIDR_PID21_MASK (0x200000U) +#define GPIO_PIDR_PID21_SHIFT (21U) +/*! PID21 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK) + +#define GPIO_PIDR_PID22_MASK (0x400000U) +#define GPIO_PIDR_PID22_SHIFT (22U) +/*! PID22 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK) + +#define GPIO_PIDR_PID23_MASK (0x800000U) +#define GPIO_PIDR_PID23_SHIFT (23U) +/*! PID23 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK) + +#define GPIO_PIDR_PID24_MASK (0x1000000U) +#define GPIO_PIDR_PID24_SHIFT (24U) +/*! PID24 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK) + +#define GPIO_PIDR_PID25_MASK (0x2000000U) +#define GPIO_PIDR_PID25_SHIFT (25U) +/*! PID25 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK) + +#define GPIO_PIDR_PID26_MASK (0x4000000U) +#define GPIO_PIDR_PID26_SHIFT (26U) +/*! PID26 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK) + +#define GPIO_PIDR_PID27_MASK (0x8000000U) +#define GPIO_PIDR_PID27_SHIFT (27U) +/*! PID27 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK) + +#define GPIO_PIDR_PID28_MASK (0x10000000U) +#define GPIO_PIDR_PID28_SHIFT (28U) +/*! PID28 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK) + +#define GPIO_PIDR_PID29_MASK (0x20000000U) +#define GPIO_PIDR_PID29_SHIFT (29U) +/*! PID29 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK) + +#define GPIO_PIDR_PID30_MASK (0x40000000U) +#define GPIO_PIDR_PID30_SHIFT (30U) +/*! PID30 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK) + +#define GPIO_PIDR_PID31_MASK (0x80000000U) +#define GPIO_PIDR_PID31_SHIFT (31U) +/*! PID31 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK) +/*! @} */ + +/*! @name PDR - Pin Data */ +/*! @{ */ + +#define GPIO_PDR_PD_MASK (0x1U) +#define GPIO_PDR_PD_SHIFT (0U) +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one + */ +#define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK) +/*! @} */ + +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ +/*! @{ */ + +#define GPIO_ICR_IRQC_MASK (0xF0000U) +#define GPIO_ICR_IRQC_SHIFT (16U) +/*! IRQC - Interrupt Configuration + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers + * to generate the output trigger for use by other peripherals) + * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other + * enabled triggers to generate the output trigger for use by other peripherals) + * 0b1111..Reserved + */ +#define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK) + +#define GPIO_ICR_ISF_MASK (0x1000000U) +#define GPIO_ICR_ISF_SHIFT (24U) +/*! ISF - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK) +/*! @} */ + +/*! @name GICLR - Global Interrupt Control Low */ +/*! @{ */ + +#define GPIO_GICLR_GIWE0_MASK (0x1U) +#define GPIO_GICLR_GIWE0_SHIFT (0U) +/*! GIWE0 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK) + +#define GPIO_GICLR_GIWE1_MASK (0x2U) +#define GPIO_GICLR_GIWE1_SHIFT (1U) +/*! GIWE1 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK) + +#define GPIO_GICLR_GIWE2_MASK (0x4U) +#define GPIO_GICLR_GIWE2_SHIFT (2U) +/*! GIWE2 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK) + +#define GPIO_GICLR_GIWE3_MASK (0x8U) +#define GPIO_GICLR_GIWE3_SHIFT (3U) +/*! GIWE3 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK) + +#define GPIO_GICLR_GIWE4_MASK (0x10U) +#define GPIO_GICLR_GIWE4_SHIFT (4U) +/*! GIWE4 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK) + +#define GPIO_GICLR_GIWE5_MASK (0x20U) +#define GPIO_GICLR_GIWE5_SHIFT (5U) +/*! GIWE5 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK) + +#define GPIO_GICLR_GIWE6_MASK (0x40U) +#define GPIO_GICLR_GIWE6_SHIFT (6U) +/*! GIWE6 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK) + +#define GPIO_GICLR_GIWE7_MASK (0x80U) +#define GPIO_GICLR_GIWE7_SHIFT (7U) +/*! GIWE7 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK) + +#define GPIO_GICLR_GIWE8_MASK (0x100U) +#define GPIO_GICLR_GIWE8_SHIFT (8U) +/*! GIWE8 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK) + +#define GPIO_GICLR_GIWE9_MASK (0x200U) +#define GPIO_GICLR_GIWE9_SHIFT (9U) +/*! GIWE9 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK) + +#define GPIO_GICLR_GIWE10_MASK (0x400U) +#define GPIO_GICLR_GIWE10_SHIFT (10U) +/*! GIWE10 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK) + +#define GPIO_GICLR_GIWE11_MASK (0x800U) +#define GPIO_GICLR_GIWE11_SHIFT (11U) +/*! GIWE11 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK) + +#define GPIO_GICLR_GIWE12_MASK (0x1000U) +#define GPIO_GICLR_GIWE12_SHIFT (12U) +/*! GIWE12 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK) + +#define GPIO_GICLR_GIWE13_MASK (0x2000U) +#define GPIO_GICLR_GIWE13_SHIFT (13U) +/*! GIWE13 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK) + +#define GPIO_GICLR_GIWE14_MASK (0x4000U) +#define GPIO_GICLR_GIWE14_SHIFT (14U) +/*! GIWE14 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK) + +#define GPIO_GICLR_GIWE15_MASK (0x8000U) +#define GPIO_GICLR_GIWE15_SHIFT (15U) +/*! GIWE15 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK) + +#define GPIO_GICLR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICLR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK) +/*! @} */ + +/*! @name GICHR - Global Interrupt Control High */ +/*! @{ */ + +#define GPIO_GICHR_GIWE16_MASK (0x1U) +#define GPIO_GICHR_GIWE16_SHIFT (0U) +/*! GIWE16 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK) + +#define GPIO_GICHR_GIWE17_MASK (0x2U) +#define GPIO_GICHR_GIWE17_SHIFT (1U) +/*! GIWE17 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK) + +#define GPIO_GICHR_GIWE18_MASK (0x4U) +#define GPIO_GICHR_GIWE18_SHIFT (2U) +/*! GIWE18 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK) + +#define GPIO_GICHR_GIWE19_MASK (0x8U) +#define GPIO_GICHR_GIWE19_SHIFT (3U) +/*! GIWE19 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK) + +#define GPIO_GICHR_GIWE20_MASK (0x10U) +#define GPIO_GICHR_GIWE20_SHIFT (4U) +/*! GIWE20 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK) + +#define GPIO_GICHR_GIWE21_MASK (0x20U) +#define GPIO_GICHR_GIWE21_SHIFT (5U) +/*! GIWE21 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK) + +#define GPIO_GICHR_GIWE22_MASK (0x40U) +#define GPIO_GICHR_GIWE22_SHIFT (6U) +/*! GIWE22 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK) + +#define GPIO_GICHR_GIWE23_MASK (0x80U) +#define GPIO_GICHR_GIWE23_SHIFT (7U) +/*! GIWE23 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK) + +#define GPIO_GICHR_GIWE24_MASK (0x100U) +#define GPIO_GICHR_GIWE24_SHIFT (8U) +/*! GIWE24 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK) + +#define GPIO_GICHR_GIWE25_MASK (0x200U) +#define GPIO_GICHR_GIWE25_SHIFT (9U) +/*! GIWE25 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK) + +#define GPIO_GICHR_GIWE26_MASK (0x400U) +#define GPIO_GICHR_GIWE26_SHIFT (10U) +/*! GIWE26 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK) + +#define GPIO_GICHR_GIWE27_MASK (0x800U) +#define GPIO_GICHR_GIWE27_SHIFT (11U) +/*! GIWE27 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK) + +#define GPIO_GICHR_GIWE28_MASK (0x1000U) +#define GPIO_GICHR_GIWE28_SHIFT (12U) +/*! GIWE28 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK) + +#define GPIO_GICHR_GIWE29_MASK (0x2000U) +#define GPIO_GICHR_GIWE29_SHIFT (13U) +/*! GIWE29 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK) + +#define GPIO_GICHR_GIWE30_MASK (0x4000U) +#define GPIO_GICHR_GIWE30_SHIFT (14U) +/*! GIWE30 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK) + +#define GPIO_GICHR_GIWE31_MASK (0x8000U) +#define GPIO_GICHR_GIWE31_SHIFT (15U) +/*! GIWE31 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK) + +#define GPIO_GICHR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICHR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK) +/*! @} */ + +/*! @name ISFR - Interrupt Status Flag */ +/*! @{ */ + +#define GPIO_ISFR_ISF0_MASK (0x1U) +#define GPIO_ISFR_ISF0_SHIFT (0U) +/*! ISF0 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK) + +#define GPIO_ISFR_ISF1_MASK (0x2U) +#define GPIO_ISFR_ISF1_SHIFT (1U) +/*! ISF1 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK) + +#define GPIO_ISFR_ISF2_MASK (0x4U) +#define GPIO_ISFR_ISF2_SHIFT (2U) +/*! ISF2 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK) + +#define GPIO_ISFR_ISF3_MASK (0x8U) +#define GPIO_ISFR_ISF3_SHIFT (3U) +/*! ISF3 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK) + +#define GPIO_ISFR_ISF4_MASK (0x10U) +#define GPIO_ISFR_ISF4_SHIFT (4U) +/*! ISF4 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK) + +#define GPIO_ISFR_ISF5_MASK (0x20U) +#define GPIO_ISFR_ISF5_SHIFT (5U) +/*! ISF5 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK) + +#define GPIO_ISFR_ISF6_MASK (0x40U) +#define GPIO_ISFR_ISF6_SHIFT (6U) +/*! ISF6 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK) + +#define GPIO_ISFR_ISF7_MASK (0x80U) +#define GPIO_ISFR_ISF7_SHIFT (7U) +/*! ISF7 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK) + +#define GPIO_ISFR_ISF8_MASK (0x100U) +#define GPIO_ISFR_ISF8_SHIFT (8U) +/*! ISF8 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK) + +#define GPIO_ISFR_ISF9_MASK (0x200U) +#define GPIO_ISFR_ISF9_SHIFT (9U) +/*! ISF9 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK) + +#define GPIO_ISFR_ISF10_MASK (0x400U) +#define GPIO_ISFR_ISF10_SHIFT (10U) +/*! ISF10 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK) + +#define GPIO_ISFR_ISF11_MASK (0x800U) +#define GPIO_ISFR_ISF11_SHIFT (11U) +/*! ISF11 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK) + +#define GPIO_ISFR_ISF12_MASK (0x1000U) +#define GPIO_ISFR_ISF12_SHIFT (12U) +/*! ISF12 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK) + +#define GPIO_ISFR_ISF13_MASK (0x2000U) +#define GPIO_ISFR_ISF13_SHIFT (13U) +/*! ISF13 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK) + +#define GPIO_ISFR_ISF14_MASK (0x4000U) +#define GPIO_ISFR_ISF14_SHIFT (14U) +/*! ISF14 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK) + +#define GPIO_ISFR_ISF15_MASK (0x8000U) +#define GPIO_ISFR_ISF15_SHIFT (15U) +/*! ISF15 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK) + +#define GPIO_ISFR_ISF16_MASK (0x10000U) +#define GPIO_ISFR_ISF16_SHIFT (16U) +/*! ISF16 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK) + +#define GPIO_ISFR_ISF17_MASK (0x20000U) +#define GPIO_ISFR_ISF17_SHIFT (17U) +/*! ISF17 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK) + +#define GPIO_ISFR_ISF18_MASK (0x40000U) +#define GPIO_ISFR_ISF18_SHIFT (18U) +/*! ISF18 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK) + +#define GPIO_ISFR_ISF19_MASK (0x80000U) +#define GPIO_ISFR_ISF19_SHIFT (19U) +/*! ISF19 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK) + +#define GPIO_ISFR_ISF20_MASK (0x100000U) +#define GPIO_ISFR_ISF20_SHIFT (20U) +/*! ISF20 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK) + +#define GPIO_ISFR_ISF21_MASK (0x200000U) +#define GPIO_ISFR_ISF21_SHIFT (21U) +/*! ISF21 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK) + +#define GPIO_ISFR_ISF22_MASK (0x400000U) +#define GPIO_ISFR_ISF22_SHIFT (22U) +/*! ISF22 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK) + +#define GPIO_ISFR_ISF23_MASK (0x800000U) +#define GPIO_ISFR_ISF23_SHIFT (23U) +/*! ISF23 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK) + +#define GPIO_ISFR_ISF24_MASK (0x1000000U) +#define GPIO_ISFR_ISF24_SHIFT (24U) +/*! ISF24 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK) + +#define GPIO_ISFR_ISF25_MASK (0x2000000U) +#define GPIO_ISFR_ISF25_SHIFT (25U) +/*! ISF25 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK) + +#define GPIO_ISFR_ISF26_MASK (0x4000000U) +#define GPIO_ISFR_ISF26_SHIFT (26U) +/*! ISF26 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK) + +#define GPIO_ISFR_ISF27_MASK (0x8000000U) +#define GPIO_ISFR_ISF27_SHIFT (27U) +/*! ISF27 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK) + +#define GPIO_ISFR_ISF28_MASK (0x10000000U) +#define GPIO_ISFR_ISF28_SHIFT (28U) +/*! ISF28 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK) + +#define GPIO_ISFR_ISF29_MASK (0x20000000U) +#define GPIO_ISFR_ISF29_SHIFT (29U) +/*! ISF29 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK) + +#define GPIO_ISFR_ISF30_MASK (0x40000000U) +#define GPIO_ISFR_ISF30_SHIFT (30U) +/*! ISF30 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK) + +#define GPIO_ISFR_ISF31_MASK (0x80000000U) +#define GPIO_ISFR_ISF31_SHIFT (31U) +/*! ISF31 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_GPIO_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_INPUTMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_INPUTMUX.h new file mode 100644 index 000000000..1c003127e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_INPUTMUX.h @@ -0,0 +1,5123 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for INPUTMUX +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_INPUTMUX.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for INPUTMUX + * + * CMSIS Peripheral Access Layer for INPUTMUX + */ + +#if !defined(PERI_INPUTMUX_H_) +#define PERI_INPUTMUX_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Size of Registers Arrays */ +#define INPUTMUX_CTIMERA_COUNT 4u +#define INPUTMUX_CTIMERB_COUNT 4u +#define INPUTMUX_CTIMERC_COUNT 4u +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_COUNT 8u +#define INPUTMUX_AOI1_INPUTM_COUNT 16u +#define INPUTMUX_ADC0_TRIGM_COUNT 4u +#define INPUTMUX_ADC1_TRIGM_COUNT 4u +#define INPUTMUX_FLEXPWM0_FAULT_COUNT 4u +#define INPUTMUX_FLEXPWM1_FAULT_COUNT 4u +#define INPUTMUX_AOI0_INPUTK_COUNT 16u +#define INPUTMUX_EXT_TRIGN_COUNT 8u +#define INPUTMUX_TRIGFILP_COUNT 12u + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t CTIMER0CAP[INPUTMUX_CTIMERA_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x20, array step: 0x4 */ + __IO uint32_t TIMER0TRIG; /**< Trigger register for TIMER0, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CTIMER1CAP[INPUTMUX_CTIMERB_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x40, array step: 0x4 */ + __IO uint32_t TIMER1TRIG; /**< Trigger register for TIMER1, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CTIMER2CAP[INPUTMUX_CTIMERC_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x60, array step: 0x4 */ + __IO uint32_t TIMER2TRIG; /**< Trigger register for TIMER2 inputs, offset: 0x70 */ + uint8_t RESERVED_3[44]; + __IO uint32_t SMARTDMA_TRIG[INPUTMUX_SMARTDMA_TRIGGER_INPUTN_COUNT]; /**< SmartDMA Trigger Input Connections, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_4[192]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TAR; /**< Selection for frequency measurement reference clock, offset: 0x184 */ + uint8_t RESERVED_5[120]; + __IO uint32_t AOI1_INPUT[INPUTMUX_AOI1_INPUTM_COUNT]; /**< AOI1 trigger input connections 0, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[32]; + __IO uint32_t CMP0_TRIG; /**< CMP0 input connections, offset: 0x260 */ + uint8_t RESERVED_7[28]; + __IO uint32_t ADC0_TRIG[INPUTMUX_ADC0_TRIGM_COUNT]; /**< ADC Trigger input connections, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_8[48]; + __IO uint32_t ADC1_TRIG[INPUTMUX_ADC1_TRIGM_COUNT]; /**< ADC Trigger input connections, array offset: 0x2C0, array step: 0x4 */ + uint8_t RESERVED_9[144]; + __IO uint32_t QDC0_TRIG; /**< QDC0 Trigger Input Connections, offset: 0x360 */ + __IO uint32_t QDC0_HOME; /**< QDC0 Trigger Input Connections, offset: 0x364 */ + __IO uint32_t QDC0_INDEX; /**< QDC0 Trigger Input Connections, offset: 0x368 */ + __IO uint32_t QDC0_PHASEB; /**< QDC0 Trigger Input Connections, offset: 0x36C */ + __IO uint32_t QDC0_PHASEA; /**< QDC0 Trigger Input Connections, offset: 0x370 */ + __IO uint32_t QDC0_ICAP1; /**< QDC0 Trigger Input Connections, offset: 0x374 */ + __IO uint32_t QDC0_ICAP2; /**< QDC0 Trigger Input Connections, offset: 0x378 */ + __IO uint32_t QDC0_ICAP3; /**< QDC0 Trigger Input Connections, offset: 0x37C */ + __IO uint32_t QDC1_TRIG; /**< QDC1 Trigger Input Connections, offset: 0x380 */ + __IO uint32_t QDC1_HOME; /**< QDC1 Trigger Input Connections, offset: 0x384 */ + __IO uint32_t QDC1_INDEX; /**< QDC1 Trigger Input Connections, offset: 0x388 */ + __IO uint32_t QDC1_PHASEB; /**< QDC1 Trigger Input Connections, offset: 0x38C */ + __IO uint32_t QDC1_PHASEA; /**< QDC1 Trigger Input Connections, offset: 0x390 */ + __IO uint32_t QDC1_ICAP1; /**< QDC1 Trigger Input Connections, offset: 0x394 */ + __IO uint32_t QDC1_ICAP2; /**< QDC1 Trigger Input Connections, offset: 0x398 */ + __IO uint32_t QDC1_ICAP3; /**< QDC1 Trigger Input Connections, offset: 0x39C */ + __IO uint32_t FLEXPWM0_SM0_EXTA0; /**< PWM0 input trigger connections, offset: 0x3A0 */ + __IO uint32_t FLEXPWM0_SM0_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3A4 */ + __IO uint32_t FLEXPWM0_SM1_EXTA; /**< PWM0 input trigger connections, offset: 0x3A8 */ + __IO uint32_t FLEXPWM0_SM1_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3AC */ + __IO uint32_t FLEXPWM0_SM2_EXTA; /**< PWM0 input trigger connections, offset: 0x3B0 */ + __IO uint32_t FLEXPWM0_SM2_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3B4 */ + __IO uint32_t FLEXPWM0_SM3_EXTA0; /**< PWM0 input trigger connections, offset: 0x3B8 */ + __IO uint32_t FLEXPWM0_SM3_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3BC */ + __IO uint32_t FLEXPWM0_FAULT[INPUTMUX_FLEXPWM0_FAULT_COUNT]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C0, array step: 0x4 */ + __IO uint32_t FLEXPWM0_FORCE; /**< PWM0 input trigger connections, offset: 0x3D0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t FLEXPWM1_SM0_EXTA0; /**< PWM1 input trigger connections, offset: 0x3E0 */ + __IO uint32_t FLEXPWM1_SM0_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3E4 */ + __IO uint32_t FLEXPWM1_SM1_EXTA; /**< PWM1 input trigger connections, offset: 0x3E8 */ + __IO uint32_t FLEXPWM1_SM1_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3EC */ + __IO uint32_t FLEXPWM1_SM2_EXTA; /**< PWM1 input trigger connections, offset: 0x3F0 */ + __IO uint32_t FLEXPWM1_SM2_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3F4 */ + __IO uint32_t FLEXPWM1_SM3_EXTA0; /**< PWM1 input trigger connections, offset: 0x3F8 */ + __IO uint32_t FLEXPWM1_SM3_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3FC */ + __IO uint32_t FLEXPWM1_FAULT[INPUTMUX_FLEXPWM1_FAULT_COUNT]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x400, array step: 0x4 */ + __IO uint32_t FLEXPWM1_FORCE; /**< PWM1 input trigger connections, offset: 0x410 */ + uint8_t RESERVED_11[12]; + __IO uint32_t PWM0_EXT_CLK; /**< PWM0 external clock trigger, offset: 0x420 */ + __IO uint32_t PWM1_EXT_CLK; /**< PWM1 external clock trigger, offset: 0x424 */ + uint8_t RESERVED_12[24]; + __IO uint32_t AOI0_INPUT[INPUTMUX_AOI0_INPUTK_COUNT]; /**< AOI0 trigger input connections 0, array offset: 0x440, array step: 0x4 */ + uint8_t RESERVED_13[64]; + __IO uint32_t TRIG_OUT[INPUTMUX_EXT_TRIGN_COUNT]; /**< EXT trigger connections, array offset: 0x4C0, array step: 0x4 */ + __IO uint32_t CMP1_TRIG; /**< CMP1 input connections, offset: 0x4E0 */ + uint8_t RESERVED_14[28]; + __IO uint32_t CMP2_TRIG; /**< CMP2 input connections, offset: 0x500 */ + uint8_t RESERVED_15[156]; + __IO uint32_t LPI2C0_TRIG; /**< LPI2C0 trigger input connections, offset: 0x5A0 */ + uint8_t RESERVED_16[28]; + __IO uint32_t LPI2C1_TRIG; /**< LPI2C1 trigger input connections, offset: 0x5C0 */ + uint8_t RESERVED_17[28]; + __IO uint32_t LPSPI0_TRIG; /**< LPSPI0 trigger input connections, offset: 0x5E0 */ + uint8_t RESERVED_18[28]; + __IO uint32_t LPSPI1_TRIG; /**< LPSPI1 trigger input connections, offset: 0x600 */ + uint8_t RESERVED_19[28]; + __IO uint32_t LPUART0r; /**< LPUART0 trigger input connections, offset: 0x620, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART0' */ + uint8_t RESERVED_20[28]; + __IO uint32_t LPUART1r; /**< LPUART1 trigger input connections, offset: 0x640, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART1' */ + uint8_t RESERVED_21[28]; + __IO uint32_t LPUART2r; /**< LPUART2 trigger input connections, offset: 0x660, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART2' */ + uint8_t RESERVED_22[28]; + __IO uint32_t LPUART3r; /**< LPUART3 trigger input connections, offset: 0x680, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART3' */ + uint8_t RESERVED_23[892]; + __IO uint32_t TRIGFIL_PRSC; /**< Trigger filter prescaller, offset: 0xA00 */ + __I uint32_t TRIGFIL_STAT0; /**< Trigger filter stat, offset: 0xA04 */ + uint8_t RESERVED_24[8]; + __IO uint32_t TRIGFIL[INPUTMUX_TRIGFILP_COUNT]; /**< TRIGFIL control, array offset: 0xA10, array step: 0x4 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name CTIMERA_CTIMER0CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER0 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..Reserved + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..Reserved + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer1_MAT1 input is selected + * 0b0100010..CTimer1_MAT2 input is selected + * 0b0100011..CTimer1_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * 0b1000110..Reserved + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..Reserved + * 0b1010000..Reserved + * 0b1010001..Reserved + * 0b1010010..Reserved + * 0b1010011..Reserved + * 0b1010100..Reserved + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..Reserved + * 0b1011111..Reserved + * 0b1100000..Reserved + * 0b1100001..Reserved + * 0b1100010..Reserved + * 0b1100011..Reserved + * 0b1100100..Reserved + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..Reserved + * 0b1101010..Reserved + * 0b1101011..Reserved + * 0b1101100..Reserved + * 0b1101101..Reserved + * 0b1101110..Reserved + * 0b1101111..Reserved + * 0b1110000..Reserved + */ +#define INPUTMUX_CTIMERA_CTIMER0CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT)) & INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERA_CTIMER0CAP */ +#define INPUTMUX_CTIMERA_CTIMER0CAP_COUNT (4U) + +/*! @name TIMER0TRIG - Trigger register for TIMER0 */ +/*! @{ */ + +#define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER0 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..Reserved + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..Reserved + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer1_MAT1 input is selected + * 0b0100010..CTimer1_MAT2 input is selected + * 0b0100011..CTimer1_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * 0b1000110..Reserved + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..Reserved + * 0b1010000..Reserved + * 0b1010001..Reserved + * 0b1010010..Reserved + * 0b1010011..Reserved + * 0b1010100..Reserved + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..Reserved + * 0b1011111..Reserved + * 0b1100000..Reserved + * 0b1100001..Reserved + * 0b1100010..Reserved + * 0b1100011..Reserved + * 0b1100100..Reserved + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..Reserved + * 0b1101010..Reserved + * 0b1101011..Reserved + * 0b1101100..Reserved + * 0b1101101..Reserved + * 0b1101110..Reserved + * 0b1101111..Reserved + * 0b1110000..Reserved + */ +#define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMERB_CTIMER1CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER1 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..Reserved + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..Reserved + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * 0b1000110..Reserved + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..Reserved + * 0b1010000..Reserved + * 0b1010001..Reserved + * 0b1010010..Reserved + * 0b1010011..Reserved + * 0b1010100..Reserved + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIGmbc_bt_spec0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..Reserved + * 0b1011111..Reserved + * 0b1100000..Reserved + * 0b1100001..Reserved + * 0b1100010..Reserved + * 0b1100011..Reserved + * 0b1100100..Reserved + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..Reserved + * 0b1101010..Reserved + * 0b1101011..Reserved + * 0b1101100..Reserved + * 0b1101101..Reserved + * 0b1101110..Reserved + * 0b1101111..Reserved + * 0b1110000..Reserved + */ +#define INPUTMUX_CTIMERB_CTIMER1CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT)) & INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERB_CTIMER1CAP */ +#define INPUTMUX_CTIMERB_CTIMER1CAP_COUNT (4U) + +/*! @name TIMER1TRIG - Trigger register for TIMER1 */ +/*! @{ */ + +#define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER1 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..Reserved + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..Reserved + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * 0b1000110..Reserved + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..Reserved + * 0b1010000..Reserved + * 0b1010001..Reserved + * 0b1010010..Reserved + * 0b1010011..Reserved + * 0b1010100..Reserved + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..Reserved + * 0b1011111..Reserved + * 0b1100000..Reserved + * 0b1100001..Reserved + * 0b1100010..Reserved + * 0b1100011..Reserved + * 0b1100100..Reserved + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..Reserved + * 0b1101010..Reserved + * 0b1101011..Reserved + * 0b1101100..Reserved + * 0b1101101..Reserved + * 0b1101110..Reserved + * 0b1101111..Reserved + * 0b1110000..Reserved + */ +#define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMERC_CTIMER2CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER2 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..Reserved + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..Reserved + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * 0b1000110..Reserved + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..Reserved + * 0b1010000..Reserved + * 0b1010001..Reserved + * 0b1010010..Reserved + * 0b1010011..Reserved + * 0b1010100..Reserved + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..Reserved + * 0b1011111..Reserved + * 0b1100000..Reserved + * 0b1100001..Reserved + * 0b1100010..Reserved + * 0b1100011..Reserved + * 0b1100100..Reserved + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..Reserved + * 0b1101010..Reserved + * 0b1101011..Reserved + * 0b1101100..Reserved + * 0b1101101..Reserved + * 0b1101110..Reserved + * 0b1101111..Reserved + * 0b1110000..Reserved + */ +#define INPUTMUX_CTIMERC_CTIMER2CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT)) & INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERC_CTIMER2CAP */ +#define INPUTMUX_CTIMERC_CTIMER2CAP_COUNT (4U) + +/*! @name TIMER2TRIG - Trigger register for TIMER2 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER2 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..Reserved + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..Reserved + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * 0b1000110..Reserved + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..Reserved + * 0b1010000..Reserved + * 0b1010001..Reserved + * 0b1010010..Reserved + * 0b1010011..Reserved + * 0b1010100..Reserved + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..Reserved + * 0b1011111..Reserved + * 0b1100000..Reserved + * 0b1100001..Reserved + * 0b1100010..Reserved + * 0b1100011..Reserved + * 0b1100100..Reserved + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..Reserved + * 0b1101010..Reserved + * 0b1101011..Reserved + * 0b1101100..Reserved + * 0b1101101..Reserved + * 0b1101110..Reserved + * 0b1101111..Reserved + * 0b1110000..Reserved + */ +#define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK) +/*! @} */ + +/*! @name SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG - SmartDMA Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_SHIFT (0U) +/*! INP - Input number for FlexIO0. + * 0b0000000..Reserved + * 0b0000001..GPIO P0_16 input is selected + * 0b0000010..GPIO P0_17 input is selected + * 0b0000011..GPIO P1_8 input is selected + * 0b0000100..GPIO P1_9 input is selected + * 0b0000101..GPIO P1_10 input is selected + * 0b0000110..GPIO P1_11 input is selected + * 0b0000111..GPIO P1_12 input is selected + * 0b0001000..GPIO P1_13 input is selected + * 0b0001001..GPIO P2_0 input is selected + * 0b0001010..GPIO P2_1 input is selected + * 0b0001011..GPIO P2_2 input is selected + * 0b0001100..GPIO P2_3 input is selected + * 0b0001101..GPIO P2_6 input is selected + * 0b0001110..GPIO P3_8 input is selected + * 0b0001111..GPIO P3_9 input is selected + * 0b0010000..GPIO P3_10 input is selected + * 0b0010001..GPIO P3_11 input is selected + * 0b0010010..GPIO P3_12 input is seclected + * 0b0010011..GPIO0 Pin Event Trig input is selected + * 0b0010100..GPIO1 Pin Event Trig input is selected + * 0b0010101..GPIO2 Pin Event Trig input is selected + * 0b0010110..GPIO3 Pin Event Trig input is selected + * 0b0010111..GPIO4 Pin Event Trig input is selected + * 0b0011000..ARM_TXEV input is selected + * 0b0011001..AOI0_OUT0 input is selected + * 0b0011010..AOI1_OUT1 input is selected + * 0b0011011..DMA_IRQ input is selected + * 0b0011100..MAU_IRQ input is selected + * 0b0011101..WUU_IRQ input is selected + * 0b0011110..CTimer0_MAT2 input is selected + * 0b0011111..CTimer0_MAT3 input is selected + * 0b0100000..CTimer1_MAT2 input is selected + * 0b0100001..CTimer1_MAT3 input is selected + * 0b0100010..CTimer2_MAT2 input is selected + * 0b0100011..CTimer2_MAT3 input is selected + * 0b0100100..Reserved + * 0b0100101..Reserved + * 0b0100110..Reserved + * 0b0100111..Reserved + * 0b0101000..OSTIMER_IRQ input is selected + * 0b0101001..PWM0_IRQ input is selected + * 0b0101010..PWM1_IRQ input is selected + * 0b0101011..QDC0_IRQ input is selected + * 0b0101100..QDC1_IRQ input is selected + * 0b0101101..RTC_Alarm_IRQ input is selected + * 0b0101110..RTC_1Hz_IRQ input is selected + * 0b0101111..uTICK_IRQ input is selected + * 0b0110000..WDT_IRQ input is selected + * 0b0110001..Wakeup_Timer_IRQ input is selected + * 0b0110010..CAN0_IRQ input is selected + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..LPI2C0_IRQ input is selected + * 0b0111011..LPI2C1_IRQ input is selected + * 0b0111100..LPSPI0_IRQ input is selected + * 0b0111101..LPSPI1_IRQ input is selected + * 0b0111110..LPUART0_IRQ input is selected + * 0b0111111..LPUART1_IRQ input is selected + * 0b1000000..LPUART2_IRQ input is selected + * 0b1000001..LPUART3_IRQ input is selected + * 0b1000010..USB0_SOF input is selected + * 0b1000011..Reserved + * 0b1000100..ADC0_IRQ input is selected + * 0b1000101..ADC1_IRQ input is selected + * 0b1000110..ADC2_IRQ input is selected + * 0b1000111..ADC3_IRQ input is selected + * 0b1001000..CMP0_IRQ input is selected + * 0b1001001..CMP1_IRQ input is selected + * 0b1001010..CMP2_IRQ input is selected + * 0b1001011..CMP0_OUT input is selected + * 0b1001100..CMP1_OUT input is selected + * 0b1001101..CMP2_OUT input is selected + * 0b1001110..DAC0_IRQ input is selected + * 0b1001111..SLCD_IRQ input is selected + */ +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_SHIFT)) & INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG */ +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_COUNT (8U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_INP_MASK (0x7FU) +#define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b0000000..Reserved + * 0b0000001..clk_in input is selected + * 0b0000010..FRO_OSC_12M input is selected + * 0b0000011..fro_hf_div input is selected + * 0b0000100..Reserved + * 0b0000101..clk_16k[1] input is selected + * 0b0000110..SLOW_CLK input is selected + * 0b0000111..FREQME_CLK_IN0 input is selected + * 0b0001000..FREQME_CLK_IN1 input is selected input is selected + * 0b0001001..AOI0_OUT0 input is selected + * 0b0001010..AOI0_OUT1 + * 0b0001011..PWM0_SM0_MUX_TRIG0 + * 0b0001100..PWM0_SM0_MUX_TRIG1 + * 0b0001101..PWM0_SM1_MUX_TRIG0 + * 0b0001110..PWM0_SM1_MUX_TRIG1 + * 0b0001111..PWM0_SM2_MUX_TRIG0 + * 0b0010000..PWM0_SM2_MUX_TRIG1 + * 0b0010001..PWM0_SM3_MUX_TRIG0 + * 0b0010010..PWM0_SM3_MUX_TRIG1 + * 0b0010011..Reserved + * 0b0010100..Reserved + * 0b0010101..Reserved + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..Reserved + * 0b0011001..Reserved + * 0b0011010..Reserved + * 0b0011011..Reserved + * 0b0011100..Reserved + * 0b0011101..Reserved + * 0b0011110..Reserved + * 0b0011111..Reserved + * 0b0100000..AOI1_OUT0 input is selected + * 0b0100001..AOI1_OUT1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0100101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0100111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b0101001..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FREQMEAS_REF_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_TAR - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TAR_INP_MASK (0x7FU) +#define INPUTMUX_FREQMEAS_TAR_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b0000000..Reserved + * 0b0000001..clk_in input is selected + * 0b0000010..FRO_OSC_12M input is selected + * 0b0000011..fro_hf_div input is selected + * 0b0000100..Reserved + * 0b0000101..clk_16k[1] input is selected + * 0b0000110..SLOW_CLK input is selected + * 0b0000111..FREQME_CLK_IN0 input is selected + * 0b0001000..FREQME_CLK_IN1 input is selected input is selected + * 0b0001001..AOI0_OUT0 input is selected + * 0b0001010..AOI0_OUT1 + * 0b0001011..PWM0_SM0_MUX_TRIG0 + * 0b0001100..PWM0_SM0_MUX_TRIG1 + * 0b0001101..PWM0_SM1_MUX_TRIG0 + * 0b0001110..PWM0_SM1_MUX_TRIG1 + * 0b0001111..PWM0_SM2_MUX_TRIG0 + * 0b0010000..PWM0_SM2_MUX_TRIG1 + * 0b0010001..PWM0_SM3_MUX_TRIG0 + * 0b0010010..PWM0_SM3_MUX_TRIG1 + * 0b0010011..Reserved + * 0b0010100..Reserved + * 0b0010101..Reserved + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..Reserved + * 0b0011001..Reserved + * 0b0011010..Reserved + * 0b0011011..Reserved + * 0b0011100..Reserved + * 0b0011101..Reserved + * 0b0011110..Reserved + * 0b0011111..Reserved + * 0b0100000..AOI1_OUT0 input is selected + * 0b0100001..AOI1_OUT1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0100101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0100111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b0101001..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FREQMEAS_TAR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK) +/*! @} */ + +/*! @name AOI1_INPUTM_AOI1_INPUT - AOI1 trigger input connections 0 */ +/*! @{ */ + +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_MASK (0x7FU) +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_SHIFT (0U) +/*! INP - AOI0 trigger input connections + * 0b0000000..Reserved + * 0b0000001..ADC0_tcomp[0] input is selected + * 0b0000010..ADC0_tcomp[1] input is selected + * 0b0000011..ADC0_tcomp[2] input is selected + * 0b0000100..ADC0_tcomp[3] input is selected + * 0b0000101..CMP0_OUT input is selected + * 0b0000110..CMP1_OUT input is selected + * 0b0000111..CMP2_OUT input is selected + * 0b0001000..CTimer0_MAT0 input is selected + * 0b0001001..CTimer0_MAT1 input is selected + * 0b0001010..CTimer0_MAT2 input is selected + * 0b0001011..CTimer0_MAT3 input is selected + * 0b0001100..CTimer1_MAT0 + * 0b0001101..CTimer1_MAT1 input is selected + * 0b0001110..CTimer1_MAT2 input is selected + * 0b0001111..CTimer1_MAT3 input is selected + * 0b0010000..CTimer2_MAT0 input is selected + * 0b0010001..CTimer2_MAT1 input is selected + * 0b0010010..CTimer2_MAT2 input is selected + * 0b0010011..CTimer2_MAT3 input is selected + * 0b0010100..LPTMR0 input is selected + * 0b0010101..Reserved + * 0b0010110..QDC0_CMP_FLAG0 input is selected + * 0b0010111..QDC0_CMP_FLAG1 input is selected + * 0b0011000..QDC0_CMP_FLAG2 input is selected + * 0b0011001..QDC0_CMP_FLAG3 input is selected + * 0b0011010..QDC0_POS_MATCH input is selected + * 0b0011011..PWM0_SM0_MUX_TRIG0 0 input is selected + * 0b0011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0100010..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100011..TRIG_IN0 input is selected + * 0b0100100..TRIG_IN1 input is selected + * 0b0100101..TRIG_IN2 input is selected + * 0b0100110..TRIG_IN3 input is selected + * 0b0100111..TRIG_IN4 input is selected + * 0b0101000..TRIG_IN5 input is selected + * 0b0101001..TRIG_IN6 input is selected + * 0b0101010..TRIG_IN7 input is selected + * 0b0101011..TRIG_IN8 input is selected + * 0b0101100..TRIG_IN9 input is selected + * 0b0101101..TRIG_IN10 input is selected + * 0b0101110..TRIG_IN11 input is selected + * 0b0101111..GPIO0 Pin Event Trig 0 input is selected + * 0b0110000..GPIO1 Pin Event Trig 0 input is selected + * 0b0110001..GPIO2 Pin Event Trig 0 input is selected + * 0b0110010..GPIO3 Pin Event Trig 0 input is selected + * 0b0110011..GPIO4 Pin Event Trig 0 input is selected + * 0b0110100..ADC1_tcomp[0] input is selected + * 0b0110101..ADC1_tcomp[1] input is selected + * 0b0110110..ADC1_tcomp[2] input is selected + * 0b0110111..ADC1_tcomp[3] input is selected + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..Reserved + * 0b0111111..Reserved + * 0b1000000..Reserved + * 0b1000001..Reserved + * 0b1000010..Reserved + * 0b1000011..Reserved + * 0b1000100..QDC1_CMP_FLAG0 input is selected + * 0b1000101..QDC1_CMP_FLAG1 input is selected + * 0b1000110..QDC1_CMP_FLAG2 input is selected + * 0b1000111..QDC1_CMP_FLAG3 input is selected + * 0b1001000..QDC1_POS_MATCH0 input is selected + * 0b1001001..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1001010..PWM1_SM0_MUX_TRIG1 input is selected + * 0b1001011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1001100..PWM1_SM1_MUX_TRIG1 input is selected + * 0b1001101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1001110..PWM1_SM2_MUX_TRIG1 input is selected + * 0b1001111..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1010000..PWM1_SM3_MUX_TRIG1 input is selected + * 0b1010001..PWM0_SM0_A_Output + * 0b1010010..PWM0_SM0_B_Output + * 0b1010011..PWM0_SM1_A_Output + * 0b1010100..PWM0_SM1_B_Output + * 0b1010101..PWM0_SM2_A_Output + * 0b1010110..PWM0_SM2_B_Output + * 0b1010111..PWM0_SM3_A_Output + * 0b1011000..PWM0_SM3_B_Output + * 0b1011001..Reserved + * 0b1011010..Reserved + * 0b1011011..Reserved + * 0b1011100..Reserved + * 0b1011101..Reserved + * 0b1011110..Reserved + * 0b1011111..Reserved + * 0b1100000..Reserved + */ +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_SHIFT)) & INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_AOI1_INPUTM_AOI1_INPUT */ +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_COUNT (16U) + +/*! @name CMP0_TRIG - CMP0 input connections */ +/*! @{ */ + +#define INPUTMUX_CMP0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP1_OUT input is selected + * 0b000111..CMP2_OUT input is selected + * 0b001000..CTimer0_MAT0 input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer1_MAT0 + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer2_MAT0 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..LPTMR0 input is selected + * 0b001111..Reserved + * 0b010000..QDC0_POS_MATCH0 + * 0b010001..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010010..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010101..PWM0_SM2_MUX_TRIG0 input is selected + * 0b010110..PWM0_SM2_MUX_TRIG1 input is selected + * 0b010111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011000..PWM0_SM3_MUX_TRIG1 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..Reserved + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..QDC1_POS_MATCH0 input is selected + * 0b110000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + */ +#define INPUTMUX_CMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC0 trigger inputs + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..QDC0_POS_MATCH0 input is selected + * 0b010010..PWM0_SM0_OUT_TRIG0 input is selected + * 0b010011..PWM0_SM0_OUT_TRIG1 input is selected + * 0b010100..PWM0_SM1_OUT_TRIG0 input is selected + * 0b010101..PWM0_SM1_OUT_TRIG1 input is selected + * 0b010110..PWM0_SM2_OUT_TRIG0 input is selected + * 0b010111..PWM0_SM2_OUT_TRIG1 input is selected + * 0b011000..PWM0_SM3_OUT_TRIG0 input is selected + * 0b011001..PWM0_SM3_OUT_TRIG1 input is selected + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..WUU + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC1_tcomp[0] input is selected + * 0b100110..ADC1_tcomp[1] input is selected + * 0b100111..ADC1_tcomp[2] input is selected + * 0b101000..ADC1_tcomp[3] input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_POS_MATCH0 input is selected + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT (4U) + +/*! @name ADC1_TRIGM_ADC1_TRIG - ADC Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC0 trigger inputs + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..QDC0_POS_MATCH0 input is selected + * 0b010010..PWM0_SM0_OUT_TRIG0 input is selected + * 0b010011..PWM0_SM0_OUT_TRIG1 input is selected + * 0b010100..PWM0_SM1_OUT_TRIG0 input is selected + * 0b010101..PWM0_SM1_OUT_TRIG1 input is selected + * 0b010110..PWM0_SM2_OUT_TRIG0 input is selected + * 0b010111..PWM0_SM2_OUT_TRIG1 input is selected + * 0b011000..PWM0_SM3_OUT_TRIG0 input is selected + * 0b011001..PWM0_SM3_OUT_TRIG1 input is selected + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..WUU + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC0_tcomp[0] input is selected + * 0b100110..ADC0_tcomp[1] input is selected + * 0b100111..ADC0_tcomp[2] input is selected + * 0b101000..ADC0_tcomp[3] input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_POS_MATCH0 input is selected + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC1_TRIGM_ADC1_TRIG */ +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_COUNT (4U) + +/*! @name QDC0_TRIG - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_TRIG_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_TRIG_INP_SHIFT)) & INPUTMUX_QDC0_TRIG_INP_MASK) +/*! @} */ + +/*! @name QDC0_HOME - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_HOME_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_HOME_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_HOME_INP_SHIFT)) & INPUTMUX_QDC0_HOME_INP_MASK) +/*! @} */ + +/*! @name QDC0_INDEX - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_INDEX_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_INDEX_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_INDEX_INP_SHIFT)) & INPUTMUX_QDC0_INDEX_INP_MASK) +/*! @} */ + +/*! @name QDC0_PHASEB - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_PHASEB_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_PHASEB_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEB_INP_SHIFT)) & INPUTMUX_QDC0_PHASEB_INP_MASK) +/*! @} */ + +/*! @name QDC0_PHASEA - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_PHASEA_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_PHASEA_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEA_INP_SHIFT)) & INPUTMUX_QDC0_PHASEA_INP_MASK) +/*! @} */ + +/*! @name QDC0_ICAP1 - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_ICAP1_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_ICAP1_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_ICAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP1_INP_SHIFT)) & INPUTMUX_QDC0_ICAP1_INP_MASK) +/*! @} */ + +/*! @name QDC0_ICAP2 - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_ICAP2_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_ICAP2_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_ICAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP2_INP_SHIFT)) & INPUTMUX_QDC0_ICAP2_INP_MASK) +/*! @} */ + +/*! @name QDC0_ICAP3 - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_ICAP3_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_ICAP3_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_ICAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP3_INP_SHIFT)) & INPUTMUX_QDC0_ICAP3_INP_MASK) +/*! @} */ + +/*! @name QDC1_TRIG - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_TRIG_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_TRIG_INP_SHIFT)) & INPUTMUX_QDC1_TRIG_INP_MASK) +/*! @} */ + +/*! @name QDC1_HOME - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_HOME_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_HOME_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_HOME_INP_SHIFT)) & INPUTMUX_QDC1_HOME_INP_MASK) +/*! @} */ + +/*! @name QDC1_INDEX - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_INDEX_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_INDEX_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..>CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_INDEX_INP_SHIFT)) & INPUTMUX_QDC1_INDEX_INP_MASK) +/*! @} */ + +/*! @name QDC1_PHASEB - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_PHASEB_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_PHASEB_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 inout is selected + */ +#define INPUTMUX_QDC1_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_PHASEB_INP_SHIFT)) & INPUTMUX_QDC1_PHASEB_INP_MASK) +/*! @} */ + +/*! @name QDC1_PHASEA - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_PHASEA_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_PHASEA_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_PHASEA_INP_SHIFT)) & INPUTMUX_QDC1_PHASEA_INP_MASK) +/*! @} */ + +/*! @name QDC1_ICAP1 - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_ICAP1_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_ICAP1_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_ICAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP1_INP_SHIFT)) & INPUTMUX_QDC1_ICAP1_INP_MASK) +/*! @} */ + +/*! @name QDC1_ICAP2 - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_ICAP2_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_ICAP2_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_ICAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP2_INP_SHIFT)) & INPUTMUX_QDC1_ICAP2_INP_MASK) +/*! @} */ + +/*! @name QDC1_ICAP3 - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_ICAP3_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_ICAP3_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..Reserved + * 0b0110011..Reserved + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_ICAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP3_INP_SHIFT)) & INPUTMUX_QDC1_ICAP3_INP_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM0_EXTA0 - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM0_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM1_EXTA - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM1_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM2_EXTA - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM2_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM3_EXTA0 - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM3_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_FAULT - PWM0 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FAULT_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_FORCE - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM0_EXTA0 - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM0_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM1_EXTA - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM1_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM2_EXTA - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM2_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM3_EXTA0 - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM3_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_FAULT - PWM1 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM1 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_FORCE - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM1 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM0_EXT_CLK - PWM0 external clock trigger */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0xFU) +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM + * 0b0000..Reserved + * 0b0001..clk_16k[1] input is selected + * 0b0010..clk_in input is selected + * 0b0011..AOI0_OUT0 input is selected + * 0b0100..AOI0_OUT1 input is selected + * 0b0101..EXTTRIG_IN0 input is selected + * 0b0110..EXTTRIG_IN7 input is selected + * 0b0111..AOI1_OUT0 input is selected + * 0b1000..AOI1_OUT1 input is selected + */ +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM1_EXT_CLK - PWM1 external clock trigger */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK (0xFU) +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM + * 0b0000..Reserved + * 0b0001..clk_16k[1] input is selected + * 0b0010..clk_in input is selected + * 0b0011..AOI0_OUT0 input is selected + * 0b0100..AOI0_OUT1 input is selected + * 0b0101..EXTTRIG_IN0 input is selected + * 0b0110..EXTTRIG_IN7 input is selected + * 0b0111..AOI1_OUT0 input is selected + * 0b1000..AOI1_OUT1 input is selected + */ +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name AOI0_INPUTK_AOI0_INPUT - AOI0 trigger input connections 0 */ +/*! @{ */ + +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_MASK (0x7FU) +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_SHIFT (0U) +/*! INP - AOI0 trigger input connections + * 0b0000000..Reserved + * 0b0000001..ADC0_tcomp[0] input is selected + * 0b0000010..ADC0_tcomp[1] input is selected + * 0b0000011..ADC0_tcomp[2] input is selected + * 0b0000100..ADC0_tcomp[3] input is selected + * 0b0000101..CMP0_OUT input is selected + * 0b0000110..CMP1_OUT input is selected + * 0b0000111..CMP2_OUT input is selected + * 0b0001000..CTimer0_MAT0 input is selected + * 0b0001001..CTimer0_MAT1 input is selected + * 0b0001010..CTimer0_MAT2 input is selected + * 0b0001011..CTimer0_MAT3 input is selected + * 0b0001100..CTimer1_MAT0 + * 0b0001101..CTimer1_MAT1 input is selected + * 0b0001110..CTimer1_MAT2 input is selected + * 0b0001111..CTimer1_MAT3 input is selected + * 0b0010000..CTimer2_MAT0 input is selected + * 0b0010001..CTimer2_MAT1 input is selected + * 0b0010010..CTimer2_MAT2 input is selected + * 0b0010011..CTimer2_MAT3 input is selected + * 0b0010100..LPTMR0 input is selected + * 0b0010101..Reserved + * 0b0010110..QDC0_CMP_FLAG0 input is selected + * 0b0010111..QDC0_CMP_FLAG1 input is selected + * 0b0011000..QDC0_CMP_FLAG2 input is selected + * 0b0011001..QDC0_CMP_FLAG3 input is selected + * 0b0011010..QDC0_POS_MATCH input is selected + * 0b0011011..PWM0_SM0_MUX_TRIG0 0 input is selected + * 0b0011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0100010..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100011..TRIG_IN0 input is selected + * 0b0100100..TRIG_IN1 input is selected + * 0b0100101..TRIG_IN2 input is selected + * 0b0100110..TRIG_IN3 input is selected + * 0b0100111..TRIG_IN4 input is selected + * 0b0101000..TRIG_IN5 input is selected + * 0b0101001..TRIG_IN6 input is selected + * 0b0101010..TRIG_IN7 input is selected + * 0b0101011..TRIG_IN8 input is selected + * 0b0101100..TRIG_IN9 input is selected + * 0b0101101..TRIG_IN10 input is selected + * 0b0101110..TRIG_IN11 input is selected + * 0b0101111..GPIO0 Pin Event Trig 0 input is selected + * 0b0110000..GPIO1 Pin Event Trig 0 input is selected + * 0b0110001..GPIO2 Pin Event Trig 0 input is selected + * 0b0110010..GPIO3 Pin Event Trig 0 input is selected + * 0b0110011..GPIO4 Pin Event Trig 0 input is selected + * 0b0110100..ADC1_tcomp[0] input is selected + * 0b0110101..ADC1_tcomp[1] input is selected + * 0b0110110..ADC1_tcomp[2] input is selected + * 0b0110111..ADC1_tcomp[3] input is selected + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..Reserved + * 0b0111111..Reserved + * 0b1000000..Reserved + * 0b1000001..Reserved + * 0b1000010..Reserved + * 0b1000011..Reserved + * 0b1000100..QDC1_CMP_FLAG0 input is selected + * 0b1000101..QDC1_CMP_FLAG1 input is selected + * 0b1000110..QDC1_CMP_FLAG2 input is selected + * 0b1000111..QDC1_CMP_FLAG3 input is selected + * 0b1001000..QDC1_POS_MATCH0 input is selected + * 0b1001001..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1001010..PWM1_SM0_MUX_TRIG1 input is selected + * 0b1001011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1001100..PWM1_SM1_MUX_TRIG1 input is selected + * 0b1001101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1001110..PWM1_SM2_MUX_TRIG1 input is selected + * 0b1001111..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1010000..PWM1_SM3_MUX_TRIG1 input is selected + * 0b1010001..PWM0_SM0_A_Output + * 0b1010010..PWM0_SM0_B_Output + * 0b1010011..PWM0_SM1_A_Output + * 0b1010100..PWM0_SM1_B_Output + * 0b1010101..PWM0_SM2_A_Output + * 0b1010110..PWM0_SM2_B_Output + * 0b1010111..PWM0_SM3_A_Output + * 0b1011000..PWM0_SM3_B_Output + * 0b1011001..Reserved + * 0b1011010..Reserved + * 0b1011011..Reserved + * 0b1011100..Reserved + * 0b1011101..Reserved + * 0b1011110..Reserved + * 0b1011111..Reserved + * 0b1100000..Reserved + */ +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_SHIFT)) & INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_AOI0_INPUTK_AOI0_INPUT */ +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_COUNT (16U) + +/*! @name EXT_TRIGN_TRIG_OUT - EXT trigger connections */ +/*! @{ */ + +#define INPUTMUX_EXT_TRIGN_TRIG_OUT_INP_MASK (0x1FU) +#define INPUTMUX_EXT_TRIGN_TRIG_OUT_INP_SHIFT (0U) +/*! INP - EXT trigger input connections + * 0b00000..Reserved + * 0b00001..Reserved + * 0b00010..AOI0_OUT0 input is selected + * 0b00011..AOI0_OUT1 input is selected + * 0b00100..AOI0_OUT2 input is selected + * 0b00101..AOI0_OUT3 input is selected + * 0b00110..CMP0_OUT input is selected + * 0b00111..CMP1_OUT input is selected + * 0b01000..CMP2_OUT input is selected + * 0b01001..LPUART0 ipp_do_lpuart_txd input is selected + * 0b01010..LPUART1 ipp_do_lpuart_txd input is selected + * 0b01011..LPUART2 ipp_do_lpuart_txd input is selected + * 0b01100..LPUART3 ipp_do_lpuart_txd input is selected + * 0b01101..Reserved + * 0b01110..AOI1_OUT0 input is selected + * 0b01111..AOI1_OUT1 input is selected + * 0b10000..AOI1_OUT2 input is selected + * 0b10001..RTC_1Hz_CLK input is selected + * 0b10010..Reserved + */ +#define INPUTMUX_EXT_TRIGN_TRIG_OUT_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_TRIG_OUT_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_TRIG_OUT_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_EXT_TRIGN_TRIG_OUT */ +#define INPUTMUX_EXT_TRIGN_TRIG_OUT_COUNT (8U) + +/*! @name CMP1_TRIG - CMP1 input connections */ +/*! @{ */ + +#define INPUTMUX_CMP1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP2_OUT input is selected + * 0b001000..CTimer0_MAT0 input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer1_MAT0 + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer2_MAT0 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..LPTMR0 input is selected + * 0b001111..Reserved + * 0b010000..QDC0_POS_MATCH0 + * 0b010001..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010010..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010101..PWM0_SM2_MUX_TRIG0 input is selected + * 0b010110..PWM0_SM2_MUX_TRIG1 input is selected + * 0b010111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011000..PWM0_SM3_MUX_TRIG1 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..Reserved + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..QDC1_POS_MATCH0 input is selected + * 0b110000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + */ +#define INPUTMUX_CMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name CMP2_TRIG - CMP2 input connections */ +/*! @{ */ + +#define INPUTMUX_CMP2_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CTimer0_MAT0 input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer1_MAT0 + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer2_MAT0 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..LPTMR0 input is selected + * 0b001111..Reserved + * 0b010000..QDC0_POS_MATCH0 + * 0b010001..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010010..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010101..PWM0_SM2_MUX_TRIG0 input is selected + * 0b010110..PWM0_SM2_MUX_TRIG1 input is selected + * 0b010111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011000..PWM0_SM3_MUX_TRIG1 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..Reserved + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..QDC1_POS_MATCH0 input is selected + * 0b110000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + */ +#define INPUTMUX_CMP2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP2_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name LPI2C0_TRIG - LPI2C0 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPI2C0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPI2C0_TRIG_INP_SHIFT (0U) +/*! INP - LPI2C0 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..Reserved + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + */ +#define INPUTMUX_LPI2C0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C0_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C0_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPI2C1_TRIG - LPI2C1 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPI2C1_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPI2C1_TRIG_INP_SHIFT (0U) +/*! INP - LPI2C1 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..Reserved + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + */ +#define INPUTMUX_LPI2C1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C1_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C1_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPSPI0_TRIG - LPSPI0 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPSPI0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPSPI0_TRIG_INP_SHIFT (0U) +/*! INP - LPSPI0 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP3_OUT input is selected + * 0b001001..CTimer0_MAT1 input is selected + * 0b001010..CTimer0_MAT2 input is selected + * 0b001011..CTimer1_MAT1 input is selected + * 0b001100..CTimer1_MAT2 input is selected + * 0b001101..CTimer2_MAT1 input is selected + * 0b001110..CTimer2_MAT2 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..Reserved + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + */ +#define INPUTMUX_LPSPI0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI0_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI0_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPSPI1_TRIG - LPSPI1 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPSPI1_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPSPI1_TRIG_INP_SHIFT (0U) +/*! INP - LPSPI1 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT1 input is selected + * 0b001010..CTimer0_MAT2 input is selected + * 0b001011..CTimer1_MAT1 input is selected + * 0b001100..CTimer1_MAT2 input is selected + * 0b001101..CTimer2_MAT1 input is selected + * 0b001110..CTimer2_MAT2 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..Reserved + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + */ +#define INPUTMUX_LPSPI1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI1_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI1_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPUART0 - LPUART0 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART0_INP_MASK (0x3FU) +#define INPUTMUX_LPUART0_INP_SHIFT (0U) +/*! INP - LPUART0 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..Reserved + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + */ +#define INPUTMUX_LPUART0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART0_INP_SHIFT)) & INPUTMUX_LPUART0_INP_MASK) +/*! @} */ + +/*! @name LPUART1 - LPUART1 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART1_INP_MASK (0x3FU) +#define INPUTMUX_LPUART1_INP_SHIFT (0U) +/*! INP - LPUART1 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..Reserved + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + */ +#define INPUTMUX_LPUART1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART1_INP_SHIFT)) & INPUTMUX_LPUART1_INP_MASK) +/*! @} */ + +/*! @name LPUART2 - LPUART2 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART2_INP_MASK (0x3FU) +#define INPUTMUX_LPUART2_INP_SHIFT (0U) +/*! INP - LPUART2 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..UReserved + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + */ +#define INPUTMUX_LPUART2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART2_INP_SHIFT)) & INPUTMUX_LPUART2_INP_MASK) +/*! @} */ + +/*! @name LPUART3 - LPUART3 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART3_INP_MASK (0x3FU) +#define INPUTMUX_LPUART3_INP_SHIFT (0U) +/*! INP - LPUART3 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..Reserved + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..Reserved + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + */ +#define INPUTMUX_LPUART3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART3_INP_SHIFT)) & INPUTMUX_LPUART3_INP_MASK) +/*! @} */ + +/*! @name TRIGFIL_PRSC - Trigger filter prescaller */ +/*! @{ */ + +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_MASK (0x3U) +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_SHIFT (0U) +/*! FILT_SCALE_VAL - Filter Prescaller Value + * 0b00..Bypass the clock + * 0b01..Divide 2 + * 0b10..Divide 4 + * 0b11..Divide 8 + */ +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_SHIFT)) & INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_MASK) + +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_MASK (0x80000000U) +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_SHIFT (31U) +/*! FILT_SCALE_EN - Enable trigger filter prescaller + * 0b0..Disable prescaller + * 0b1..Enabled prescaller + */ +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_SHIFT)) & INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_MASK) +/*! @} */ + +/*! @name TRIGFIL_STAT0 - Trigger filter stat */ +/*! @{ */ + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_MASK (0x1U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_SHIFT (0U) +/*! TRIG_IN0_VAL - TRIG_IN value + * 0b0..TRIG_IN0 is 0 + * 0b1..TRIG_IN0 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_MASK (0x2U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_SHIFT (1U) +/*! TRIG_IN1_VAL - TRIG_IN value + * 0b0..TRIG_IN1 is 0 + * 0b1..TRIG_IN1 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_MASK (0x4U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_SHIFT (2U) +/*! TRIG_IN2_VAL - TRIG_IN value + * 0b0..TRIG_IN2 is 0 + * 0b1..TRIG_IN2 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_MASK (0x8U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_SHIFT (3U) +/*! TRIG_IN3_VAL - TRIG_IN value + * 0b0..TRIG_IN3 is 0 + * 0b1..TRIG_IN3 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_MASK (0x10U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_SHIFT (4U) +/*! TRIG_IN4_VAL - TRIG_IN value + * 0b0..TRIG_IN4 is 0 + * 0b1..TRIG_IN4 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_MASK (0x20U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_SHIFT (5U) +/*! TRIG_IN5_VAL - TRIG_IN value + * 0b0..TRIG_IN5 is 0 + * 0b1..TRIG_IN5 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_MASK (0x40U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_SHIFT (6U) +/*! TRIG_IN6_VAL - TRIG_IN value + * 0b0..TRIG_IN6 is 0 + * 0b1..TRIG_IN6 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_MASK (0x80U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_SHIFT (7U) +/*! TRIG_IN7_VAL - TRIG_IN value + * 0b0..TRIG_IN7 is 0 + * 0b1..TRIG_IN7 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_MASK (0x100U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_SHIFT (8U) +/*! TRIG_IN8_VAL - TRIG_IN value + * 0b0..TRIG_IN8 is 0 + * 0b1..TRIG_IN8 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_MASK (0x200U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_SHIFT (9U) +/*! TRIG_IN9_VAL - TRIG_IN value + * 0b0..TRIG_IN9 is 0 + * 0b1..TRIG_IN9 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_MASK (0x400U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_SHIFT (10U) +/*! TRIG_IN10_VAL - TRIG_IN value + * 0b0..TRIG_IN10 is 0 + * 0b1..TRIG_IN10 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_MASK (0x800U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_SHIFT (11U) +/*! TRIG_IN11_VAL - TRIG_IN value + * 0b0..TRIG_IN11 is 0 + * 0b1..TRIG_IN11 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_MASK) +/*! @} */ + +/*! @name TRIGFILP_TRIGFIL - TRIGFIL control */ +/*! @{ */ + +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_MASK (0xFFU) +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_SHIFT)) & INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_MASK) + +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_MASK (0x700U) +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_SHIFT)) & INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_MASK) +/*! @} */ + +/* The count of INPUTMUX_TRIGFILP_TRIGFIL */ +#define INPUTMUX_TRIGFILP_TRIGFIL_COUNT (12U) + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_INPUTMUX_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPCMP.h new file mode 100644 index 000000000..6872b029d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPCMP.h @@ -0,0 +1,821 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPCMP +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_LPCMP.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for LPCMP + * + * CMSIS Peripheral Access Layer for LPCMP + */ + +#if !defined(PERI_LPCMP_H_) +#define PERI_LPCMP_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPCMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer + * @{ + */ + +/** LPCMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ + __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ + __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DCR; /**< DAC Control, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t CSR; /**< Comparator Status, offset: 0x20 */ + __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ + __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ + __IO uint32_t RRCSR; /**< Round Robin Control and Status, offset: 0x2C */ + __IO uint32_t RRSR; /**< Round Robin Status, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */ +} LPCMP_Type; + +/* ---------------------------------------------------------------------------- + -- LPCMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Register_Masks LPCMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPCMP_VERID_FEATURE_MASK (0xFFFFU) +#define LPCMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000001..Round robin feature + */ +#define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) + +#define LPCMP_VERID_MINOR_MASK (0xFF0000U) +#define LPCMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) + +#define LPCMP_VERID_MAJOR_MASK (0xFF000000U) +#define LPCMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPCMP_PARAM_DAC_RES_MASK (0xFU) +#define LPCMP_PARAM_DAC_RES_SHIFT (0U) +/*! DAC_RES - DAC Resolution + * 0b0000..4-bit DAC + * 0b0001..6-bit DAC + * 0b0010..8-bit DAC + * 0b0011..10-bit DAC + * 0b0100..12-bit DAC + * 0b0101..14-bit DAC + * 0b0110..16-bit DAC + */ +#define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) +/*! @} */ + +/*! @name CCR0 - Comparator Control Register 0 */ +/*! @{ */ + +#define LPCMP_CCR0_CMP_EN_MASK (0x1U) +#define LPCMP_CCR0_CMP_EN_SHIFT (0U) +/*! CMP_EN - Comparator Enable + * 0b0..Disable (The analog logic remains off and consumes no power.) + * 0b1..Enable + */ +#define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) + +#define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U) +#define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U) +/*! CMP_STOP_EN - Comparator Deep sleep Mode Enable + * 0b0..Disables the analog comparator regardless of CMP_EN. + * 0b1..Allows CMP_EN to enable the analog comparator. + */ +#define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK) +/*! @} */ + +/*! @name CCR1 - Comparator Control Register 1 */ +/*! @{ */ + +#define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) +#define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) +/*! WINDOW_EN - Windowing Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) + +#define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) +#define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) +/*! SAMPLE_EN - Sampling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) + +#define LPCMP_CCR1_DMA_EN_MASK (0x4U) +#define LPCMP_CCR1_DMA_EN_SHIFT (2U) +/*! DMA_EN - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) + +#define LPCMP_CCR1_COUT_INV_MASK (0x8U) +#define LPCMP_CCR1_COUT_INV_SHIFT (3U) +/*! COUT_INV - Comparator Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) + +#define LPCMP_CCR1_COUT_SEL_MASK (0x10U) +#define LPCMP_CCR1_COUT_SEL_SHIFT (4U) +/*! COUT_SEL - Comparator Output Select + * 0b0..Use COUT (filtered) + * 0b1..Use COUTA (unfiltered) + */ +#define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) + +#define LPCMP_CCR1_COUT_PEN_MASK (0x20U) +#define LPCMP_CCR1_COUT_PEN_SHIFT (5U) +/*! COUT_PEN - Comparator Output Pin Enable + * 0b0..Not available + * 0b1..Available + */ +#define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) + +#define LPCMP_CCR1_COUTA_OWEN_MASK (0x40U) +#define LPCMP_CCR1_COUTA_OWEN_SHIFT (6U) +/*! COUTA_OWEN - COUTA_OW Enable + * 0b0..COUTA holds the last sampled value. + * 0b1..Enables the COUTA signal value to be defined by COUTA_OW. + */ +#define LPCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK) + +#define LPCMP_CCR1_COUTA_OW_MASK (0x80U) +#define LPCMP_CCR1_COUTA_OW_SHIFT (7U) +/*! COUTA_OW - COUTA Output Level for Closed Window + * 0b0..COUTA is 0 + * 0b1..COUTA is 1 + */ +#define LPCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK) + +#define LPCMP_CCR1_WINDOW_INV_MASK (0x100U) +#define LPCMP_CCR1_WINDOW_INV_SHIFT (8U) +/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK) + +#define LPCMP_CCR1_WINDOW_CLS_MASK (0x200U) +#define LPCMP_CCR1_WINDOW_CLS_SHIFT (9U) +/*! WINDOW_CLS - COUT Event Window Close + * 0b0..COUT event cannot close the window + * 0b1..COUT event can close the window + */ +#define LPCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK) + +#define LPCMP_CCR1_EVT_SEL_MASK (0xC00U) +#define LPCMP_CCR1_EVT_SEL_SHIFT (10U) +/*! EVT_SEL - COUT Event Select + * 0b00..Rising edge + * 0b01..Falling edge + * 0b1x..Both edges + */ +#define LPCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK) + +#define LPCMP_CCR1_FUNC_CLK_SEL_MASK (0x3000U) +#define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT (12U) +/*! FUNC_CLK_SEL - Functional Clock Source Select + * 0b00..Select functional clock source 0 + * 0b01..Select functional clock source 1 + * 0b10..Select functional clock source 2 + * 0b11..Select functional clock source 3 + */ +#define LPCMP_CCR1_FUNC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK) + +#define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) +#define LPCMP_CCR1_FILT_CNT_SHIFT (16U) +/*! FILT_CNT - Filter Sample Count + * 0b000..Filter is bypassed: COUT = COUTA + * 0b001..1 consecutive sample (Comparator output is simply sampled.) + * 0b010..2 consecutive samples + * 0b011..3 consecutive samples + * 0b100..4 consecutive samples + * 0b101..5 consecutive samples + * 0b110..6 consecutive samples + * 0b111..7 consecutive samples + */ +#define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) + +#define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) +#define LPCMP_CCR1_FILT_PER_SHIFT (24U) +/*! FILT_PER - Filter Sample Period */ +#define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) +/*! @} */ + +/*! @name CCR2 - Comparator Control Register 2 */ +/*! @{ */ + +#define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) +#define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) +/*! CMP_HPMD - CMP High Power Mode Select + * 0b0..Low power (speed) comparison mode + * 0b1..High power (speed) comparison mode + */ +#define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) + +#define LPCMP_CCR2_CMP_NPMD_MASK (0x2U) +#define LPCMP_CCR2_CMP_NPMD_SHIFT (1U) +/*! CMP_NPMD - CMP Nano Power Mode Select + * 0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator. + * 0b1..Enables CMP Nano power mode. + */ +#define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK) + +#define LPCMP_CCR2_HYSTCTR_MASK (0x30U) +#define LPCMP_CCR2_HYSTCTR_SHIFT (4U) +/*! HYSTCTR - Comparator Hysteresis Control + * 0b00..Level 0: Analog comparator hysteresis 0 mV. + * 0b01..Level 1: Analog comparator hysteresis 10 mV. + * 0b10..Level 2: Analog comparator hysteresis 20 mV. + * 0b11..Level 3: Analog comparator hysteresis 30 mV. + */ +#define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) + +#define LPCMP_CCR2_PSEL_MASK (0x70000U) +#define LPCMP_CCR2_PSEL_SHIFT (16U) +/*! PSEL - Plus Input MUX Select + * 0b000..Input 0p + * 0b001..Input 1p + * 0b010..Input 2p + * 0b011..Input 3p + * 0b100..Input 4p + * 0b101..Input 5p + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) + +#define LPCMP_CCR2_MSEL_MASK (0x700000U) +#define LPCMP_CCR2_MSEL_SHIFT (20U) +/*! MSEL - Minus Input MUX Select + * 0b000..Input 0m + * 0b001..Input 1m + * 0b010..Input 2m + * 0b011..Input 3m + * 0b100..Input 4m + * 0b101..Input 5m + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) +/*! @} */ + +/*! @name DCR - DAC Control */ +/*! @{ */ + +#define LPCMP_DCR_DAC_EN_MASK (0x1U) +#define LPCMP_DCR_DAC_EN_SHIFT (0U) +/*! DAC_EN - DAC Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) + +#define LPCMP_DCR_DAC_HPMD_MASK (0x2U) +#define LPCMP_DCR_DAC_HPMD_SHIFT (1U) +/*! DAC_HPMD - DAC High Power Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) + +#define LPCMP_DCR_VRSEL_MASK (0x100U) +#define LPCMP_DCR_VRSEL_SHIFT (8U) +/*! VRSEL - DAC Reference High Voltage Source Select + * 0b0..VREFH0 + * 0b1..VREFH1 + */ +#define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) + +#define LPCMP_DCR_DAC_DATA_MASK (0xFF0000U) +#define LPCMP_DCR_DAC_DATA_SHIFT (16U) +/*! DAC_DATA - DAC Output Voltage Select */ +#define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPCMP_IER_CFR_IE_MASK (0x1U) +#define LPCMP_IER_CFR_IE_SHIFT (0U) +/*! CFR_IE - Comparator Flag Rising Interrupt Enable + * 0b0..Disables the comparator flag rising interrupt. + * 0b1..Enables the comparator flag rising interrupt when CFR is set. + */ +#define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) + +#define LPCMP_IER_CFF_IE_MASK (0x2U) +#define LPCMP_IER_CFF_IE_SHIFT (1U) +/*! CFF_IE - Comparator Flag Falling Interrupt Enable + * 0b0..Disables the comparator flag falling interrupt. + * 0b1..Enables the comparator flag falling interrupt when CFF is set. + */ +#define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) + +#define LPCMP_IER_RRF_IE_MASK (0x4U) +#define LPCMP_IER_RRF_IE_SHIFT (2U) +/*! RRF_IE - Round-Robin Flag Interrupt Enable + * 0b0..Disables the round-robin flag interrupt. + * 0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel. + */ +#define LPCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK) +/*! @} */ + +/*! @name CSR - Comparator Status */ +/*! @{ */ + +#define LPCMP_CSR_CFR_MASK (0x1U) +#define LPCMP_CSR_CFR_SHIFT (0U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) + +#define LPCMP_CSR_CFF_MASK (0x2U) +#define LPCMP_CSR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) + +#define LPCMP_CSR_RRF_MASK (0x4U) +#define LPCMP_CSR_RRF_SHIFT (2U) +/*! RRF - Round-Robin Flag + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK) + +#define LPCMP_CSR_COUT_MASK (0x100U) +#define LPCMP_CSR_COUT_SHIFT (8U) +/*! COUT - Analog Comparator Output */ +#define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) +/*! @} */ + +/*! @name RRCR0 - Round Robin Control Register 0 */ +/*! @{ */ + +#define LPCMP_RRCR0_RR_EN_MASK (0x1U) +#define LPCMP_RRCR0_RR_EN_SHIFT (0U) +/*! RR_EN - Round-Robin Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) + +#define LPCMP_RRCR0_RR_TRG_SEL_MASK (0x2U) +#define LPCMP_RRCR0_RR_TRG_SEL_SHIFT (1U) +/*! RR_TRG_SEL - Round-Robin Trigger Select + * 0b0..External trigger + * 0b1..Internal trigger + */ +#define LPCMP_RRCR0_RR_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK) + +#define LPCMP_RRCR0_RR_EXTTRG_SEL_MASK (0x3CU) +#define LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT (2U) +/*! RR_EXTTRG_SEL - External Trigger Source Select + * 0b0000..Select external trigger source 0 + * 0b0001..Select external trigger source 1 + * 0b0010..Select external trigger source 2 + * 0b0011..Select external trigger source 3 + * 0b0100..Select external trigger source 4 + * 0b0101..Select external trigger source 5 + * 0b0110..Select external trigger source 6 + * 0b0111..Select external trigger source 7 + * 0b1000..Select external trigger source 8 + * 0b1001..Select external trigger source 9 + * 0b1010..Select external trigger source 10 + * 0b1011..Select external trigger source 11 + * 0b1100..Select external trigger source 12 + * 0b1101..Select external trigger source 13 + * 0b1110..Select external trigger source 14 + * 0b1111..Select external trigger source 15 + */ +#define LPCMP_RRCR0_RR_EXTTRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_EXTTRG_SEL_MASK) + +#define LPCMP_RRCR0_RR_NSAM_MASK (0x300U) +#define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) +/*! RR_NSAM - Number of Sample Clocks + * 0b00..0 clock + * 0b01..1 clock + * 0b10..2 clocks + * 0b11..3 clocks + */ +#define LPCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK) + +#define LPCMP_RRCR0_RR_CLK_SEL_MASK (0x3000U) +#define LPCMP_RRCR0_RR_CLK_SEL_SHIFT (12U) +/*! RR_CLK_SEL - Round Robin Clock Source Select + * 0b00..Select Round Robin clock Source 0 + * 0b01..Select Round Robin clock Source 1 + * 0b10..Select Round Robin clock Source 2 + * 0b11..Select Round Robin clock Source 3 + */ +#define LPCMP_RRCR0_RR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK) + +#define LPCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) +#define LPCMP_RRCR0_RR_INITMOD_SHIFT (16U) +/*! RR_INITMOD - Initialization Delay Modulus + * 0b000000..63 cycles (same as 111111b) + * 0b000001-0b111111..1 to 63 cycles + */ +#define LPCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK (0xF000000U) +#define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT (24U) +/*! RR_SAMPLE_CNT - Number of Sample for One Channel + * 0b0000..1 samples + * 0b0001..2 samples + * 0b0010..3 samples + * 0b0011..4 samples + * 0b0100..5 samples + * 0b0101..6 samples + * 0b0110..7 samples + * 0b0111..8 samples + * 0b1000..9 samples + * 0b1001..10 samples + * 0b1010..11 samples + * 0b1011..12 samples + * 0b1100..13 samples + * 0b1101..14 samples + * 0b1110..15 samples + * 0b1111..16 samples + */ +#define LPCMP_RRCR0_RR_SAMPLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK (0xF0000000U) +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT (28U) +/*! RR_SAMPLE_THRESHOLD - Sample Time Threshold + * 0b0000..At least 1 sampled "1", the final result is "1" + * 0b0001..At least 2 sampled "1", the final result is "1" + * 0b0010..At least 3 sampled "1", the final result is "1" + * 0b0011..At least 4 sampled "1", the final result is "1" + * 0b0100..At least 5 sampled "1", the final result is "1" + * 0b0101..At least 6 sampled "1", the final result is "1" + * 0b0110..At least 7 sampled "1", the final result is "1" + * 0b0111..At least 8 sampled "1", the final result is "1" + * 0b1000..At least 9 sampled "1", the final result is "1" + * 0b1001..At least 10 sampled "1", the final result is "1" + * 0b1010..At least 11 sampled "1", the final result is "1" + * 0b1011..At least 12 sampled "1", the final result is "1" + * 0b1100..At least 13 sampled "1", the final result is "1" + * 0b1101..At least 14 sampled "1", the final result is "1" + * 0b1110..At least 15 sampled "1", the final result is "1" + * 0b1111..At least 16 sampled "1", the final result is "1" + */ +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK) +/*! @} */ + +/*! @name RRCR1 - Round Robin Control Register 1 */ +/*! @{ */ + +#define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) +#define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) +/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) + +#define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) +#define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) +/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) + +#define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) +#define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) +/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) + +#define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) +#define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) +/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) + +#define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) +#define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) +/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) + +#define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) +#define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) +/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) + +#define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) +#define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) +/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) + +#define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) +#define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) +/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) + +#define LPCMP_RRCR1_FIXP_MASK (0x10000U) +#define LPCMP_RRCR1_FIXP_SHIFT (16U) +/*! FIXP - Fixed Port + * 0b0..Fix the plus port. Sweep only the inputs to the minus port. + * 0b1..Fix the minus port. Sweep only the inputs to the plus port. + */ +#define LPCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK) + +#define LPCMP_RRCR1_FIXCH_MASK (0x700000U) +#define LPCMP_RRCR1_FIXCH_SHIFT (20U) +/*! FIXCH - Fixed Channel Select + * 0b000..Channel 0 + * 0b001..Channel 1 + * 0b010..Channel 2 + * 0b011..Channel 3 + * 0b100..Channel 4 + * 0b101..Channel 5 + * 0b110..Channel 6 + * 0b111..Channel 7 + */ +#define LPCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK) +/*! @} */ + +/*! @name RRCSR - Round Robin Control and Status */ +/*! @{ */ + +#define LPCMP_RRCSR_RR_CH0OUT_MASK (0x1U) +#define LPCMP_RRCSR_RR_CH0OUT_SHIFT (0U) +/*! RR_CH0OUT - Comparison Result for Channel 0 */ +#define LPCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK) + +#define LPCMP_RRCSR_RR_CH1OUT_MASK (0x2U) +#define LPCMP_RRCSR_RR_CH1OUT_SHIFT (1U) +/*! RR_CH1OUT - Comparison Result for Channel 1 */ +#define LPCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK) + +#define LPCMP_RRCSR_RR_CH2OUT_MASK (0x4U) +#define LPCMP_RRCSR_RR_CH2OUT_SHIFT (2U) +/*! RR_CH2OUT - Comparison Result for Channel 2 */ +#define LPCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK) + +#define LPCMP_RRCSR_RR_CH3OUT_MASK (0x8U) +#define LPCMP_RRCSR_RR_CH3OUT_SHIFT (3U) +/*! RR_CH3OUT - Comparison Result for Channel 3 */ +#define LPCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK) + +#define LPCMP_RRCSR_RR_CH4OUT_MASK (0x10U) +#define LPCMP_RRCSR_RR_CH4OUT_SHIFT (4U) +/*! RR_CH4OUT - Comparison Result for Channel 4 */ +#define LPCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK) + +#define LPCMP_RRCSR_RR_CH5OUT_MASK (0x20U) +#define LPCMP_RRCSR_RR_CH5OUT_SHIFT (5U) +/*! RR_CH5OUT - Comparison Result for Channel 5 */ +#define LPCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK) + +#define LPCMP_RRCSR_RR_CH6OUT_MASK (0x40U) +#define LPCMP_RRCSR_RR_CH6OUT_SHIFT (6U) +/*! RR_CH6OUT - Comparison Result for Channel 6 */ +#define LPCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK) + +#define LPCMP_RRCSR_RR_CH7OUT_MASK (0x80U) +#define LPCMP_RRCSR_RR_CH7OUT_SHIFT (7U) +/*! RR_CH7OUT - Comparison Result for Channel 7 */ +#define LPCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK) +/*! @} */ + +/*! @name RRSR - Round Robin Status */ +/*! @{ */ + +#define LPCMP_RRSR_RR_CH0F_MASK (0x1U) +#define LPCMP_RRSR_RR_CH0F_SHIFT (0U) +/*! RR_CH0F - Channel 0 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) + +#define LPCMP_RRSR_RR_CH1F_MASK (0x2U) +#define LPCMP_RRSR_RR_CH1F_SHIFT (1U) +/*! RR_CH1F - Channel 1 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) + +#define LPCMP_RRSR_RR_CH2F_MASK (0x4U) +#define LPCMP_RRSR_RR_CH2F_SHIFT (2U) +/*! RR_CH2F - Channel 2 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) + +#define LPCMP_RRSR_RR_CH3F_MASK (0x8U) +#define LPCMP_RRSR_RR_CH3F_SHIFT (3U) +/*! RR_CH3F - Channel 3 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) + +#define LPCMP_RRSR_RR_CH4F_MASK (0x10U) +#define LPCMP_RRSR_RR_CH4F_SHIFT (4U) +/*! RR_CH4F - Channel 4 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) + +#define LPCMP_RRSR_RR_CH5F_MASK (0x20U) +#define LPCMP_RRSR_RR_CH5F_SHIFT (5U) +/*! RR_CH5F - Channel 5 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) + +#define LPCMP_RRSR_RR_CH6F_MASK (0x40U) +#define LPCMP_RRSR_RR_CH6F_SHIFT (6U) +/*! RR_CH6F - Channel 6 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) + +#define LPCMP_RRSR_RR_CH7F_MASK (0x80U) +#define LPCMP_RRSR_RR_CH7F_SHIFT (7U) +/*! RR_CH7F - Channel 7 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) +/*! @} */ + +/*! @name RRCR2 - Round Robin Control Register 2 */ +/*! @{ */ + +#define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU) +#define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U) +/*! RR_TIMER_RELOAD - Number of Sample Clocks */ +#define LPCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK) + +#define LPCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U) +#define LPCMP_RRCR2_RR_TIMER_EN_SHIFT (31U) +/*! RR_TIMER_EN - Round-Robin Internal Timer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPCMP_Register_Masks */ + + +/*! + * @} + */ /* end of group LPCMP_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPCMP_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPI2C.h new file mode 100644 index 000000000..d09c1db50 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPI2C.h @@ -0,0 +1,1428 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPI2C +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_LPI2C.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for LPI2C + * + * CMSIS Peripheral Access Layer for LPI2C + */ + +#if !defined(PERI_LPI2C_H_) +#define PERI_LPI2C_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ + __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ + __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ + __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ + __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ + __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_7[148]; + __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ + __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ + __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ + __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ + __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ + __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ + uint8_t RESERVED_12[4]; + __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Controller only, with standard feature set + * 0b0000000000000011..Controller and target, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) + +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) + +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +/*! MTXFIFO - Controller Transmit FIFO Size */ +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) + +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +/*! MRXFIFO - Controller Receive FIFO Size */ +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Controller Control */ +/*! @{ */ + +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Controller Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) + +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..No effect + * 0b1..Reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) + +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) + +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) + +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset transmit FIFO + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) + +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset receive FIFO + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Controller Status */ +/*! @{ */ + +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) + +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) + +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..No Stop or repeated Start generated + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Stop or repeated Start generated + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) + +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Stop condition generated + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) + +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..No effect + * 0b0..No unexpected NACK detected + * 0b1..Clear the flag + * 0b1..Unexpected NACK detected + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) + +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Controller did not lose arbitration + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Controller lost arbitration + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) + +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..FIFO error + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) + +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..No effect + * 0b0..Pin low timeout did not occur + * 0b1..Clear the flag + * 0b1..Pin low timeout occurred + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) + +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Matching data not received + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Matching data received + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) + +#define LPI2C_MSR_STF_MASK (0x8000U) +#define LPI2C_MSR_STF_SHIFT (15U) +/*! STF - Start Flag + * 0b0..No effect + * 0b0..Start condition not detected + * 0b1..Clear the flag + * 0b1..Start condition detected + */ +#define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) + +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Controller Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) + +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Controller Interrupt Enable */ +/*! @{ */ + +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) + +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) + +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) + +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) + +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) + +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) + +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) + +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) + +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +#define LPI2C_MIER_STIE_MASK (0x8000U) +#define LPI2C_MIER_STIE_SHIFT (15U) +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) +/*! @} */ + +/*! @name MDER - Controller DMA Enable */ +/*! @{ */ + +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) + +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Controller Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) + +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) + +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) + +#define LPI2C_MCFGR0_HRDIR_MASK (0x8U) +#define LPI2C_MCFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..HREQ pin is input (for LPI2C controller) + * 0b1..HREQ pin is output (for LPI2C target) + */ +#define LPI2C_MCFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK) + +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) + +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless MSR[DMF] is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +#define LPI2C_MCFGR0_RELAX_MASK (0x10000U) +#define LPI2C_MCFGR0_RELAX_SHIFT (16U) +/*! RELAX - Relaxed Mode + * 0b0..Normal transfer + * 0b1..Relaxed transfer + */ +#define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) + +#define LPI2C_MCFGR0_ABORT_MASK (0x20000U) +#define LPI2C_MCFGR0_ABORT_SHIFT (17U) +/*! ABORT - Abort Transfer + * 0b0..Normal transfer + * 0b1..Abort existing transfer and do not start a new one + */ +#define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) +/*! @} */ + +/*! @name MCFGR1 - Controller Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) + +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic Stop Generation + * 0b0..No effect + * 0b1..Stop automatically generated + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) + +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - Ignore NACK + * 0b0..No effect + * 0b1..Treat a received NACK as an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) + +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..SCL + * 0b1..SCL or SDA + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) + +#define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) +#define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition + */ +#define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) + +#define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) +#define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle + */ +#define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) + +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) + +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..Two-pin open drain mode + * 0b001..Two-pin output only mode (Ultra-Fast mode) + * 0b010..Two-pin push-pull mode + * 0b011..Four-pin push-pull mode + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target + * 0b110..Two-pin push-pull mode with separate LPI2C target + * 0b111..Four-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Controller Configuration 2 */ +/*! @{ */ + +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +/*! BUSIDLE - Bus Idle Timeout */ +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) + +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) + +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Controller Configuration 3 */ +/*! @{ */ + +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +/*! PINLOW - Pin Low Timeout */ +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Controller Data Match */ +/*! @{ */ + +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) + +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +/*! MATCH1 - Match 1 Value */ +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Controller Clock Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) + +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) + +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) + +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Controller Clock Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) + +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) + +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) + +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Controller FIFO Control */ +/*! @{ */ + +#define LPI2C_MFCR_TXWATER_MASK (0x3U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) + +#define LPI2C_MFCR_RXWATER_MASK (0x30000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Controller FIFO Status */ +/*! @{ */ + +#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) + +#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Controller Transmit Data */ +/*! @{ */ + +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) + +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit the value in DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate Stop condition on I2C bus + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Controller Receive Data */ +/*! @{ */ + +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) + +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name MRDROR - Controller Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_MRDROR_DATA_MASK (0xFFU) +#define LPI2C_MRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) + +#define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Target Control */ +/*! @{ */ + +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) + +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) + +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) + +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) + +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..STDR is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) + +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..SRDR is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Target Status */ +/*! @{ */ + +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) + +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) + +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) + +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) + +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..No effect + * 0b0..No repeated Start detected + * 0b1..Clear the flag + * 0b1..Repeated Start detected + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) + +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Stop detected + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) + +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b0..No effect + * 0b1..Bit error occurred + * 0b1..Clear the flag + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) + +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..FIFO error + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) + +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..ADDR0 matching address not received + * 0b1..ADDR0 matching address received + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) + +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) + +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) + +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) + +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Target Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) + +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Target Interrupt Enable */ +/*! @{ */ + +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) + +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) + +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) + +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) + +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) + +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) + +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) + +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) + +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) + +#define LPI2C_SIER_AM1IE_MASK (0x2000U) +#define LPI2C_SIER_AM1IE_SHIFT (13U) +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) + +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) + +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Target DMA Enable */ +/*! @{ */ + +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) + +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) + +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +#define LPI2C_SDER_RSDE_MASK (0x100U) +#define LPI2C_SDER_RSDE_SHIFT (8U) +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) + +#define LPI2C_SDER_SDDE_MASK (0x200U) +#define LPI2C_SDER_SDDE_SHIFT (9U) +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) +/*! @} */ + +/*! @name SCFGR0 - Target Configuration 0 */ +/*! @{ */ + +#define LPI2C_SCFGR0_RDREQ_MASK (0x1U) +#define LPI2C_SCFGR0_RDREQ_SHIFT (0U) +/*! RDREQ - Read Request + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) + +#define LPI2C_SCFGR0_RDACK_MASK (0x2U) +#define LPI2C_SCFGR0_RDACK_SHIFT (1U) +/*! RDACK - Read Acknowledge Flag + * 0b0..Read Request not acknowledged + * 0b1..Read Request acknowledged + */ +#define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) +/*! @} */ + +/*! @name SCFGR1 - Target Configuration 1 */ +/*! @{ */ + +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) + +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) + +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) + +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) + +#define LPI2C_SCFGR1_RXNACK_MASK (0x10U) +#define LPI2C_SCFGR1_RXNACK_SHIFT (4U) +/*! RXNACK - Receive NACK + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] + */ +#define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) + +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) + +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) + +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..SSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..SSR[TDF] is set whenever STDR is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) + +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Return received data, clear SSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear SSR[RDF] when SSR[AFV] is not set + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) + +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) + +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - HS Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) + +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +#define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) +#define LPI2C_SCFGR1_RXALL_SHIFT (24U) +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) + +#define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) +#define LPI2C_SCFGR1_RSCFG_SHIFT (25U) +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition + */ +#define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) + +#define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) +#define LPI2C_SCFGR1_SDCFG_SHIFT (26U) +/*! SDCFG - Stop Detect Configuration + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition + */ +#define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Target Configuration 2 */ +/*! @{ */ + +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +/*! CLKHOLD - Clock Hold Time */ +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) + +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) + +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) + +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Target Address Match */ +/*! @{ */ + +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +/*! ADDR0 - Address 0 Value */ +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) + +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +/*! ADDR1 - Address 1 Value */ +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Target Address Status */ +/*! @{ */ + +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +/*! RADDR - Received Address */ +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) + +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Target Transmit ACK */ +/*! @{ */ + +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Transmit ACK + * 0b1..Transmit NACK + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Target Transmit Data */ +/*! @{ */ + +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Target Receive Data */ +/*! @{ */ + +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +/*! DATA - Received Data */ +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) + +#define LPI2C_SRDR_RADDR_MASK (0x700U) +#define LPI2C_SRDR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) + +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) + +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + +/*! @name SRDROR - Target Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_SRDROR_DATA_MASK (0xFFU) +#define LPI2C_SRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) + +#define LPI2C_SRDROR_RADDR_MASK (0x700U) +#define LPI2C_SRDROR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) + +#define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) + +#define LPI2C_SRDROR_SOF_MASK (0x8000U) +#define LPI2C_SRDROR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First + */ +#define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPI2C_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPSPI.h new file mode 100644 index 000000000..30451e953 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPSPI.h @@ -0,0 +1,860 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPSPI +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_LPSPI.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for LPSPI + * + * CMSIS Peripheral Access Layer for LPSPI + */ + +#if !defined(PERI_LPSPI_H_) +#define PERI_LPSPI_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Size of Registers Arrays */ +#define LPSPI_TDBR_COUNT 128u +#define LPSPI_RDBR_COUNT 128u + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ + __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ + __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_5[896]; + __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ + __O uint32_t TDBR[LPSPI_TDBR_COUNT]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ + __I uint32_t RDBR[LPSPI_RDBR_COUNT]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) + +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) + +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) + +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) + +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +/*! PCSNUM - PCS Number */ +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) + +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) + +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) + +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) + +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) + +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) + +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..No effect + * 0b0..Not complete + * 0b1..Clear the flag + * 0b1..Complete + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) + +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..No effect + * 0b0..Not complete + * 0b1..Clear the flag + * 0b1..Complete + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) + +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..No effect + * 0b0..Not complete + * 0b1..Clear the flag + * 0b1..Complete + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) + +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..No effect + * 0b0..No underrun + * 0b1..Clear the flag + * 0b1..Underrun + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) + +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..No effect + * 0b0..No overflow + * 0b1..Clear the flag + * 0b1..Overflow + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) + +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..No effect + * 0b0..No match + * 0b1..Clear the flag + * 0b1..Match + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) + +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) + +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) + +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) + +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) + +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) + +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) + +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) + +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) + +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) + +#define LPSPI_DER_FCDE_MASK (0x200U) +#define LPSPI_DER_FCDE_SHIFT (9U) +/*! FCDE - Frame Complete DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration 0 */ +/*! @{ */ + +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) + +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) + +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..HREQ pin + * 0b1..Input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) + +#define LPSPI_CFGR0_HRDIR_MASK (0x8U) +#define LPSPI_CFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..Input + * 0b1..Output + */ +#define LPSPI_CFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK) + +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) + +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration 1 */ +/*! @{ */ + +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Controller Mode + * 0b0..Peripheral mode + * 0b1..Controller mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) + +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..SCK edge + * 0b1..Delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) + +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) + +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) + +#define LPSPI_CFGR1_PARTIAL_MASK (0x10U) +#define LPSPI_CFGR1_PARTIAL_SHIFT (4U) +/*! PARTIAL - Partial Enable + * 0b0..Discard + * 0b1..Store + */ +#define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) + +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..Active low + * 0b0001..Active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) + +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001.. + * 0b010..Match first data word with compare word + * 0b011..Match any data word with compare word + * 0b100..Sequential match, first data word + * 0b101..Sequential match, any data word + * 0b110..Match first data word (masked) with compare word (masked) + * 0b111..Match any data word (masked) with compare word (masked) + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) + +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) + +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Configuration + * 0b0..Retain last value + * 0b1..3-stated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) + +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] configured for chip select function + * 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match 0 */ +/*! @{ */ + +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match 1 */ +/*! @{ */ + +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +/*! MATCH1 - Match 1 Value */ +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration */ +/*! @{ */ + +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +/*! SCKDIV - SCK Divider */ +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) + +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +/*! DBT - Delay Between Transfers */ +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) + +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +/*! PCSSCK - PCS-to-SCK Delay */ +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) + +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +/*! SCKPCS - SCK-to-PCS Delay */ +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name CCR1 - Clock Configuration 1 */ +/*! @{ */ + +#define LPSPI_CCR1_SCKSET_MASK (0xFFU) +#define LPSPI_CCR1_SCKSET_SHIFT (0U) +/*! SCKSET - SCK Setup */ +#define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) + +#define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) +#define LPSPI_CCR1_SCKHLD_SHIFT (8U) +/*! SCKHLD - SCK Hold */ +#define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) + +#define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) +#define LPSPI_CCR1_PCSPCS_SHIFT (16U) +/*! PCSPCS - PCS to PCS Delay */ +#define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) + +#define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) +#define LPSPI_CCR1_SCKSCK_SHIFT (24U) +/*! SCKSCK - SCK Inter-Frame Delay */ +#define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control */ +/*! @{ */ + +#define LPSPI_FCR_TXWATER_MASK (0x3U) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) + +#define LPSPI_FCR_RXWATER_MASK (0x30000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPSPI_FSR_TXCOUNT_MASK (0x7U) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) + +#define LPSPI_FSR_RXCOUNT_MASK (0x70000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command */ +/*! @{ */ + +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +/*! FRAMESZ - Frame Size */ +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) + +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1-bit transfer + * 0b01..2-bit transfer + * 0b10..4-bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) + +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) + +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Mask receive data + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) + +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) + +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) + +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Disable byte swap + * 0b1..Enable byte swap + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) + +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..MSB first + * 0b1..LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) + +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using PCS[0] + * 0b01..Transfer using PCS[1] + * 0b10..Transfer using PCS[2] + * 0b11..Transfer using PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) + +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) + +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Captured + * 0b1..Changed + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) + +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..Inactive low + * 0b1..Inactive high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start of Frame + * 0b0..Subsequent data word or RX FIFO is empty (RXEMPTY=1). + * 0b1..First data word + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) + +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + +/*! @name RDROR - Receive Data Read Only */ +/*! @{ */ + +#define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) +/*! @} */ + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TCBR_DATA_SHIFT (0U) +/*! DATA - Command Data */ +#define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) +/*! @} */ + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) +/*! @} */ + +/*! @name RDBR - Receive Data Burst */ +/*! @{ */ + +#define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPSPI_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPTMR.h new file mode 100644 index 000000000..53dd6eed4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPTMR.h @@ -0,0 +1,279 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPTMR +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_LPTMR.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for LPTMR + * + * CMSIS Peripheral Access Layer for LPTMR + */ + +#if !defined(PERI_LPTMR_H_) +#define PERI_LPTMR_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ + __IO uint32_t CMR; /**< Compare, offset: 0x8 */ + __IO uint32_t CNR; /**< Counter, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Control Status */ +/*! @{ */ + +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) + +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +/*! TMS - Timer Mode Select + * 0b0..Time Counter + * 0b1..Pulse Counter + */ +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) + +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +/*! TFC - Timer Free-Running Counter + * 0b0..Reset when TCF asserts + * 0b1..Reset on overflow + */ +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) + +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +/*! TPP - Timer Pin Polarity + * 0b0..Active-high + * 0b1..Active-low + */ +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) + +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +/*! TPS - Timer Pin Select + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 + */ +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) + +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) + +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +/*! TCF - Timer Compare Flag + * 0b0..CNR != (CMR + 1) + * 0b0..No effect + * 0b1..CNR = (CMR + 1) + * 0b1..Clear the flag + */ +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +#define LPTMR_CSR_TDRE_MASK (0x100U) +#define LPTMR_CSR_TDRE_SHIFT (8U) +/*! TDRE - Timer DMA Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) +/*! @} */ + +/*! @name PSR - Prescaler and Glitch Filter */ +/*! @{ */ + +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +/*! PCS - Prescaler and Glitch Filter Clock Select + * 0b00..Clock 0 + * 0b01..Clock 1 + * 0b10..Clock 2 + * 0b11..Clock 3 + */ +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) + +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass + */ +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) + +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges + */ +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) +/*! @} */ + +/*! @name CMR - Compare */ +/*! @{ */ + +#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +/*! COMPARE - Compare Value */ +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) +/*! @} */ + +/*! @name CNR - Counter */ +/*! @{ */ + +#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +/*! COUNTER - Counter Value */ +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPTMR_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPUART.h new file mode 100644 index 000000000..59803584a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_LPUART.h @@ -0,0 +1,1133 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPUART +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_LPUART.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for LPUART + * + * CMSIS Peripheral Access Layer for LPUART + */ + +#if !defined(PERI_LPUART_H_) +#define PERI_LPUART_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ + __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ + __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ + __IO uint32_t STAT; /**< Status, offset: 0x14 */ + __IO uint32_t CTRL; /**< Control, offset: 0x18 */ + __IO uint32_t DATA; /**< Data, offset: 0x1C */ + __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ + __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ + __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ + __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ + __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with MODEM and IrDA support + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) + +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) + +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) + +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - Global */ +/*! @{ */ + +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - Pin Configuration */ +/*! @{ */ + +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger disabled + * 0b01..Input trigger used instead of the RXD pin input + * 0b10..Input trigger used instead of the CTS_B pin input + * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - Baud Rate */ +/*! @{ */ + +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +/*! SBR - Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) + +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit + * 0b1..Two stop bits + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) + +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) + +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) + +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) + +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Rising edge + * 0b1..Both rising and falling edges + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) + +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address match wake-up + * 0b01..Idle match wake-up + * 0b10..Match on and match off + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) + +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) + +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) + +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) + +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Results in an OSR of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) + * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) + * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) + * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) + * 0b00111..Results in an OSR of 8 + * 0b01000..Results in an OSR of 9 + * 0b01001..Results in an OSR of 10 + * 0b01010..Results in an OSR of 11 + * 0b01011..Results in an OSR of 12 + * 0b01100..Results in an OSR of 13 + * 0b01101..Results in an OSR of 14 + * 0b01110..Results in an OSR of 15 + * 0b01111..Results in an OSR of 16 + * 0b10000..Results in an OSR of 17 + * 0b10001..Results in an OSR of 18 + * 0b10010..Results in an OSR of 19 + * 0b10011..Results in an OSR of 20 + * 0b10100..Results in an OSR of 21 + * 0b10101..Results in an OSR of 22 + * 0b10110..Results in an OSR of 23 + * 0b10111..Results in an OSR of 24 + * 0b11000..Results in an OSR of 25 + * 0b11001..Results in an OSR of 26 + * 0b11010..Results in an OSR of 27 + * 0b11011..Results in an OSR of 28 + * 0b11100..Results in an OSR of 29 + * 0b11101..Results in an OSR of 30 + * 0b11110..Results in an OSR of 31 + * 0b11111..Results in an OSR of 32 + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) + +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-Bit Mode Select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters + * 0b1..Receiver and transmitter use 10-bit data characters + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) + +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) + +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define LPUART_STAT_LBKFE_MASK (0x1U) +#define LPUART_STAT_LBKFE_SHIFT (0U) +/*! LBKFE - LIN Break Flag Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) + +#define LPUART_STAT_AME_MASK (0x2U) +#define LPUART_STAT_AME_SHIFT (1U) +/*! AME - Address Mark Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) + +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..No effect + * 0b0..Not equal to MA2 + * 0b1..Clear the flag + * 0b1..Equal to MA2 + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) + +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..No effect + * 0b0..Not equal to MA1 + * 0b1..Clear the flag + * 0b1..Equal to MA1 + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) + +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No effect + * 0b0..No parity error detected + * 0b1..Clear the flag + * 0b1..Parity error detected + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) + +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No effect + * 0b0..No framing error detected (this does not guarantee that the framing is correct) + * 0b1..Clear the flag + * 0b1..Framing error detected + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) + +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No effect + * 0b0..No noise detected + * 0b1..Clear the flag + * 0b1..Noise detected + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) + +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No effect + * 0b0..No overrun + * 0b1..Clear the flag + * 0b1..Receive overrun (new LPUART data is lost) + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) + +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..Idle line detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Idle line not detected + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) + +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Equal to or less than watermark + * 0b1..Greater than watermark + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) + +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active + * 0b1..Transmitter idle + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) + +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Greater than watermark + * 0b1..Equal to or less than watermark + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) + +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..Idle, waiting for a start bit + * 0b1..Receiver active (RXD pin input not idle) + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) + +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) + +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..9 to 13 bit times + * 0b1..12 to 15 bit times + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) + +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..STAT[IDLE] does not become 1 + * 0b1..STAT[IDLE] becomes 1 + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) + +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Inverted + * 0b1..Not inverted + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) + +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) + +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..No effect + * 0b0..Not occurred + * 0b1..Clear the flag + * 0b1..Occurred + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) + +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity + * 0b1..Odd parity + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) + +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) + +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..After the start bit + * 0b1..After the stop bit + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) + +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) + +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit Or 8-Bit Mode Select + * 0b0..8-bit + * 0b1..9-bit + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) + +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Internal Loopback mode + * 0b1..Single-wire mode + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) + +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) + +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation: RXD and TXD use separate pins + * 0b1..Loop mode or Single-Wire mode + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) + +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) + +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..8-bit to 10-bit + * 0b1..7-bit + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) + +#define LPUART_CTRL_SWAP_MASK (0x1000U) +#define LPUART_CTRL_SWAP_SHIFT (12U) +/*! SWAP - TXD and RXD Pin Swap + * 0b0..Use the standard way + * 0b1..Swap + */ +#define LPUART_CTRL_SWAP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SWAP_SHIFT)) & LPUART_CTRL_SWAP_MASK) + +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 (MA2F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) + +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 (MA1F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) + +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation + * 0b1..Queue break character(s) to be sent + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) + +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wake-Up Control + * 0b0..Normal receiver operation + * 0b1..LPUART receiver in standby, waiting for a wake-up condition + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) + +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) + +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) + +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) + +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) + +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) + +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) + +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) + +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) + +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) + +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) + +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Not inverted + * 0b1..Inverted + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) + +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..Input + * 0b1..Output + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) + +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +/*! R9T8 - Receive Bit 9 Transmit Bit 8 */ +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) + +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +/*! R8T9 - Receive Bit 8 Transmit Bit 9 */ +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) + +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) + +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) + +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) + +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) + +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) + +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) + +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) + +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) + +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) + +#define LPUART_DATA_LINBRK_MASK (0x400U) +#define LPUART_DATA_LINBRK_SHIFT (10U) +/*! LINBRK - LIN Break + * 0b0..Not detected + * 0b1..Detected + */ +#define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) + +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Not idle + * 0b1..Idle + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) + +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Valid data + * 0b1..Invalid data and empty + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) + +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error Transmit Special Character + * 0b0..Received without a frame error on reads or transmits a normal character on writes + * 0b1..Received with a frame error on reads or transmits an idle or break character on writes + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) + +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - Parity Error + * 0b0..Received without a parity error + * 0b1..Received with a parity error + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) + +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - Noisy Data Received + * 0b0..Received without noise + * 0b1..Received with noise + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - Match Address */ +/*! @{ */ + +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +/*! MA1 - Match Address 1 */ +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) + +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +/*! MA2 - Match Address 2 */ +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - MODEM IrDA */ +/*! @{ */ + +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter CTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) + +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) + +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter RTS Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) + +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) + +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..Sampled at the start of each character + * 0b1..Sampled when the transmitter is idle + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) + +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..The CTS_B pin + * 0b1..An internal connection to the receiver address match result + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) + +#define LPUART_MODIR_RTSWATER_MASK (0x300U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +/*! RTSWATER - Receive RTS Configuration */ +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) + +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter Narrow Pulse + * 0b00..1 / OSR + * 0b01..2 / OSR + * 0b10..3 / OSR + * 0b11..4 / OSR + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) + +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - IR Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - FIFO */ +/*! @{ */ + +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) + +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) + +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) + +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) + +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) + +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) + +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) + +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) + +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) + +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver FIFO Underflow Flag + * 0b0..No effect + * 0b0..No underflow + * 0b1..Clear the flag + * 0b1..Underflow + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) + +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter FIFO Overflow Flag + * 0b0..No effect + * 0b0..No overflow + * 0b1..Clear the flag + * 0b1..Overflow + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) + +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) + +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - Watermark */ +/*! @{ */ + +#define LPUART_WATER_TXWATER_MASK (0x3U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit Watermark */ +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) + +#define LPUART_WATER_TXCOUNT_MASK (0x700U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +/*! TXCOUNT - Transmit Counter */ +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) + +#define LPUART_WATER_RXWATER_MASK (0x30000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +/*! RXWATER - Receive Watermark */ +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) + +#define LPUART_WATER_RXCOUNT_MASK (0x7000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Counter */ +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + +/*! @name DATARO - Data Read-Only */ +/*! @{ */ + +#define LPUART_DATARO_DATA_MASK (0xFFFFU) +#define LPUART_DATARO_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPUART_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MAU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MAU.h new file mode 100644 index 000000000..5856b158f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MAU.h @@ -0,0 +1,598 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for MAU +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_MAU.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MAU + * + * CMSIS Peripheral Access Layer for MAU + */ + +#if !defined(PERI_MAU_H_) +#define PERI_MAU_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- MAU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAU_Peripheral_Access_Layer MAU Peripheral Access Layer + * @{ + */ + +/** MAU - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2064]; + __IO uint32_t SYS_CTLR; /**< System Control, offset: 0x810 */ + __IO uint32_t GEXP_STATUS_IE; /**< General Exception Status Interrupt Enable, offset: 0x814 */ + __IO uint32_t GEXP_STATUS; /**< General Exception Status, offset: 0x818 */ + uint8_t RESERVED_1[20]; + __IO uint32_t OP_CTRL; /**< Operation Control, offset: 0x830 */ + uint8_t RESERVED_2[4]; + __IO uint32_t RES_STATUS_IE; /**< Result Status Interrupt Enable, offset: 0x838 */ + __IO uint32_t RES_STATUS; /**< Result Status, offset: 0x83C */ + __IO uint32_t RES0; /**< Result Register 0, offset: 0x840 */ + __IO uint32_t RES1; /**< Result Register 1, offset: 0x844 */ + __IO uint32_t RES2; /**< Result Register 2, offset: 0x848 */ + __IO uint32_t RES3; /**< Result Register 3, offset: 0x84C */ +} MAU_Type; + +/* ---------------------------------------------------------------------------- + -- MAU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAU_Register_Masks MAU Register Masks + * @{ + */ + +/*! @name SYS_CTLR - System Control */ +/*! @{ */ + +#define MAU_SYS_CTLR_ACG_EN_MASK (0x1U) +#define MAU_SYS_CTLR_ACG_EN_SHIFT (0U) +/*! ACG_EN - Automatic Clock Gating Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_SYS_CTLR_ACG_EN(x) (((uint32_t)(((uint32_t)(x)) << MAU_SYS_CTLR_ACG_EN_SHIFT)) & MAU_SYS_CTLR_ACG_EN_MASK) +/*! @} */ + +/*! @name GEXP_STATUS_IE - General Exception Status Interrupt Enable */ +/*! @{ */ + +#define MAU_GEXP_STATUS_IE_ERROR_IE_MASK (0x1U) +#define MAU_GEXP_STATUS_IE_ERROR_IE_SHIFT (0U) +/*! ERROR_IE - Direct operation Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_GEXP_STATUS_IE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << MAU_GEXP_STATUS_IE_ERROR_IE_SHIFT)) & MAU_GEXP_STATUS_IE_ERROR_IE_MASK) +/*! @} */ + +/*! @name GEXP_STATUS - General Exception Status */ +/*! @{ */ + +#define MAU_GEXP_STATUS_ERROR_MASK (0x1U) +#define MAU_GEXP_STATUS_ERROR_SHIFT (0U) +/*! ERROR - Direct operation Error + * 0b0..No error is generated. + * 0b1..An error is generated. + */ +#define MAU_GEXP_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MAU_GEXP_STATUS_ERROR_SHIFT)) & MAU_GEXP_STATUS_ERROR_MASK) +/*! @} */ + +/*! @name OP_CTRL - Operation Control */ +/*! @{ */ + +#define MAU_OP_CTRL_OVDT_EN_RES0_MASK (0x1U) +#define MAU_OP_CTRL_OVDT_EN_RES0_SHIFT (0U) +/*! OVDT_EN_RES0 - Override RES0 Data Type Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_OP_CTRL_OVDT_EN_RES0(x) (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_EN_RES0_SHIFT)) & MAU_OP_CTRL_OVDT_EN_RES0_MASK) + +#define MAU_OP_CTRL_OVDT_RES0_MASK (0x6U) +#define MAU_OP_CTRL_OVDT_RES0_SHIFT (1U) +/*! OVDT_RES0 - Override RES0 Data Type + * 0b00..UINT + * 0b01..INT + * 0b10..Q1.X + * 0b11..FLOAT + */ +#define MAU_OP_CTRL_OVDT_RES0(x) (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_RES0_SHIFT)) & MAU_OP_CTRL_OVDT_RES0_MASK) + +#define MAU_OP_CTRL_OVDT_EN_RES1_MASK (0x100U) +#define MAU_OP_CTRL_OVDT_EN_RES1_SHIFT (8U) +/*! OVDT_EN_RES1 - Override RES1 Data Type Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_OP_CTRL_OVDT_EN_RES1(x) (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_EN_RES1_SHIFT)) & MAU_OP_CTRL_OVDT_EN_RES1_MASK) + +#define MAU_OP_CTRL_OVDT_RES1_MASK (0x600U) +#define MAU_OP_CTRL_OVDT_RES1_SHIFT (9U) +/*! OVDT_RES1 - Override RES1 Data Type + * 0b00..UINT + * 0b01..INT + * 0b10..Q1.X + * 0b11..FLOAT + */ +#define MAU_OP_CTRL_OVDT_RES1(x) (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_RES1_SHIFT)) & MAU_OP_CTRL_OVDT_RES1_MASK) + +#define MAU_OP_CTRL_OVDT_EN_RES2_MASK (0x10000U) +#define MAU_OP_CTRL_OVDT_EN_RES2_SHIFT (16U) +/*! OVDT_EN_RES2 - Override RES2 Data Type Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_OP_CTRL_OVDT_EN_RES2(x) (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_EN_RES2_SHIFT)) & MAU_OP_CTRL_OVDT_EN_RES2_MASK) + +#define MAU_OP_CTRL_OVDT_RES2_MASK (0x60000U) +#define MAU_OP_CTRL_OVDT_RES2_SHIFT (17U) +/*! OVDT_RES2 - Override RES2 Data Type + * 0b00..UINT + * 0b01..INT + * 0b10..Q1.X + * 0b11..FLOAT + */ +#define MAU_OP_CTRL_OVDT_RES2(x) (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_RES2_SHIFT)) & MAU_OP_CTRL_OVDT_RES2_MASK) + +#define MAU_OP_CTRL_OVDT_EN_RES3_MASK (0x1000000U) +#define MAU_OP_CTRL_OVDT_EN_RES3_SHIFT (24U) +/*! OVDT_EN_RES3 - Override RES3 Data Type Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_OP_CTRL_OVDT_EN_RES3(x) (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_EN_RES3_SHIFT)) & MAU_OP_CTRL_OVDT_EN_RES3_MASK) + +#define MAU_OP_CTRL_OVDT_RES3_MASK (0x6000000U) +#define MAU_OP_CTRL_OVDT_RES3_SHIFT (25U) +/*! OVDT_RES3 - Override RES3 Data Type + * 0b00..UINT + * 0b01..INT + * 0b10..Q1.X + * 0b11..FLOAT + */ +#define MAU_OP_CTRL_OVDT_RES3(x) (((uint32_t)(((uint32_t)(x)) << MAU_OP_CTRL_OVDT_RES3_SHIFT)) & MAU_OP_CTRL_OVDT_RES3_MASK) +/*! @} */ + +/*! @name RES_STATUS_IE - Result Status Interrupt Enable */ +/*! @{ */ + +#define MAU_RES_STATUS_IE_RES0_IE_MASK (0x1U) +#define MAU_RES_STATUS_IE_RES0_IE_SHIFT (0U) +/*! RES0_IE - RES0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_RES_STATUS_IE_RES0_IE(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_IE_RES0_IE_SHIFT)) & MAU_RES_STATUS_IE_RES0_IE_MASK) + +#define MAU_RES_STATUS_IE_RES1_IE_MASK (0x2U) +#define MAU_RES_STATUS_IE_RES1_IE_SHIFT (1U) +/*! RES1_IE - RES1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_RES_STATUS_IE_RES1_IE(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_IE_RES1_IE_SHIFT)) & MAU_RES_STATUS_IE_RES1_IE_MASK) + +#define MAU_RES_STATUS_IE_RES2_IE_MASK (0x4U) +#define MAU_RES_STATUS_IE_RES2_IE_SHIFT (2U) +/*! RES2_IE - RES2 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_RES_STATUS_IE_RES2_IE(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_IE_RES2_IE_SHIFT)) & MAU_RES_STATUS_IE_RES2_IE_MASK) + +#define MAU_RES_STATUS_IE_RES3_IE_MASK (0x8U) +#define MAU_RES_STATUS_IE_RES3_IE_SHIFT (3U) +/*! RES3_IE - RES3 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MAU_RES_STATUS_IE_RES3_IE(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_IE_RES3_IE_SHIFT)) & MAU_RES_STATUS_IE_RES3_IE_MASK) +/*! @} */ + +/*! @name RES_STATUS - Result Status */ +/*! @{ */ + +#define MAU_RES_STATUS_RES0_NX_MASK (0x1U) +#define MAU_RES_STATUS_RES0_NX_SHIFT (0U) +/*! RES0_NX - RES0 IEEE Inexact Flag + * 0b0..The result is not rounded. + * 0b1..The result is rounded, and as a result some digits lost. + */ +#define MAU_RES_STATUS_RES0_NX(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_NX_SHIFT)) & MAU_RES_STATUS_RES0_NX_MASK) + +#define MAU_RES_STATUS_RES0_UF_MASK (0x2U) +#define MAU_RES_STATUS_RES0_UF_SHIFT (1U) +/*! RES0_UF - RES0 IEEE Underflow Flag + * 0b0..No tiny non-zero result is detected. + * 0b1..A tiny non-zero result is detected. + */ +#define MAU_RES_STATUS_RES0_UF(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_UF_SHIFT)) & MAU_RES_STATUS_RES0_UF_MASK) + +#define MAU_RES_STATUS_RES0_OF_MASK (0x4U) +#define MAU_RES_STATUS_RES0_OF_SHIFT (2U) +/*! RES0_OF - RES0 IEEE Overflow Flag + * 0b0..The result format's largest finite number is not exceeded. + * 0b1..The result format's largest finite number is exceeded. + */ +#define MAU_RES_STATUS_RES0_OF(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_OF_SHIFT)) & MAU_RES_STATUS_RES0_OF_MASK) + +#define MAU_RES_STATUS_RES0_DZ_MASK (0x8U) +#define MAU_RES_STATUS_RES0_DZ_SHIFT (3U) +/*! RES0_DZ - RES0 IEEE Divide by Zero Flag + * 0b0..No exact infinite result is defined for an operation on finite operands. + * 0b1..An exact infinite result is defined for an operation on finite operands. + */ +#define MAU_RES_STATUS_RES0_DZ(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_DZ_SHIFT)) & MAU_RES_STATUS_RES0_DZ_MASK) + +#define MAU_RES_STATUS_RES0_NV_MASK (0x10U) +#define MAU_RES_STATUS_RES0_NV_SHIFT (4U) +/*! RES0_NV - RES0 IEEE Invalid Flag + * 0b0..There is usefully definable result. + * 0b1..There is no usefully definable result. + */ +#define MAU_RES_STATUS_RES0_NV(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_NV_SHIFT)) & MAU_RES_STATUS_RES0_NV_MASK) + +#define MAU_RES_STATUS_RES0_ERR_MASK (0x20U) +#define MAU_RES_STATUS_RES0_ERR_SHIFT (5U) +/*! RES0_ERR - RES0 Indirect Operation Error Flag + * 0b0..No invalid indirect operation is detected. + * 0b1..An invalid indirect operation error is detected. + */ +#define MAU_RES_STATUS_RES0_ERR(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_ERR_SHIFT)) & MAU_RES_STATUS_RES0_ERR_MASK) + +#define MAU_RES_STATUS_RES0_OVWR_MASK (0x40U) +#define MAU_RES_STATUS_RES0_OVWR_SHIFT (6U) +/*! RES0_OVWR - RES0 Overwrite Flag + * 0b0..The value of RES0 has been read. + * 0b1..The value of RES0 has not been read yet and is overwritten by a new MAUWRAP result. + */ +#define MAU_RES_STATUS_RES0_OVWR(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_OVWR_SHIFT)) & MAU_RES_STATUS_RES0_OVWR_MASK) + +#define MAU_RES_STATUS_RES0_FULL_MASK (0x80U) +#define MAU_RES_STATUS_RES0_FULL_SHIFT (7U) +/*! RES0_FULL - RES0 Full Flag + * 0b0..RES0 has not updated and cannot be read. + * 0b1..RES0 has updated and can be read. + */ +#define MAU_RES_STATUS_RES0_FULL(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES0_FULL_SHIFT)) & MAU_RES_STATUS_RES0_FULL_MASK) + +#define MAU_RES_STATUS_RES1_NX_MASK (0x100U) +#define MAU_RES_STATUS_RES1_NX_SHIFT (8U) +/*! RES1_NX - RES1 IEEE Inexact Flag + * 0b0..The result is not rounded. + * 0b1..The result is rounded, and as a result some digits lost. + */ +#define MAU_RES_STATUS_RES1_NX(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_NX_SHIFT)) & MAU_RES_STATUS_RES1_NX_MASK) + +#define MAU_RES_STATUS_RES1_UF_MASK (0x200U) +#define MAU_RES_STATUS_RES1_UF_SHIFT (9U) +/*! RES1_UF - RES1 IEEE Underflow Flag + * 0b0..No tiny non-zero result is detected. + * 0b1..A tiny non-zero result is detected. + */ +#define MAU_RES_STATUS_RES1_UF(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_UF_SHIFT)) & MAU_RES_STATUS_RES1_UF_MASK) + +#define MAU_RES_STATUS_RES1_OF_MASK (0x400U) +#define MAU_RES_STATUS_RES1_OF_SHIFT (10U) +/*! RES1_OF - RES1 IEEE Overflow Flag + * 0b0..The result format's largest finite number is not exceeded. + * 0b1..The result format's largest finite number is exceeded. + */ +#define MAU_RES_STATUS_RES1_OF(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_OF_SHIFT)) & MAU_RES_STATUS_RES1_OF_MASK) + +#define MAU_RES_STATUS_RES1_DZ_MASK (0x800U) +#define MAU_RES_STATUS_RES1_DZ_SHIFT (11U) +/*! RES1_DZ - RES1 IEEE Divide by Zero Flag + * 0b0..No exact infinite result is defined for an operation on finite operands. + * 0b1..An exact infinite result is defined for an operation on finite operands. + */ +#define MAU_RES_STATUS_RES1_DZ(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_DZ_SHIFT)) & MAU_RES_STATUS_RES1_DZ_MASK) + +#define MAU_RES_STATUS_RES1_NV_MASK (0x1000U) +#define MAU_RES_STATUS_RES1_NV_SHIFT (12U) +/*! RES1_NV - RES1 IEEE Invalid Flag + * 0b0..There is usefully definable result. + * 0b1..There is no usefully definable result. + */ +#define MAU_RES_STATUS_RES1_NV(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_NV_SHIFT)) & MAU_RES_STATUS_RES1_NV_MASK) + +#define MAU_RES_STATUS_RES1_ERR_MASK (0x2000U) +#define MAU_RES_STATUS_RES1_ERR_SHIFT (13U) +/*! RES1_ERR - RES1 Indirect Operation Error Flag + * 0b0..No invalid indirect operation is detected. + * 0b1..An invalid indirect operation error is detected. + */ +#define MAU_RES_STATUS_RES1_ERR(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_ERR_SHIFT)) & MAU_RES_STATUS_RES1_ERR_MASK) + +#define MAU_RES_STATUS_RES1_OVWR_MASK (0x4000U) +#define MAU_RES_STATUS_RES1_OVWR_SHIFT (14U) +/*! RES1_OVWR - RES1 Overwrite Flag + * 0b0..The value of RES1 has been read. + * 0b1..The value of RES1 has not been read yet and is overwritten by a new MAUWRAP result. + */ +#define MAU_RES_STATUS_RES1_OVWR(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_OVWR_SHIFT)) & MAU_RES_STATUS_RES1_OVWR_MASK) + +#define MAU_RES_STATUS_RES1_FULL_MASK (0x8000U) +#define MAU_RES_STATUS_RES1_FULL_SHIFT (15U) +/*! RES1_FULL - RES1 Full Flag + * 0b0..RES1 has not updated and cannot be read. + * 0b1..RES1 has updated and can be read. + */ +#define MAU_RES_STATUS_RES1_FULL(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES1_FULL_SHIFT)) & MAU_RES_STATUS_RES1_FULL_MASK) + +#define MAU_RES_STATUS_RES2_NX_MASK (0x10000U) +#define MAU_RES_STATUS_RES2_NX_SHIFT (16U) +/*! RES2_NX - RES2 IEEE Inexact Flag + * 0b0..The result is not rounded. + * 0b1..The result is rounded, and as a result some digits lost. + */ +#define MAU_RES_STATUS_RES2_NX(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_NX_SHIFT)) & MAU_RES_STATUS_RES2_NX_MASK) + +#define MAU_RES_STATUS_RES2_UF_MASK (0x20000U) +#define MAU_RES_STATUS_RES2_UF_SHIFT (17U) +/*! RES2_UF - RES2 IEEE Underflow Flag + * 0b0..No tiny non-zero result is detected. + * 0b1..A tiny non-zero result is detected. + */ +#define MAU_RES_STATUS_RES2_UF(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_UF_SHIFT)) & MAU_RES_STATUS_RES2_UF_MASK) + +#define MAU_RES_STATUS_RES2_OF_MASK (0x40000U) +#define MAU_RES_STATUS_RES2_OF_SHIFT (18U) +/*! RES2_OF - RES2 IEEE Overflow Flag + * 0b0..The result format's largest finite number is not exceeded. + * 0b1..The result format's largest finite number is exceeded. + */ +#define MAU_RES_STATUS_RES2_OF(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_OF_SHIFT)) & MAU_RES_STATUS_RES2_OF_MASK) + +#define MAU_RES_STATUS_RES2_DZ_MASK (0x80000U) +#define MAU_RES_STATUS_RES2_DZ_SHIFT (19U) +/*! RES2_DZ - RES2 IEEE Divide by Zero Flag + * 0b0..No exact infinite result is defined for an operation on finite operands. + * 0b1..An exact infinite result is defined for an operation on finite operands. + */ +#define MAU_RES_STATUS_RES2_DZ(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_DZ_SHIFT)) & MAU_RES_STATUS_RES2_DZ_MASK) + +#define MAU_RES_STATUS_RES2_NV_MASK (0x100000U) +#define MAU_RES_STATUS_RES2_NV_SHIFT (20U) +/*! RES2_NV - RES2 IEEE Invalid Flag + * 0b0..There is usefully definable result. + * 0b1..There is no usefully definable result. + */ +#define MAU_RES_STATUS_RES2_NV(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_NV_SHIFT)) & MAU_RES_STATUS_RES2_NV_MASK) + +#define MAU_RES_STATUS_RES2_ERR_MASK (0x200000U) +#define MAU_RES_STATUS_RES2_ERR_SHIFT (21U) +/*! RES2_ERR - RES2 Indirect Operation Error Flag + * 0b0..No invalid indirect operation is detected. + * 0b1..An invalid indirect operation error is detected. + */ +#define MAU_RES_STATUS_RES2_ERR(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_ERR_SHIFT)) & MAU_RES_STATUS_RES2_ERR_MASK) + +#define MAU_RES_STATUS_RES2_OVWR_MASK (0x400000U) +#define MAU_RES_STATUS_RES2_OVWR_SHIFT (22U) +/*! RES2_OVWR - RES2 Overwrite Flag + * 0b0..The value of RES2 has been read. + * 0b1..The value of RES2 has not been read yet and is overwritten by a new MAUWRAP result. + */ +#define MAU_RES_STATUS_RES2_OVWR(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_OVWR_SHIFT)) & MAU_RES_STATUS_RES2_OVWR_MASK) + +#define MAU_RES_STATUS_RES2_FULL_MASK (0x800000U) +#define MAU_RES_STATUS_RES2_FULL_SHIFT (23U) +/*! RES2_FULL - RES2 Full Flag + * 0b0..RES2 has not updated and cannot be read. + * 0b1..RES2 has updated and can be read. + */ +#define MAU_RES_STATUS_RES2_FULL(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES2_FULL_SHIFT)) & MAU_RES_STATUS_RES2_FULL_MASK) + +#define MAU_RES_STATUS_RES3_NX_MASK (0x1000000U) +#define MAU_RES_STATUS_RES3_NX_SHIFT (24U) +/*! RES3_NX - RES3 IEEE Inexact Flag + * 0b0..The result is not rounded. + * 0b1..The result is rounded, and as a result some digits lost. + */ +#define MAU_RES_STATUS_RES3_NX(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_NX_SHIFT)) & MAU_RES_STATUS_RES3_NX_MASK) + +#define MAU_RES_STATUS_RES3_UF_MASK (0x2000000U) +#define MAU_RES_STATUS_RES3_UF_SHIFT (25U) +/*! RES3_UF - RES3 IEEE Underflow Flag + * 0b0..No tiny non-zero result is detected. + * 0b1..A tiny non-zero result is detected. + */ +#define MAU_RES_STATUS_RES3_UF(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_UF_SHIFT)) & MAU_RES_STATUS_RES3_UF_MASK) + +#define MAU_RES_STATUS_RES3_OF_MASK (0x4000000U) +#define MAU_RES_STATUS_RES3_OF_SHIFT (26U) +/*! RES3_OF - RES3 IEEE Overflow Flag + * 0b0..The result format's largest finite number is not exceeded. + * 0b1..The result format's largest finite number is exceeded. + */ +#define MAU_RES_STATUS_RES3_OF(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_OF_SHIFT)) & MAU_RES_STATUS_RES3_OF_MASK) + +#define MAU_RES_STATUS_RES3_DZ_MASK (0x8000000U) +#define MAU_RES_STATUS_RES3_DZ_SHIFT (27U) +/*! RES3_DZ - RES3 IEEE Divide by Zero Flag + * 0b0..No exact infinite result is defined for an operation on finite operands. + * 0b1..An exact infinite result is defined for an operation on finite operands. + */ +#define MAU_RES_STATUS_RES3_DZ(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_DZ_SHIFT)) & MAU_RES_STATUS_RES3_DZ_MASK) + +#define MAU_RES_STATUS_RES3_NV_MASK (0x10000000U) +#define MAU_RES_STATUS_RES3_NV_SHIFT (28U) +/*! RES3_NV - RES3 IEEE Invalid Flag + * 0b0..There is usefully definable result. + * 0b1..There is no usefully definable result. + */ +#define MAU_RES_STATUS_RES3_NV(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_NV_SHIFT)) & MAU_RES_STATUS_RES3_NV_MASK) + +#define MAU_RES_STATUS_RES3_ERR_MASK (0x20000000U) +#define MAU_RES_STATUS_RES3_ERR_SHIFT (29U) +/*! RES3_ERR - RES3 Indirect Operation Error Flag + * 0b0..No invalid indirect operation is detected. + * 0b1..An invalid indirect operation error is detected. + */ +#define MAU_RES_STATUS_RES3_ERR(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_ERR_SHIFT)) & MAU_RES_STATUS_RES3_ERR_MASK) + +#define MAU_RES_STATUS_RES3_OVWR_MASK (0x40000000U) +#define MAU_RES_STATUS_RES3_OVWR_SHIFT (30U) +/*! RES3_OVWR - RES3 Overwrite Flag + * 0b0..The value of RES3 has been read. + * 0b1..The value of RES3 has not been read yet and is overwritten by a new MAUWRAP result. + */ +#define MAU_RES_STATUS_RES3_OVWR(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_OVWR_SHIFT)) & MAU_RES_STATUS_RES3_OVWR_MASK) + +#define MAU_RES_STATUS_RES3_FULL_MASK (0x80000000U) +#define MAU_RES_STATUS_RES3_FULL_SHIFT (31U) +/*! RES3_FULL - RES3 Full Flag + * 0b0..RES3 has not updated and cannot be read. + * 0b1..RES3 has updated and can be read. + */ +#define MAU_RES_STATUS_RES3_FULL(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES_STATUS_RES3_FULL_SHIFT)) & MAU_RES_STATUS_RES3_FULL_MASK) +/*! @} */ + +/*! @name RES0 - Result Register 0 */ +/*! @{ */ + +#define MAU_RES0_MAU_RES0_MASK (0xFFFFFFFFU) +#define MAU_RES0_MAU_RES0_SHIFT (0U) +/*! MAU_RES0 - MAUWRAP Result Register 0 */ +#define MAU_RES0_MAU_RES0(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES0_MAU_RES0_SHIFT)) & MAU_RES0_MAU_RES0_MASK) +/*! @} */ + +/*! @name RES1 - Result Register 1 */ +/*! @{ */ + +#define MAU_RES1_MAU_RES1_MASK (0xFFFFFFFFU) +#define MAU_RES1_MAU_RES1_SHIFT (0U) +/*! MAU_RES1 - MAUWRAP Result Register 1 */ +#define MAU_RES1_MAU_RES1(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES1_MAU_RES1_SHIFT)) & MAU_RES1_MAU_RES1_MASK) +/*! @} */ + +/*! @name RES2 - Result Register 2 */ +/*! @{ */ + +#define MAU_RES2_MAU_RES2_MASK (0xFFFFFFFFU) +#define MAU_RES2_MAU_RES2_SHIFT (0U) +/*! MAU_RES2 - MAUWRAP Result Register 2 */ +#define MAU_RES2_MAU_RES2(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES2_MAU_RES2_SHIFT)) & MAU_RES2_MAU_RES2_MASK) +/*! @} */ + +/*! @name RES3 - Result Register 3 */ +/*! @{ */ + +#define MAU_RES3_MAU_RES3_MASK (0xFFFFFFFFU) +#define MAU_RES3_MAU_RES3_SHIFT (0U) +/*! MAU_RES3 - MAUWRAP Result Register 3 */ +#define MAU_RES3_MAU_RES3(x) (((uint32_t)(((uint32_t)(x)) << MAU_RES3_MAU_RES3_SHIFT)) & MAU_RES3_MAU_RES3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MAU_Register_Masks */ + + +/*! + * @} + */ /* end of group MAU_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_MAU_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MRCC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MRCC.h new file mode 100644 index 000000000..eb981b941 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_MRCC.h @@ -0,0 +1,2600 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for MRCC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_MRCC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MRCC + * + * CMSIS Peripheral Access Layer for MRCC + */ + +#if !defined(PERI_MRCC_H_) +#define PERI_MRCC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- MRCC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRCC_Peripheral_Access_Layer MRCC Peripheral Access Layer + * @{ + */ + +/** MRCC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MRCC_GLB_RST0; /**< Peripheral Reset Control 0, offset: 0x0 */ + __O uint32_t MRCC_GLB_RST0_SET; /**< Peripheral Reset Control Set 0, offset: 0x4 */ + __O uint32_t MRCC_GLB_RST0_CLR; /**< Peripheral Reset Control Clear 0, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t MRCC_GLB_RST1; /**< Peripheral Reset Control 1, offset: 0x10 */ + __O uint32_t MRCC_GLB_RST1_SET; /**< Peripheral Reset Control Set 1, offset: 0x14 */ + __O uint32_t MRCC_GLB_RST1_CLR; /**< Peripheral Reset Control Clear 1, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MRCC_GLB_RST2; /**< Peripheral Reset Control 2, offset: 0x20 */ + __O uint32_t MRCC_GLB_RST2_SET; /**< Peripheral Reset Control Set 2, offset: 0x24 */ + __O uint32_t MRCC_GLB_RST2_CLR; /**< Peripheral Reset Control Clear 2, offset: 0x28 */ + uint8_t RESERVED_2[20]; + __IO uint32_t MRCC_GLB_CC0; /**< AHB Clock Control 0, offset: 0x40 */ + __O uint32_t MRCC_GLB_CC0_SET; /**< AHB Clock Control Set 0, offset: 0x44 */ + __O uint32_t MRCC_GLB_CC0_CLR; /**< AHB Clock Control Clear 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MRCC_GLB_CC1; /**< AHB Clock Control 1, offset: 0x50 */ + __O uint32_t MRCC_GLB_CC1_SET; /**< AHB Clock Control Set 1, offset: 0x54 */ + __O uint32_t MRCC_GLB_CC1_CLR; /**< AHB Clock Control Clear 1, offset: 0x58 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MRCC_GLB_CC2; /**< AHB Clock Control 2, offset: 0x60 */ + __O uint32_t MRCC_GLB_CC2_SET; /**< AHB Clock Control Set 2, offset: 0x64 */ + __O uint32_t MRCC_GLB_CC2_CLR; /**< AHB Clock Control Clear 2, offset: 0x68 */ + uint8_t RESERVED_5[20]; + __IO uint32_t MRCC_GLB_ACC0; /**< Control Automatic Clock Gating 0, offset: 0x80 */ + __IO uint32_t MRCC_GLB_ACC1; /**< Control Automatic Clock Gating 1, offset: 0x84 */ + __IO uint32_t MRCC_GLB_ACC2; /**< Control Automatic Clock Gating 2, offset: 0x88 */ + uint8_t RESERVED_6[20]; + __IO uint32_t MRCC_CTIMER0_CLKSEL; /**< CTIMER0 clock selection control, offset: 0xA0 */ + __IO uint32_t MRCC_CTIMER0_CLKDIV; /**< CTIMER0 clock divider control, offset: 0xA4 */ + __IO uint32_t MRCC_CTIMER1_CLKSEL; /**< CTIMER1 clock selection control, offset: 0xA8 */ + __IO uint32_t MRCC_CTIMER1_CLKDIV; /**< CTIMER1 clock divider control, offset: 0xAC */ + __IO uint32_t MRCC_CTIMER2_CLKSEL; /**< CTIMER2 clock selection control, offset: 0xB0 */ + __IO uint32_t MRCC_CTIMER2_CLKDIV; /**< CTIMER2 clock divider control, offset: 0xB4 */ + uint8_t RESERVED_7[4]; + __IO uint32_t MRCC_WWDT0_CLKDIV; /**< WWDT0 clock divider control, offset: 0xBC */ + __IO uint32_t MRCC_LPI2C0_CLKSEL; /**< LPI2C0 clock selection control, offset: 0xC0 */ + __IO uint32_t MRCC_LPI2C0_CLKDIV; /**< LPI2C0 clock divider control, offset: 0xC4 */ + __IO uint32_t MRCC_LPI2C1_CLKSEL; /**< LPI2C1 clock selection control, offset: 0xC8 */ + __IO uint32_t MRCC_LPI2C1_CLKDIV; /**< LPI2C1 clock divider control, offset: 0xCC */ + __IO uint32_t MRCC_LPSPI0_CLKSEL; /**< LPSPI0 clock selection control, offset: 0xD0 */ + __IO uint32_t MRCC_LPSPI0_CLKDIV; /**< LPSPI0 clock divider control, offset: 0xD4 */ + __IO uint32_t MRCC_LPSPI1_CLKSEL; /**< LPSPI1 clock selection control, offset: 0xD8 */ + __IO uint32_t MRCC_LPSPI1_CLKDIV; /**< LPSPI1 clock divider control, offset: 0xDC */ + __IO uint32_t MRCC_LPUART0_CLKSEL; /**< LPUART0 clock selection control, offset: 0xE0 */ + __IO uint32_t MRCC_LPUART0_CLKDIV; /**< LPUART0 clock divider control, offset: 0xE4 */ + __IO uint32_t MRCC_LPUART1_CLKSEL; /**< LPUART1 clock selection control, offset: 0xE8 */ + __IO uint32_t MRCC_LPUART1_CLKDIV; /**< LPUART1 clock divider control, offset: 0xEC */ + __IO uint32_t MRCC_LPUART2_CLKSEL; /**< LPUART2 clock selection control, offset: 0xF0 */ + __IO uint32_t MRCC_LPUART2_CLKDIV; /**< LPUART2 clock divider control, offset: 0xF4 */ + __IO uint32_t MRCC_LPUART3_CLKSEL; /**< LPUART3 clock selection control, offset: 0xF8 */ + __IO uint32_t MRCC_LPUART3_CLKDIV; /**< LPUART3 clock divider control, offset: 0xFC */ + __IO uint32_t MRCC_LPTMR0_CLKSEL; /**< LPTMR0 clock selection control, offset: 0x100 */ + __IO uint32_t MRCC_LPTMR0_CLKDIV; /**< LPTMR0 clock divider control, offset: 0x104 */ + __IO uint32_t MRCC_OSTIMER0_CLKSEL; /**< OSTIMER0 clock selection control, offset: 0x108 */ + uint8_t RESERVED_8[4]; + __IO uint32_t MRCC_ADC_CLKSEL; /**< ADCx clock selection control, offset: 0x110 */ + __IO uint32_t MRCC_ADC_CLKDIV; /**< ADCx clock divider control, offset: 0x114 */ + uint8_t RESERVED_9[4]; + __IO uint32_t MRCC_CMP0_FUNC_CLKDIV; /**< CMP0_FUNC clock divider control, offset: 0x11C */ + __IO uint32_t MRCC_CMP0_RR_CLKSEL; /**< CMP0_RR clock selection control, offset: 0x120 */ + __IO uint32_t MRCC_CMP0_RR_CLKDIV; /**< CMP0_RR clock divider control, offset: 0x124 */ + uint8_t RESERVED_10[4]; + __IO uint32_t MRCC_CMP1_FUNC_CLKDIV; /**< CMP1_FUNC clock divider control, offset: 0x12C */ + __IO uint32_t MRCC_CMP1_RR_CLKSEL; /**< CMP1_RR clock selection control, offset: 0x130 */ + __IO uint32_t MRCC_CMP1_RR_CLKDIV; /**< CMP1_RR clock divider control, offset: 0x134 */ + uint8_t RESERVED_11[4]; + __IO uint32_t MRCC_CMP2_FUNC_CLKDIV; /**< CMP2_FUNC clock divider control, offset: 0x13C */ + __IO uint32_t MRCC_CMP2_RR_CLKSEL; /**< CMP2_RR clock selection control, offset: 0x140 */ + __IO uint32_t MRCC_CMP2_RR_CLKDIV; /**< CMP2_RR clock divider control, offset: 0x144 */ + __IO uint32_t MRCC_FLEXCAN0_CLKSEL; /**< FLEXCAN0 clock selection control, offset: 0x148 */ + __IO uint32_t MRCC_FLEXCAN0_CLKDIV; /**< FLEXCAN0 clock divider control, offset: 0x14C */ + __IO uint32_t MRCC_DBG_TRACE_CLKSEL; /**< DBG_TRACE clock selection control, offset: 0x150 */ + __IO uint32_t MRCC_DBG_TRACE_CLKDIV; /**< DBG_TRACE clock divider control, offset: 0x154 */ + __IO uint32_t MRCC_CLKOUT_CLKSEL; /**< CLKOUT clock selection control, offset: 0x158 */ + __IO uint32_t MRCC_CLKOUT_CLKDIV; /**< CLKOUT clock divider control, offset: 0x15C */ +} MRCC_Type; + +/* ---------------------------------------------------------------------------- + -- MRCC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRCC_Register_Masks MRCC Register Masks + * @{ + */ + +/*! @name MRCC_GLB_RST0 - Peripheral Reset Control 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK (0x1U) +#define MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT (0U) +/*! INPUTMUX0 - INPUTMUX0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER0_MASK (0x4U) +#define MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT (2U) +/*! CTIMER0 - CTIMER0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER0_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER1_MASK (0x8U) +#define MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT (3U) +/*! CTIMER1 - CTIMER1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER1_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER2_MASK (0x10U) +#define MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER2_MASK) + +#define MRCC_MRCC_GLB_RST0_FREQME_MASK (0x80U) +#define MRCC_MRCC_GLB_RST0_FREQME_SHIFT (7U) +/*! FREQME - FREQME + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FREQME_SHIFT)) & MRCC_MRCC_GLB_RST0_FREQME_MASK) + +#define MRCC_MRCC_GLB_RST0_UTICK0_MASK (0x100U) +#define MRCC_MRCC_GLB_RST0_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_RST0_UTICK0_MASK) + +#define MRCC_MRCC_GLB_RST0_SMARTDMA0_MASK (0x400U) +#define MRCC_MRCC_GLB_RST0_SMARTDMA0_SHIFT (10U) +/*! SMARTDMA0 - SMARTDMA0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_SMARTDMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_SMARTDMA0_SHIFT)) & MRCC_MRCC_GLB_RST0_SMARTDMA0_MASK) + +#define MRCC_MRCC_GLB_RST0_DMA0_MASK (0x800U) +#define MRCC_MRCC_GLB_RST0_DMA0_SHIFT (11U) +/*! DMA0 - DMA0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_DMA0_SHIFT)) & MRCC_MRCC_GLB_RST0_DMA0_MASK) + +#define MRCC_MRCC_GLB_RST0_AOI0_MASK (0x1000U) +#define MRCC_MRCC_GLB_RST0_AOI0_SHIFT (12U) +/*! AOI0 - AOI0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_AOI0_SHIFT)) & MRCC_MRCC_GLB_RST0_AOI0_MASK) + +#define MRCC_MRCC_GLB_RST0_CRC0_MASK (0x2000U) +#define MRCC_MRCC_GLB_RST0_CRC0_SHIFT (13U) +/*! CRC0 - CRC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CRC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CRC0_SHIFT)) & MRCC_MRCC_GLB_RST0_CRC0_MASK) + +#define MRCC_MRCC_GLB_RST0_EIM0_MASK (0x4000U) +#define MRCC_MRCC_GLB_RST0_EIM0_SHIFT (14U) +/*! EIM0 - EIM0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_EIM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_EIM0_SHIFT)) & MRCC_MRCC_GLB_RST0_EIM0_MASK) + +#define MRCC_MRCC_GLB_RST0_ERM0_MASK (0x8000U) +#define MRCC_MRCC_GLB_RST0_ERM0_SHIFT (15U) +/*! ERM0 - ERM0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_ERM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_ERM0_SHIFT)) & MRCC_MRCC_GLB_RST0_ERM0_MASK) + +#define MRCC_MRCC_GLB_RST0_AOI1_MASK (0x20000U) +#define MRCC_MRCC_GLB_RST0_AOI1_SHIFT (17U) +/*! AOI1 - AOI1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_AOI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_AOI1_SHIFT)) & MRCC_MRCC_GLB_RST0_AOI1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPI2C0_MASK (0x80000U) +#define MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT (19U) +/*! LPI2C0 - LPI2C0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPI2C0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPI2C1_MASK (0x100000U) +#define MRCC_MRCC_GLB_RST0_LPI2C1_SHIFT (20U) +/*! LPI2C1 - LPI2C1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPI2C1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPSPI0_MASK (0x200000U) +#define MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT (21U) +/*! LPSPI0 - LPSPI0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPSPI1_MASK (0x400000U) +#define MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT (22U) +/*! LPSPI1 - LPSPI1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART0_MASK (0x800000U) +#define MRCC_MRCC_GLB_RST0_LPUART0_SHIFT (23U) +/*! LPUART0 - LPUART0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART1_MASK (0x1000000U) +#define MRCC_MRCC_GLB_RST0_LPUART1_SHIFT (24U) +/*! LPUART1 - LPUART1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART2_MASK (0x2000000U) +#define MRCC_MRCC_GLB_RST0_LPUART2_SHIFT (25U) +/*! LPUART2 - LPUART2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART2_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART3_MASK (0x4000000U) +#define MRCC_MRCC_GLB_RST0_LPUART3_SHIFT (26U) +/*! LPUART3 - LPUART3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART3_MASK) + +#define MRCC_MRCC_GLB_RST0_QDC0_MASK (0x20000000U) +#define MRCC_MRCC_GLB_RST0_QDC0_SHIFT (29U) +/*! QDC0 - QDC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_QDC0_SHIFT)) & MRCC_MRCC_GLB_RST0_QDC0_MASK) + +#define MRCC_MRCC_GLB_RST0_QDC1_MASK (0x40000000U) +#define MRCC_MRCC_GLB_RST0_QDC1_SHIFT (30U) +/*! QDC1 - QDC1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_QDC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_QDC1_SHIFT)) & MRCC_MRCC_GLB_RST0_QDC1_MASK) + +#define MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK (0x80000000U) +#define MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT (31U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST0_SET - Peripheral Reset Control Set 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST0_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST0_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST0_CLR - Peripheral Reset Control Clear 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST0_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST0_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST1 - Peripheral Reset Control 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST1_FLEXPWM1_MASK (0x1U) +#define MRCC_MRCC_GLB_RST1_FLEXPWM1_SHIFT (0U) +/*! FLEXPWM1 - FLEXPWM1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_RST1_FLEXPWM1_MASK) + +#define MRCC_MRCC_GLB_RST1_OSTIMER0_MASK (0x2U) +#define MRCC_MRCC_GLB_RST1_OSTIMER0_SHIFT (1U) +/*! OSTIMER0 - OSTIMER0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST1_OSTIMER0_MASK) + +#define MRCC_MRCC_GLB_RST1_ADC0_MASK (0x4U) +#define MRCC_MRCC_GLB_RST1_ADC0_SHIFT (2U) +/*! ADC0 - ADC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC0_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC0_MASK) + +#define MRCC_MRCC_GLB_RST1_ADC1_MASK (0x8U) +#define MRCC_MRCC_GLB_RST1_ADC1_SHIFT (3U) +/*! ADC1 - ADC1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC1_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC1_MASK) + +#define MRCC_MRCC_GLB_RST1_CMP1_MASK (0x20U) +#define MRCC_MRCC_GLB_RST1_CMP1_SHIFT (5U) +/*! CMP1 - CMP1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CMP1_SHIFT)) & MRCC_MRCC_GLB_RST1_CMP1_MASK) + +#define MRCC_MRCC_GLB_RST1_CMP2_MASK (0x40U) +#define MRCC_MRCC_GLB_RST1_CMP2_SHIFT (6U) +/*! CMP2 - CMP2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_CMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CMP2_SHIFT)) & MRCC_MRCC_GLB_RST1_CMP2_MASK) + +#define MRCC_MRCC_GLB_RST1_OPAMP0_MASK (0x100U) +#define MRCC_MRCC_GLB_RST1_OPAMP0_SHIFT (8U) +/*! OPAMP0 - OPAMP0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP0_MASK) + +#define MRCC_MRCC_GLB_RST1_OPAMP1_MASK (0x200U) +#define MRCC_MRCC_GLB_RST1_OPAMP1_SHIFT (9U) +/*! OPAMP1 - OPAMP1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP1_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP1_MASK) + +#define MRCC_MRCC_GLB_RST1_OPAMP2_MASK (0x400U) +#define MRCC_MRCC_GLB_RST1_OPAMP2_SHIFT (10U) +/*! OPAMP2 - OPAMP2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP2_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP2_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT0_MASK (0x1000U) +#define MRCC_MRCC_GLB_RST1_PORT0_SHIFT (12U) +/*! PORT0 - PORT0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT0_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT0_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT1_MASK (0x2000U) +#define MRCC_MRCC_GLB_RST1_PORT1_SHIFT (13U) +/*! PORT1 - PORT1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT1_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT1_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT2_MASK (0x4000U) +#define MRCC_MRCC_GLB_RST1_PORT2_SHIFT (14U) +/*! PORT2 - PORT2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT2_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT2_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT3_MASK (0x8000U) +#define MRCC_MRCC_GLB_RST1_PORT3_SHIFT (15U) +/*! PORT3 - PORT3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT3_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT3_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT4_MASK (0x10000U) +#define MRCC_MRCC_GLB_RST1_PORT4_SHIFT (16U) +/*! PORT4 - PORT4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT4_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT4_MASK) + +#define MRCC_MRCC_GLB_RST1_FLEXCAN0_MASK (0x40000U) +#define MRCC_MRCC_GLB_RST1_FLEXCAN0_SHIFT (18U) +/*! FLEXCAN0 - FLEXCAN0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_RST1_FLEXCAN0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST1_SET - Peripheral Reset Control Set 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST1_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST1_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST1_CLR - Peripheral Reset Control Clear 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST1_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST1_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST2 - Peripheral Reset Control 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST2_GPIO0_MASK (0x10U) +#define MRCC_MRCC_GLB_RST2_GPIO0_SHIFT (4U) +/*! GPIO0 - GPIO0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO0_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO0_MASK) + +#define MRCC_MRCC_GLB_RST2_GPIO1_MASK (0x20U) +#define MRCC_MRCC_GLB_RST2_GPIO1_SHIFT (5U) +/*! GPIO1 - GPIO1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO1_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO1_MASK) + +#define MRCC_MRCC_GLB_RST2_GPIO2_MASK (0x40U) +#define MRCC_MRCC_GLB_RST2_GPIO2_SHIFT (6U) +/*! GPIO2 - GPIO2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO2_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO2_MASK) + +#define MRCC_MRCC_GLB_RST2_GPIO3_MASK (0x80U) +#define MRCC_MRCC_GLB_RST2_GPIO3_SHIFT (7U) +/*! GPIO3 - GPIO3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO3_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO3_MASK) + +#define MRCC_MRCC_GLB_RST2_GPIO4_MASK (0x100U) +#define MRCC_MRCC_GLB_RST2_GPIO4_SHIFT (8U) +/*! GPIO4 - GPIO4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO4_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO4_MASK) + +#define MRCC_MRCC_GLB_RST2_MAU0_MASK (0x200U) +#define MRCC_MRCC_GLB_RST2_MAU0_SHIFT (9U) +/*! MAU0 - MAU0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_MAU0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_MAU0_SHIFT)) & MRCC_MRCC_GLB_RST2_MAU0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST2_SET - Peripheral Reset Control Set 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST2_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST2_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST2_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST2_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST2_CLR - Peripheral Reset Control Clear 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST2_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST2_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST2_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST2_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC0 - AHB Clock Control 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK (0x1U) +#define MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT (0U) +/*! INPUTMUX0 - INPUTMUX0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER0_MASK (0x4U) +#define MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT (2U) +/*! CTIMER0 - CTIMER0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER0_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER1_MASK (0x8U) +#define MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT (3U) +/*! CTIMER1 - CTIMER1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER1_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER2_MASK (0x10U) +#define MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER2_MASK) + +#define MRCC_MRCC_GLB_CC0_FREQME_MASK (0x80U) +#define MRCC_MRCC_GLB_CC0_FREQME_SHIFT (7U) +/*! FREQME - FREQME + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_CC0_FREQME_MASK) + +#define MRCC_MRCC_GLB_CC0_UTICK0_MASK (0x100U) +#define MRCC_MRCC_GLB_CC0_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_CC0_UTICK0_MASK) + +#define MRCC_MRCC_GLB_CC0_WWDT0_MASK (0x200U) +#define MRCC_MRCC_GLB_CC0_WWDT0_SHIFT (9U) +/*! WWDT0 - WWDT0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_CC0_WWDT0_MASK) + +#define MRCC_MRCC_GLB_CC0_SMARTDMA0_MASK (0x400U) +#define MRCC_MRCC_GLB_CC0_SMARTDMA0_SHIFT (10U) +/*! SMARTDMA0 - SMARTDMA0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_SMARTDMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_SMARTDMA0_SHIFT)) & MRCC_MRCC_GLB_CC0_SMARTDMA0_MASK) + +#define MRCC_MRCC_GLB_CC0_DMA0_MASK (0x800U) +#define MRCC_MRCC_GLB_CC0_DMA0_SHIFT (11U) +/*! DMA0 - DMA0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_DMA0_SHIFT)) & MRCC_MRCC_GLB_CC0_DMA0_MASK) + +#define MRCC_MRCC_GLB_CC0_AOI0_MASK (0x1000U) +#define MRCC_MRCC_GLB_CC0_AOI0_SHIFT (12U) +/*! AOI0 - AOI0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_CC0_AOI0_MASK) + +#define MRCC_MRCC_GLB_CC0_CRC0_MASK (0x2000U) +#define MRCC_MRCC_GLB_CC0_CRC0_SHIFT (13U) +/*! CRC0 - CRC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CRC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CRC0_SHIFT)) & MRCC_MRCC_GLB_CC0_CRC0_MASK) + +#define MRCC_MRCC_GLB_CC0_EIM0_MASK (0x4000U) +#define MRCC_MRCC_GLB_CC0_EIM0_SHIFT (14U) +/*! EIM0 - EIM0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_EIM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_EIM0_SHIFT)) & MRCC_MRCC_GLB_CC0_EIM0_MASK) + +#define MRCC_MRCC_GLB_CC0_ERM0_MASK (0x8000U) +#define MRCC_MRCC_GLB_CC0_ERM0_SHIFT (15U) +/*! ERM0 - ERM0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_ERM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_ERM0_SHIFT)) & MRCC_MRCC_GLB_CC0_ERM0_MASK) + +#define MRCC_MRCC_GLB_CC0_AOI1_MASK (0x20000U) +#define MRCC_MRCC_GLB_CC0_AOI1_SHIFT (17U) +/*! AOI1 - AOI1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_AOI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_AOI1_SHIFT)) & MRCC_MRCC_GLB_CC0_AOI1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPI2C0_MASK (0x80000U) +#define MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT (19U) +/*! LPI2C0 - LPI2C0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPI2C0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPI2C1_MASK (0x100000U) +#define MRCC_MRCC_GLB_CC0_LPI2C1_SHIFT (20U) +/*! LPI2C1 - LPI2C1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPI2C1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPSPI0_MASK (0x200000U) +#define MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT (21U) +/*! LPSPI0 - LPSPI0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPSPI1_MASK (0x400000U) +#define MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT (22U) +/*! LPSPI1 - LPSPI1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART0_MASK (0x800000U) +#define MRCC_MRCC_GLB_CC0_LPUART0_SHIFT (23U) +/*! LPUART0 - LPUART0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART1_MASK (0x1000000U) +#define MRCC_MRCC_GLB_CC0_LPUART1_SHIFT (24U) +/*! LPUART1 - LPUART1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART2_MASK (0x2000000U) +#define MRCC_MRCC_GLB_CC0_LPUART2_SHIFT (25U) +/*! LPUART2 - LPUART2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART2_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART3_MASK (0x4000000U) +#define MRCC_MRCC_GLB_CC0_LPUART3_SHIFT (26U) +/*! LPUART3 - LPUART3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART3_MASK) + +#define MRCC_MRCC_GLB_CC0_QDC0_MASK (0x20000000U) +#define MRCC_MRCC_GLB_CC0_QDC0_SHIFT (29U) +/*! QDC0 - QDC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_CC0_QDC0_MASK) + +#define MRCC_MRCC_GLB_CC0_QDC1_MASK (0x40000000U) +#define MRCC_MRCC_GLB_CC0_QDC1_SHIFT (30U) +/*! QDC1 - QDC1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_QDC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_QDC1_SHIFT)) & MRCC_MRCC_GLB_CC0_QDC1_MASK) + +#define MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK (0x80000000U) +#define MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT (31U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC0_SET - AHB Clock Control Set 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC0_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC0_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC0_CLR - AHB Clock Control Clear 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC0_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC0_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC1 - AHB Clock Control 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK (0x1U) +#define MRCC_MRCC_GLB_CC1_FLEXPWM1_SHIFT (0U) +/*! FLEXPWM1 - FLEXPWM1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK) + +#define MRCC_MRCC_GLB_CC1_OSTIMER0_MASK (0x2U) +#define MRCC_MRCC_GLB_CC1_OSTIMER0_SHIFT (1U) +/*! OSTIMER0 - OSTIMER0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC1_OSTIMER0_MASK) + +#define MRCC_MRCC_GLB_CC1_ADC0_MASK (0x4U) +#define MRCC_MRCC_GLB_CC1_ADC0_SHIFT (2U) +/*! ADC0 - ADC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC0_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC0_MASK) + +#define MRCC_MRCC_GLB_CC1_ADC1_MASK (0x8U) +#define MRCC_MRCC_GLB_CC1_ADC1_SHIFT (3U) +/*! ADC1 - ADC1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC1_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC1_MASK) + +#define MRCC_MRCC_GLB_CC1_CMP0_MASK (0x10U) +#define MRCC_MRCC_GLB_CC1_CMP0_SHIFT (4U) +/*! CMP0 - CMP0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP0_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP0_MASK) + +#define MRCC_MRCC_GLB_CC1_CMP1_MASK (0x20U) +#define MRCC_MRCC_GLB_CC1_CMP1_SHIFT (5U) +/*! CMP1 - CMP1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP1_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP1_MASK) + +#define MRCC_MRCC_GLB_CC1_CMP2_MASK (0x40U) +#define MRCC_MRCC_GLB_CC1_CMP2_SHIFT (6U) +/*! CMP2 - CMP2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_CMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP2_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP2_MASK) + +#define MRCC_MRCC_GLB_CC1_OPAMP0_MASK (0x100U) +#define MRCC_MRCC_GLB_CC1_OPAMP0_SHIFT (8U) +/*! OPAMP0 - OPAMP0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP0_MASK) + +#define MRCC_MRCC_GLB_CC1_OPAMP1_MASK (0x200U) +#define MRCC_MRCC_GLB_CC1_OPAMP1_SHIFT (9U) +/*! OPAMP1 - OPAMP1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP1_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP1_MASK) + +#define MRCC_MRCC_GLB_CC1_OPAMP2_MASK (0x400U) +#define MRCC_MRCC_GLB_CC1_OPAMP2_SHIFT (10U) +/*! OPAMP2 - OPAMP2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP2_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP2_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT0_MASK (0x1000U) +#define MRCC_MRCC_GLB_CC1_PORT0_SHIFT (12U) +/*! PORT0 - PORT0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT0_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT0_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT1_MASK (0x2000U) +#define MRCC_MRCC_GLB_CC1_PORT1_SHIFT (13U) +/*! PORT1 - PORT1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT1_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT1_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT2_MASK (0x4000U) +#define MRCC_MRCC_GLB_CC1_PORT2_SHIFT (14U) +/*! PORT2 - PORT2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT2_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT2_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT3_MASK (0x8000U) +#define MRCC_MRCC_GLB_CC1_PORT3_SHIFT (15U) +/*! PORT3 - PORT3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT3_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT4_MASK (0x10000U) +#define MRCC_MRCC_GLB_CC1_PORT4_SHIFT (16U) +/*! PORT4 - PORT4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT4_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT4_MASK) + +#define MRCC_MRCC_GLB_CC1_FLEXCAN0_MASK (0x40000U) +#define MRCC_MRCC_GLB_CC1_FLEXCAN0_SHIFT (18U) +/*! FLEXCAN0 - FLEXCAN0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_CC1_FLEXCAN0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC1_SET - AHB Clock Control Set 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC1_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC1_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC1_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC1_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC1_CLR - AHB Clock Control Clear 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC1_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC1_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC1_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC1_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC2 - AHB Clock Control 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC2_RAMA_MASK (0x2U) +#define MRCC_MRCC_GLB_CC2_RAMA_SHIFT (1U) +/*! RAMA - RAMA + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_RAMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_RAMA_SHIFT)) & MRCC_MRCC_GLB_CC2_RAMA_MASK) + +#define MRCC_MRCC_GLB_CC2_RAMB_MASK (0x4U) +#define MRCC_MRCC_GLB_CC2_RAMB_SHIFT (2U) +/*! RAMB - RAMB + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_RAMB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_RAMB_SHIFT)) & MRCC_MRCC_GLB_CC2_RAMB_MASK) + +#define MRCC_MRCC_GLB_CC2_RAMC_MASK (0x8U) +#define MRCC_MRCC_GLB_CC2_RAMC_SHIFT (3U) +/*! RAMC - RAMC + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_RAMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_RAMC_SHIFT)) & MRCC_MRCC_GLB_CC2_RAMC_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO0_MASK (0x10U) +#define MRCC_MRCC_GLB_CC2_GPIO0_SHIFT (4U) +/*! GPIO0 - GPIO0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO0_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO0_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO1_MASK (0x20U) +#define MRCC_MRCC_GLB_CC2_GPIO1_SHIFT (5U) +/*! GPIO1 - GPIO1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO1_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO1_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO2_MASK (0x40U) +#define MRCC_MRCC_GLB_CC2_GPIO2_SHIFT (6U) +/*! GPIO2 - GPIO2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO2_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO2_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO3_MASK (0x80U) +#define MRCC_MRCC_GLB_CC2_GPIO3_SHIFT (7U) +/*! GPIO3 - GPIO3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO3_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO3_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO4_MASK (0x100U) +#define MRCC_MRCC_GLB_CC2_GPIO4_SHIFT (8U) +/*! GPIO4 - GPIO4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO4_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO4_MASK) + +#define MRCC_MRCC_GLB_CC2_MAU0_MASK (0x200U) +#define MRCC_MRCC_GLB_CC2_MAU0_SHIFT (9U) +/*! MAU0 - MAU0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_MAU0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_MAU0_SHIFT)) & MRCC_MRCC_GLB_CC2_MAU0_MASK) + +#define MRCC_MRCC_GLB_CC2_ROMC_MASK (0x400U) +#define MRCC_MRCC_GLB_CC2_ROMC_SHIFT (10U) +/*! ROMC - ROMC + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_ROMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_ROMC_SHIFT)) & MRCC_MRCC_GLB_CC2_ROMC_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC2_SET - AHB Clock Control Set 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC2_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC2_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC2_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC2_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC2_CLR - AHB Clock Control Clear 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC2_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC2_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC2_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC2_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_ACC0 - Control Automatic Clock Gating 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK (0x1U) +#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT (0U) +/*! INPUTMUX0 - INPUTMUX0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER0_MASK (0x4U) +#define MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT (2U) +/*! CTIMER0 - CTIMER0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER0_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER1_MASK (0x8U) +#define MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT (3U) +/*! CTIMER1 - CTIMER1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER1_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER2_MASK (0x10U) +#define MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER2_MASK) + +#define MRCC_MRCC_GLB_ACC0_FREQME_MASK (0x80U) +#define MRCC_MRCC_GLB_ACC0_FREQME_SHIFT (7U) +/*! FREQME - FREQME + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_ACC0_FREQME_MASK) + +#define MRCC_MRCC_GLB_ACC0_UTICK0_MASK (0x100U) +#define MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_ACC0_UTICK0_MASK) + +#define MRCC_MRCC_GLB_ACC0_WWDT0_MASK (0x200U) +#define MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT (9U) +/*! WWDT0 - WWDT0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_ACC0_WWDT0_MASK) + +#define MRCC_MRCC_GLB_ACC0_SMARTDMA0_MASK (0x400U) +#define MRCC_MRCC_GLB_ACC0_SMARTDMA0_SHIFT (10U) +/*! SMARTDMA0 - SMARTDMA0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_SMARTDMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_SMARTDMA0_SHIFT)) & MRCC_MRCC_GLB_ACC0_SMARTDMA0_MASK) + +#define MRCC_MRCC_GLB_ACC0_DMA0_MASK (0x800U) +#define MRCC_MRCC_GLB_ACC0_DMA0_SHIFT (11U) +/*! DMA0 - DMA0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_DMA0_SHIFT)) & MRCC_MRCC_GLB_ACC0_DMA0_MASK) + +#define MRCC_MRCC_GLB_ACC0_AOI0_MASK (0x1000U) +#define MRCC_MRCC_GLB_ACC0_AOI0_SHIFT (12U) +/*! AOI0 - AOI0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_AOI0_MASK) + +#define MRCC_MRCC_GLB_ACC0_CRC0_MASK (0x2000U) +#define MRCC_MRCC_GLB_ACC0_CRC0_SHIFT (13U) +/*! CRC0 - CRC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CRC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CRC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CRC0_MASK) + +#define MRCC_MRCC_GLB_ACC0_EIM0_MASK (0x4000U) +#define MRCC_MRCC_GLB_ACC0_EIM0_SHIFT (14U) +/*! EIM0 - EIM0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_EIM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_EIM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_EIM0_MASK) + +#define MRCC_MRCC_GLB_ACC0_ERM0_MASK (0x8000U) +#define MRCC_MRCC_GLB_ACC0_ERM0_SHIFT (15U) +/*! ERM0 - ERM0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_ERM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_ERM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_ERM0_MASK) + +#define MRCC_MRCC_GLB_ACC0_AOI1_MASK (0x20000U) +#define MRCC_MRCC_GLB_ACC0_AOI1_SHIFT (17U) +/*! AOI1 - AOI1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_AOI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_AOI1_SHIFT)) & MRCC_MRCC_GLB_ACC0_AOI1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPI2C0_MASK (0x80000U) +#define MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT (19U) +/*! LPI2C0 - LPI2C0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPI2C0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPI2C1_MASK (0x100000U) +#define MRCC_MRCC_GLB_ACC0_LPI2C1_SHIFT (20U) +/*! LPI2C1 - LPI2C1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPI2C1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPSPI0_MASK (0x200000U) +#define MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT (21U) +/*! LPSPI0 - LPSPI0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPSPI1_MASK (0x400000U) +#define MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT (22U) +/*! LPSPI1 - LPSPI1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART0_MASK (0x800000U) +#define MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT (23U) +/*! LPUART0 - LPUART0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART1_MASK (0x1000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT (24U) +/*! LPUART1 - LPUART1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART2_MASK (0x2000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT (25U) +/*! LPUART2 - LPUART2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART2_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART3_MASK (0x4000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART3_SHIFT (26U) +/*! LPUART3 - LPUART3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART3_MASK) + +#define MRCC_MRCC_GLB_ACC0_QDC0_MASK (0x20000000U) +#define MRCC_MRCC_GLB_ACC0_QDC0_SHIFT (29U) +/*! QDC0 - QDC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_QDC0_MASK) + +#define MRCC_MRCC_GLB_ACC0_QDC1_MASK (0x40000000U) +#define MRCC_MRCC_GLB_ACC0_QDC1_SHIFT (30U) +/*! QDC1 - QDC1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_QDC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_QDC1_SHIFT)) & MRCC_MRCC_GLB_ACC0_QDC1_MASK) + +#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK (0x80000000U) +#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT (31U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_ACC1 - Control Automatic Clock Gating 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_ACC1_FLEXPWM1_MASK (0x1U) +#define MRCC_MRCC_GLB_ACC1_FLEXPWM1_SHIFT (0U) +/*! FLEXPWM1 - FLEXPWM1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_ACC1_FLEXPWM1_MASK) + +#define MRCC_MRCC_GLB_ACC1_OSTIMER0_MASK (0x2U) +#define MRCC_MRCC_GLB_ACC1_OSTIMER0_SHIFT (1U) +/*! OSTIMER0 - OSTIMER0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC1_OSTIMER0_MASK) + +#define MRCC_MRCC_GLB_ACC1_ADC0_MASK (0x4U) +#define MRCC_MRCC_GLB_ACC1_ADC0_SHIFT (2U) +/*! ADC0 - ADC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC0_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC0_MASK) + +#define MRCC_MRCC_GLB_ACC1_ADC1_MASK (0x8U) +#define MRCC_MRCC_GLB_ACC1_ADC1_SHIFT (3U) +/*! ADC1 - ADC1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC1_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC1_MASK) + +#define MRCC_MRCC_GLB_ACC1_CMP0_MASK (0x10U) +#define MRCC_MRCC_GLB_ACC1_CMP0_SHIFT (4U) +/*! CMP0 - CMP0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP0_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP0_MASK) + +#define MRCC_MRCC_GLB_ACC1_CMP1_MASK (0x20U) +#define MRCC_MRCC_GLB_ACC1_CMP1_SHIFT (5U) +/*! CMP1 - CMP1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP1_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP1_MASK) + +#define MRCC_MRCC_GLB_ACC1_CMP2_MASK (0x40U) +#define MRCC_MRCC_GLB_ACC1_CMP2_SHIFT (6U) +/*! CMP2 - CMP2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_CMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP2_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP2_MASK) + +#define MRCC_MRCC_GLB_ACC1_OPAMP0_MASK (0x100U) +#define MRCC_MRCC_GLB_ACC1_OPAMP0_SHIFT (8U) +/*! OPAMP0 - OPAMP0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP0_MASK) + +#define MRCC_MRCC_GLB_ACC1_OPAMP1_MASK (0x200U) +#define MRCC_MRCC_GLB_ACC1_OPAMP1_SHIFT (9U) +/*! OPAMP1 - OPAMP1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP1_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP1_MASK) + +#define MRCC_MRCC_GLB_ACC1_OPAMP2_MASK (0x400U) +#define MRCC_MRCC_GLB_ACC1_OPAMP2_SHIFT (10U) +/*! OPAMP2 - OPAMP2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP2_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP2_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT0_MASK (0x1000U) +#define MRCC_MRCC_GLB_ACC1_PORT0_SHIFT (12U) +/*! PORT0 - PORT0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT0_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT0_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT1_MASK (0x2000U) +#define MRCC_MRCC_GLB_ACC1_PORT1_SHIFT (13U) +/*! PORT1 - PORT1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT1_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT1_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT2_MASK (0x4000U) +#define MRCC_MRCC_GLB_ACC1_PORT2_SHIFT (14U) +/*! PORT2 - PORT2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT2_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT2_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT3_MASK (0x8000U) +#define MRCC_MRCC_GLB_ACC1_PORT3_SHIFT (15U) +/*! PORT3 - PORT3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT3_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT4_MASK (0x10000U) +#define MRCC_MRCC_GLB_ACC1_PORT4_SHIFT (16U) +/*! PORT4 - PORT4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT4_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT4_MASK) + +#define MRCC_MRCC_GLB_ACC1_FLEXCAN0_MASK (0x40000U) +#define MRCC_MRCC_GLB_ACC1_FLEXCAN0_SHIFT (18U) +/*! FLEXCAN0 - FLEXCAN0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_ACC1_FLEXCAN0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_ACC2 - Control Automatic Clock Gating 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_ACC2_RAMA_MASK (0x2U) +#define MRCC_MRCC_GLB_ACC2_RAMA_SHIFT (1U) +/*! RAMA - RAMA + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_RAMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_RAMA_SHIFT)) & MRCC_MRCC_GLB_ACC2_RAMA_MASK) + +#define MRCC_MRCC_GLB_ACC2_RAMB_MASK (0x4U) +#define MRCC_MRCC_GLB_ACC2_RAMB_SHIFT (2U) +/*! RAMB - RAMB + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_RAMB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_RAMB_SHIFT)) & MRCC_MRCC_GLB_ACC2_RAMB_MASK) + +#define MRCC_MRCC_GLB_ACC2_RAMC_MASK (0x8U) +#define MRCC_MRCC_GLB_ACC2_RAMC_SHIFT (3U) +/*! RAMC - RAMC + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_RAMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_RAMC_SHIFT)) & MRCC_MRCC_GLB_ACC2_RAMC_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO0_MASK (0x10U) +#define MRCC_MRCC_GLB_ACC2_GPIO0_SHIFT (4U) +/*! GPIO0 - GPIO0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO0_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO0_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO1_MASK (0x20U) +#define MRCC_MRCC_GLB_ACC2_GPIO1_SHIFT (5U) +/*! GPIO1 - GPIO1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO1_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO1_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO2_MASK (0x40U) +#define MRCC_MRCC_GLB_ACC2_GPIO2_SHIFT (6U) +/*! GPIO2 - GPIO2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO2_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO2_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO3_MASK (0x80U) +#define MRCC_MRCC_GLB_ACC2_GPIO3_SHIFT (7U) +/*! GPIO3 - GPIO3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO3_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO3_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO4_MASK (0x100U) +#define MRCC_MRCC_GLB_ACC2_GPIO4_SHIFT (8U) +/*! GPIO4 - GPIO4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO4_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO4_MASK) + +#define MRCC_MRCC_GLB_ACC2_MAU0_MASK (0x200U) +#define MRCC_MRCC_GLB_ACC2_MAU0_SHIFT (9U) +/*! MAU0 - MAU0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_MAU0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_MAU0_SHIFT)) & MRCC_MRCC_GLB_ACC2_MAU0_MASK) + +#define MRCC_MRCC_GLB_ACC2_ROMC_MASK (0x400U) +#define MRCC_MRCC_GLB_ACC2_ROMC_SHIFT (10U) +/*! ROMC - ROMC + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_ROMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_ROMC_SHIFT)) & MRCC_MRCC_GLB_ACC2_ROMC_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER0_CLKSEL - CTIMER0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CTIMER0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER0_CLKDIV - CTIMER0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER1_CLKSEL - CTIMER1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CTIMER1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER1_CLKDIV - CTIMER1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER2_CLKSEL - CTIMER2 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CTIMER2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER2_CLKDIV - CTIMER2 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_WWDT0_CLKDIV - WWDT0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_WWDT0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_WWDT0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_WWDT0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C0_CLKSEL - LPI2C0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPI2C0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C0_CLKDIV - LPI2C0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C1_CLKSEL - LPI2C1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPI2C1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C1_CLKDIV - LPI2C1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI0_CLKSEL - LPSPI0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPSPI0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI0_CLKDIV - LPSPI0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPSPI0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPSPI0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPSPI0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI1_CLKSEL - LPSPI1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPSPI1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI1_CLKDIV - LPSPI1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPSPI1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPSPI1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPSPI1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART0_CLKSEL - LPUART0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART0_CLKDIV - LPUART0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART1_CLKSEL - LPUART1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART1_CLKDIV - LPUART1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART2_CLKSEL - LPUART2 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART2_CLKDIV - LPUART2 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART3_CLKSEL - LPUART3 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART3_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART3_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART3_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART3_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART3_CLKDIV - LPUART3 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART3_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART3_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART3_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART3_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART3_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART3_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART3_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART3_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART3_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPTMR0_CLKSEL - LPTMR0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPTMR0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPTMR0_CLKDIV - LPTMR0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPTMR0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPTMR0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPTMR0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_OSTIMER0_CLKSEL - OSTIMER0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b00..CLK_16K + * 0b10..CLK_1M + * 0b11..Reserved2(NO Clock) + */ +#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_ADC_CLKSEL - ADCx clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_ADC_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_ADC_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_ADC_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_ADC_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_ADC_CLKDIV - ADCx clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_ADC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_ADC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_ADC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_ADC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_ADC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_ADC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_ADC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_ADC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_ADC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_ADC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_ADC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_ADC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP0_FUNC_CLKDIV - CMP0_FUNC clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP0_RR_CLKSEL - CMP0_RR clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CMP0_RR_CLKDIV - CMP0_RR clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP1_FUNC_CLKDIV - CMP1_FUNC clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP1_RR_CLKSEL - CMP1_RR clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CMP1_RR_CLKDIV - CMP1_RR clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP2_FUNC_CLKDIV - CMP2_FUNC clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP2_RR_CLKSEL - CMP2_RR clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CMP2_RR_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CMP2_RR_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CMP2_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CMP2_RR_CLKDIV - CMP2_RR clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP2_RR_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP2_RR_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP2_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP2_RR_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP2_RR_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP2_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP2_RR_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP2_RR_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP2_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_FLEXCAN0_CLKSEL - FLEXCAN0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b001..FRO_HF_GATED + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_FLEXCAN0_CLKDIV - FLEXCAN0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_DBG_TRACE_CLKSEL - DBG_TRACE clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b00..CPU_CLK + * 0b01..CLK_1M + * 0b10..CLK_16K + * 0b11..Reserved1(NO Clock) + */ +#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_DBG_TRACE_CLKDIV - DBG_TRACE clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CLKOUT_CLKSEL - CLKOUT clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_12M + * 0b001..FRO_HF_DIV + * 0b010..CLK_IN + * 0b011..CLK_16K + * 0b110..SLOW_CLK + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CLKOUT_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CLKOUT_CLKDIV - CLKOUT clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CLKOUT_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CLKOUT_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CLKOUT_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRCC_Register_Masks */ + + +/*! + * @} + */ /* end of group MRCC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_MRCC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OPAMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OPAMP.h new file mode 100644 index 000000000..29dfaecca --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OPAMP.h @@ -0,0 +1,204 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for OPAMP +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_OPAMP.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for OPAMP + * + * CMSIS Peripheral Access Layer for OPAMP + */ + +#if !defined(PERI_OPAMP_H_) +#define PERI_OPAMP_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- OPAMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OPAMP_Peripheral_Access_Layer OPAMP Peripheral Access Layer + * @{ + */ + +/** OPAMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t OPAMP_CTRL; /**< OPAMP Control, offset: 0x8 */ +} OPAMP_Type; + +/* ---------------------------------------------------------------------------- + -- OPAMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OPAMP_Register_Masks OPAMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define OPAMP_VERID_FEATURE_MASK (0xFFFFU) +#define OPAMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define OPAMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_FEATURE_SHIFT)) & OPAMP_VERID_FEATURE_MASK) + +#define OPAMP_VERID_MINOR_MASK (0xFF0000U) +#define OPAMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define OPAMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MINOR_SHIFT)) & OPAMP_VERID_MINOR_MASK) + +#define OPAMP_VERID_MAJOR_MASK (0xFF000000U) +#define OPAMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define OPAMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MAJOR_SHIFT)) & OPAMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define OPAMP_PARAM_PARAM_MASK (0xFFFFFFFFU) +#define OPAMP_PARAM_PARAM_SHIFT (0U) +/*! PARAM - Parameters */ +#define OPAMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_PARAM_PARAM_SHIFT)) & OPAMP_PARAM_PARAM_MASK) +/*! @} */ + +/*! @name OPAMP_CTRL - OPAMP Control */ +/*! @{ */ + +#define OPAMP_OPAMP_CTRL_OPA_EN_MASK (0x1U) +#define OPAMP_OPAMP_CTRL_OPA_EN_SHIFT (0U) +/*! OPA_EN - OPAMP Enable + * 0b0..Disable + * 0b1..Enable + */ +#define OPAMP_OPAMP_CTRL_OPA_EN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTRL_OPA_EN_SHIFT)) & OPAMP_OPAMP_CTRL_OPA_EN_MASK) + +#define OPAMP_OPAMP_CTRL_OPA_CC_SEL_MASK (0x30U) +#define OPAMP_OPAMP_CTRL_OPA_CC_SEL_SHIFT (4U) +/*! OPA_CC_SEL - Compensation capcitor config selection + * 0b00..Fit 2X gains + * 0b01..Fit 4X gains + * 0b10..Fit 8X gains + * 0b11..Fit 16X gains + */ +#define OPAMP_OPAMP_CTRL_OPA_CC_SEL(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTRL_OPA_CC_SEL_SHIFT)) & OPAMP_OPAMP_CTRL_OPA_CC_SEL_MASK) + +#define OPAMP_OPAMP_CTRL_OPA_BC_SEL_MASK (0xC0U) +#define OPAMP_OPAMP_CTRL_OPA_BC_SEL_SHIFT (6U) +/*! OPA_BC_SEL - Bias current config selection + * 0b00..Default value. Keep power consumption constant + * 0b01..Reduce power consumption to 1/4 + * 0b10..Reduce power consumption to 1/2 + * 0b11..Increase power consumption to 3/2 + */ +#define OPAMP_OPAMP_CTRL_OPA_BC_SEL(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTRL_OPA_BC_SEL_SHIFT)) & OPAMP_OPAMP_CTRL_OPA_BC_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OPAMP_Register_Masks */ + + +/*! + * @} + */ /* end of group OPAMP_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_OPAMP_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OSTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OSTIMER.h new file mode 100644 index 000000000..43d639b49 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_OSTIMER.h @@ -0,0 +1,233 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for OSTIMER +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_OSTIMER.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for OSTIMER + * + * CMSIS Peripheral Access Layer for OSTIMER + */ + +#if !defined(PERI_OSTIMER_H_) +#define PERI_OSTIMER_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Local Capture Low for CPU, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Local Capture High for CPU, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Local Match Low for CPU, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Local Match High for CPU, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OSTIMER Control for CPU, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Local Capture Low for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Local Capture High for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Local Match Low for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Local Match High for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OSTIMER Control for CPU */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - Interrupt Flag */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - Interrupt or Wake-Up Request + * 0b0..Interrupts blocked + * 0b1..Interrupts enabled + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - EVTimer Match Write Ready */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) + +#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK (0x8U) +#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT (3U) +/*! DEBUG_EN - Debug Enable + * 0b0..Disables + * 0b1..Enables + */ +#define OSTIMER_OSEVENT_CTRL_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT)) & OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_OSTIMER_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PORT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PORT.h new file mode 100644 index 000000000..b35dc4e08 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PORT.h @@ -0,0 +1,602 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for PORT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_PORT.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for PORT + * + * CMSIS Peripheral Access Layer for PORT + */ + +#if !defined(PERI_PORT_H_) +#define PERI_PORT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Size of Registers Arrays */ +#define PORT_PCR_COUNT 32u + +/** PORT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t GPCLR; /**< Global Pin Control Low, offset: 0x10 */ + __IO uint32_t GPCHR; /**< Global Pin Control High, offset: 0x14 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CONFIG; /**< Configuration, offset: 0x20 */ + uint8_t RESERVED_2[60]; + __IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT3, PORT4 (missing on PORT2) */ + __IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT3, PORT4 (missing on PORT2) */ + uint8_t RESERVED_3[24]; + __IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PORT_VERID_FEATURE_MASK (0xFFFFU) +#define PORT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + */ +#define PORT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK) + +#define PORT_VERID_MINOR_MASK (0xFF0000U) +#define PORT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PORT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK) + +#define PORT_VERID_MAJOR_MASK (0xFF000000U) +#define PORT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PORT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name GPCLR - Global Pin Control Low */ +/*! @{ */ + +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) + +#define PORT_GPCLR_GPWE0_MASK (0x10000U) +#define PORT_GPCLR_GPWE0_SHIFT (16U) +/*! GPWE0 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK) + +#define PORT_GPCLR_GPWE1_MASK (0x20000U) +#define PORT_GPCLR_GPWE1_SHIFT (17U) +/*! GPWE1 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK) + +#define PORT_GPCLR_GPWE2_MASK (0x40000U) +#define PORT_GPCLR_GPWE2_SHIFT (18U) +/*! GPWE2 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK) + +#define PORT_GPCLR_GPWE3_MASK (0x80000U) +#define PORT_GPCLR_GPWE3_SHIFT (19U) +/*! GPWE3 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK) + +#define PORT_GPCLR_GPWE4_MASK (0x100000U) +#define PORT_GPCLR_GPWE4_SHIFT (20U) +/*! GPWE4 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK) + +#define PORT_GPCLR_GPWE5_MASK (0x200000U) +#define PORT_GPCLR_GPWE5_SHIFT (21U) +/*! GPWE5 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK) + +#define PORT_GPCLR_GPWE6_MASK (0x400000U) +#define PORT_GPCLR_GPWE6_SHIFT (22U) +/*! GPWE6 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK) + +#define PORT_GPCLR_GPWE7_MASK (0x800000U) +#define PORT_GPCLR_GPWE7_SHIFT (23U) +/*! GPWE7 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK) + +#define PORT_GPCLR_GPWE8_MASK (0x1000000U) +#define PORT_GPCLR_GPWE8_SHIFT (24U) +/*! GPWE8 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK) + +#define PORT_GPCLR_GPWE9_MASK (0x2000000U) +#define PORT_GPCLR_GPWE9_SHIFT (25U) +/*! GPWE9 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK) + +#define PORT_GPCLR_GPWE10_MASK (0x4000000U) +#define PORT_GPCLR_GPWE10_SHIFT (26U) +/*! GPWE10 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK) + +#define PORT_GPCLR_GPWE11_MASK (0x8000000U) +#define PORT_GPCLR_GPWE11_SHIFT (27U) +/*! GPWE11 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK) + +#define PORT_GPCLR_GPWE12_MASK (0x10000000U) +#define PORT_GPCLR_GPWE12_SHIFT (28U) +/*! GPWE12 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK) + +#define PORT_GPCLR_GPWE13_MASK (0x20000000U) +#define PORT_GPCLR_GPWE13_SHIFT (29U) +/*! GPWE13 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK) + +#define PORT_GPCLR_GPWE14_MASK (0x40000000U) +#define PORT_GPCLR_GPWE14_SHIFT (30U) +/*! GPWE14 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK) + +#define PORT_GPCLR_GPWE15_MASK (0x80000000U) +#define PORT_GPCLR_GPWE15_SHIFT (31U) +/*! GPWE15 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK) +/*! @} */ + +/*! @name GPCHR - Global Pin Control High */ +/*! @{ */ + +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) + +#define PORT_GPCHR_GPWE16_MASK (0x10000U) +#define PORT_GPCHR_GPWE16_SHIFT (16U) +/*! GPWE16 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK) + +#define PORT_GPCHR_GPWE17_MASK (0x20000U) +#define PORT_GPCHR_GPWE17_SHIFT (17U) +/*! GPWE17 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK) + +#define PORT_GPCHR_GPWE18_MASK (0x40000U) +#define PORT_GPCHR_GPWE18_SHIFT (18U) +/*! GPWE18 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK) + +#define PORT_GPCHR_GPWE19_MASK (0x80000U) +#define PORT_GPCHR_GPWE19_SHIFT (19U) +/*! GPWE19 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK) + +#define PORT_GPCHR_GPWE20_MASK (0x100000U) +#define PORT_GPCHR_GPWE20_SHIFT (20U) +/*! GPWE20 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK) + +#define PORT_GPCHR_GPWE21_MASK (0x200000U) +#define PORT_GPCHR_GPWE21_SHIFT (21U) +/*! GPWE21 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK) + +#define PORT_GPCHR_GPWE22_MASK (0x400000U) +#define PORT_GPCHR_GPWE22_SHIFT (22U) +/*! GPWE22 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK) + +#define PORT_GPCHR_GPWE23_MASK (0x800000U) +#define PORT_GPCHR_GPWE23_SHIFT (23U) +/*! GPWE23 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK) + +#define PORT_GPCHR_GPWE24_MASK (0x1000000U) +#define PORT_GPCHR_GPWE24_SHIFT (24U) +/*! GPWE24 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK) + +#define PORT_GPCHR_GPWE25_MASK (0x2000000U) +#define PORT_GPCHR_GPWE25_SHIFT (25U) +/*! GPWE25 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK) + +#define PORT_GPCHR_GPWE26_MASK (0x4000000U) +#define PORT_GPCHR_GPWE26_SHIFT (26U) +/*! GPWE26 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK) + +#define PORT_GPCHR_GPWE27_MASK (0x8000000U) +#define PORT_GPCHR_GPWE27_SHIFT (27U) +/*! GPWE27 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK) + +#define PORT_GPCHR_GPWE28_MASK (0x10000000U) +#define PORT_GPCHR_GPWE28_SHIFT (28U) +/*! GPWE28 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK) + +#define PORT_GPCHR_GPWE29_MASK (0x20000000U) +#define PORT_GPCHR_GPWE29_SHIFT (29U) +/*! GPWE29 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK) + +#define PORT_GPCHR_GPWE30_MASK (0x40000000U) +#define PORT_GPCHR_GPWE30_SHIFT (30U) +/*! GPWE30 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK) + +#define PORT_GPCHR_GPWE31_MASK (0x80000000U) +#define PORT_GPCHR_GPWE31_SHIFT (31U) +/*! GPWE31 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK) +/*! @} */ + +/*! @name CONFIG - Configuration */ +/*! @{ */ + +#define PORT_CONFIG_RANGE_MASK (0x1U) +#define PORT_CONFIG_RANGE_SHIFT (0U) +/*! RANGE - Port Voltage Range + * 0b0..1.71 V-3.6 V + * 0b1..2.70 V-3.6 V + */ +#define PORT_CONFIG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK) +/*! @} */ + +/*! @name CALIB0 - Calibration 0 */ +/*! @{ */ + +#define PORT_CALIB0_NCAL_MASK (0x3FU) +#define PORT_CALIB0_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB0_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK) + +#define PORT_CALIB0_PCAL_MASK (0x3F0000U) +#define PORT_CALIB0_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB0_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK) +/*! @} */ + +/*! @name CALIB1 - Calibration 1 */ +/*! @{ */ + +#define PORT_CALIB1_NCAL_MASK (0x3FU) +#define PORT_CALIB1_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB1_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK) + +#define PORT_CALIB1_PCAL_MASK (0x3F0000U) +#define PORT_CALIB1_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK) +/*! @} */ + +/*! @name PCR - Pin Control 0..Pin Control 31 */ +/*! @{ */ + +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +/*! PS - Pull Select + * 0b0..Enables internal pulldown resistor + * 0b1..Enables internal pullup resistor + */ +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) + +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +/*! PE - Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) + +#define PORT_PCR_PV_MASK (0x4U) +#define PORT_PCR_PV_SHIFT (2U) +/*! PV - Pull Value + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_PV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK) + +#define PORT_PCR_SRE_MASK (0x8U) +#define PORT_PCR_SRE_SHIFT (3U) +/*! SRE - Slew Rate Enable + * 0b0..Fast + * 0b1..Slow + */ +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) + +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +/*! PFE - Passive Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) + +#define PORT_PCR_ODE_MASK (0x20U) +#define PORT_PCR_ODE_SHIFT (5U) +/*! ODE - Open Drain Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) + +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +/*! DSE - Drive Strength Enable + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) + +#define PORT_PCR_DSE1_MASK (0x80U) +#define PORT_PCR_DSE1_SHIFT (7U) +/*! DSE1 - Drive Strength Enable + * 0b0..Normal + * 0b1..Double + */ +#define PORT_PCR_DSE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE1_SHIFT)) & PORT_PCR_DSE1_MASK) + +#define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */ +#define PORT_PCR_MUX_SHIFT (8U) +/*! MUX - Pin Multiplex Control + * 0b0000..Alternative 0 (GPIO) + * 0b0001..Alternative 1 (chip-specific) + * 0b0010..Alternative 2 (chip-specific) + * 0b0011..Alternative 3 (chip-specific) + * 0b0100..Alternative 4 (chip-specific) + * 0b0101..Alternative 5 (chip-specific) + * 0b0110..Alternative 6 (chip-specific) + * 0b0111..Alternative 7 (chip-specific) + * 0b1000..Alternative 8 (chip-specific) + * 0b1001..Alternative 9 (chip-specific) + * 0b1010..Alternative 10 (chip-specific) + * 0b1011..Alternative 11 (chip-specific) + * 0b1100..Alternative 12 (chip-specific) + * 0b1101..Alternative 13 (chip-specific) + */ +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */ + +#define PORT_PCR_IBE_MASK (0x1000U) +#define PORT_PCR_IBE_SHIFT (12U) +/*! IBE - Input Buffer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK) + +#define PORT_PCR_INV_MASK (0x2000U) +#define PORT_PCR_INV_SHIFT (13U) +/*! INV - Invert Input + * 0b0..Does not invert + * 0b1..Inverts + */ +#define PORT_PCR_INV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK) + +#define PORT_PCR_LK_MASK (0x8000U) +#define PORT_PCR_LK_SHIFT (15U) +/*! LK - Lock Register + * 0b0..Does not lock + * 0b1..Locks + */ +#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PORT_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PWM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PWM.h new file mode 100644 index 000000000..bab505322 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_PWM.h @@ -0,0 +1,1355 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for PWM +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_PWM.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for PWM + * + * CMSIS Peripheral Access Layer for PWM + */ + +#if !defined(PERI_PWM_H_) +#define PERI_PWM_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Size of Registers Arrays */ +#define PWM_SM_DISMAP_COUNT 1u +#define PWM_SM_COUNT 4u + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + uint8_t RESERVED_1[2]; + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + uint8_t RESERVED_2[2]; + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + uint8_t RESERVED_3[2]; + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + uint8_t RESERVED_4[2]; + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + uint8_t RESERVED_5[2]; + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + uint8_t RESERVED_6[2]; + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[PWM_SM_DISMAP_COUNT]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + uint8_t RESERVED_7[2]; + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + uint8_t RESERVED_8[8]; + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60, irregular array, not all indices are valid */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60, irregular array, not all indices are valid */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60, irregular array, not all indices are valid */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60, irregular array, not all indices are valid */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60, irregular array, not all indices are valid */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60, irregular array, not all indices are valid */ + uint8_t RESERVED_9[16]; + __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-3] */ + uint8_t RESERVED_10[4]; + __IO uint16_t CAPTFILTX; /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60, irregular array, not all indices are valid */ + } SM[PWM_SM_COUNT]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ + +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +/*! CNT - Counter Register Bits */ +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ + +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +/*! INIT - Initial Count Register Bits */ +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it forces the clock to logic 0. + * 0b11..Reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) + +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it forces the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) + +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - Force Select + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the eFlexPWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the eFlexPWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) + +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +/*! FORCE - Force Initialization */ +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) + +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - Force Enable + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) + +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload + * occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) + +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +/*! PWMX_INIT - PWM_X Initial Value */ +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) + +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +/*! PWM45_INIT - PWM45 Initial Value */ +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) + +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +/*! PWM23_INIT - PWM23 Initial Value */ +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) + +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) + +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +/*! DBGEN - Debug Enable */ +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) + +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWM_X Double Switching Enable + * 0b0..PWM_X double pulse disabled. + * 0b1..PWM_X double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) + +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) + +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B + * 0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses. + * 0b1..DBLPWM is split to PWM_A and PWM_B. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) + +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..Prescaler 1 + * 0b001..Prescaler 2 + * 0b010..Prescaler 4 + * 0b011..Prescaler 8 + * 0b100..Prescaler 16 + * 0b101..Prescaler 32 + * 0b110..Prescaler 64 + * 0b111..Prescaler 128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) + +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A + * output that is high at the end of a period maintains this state until a match with VAL3 clears the output + * in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) + +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +/*! DT - Deadtime */ +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) + +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) + +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) + +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ + +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +/*! VAL0 - Value 0 */ +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ + +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +/*! VAL1 - Value 1 */ +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ + +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +/*! VAL2 - Value 2 */ +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ + +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +/*! VAL3 - Value 3 */ +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ + +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +/*! VAL4 - Value 4 */ +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ + +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +/*! VAL5 - Value 5 */ +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ + +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) + +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) + +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) + +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) + +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) + +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) + +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +/*! PWMX_IN - PWM_X Input */ +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) + +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +/*! PWMB_IN - PWM_B Input */ +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) + +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +/*! PWMA_IN - PWM_A Input */ +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ + +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) + +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +/*! CFX0 - Capture Flag X0 */ +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) + +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +/*! CFX1 - Capture Flag X1 */ +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) + +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) + +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) + +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ + +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) + +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) + +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) + +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) + +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ + +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +/*! CX0DE - Capture X0 FIFO DMA Enable */ +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) + +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +/*! CX1DE - Capture X1 FIFO DMA Enable */ +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) + +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CX1DE], or + * DMAEN[CX0DE] to be set to determine which watermark(s) the DMA request is sensitive. + * 0b10..A local synchronization (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) + +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) + +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..Enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ + +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. + * 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value. + * 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value. + * 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value. + * 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value. + * 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) + +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger Frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) + +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Mux Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. + * 0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) + +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Mux Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. + * 0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0 */ +/*! @{ */ + +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +/*! DIS0A - PWM_A Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) + +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +/*! DIS0B - PWM_B Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) + +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +/*! DIS0X - PWM_X Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (1U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ + +#define PWM_DTCNT0_DTCNT0_MASK (0x7FFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +/*! DTCNT0 - Deadtime Count Register 0 */ +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ + +#define PWM_DTCNT1_DTCNT1_MASK (0x7FFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +/*! DTCNT1 - Deadtime Count Register 1 */ +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ + +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) + +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) + +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) + +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) + +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) + +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) + +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +/*! CFXWM - Capture X FIFOs Water Mark */ +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) + +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +/*! CX0CNT - Capture X0 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) + +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +/*! CX1CNT - Capture X1 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ + +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +/*! EDGCMPX - Edge Compare X */ +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) + +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +/*! EDGCNTX - Edge Counter X */ +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ + +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +/*! CAPTVAL0 - Capture Value 0 */ +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +/*! CVAL0CYC - Capture Value 0 Cycle */ +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ + +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +/*! CAPTVAL1 - Capture Value 1 */ +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +/*! CVAL1CYC - Capture Value 1 Cycle */ +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name PHASEDLY - Phase Delay Register */ +/*! @{ */ + +#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) +#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) +/*! PHASEDLY - Initial Count Register Bits */ +#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) +/*! @} */ + +/* The count of PWM_PHASEDLY */ +#define PWM_PHASEDLY_COUNT (4U) + +/*! @name CAPTFILTX - Capture PWM_X Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) +/*! CAPTX_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) + +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) +/*! CAPTX_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTX */ +#define PWM_CAPTFILTX_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ + +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) + +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) + +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ + +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) + +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) + +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) + +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ + +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) + +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) + +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) + +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) + +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) + +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) + +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) + +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ + +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) + +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] used by the deadtime logic. + * 0b11..PWM0_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) + +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) + +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] used by the deadtime logic. + * 0b11..PWM1_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) + +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) + +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] used by the deadtime logic. + * 0b11..PWM2_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) + +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) + +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] used by the deadtime logic. + * 0b11..PWM3_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ + +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) + +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +/*! CLDOK - Clear Load Okay */ +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) + +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM counter is stopped, but PWM outputs hold the current state. + * 0b0001..PWM counter is started in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) + +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ + +#define PWM_MCTRL2_WRPROT_MASK (0xCU) +#define PWM_MCTRL2_WRPROT_SHIFT (2U) +/*! WRPROT - Write protect + * 0b00..Write protection off (default). + * 0b01..Write protection on. + * 0b10..Write protection off and locked until chip reset. + * 0b11..Write protection on and locked until chip reset. + */ +#define PWM_MCTRL2_WRPROT(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK) + +#define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK (0xC0U) +#define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT (6U) +/*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig + * 0b00..Stretch count is zero, no stretch. + * 0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period. + * 0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period. + * 0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period. + */ +#define PWM_MCTRL2_STRETCH_CNT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ + +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) + +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard + * to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be + * cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input + * signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in + * DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and + * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) + +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If + * neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled + * by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without + * regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition + * cannot be cleared. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) + +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ + +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) + +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) + +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +/*! FFPIN - Filtered Fault Pins */ +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) + +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ + +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Fault Filter Period */ +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) + +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Fault Filter Count */ +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) + +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals are stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ + +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ + +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PWM_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_RTC.h new file mode 100644 index 000000000..862b51573 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_RTC.h @@ -0,0 +1,358 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for RTC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_RTC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for RTC + * + * CMSIS Peripheral Access Layer for RTC + */ + +#if !defined(PERI_RTC_H_) +#define PERI_RTC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t TSR; /**< RTC Time Seconds, offset: 0x0 */ + __IO uint32_t TPR; /**< RTC Time Prescaler, offset: 0x4 */ + __IO uint32_t TAR; /**< RTC Time Alarm, offset: 0x8 */ + __IO uint32_t TCR; /**< RTC Time Compensation, offset: 0xC */ + __IO uint32_t CR; /**< RTC Control, offset: 0x10 */ + __IO uint32_t SR; /**< RTC Status, offset: 0x14 */ + __IO uint32_t LR; /**< RTC Lock, offset: 0x18 */ + __IO uint32_t IER; /**< RTC Interrupt Enable, offset: 0x1C */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name TSR - RTC Time Seconds */ +/*! @{ */ + +#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) +#define RTC_TSR_TSR_SHIFT (0U) +/*! TSR - Time Seconds Register */ +#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) +/*! @} */ + +/*! @name TPR - RTC Time Prescaler */ +/*! @{ */ + +#define RTC_TPR_TPR_MASK (0xFFFFU) +#define RTC_TPR_TPR_SHIFT (0U) +/*! TPR - Time Prescaler Register */ +#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) +/*! @} */ + +/*! @name TAR - RTC Time Alarm */ +/*! @{ */ + +#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) +#define RTC_TAR_TAR_SHIFT (0U) +/*! TAR - Time Alarm Register */ +#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) +/*! @} */ + +/*! @name TCR - RTC Time Compensation */ +/*! @{ */ + +#define RTC_TCR_TCR_MASK (0xFFU) +#define RTC_TCR_TCR_SHIFT (0U) +/*! TCR - Time Compensation Register + * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. + * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. + * 0b01111110..Time Prescaler Register overflows every 32642 clock cycles. + * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles. + * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. + * 0b10000001..Time Prescaler Register overflows every 32895 clock cycles. + * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. + */ +#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) + +#define RTC_TCR_CIR_MASK (0xFF00U) +#define RTC_TCR_CIR_SHIFT (8U) +/*! CIR - Compensation Interval Register */ +#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) + +#define RTC_TCR_TCV_MASK (0xFF0000U) +#define RTC_TCR_TCV_SHIFT (16U) +/*! TCV - Time Compensation Value */ +#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) + +#define RTC_TCR_CIC_MASK (0xFF000000U) +#define RTC_TCR_CIC_SHIFT (24U) +/*! CIC - Compensation Interval Counter */ +#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) +/*! @} */ + +/*! @name CR - RTC Control */ +/*! @{ */ + +#define RTC_CR_SWR_MASK (0x1U) +#define RTC_CR_SWR_SHIFT (0U) +/*! SWR - Software Reset + * 0b0..No effect. + * 0b1..Resets all RTC registers except for this bit . This bit is cleared by POR and by software explicitly clearing it. + */ +#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) + +#define RTC_CR_UM_MASK (0x8U) +#define RTC_CR_UM_SHIFT (3U) +/*! UM - Update Mode + * 0b0..Registers cannot be written when locked. + * 0b1..Registers can be written when locked under limited conditions. + */ +#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) + +#define RTC_CR_LPOS_MASK (0x80U) +#define RTC_CR_LPOS_SHIFT (7U) +/*! LPOS - LPO Select + * 0b0..RTC prescaler increments using 32.768 kHz clock. + * 0b1..RTC prescaler increments using 16.384 kHz LPO. Bit [0] of the prescaler is ignored. + */ +#define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK) +/*! @} */ + +/*! @name SR - RTC Status */ +/*! @{ */ + +#define RTC_SR_TIF_MASK (0x1U) +#define RTC_SR_TIF_SHIFT (0U) +/*! TIF - Time Invalid Flag + * 0b0..Time is valid. + * 0b1..Time is invalid and time counter is read as zero. + */ +#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) + +#define RTC_SR_TOF_MASK (0x2U) +#define RTC_SR_TOF_SHIFT (1U) +/*! TOF - Time Overflow Flag + * 0b0..Time overflow has not occurred. + * 0b1..Time overflow has occurred and time counter reads as zero. + */ +#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) + +#define RTC_SR_TAF_MASK (0x4U) +#define RTC_SR_TAF_SHIFT (2U) +/*! TAF - Time Alarm Flag + * 0b0..Time alarm has not occurred. + * 0b1..Time alarm has occurred. + */ +#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) + +#define RTC_SR_TCE_MASK (0x10U) +#define RTC_SR_TCE_SHIFT (4U) +/*! TCE - Time Counter Enable + * 0b0..Disables. + * 0b1..Enables. + */ +#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) +/*! @} */ + +/*! @name LR - RTC Lock */ +/*! @{ */ + +#define RTC_LR_TCL_MASK (0x8U) +#define RTC_LR_TCL_SHIFT (3U) +/*! TCL - Time Compensation Lock + * 0b0..Time Compensation Register is locked and writes are ignored. + * 0b1..Time Compensation Register is not locked and writes complete as normal. + */ +#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) + +#define RTC_LR_CRL_MASK (0x10U) +#define RTC_LR_CRL_SHIFT (4U) +/*! CRL - Control Register Lock + * 0b0..Control Register is locked and writes are ignored. + * 0b1..Control Register is not locked and writes complete as normal. + */ +#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) + +#define RTC_LR_SRL_MASK (0x20U) +#define RTC_LR_SRL_SHIFT (5U) +/*! SRL - Status Register Lock + * 0b0..Status Register is locked and writes are ignored. + * 0b1..Status Register is not locked and writes complete as normal. + */ +#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) + +#define RTC_LR_LRL_MASK (0x40U) +#define RTC_LR_LRL_SHIFT (6U) +/*! LRL - Lock Register Lock + * 0b0..Lock Register is locked and writes are ignored. + * 0b1..Lock Register is not locked and writes complete as normal. + */ +#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) +/*! @} */ + +/*! @name IER - RTC Interrupt Enable */ +/*! @{ */ + +#define RTC_IER_TIIE_MASK (0x1U) +#define RTC_IER_TIIE_SHIFT (0U) +/*! TIIE - Time Invalid Interrupt Enable + * 0b0..No interrupt is generated. + * 0b1..An interrupt is generated. + */ +#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) + +#define RTC_IER_TOIE_MASK (0x2U) +#define RTC_IER_TOIE_SHIFT (1U) +/*! TOIE - Time Overflow Interrupt Enable + * 0b0..No interrupt is generated. + * 0b1..An interrupt is generated. + */ +#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) + +#define RTC_IER_TAIE_MASK (0x4U) +#define RTC_IER_TAIE_SHIFT (2U) +/*! TAIE - Time Alarm Interrupt Enable + * 0b0..No interrupt is generated. + * 0b1..An interrupt is generated. + */ +#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) + +#define RTC_IER_TSIE_MASK (0x10U) +#define RTC_IER_TSIE_SHIFT (4U) +/*! TSIE - Time Seconds Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) + +#define RTC_IER_TSIC_MASK (0x70000U) +#define RTC_IER_TSIC_SHIFT (16U) +/*! TSIC - Timer Seconds Interrupt Configuration + * 0b000..1 Hz. + * 0b001..2 Hz. + * 0b010..4 Hz. + * 0b011..8 Hz. + * 0b100..16 Hz. + * 0b101..32 Hz. + * 0b110..64 Hz. + * 0b111..128 Hz. + */ +#define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_RTC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SCG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SCG.h new file mode 100644 index 000000000..fb005601f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SCG.h @@ -0,0 +1,720 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for SCG +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_SCG.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for SCG + * + * CMSIS Peripheral Access Layer for SCG + */ + +#if !defined(PERI_SCG_H_) +#define PERI_SCG_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer + * @{ + */ + +/** SCG - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t TRIM_LOCK; /**< Trim Lock, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< Clock Status, offset: 0x10 */ + __IO uint32_t RCCR; /**< Run Clock Control, offset: 0x14 */ + uint8_t RESERVED_1[232]; + __IO uint32_t SOSCCSR; /**< SOSC Control Status, offset: 0x100 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOSCCFG; /**< SOSC Configuration, offset: 0x108 */ + uint8_t RESERVED_3[244]; + __IO uint32_t SIRCCSR; /**< SIRC Control Status, offset: 0x200 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration, offset: 0x20C */ + __IO uint32_t SIRCTRIM; /**< SIRC Trim, offset: 0x210 */ + uint8_t RESERVED_5[4]; + __IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status, offset: 0x218 */ + uint8_t RESERVED_6[228]; + __IO uint32_t FIRCCSR; /**< FIRC Control Status, offset: 0x300 */ + uint8_t RESERVED_7[4]; + __IO uint32_t FIRCCFG; /**< FIRC Configuration, offset: 0x308 */ + uint8_t RESERVED_8[4]; + __IO uint32_t FIRCTRIM; /**< FIRC Trim, offset: 0x310 */ + uint8_t RESERVED_9[236]; + __IO uint32_t ROSCCSR; /**< ROSC Control Status, offset: 0x400 */ + uint8_t RESERVED_10[1020]; + __IO uint32_t LDOCSR; /**< LDO Control and Status, offset: 0x800 */ +} SCG_Type; + +/* ---------------------------------------------------------------------------- + -- SCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Register_Masks SCG Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) +#define SCG_VERID_VERSION_SHIFT (0U) +/*! VERSION - SCG Version Number */ +#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define SCG_PARAM_SOSCCLKPRES_MASK (0x2U) +#define SCG_PARAM_SOSCCLKPRES_SHIFT (1U) +/*! SOSCCLKPRES - SOSC Clock Present + * 0b0..SOSC clock source is not present + * 0b1..SOSC clock source is present + */ +#define SCG_PARAM_SOSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK) + +#define SCG_PARAM_SIRCCLKPRES_MASK (0x4U) +#define SCG_PARAM_SIRCCLKPRES_SHIFT (2U) +/*! SIRCCLKPRES - SIRC Clock Present + * 0b0..SIRC clock source is not present + * 0b1..SIRC clock source is present + */ +#define SCG_PARAM_SIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK) + +#define SCG_PARAM_FIRCCLKPRES_MASK (0x8U) +#define SCG_PARAM_FIRCCLKPRES_SHIFT (3U) +/*! FIRCCLKPRES - FIRC Clock Present + * 0b0..FIRC clock source is not present + * 0b1..FIRC clock source is present + */ +#define SCG_PARAM_FIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK) + +#define SCG_PARAM_ROSCCLKPRES_MASK (0x10U) +#define SCG_PARAM_ROSCCLKPRES_SHIFT (4U) +/*! ROSCCLKPRES - ROSC Clock Present + * 0b0..ROSC clock source is not present + * 0b1..ROSC clock source is present + */ +#define SCG_PARAM_ROSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK) +/*! @} */ + +/*! @name TRIM_LOCK - Trim Lock */ +/*! @{ */ + +#define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK (0x1U) +#define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT (0U) +/*! TRIM_UNLOCK - TRIM_UNLOCK + * 0b0..SCG Trim Registers locked and not writable. + * 0b1..SCG Trim registers unlocked and writable. + */ +#define SCG_TRIM_LOCK_TRIM_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK) + +#define SCG_TRIM_LOCK_IFR_DISABLE_MASK (0x2U) +#define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT (1U) +/*! IFR_DISABLE - IFR_DISABLE + * 0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. + * 0b1..IFR write access to SCG trim registers during system reset is blocked. + */ +#define SCG_TRIM_LOCK_IFR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK) + +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK (0xFFFF0000U) +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT (16U) +/*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */ +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK) +/*! @} */ + +/*! @name CSR - Clock Status */ +/*! @{ */ + +#define SCG_CSR_SCS_MASK (0x7000000U) +#define SCG_CSR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b001..SOSC + * 0b010..SIRC + * 0b011..FIRC + * 0b100..ROSC + */ +#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) +/*! @} */ + +/*! @name RCCR - Run Clock Control */ +/*! @{ */ + +#define SCG_RCCR_SCS_MASK (0x7000000U) +#define SCG_RCCR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b001..SOSC + * 0b010..SIRC + * 0b011..FIRC + * 0b100..ROSC + */ +#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) +/*! @} */ + +/*! @name SOSCCSR - SOSC Control Status */ +/*! @{ */ + +#define SCG_SOSCCSR_SOSCEN_MASK (0x1U) +#define SCG_SOSCCSR_SOSCEN_SHIFT (0U) +/*! SOSCEN - SOSC Enable + * 0b0..SOSC is disabled + * 0b1..SOSC is enabled + */ +#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) + +#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) +#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) +/*! SOSCSTEN - SOSC Stop Enable + * 0b0..SOSC is disabled in Deep Sleep mode + * 0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set + */ +#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) + +#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) +#define SCG_SOSCCSR_SOSCCM_SHIFT (16U) +/*! SOSCCM - SOSC Clock Monitor Enable + * 0b0..SOSC Clock Monitor is disabled + * 0b1..SOSC Clock Monitor is enabled + */ +#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) + +#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) +#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) +/*! SOSCCMRE - SOSC Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) + +#define SCG_SOSCCSR_LK_MASK (0x800000U) +#define SCG_SOSCCSR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..This Control Status Register can be written + * 0b1..This Control Status Register cannot be written + */ +#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) + +#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) +#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) +/*! SOSCVLD - SOSC Valid + * 0b0..SOSC is not enabled or clock is not valid + * 0b1..SOSC is enabled and output clock is valid + */ +#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) + +#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) +#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) +/*! SOSCSEL - SOSC Selected + * 0b0..SOSC is not the system clock source + * 0b1..SOSC is the system clock source + */ +#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) + +#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) +#define SCG_SOSCCSR_SOSCERR_SHIFT (26U) +/*! SOSCERR - SOSC Clock Error + * 0b0..SOSC Clock Monitor is disabled or has not detected an error + * 0b1..SOSC Clock Monitor is enabled and detected an error + */ +#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) + +#define SCG_SOSCCSR_SOSCVLD_IE_MASK (0x40000000U) +#define SCG_SOSCCSR_SOSCVLD_IE_SHIFT (30U) +/*! SOSCVLD_IE - SOSC Valid Interrupt Enable + * 0b0..SOSCVLD interrupt is not enabled + * 0b1..SOSCVLD interrupt is enabled + */ +#define SCG_SOSCCSR_SOSCVLD_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK) +/*! @} */ + +/*! @name SOSCCFG - SOSC Configuration */ +/*! @{ */ + +#define SCG_SOSCCFG_EREFS_MASK (0x4U) +#define SCG_SOSCCFG_EREFS_SHIFT (2U) +/*! EREFS - External Reference Select + * 0b0..External reference clock selected. + * 0b1..Internal crystal oscillator of OSC selected. + */ +#define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) + +#define SCG_SOSCCFG_RANGE_MASK (0x30U) +#define SCG_SOSCCFG_RANGE_SHIFT (4U) +/*! RANGE - SOSC Range Select + * 0b00..Frequency range select of 8-16 MHz. + * 0b01..Frequency range select of 16-25 MHz. + * 0b10..Frequency range select of 25-40 MHz. + * 0b11..Frequency range select of 40-50 MHz. + */ +#define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) +/*! @} */ + +/*! @name SIRCCSR - SIRC Control Status */ +/*! @{ */ + +#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) +#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) +/*! SIRCSTEN - SIRC Stop Enable + * 0b0..SIRC is disabled in Deep Sleep mode + * 0b1..SIRC is enabled in Deep Sleep mode + */ +#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) + +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK (0x20U) +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT (5U) +/*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable + * 0b0..SIRC clock to peripherals is disabled + * 0b1..SIRC clock to peripherals is enabled + */ +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) + +#define SCG_SIRCCSR_SIRCTREN_MASK (0x100U) +#define SCG_SIRCCSR_SIRCTREN_SHIFT (8U) +/*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1) + * 0b0..Disables trimming SIRC to an external clock source + * 0b1..Enables trimming SIRC to an external clock source + */ +#define SCG_SIRCCSR_SIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK) + +#define SCG_SIRCCSR_SIRCTRUP_MASK (0x200U) +#define SCG_SIRCCSR_SIRCTRUP_SHIFT (9U) +/*! SIRCTRUP - SIRC Trim Update + * 0b0..Disables SIRC trimming updates + * 0b1..Enables SIRC trimming updates + */ +#define SCG_SIRCCSR_SIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK) + +#define SCG_SIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_SIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - SIRC TRIM LOCK + * 0b0..SIRC auto trim not locked to target frequency range + * 0b1..SIRC auto trim locked to target frequency range + */ +#define SCG_SIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK) + +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..SIRC Coarse Auto Trim NOT Bypassed + * 0b1..SIRC Coarse Auto Trim Bypassed + */ +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_SIRCCSR_LK_MASK (0x800000U) +#define SCG_SIRCCSR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) + +#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) +#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) +/*! SIRCVLD - SIRC Valid + * 0b0..SIRC is not enabled or clock is not valid + * 0b1..SIRC is enabled and output clock is valid + */ +#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) + +#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) +#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) +/*! SIRCSEL - SIRC Selected + * 0b0..SIRC is not the system clock source + * 0b1..SIRC is the system clock source + */ +#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) + +#define SCG_SIRCCSR_SIRCERR_MASK (0x4000000U) +#define SCG_SIRCCSR_SIRCERR_SHIFT (26U) +/*! SIRCERR - SIRC Clock Error + * 0b0..Error not detected with the SIRC trimming + * 0b1..Error detected with the SIRC trimming + */ +#define SCG_SIRCCSR_SIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK) + +#define SCG_SIRCCSR_SIRCERR_IE_MASK (0x8000000U) +#define SCG_SIRCCSR_SIRCERR_IE_SHIFT (27U) +/*! SIRCERR_IE - SIRC Clock Error Interrupt Enable + * 0b0..SIRCERR interrupt is not enabled + * 0b1..SIRCERR interrupt is enabled + */ +#define SCG_SIRCCSR_SIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK) +/*! @} */ + +/*! @name SIRCTCFG - SIRC Trim Configuration */ +/*! @{ */ + +#define SCG_SIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_SIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..Reserved + * 0b01..Reserved + * 0b10..SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. + * 0b11..Reserved + */ +#define SCG_SIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK) + +#define SCG_SIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_SIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - SIRC Trim Pre-divider */ +#define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name SIRCTRIM - SIRC Trim */ +/*! @{ */ + +#define SCG_SIRCTRIM_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCTRIM_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCTRIM_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK) + +#define SCG_SIRCTRIM_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCTRIM_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCTRIM_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK) + +#define SCG_SIRCTRIM_TCTRIM_MASK (0x1F0000U) +#define SCG_SIRCTRIM_TCTRIM_SHIFT (16U) +/*! TCTRIM - Trim Temp */ +#define SCG_SIRCTRIM_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK) + +#define SCG_SIRCTRIM_FVCHTRIM_MASK (0x1F000000U) +#define SCG_SIRCTRIM_FVCHTRIM_SHIFT (24U) +#define SCG_SIRCTRIM_FVCHTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK) +/*! @} */ + +/*! @name SIRCSTAT - SIRC Auto-trimming Status */ +/*! @{ */ + +#define SCG_SIRCSTAT_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCSTAT_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCSTAT_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK) + +#define SCG_SIRCSTAT_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCSTAT_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCSTAT_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK) +/*! @} */ + +/*! @name FIRCCSR - FIRC Control Status */ +/*! @{ */ + +#define SCG_FIRCCSR_FIRCEN_MASK (0x1U) +#define SCG_FIRCCSR_FIRCEN_SHIFT (0U) +/*! FIRCEN - FIRC Enable + * 0b0..FIRC is disabled + * 0b1..FIRC is enabled + */ +#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) + +#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) +#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) +/*! FIRCSTEN - FIRC Stop Enable + * 0b0..FIRC is disabled in Deep Sleep mode + * 0b1..FIRC is enabled in Deep Sleep mode + */ +#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) + +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK (0x10U) +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT (4U) +/*! FIRC_SCLK_PERIPH_EN - FIRC 45 MHz Clock to peripherals Enable + * 0b0..FIRC 45 MHz to peripherals is disabled + * 0b1..FIRC 45 MHz to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK (0x20U) +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT (5U) +/*! FIRC_FCLK_PERIPH_EN - FRO_HF Clock to peripherals Enable + * 0b0..FRO_HF to peripherals is disabled + * 0b1..FRO_HF to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_LK_MASK (0x800000U) +#define SCG_FIRCCSR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) + +#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) +#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) +/*! FIRCVLD - FIRC Valid status + * 0b0..FIRC is not enabled or clock is not valid. + * 0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. + */ +#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) + +#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) +#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) +/*! FIRCSEL - FIRC Selected + * 0b0..FIRC is not the system clock source + * 0b1..FIRC is the system clock source + */ +#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) + +#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) +#define SCG_FIRCCSR_FIRCERR_SHIFT (26U) +/*! FIRCERR - FIRC Clock Error + * 0b0..Error not detected with the FIRC trimming + * 0b1..Error detected with the FIRC trimming + */ +#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) + +#define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) +#define SCG_FIRCCSR_FIRCERR_IE_SHIFT (27U) +/*! FIRCERR_IE - FIRC Clock Error Interrupt Enable + * 0b0..FIRCERR interrupt is not enabled + * 0b1..FIRCERR interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_IE_MASK (0x40000000U) +#define SCG_FIRCCSR_FIRCACC_IE_SHIFT (30U) +/*! FIRCACC_IE - FIRC Accurate Interrupt Enable + * 0b0..FIRCACC interrupt is not enabled + * 0b1..FIRCACC interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCACC_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_MASK (0x80000000U) +#define SCG_FIRCCSR_FIRCACC_SHIFT (31U) +/*! FIRCACC - FIRC Frequency Accurate + * 0b0..FIRC is not enabled or clock is not accurate. + * 0b1..FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock. + */ +#define SCG_FIRCCSR_FIRCACC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK) +/*! @} */ + +/*! @name FIRCCFG - FIRC Configuration */ +/*! @{ */ + +#define SCG_FIRCCFG_FREQ_SEL_MASK (0xEU) +#define SCG_FIRCCFG_FREQ_SEL_SHIFT (1U) +/*! FREQ_SEL - Frequency select + * 0b001..45 MHz FIRC clock selected, divided from 180 MHz + * 0b011..60 MHz FIRC clock selected + * 0b101..90 MHz FIRC clock selected + * 0b111..180 MHz FIRC clock selected + */ +#define SCG_FIRCCFG_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_FREQ_SEL_SHIFT)) & SCG_FIRCCFG_FREQ_SEL_MASK) +/*! @} */ + +/*! @name FIRCTRIM - FIRC Trim */ +/*! @{ */ + +#define SCG_FIRCTRIM_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCTRIM_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCTRIM_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK) + +#define SCG_FIRCTRIM_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCTRIM_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCTRIM_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK) + +#define SCG_FIRCTRIM_TRIMTEMP_MASK (0xF0000U) +#define SCG_FIRCTRIM_TRIMTEMP_SHIFT (16U) +/*! TRIMTEMP - Trim Temperature */ +#define SCG_FIRCTRIM_TRIMTEMP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP_MASK) + +#define SCG_FIRCTRIM_TRIMSTART_MASK (0x3F000000U) +#define SCG_FIRCTRIM_TRIMSTART_SHIFT (24U) +/*! TRIMSTART - Trim Start */ +#define SCG_FIRCTRIM_TRIMSTART(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK) +/*! @} */ + +/*! @name ROSCCSR - ROSC Control Status */ +/*! @{ */ + +#define SCG_ROSCCSR_LK_MASK (0x800000U) +#define SCG_ROSCCSR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) + +#define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) +#define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) +/*! ROSCVLD - ROSC Valid + * 0b0..ROSC is not enabled or clock is not valid + * 0b1..ROSC is enabled and output clock is valid + */ +#define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) + +#define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) +#define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) +/*! ROSCSEL - ROSC Selected + * 0b0..ROSC is not the system clock source + * 0b1..ROSC is the system clock source + */ +#define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) + +#define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) +#define SCG_ROSCCSR_ROSCERR_SHIFT (26U) +/*! ROSCERR - ROSC Clock Error + * 0b0..ROSC Clock has not detected an error + * 0b1..ROSC Clock has detected an error + */ +#define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) +/*! @} */ + +/*! @name LDOCSR - LDO Control and Status */ +/*! @{ */ + +#define SCG_LDOCSR_LDOEN_MASK (0x1U) +#define SCG_LDOCSR_LDOEN_SHIFT (0U) +/*! LDOEN - LDO Enable + * 0b0..LDO is disabled + * 0b1..LDO is enabled + */ +#define SCG_LDOCSR_LDOEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOEN_SHIFT)) & SCG_LDOCSR_LDOEN_MASK) + +#define SCG_LDOCSR_VOUT_SEL_MASK (0xEU) +#define SCG_LDOCSR_VOUT_SEL_SHIFT (1U) +/*! VOUT_SEL - LDO output voltage select + * 0b000..VOUT = 1V + * 0b001..VOUT = 1V + * 0b010..VOUT = 1V + * 0b011..VOUT = 1.05V + * 0b100..VOUT = 1.1V + * 0b101..VOUT = 1.15V + * 0b110..VOUT = 1.2V + * 0b111..VOUT = 1.25V + */ +#define SCG_LDOCSR_VOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_SEL_SHIFT)) & SCG_LDOCSR_VOUT_SEL_MASK) + +#define SCG_LDOCSR_LDOBYPASS_MASK (0x10U) +#define SCG_LDOCSR_LDOBYPASS_SHIFT (4U) +/*! LDOBYPASS - LDO Bypass + * 0b0..LDO is not bypassed + * 0b1..LDO is bypassed + */ +#define SCG_LDOCSR_LDOBYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOBYPASS_SHIFT)) & SCG_LDOCSR_LDOBYPASS_MASK) + +#define SCG_LDOCSR_VOUT_OK_MASK (0x80000000U) +#define SCG_LDOCSR_VOUT_OK_SHIFT (31U) +/*! VOUT_OK - LDO VOUT OK Inform. + * 0b0..LDO output VOUT is not OK + * 0b1..LDO output VOUT is OK + */ +#define SCG_LDOCSR_VOUT_OK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SCG_Register_Masks */ + + +/*! + * @} + */ /* end of group SCG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SCG_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SMARTDMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SMARTDMA.h new file mode 100644 index 000000000..a4309390b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SMARTDMA.h @@ -0,0 +1,253 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for SMARTDMA +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_SMARTDMA.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for SMARTDMA + * + * CMSIS Peripheral Access Layer for SMARTDMA + */ + +#if !defined(PERI_SMARTDMA_H_) +#define PERI_SMARTDMA_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Peripheral_Access_Layer SMARTDMA Peripheral Access Layer + * @{ + */ + +/** SMARTDMA - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t BOOTADR; /**< Boot Address, offset: 0x20 */ + __IO uint32_t CTRL; /**< Control, offset: 0x24 */ + __I uint32_t PC; /**< Program Counter, offset: 0x28 */ + __I uint32_t SP; /**< Stack Pointer, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t ARM2EZH; /**< ARM to EZH Interrupt Control, offset: 0x40 */ + __IO uint32_t EZH2ARM; /**< EZH to ARM Trigger, offset: 0x44 */ + __IO uint32_t PENDTRAP; /**< Pending Trap Control, offset: 0x48 */ +} SMARTDMA_Type; + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Register_Masks SMARTDMA Register Masks + * @{ + */ + +/*! @name BOOTADR - Boot Address */ +/*! @{ */ + +#define SMARTDMA_BOOTADR_ADDR_MASK (0xFFFFFFFCU) +#define SMARTDMA_BOOTADR_ADDR_SHIFT (2U) +/*! ADDR - 32-bit boot address, the boot address should be 4-byte aligned. */ +#define SMARTDMA_BOOTADR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BOOTADR_ADDR_SHIFT)) & SMARTDMA_BOOTADR_ADDR_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define SMARTDMA_CTRL_START_MASK (0x1U) +#define SMARTDMA_CTRL_START_SHIFT (0U) +/*! START - Start Bit Ignition */ +#define SMARTDMA_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_START_SHIFT)) & SMARTDMA_CTRL_START_MASK) + +#define SMARTDMA_CTRL_EXF_MASK (0x2U) +#define SMARTDMA_CTRL_EXF_SHIFT (1U) +/*! EXF - External Flag */ +#define SMARTDMA_CTRL_EXF(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_EXF_SHIFT)) & SMARTDMA_CTRL_EXF_MASK) + +#define SMARTDMA_CTRL_ERRDIS_MASK (0x4U) +#define SMARTDMA_CTRL_ERRDIS_SHIFT (2U) +/*! ERRDIS - Error Disable */ +#define SMARTDMA_CTRL_ERRDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_ERRDIS_SHIFT)) & SMARTDMA_CTRL_ERRDIS_MASK) + +#define SMARTDMA_CTRL_BUFEN_MASK (0x8U) +#define SMARTDMA_CTRL_BUFEN_SHIFT (3U) +/*! BUFEN - Buffer Enable */ +#define SMARTDMA_CTRL_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_BUFEN_SHIFT)) & SMARTDMA_CTRL_BUFEN_MASK) + +#define SMARTDMA_CTRL_SYNCEN_MASK (0x10U) +#define SMARTDMA_CTRL_SYNCEN_SHIFT (4U) +/*! SYNCEN - Sync Enable */ +#define SMARTDMA_CTRL_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_SYNCEN_SHIFT)) & SMARTDMA_CTRL_SYNCEN_MASK) + +#define SMARTDMA_CTRL_WKEY_MASK (0xFFFF0000U) +#define SMARTDMA_CTRL_WKEY_SHIFT (16U) +/*! WKEY - Write Key */ +#define SMARTDMA_CTRL_WKEY(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_WKEY_SHIFT)) & SMARTDMA_CTRL_WKEY_MASK) +/*! @} */ + +/*! @name PC - Program Counter */ +/*! @{ */ + +#define SMARTDMA_PC_PC_MASK (0xFFFFFFFFU) +#define SMARTDMA_PC_PC_SHIFT (0U) +/*! PC - Program Counter */ +#define SMARTDMA_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PC_PC_SHIFT)) & SMARTDMA_PC_PC_MASK) +/*! @} */ + +/*! @name SP - Stack Pointer */ +/*! @{ */ + +#define SMARTDMA_SP_SP_MASK (0xFFFFFFFFU) +#define SMARTDMA_SP_SP_SHIFT (0U) +/*! SP - Stack Pointer */ +#define SMARTDMA_SP_SP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_SP_SP_SHIFT)) & SMARTDMA_SP_SP_MASK) +/*! @} */ + +/*! @name ARM2EZH - ARM to EZH Interrupt Control */ +/*! @{ */ + +#define SMARTDMA_ARM2EZH_IE_MASK (0x3U) +#define SMARTDMA_ARM2EZH_IE_SHIFT (0U) +/*! IE - Interrupt Enable */ +#define SMARTDMA_ARM2EZH_IE(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_IE_SHIFT)) & SMARTDMA_ARM2EZH_IE_MASK) + +#define SMARTDMA_ARM2EZH_GP_MASK (0xFFFFFFFCU) +#define SMARTDMA_ARM2EZH_GP_SHIFT (2U) +/*! GP - General purpose register bits */ +#define SMARTDMA_ARM2EZH_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_GP_SHIFT)) & SMARTDMA_ARM2EZH_GP_MASK) +/*! @} */ + +/*! @name EZH2ARM - EZH to ARM Trigger */ +/*! @{ */ + +#define SMARTDMA_EZH2ARM_GP_MASK (0xFFFFFFFFU) +#define SMARTDMA_EZH2ARM_GP_SHIFT (0U) +/*! GP - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH [1:0] == 2h */ +#define SMARTDMA_EZH2ARM_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EZH2ARM_GP_SHIFT)) & SMARTDMA_EZH2ARM_GP_MASK) +/*! @} */ + +/*! @name PENDTRAP - Pending Trap Control */ +/*! @{ */ + +#define SMARTDMA_PENDTRAP_STATUS_MASK (0xFFU) +#define SMARTDMA_PENDTRAP_STATUS_SHIFT (0U) +/*! STATUS - Status Flag or Pending Trap Request */ +#define SMARTDMA_PENDTRAP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_STATUS_SHIFT)) & SMARTDMA_PENDTRAP_STATUS_MASK) + +#define SMARTDMA_PENDTRAP_POL_MASK (0xFF00U) +#define SMARTDMA_PENDTRAP_POL_SHIFT (8U) +/*! POL - Polarity */ +#define SMARTDMA_PENDTRAP_POL(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_POL_SHIFT)) & SMARTDMA_PENDTRAP_POL_MASK) + +#define SMARTDMA_PENDTRAP_EN_MASK (0xFF0000U) +#define SMARTDMA_PENDTRAP_EN_SHIFT (16U) +/*! EN - Enable Pending Trap */ +#define SMARTDMA_PENDTRAP_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_EN_SHIFT)) & SMARTDMA_PENDTRAP_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SMARTDMA_Register_Masks */ + + +/*! + * @} + */ /* end of group SMARTDMA_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SMARTDMA_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SPC.h new file mode 100644 index 000000000..274de6a17 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SPC.h @@ -0,0 +1,818 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for SPC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_SPC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for SPC + * + * CMSIS Peripheral Access Layer for SPC + */ + +#if !defined(PERI_SPC_H_) +#define PERI_SPC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer + * @{ + */ + +/** SPC - Size of Registers Arrays */ +#define SPC_PD_STATUS_COUNT 1u + +/** SPC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SC; /**< Status Control, offset: 0x10 */ + __IO uint32_t CNTRL; /**< SPC Regulator Control, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPREQ_CFG; /**< Low-Power Request Configuration, offset: 0x1C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PD_STATUS[SPC_PD_STATUS_COUNT]; /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SRAMCTL; /**< SRAM Control, offset: 0x40 */ + uint8_t RESERVED_4[16]; + __IO uint32_t SRAMRETLDO_REFTRIM; /**< SRAM Retention Reference Trim, offset: 0x54 */ + __IO uint32_t SRAMRETLDO_CNTRL; /**< SRAM Retention LDO Control, offset: 0x58 */ + uint8_t RESERVED_5[4]; + __IO uint32_t HP_CNFG_CTRL; /**< High Power Config Control, offset: 0x60 */ + uint8_t RESERVED_6[156]; + __IO uint32_t ACTIVE_CFG; /**< Active Power Mode Configuration, offset: 0x100 */ + __IO uint32_t ACTIVE_CFG1; /**< Active Power Mode Configuration 1, offset: 0x104 */ + __IO uint32_t LP_CFG; /**< Low-Power Mode Configuration, offset: 0x108 */ + __IO uint32_t LP_CFG1; /**< Low Power Mode Configuration 1, offset: 0x10C */ + __IO uint32_t HP_CFG; /**< High Power Mode Configuration, offset: 0x110 */ + uint8_t RESERVED_7[12]; + __IO uint32_t LPWKUP_DELAY; /**< Low Power Wake-Up Delay, offset: 0x120 */ + __IO uint32_t ACTIVE_VDELAY; /**< Active Voltage Trim Delay, offset: 0x124 */ + uint8_t RESERVED_8[8]; + __IO uint32_t VD_STAT; /**< Voltage Detect Status, offset: 0x130 */ + __IO uint32_t VD_CORE_CFG; /**< Core Voltage Detect Configuration, offset: 0x134 */ + __IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */ + uint8_t RESERVED_9[4]; + __IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */ + __IO uint32_t GLITCH_DETECT_SC; /**< Glitch Detect Status Control, offset: 0x144 */ + uint8_t RESERVED_10[440]; + uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */ +} SPC_Type; + +/* ---------------------------------------------------------------------------- + -- SPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Register_Masks SPC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define SPC_VERID_FEATURE_MASK (0xFFFFU) +#define SPC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features + */ +#define SPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK) + +#define SPC_VERID_MINOR_MASK (0xFF0000U) +#define SPC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define SPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK) + +#define SPC_VERID_MAJOR_MASK (0xFF000000U) +#define SPC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define SPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name SC - Status Control */ +/*! @{ */ + +#define SPC_SC_BUSY_MASK (0x1U) +#define SPC_SC_BUSY_SHIFT (0U) +/*! BUSY - SPC Busy Status Flag + * 0b0..Not busy + * 0b1..Busy + */ +#define SPC_SC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK) + +#define SPC_SC_SPC_LP_REQ_MASK (0x2U) +#define SPC_SC_SPC_LP_REQ_SHIFT (1U) +/*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag + * 0b0..No effect + * 0b0..SPC is in Active mode; the ACTIVE_CFG register has control + * 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register + * 0b1..Clear the flag + */ +#define SPC_SC_SPC_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK) + +#define SPC_SC_HP_ACTIVE_MASK (0x8U) +#define SPC_SC_HP_ACTIVE_SHIFT (3U) +/*! HP_ACTIVE - HP_CFG Select Status Flag + * 0b0..ACTIVE_CFG selected + * 0b1..HP_CFG selected + */ +#define SPC_SC_HP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_HP_ACTIVE_SHIFT)) & SPC_SC_HP_ACTIVE_MASK) + +#define SPC_SC_SPC_LP_MODE_MASK (0xF0U) +#define SPC_SC_SPC_LP_MODE_SHIFT (4U) +/*! SPC_LP_MODE - Power Domain Low-Power Mode Request + * 0b0000.. + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_SC_SPC_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK) + +#define SPC_SC_ISO_CLR_MASK (0x10000U) +#define SPC_SC_ISO_CLR_SHIFT (16U) +/*! ISO_CLR - Isolation Clear Flags */ +#define SPC_SC_ISO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK) +/*! @} */ + +/*! @name CNTRL - SPC Regulator Control */ +/*! @{ */ + +#define SPC_CNTRL_CORELDO_EN_MASK (0x1U) +#define SPC_CNTRL_CORELDO_EN_SHIFT (0U) +/*! CORELDO_EN - LDO_CORE Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_CORELDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_CORELDO_EN_SHIFT)) & SPC_CNTRL_CORELDO_EN_MASK) +/*! @} */ + +/*! @name LPREQ_CFG - Low-Power Request Configuration */ +/*! @{ */ + +#define SPC_LPREQ_CFG_LPREQOE_MASK (0x1U) +#define SPC_LPREQ_CFG_LPREQOE_SHIFT (0U) +/*! LPREQOE - Low-Power Request Output Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LPREQ_CFG_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK) + +#define SPC_LPREQ_CFG_LPREQPOL_MASK (0x2U) +#define SPC_LPREQ_CFG_LPREQPOL_SHIFT (1U) +/*! LPREQPOL - Low-Power Request Output Pin Polarity Control + * 0b0..High + * 0b1..Low + */ +#define SPC_LPREQ_CFG_LPREQPOL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK) + +#define SPC_LPREQ_CFG_LPREQOV_MASK (0xCU) +#define SPC_LPREQ_CFG_LPREQOV_SHIFT (2U) +/*! LPREQOV - Low-Power Request Output Override + * 0b00..Not forced + * 0b01.. + * 0b10..Forced low (ignore LPREQPOL settings) + * 0b11..Forced high (ignore LPREQPOL settings) + */ +#define SPC_LPREQ_CFG_LPREQOV(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK) +/*! @} */ + +/*! @name PD_STATUS - SPC Power Domain Mode Status */ +/*! @{ */ + +#define SPC_PD_STATUS_PD_LP_REQ_MASK (0x10U) +#define SPC_PD_STATUS_PD_LP_REQ_SHIFT (4U) +/*! PD_LP_REQ - Power Domain Low Power Request Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PD_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK) + +#define SPC_PD_STATUS_LP_MODE_MASK (0xF00U) +#define SPC_PD_STATUS_LP_MODE_SHIFT (8U) +/*! LP_MODE - Power Domain Low Power Mode Request + * 0b0000.. + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_PD_STATUS_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK) +/*! @} */ + +/*! @name SRAMCTL - SRAM Control */ +/*! @{ */ + +#define SPC_SRAMCTL_VSM_MASK (0x3U) +#define SPC_SRAMCTL_VSM_SHIFT (0U) +/*! VSM - Voltage Select Margin + * 0b00.. + * 0b01..1.0 V + * 0b10..1.1 V + * 0b11.. + */ +#define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK) + +#define SPC_SRAMCTL_REQ_MASK (0x40000000U) +#define SPC_SRAMCTL_REQ_SHIFT (30U) +/*! REQ - SRAM Voltage Update Request + * 0b0..Do not request + * 0b1..Request + */ +#define SPC_SRAMCTL_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK) + +#define SPC_SRAMCTL_ACK_MASK (0x80000000U) +#define SPC_SRAMCTL_ACK_SHIFT (31U) +/*! ACK - SRAM Voltage Update Request Acknowledge + * 0b0..Not acknowledged + * 0b1..Acknowledged + */ +#define SPC_SRAMCTL_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK) +/*! @} */ + +/*! @name SRAMRETLDO_REFTRIM - SRAM Retention Reference Trim */ +/*! @{ */ + +#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK (0x1FU) +#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT (0U) +/*! REFTRIM - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV. */ +#define SPC_SRAMRETLDO_REFTRIM_REFTRIM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT)) & SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) +/*! @} */ + +/*! @name SRAMRETLDO_CNTRL - SRAM Retention LDO Control */ +/*! @{ */ + +#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK (0x1U) +#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT (0U) +/*! SRAMLDO_ON - SRAM LDO Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK) + +#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK (0xF00U) +#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT (8U) +/*! SRAM_RET_EN - SRAM Retention */ +#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK) +/*! @} */ + +/*! @name HP_CNFG_CTRL - High Power Config Control */ +/*! @{ */ + +#define SPC_HP_CNFG_CTRL_HP_REQ_EN_MASK (0x1U) +#define SPC_HP_CNFG_CTRL_HP_REQ_EN_SHIFT (0U) +/*! HP_REQ_EN - High Power Request Enable + * 0b0..High Power request Disable + * 0b1..High power reqeust Enable + */ +#define SPC_HP_CNFG_CTRL_HP_REQ_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CNFG_CTRL_HP_REQ_EN_SHIFT)) & SPC_HP_CNFG_CTRL_HP_REQ_EN_MASK) + +#define SPC_HP_CNFG_CTRL_OVERRIDE_EN_MASK (0x2U) +#define SPC_HP_CNFG_CTRL_OVERRIDE_EN_SHIFT (1U) +/*! OVERRIDE_EN - Override Enable + * 0b0..Override Disabled + * 0b1..Override Enabled + */ +#define SPC_HP_CNFG_CTRL_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CNFG_CTRL_OVERRIDE_EN_SHIFT)) & SPC_HP_CNFG_CTRL_OVERRIDE_EN_MASK) + +#define SPC_HP_CNFG_CTRL_OVERRIDE_SEL_MASK (0x4U) +#define SPC_HP_CNFG_CTRL_OVERRIDE_SEL_SHIFT (2U) +/*! OVERRIDE_SEL - Override Select + * 0b0..Force the HP request to 0 + * 0b1..Force the HP request to 1 + */ +#define SPC_HP_CNFG_CTRL_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CNFG_CTRL_OVERRIDE_SEL_SHIFT)) & SPC_HP_CNFG_CTRL_OVERRIDE_SEL_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG - Active Power Mode Configuration */ +/*! @{ */ + +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00.. + * 0b01..Regulate to mid voltage (1 V) + * 0b10..Regulate to normal voltage (1.1 V) + * 0b11..Regulate to overdrive voltage (1.15 V) + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Low Voltage Glitch Detect enabled + * 0b1..Low Voltage Glitch Detect disabled + */ +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) + +#define SPC_ACTIVE_CFG_BGMODE_MASK (0x300000U) +#define SPC_ACTIVE_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_ACTIVE_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK) + +#define SPC_ACTIVE_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Active Config Chip Control */ +#define SPC_ACTIVE_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LP_CFG - Low-Power Mode Configuration */ +/*! @{ */ + +#define SPC_LP_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_LP_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00..Reserved + * 0b01..Mid voltage (1 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.15 V) + */ +#define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Enable + * 0b1..Disable + */ +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) + +#define SPC_LP_CFG_SRAMLDO_DPD_ON_MASK (0x80000U) +#define SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT (19U) +/*! SRAMLDO_DPD_ON - SRAM_LDO Deep Power Low Power IREF Enable + * 0b0..Low Power IREF is disabled for power saving in Deep Power Down mode + * 0b1..Low Power IREF is enabled + */ +#define SPC_LP_CFG_SRAMLDO_DPD_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT)) & SPC_LP_CFG_SRAMLDO_DPD_ON_MASK) + +#define SPC_LP_CFG_BGMODE_MASK (0x300000U) +#define SPC_LP_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_LP_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK) + +#define SPC_LP_CFG_LP_IREFEN_MASK (0x800000U) +#define SPC_LP_CFG_LP_IREFEN_SHIFT (23U) +/*! LP_IREFEN - Low-Power IREF Enable + * 0b0..Disable for power saving in Deep Power Down mode + * 0b1..Enable + */ +#define SPC_LP_CFG_LP_IREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK) + +#define SPC_LP_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_LP_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK) + +#define SPC_LP_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_LP_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK) + +#define SPC_LP_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_LP_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK) +/*! @} */ + +/*! @name LP_CFG1 - Low Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_LP_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_LP_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Low-Power Configuration Chip Control */ +#define SPC_LP_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name HP_CFG - High Power Mode Configuration */ +/*! @{ */ + +#define SPC_HP_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_HP_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_HP_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_HP_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_HP_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_HP_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00.. + * 0b01..Regulate to mid voltage (1 V) + * 0b10..Regulate to normal voltage (1.1 V) + * 0b11..Regulate to overdrive voltage (1.15 V) + */ +#define SPC_HP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_HP_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_HP_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) +#define SPC_HP_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) +/*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable + * 0b0..VDD Core Low Voltage Glitch Detect enabled + * 0b1..VDD Core Low Voltage Glitch Detect disabled + */ +#define SPC_HP_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_HP_CFG_GLITCH_DETECT_DISABLE_MASK) + +#define SPC_HP_CFG_BGMODE_MASK (0x300000U) +#define SPC_HP_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_HP_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_BGMODE_SHIFT)) & SPC_HP_CFG_BGMODE_MASK) + +#define SPC_HP_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_HP_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_HP_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_CORE_LVDE_SHIFT)) & SPC_HP_CFG_CORE_LVDE_MASK) + +#define SPC_HP_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_HP_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_HP_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_SYS_LVDE_SHIFT)) & SPC_HP_CFG_SYS_LVDE_MASK) + +#define SPC_HP_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_HP_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_HP_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_SYS_HVDE_SHIFT)) & SPC_HP_CFG_SYS_HVDE_MASK) +/*! @} */ + +/*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */ +/*! @{ */ + +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK (0xFFFFU) +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT (0U) +/*! LPWKUP_DELAY - Low-Power Wake-Up Delay */ +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK) +/*! @} */ + +/*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */ +/*! @{ */ + +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK (0xFFFFU) +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT (0U) +/*! ACTIVE_VDELAY - Active Voltage Delay */ +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK) +/*! @} */ + +/*! @name VD_STAT - Voltage Detect Status */ +/*! @{ */ + +#define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U) +#define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U) +/*! COREVDD_LVDF - Core Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Event detected + */ +#define SPC_VD_STAT_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U) +#define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U) +/*! SYSVDD_LVDF - System Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Event detected + */ +#define SPC_VD_STAT_SYSVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U) +#define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U) +/*! SYSVDD_HVDF - System HVD Flag + * 0b0..Event not detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Event detected + */ +#define SPC_VD_STAT_SYSVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK) +/*! @} */ + +/*! @name VD_CORE_CFG - Core Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - Core LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK) + +#define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - Core LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK) + +#define SPC_VD_CORE_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_CORE_CFG_LOCK_SHIFT (16U) +/*! LOCK - Core Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_CORE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK) +/*! @} */ + +/*! @name VD_SYS_CFG - System Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - System LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK) + +#define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - System LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK) + +#define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - System HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK) + +#define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - System HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) + +#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - System Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) + +#define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) +/*! LOCK - System Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_SYS_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK) +/*! @} */ + +/*! @name EVD_CFG - External Voltage Domain Configuration */ +/*! @{ */ + +#define SPC_EVD_CFG_EVDISO_MASK (0x7U) +#define SPC_EVD_CFG_EVDISO_SHIFT (0U) +/*! EVDISO - External Voltage Domain Isolation */ +#define SPC_EVD_CFG_EVDISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK) + +#define SPC_EVD_CFG_EVDLPISO_MASK (0x700U) +#define SPC_EVD_CFG_EVDLPISO_SHIFT (8U) +/*! EVDLPISO - External Voltage Domain Low-Power Isolation */ +#define SPC_EVD_CFG_EVDLPISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK) + +#define SPC_EVD_CFG_EVDSTAT_MASK (0x70000U) +#define SPC_EVD_CFG_EVDSTAT_SHIFT (16U) +/*! EVDSTAT - External Voltage Domain Status */ +#define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK) +/*! @} */ + +/*! @name GLITCH_DETECT_SC - Glitch Detect Status Control */ +/*! @{ */ + +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U) +/*! CNT_SELECT - Counter Select + * 0b00..0 + * 0b01..1 + * 0b10..2 + * 0b11..3 + */ +#define SPC_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK) + +#define SPC_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU) +#define SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U) +/*! TIMEOUT - Timeout */ +#define SPC_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_GLITCH_DETECT_SC_TIMEOUT_MASK) + +#define SPC_GLITCH_DETECT_SC_RE_MASK (0x40U) +#define SPC_GLITCH_DETECT_SC_RE_SHIFT (6U) +/*! RE - Glitch Detect Reset Enable + * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset + * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset + */ +#define SPC_GLITCH_DETECT_SC_RE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_GLITCH_DETECT_SC_RE_MASK) + +#define SPC_GLITCH_DETECT_SC_IE_MASK (0x80U) +#define SPC_GLITCH_DETECT_SC_IE_SHIFT (7U) +/*! IE - Glitch Detect Interrupt Enable + * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling) + * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt + */ +#define SPC_GLITCH_DETECT_SC_IE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_GLITCH_DETECT_SC_IE_MASK) + +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U) +/*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */ +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) + +#define SPC_GLITCH_DETECT_SC_LOCK_MASK (0x10000U) +#define SPC_GLITCH_DETECT_SC_LOCK_SHIFT (16U) +/*! LOCK - Glitch Detect Reset Enable Lock Bit + * 0b0..Writes to RE are allowed. + * 0b1..Writes to RE are ignored. + */ +#define SPC_GLITCH_DETECT_SC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_GLITCH_DETECT_SC_LOCK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPC_Register_Masks */ + + +/*! + * @} + */ /* end of group SPC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SPC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SYSCON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SYSCON.h new file mode 100644 index 000000000..a8fb762b7 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_SYSCON.h @@ -0,0 +1,1337 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for SYSCON +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_SYSCON.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for SYSCON + * + * CMSIS Peripheral Access Layer for SYSCON + */ + +#if !defined(PERI_SYSCON_H_) +#define PERI_SYSCON_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[512]; + __IO uint32_t REMAP; /**< AHB Matrix Remap Control, offset: 0x200 */ + uint8_t RESERVED_1[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix Priority Control, offset: 0x210 */ + uint8_t RESERVED_2[40]; + __IO uint32_t CPU0NSTCKCAL; /**< Non-Secure CPU0 System Tick Calibration, offset: 0x23C */ + uint8_t RESERVED_3[8]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x248 */ + __IO uint32_t PROTLVL; /**< Protect Level Control, offset: 0x24C */ + uint8_t RESERVED_4[296]; + __IO uint32_t SLOWCLKDIV; /**< SLOW_CLK Clock Divider, offset: 0x378 */ + __IO uint32_t BUSCLKDIV; /**< BUS_CLK Clock Divider, offset: 0x37C */ + __IO uint32_t AHBCLKDIV; /**< System Clock Divider, offset: 0x380 */ + uint8_t RESERVED_5[4]; + __IO uint32_t FROHFDIV; /**< FRO_HF_DIV Clock Divider, offset: 0x388 */ + __IO uint32_t FROLFDIV; /**< FRO_LF_DIV Clock Divider, offset: 0x38C */ + uint8_t RESERVED_6[108]; + __IO uint32_t CLKUNLOCK; /**< Clock Configuration Unlock, offset: 0x3FC */ + __IO uint32_t NVM_CTRL; /**< NVM Control, offset: 0x400 */ + uint8_t RESERVED_7[16]; + __IO uint32_t SMARTDMAINT; /**< SmartDMA Interrupt Hijack, offset: 0x414 */ + uint8_t RESERVED_8[1012]; + __I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_9[20]; + __IO uint32_t LPCAC_CTRL; /**< LPCAC Control, offset: 0x824 */ + uint8_t RESERVED_10[272]; + __IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0x938 */ + __IO uint32_t PWM1SUBCTL; /**< PWM1 Submodule Control, offset: 0x93C */ + __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0x940 */ + __IO uint32_t RAM_CTRL; /**< RAM Control, offset: 0x944 */ + uint8_t RESERVED_11[536]; + __IO uint32_t GRAY_CODE_LSB; /**< Gray to Binary Converter Gray Code [31:0], offset: 0xB60 */ + __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray Code [41:32], offset: 0xB64 */ + __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */ + __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */ + uint8_t RESERVED_12[684]; + __IO uint32_t MSFCFG; /**< MSF Configuration, offset: 0xE1C */ + uint8_t RESERVED_13[28]; + __I uint32_t ROP_STATE; /**< ROP State Register, offset: 0xE3C */ + uint8_t RESERVED_14[24]; + __IO uint32_t SRAM_XEN; /**< RAM XEN Control, offset: 0xE58 */ + __IO uint32_t SRAM_XEN_DP; /**< RAM XEN Control (Duplicate), offset: 0xE5C */ + uint8_t RESERVED_15[32]; + __I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0xE80 */ + __I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0xE84 */ + uint8_t RESERVED_16[280]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */ + uint8_t RESERVED_17[8]; + __IO uint32_t SWD_ACCESS_CPU0; /**< CPU0 Software Debug Access, offset: 0xFB4 */ + uint8_t RESERVED_18[8]; + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */ + uint8_t RESERVED_19[44]; + __I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */ + __I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name REMAP - AHB Matrix Remap Control */ +/*! @{ */ + +#define SYSCON_REMAP_CPU0_SBUS_MASK (0xCU) +#define SYSCON_REMAP_CPU0_SBUS_SHIFT (2U) +/*! CPU0_SBUS - RAMX0 address remap for CPU System bus + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is + * 0x20000000 + (system ram size - RAMX size)*1024. + */ +#define SYSCON_REMAP_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_CPU0_SBUS_SHIFT)) & SYSCON_REMAP_CPU0_SBUS_MASK) + +#define SYSCON_REMAP_SMARTDMA_I_MASK (0x30U) +#define SYSCON_REMAP_SMARTDMA_I_SHIFT (4U) +/*! SmartDMA_I - RAMX0 address remap for SmartDMA I-BUS + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_SMARTDMA_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_SMARTDMA_I_SHIFT)) & SYSCON_REMAP_SMARTDMA_I_MASK) + +#define SYSCON_REMAP_SMARTDMA_D_MASK (0xC0U) +#define SYSCON_REMAP_SMARTDMA_D_SHIFT (6U) +/*! SmartDMA_D - RAMX0 address remap for SmartDMA D-BUS + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_SMARTDMA_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_SMARTDMA_D_SHIFT)) & SYSCON_REMAP_SMARTDMA_D_MASK) + +#define SYSCON_REMAP_DMA0_MASK (0x300U) +#define SYSCON_REMAP_DMA0_SHIFT (8U) +/*! DMA0 - RAMX0 address remap for DMA0 + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_DMA0_SHIFT)) & SYSCON_REMAP_DMA0_MASK) + +#define SYSCON_REMAP_LOCK_MASK (0x80000000U) +#define SYSCON_REMAP_LOCK_SHIFT (31U) +/*! LOCK - This 1-bit field provides a mechanism to limit writes to this register to protect its + * contents. Once set, this bit remains asserted until a system reset. + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered until a system reset. + */ +#define SYSCON_REMAP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_LOCK_SHIFT)) & SYSCON_REMAP_LOCK_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix Priority Control */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT (0U) +/*! CPU0_CBUS - CPU0 C-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT (2U) +/*! CPU0_SBUS - CPU0 S-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_MASK (0x30U) +#define SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_SHIFT (4U) +/*! CPU1_CBUS_SmartDMA_I - SmartDMA-I bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_SHIFT)) & SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_MASK) + +#define SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_SHIFT (6U) +/*! CPU1_SBUS_SmartDMA_D - SmartDMA-D bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_SHIFT)) & SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_MASK) + +#define SYSCON_AHBMATPRIO_DMA0_MASK (0x300U) +#define SYSCON_AHBMATPRIO_DMA0_SHIFT (8U) +/*! DMA0 - DMA0 controller bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0xFFU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + * 0b0..Disable. + * 0b1..Enable. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PROTLVL - Protect Level Control */ +/*! @{ */ + +#define SYSCON_PROTLVL_PRIV_MASK (0x1U) +#define SYSCON_PROTLVL_PRIV_SHIFT (0U) +/*! PRIV - Control privileged access of EIM, ERM, Flexcan, MBC, SCG. + * 0b0..privileged access is disabled. the peripherals could be access in user mode. + * 0b1..privileged access is enabled. the peripherals could be access in privilege mode. + */ +#define SYSCON_PROTLVL_PRIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PROTLVL_PRIV_SHIFT)) & SYSCON_PROTLVL_PRIV_MASK) + +#define SYSCON_PROTLVL_LOCKNSMPU_MASK (0x10000U) +#define SYSCON_PROTLVL_LOCKNSMPU_SHIFT (16U) +/*! LOCKNSMPU - Control write access to Nonsecure MPU memory regions. + * 0b0..Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed. + * 0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and + * MPU_RLAR_A_NSn. All writes to the registers are ignored. + */ +#define SYSCON_PROTLVL_LOCKNSMPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PROTLVL_LOCKNSMPU_SHIFT)) & SYSCON_PROTLVL_LOCKNSMPU_MASK) + +#define SYSCON_PROTLVL_LOCK_MASK (0x80000000U) +#define SYSCON_PROTLVL_LOCK_SHIFT (31U) +/*! LOCK - This 1-bit field provides a mechanism to limit writes to this register to protect its + * contents. Once set, this bit remains asserted until a system reset. + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered until a system reset. + */ +#define SYSCON_PROTLVL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PROTLVL_LOCK_SHIFT)) & SYSCON_PROTLVL_LOCK_MASK) +/*! @} */ + +/*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */ +/*! @{ */ + +#define SYSCON_SLOWCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SLOWCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SLOWCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_DIV_SHIFT)) & SYSCON_SLOWCLKDIV_DIV_MASK) + +#define SYSCON_SLOWCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SLOWCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_SLOWCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK) + +#define SYSCON_SLOWCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SLOWCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define SYSCON_SLOWCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK) + +#define SYSCON_SLOWCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_SLOWCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name BUSCLKDIV - BUS_CLK Clock Divider */ +/*! @{ */ + +#define SYSCON_BUSCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_BUSCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_BUSCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_DIV_SHIFT)) & SYSCON_BUSCLKDIV_DIV_MASK) + +#define SYSCON_BUSCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_BUSCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_BUSCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_RESET_SHIFT)) & SYSCON_BUSCLKDIV_RESET_MASK) + +#define SYSCON_BUSCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_BUSCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define SYSCON_BUSCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_HALT_SHIFT)) & SYSCON_BUSCLKDIV_HALT_MASK) + +#define SYSCON_BUSCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_BUSCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_BUSCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_UNSTAB_SHIFT)) & SYSCON_BUSCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name AHBCLKDIV - System Clock Divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF_DIV Clock Divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FROHFDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_FROHFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FROLFDIV - FRO_LF_DIV Clock Divider */ +/*! @{ */ + +#define SYSCON_FROLFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROLFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FROLFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_DIV_SHIFT)) & SYSCON_FROLFDIV_DIV_MASK) + +#define SYSCON_FROLFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROLFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_FROLFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_RESET_SHIFT)) & SYSCON_FROLFDIV_RESET_MASK) + +#define SYSCON_FROLFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROLFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define SYSCON_FROLFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_HALT_SHIFT)) & SYSCON_FROLFDIV_HALT_MASK) + +#define SYSCON_FROLFDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FROLFDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_FROLFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_UNSTAB_SHIFT)) & SYSCON_FROLFDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKUNLOCK - Clock Configuration Unlock */ +/*! @{ */ + +#define SYSCON_CLKUNLOCK_UNLOCK_MASK (0x1U) +#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U) +/*! UNLOCK - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, + * AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx) + * 0b0..Updates are allowed to all clock configuration registers + * 0b1..Freezes all clock configuration registers update. + */ +#define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK) +/*! @} */ + +/*! @name NVM_CTRL - NVM Control */ +/*! @{ */ + +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK (0x1U) +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT (0U) +/*! DIS_FLASH_SPEC - Flash speculation control + * 0b0..Enables flash speculation + * 0b1..Disables flash speculation + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK) + +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK (0x2U) +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT (1U) +/*! DIS_DATA_SPEC - Flash data speculation control + * 0b0..Enables data speculation + * 0b1..Disables data speculation + */ +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK) + +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK (0x400U) +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT (10U) +/*! FLASH_STALL_EN - FLASH stall on busy control + * 0b0..No stall on FLASH busy + * 0b1..Stall on FLASH busy + */ +#define SYSCON_NVM_CTRL_FLASH_STALL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK (0x10000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U) +/*! DIS_MBECC_ERR_INST + * 0b0..Enables bus error on multi-bit ECC error for instruction + * 0b1..Disables bus error on multi-bit ECC error for instruction + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK (0x20000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U) +/*! DIS_MBECC_ERR_DATA + * 0b0..Enables bus error on multi-bit ECC error for data + * 0b1..Disables bus error on multi-bit ECC error for data + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK) +/*! @} */ + +/*! @name SMARTDMAINT - SmartDMA Interrupt Hijack */ +/*! @{ */ + +#define SYSCON_SMARTDMAINT_INT0_MASK (0x1U) +#define SYSCON_SMARTDMAINT_INT0_SHIFT (0U) +/*! INT0 - SmartDMA hijack NVIC IRQ2 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT0_SHIFT)) & SYSCON_SMARTDMAINT_INT0_MASK) + +#define SYSCON_SMARTDMAINT_INT2_MASK (0x4U) +#define SYSCON_SMARTDMAINT_INT2_SHIFT (2U) +/*! INT2 - SmartDMA hijack NVIC IRQ26 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT2_SHIFT)) & SYSCON_SMARTDMAINT_INT2_MASK) + +#define SYSCON_SMARTDMAINT_INT3_MASK (0x8U) +#define SYSCON_SMARTDMAINT_INT3_SHIFT (3U) +/*! INT3 - SmartDMA hijack NVIC IRQ27 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT3_SHIFT)) & SYSCON_SMARTDMAINT_INT3_MASK) + +#define SYSCON_SMARTDMAINT_INT4_MASK (0x10U) +#define SYSCON_SMARTDMAINT_INT4_SHIFT (4U) +/*! INT4 - SmartDMA hijack NVIC IRQ28 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT4_SHIFT)) & SYSCON_SMARTDMAINT_INT4_MASK) + +#define SYSCON_SMARTDMAINT_INT5_MASK (0x20U) +#define SYSCON_SMARTDMAINT_INT5_SHIFT (5U) +/*! INT5 - SmartDMA hijack NVIC IRQ29 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT5_SHIFT)) & SYSCON_SMARTDMAINT_INT5_MASK) + +#define SYSCON_SMARTDMAINT_INT6_MASK (0x40U) +#define SYSCON_SMARTDMAINT_INT6_SHIFT (6U) +/*! INT6 - SmartDMA hijack NVIC IRQ31 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT6_SHIFT)) & SYSCON_SMARTDMAINT_INT6_MASK) + +#define SYSCON_SMARTDMAINT_INT7_MASK (0x80U) +#define SYSCON_SMARTDMAINT_INT7_SHIFT (7U) +/*! INT7 - SmartDMA hijack NVIC IRQ32 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT7_SHIFT)) & SYSCON_SMARTDMAINT_INT7_MASK) + +#define SYSCON_SMARTDMAINT_INT8_MASK (0x100U) +#define SYSCON_SMARTDMAINT_INT8_SHIFT (8U) +/*! INT8 - SmartDMA hijack NVIC IRQ33 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT8_SHIFT)) & SYSCON_SMARTDMAINT_INT8_MASK) + +#define SYSCON_SMARTDMAINT_INT9_MASK (0x200U) +#define SYSCON_SMARTDMAINT_INT9_SHIFT (9U) +/*! INT9 - SmartDMA hijack NVIC IRQ34 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT9_SHIFT)) & SYSCON_SMARTDMAINT_INT9_MASK) + +#define SYSCON_SMARTDMAINT_INT11_MASK (0x800U) +#define SYSCON_SMARTDMAINT_INT11_SHIFT (11U) +/*! INT11 - SmartDMA hijack NVIC IRQ39 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT11(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT11_SHIFT)) & SYSCON_SMARTDMAINT_INT11_MASK) + +#define SYSCON_SMARTDMAINT_INT12_MASK (0x1000U) +#define SYSCON_SMARTDMAINT_INT12_SHIFT (12U) +/*! INT12 - SmartDMA hijack NVIC IRQ40 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT12(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT12_SHIFT)) & SYSCON_SMARTDMAINT_INT12_MASK) + +#define SYSCON_SMARTDMAINT_INT13_MASK (0x2000U) +#define SYSCON_SMARTDMAINT_INT13_SHIFT (13U) +/*! INT13 - SmartDMA hijack NVIC IRQ41 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT13(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT13_SHIFT)) & SYSCON_SMARTDMAINT_INT13_MASK) + +#define SYSCON_SMARTDMAINT_INT14_MASK (0x4000U) +#define SYSCON_SMARTDMAINT_INT14_SHIFT (14U) +/*! INT14 - SmartDMA hijack NVIC IRQ59 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT14(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT14_SHIFT)) & SYSCON_SMARTDMAINT_INT14_MASK) + +#define SYSCON_SMARTDMAINT_INT15_MASK (0x8000U) +#define SYSCON_SMARTDMAINT_INT15_SHIFT (15U) +/*! INT15 - SmartDMA hijack NVIC IRQ62 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT15(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT15_SHIFT)) & SYSCON_SMARTDMAINT_INT15_MASK) + +#define SYSCON_SMARTDMAINT_INT16_MASK (0x10000U) +#define SYSCON_SMARTDMAINT_INT16_SHIFT (16U) +/*! INT16 - SmartDMA hijack NVIC IRQ64 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT16(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT16_SHIFT)) & SYSCON_SMARTDMAINT_INT16_MASK) + +#define SYSCON_SMARTDMAINT_INT17_MASK (0x20000U) +#define SYSCON_SMARTDMAINT_INT17_SHIFT (17U) +/*! INT17 - SmartDMA hijack NVIC IRQ71 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT17(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT17_SHIFT)) & SYSCON_SMARTDMAINT_INT17_MASK) + +#define SYSCON_SMARTDMAINT_INT18_MASK (0x40000U) +#define SYSCON_SMARTDMAINT_INT18_SHIFT (18U) +/*! INT18 - SmartDMA hijack NVIC IRQ72 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT18(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT18_SHIFT)) & SYSCON_SMARTDMAINT_INT18_MASK) + +#define SYSCON_SMARTDMAINT_INT19_MASK (0x80000U) +#define SYSCON_SMARTDMAINT_INT19_SHIFT (19U) +/*! INT19 - SmartDMA hijack NVIC IRQ73 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT19(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT19_SHIFT)) & SYSCON_SMARTDMAINT_INT19_MASK) + +#define SYSCON_SMARTDMAINT_INT20_MASK (0x100000U) +#define SYSCON_SMARTDMAINT_INT20_SHIFT (20U) +/*! INT20 - SmartDMA hijack NVIC IRQ74 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT20(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT20_SHIFT)) & SYSCON_SMARTDMAINT_INT20_MASK) + +#define SYSCON_SMARTDMAINT_INT21_MASK (0x200000U) +#define SYSCON_SMARTDMAINT_INT21_SHIFT (21U) +/*! INT21 - SmartDMA hijack NVIC IRQ75 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT21(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT21_SHIFT)) & SYSCON_SMARTDMAINT_INT21_MASK) +/*! @} */ + +/*! @name CPUSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - CPU0 sleeping state + * 0b0..CPU is not sleeping + * 0b1..CPU is sleeping + */ +#define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - CPU0 lockup state + * 0b0..CPU is not in lockup + * 0b1..CPU is in lockup + */ +#define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK) +/*! @} */ + +/*! @name LPCAC_CTRL - LPCAC Control */ +/*! @{ */ + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U) +/*! DIS_LPCAC - Disables/enables the cache function. + * 0b0..Enabled + * 0b1..Disabled + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U) +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U) +/*! CLR_LPCAC - Clears the cache function. + * 0b0..Unclears the cache + * 0b1..Clears the cache + */ +#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U) +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U) +/*! FRC_NO_ALLOC - Forces no allocation. + * 0b0..Forces allocation + * 0b1..Forces no allocation + */ +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK) + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK (0x10U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT (4U) +/*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer. + * 0b0..Enables write through buffer + * 0b1..Disables write through buffer + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK (0x20U) +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT (5U) +/*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer. + * 0b0..Write buffer enabled when transaction is bufferable. + * 0b1..Write buffer enabled when transaction is cacheable and bufferable + */ +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK (0x80U) +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT (7U) +/*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SYSCON_LPCAC_CTRL_LPCAC_XOM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK) + +#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK (0x100U) +#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT (8U) +/*! LPCAC_MEM_REQ - Request LPCAC memories. + * 0b0..Configure shared memories RAMX1 as general memories. + * 0b1..Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset. + */ +#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK) +/*! @} */ + +/*! @name PWM0SUBCTL - PWM0 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM0 SUB Clock0 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM0 SUB Clock1 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM0 SUB Clock2 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM0 SUB Clock3 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK) +/*! @} */ + +/*! @name PWM1SUBCTL - PWM1 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM1 SUB Clock0 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM1SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM1 SUB Clock1 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM1SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM1 SUB Clock2 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM1SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM1 SUB Clock3 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM1SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK) +/*! @} */ + +/*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */ +/*! @{ */ + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U) +/*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U) +/*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U) +/*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK) +/*! @} */ + +/*! @name RAM_CTRL - RAM Control */ +/*! @{ */ + +#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK (0x1U) +#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT (0U) +/*! RAMA_ECC_ENABLE - RAMA ECC enable + * 0b0..ECC is disabled + * 0b1..ECC is enabled + */ +#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK) + +#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK (0x10000U) +#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT (16U) +/*! RAMA_CG_OVERRIDE - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0. + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + * 0b1..Auto clock gating feature is disabled + */ +#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK) + +#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK (0x20000U) +#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT (17U) +/*! RAMX_CG_OVERRIDE - RAMX bank clock gating control + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + * 0b1..Auto clock gating feature is disabled + */ +#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK) + +#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_MASK (0x40000U) +#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_SHIFT (18U) +/*! RAMB_CG_OVERRIDE - RAMB bank clock gating control + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + * 0b1..Auto clock gating feature is disabled + */ +#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_MASK) + +#define SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_MASK (0x80000U) +#define SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_SHIFT (19U) +/*! RAMC_CG_OVERRIDE - RAMC bank clock gating control + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + * 0b1..Auto clock gating feature is disabled + */ +#define SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_MASK) +/*! @} */ + +/*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray Code [31:0] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT (0U) +/*! code_gray_31_0 - Gray code [31:0] */ +#define SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK) +/*! @} */ + +/*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray Code [41:32] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_MASK (0x3FFU) +#define SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_SHIFT (0U) +/*! code_gray_41_32 - Gray code [41:32] */ +#define SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_MASK) +/*! @} */ + +/*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT (0U) +/*! code_bin_31_0 - Binary code [31:0] */ +#define SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_MASK) +/*! @} */ + +/*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_MASK (0x3FFU) +#define SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_SHIFT (0U) +/*! code_bin_41_32 - Binary code [41:32] */ +#define SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_MASK) +/*! @} */ + +/*! @name MSFCFG - MSF Configuration */ +/*! @{ */ + +#define SYSCON_MSFCFG_IFR_ERASE_DIS0_MASK (0x1U) +#define SYSCON_MSFCFG_IFR_ERASE_DIS0_SHIFT (0U) +/*! IFR_ERASE_DIS0 - user IFR sector 0 erase control + * 0b0..Enable IFR sector erase. + * 0b1..Disable IFR sector erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_IFR_ERASE_DIS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS0_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS0_MASK) + +#define SYSCON_MSFCFG_IFR_ERASE_DIS1_MASK (0x2U) +#define SYSCON_MSFCFG_IFR_ERASE_DIS1_SHIFT (1U) +/*! IFR_ERASE_DIS1 - user IFR sector 1 erase control + * 0b0..Enable IFR sector erase. + * 0b1..Disable IFR sector erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_IFR_ERASE_DIS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS1_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS1_MASK) + +#define SYSCON_MSFCFG_IFR_ERASE_DIS2_MASK (0x4U) +#define SYSCON_MSFCFG_IFR_ERASE_DIS2_SHIFT (2U) +/*! IFR_ERASE_DIS2 - user IFR sector 2 erase control + * 0b0..Enable IFR sector erase. + * 0b1..Disable IFR sector erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_IFR_ERASE_DIS2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS2_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS2_MASK) + +#define SYSCON_MSFCFG_IFR_ERASE_DIS3_MASK (0x8U) +#define SYSCON_MSFCFG_IFR_ERASE_DIS3_SHIFT (3U) +/*! IFR_ERASE_DIS3 - user IFR sector 3 erase control + * 0b0..Enable IFR sector erase. + * 0b1..Disable IFR sector erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_IFR_ERASE_DIS3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS3_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS3_MASK) + +#define SYSCON_MSFCFG_MASS_ERASE_DIS_MASK (0x100U) +#define SYSCON_MSFCFG_MASS_ERASE_DIS_SHIFT (8U) +/*! MASS_ERASE_DIS - Mass erase control + * 0b0..Enables mass erase + * 0b1..Disables mass erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_MASS_ERASE_DIS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_MASS_ERASE_DIS_SHIFT)) & SYSCON_MSFCFG_MASS_ERASE_DIS_MASK) +/*! @} */ + +/*! @name ROP_STATE - ROP State Register */ +/*! @{ */ + +#define SYSCON_ROP_STATE_ROP_STATE_MASK (0xFFFFFFFFU) +#define SYSCON_ROP_STATE_ROP_STATE_SHIFT (0U) +/*! ROP_STATE - ROP state */ +#define SYSCON_ROP_STATE_ROP_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROP_STATE_ROP_STATE_SHIFT)) & SYSCON_ROP_STATE_ROP_STATE_MASK) +/*! @} */ + +/*! @name SRAM_XEN - RAM XEN Control */ +/*! @{ */ + +#define SYSCON_SRAM_XEN_RAMX0_XEN_MASK (0x1U) +#define SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT (0U) +/*! RAMX0_XEN - RAMX0 Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMX0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX0_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMX1_XEN_MASK (0x2U) +#define SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT (1U) +/*! RAMX1_XEN - RAMX1 Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMX1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX1_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMA0_XEN_MASK (0x4U) +#define SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT (2U) +/*! RAMA0_XEN - RAMA0 Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMA0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA0_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMA1_XEN_MASK (0x8U) +#define SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT (3U) +/*! RAMA1_XEN - RAMAx (excepts RAMA0) Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMA1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA1_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMB_XEN_MASK (0x10U) +#define SYSCON_SRAM_XEN_RAMB_XEN_SHIFT (4U) +/*! RAMB_XEN - RAMBx Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMB_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMB_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMB_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMC_XEN_MASK (0x20U) +#define SYSCON_SRAM_XEN_RAMC_XEN_SHIFT (5U) +/*! RAMC_XEN - RAMCx Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMC_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMC_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMC_XEN_MASK) + +#define SYSCON_SRAM_XEN_LOCK_MASK (0x80000000U) +#define SYSCON_SRAM_XEN_LOCK_SHIFT (31U) +/*! LOCK - This 1-bit field provides a mechanism to limit writes to this register (and SRAM_XEN_DP) + * to protect its contents. Once set, this bit remains asserted until a system reset. + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define SYSCON_SRAM_XEN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_LOCK_SHIFT)) & SYSCON_SRAM_XEN_LOCK_MASK) +/*! @} */ + +/*! @name SRAM_XEN_DP - RAM XEN Control (Duplicate) */ +/*! @{ */ + +#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK (0x1U) +#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT (0U) +/*! RAMX0_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMX0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK (0x2U) +#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT (1U) +/*! RAMX1_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMX1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK (0x4U) +#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT (2U) +/*! RAMA0_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMA0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK (0x8U) +#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT (3U) +/*! RAMA1_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMA1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMB_XEN_MASK (0x10U) +#define SYSCON_SRAM_XEN_DP_RAMB_XEN_SHIFT (4U) +/*! RAMB_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMB_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMB_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMB_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMC_XEN_MASK (0x20U) +#define SYSCON_SRAM_XEN_DP_RAMC_XEN_SHIFT (5U) +/*! RAMC_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMC_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMC_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMC_XEN_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE - Life Cycle State Register */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U) +/*! OTP_LC_STATE - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U) +/*! OTP_LC_STATE_DP - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control Write Access to Security */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Controls write access to the security registers + * 0b0000..Any other value than b1010: disables write access to all registers + * 0b1010..Enables write access to all registers + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex Debug Features Control */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) +/*! @} */ + +/*! @name SWD_ACCESS_CPU0 - CPU0 Software Debug Access */ +/*! @{ */ + +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - CPU0 SWD-AP: 0x12345678 + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5. + * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. + */ +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to the application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name JTAG_ID - JTAG Chip ID */ +/*! @{ */ + +#define SYSCON_JTAG_ID_JTAG_ID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAG_ID_JTAG_ID_SHIFT (0U) +/*! JTAG_ID - Indicates the device ID */ +#define SYSCON_JTAG_ID_JTAG_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK) +/*! @} */ + +/*! @name DEVICE_TYPE - Device Type */ +/*! @{ */ + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK (0xFFFFU) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT (0U) +/*! DEVICE_TYPE_NUM - Indicates the device part number */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK) + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK (0x10000U) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT (16U) +/*! DEVICE_TYPE_SEC - Indicates the device type + * 0b0..Non Secure + * 0b1..Secure + */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK) + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK (0xF00000U) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT (20U) +/*! DEVICE_TYPE_PKG - Indicates the device's package type + * 0b0000..HLQFP + * 0b0001..HTQFP + * 0b0010..BGA + * 0b0011..HDQFP + * 0b0100..QFN + * 0b0101..CSP + * 0b0110..LQFP + */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK) + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK (0xFF000000U) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT (24U) +/*! DEVICE_TYPE_PIN - Indicates the device's pin number */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_RAM_SIZE_MASK (0xFU) +#define SYSCON_DEVICE_ID0_RAM_SIZE_SHIFT (0U) +/*! RAM_SIZE - Indicates the device's ram size + * 0b0000..8KB. + * 0b0001..16KB. + * 0b0010..32KB. + * 0b0011..64KB. + * 0b0100..96KB. + * 0b0101..128KB. + * 0b0110..160KB. + * 0b0111..192KB. + * 0b1000..256KB. + * 0b1001..288KB. + * 0b1010..352KB. + * 0b1011..512KB. + */ +#define SYSCON_DEVICE_ID0_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_RAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_RAM_SIZE_MASK) + +#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0xF0U) +#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (4U) +/*! FLASH_SIZE - Indicates the device's flash size + * 0b0000..32KB. + * 0b0001..64KB. + * 0b0010..128KB. + * 0b0011..256KB. + * 0b0100..512KB. + * 0b0101..768KB. + * 0b0110..1MB. + * 0b0111..1.5MB. + * 0b1000..2MB. + */ +#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK) + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - Indicates the device's ROM revision */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) + +#define SYSCON_DEVICE_ID0_SECURITY_MASK (0xF000000U) +#define SYSCON_DEVICE_ID0_SECURITY_SHIFT (24U) +/*! SECURITY + * 0b0101..Secure version. (All values other than 1010b represent the secure version.) + * 0b1010..Non secure version. + */ +#define SYSCON_DEVICE_ID0_SECURITY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SECURITY_SHIFT)) & SYSCON_DEVICE_ID0_SECURITY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SYSCON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_TRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_TRDC.h new file mode 100644 index 000000000..eabacda7f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_TRDC.h @@ -0,0 +1,904 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for TRDC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_TRDC.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for TRDC + * + * CMSIS Peripheral Access Layer for TRDC + */ + +#if !defined(PERI_TRDC_H_) +#define PERI_TRDC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- TRDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer + * @{ + */ + +/** TRDC - Size of Registers Arrays */ +#define MBC_MEM_GLBCFG_COUNT 4u +#define MBC_MEMN_GLBAC_COUNT 8u +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_COUNT 4u +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_COUNT 2u +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_COUNT 1u +#define TRDC_MBC_INDEX_COUNT 1u + +/** TRDC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x1AC */ + __IO uint32_t MBC_MEM_GLBCFG[MBC_MEM_GLBCFG_COUNT]; /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1AC, index2*0x4 */ + uint8_t RESERVED_0[16]; + __IO uint32_t MBC_MEMN_GLBAC[MBC_MEMN_GLBAC_COUNT]; /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1AC, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_COUNT]; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1AC, index2*0x4 */ + uint8_t RESERVED_1[304]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_COUNT]; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1AC, index2*0x4 */ + uint8_t RESERVED_2[32]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_COUNT]; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1AC, index2*0x4 */ + } MBC_INDEX[TRDC_MBC_INDEX_COUNT]; +} TRDC_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Register_Masks TRDC Register Masks + * @{ + */ + +/*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK (0xC0000000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U) +/*! CLRE - Clear Error */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (4U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (2U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + + +/*! + * @} + */ /* end of group TRDC_Register_Masks */ + + +/*! + * @} + */ /* end of group TRDC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_TRDC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_UTICK.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_UTICK.h new file mode 100644 index 000000000..15524a5b4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_UTICK.h @@ -0,0 +1,310 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for UTICK +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_UTICK.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for UTICK + * + * CMSIS Peripheral Access Layer for UTICK + */ + +#if !defined(PERI_UTICK_H_) +#define PERI_UTICK_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Size of Registers Arrays */ +#define UTICK_CAP_COUNT 4u + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control, offset: 0x0 */ + __IO uint32_t STAT; /**< Status, offset: 0x4 */ + __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */ + __I uint32_t CAP[UTICK_CAP_COUNT]; /**< Capture, array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick Interval + * 0b0000000000000000000000000000000.. + * *..Clock cycles as defined in the description + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat Delay + * 0b0..One-time delay + * 0b1..Delay repeats continuously + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt Flag + * 0b0..Not pending + * 0b1..Pending + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Timer Active Flag + * 0b0..Inactive (stopped) + * 0b1..Active + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture Configuration */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture-Polarity 1 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture Clear */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear Capture 0 + * 0b0..Does nothing + * 0b1..Clears the CAP0 register value + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear Capture 1 + * 0b0..Does nothing + * 0b1..Clears the CAP1 register value + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear Capture 2 + * 0b0..Does nothing + * 0b1..Clears the CAP2 register value + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear Capture 3 + * 0b0..Does nothing + * 0b1..Clears the CAP3 register value + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Captured Value for the Related Capture Event */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Captured Value Valid Flag + * 0b0..Valid value not captured + * 0b1..Valid value captured + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_UTICK_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_VBAT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_VBAT.h new file mode 100644 index 000000000..3c910f08b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_VBAT.h @@ -0,0 +1,234 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for VBAT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_VBAT.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for VBAT + * + * CMSIS Peripheral Access Layer for VBAT + */ + +#if !defined(PERI_VBAT_H_) +#define PERI_VBAT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- VBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer + * @{ + */ + +/** VBAT - Size of Registers Arrays */ +#define VBAT_WAKEUP_COUNT 2u + +/** VBAT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[508]; + __IO uint32_t FROCTLA; /**< FRO16K Control A, offset: 0x200 */ + uint8_t RESERVED_1[20]; + __IO uint32_t FROLCKA; /**< FRO16K Lock A, offset: 0x218 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FROCLKE; /**< FRO16K Clock Enable, offset: 0x220 */ + uint8_t RESERVED_3[1244]; + struct { /* offset: 0x700, array step: 0x8 */ + __IO uint32_t WAKEUPA; /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } WAKEUP[VBAT_WAKEUP_COUNT]; + uint8_t RESERVED_4[232]; + __IO uint32_t WAKLCKA; /**< Wakeup Lock A, offset: 0x7F8 */ +} VBAT_Type; + +/* ---------------------------------------------------------------------------- + -- VBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Register_Masks VBAT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define VBAT_VERID_FEATURE_MASK (0xFFFFU) +#define VBAT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define VBAT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK) + +#define VBAT_VERID_MINOR_MASK (0xFF0000U) +#define VBAT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define VBAT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK) + +#define VBAT_VERID_MAJOR_MASK (0xFF000000U) +#define VBAT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define VBAT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name FROCTLA - FRO16K Control A */ +/*! @{ */ + +#define VBAT_FROCTLA_FRO_EN_MASK (0x1U) +#define VBAT_FROCTLA_FRO_EN_SHIFT (0U) +/*! FRO_EN - FRO16K Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_FROCTLA_FRO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK) +/*! @} */ + +/*! @name FROLCKA - FRO16K Lock A */ +/*! @{ */ + +#define VBAT_FROLCKA_LOCK_MASK (0x1U) +#define VBAT_FROLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_FROLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK) +/*! @} */ + +/*! @name FROCLKE - FRO16K Clock Enable */ +/*! @{ */ + +#define VBAT_FROCLKE_CLKE_MASK (0x3U) +#define VBAT_FROCLKE_CLKE_SHIFT (0U) +/*! CLKE - Clock Enable */ +#define VBAT_FROCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK) +/*! @} */ + +/*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */ +/*! @{ */ + +#define VBAT_WAKEUP_WAKEUPA_REG_MASK (0xFFFFFFFFU) +#define VBAT_WAKEUP_WAKEUPA_REG_SHIFT (0U) +/*! REG - Register */ +#define VBAT_WAKEUP_WAKEUPA_REG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK) +/*! @} */ + +/* The count of VBAT_WAKEUP_WAKEUPA */ +#define VBAT_WAKEUP_WAKEUPA_COUNT (2U) + +/*! @name WAKLCKA - Wakeup Lock A */ +/*! @{ */ + +#define VBAT_WAKLCKA_LOCK_MASK (0x1U) +#define VBAT_WAKLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_WAKLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VBAT_Register_Masks */ + + +/*! + * @} + */ /* end of group VBAT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_VBAT_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WAKETIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WAKETIMER.h new file mode 100644 index 000000000..eeb911a90 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WAKETIMER.h @@ -0,0 +1,189 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for WAKETIMER +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_WAKETIMER.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for WAKETIMER + * + * CMSIS Peripheral Access Layer for WAKETIMER + */ + +#if !defined(PERI_WAKETIMER_H_) +#define PERI_WAKETIMER_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- WAKETIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WAKETIMER_Peripheral_Access_Layer WAKETIMER Peripheral Access Layer + * @{ + */ + +/** WAKETIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t WAKE_TIMER_CTRL; /**< Wake Timer Control, offset: 0x0 */ + uint8_t RESERVED_0[8]; + __IO uint32_t WAKE_TIMER_CNT; /**< Wake Timer Counter, offset: 0xC */ +} WAKETIMER_Type; + +/* ---------------------------------------------------------------------------- + -- WAKETIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WAKETIMER_Register_Masks WAKETIMER Register Masks + * @{ + */ + +/*! @name WAKE_TIMER_CTRL - Wake Timer Control */ +/*! @{ */ + +#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) +#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) +/*! WAKE_FLAG - Wake Timer Status Flag + * 0b0..Wake timer has not timed out. + * 0b1..Wake timer has timed out. + */ +#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) + +#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) +#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) +/*! CLR_WAKE_TIMER - Clear Wake Timer + * 0b0..No effect. + * 0b1..Clears the wake timer counter and halts operation until a new count value is loaded. + */ +#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) + +#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) +#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) +/*! OSC_DIV_ENA - OSC Divide Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) + +#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) +#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) +/*! INTR_EN - Enable Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CNT - Wake Timer Counter */ +/*! @{ */ + +#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU) +#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U) +/*! WAKE_CNT - Wake Counter */ +#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WAKETIMER_Register_Masks */ + + +/*! + * @} + */ /* end of group WAKETIMER_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_WAKETIMER_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WUU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WUU.h new file mode 100644 index 000000000..2faeaa0ab --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WUU.h @@ -0,0 +1,1573 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for WUU +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_WUU.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for WUU + * + * CMSIS Peripheral Access Layer for WUU + */ + +#if !defined(PERI_WUU_H_) +#define PERI_WUU_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- WUU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer + * @{ + */ + +/** WUU - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t PE1; /**< Pin Enable 1, offset: 0x8 */ + __IO uint32_t PE2; /**< Pin Enable 2, offset: 0xC */ + uint8_t RESERVED_0[8]; + __IO uint32_t ME; /**< Module Interrupt Enable, offset: 0x18 */ + __IO uint32_t DE; /**< Module DMA/Trigger Enable, offset: 0x1C */ + __IO uint32_t PF; /**< Pin Flag, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FILT; /**< Pin Filter, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */ + __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */ + uint8_t RESERVED_3[8]; + __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */ + uint8_t RESERVED_4[4]; + __IO uint32_t PMC; /**< Pin Mode Configuration, offset: 0x50 */ + uint8_t RESERVED_5[4]; + __IO uint32_t FMC; /**< Pin Filter Mode Configuration, offset: 0x58 */ +} WUU_Type; + +/* ---------------------------------------------------------------------------- + -- WUU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Register_Masks WUU Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define WUU_VERID_FEATURE_MASK (0xFFFFU) +#define WUU_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for + * external pin/filter detection during all power modes enabled. + */ +#define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK) + +#define WUU_VERID_MINOR_MASK (0xFF0000U) +#define WUU_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define WUU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK) + +#define WUU_VERID_MAJOR_MASK (0xFF000000U) +#define WUU_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define WUU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define WUU_PARAM_FILTERS_MASK (0xFFU) +#define WUU_PARAM_FILTERS_SHIFT (0U) +/*! FILTERS - Filter Number */ +#define WUU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK) + +#define WUU_PARAM_DMAS_MASK (0xFF00U) +#define WUU_PARAM_DMAS_SHIFT (8U) +/*! DMAS - DMA Number */ +#define WUU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK) + +#define WUU_PARAM_MODULES_MASK (0xFF0000U) +#define WUU_PARAM_MODULES_SHIFT (16U) +/*! MODULES - Module Number */ +#define WUU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK) + +#define WUU_PARAM_PINS_MASK (0xFF000000U) +#define WUU_PARAM_PINS_SHIFT (24U) +/*! PINS - Pin Number */ +#define WUU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK) +/*! @} */ + +/*! @name PE1 - Pin Enable 1 */ +/*! @{ */ + +#define WUU_PE1_Reserved0_MASK (0x3U) +#define WUU_PE1_Reserved0_SHIFT (0U) +/*! Reserved0 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved0_SHIFT)) & WUU_PE1_Reserved0_MASK) + +#define WUU_PE1_Reserved1_MASK (0xCU) +#define WUU_PE1_Reserved1_SHIFT (2U) +/*! Reserved1 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved1_SHIFT)) & WUU_PE1_Reserved1_MASK) + +#define WUU_PE1_WUPE2_MASK (0x30U) +#define WUU_PE1_WUPE2_SHIFT (4U) +/*! WUPE2 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK) + +#define WUU_PE1_WUPE3_MASK (0xC0U) +#define WUU_PE1_WUPE3_SHIFT (6U) +/*! WUPE3 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK) + +#define WUU_PE1_WUPE4_MASK (0x300U) +#define WUU_PE1_WUPE4_SHIFT (8U) +/*! WUPE4 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK) + +#define WUU_PE1_WUPE5_MASK (0xC00U) +#define WUU_PE1_WUPE5_SHIFT (10U) +/*! WUPE5 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK) + +#define WUU_PE1_WUPE6_MASK (0x3000U) +#define WUU_PE1_WUPE6_SHIFT (12U) +/*! WUPE6 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK) + +#define WUU_PE1_WUPE7_MASK (0xC000U) +#define WUU_PE1_WUPE7_SHIFT (14U) +/*! WUPE7 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK) + +#define WUU_PE1_WUPE8_MASK (0x30000U) +#define WUU_PE1_WUPE8_SHIFT (16U) +/*! WUPE8 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK) + +#define WUU_PE1_WUPE9_MASK (0xC0000U) +#define WUU_PE1_WUPE9_SHIFT (18U) +/*! WUPE9 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK) + +#define WUU_PE1_WUPE10_MASK (0x300000U) +#define WUU_PE1_WUPE10_SHIFT (20U) +/*! WUPE10 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK) + +#define WUU_PE1_WUPE11_MASK (0xC00000U) +#define WUU_PE1_WUPE11_SHIFT (22U) +/*! WUPE11 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK) + +#define WUU_PE1_WUPE12_MASK (0x3000000U) +#define WUU_PE1_WUPE12_SHIFT (24U) +/*! WUPE12 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK) + +#define WUU_PE1_WUPE13_MASK (0xC000000U) +#define WUU_PE1_WUPE13_SHIFT (26U) +/*! WUPE13 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK) + +#define WUU_PE1_Reserved14_MASK (0x30000000U) +#define WUU_PE1_Reserved14_SHIFT (28U) +/*! Reserved14 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved14_SHIFT)) & WUU_PE1_Reserved14_MASK) + +#define WUU_PE1_Reserved15_MASK (0xC0000000U) +#define WUU_PE1_Reserved15_SHIFT (30U) +/*! Reserved15 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved15_SHIFT)) & WUU_PE1_Reserved15_MASK) +/*! @} */ + +/*! @name PE2 - Pin Enable 2 */ +/*! @{ */ + +#define WUU_PE2_WUPE16_MASK (0x3U) +#define WUU_PE2_WUPE16_SHIFT (0U) +/*! WUPE16 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK) + +#define WUU_PE2_WUPE17_MASK (0xCU) +#define WUU_PE2_WUPE17_SHIFT (2U) +/*! WUPE17 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK) + +#define WUU_PE2_WUPE18_MASK (0x30U) +#define WUU_PE2_WUPE18_SHIFT (4U) +/*! WUPE18 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK) + +#define WUU_PE2_WUPE19_MASK (0xC0U) +#define WUU_PE2_WUPE19_SHIFT (6U) +/*! WUPE19 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK) + +#define WUU_PE2_WUPE20_MASK (0x300U) +#define WUU_PE2_WUPE20_SHIFT (8U) +/*! WUPE20 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK) + +#define WUU_PE2_WUPE21_MASK (0xC00U) +#define WUU_PE2_WUPE21_SHIFT (10U) +/*! WUPE21 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE21_SHIFT)) & WUU_PE2_WUPE21_MASK) + +#define WUU_PE2_WUPE22_MASK (0x3000U) +#define WUU_PE2_WUPE22_SHIFT (12U) +/*! WUPE22 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK) + +#define WUU_PE2_WUPE23_MASK (0xC000U) +#define WUU_PE2_WUPE23_SHIFT (14U) +/*! WUPE23 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK) + +#define WUU_PE2_WUPE24_MASK (0x30000U) +#define WUU_PE2_WUPE24_SHIFT (16U) +/*! WUPE24 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK) + +#define WUU_PE2_WUPE25_MASK (0xC0000U) +#define WUU_PE2_WUPE25_SHIFT (18U) +/*! WUPE25 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK) + +#define WUU_PE2_WUPE26_MASK (0x300000U) +#define WUU_PE2_WUPE26_SHIFT (20U) +/*! WUPE26 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK) + +#define WUU_PE2_WUPE27_MASK (0xC00000U) +#define WUU_PE2_WUPE27_SHIFT (22U) +/*! WUPE27 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK) + +#define WUU_PE2_Reserved28_MASK (0x3000000U) +#define WUU_PE2_Reserved28_SHIFT (24U) +/*! Reserved28 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved28_SHIFT)) & WUU_PE2_Reserved28_MASK) + +#define WUU_PE2_Reserved29_MASK (0xC000000U) +#define WUU_PE2_Reserved29_SHIFT (26U) +/*! Reserved29 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved29_SHIFT)) & WUU_PE2_Reserved29_MASK) + +#define WUU_PE2_WUPE30_MASK (0x30000000U) +#define WUU_PE2_WUPE30_SHIFT (28U) +/*! WUPE30 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE30_SHIFT)) & WUU_PE2_WUPE30_MASK) + +#define WUU_PE2_WUPE31_MASK (0xC0000000U) +#define WUU_PE2_WUPE31_SHIFT (30U) +/*! WUPE31 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE31_SHIFT)) & WUU_PE2_WUPE31_MASK) +/*! @} */ + +/*! @name ME - Module Interrupt Enable */ +/*! @{ */ + +#define WUU_ME_WUME0_MASK (0x1U) +#define WUU_ME_WUME0_SHIFT (0U) +/*! WUME0 - Module Interrupt Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK) + +#define WUU_ME_WUME1_MASK (0x2U) +#define WUU_ME_WUME1_SHIFT (1U) +/*! WUME1 - Module Interrupt Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK) + +#define WUU_ME_WUME2_MASK (0x4U) +#define WUU_ME_WUME2_SHIFT (2U) +/*! WUME2 - Module Interrupt Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK) + +#define WUU_ME_WUME6_MASK (0x40U) +#define WUU_ME_WUME6_SHIFT (6U) +/*! WUME6 - Module Interrupt Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK) + +#define WUU_ME_WUME8_MASK (0x100U) +#define WUU_ME_WUME8_SHIFT (8U) +/*! WUME8 - Module Interrupt Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK) +/*! @} */ + +/*! @name DE - Module DMA/Trigger Enable */ +/*! @{ */ + +#define WUU_DE_WUDE4_MASK (0x10U) +#define WUU_DE_WUDE4_SHIFT (4U) +/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK) + +#define WUU_DE_WUDE6_MASK (0x40U) +#define WUU_DE_WUDE6_SHIFT (6U) +/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK) + +#define WUU_DE_WUDE8_MASK (0x100U) +#define WUU_DE_WUDE8_SHIFT (8U) +/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK) +/*! @} */ + +/*! @name PF - Pin Flag */ +/*! @{ */ + +#define WUU_PF_Reserved0_MASK (0x1U) +#define WUU_PF_Reserved0_SHIFT (0U) +/*! Reserved0 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved0_SHIFT)) & WUU_PF_Reserved0_MASK) + +#define WUU_PF_Reserved1_MASK (0x2U) +#define WUU_PF_Reserved1_SHIFT (1U) +/*! Reserved1 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved1_SHIFT)) & WUU_PF_Reserved1_MASK) + +#define WUU_PF_WUF2_MASK (0x4U) +#define WUU_PF_WUF2_SHIFT (2U) +/*! WUF2 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK) + +#define WUU_PF_WUF3_MASK (0x8U) +#define WUU_PF_WUF3_SHIFT (3U) +/*! WUF3 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK) + +#define WUU_PF_WUF4_MASK (0x10U) +#define WUU_PF_WUF4_SHIFT (4U) +/*! WUF4 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK) + +#define WUU_PF_WUF5_MASK (0x20U) +#define WUU_PF_WUF5_SHIFT (5U) +/*! WUF5 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK) + +#define WUU_PF_WUF6_MASK (0x40U) +#define WUU_PF_WUF6_SHIFT (6U) +/*! WUF6 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK) + +#define WUU_PF_WUF7_MASK (0x80U) +#define WUU_PF_WUF7_SHIFT (7U) +/*! WUF7 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK) + +#define WUU_PF_WUF8_MASK (0x100U) +#define WUU_PF_WUF8_SHIFT (8U) +/*! WUF8 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK) + +#define WUU_PF_WUF9_MASK (0x200U) +#define WUU_PF_WUF9_SHIFT (9U) +/*! WUF9 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK) + +#define WUU_PF_WUF10_MASK (0x400U) +#define WUU_PF_WUF10_SHIFT (10U) +/*! WUF10 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK) + +#define WUU_PF_WUF11_MASK (0x800U) +#define WUU_PF_WUF11_SHIFT (11U) +/*! WUF11 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK) + +#define WUU_PF_WUF12_MASK (0x1000U) +#define WUU_PF_WUF12_SHIFT (12U) +/*! WUF12 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK) + +#define WUU_PF_WUF13_MASK (0x2000U) +#define WUU_PF_WUF13_SHIFT (13U) +/*! WUF13 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK) + +#define WUU_PF_Reserved14_MASK (0x4000U) +#define WUU_PF_Reserved14_SHIFT (14U) +/*! Reserved14 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved14_SHIFT)) & WUU_PF_Reserved14_MASK) + +#define WUU_PF_Reserved15_MASK (0x8000U) +#define WUU_PF_Reserved15_SHIFT (15U) +/*! Reserved15 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved15_SHIFT)) & WUU_PF_Reserved15_MASK) + +#define WUU_PF_WUF16_MASK (0x10000U) +#define WUU_PF_WUF16_SHIFT (16U) +/*! WUF16 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK) + +#define WUU_PF_WUF17_MASK (0x20000U) +#define WUU_PF_WUF17_SHIFT (17U) +/*! WUF17 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK) + +#define WUU_PF_WUF18_MASK (0x40000U) +#define WUU_PF_WUF18_SHIFT (18U) +/*! WUF18 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK) + +#define WUU_PF_WUF19_MASK (0x80000U) +#define WUU_PF_WUF19_SHIFT (19U) +/*! WUF19 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK) + +#define WUU_PF_WUF20_MASK (0x100000U) +#define WUU_PF_WUF20_SHIFT (20U) +/*! WUF20 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK) + +#define WUU_PF_WUF21_MASK (0x200000U) +#define WUU_PF_WUF21_SHIFT (21U) +/*! WUF21 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF21_SHIFT)) & WUU_PF_WUF21_MASK) + +#define WUU_PF_WUF22_MASK (0x400000U) +#define WUU_PF_WUF22_SHIFT (22U) +/*! WUF22 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK) + +#define WUU_PF_WUF23_MASK (0x800000U) +#define WUU_PF_WUF23_SHIFT (23U) +/*! WUF23 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK) + +#define WUU_PF_WUF24_MASK (0x1000000U) +#define WUU_PF_WUF24_SHIFT (24U) +/*! WUF24 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK) + +#define WUU_PF_WUF25_MASK (0x2000000U) +#define WUU_PF_WUF25_SHIFT (25U) +/*! WUF25 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK) + +#define WUU_PF_WUF26_MASK (0x4000000U) +#define WUU_PF_WUF26_SHIFT (26U) +/*! WUF26 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK) + +#define WUU_PF_WUF27_MASK (0x8000000U) +#define WUU_PF_WUF27_SHIFT (27U) +/*! WUF27 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK) + +#define WUU_PF_Reserved28_MASK (0x10000000U) +#define WUU_PF_Reserved28_SHIFT (28U) +/*! Reserved28 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved28_SHIFT)) & WUU_PF_Reserved28_MASK) + +#define WUU_PF_Reserved29_MASK (0x20000000U) +#define WUU_PF_Reserved29_SHIFT (29U) +/*! Reserved29 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved29_SHIFT)) & WUU_PF_Reserved29_MASK) + +#define WUU_PF_WUF30_MASK (0x40000000U) +#define WUU_PF_WUF30_SHIFT (30U) +/*! WUF30 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF30_SHIFT)) & WUU_PF_WUF30_MASK) + +#define WUU_PF_WUF31_MASK (0x80000000U) +#define WUU_PF_WUF31_SHIFT (31U) +/*! WUF31 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF31_SHIFT)) & WUU_PF_WUF31_MASK) +/*! @} */ + +/*! @name FILT - Pin Filter */ +/*! @{ */ + +#define WUU_FILT_FILTSEL1_MASK (0x1FU) +#define WUU_FILT_FILTSEL1_SHIFT (0U) +/*! FILTSEL1 - Filter 1 Pin Select */ +#define WUU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK) + +#define WUU_FILT_FILTE1_MASK (0x60U) +#define WUU_FILT_FILTE1_SHIFT (5U) +/*! FILTE1 - Filter 1 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK) + +#define WUU_FILT_FILTF1_MASK (0x80U) +#define WUU_FILT_FILTF1_SHIFT (7U) +/*! FILTF1 - Filter 1 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK) + +#define WUU_FILT_FILTSEL2_MASK (0x1F00U) +#define WUU_FILT_FILTSEL2_SHIFT (8U) +/*! FILTSEL2 - Filter 2 Pin Select */ +#define WUU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK) + +#define WUU_FILT_FILTE2_MASK (0x6000U) +#define WUU_FILT_FILTE2_SHIFT (13U) +/*! FILTE2 - Filter 2 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK) + +#define WUU_FILT_FILTF2_MASK (0x8000U) +#define WUU_FILT_FILTF2_SHIFT (15U) +/*! FILTF2 - Filter 2 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK) +/*! @} */ + +/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */ +/*! @{ */ + +#define WUU_PDC1_Reserved0_MASK (0x3U) +#define WUU_PDC1_Reserved0_SHIFT (0U) +/*! Reserved0 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved0_SHIFT)) & WUU_PDC1_Reserved0_MASK) + +#define WUU_PDC1_Reserved1_MASK (0xCU) +#define WUU_PDC1_Reserved1_SHIFT (2U) +/*! Reserved1 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved1_SHIFT)) & WUU_PDC1_Reserved1_MASK) + +#define WUU_PDC1_WUPDC2_MASK (0x30U) +#define WUU_PDC1_WUPDC2_SHIFT (4U) +/*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK) + +#define WUU_PDC1_WUPDC3_MASK (0xC0U) +#define WUU_PDC1_WUPDC3_SHIFT (6U) +/*! WUPDC3 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK) + +#define WUU_PDC1_WUPDC4_MASK (0x300U) +#define WUU_PDC1_WUPDC4_SHIFT (8U) +/*! WUPDC4 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK) + +#define WUU_PDC1_WUPDC5_MASK (0xC00U) +#define WUU_PDC1_WUPDC5_SHIFT (10U) +/*! WUPDC5 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK) + +#define WUU_PDC1_WUPDC6_MASK (0x3000U) +#define WUU_PDC1_WUPDC6_SHIFT (12U) +/*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK) + +#define WUU_PDC1_WUPDC7_MASK (0xC000U) +#define WUU_PDC1_WUPDC7_SHIFT (14U) +/*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK) + +#define WUU_PDC1_WUPDC8_MASK (0x30000U) +#define WUU_PDC1_WUPDC8_SHIFT (16U) +/*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK) + +#define WUU_PDC1_WUPDC9_MASK (0xC0000U) +#define WUU_PDC1_WUPDC9_SHIFT (18U) +/*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK) + +#define WUU_PDC1_WUPDC10_MASK (0x300000U) +#define WUU_PDC1_WUPDC10_SHIFT (20U) +/*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK) + +#define WUU_PDC1_WUPDC11_MASK (0xC00000U) +#define WUU_PDC1_WUPDC11_SHIFT (22U) +/*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK) + +#define WUU_PDC1_WUPDC12_MASK (0x3000000U) +#define WUU_PDC1_WUPDC12_SHIFT (24U) +/*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK) + +#define WUU_PDC1_WUPDC13_MASK (0xC000000U) +#define WUU_PDC1_WUPDC13_SHIFT (26U) +/*! WUPDC13 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK) + +#define WUU_PDC1_Reserved14_MASK (0x30000000U) +#define WUU_PDC1_Reserved14_SHIFT (28U) +/*! Reserved14 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved14_SHIFT)) & WUU_PDC1_Reserved14_MASK) + +#define WUU_PDC1_Reserved15_MASK (0xC0000000U) +#define WUU_PDC1_Reserved15_SHIFT (30U) +/*! Reserved15 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved15_SHIFT)) & WUU_PDC1_Reserved15_MASK) +/*! @} */ + +/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */ +/*! @{ */ + +#define WUU_PDC2_WUPDC16_MASK (0x3U) +#define WUU_PDC2_WUPDC16_SHIFT (0U) +/*! WUPDC16 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK) + +#define WUU_PDC2_WUPDC17_MASK (0xCU) +#define WUU_PDC2_WUPDC17_SHIFT (2U) +/*! WUPDC17 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK) + +#define WUU_PDC2_WUPDC18_MASK (0x30U) +#define WUU_PDC2_WUPDC18_SHIFT (4U) +/*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK) + +#define WUU_PDC2_WUPDC19_MASK (0xC0U) +#define WUU_PDC2_WUPDC19_SHIFT (6U) +/*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK) + +#define WUU_PDC2_WUPDC20_MASK (0x300U) +#define WUU_PDC2_WUPDC20_SHIFT (8U) +/*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK) + +#define WUU_PDC2_WUPDC21_MASK (0xC00U) +#define WUU_PDC2_WUPDC21_SHIFT (10U) +/*! WUPDC21 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC21_SHIFT)) & WUU_PDC2_WUPDC21_MASK) + +#define WUU_PDC2_WUPDC22_MASK (0x3000U) +#define WUU_PDC2_WUPDC22_SHIFT (12U) +/*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK) + +#define WUU_PDC2_WUPDC23_MASK (0xC000U) +#define WUU_PDC2_WUPDC23_SHIFT (14U) +/*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK) + +#define WUU_PDC2_WUPDC24_MASK (0x30000U) +#define WUU_PDC2_WUPDC24_SHIFT (16U) +/*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK) + +#define WUU_PDC2_WUPDC25_MASK (0xC0000U) +#define WUU_PDC2_WUPDC25_SHIFT (18U) +/*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK) + +#define WUU_PDC2_WUPDC26_MASK (0x300000U) +#define WUU_PDC2_WUPDC26_SHIFT (20U) +/*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK) + +#define WUU_PDC2_WUPDC27_MASK (0xC00000U) +#define WUU_PDC2_WUPDC27_SHIFT (22U) +/*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK) + +#define WUU_PDC2_Reserved28_MASK (0x3000000U) +#define WUU_PDC2_Reserved28_SHIFT (24U) +/*! Reserved28 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved28_SHIFT)) & WUU_PDC2_Reserved28_MASK) + +#define WUU_PDC2_Reserved29_MASK (0xC000000U) +#define WUU_PDC2_Reserved29_SHIFT (26U) +/*! Reserved29 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved29_SHIFT)) & WUU_PDC2_Reserved29_MASK) + +#define WUU_PDC2_WUPDC30_MASK (0x30000000U) +#define WUU_PDC2_WUPDC30_SHIFT (28U) +/*! WUPDC30 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC30_SHIFT)) & WUU_PDC2_WUPDC30_MASK) + +#define WUU_PDC2_WUPDC31_MASK (0xC0000000U) +#define WUU_PDC2_WUPDC31_SHIFT (30U) +/*! WUPDC31 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC31_SHIFT)) & WUU_PDC2_WUPDC31_MASK) +/*! @} */ + +/*! @name FDC - Pin Filter DMA/Trigger Configuration */ +/*! @{ */ + +#define WUU_FDC_FILTC1_MASK (0x3U) +#define WUU_FDC_FILTC1_SHIFT (0U) +/*! FILTC1 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK) + +#define WUU_FDC_FILTC2_MASK (0xCU) +#define WUU_FDC_FILTC2_SHIFT (2U) +/*! FILTC2 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK) +/*! @} */ + +/*! @name PMC - Pin Mode Configuration */ +/*! @{ */ + +#define WUU_PMC_Reserved0_MASK (0x1U) +#define WUU_PMC_Reserved0_SHIFT (0U) +/*! Reserved0 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved0_SHIFT)) & WUU_PMC_Reserved0_MASK) + +#define WUU_PMC_Reserved1_MASK (0x2U) +#define WUU_PMC_Reserved1_SHIFT (1U) +/*! Reserved1 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved1_SHIFT)) & WUU_PMC_Reserved1_MASK) + +#define WUU_PMC_WUPMC2_MASK (0x4U) +#define WUU_PMC_WUPMC2_SHIFT (2U) +/*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK) + +#define WUU_PMC_WUPMC3_MASK (0x8U) +#define WUU_PMC_WUPMC3_SHIFT (3U) +/*! WUPMC3 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK) + +#define WUU_PMC_WUPMC4_MASK (0x10U) +#define WUU_PMC_WUPMC4_SHIFT (4U) +/*! WUPMC4 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK) + +#define WUU_PMC_WUPMC5_MASK (0x20U) +#define WUU_PMC_WUPMC5_SHIFT (5U) +/*! WUPMC5 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK) + +#define WUU_PMC_WUPMC6_MASK (0x40U) +#define WUU_PMC_WUPMC6_SHIFT (6U) +/*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK) + +#define WUU_PMC_WUPMC7_MASK (0x80U) +#define WUU_PMC_WUPMC7_SHIFT (7U) +/*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK) + +#define WUU_PMC_WUPMC8_MASK (0x100U) +#define WUU_PMC_WUPMC8_SHIFT (8U) +/*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK) + +#define WUU_PMC_WUPMC9_MASK (0x200U) +#define WUU_PMC_WUPMC9_SHIFT (9U) +/*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK) + +#define WUU_PMC_WUPMC10_MASK (0x400U) +#define WUU_PMC_WUPMC10_SHIFT (10U) +/*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK) + +#define WUU_PMC_WUPMC11_MASK (0x800U) +#define WUU_PMC_WUPMC11_SHIFT (11U) +/*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK) + +#define WUU_PMC_WUPMC12_MASK (0x1000U) +#define WUU_PMC_WUPMC12_SHIFT (12U) +/*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK) + +#define WUU_PMC_WUPMC13_MASK (0x2000U) +#define WUU_PMC_WUPMC13_SHIFT (13U) +/*! WUPMC13 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK) + +#define WUU_PMC_Reserved14_MASK (0x4000U) +#define WUU_PMC_Reserved14_SHIFT (14U) +/*! Reserved14 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved14_SHIFT)) & WUU_PMC_Reserved14_MASK) + +#define WUU_PMC_Reserved15_MASK (0x8000U) +#define WUU_PMC_Reserved15_SHIFT (15U) +/*! Reserved15 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved15_SHIFT)) & WUU_PMC_Reserved15_MASK) + +#define WUU_PMC_WUPMC16_MASK (0x10000U) +#define WUU_PMC_WUPMC16_SHIFT (16U) +/*! WUPMC16 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK) + +#define WUU_PMC_WUPMC17_MASK (0x20000U) +#define WUU_PMC_WUPMC17_SHIFT (17U) +/*! WUPMC17 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK) + +#define WUU_PMC_WUPMC18_MASK (0x40000U) +#define WUU_PMC_WUPMC18_SHIFT (18U) +/*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK) + +#define WUU_PMC_WUPMC19_MASK (0x80000U) +#define WUU_PMC_WUPMC19_SHIFT (19U) +/*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK) + +#define WUU_PMC_WUPMC20_MASK (0x100000U) +#define WUU_PMC_WUPMC20_SHIFT (20U) +/*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK) + +#define WUU_PMC_WUPMC21_MASK (0x200000U) +#define WUU_PMC_WUPMC21_SHIFT (21U) +/*! WUPMC21 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC21_SHIFT)) & WUU_PMC_WUPMC21_MASK) + +#define WUU_PMC_WUPMC22_MASK (0x400000U) +#define WUU_PMC_WUPMC22_SHIFT (22U) +/*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK) + +#define WUU_PMC_WUPMC23_MASK (0x800000U) +#define WUU_PMC_WUPMC23_SHIFT (23U) +/*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK) + +#define WUU_PMC_WUPMC24_MASK (0x1000000U) +#define WUU_PMC_WUPMC24_SHIFT (24U) +/*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK) + +#define WUU_PMC_WUPMC25_MASK (0x2000000U) +#define WUU_PMC_WUPMC25_SHIFT (25U) +/*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK) + +#define WUU_PMC_WUPMC26_MASK (0x4000000U) +#define WUU_PMC_WUPMC26_SHIFT (26U) +/*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK) + +#define WUU_PMC_WUPMC27_MASK (0x8000000U) +#define WUU_PMC_WUPMC27_SHIFT (27U) +/*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK) + +#define WUU_PMC_Reserved28_MASK (0x10000000U) +#define WUU_PMC_Reserved28_SHIFT (28U) +/*! Reserved28 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved28_SHIFT)) & WUU_PMC_Reserved28_MASK) + +#define WUU_PMC_Reserved29_MASK (0x20000000U) +#define WUU_PMC_Reserved29_SHIFT (29U) +/*! Reserved29 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved29_SHIFT)) & WUU_PMC_Reserved29_MASK) + +#define WUU_PMC_WUPMC30_MASK (0x40000000U) +#define WUU_PMC_WUPMC30_SHIFT (30U) +/*! WUPMC30 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_WUPMC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC30_SHIFT)) & WUU_PMC_WUPMC30_MASK) + +#define WUU_PMC_WUPMC31_MASK (0x80000000U) +#define WUU_PMC_WUPMC31_SHIFT (31U) +/*! WUPMC31 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_WUPMC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC31_SHIFT)) & WUU_PMC_WUPMC31_MASK) +/*! @} */ + +/*! @name FMC - Pin Filter Mode Configuration */ +/*! @{ */ + +#define WUU_FMC_FILTM1_MASK (0x1U) +#define WUU_FMC_FILTM1_SHIFT (0U) +/*! FILTM1 - Filter Mode for FILTn + * 0b0..Active only during Deep Sleep 1/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK) + +#define WUU_FMC_FILTM2_MASK (0x2U) +#define WUU_FMC_FILTM2_SHIFT (1U) +/*! FILTM2 - Filter Mode for FILTn + * 0b0..Active only during Deep Sleep 1/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WUU_Register_Masks */ + + +/*! + * @} + */ /* end of group WUU_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_WUU_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WWDT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WWDT.h new file mode 100644 index 000000000..211644874 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph3/PERI_WWDT.h @@ -0,0 +1,245 @@ +/* +** ################################################################### +** Processors: MCXA343VFM +** MCXA343VLF +** MCXA343VLH +** MCXA343VLL +** MCXA344VFM +** MCXA344VLF +** MCXA344VLH +** MCXA344VLL +** +** Version: rev. 2.0, 2024-10-29 +** Build: b250806 +** +** Abstract: +** CMSIS Peripheral Access Layer for WWDT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-03-26) +** Initial version based on Rev1 DraftC RM +** - rev. 2.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file PERI_WWDT.h + * @version 2.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for WWDT + * + * CMSIS Peripheral Access Layer for WWDT + */ + +#if !defined(PERI_WWDT_H_) +#define PERI_WWDT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA343VFM) || defined(CPU_MCXA343VLF) || defined(CPU_MCXA343VLH) || defined(CPU_MCXA343VLL)) +#include "MCXA343_COMMON.h" +#elif (defined(CPU_MCXA344VFM) || defined(CPU_MCXA344VLF) || defined(CPU_MCXA344VLH) || defined(CPU_MCXA344VLL)) +#include "MCXA344_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Mode, offset: 0x0 */ + __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */ + __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */ + __I uint32_t TV; /**< Timer Value, offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */ + __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Mode */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog Enable + * 0b0..Timer stopped + * 0b1..Timer running + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog Reset Enable + * 0b0..Interrupt + * 0b1..Reset + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog Timeout Flag + * 0b0..Watchdog event has not occurred. + * 0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1). + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning Interrupt Flag + * 0b0..No flag + * 0b1..Flag + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog Update Mode + * 0b0..Flexible + * 0b1..Threshold + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) + +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +/*! LOCK - Lock + * 0b0..No Lock + * 0b1..Lock + */ +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) +/*! @} */ + +/*! @name TC - Timer Constant */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog Timeout Value */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Feed Sequence */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed Value */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Timer Value */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter Timer Value */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Warning Interrupt Compare Value */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog Warning Interrupt Compare Value */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Window Compare Value */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog Window Value */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_WWDT_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_ADC.h new file mode 100644 index 000000000..3fea5bf4d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_ADC.h @@ -0,0 +1,1051 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for ADC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_ADC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for ADC + * + * CMSIS Peripheral Access Layer for ADC + */ + +#if !defined(PERI_ADC_H_) +#define PERI_ADC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Size of Registers Arrays */ +#define ADC_TCTRL_COUNT 4u +#define ADC_GCC_COUNT 1u +#define ADC_GCR_COUNT 1u +#define ADC_CMD_COUNT 7u +#define ADC_CV_COUNT 7u +#define ADC_CAL_GAR_COUNT 34u + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[4]; + __IO uint32_t HSTRIM; /**< High Speed Trim Register, offset: 0x48 */ + uint8_t RESERVED_4[84]; + __IO uint32_t TCTRL[ADC_TCTRL_COUNT]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[48]; + __IO uint32_t FCTRL; /**< FIFO Control Register, offset: 0xE0 */ + uint8_t RESERVED_6[12]; + __I uint32_t GCC[ADC_GCC_COUNT]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + uint8_t RESERVED_7[4]; + __IO uint32_t GCR[ADC_GCR_COUNT]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + uint8_t RESERVED_8[4]; + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[ADC_CMD_COUNT]; + uint8_t RESERVED_9[200]; + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[228]; + __I uint32_t RESFIFO; /**< Data Result FIFO Register, offset: 0x300 */ + uint8_t RESERVED_11[252]; + __IO uint32_t CAL_GAR[ADC_CAL_GAR_COUNT]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_12[2928]; + __IO uint32_t CFG2; /**< Configuration 2 Register, offset: 0xFF8 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID[DIFFEN] = 1b). + * 0b1..Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID[DIFFEN] = 1b). + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock Implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultaneous single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 2 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in low power mode. + * 0b1..ADC is disabled in low power mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for hardware calibration has been made + * 0b1..A request for hardware calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Offset Calibration Request + * 0b0..No request for offset calibration has been made + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_CALHS_MASK (0x40U) +#define ADC_CTRL_CALHS_SHIFT (6U) +/*! CALHS - High Speed Mode Trim Request + * 0b0..No request for high speed mode trim has been made + * 0b1..Request for high speed mode trim has been made + */ +#define ADC_CTRL_CALHS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALHS_SHIFT)) & ADC_CTRL_CALHS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0xF0000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b0000..Single conversion. + * 0b0001..2 conversions averaged. + * 0b0010..4 conversions averaged. + * 0b0011..8 conversions averaged. + * 0b0100..16 conversions averaged. + * 0b0101..32 conversions averaged. + * 0b0110..64 conversions averaged. + * 0b0111..128 conversions averaged. + * 0b1000..256 conversions averaged. + * 0b1001..512 conversions averaged. + * 0b1010..1024 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0x30000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b00..Command (sequence) associated with Trigger 0 currently being executed. + * 0b01..Command (sequence) associated with Trigger 1 currently being executed. + * 0b10..Command (sequence) associated with Trigger 2 currently being executed. + * 0b11..Command (sequence) associated with Trigger 3 currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0x7000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b000..No command is currently in progress. + * 0b001..Command 1 currently being executed. + * 0b010..Command 2 currently being executed. + * 0b011-0b111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000..Trigger completion interrupts are disabled. + * 0b0001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0011-0b1110..Associated trigger completion interrupts are enabled. + * 0b1111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) +/*! @} */ + +/*! @name CFG - Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC Trigger Priority Control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11.. + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x20U) +#define ADC_CFG_PWRSEL_SHIFT (5U) +/*! PWRSEL - Power Configuration Select + * 0b0..Low power + * 0b1..High power + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately + * once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has + * passed. After this initial delay expires the analog remains pre-enabled and no additional delays are + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software Trigger 0 Event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software Trigger 1 Event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software Trigger 2 Event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software Trigger 3 Event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0001..Trigger 0 has been interrupted by a high priority exception. + * 0b0010..Trigger 1 has been interrupted by a high priority exception. + * 0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts. + * 0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts. + * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_MASK (0x3FFU) +#define ADC_OFSTRIM_OFSTRIM_SHIFT (0U) +/*! OFSTRIM - Trim for Offset */ +#define ADC_OFSTRIM_OFSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK) +/*! @} */ + +/*! @name HSTRIM - High Speed Trim Register */ +/*! @{ */ + +#define ADC_HSTRIM_HSTRIM_MASK (0x1FU) +#define ADC_HSTRIM_HSTRIM_SHIFT (0U) +/*! HSTRIM - Trim for High Speed Conversions */ +#define ADC_HSTRIM_HSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_HSTRIM_HSTRIM_SHIFT)) & ADC_HSTRIM_HSTRIM_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger Enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_TPRI_MASK (0x300U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger Priority Setting + * 0b00..Set to highest priority, Level 1 + * 0b01-0b10..Set to corresponding priority level + * 0b11..Set to lowest priority, Level 4 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger Delay Select */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TSYNC_MASK (0x800000U) +#define ADC_TCTRL_TSYNC_SHIFT (23U) +/*! TSYNC - Trigger Synchronous Select */ +#define ADC_TCTRL_TSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TSYNC_SHIFT)) & ADC_TCTRL_TSYNC_MASK) + +#define ADC_TCTRL_TCMD_MASK (0x7000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger Command Select + * 0b000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b001..CMD1 is executed + * 0b010-0b110..Corresponding CMD is executed + * 0b111..CMD7 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0xFU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO Counter */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0x70000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark Level Selection */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set. + * 0b1..The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR]. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0x1FFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The GCALR value is invalid. + * 0b1..The GCALR value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/*! @name CMDL - Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b00000..Select CH0A. + * 0b00001..Select CH1A. + * 0b00010..Select CH2A. + * 0b00011..Select CH3A. + * 0b00100-0b11101..Select corresponding channel CHnA. + * 0b11110..Select CH30A. + * 0b11111..Select CH31A. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01-0b11..Reserved. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select Resolution of Conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion. + * 0b1..High resolution. Single-ended 16-bit conversion. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (7U) + +/*! @name CMDH - Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for Trigger Assertion before Execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3.5 ADCK cycles. + * 0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time. + * 0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time. + * 0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time. + * 0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time. + * 0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time. + * 0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time. + * 0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0xF000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b0000..Single conversion. + * 0b0001..2 conversions averaged. + * 0b0010..4 conversions averaged. + * 0b0011..8 conversions averaged. + * 0b0100..16 conversions averaged. + * 0b0101..32 conversions averaged. + * 0b0110..64 conversions averaged. + * 0b0111..128 conversions averaged. + * 0b1000..256 conversions averaged. + * 0b1001..512 conversions averaged. + * 0b1010..1024 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0x7000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b001..Select CMD1 command buffer register as next command. + * 0b010-0b110..Select corresponding CMD command buffer register as next command + * 0b111..Select CMD7 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (7U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/*! @name RESFIFO - Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data Result */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0x30000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b00..Trigger source 0 initiated this conversion. + * 0b01..Trigger source 1 initiated this conversion. + * 0b10..Trigger source 2 initiated this conversion. + * 0b11..Trigger source 3 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop Count Value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0x7000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior + * to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b001..CMD1 buffer used as control settings for this conversion. + * 0b010-0b110..Corresponding command buffer used as control settings for this conversion. + * 0b111..CMD7 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO Entry is Valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration 2 Register */ +/*! @{ */ + +#define ADC_CFG2_JLEFT_MASK (0x100U) +#define ADC_CFG2_JLEFT_SHIFT (8U) +/*! JLEFT - Justified Left Enable register */ +#define ADC_CFG2_JLEFT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_JLEFT_SHIFT)) & ADC_CFG2_JLEFT_MASK) + +#define ADC_CFG2_HS_MASK (0x200U) +#define ADC_CFG2_HS_SHIFT (9U) +/*! HS - High Speed Enable register + * 0b0..High speed conversion mode disabled + * 0b1..High speed conversion mode enabled + */ +#define ADC_CFG2_HS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HS_SHIFT)) & ADC_CFG2_HS_MASK) + +#define ADC_CFG2_HSEXTRA_MASK (0x400U) +#define ADC_CFG2_HSEXTRA_SHIFT (10U) +/*! HSEXTRA - High Speed Extra register + * 0b0..No extra cycle added + * 0b1..Extra cycle added + */ +#define ADC_CFG2_HSEXTRA(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HSEXTRA_SHIFT)) & ADC_CFG2_HSEXTRA_MASK) + +#define ADC_CFG2_TUNE_MASK (0x3000U) +#define ADC_CFG2_TUNE_SHIFT (12U) +/*! TUNE - Tune Mode register */ +#define ADC_CFG2_TUNE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_TUNE_SHIFT)) & ADC_CFG2_TUNE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + +/* Backward compatibility */ +#define ADC_CTRL_RSTFIFO_MASK ADC_CTRL_RSTFIFO0_MASK +#define ADC_CTRL_RSTFIFO_SHIFT ADC_CTRL_RSTFIFO0_SHIFT +#define ADC_CTRL_RSTFIFO(x) ADC_CTRL_RSTFIFO0(x) +#define ADC_STAT_RDY_MASK ADC_STAT_RDY0_MASK +#define ADC_STAT_RDY_SHIFT ADC_STAT_RDY0_SHIFT +#define ADC_STAT_RDY(x) ADC_STAT_RDY0(x) +#define ADC_STAT_FOF_MASK ADC_STAT_FOF0_MASK +#define ADC_STAT_FOF_SHIFT ADC_STAT_FOF0_SHIFT +#define ADC_STAT_FOF(x) ADC_STAT_FOF0(x) +#define ADC_IE_FWMIE_MASK ADC_IE_FWMIE0_MASK +#define ADC_IE_FWMIE_SHIFT ADC_IE_FWMIE0_SHIFT +#define ADC_IE_FWMIE(x) ADC_IE_FWMIE0(x) +#define ADC_IE_FOFIE_MASK ADC_IE_FOFIE0_MASK +#define ADC_IE_FOFIE_SHIFT ADC_IE_FOFIE0_SHIFT +#define ADC_IE_FOFIE(x) ADC_IE_FOFIE0(x) +#define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK +#define ADC_DE_FWMDE_SHIFT ADC_DE_FWMDE0_SHIFT +#define ADC_DE_FWMDE(x) ADC_DE_FWMDE0(x) + + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_ADC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_AOI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_AOI.h new file mode 100644 index 000000000..31e1eb511 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_AOI.h @@ -0,0 +1,355 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for AOI +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_AOI.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for AOI + * + * CMSIS Peripheral Access Layer for AOI + */ + +#if !defined(PERI_AOI_H_) +#define PERI_AOI_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- AOI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer + * @{ + */ + +/** AOI - Size of Registers Arrays */ +#define AOI_BFCRT_COUNT 4u + +/** AOI - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3, array offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3, array offset: 0x2, array step: 0x4 */ + } BFCRT[AOI_BFCRT_COUNT]; +} AOI_Type; + +/* ---------------------------------------------------------------------------- + -- AOI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Register_Masks AOI Register Masks + * @{ + */ + +/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3 */ +/*! @{ */ + +#define AOI_BFCRT01_PT1_DC_MASK (0x3U) +#define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product Term 1, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) + +#define AOI_BFCRT01_PT1_CC_MASK (0xCU) +#define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product Term 1, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) + +#define AOI_BFCRT01_PT1_BC_MASK (0x30U) +#define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product Term 1, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) + +#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) +#define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product Term 1, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input A to become 1 + */ +#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) + +#define AOI_BFCRT01_PT0_DC_MASK (0x300U) +#define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product Term 0, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) + +#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) +#define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product Term 0, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) + +#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) +#define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product Term 0, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) + +#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) +#define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product Term 0, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input A to become 1 + */ +#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT01 */ +#define AOI_BFCRT01_COUNT (4U) + +/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3 */ +/*! @{ */ + +#define AOI_BFCRT23_PT3_DC_MASK (0x3U) +#define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product Term 3, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) + +#define AOI_BFCRT23_PT3_CC_MASK (0xCU) +#define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product Term 3, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) + +#define AOI_BFCRT23_PT3_BC_MASK (0x30U) +#define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product Term 3, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) + +#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) +#define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product Term 3, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input to become 1 + */ +#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) + +#define AOI_BFCRT23_PT2_DC_MASK (0x300U) +#define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product Term 2, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) + +#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) +#define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product Term 2, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) + +#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) +#define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product Term 2, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) + +#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) +#define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product Term 2, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input A to become 1 + */ +#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT23 */ +#define AOI_BFCRT23_COUNT (4U) + + +/*! + * @} + */ /* end of group AOI_Register_Masks */ + + +/*! + * @} + */ /* end of group AOI_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_AOI_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CAN.h new file mode 100644 index 000000000..b9c0a33d6 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CAN.h @@ -0,0 +1,2288 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for CAN +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_CAN.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for CAN + * + * CMSIS Peripheral Access Layer for CAN + */ + +#if !defined(PERI_CAN_H_) +#define PERI_CAN_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Size of Registers Arrays */ +#define CAN_MB_SIZE_MB_8B_GROUP_MB_8B_WORD_8B_COUNT 2u +#define CAN_MB_SIZE_MB_8B_GROUP_MB_8B_COUNT 32u +#define CAN_MB_SIZE_MB_16B_GROUP_MB_16B_WORD_16B_COUNT 4u +#define CAN_MB_SIZE_MB_16B_GROUP_MB_16B_COUNT 21u +#define CAN_MB_SIZE_MB_32B_GROUP_MB_32B_WORD_32B_COUNT 8u +#define CAN_MB_SIZE_MB_32B_GROUP_MB_32B_COUNT 12u +#define CAN_MB_SIZE_MB_64B_GROUP_MB_64B_WORD_64B_COUNT 16u +#define CAN_MB_SIZE_MB_64B_GROUP_MB_64B_COUNT 7u +#define CAN_MB_SIZE_MB_GROUP_MB_COUNT 32u +#define CAN_RXIMR_COUNT 32u +#define CAN_WMB_COUNT 4u +#define CAN_ERFFEL_COUNT 32u + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ + uint8_t RESERVED_3[8]; + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ + uint8_t RESERVED_4[44]; + union { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD[CAN_MB_SIZE_MB_8B_GROUP_MB_8B_WORD_8B_COUNT]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ + } MB_8B[CAN_MB_SIZE_MB_8B_GROUP_MB_8B_COUNT]; + struct { /* offset: 0x80, array step: 0x18 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */ + __IO uint32_t WORD[CAN_MB_SIZE_MB_16B_GROUP_MB_16B_WORD_16B_COUNT]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ + } MB_16B[CAN_MB_SIZE_MB_16B_GROUP_MB_16B_COUNT]; + struct { /* offset: 0x80, array step: 0x28 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */ + __IO uint32_t WORD[CAN_MB_SIZE_MB_32B_GROUP_MB_32B_WORD_32B_COUNT]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ + } MB_32B[CAN_MB_SIZE_MB_32B_GROUP_MB_32B_COUNT]; + struct { /* offset: 0x80, array step: 0x48 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */ + __IO uint32_t WORD[CAN_MB_SIZE_MB_64B_GROUP_MB_64B_WORD_64B_COUNT]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ + } MB_64B[CAN_MB_SIZE_MB_64B_GROUP_MB_64B_COUNT]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[CAN_MB_SIZE_MB_GROUP_MB_COUNT]; + }; + uint8_t RESERVED_5[1536]; + __IO uint32_t RXIMR[CAN_RXIMR_COUNT]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_6[512]; + __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1, offset: 0xB00 */ + __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2, offset: 0xB04 */ + __IO uint32_t WU_MTC; /**< Pretended Networking Wake-Up Match, offset: 0xB08 */ + __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1, offset: 0xB0C */ + __IO uint32_t FLT_DLC; /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */ + __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */ + __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */ + __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */ + __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */ + __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */ + uint8_t RESERVED_7[24]; + struct { /* offset: 0xB40, array step: 0x10 */ + __I uint32_t CS; /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */ + __I uint32_t ID; /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */ + __I uint32_t D03; /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */ + __I uint32_t D47; /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ + } WMB[CAN_WMB_COUNT]; + uint8_t RESERVED_8[112]; + __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ + __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ + __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ + uint8_t RESERVED_9[9192]; + __IO uint32_t ERFFEL[CAN_ERFFEL_COUNT]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration */ +/*! @{ */ + +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +/*! MAXMB - Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) + +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A: One full ID (standard and extended) per ID filter table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. + * 0b11..Format D: All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) + +#define CAN_MCR_FDEN_MASK (0x800U) +#define CAN_MCR_FDEN_SHIFT (11U) +/*! FDEN - CAN FD Operation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) + +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) + +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) + +#define CAN_MCR_PNET_EN_MASK (0x4000U) +#define CAN_MCR_PNET_EN_SHIFT (14U) +/*! PNET_EN - Pretended Networking Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) + +#define CAN_MCR_DMA_MASK (0x8000U) +#define CAN_MCR_DMA_SHIFT (15U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) + +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) + +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) + +#define CAN_MCR_DOZE_MASK (0x40000U) +#define CAN_MCR_DOZE_SHIFT (18U) +/*! DOZE - Doze Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) + +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) + +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) + +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) + +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self-Wake-Up Feature + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) + +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV - Supervisor Mode + * 0b0..User mode + * 0b1..Supervisor mode + */ +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) + +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) + +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b0..No reset + * 0b1..Soft reset affects reset registers + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) + +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) + +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode. + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) + +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) + +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) + +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) + +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +/*! PROPSEG - Propagation Segment */ +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) + +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) + +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) + +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) + +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) + +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b0..One sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two + * preceding samples. A majority rule is used. + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) + +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) + +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) + +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) + +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) + +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) + +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +/*! PSEG2 - Phase Segment 2 */ +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) + +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +/*! PSEG1 - Phase Segment 1 */ +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) + +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +/*! RJW - Resync Jump Width */ +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) + +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +/*! PRESDIV - Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free-Running Timer */ +/*! @{ */ + +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer Value */ +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - RX Message Buffers Global Mask */ +/*! @{ */ + +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Global Mask for RX Message Buffers */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Receive 14 Mask */ +/*! @{ */ + +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - RX Buffer 14 Mask Bits */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Receive 15 Mask */ +/*! @{ */ + +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - RX Buffer 15 Mask Bits */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter */ +/*! @{ */ + +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +/*! TXERRCNT - Transmit Error Counter */ +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) + +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +/*! RXERRCNT - Receive Error Counter */ +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ +#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) + +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ +#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 */ +/*! @{ */ + +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-up Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) + +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates setting of any error flag in the Error and Status register. + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) + +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt Flag + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) + +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) + +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus Off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) + +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b0..Not transmitting + * 0b1..Transmitting + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) + +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) + +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - RX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) + +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..TXERRCNT is 96 or greater. + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) + +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) + +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) + +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) + +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) + +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) + +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) + +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) + +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) + +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) +#define CAN_ESR1_BOFFDONEINT_SHIFT (19U) +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence + * 0b1..FlexCAN module has completed Bus Off process. + */ +#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) + +#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) +#define CAN_ESR1_ERRINT_FAST_SHIFT (20U) +/*! ERRINT_FAST - Fast Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. + */ +#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) + +#define CAN_ESR1_ERROVR_MASK (0x200000U) +#define CAN_ESR1_ERROVR_SHIFT (21U) +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun + */ +#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) + +#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) +#define CAN_ESR1_STFERR_FAST_SHIFT (26U) +/*! STFERR_FAST - Fast Stuffing Error Flag + * 0b0..No such occurrence. + * 0b1..A stuffing error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) + +#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) +#define CAN_ESR1_FRMERR_FAST_SHIFT (27U) +/*! FRMERR_FAST - Fast Form Error Flag + * 0b0..No such occurrence. + * 0b1..A form error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) + +#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) +#define CAN_ESR1_CRCERR_FAST_SHIFT (28U) +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) + +#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) +#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) +/*! BIT0ERR_FAST - Fast Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) + +#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) +#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) +/*! BIT1ERR_FAST - Fast Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 */ +/*! @{ */ + +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUF31TO0M_SHIFT (0U) +/*! BUF31TO0M - Buffer MBi Mask */ +#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 */ +/*! @{ */ + +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. + */ +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) + +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) + +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) + +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) + +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) + +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_PES_MASK (0x1U) +#define CAN_CTRL2_PES_SHIFT (0U) +/*! PES - Payload Byte and Bit Order Selection + * 0b0..Big-endian + * 0b1..Little-endian + */ +#define CAN_CTRL2_PES(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PES_SHIFT)) & CAN_CTRL2_PES_MASK) + +#define CAN_CTRL2_ASD_MASK (0x2U) +#define CAN_CTRL2_ASD_SHIFT (1U) +/*! ASD - ACK Suppression Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_ASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ASD_SHIFT)) & CAN_CTRL2_ASD_MASK) + +#define CAN_CTRL2_EDFLTDIS_MASK (0x800U) +#define CAN_CTRL2_EDFLTDIS_SHIFT (11U) +/*! EDFLTDIS - Edge Filter Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) + +#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) +#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) +/*! ISOCANFDEN - ISO CAN FD Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) + +#define CAN_CTRL2_BTE_MASK (0x2000U) +#define CAN_CTRL2_BTE_SHIFT (13U) +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) + +#define CAN_CTRL2_PREXCEN_MASK (0x4000U) +#define CAN_CTRL2_PREXCEN_SHIFT (14U) +/*! PREXCEN - Protocol Exception Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) + +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) + +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b0..Generated + * 0b1..Stored + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) + +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) + +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +/*! TASD - Transmission Arbitration Start Delay */ +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) + +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +/*! RFFN - Number of Legacy Receive FIFO Filters */ +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) + +#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) +#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) +/*! BOFFDONEMSK - Bus Off Done Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) + +#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) +#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 */ +/*! @{ */ + +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) + +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b0..Invalid + * 0b1..Valid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) + +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +/*! LPTM - Lowest Priority TX Message Buffer */ +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - Cyclic Redundancy Check */ +/*! @{ */ + +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +/*! TXCRC - Transmitted CRC value */ +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) + +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +/*! MBCRC - CRC Message Buffer */ +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ +/*! @{ */ + +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy RX FIFO Global Mask Bits */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Legacy RX FIFO Information */ +/*! @{ */ + +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +/*! IDHIT - Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CBT - CAN Bit Timing */ +/*! @{ */ + +#define CAN_CBT_EPSEG2_MASK (0x1FU) +#define CAN_CBT_EPSEG2_SHIFT (0U) +/*! EPSEG2 - Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) + +#define CAN_CBT_EPSEG1_MASK (0x3E0U) +#define CAN_CBT_EPSEG1_SHIFT (5U) +/*! EPSEG1 - Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) + +#define CAN_CBT_EPROPSEG_MASK (0xFC00U) +#define CAN_CBT_EPROPSEG_SHIFT (10U) +/*! EPROPSEG - Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) + +#define CAN_CBT_ERJW_MASK (0x1F0000U) +#define CAN_CBT_ERJW_SHIFT (16U) +/*! ERJW - Extended Resync Jump Width */ +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) + +#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) +#define CAN_CBT_EPRESDIV_SHIFT (21U) +/*! EPRESDIV - Extended Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) + +#define CAN_CBT_BTF_MASK (0x80000000U) +#define CAN_CBT_BTF_SHIFT (31U) +/*! BTF - Bit Timing Format Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB8B (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B2 (2U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB16B (21U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B2 (4U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB32B (12U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B2 (8U) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */ +/*! @{ */ + +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running + * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field + * appears on the CAN bus. + */ +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) + +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +/*! DLC - Length of the data to be stored/transmitted. */ +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) + +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) + +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) + +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) + +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by + * the FlexCAN module itself, as part of the message buffer matching and arbitration process. + */ +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +#define CAN_CS_ESI_MASK (0x20000000U) +#define CAN_CS_ESI_SHIFT (29U) +/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) + +#define CAN_CS_BRS_MASK (0x40000000U) +#define CAN_CS_BRS_SHIFT (30U) +/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) + +#define CAN_CS_EDL_MASK (0x80000000U) +#define CAN_CS_EDL_SHIFT (31U) +/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. + * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + */ +#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB64B (7U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */ +/*! @{ */ + +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +/*! EXT - Contains extended (LOW word) identifier of message buffer. */ +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) + +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) + +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only + * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular + * ID to define the transmission priority. + */ +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB64B (7U) + +/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */ +/*! @{ */ + +#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) + +#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) + +#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_11_SHIFT (0U) +/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) + +#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_15_SHIFT (0U) +/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) + +#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_19_SHIFT (0U) +/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) + +#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_23_SHIFT (0U) +/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) + +#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_27_SHIFT (0U) +/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) + +#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_31_SHIFT (0U) +/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) + +#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_35_SHIFT (0U) +/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) + +#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_39_SHIFT (0U) +/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) + +#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_43_SHIFT (0U) +/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) + +#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_47_SHIFT (0U) +/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) + +#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_51_SHIFT (0U) +/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) + +#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_55_SHIFT (0U) +/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) + +#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_59_SHIFT (0U) +/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) + +#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_63_SHIFT (0U) +/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) + +#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) + +#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) + +#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_10_SHIFT (8U) +/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) + +#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_14_SHIFT (8U) +/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) + +#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_18_SHIFT (8U) +/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) + +#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_22_SHIFT (8U) +/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) + +#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_26_SHIFT (8U) +/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) + +#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_30_SHIFT (8U) +/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) + +#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_34_SHIFT (8U) +/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) + +#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_38_SHIFT (8U) +/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) + +#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_42_SHIFT (8U) +/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) + +#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_46_SHIFT (8U) +/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) + +#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_50_SHIFT (8U) +/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) + +#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_54_SHIFT (8U) +/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) + +#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_58_SHIFT (8U) +/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) + +#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_62_SHIFT (8U) +/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) + +#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) + +#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) + +#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_9_SHIFT (16U) +/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) + +#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_13_SHIFT (16U) +/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) + +#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_17_SHIFT (16U) +/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) + +#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_21_SHIFT (16U) +/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) + +#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_25_SHIFT (16U) +/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) + +#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_29_SHIFT (16U) +/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) + +#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_33_SHIFT (16U) +/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) + +#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_37_SHIFT (16U) +/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) + +#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_41_SHIFT (16U) +/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) + +#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_45_SHIFT (16U) +/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) + +#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_49_SHIFT (16U) +/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) + +#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_53_SHIFT (16U) +/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) + +#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_57_SHIFT (16U) +/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) + +#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_61_SHIFT (16U) +/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) + +#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) + +#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) + +#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_8_SHIFT (24U) +/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) + +#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_12_SHIFT (24U) +/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) + +#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_16_SHIFT (24U) +/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) + +#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_20_SHIFT (24U) +/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) + +#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_24_SHIFT (24U) +/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) + +#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_28_SHIFT (24U) +/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) + +#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_32_SHIFT (24U) +/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) + +#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_36_SHIFT (24U) +/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) + +#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_40_SHIFT (24U) +/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) + +#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_44_SHIFT (24U) +/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) + +#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_48_SHIFT (24U) +/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) + +#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_52_SHIFT (24U) +/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) + +#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_56_SHIFT (24U) +/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) + +#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_60_SHIFT (24U) +/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) +/*! @} */ + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B (7U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B2 (16U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (32U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */ +/*! @{ */ + +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) + +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) + +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) + +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (32U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */ +/*! @{ */ + +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) + +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) + +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) + +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (32U) + +/*! @name RXIMR - Receive Individual Mask */ +/*! @{ */ + +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/*! @name CTRL1_PN - Pretended Networking Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PN_FCS_MASK (0x3U) +#define CAN_CTRL1_PN_FCS_SHIFT (0U) +/*! FCS - Filtering Combination Selection + * 0b00..Message ID filtering only + * 0b01..Message ID filtering and payload filtering + * 0b10..Message ID filtering occurring a specified number of times + * 0b11..Message ID filtering and payload filtering a specified number of times + */ +#define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK) + +#define CAN_CTRL1_PN_IDFS_MASK (0xCU) +#define CAN_CTRL1_PN_IDFS_SHIFT (2U) +/*! IDFS - ID Filtering Selection + * 0b00..Match ID contents to an exact target value + * 0b01..Match an ID value greater than or equal to a specified target value + * 0b10..Match an ID value smaller than or equal to a specified target value + * 0b11..Match an ID value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) + +#define CAN_CTRL1_PN_PLFS_MASK (0x30U) +#define CAN_CTRL1_PN_PLFS_SHIFT (4U) +/*! PLFS - Payload Filtering Selection + * 0b00..Match payload contents to an exact target value + * 0b01..Match a payload value greater than or equal to a specified target value + * 0b10..Match a payload value smaller than or equal to a specified target value + * 0b11..Match upon a payload value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) + +#define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) +#define CAN_CTRL1_PN_NMATCH_SHIFT (8U) +/*! NMATCH - Number of Messages Matching the Same Filtering Criteria + * 0b00000001..Once + * 0b00000010..Twice + * 0b11111111..255 times + */ +#define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) + +#define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) +#define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) +/*! WUMF_MSK - Wake-up by Matching Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) + +#define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) +#define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) +/*! WTOF_MSK - Wake-up by Timeout Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) +/*! @} */ + +/*! @name CTRL2_PN - Pretended Networking Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) +#define CAN_CTRL2_PN_MATCHTO_SHIFT (0U) +/*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */ +#define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) +/*! @} */ + +/*! @name WU_MTC - Pretended Networking Wake-Up Match */ +/*! @{ */ + +#define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) +#define CAN_WU_MTC_MCOUNTER_SHIFT (8U) +/*! MCOUNTER - Number of Matches in Pretended Networking */ +#define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) + +#define CAN_WU_MTC_WUMF_MASK (0x10000U) +#define CAN_WU_MTC_WUMF_SHIFT (16U) +/*! WUMF - Wake-up by Match Flag + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) + +#define CAN_WU_MTC_WTOF_MASK (0x20000U) +#define CAN_WU_MTC_WTOF_SHIFT (17U) +/*! WTOF - Wake-up by Timeout Flag Bit + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) +/*! @} */ + +/*! @name FLT_ID1 - Pretended Networking ID Filter 1 */ +/*! @{ */ + +#define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID1_FLT_ID1_SHIFT (0U) +/*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */ +#define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK) + +#define CAN_FLT_ID1_FLT_RTR_MASK (0x20000000U) +#define CAN_FLT_ID1_FLT_RTR_SHIFT (29U) +/*! FLT_RTR - Remote Transmission Request Filter + * 0b0..Reject remote frame (accept data frame) + * 0b1..Accept remote frame + */ +#define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK) + +#define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) +#define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) +/*! FLT_IDE - ID Extended Filter + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) +/*! @} */ + +/*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */ +/*! @{ */ + +#define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) +#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT (0U) +/*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK) + +#define CAN_FLT_DLC_FLT_DLC_LO_MASK (0xF0000U) +#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT (16U) +/*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) +/*! @} */ + +/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */ +/*! @{ */ + +#define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL1_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data byte 3 */ +#define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) + +#define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL1_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data byte 2 */ +#define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) + +#define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL1_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data byte 1 */ +#define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) + +#define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL1_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data byte 0 */ +#define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL1_HI - Pretended Networking Payload High Filter 1 */ +/*! @{ */ + +#define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL1_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data byte 7 */ +#define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) + +#define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL1_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data byte 6 */ +#define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) + +#define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL1_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data byte 5 */ +#define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) + +#define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL1_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data byte 4 */ +#define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */ +/*! @{ */ + +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) +/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */ +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) + +#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) +#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) +/*! RTR_MSK - Remote Transmission Request Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) + +#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) +#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) +/*! IDE_MSK - ID Extended Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name WMB_CS - Wake-Up Message Buffer */ +/*! @{ */ + +#define CAN_WMB_CS_DLC_MASK (0xF0000U) +#define CAN_WMB_CS_DLC_SHIFT (16U) +/*! DLC - Length of Data in Bytes */ +#define CAN_WMB_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK) + +#define CAN_WMB_CS_RTR_MASK (0x100000U) +#define CAN_WMB_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request + * 0b0..Data + * 0b1..Remote + */ +#define CAN_WMB_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK) + +#define CAN_WMB_CS_IDE_MASK (0x200000U) +#define CAN_WMB_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended Bit + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_WMB_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK) + +#define CAN_WMB_CS_SRR_MASK (0x400000U) +#define CAN_WMB_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request + * 0b0..Dominant + * 0b1..Recessive + */ +#define CAN_WMB_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK) +/*! @} */ + +/* The count of CAN_WMB_CS */ +#define CAN_WMB_CS_COUNT (4U) + +/*! @name WMB_ID - Wake-Up Message Buffer for ID */ +/*! @{ */ + +#define CAN_WMB_ID_ID_MASK (0x1FFFFFFFU) +#define CAN_WMB_ID_ID_SHIFT (0U) +/*! ID - Received ID in Pretended Networking Mode */ +#define CAN_WMB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK) +/*! @} */ + +/* The count of CAN_WMB_ID */ +#define CAN_WMB_ID_COUNT (4U) + +/*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */ +/*! @{ */ + +#define CAN_WMB_D03_Data_byte_3_MASK (0xFFU) +#define CAN_WMB_D03_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_WMB_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK) + +#define CAN_WMB_D03_Data_byte_2_MASK (0xFF00U) +#define CAN_WMB_D03_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_WMB_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK) + +#define CAN_WMB_D03_Data_byte_1_MASK (0xFF0000U) +#define CAN_WMB_D03_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_WMB_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK) + +#define CAN_WMB_D03_Data_byte_0_MASK (0xFF000000U) +#define CAN_WMB_D03_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_WMB_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK) +/*! @} */ + +/* The count of CAN_WMB_D03 */ +#define CAN_WMB_D03_COUNT (4U) + +/*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */ +/*! @{ */ + +#define CAN_WMB_D47_Data_byte_7_MASK (0xFFU) +#define CAN_WMB_D47_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_WMB_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK) + +#define CAN_WMB_D47_Data_byte_6_MASK (0xFF00U) +#define CAN_WMB_D47_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_WMB_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK) + +#define CAN_WMB_D47_Data_byte_5_MASK (0xFF0000U) +#define CAN_WMB_D47_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_WMB_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK) + +#define CAN_WMB_D47_Data_byte_4_MASK (0xFF000000U) +#define CAN_WMB_D47_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_WMB_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK) +/*! @} */ + +/* The count of CAN_WMB_D47 */ +#define CAN_WMB_D47_COUNT (4U) + +/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ +/*! @{ */ + +#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) +#define CAN_EPRS_ENPRESDIV_SHIFT (0U) +/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ +#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) + +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) +#define CAN_EPRS_EDPRESDIV_SHIFT (16U) +/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ +#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) +/*! @} */ + +/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ +/*! @{ */ + +#define CAN_ENCBT_NTSEG1_MASK (0xFFU) +#define CAN_ENCBT_NTSEG1_SHIFT (0U) +/*! NTSEG1 - Nominal Time Segment 1 */ +#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) + +#define CAN_ENCBT_NTSEG2_MASK (0x7F000U) +#define CAN_ENCBT_NTSEG2_SHIFT (12U) +/*! NTSEG2 - Nominal Time Segment 2 */ +#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) + +#define CAN_ENCBT_NRJW_MASK (0x1FC00000U) +#define CAN_ENCBT_NRJW_SHIFT (22U) +/*! NRJW - Nominal Resynchronization Jump Width */ +#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) +/*! @} */ + +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ +/*! @{ */ + +#define CAN_EDCBT_DTSEG1_MASK (0x1FU) +#define CAN_EDCBT_DTSEG1_SHIFT (0U) +/*! DTSEG1 - Data Phase Segment 1 */ +#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) + +#define CAN_EDCBT_DTSEG2_MASK (0xF000U) +#define CAN_EDCBT_DTSEG2_SHIFT (12U) +/*! DTSEG2 - Data Phase Time Segment 2 */ +#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) + +#define CAN_EDCBT_DRJW_MASK (0x3C00000U) +#define CAN_EDCBT_DRJW_SHIFT (22U) +/*! DRJW - Data Phase Resynchronization Jump Width */ +#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) +/*! @} */ + +/*! @name ETDC - Enhanced Transceiver Delay Compensation */ +/*! @{ */ + +#define CAN_ETDC_ETDCVAL_MASK (0xFFU) +#define CAN_ETDC_ETDCVAL_SHIFT (0U) +/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ +#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) + +#define CAN_ETDC_ETDCFAIL_MASK (0x8000U) +#define CAN_ETDC_ETDCFAIL_SHIFT (15U) +/*! ETDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) + +#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) +#define CAN_ETDC_ETDCOFF_SHIFT (16U) +/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ +#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) + +#define CAN_ETDC_TDMDIS_MASK (0x40000000U) +#define CAN_ETDC_TDMDIS_SHIFT (30U) +/*! TDMDIS - Transceiver Delay Measurement Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) + +#define CAN_ETDC_ETDCEN_MASK (0x80000000U) +#define CAN_ETDC_ETDCEN_SHIFT (31U) +/*! ETDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) +/*! @} */ + +/*! @name FDCTRL - CAN FD Control */ +/*! @{ */ + +#define CAN_FDCTRL_TDCVAL_MASK (0x3FU) +#define CAN_FDCTRL_TDCVAL_SHIFT (0U) +/*! TDCVAL - Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) + +#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) +#define CAN_FDCTRL_TDCOFF_SHIFT (8U) +/*! TDCOFF - Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + +#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) +#define CAN_FDCTRL_TDCFAIL_SHIFT (14U) +/*! TDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) + +#define CAN_FDCTRL_TDCEN_MASK (0x8000U) +#define CAN_FDCTRL_TDCEN_SHIFT (15U) +/*! TDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) + +#define CAN_FDCTRL_MBDSR0_MASK (0x30000U) +#define CAN_FDCTRL_MBDSR0_SHIFT (16U) +/*! MBDSR0 - Message Buffer Data Size for Region 0 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + +#define CAN_FDCTRL_FDRATE_MASK (0x80000000U) +#define CAN_FDCTRL_FDRATE_SHIFT (31U) +/*! FDRATE - Bit Rate Switch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) +/*! @} */ + +/*! @name FDCBT - CAN FD Bit Timing */ +/*! @{ */ + +#define CAN_FDCBT_FPSEG2_MASK (0x7U) +#define CAN_FDCBT_FPSEG2_SHIFT (0U) +/*! FPSEG2 - Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + +#define CAN_FDCBT_FPSEG1_MASK (0xE0U) +#define CAN_FDCBT_FPSEG1_SHIFT (5U) +/*! FPSEG1 - Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + +#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) +#define CAN_FDCBT_FPROPSEG_SHIFT (10U) +/*! FPROPSEG - Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + +#define CAN_FDCBT_FRJW_MASK (0x70000U) +#define CAN_FDCBT_FRJW_SHIFT (16U) +/*! FRJW - Fast Resync Jump Width */ +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) +#define CAN_FDCBT_FPRESDIV_SHIFT (20U) +/*! FPRESDIV - Fast Prescaler Division Factor */ +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) +/*! @} */ + +/*! @name FDCRC - CAN FD CRC */ +/*! @{ */ + +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) +#define CAN_FDCRC_FD_TXCRC_SHIFT (0U) +/*! FD_TXCRC - Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24U) +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) +/*! @} */ + +/*! @name ERFCR - Enhanced RX FIFO Control */ +/*! @{ */ + +#define CAN_ERFCR_ERFWM_MASK (0x1FU) +#define CAN_ERFCR_ERFWM_SHIFT (0U) +/*! ERFWM - Enhanced RX FIFO Watermark */ +#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) + +#define CAN_ERFCR_NFE_MASK (0x3F00U) +#define CAN_ERFCR_NFE_SHIFT (8U) +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ +#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) + +#define CAN_ERFCR_NEXIF_MASK (0x7F0000U) +#define CAN_ERFCR_NEXIF_SHIFT (16U) +/*! NEXIF - Number of Extended ID Filter Elements */ +#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) + +#define CAN_ERFCR_DMALW_MASK (0x7C000000U) +#define CAN_ERFCR_DMALW_SHIFT (26U) +/*! DMALW - DMA Last Word */ +#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) + +#define CAN_ERFCR_ERFEN_MASK (0x80000000U) +#define CAN_ERFCR_ERFEN_SHIFT (31U) +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) +/*! @} */ + +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ +/*! @{ */ + +#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) +#define CAN_ERFIER_ERFDAIE_SHIFT (28U) +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) + +#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) +#define CAN_ERFIER_ERFWMIIE_SHIFT (29U) +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) + +#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) +#define CAN_ERFIER_ERFOVFIE_SHIFT (30U) +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) + +#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) +#define CAN_ERFIER_ERFUFWIE_SHIFT (31U) +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) +/*! @} */ + +/*! @name ERFSR - Enhanced RX FIFO Status */ +/*! @{ */ + +#define CAN_ERFSR_ERFEL_MASK (0x3FU) +#define CAN_ERFSR_ERFEL_SHIFT (0U) +/*! ERFEL - Enhanced RX FIFO Elements */ +#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) + +#define CAN_ERFSR_ERFF_MASK (0x10000U) +#define CAN_ERFSR_ERFF_SHIFT (16U) +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) + +#define CAN_ERFSR_ERFE_MASK (0x20000U) +#define CAN_ERFSR_ERFE_SHIFT (17U) +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) + +#define CAN_ERFSR_ERFCLR_MASK (0x8000000U) +#define CAN_ERFSR_ERFCLR_SHIFT (27U) +/*! ERFCLR - Enhanced RX FIFO Clear + * 0b0..No effect + * 0b1..Clear enhanced RX FIFO content + */ +#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) + +#define CAN_ERFSR_ERFDA_MASK (0x10000000U) +#define CAN_ERFSR_ERFDA_SHIFT (28U) +/*! ERFDA - Enhanced RX FIFO Data Available Flag + * 0b0..No such occurrence + * 0b1..At least one message stored in Enhanced RX FIFO + */ +#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) + +#define CAN_ERFSR_ERFWMI_MASK (0x20000000U) +#define CAN_ERFSR_ERFWMI_SHIFT (29U) +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag + * 0b0..No such occurrence + * 0b1..Number of messages in FIFO is greater than the watermark + */ +#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) + +#define CAN_ERFSR_ERFOVF_MASK (0x40000000U) +#define CAN_ERFSR_ERFOVF_SHIFT (30U) +/*! ERFOVF - Enhanced RX FIFO Overflow Flag + * 0b0..No such occurrence + * 0b1..Overflow + */ +#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) + +#define CAN_ERFSR_ERFUFW_MASK (0x80000000U) +#define CAN_ERFSR_ERFUFW_SHIFT (31U) +/*! ERFUFW - Enhanced RX FIFO Underflow Flag + * 0b0..No such occurrence + * 0b1..Underflow + */ +#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) +/*! @} */ + +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ +/*! @{ */ + +#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) +#define CAN_ERFFEL_FEL_SHIFT (0U) +/*! FEL - Filter Element Bits */ +#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CAN_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CDOG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CDOG.h new file mode 100644 index 000000000..c08745326 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CDOG.h @@ -0,0 +1,505 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for CDOG +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_CDOG.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for CDOG + * + * CMSIS Peripheral Access Layer for CDOG + */ + +#if !defined(PERI_CDOG_H_) +#define PERI_CDOG_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer + * @{ + */ + +/** CDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ + __IO uint32_t RELOAD; /**< Instruction Timer Reload Register, offset: 0x4 */ + __I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Status 1 Register, offset: 0x10 */ + __I uint32_t STATUS2; /**< Status 2 Register, offset: 0x14 */ + __IO uint32_t FLAGS; /**< Flags Register, offset: 0x18 */ + __IO uint32_t PERSISTENT; /**< Persistent Data Storage Register, offset: 0x1C */ + __O uint32_t START; /**< START Command Register, offset: 0x20 */ + __O uint32_t STOP; /**< STOP Command Register, offset: 0x24 */ + __O uint32_t RESTART; /**< RESTART Command Register, offset: 0x28 */ + __O uint32_t ADD; /**< ADD Command Register, offset: 0x2C */ + __O uint32_t ADD1; /**< ADD1 Command Register, offset: 0x30 */ + __O uint32_t ADD16; /**< ADD16 Command Register, offset: 0x34 */ + __O uint32_t ADD256; /**< ADD256 Command Register, offset: 0x38 */ + __O uint32_t SUB; /**< SUB Command Register, offset: 0x3C */ + __O uint32_t SUB1; /**< SUB1 Command Register, offset: 0x40 */ + __O uint32_t SUB16; /**< SUB16 Command Register, offset: 0x44 */ + __O uint32_t SUB256; /**< SUB256 Command Register, offset: 0x48 */ + __O uint32_t ASSERT16; /**< ASSERT16 Command Register, offset: 0x4C */ +} CDOG_Type; + +/* ---------------------------------------------------------------------------- + -- CDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Register_Masks CDOG Register Masks + * @{ + */ + +/*! @name CONTROL - Control Register */ +/*! @{ */ + +#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) +#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - Lock control + * 0b01..Locked + * 0b10..Unlocked + */ +#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) + +#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) +#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) +/*! TIMEOUT_CTRL - TIMEOUT fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) + +#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) +#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) +/*! MISCOMPARE_CTRL - MISCOMPARE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) + +#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) +#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) +/*! SEQUENCE_CTRL - SEQUENCE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) + +#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) +#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) +/*! STATE_CTRL - STATE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) + +#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) +#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) +/*! ADDRESS_CTRL - ADDRESS fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) + +#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) +#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) +/*! IRQ_PAUSE - IRQ pause control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) + +#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) +#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) +/*! DEBUG_HALT_CTRL - DEBUG_HALT control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) +/*! @} */ + +/*! @name RELOAD - Instruction Timer Reload Register */ +/*! @{ */ + +#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) +#define CDOG_RELOAD_RLOAD_SHIFT (0U) +/*! RLOAD - Instruction Timer reload value */ +#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) +/*! @} */ + +/*! @name INSTRUCTION_TIMER - Instruction Timer Register */ +/*! @{ */ + +#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) +#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) +/*! INSTIM - Current value of the Instruction Timer */ +#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) +/*! @} */ + +/*! @name STATUS - Status 1 Register */ +/*! @{ */ + +#define CDOG_STATUS_NUMTOF_MASK (0xFFU) +#define CDOG_STATUS_NUMTOF_SHIFT (0U) +/*! NUMTOF - Number of TIMEOUT faults (FLAGS[TIMEOUT_FLAG]) since the last POR */ +#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) + +#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) +#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) +/*! NUMMISCOMPF - Number of MISCOMPARE faults (FLAGS[MISCOMPARE_FLAG]) since the last POR */ +#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) + +#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) +#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) +/*! NUMILSEQF - Number of SEQUENCE faults (FLAGS[SEQUENCE_FLAG]) since the last POR */ +#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) + +#define CDOG_STATUS_CURST_MASK (0xF0000000U) +#define CDOG_STATUS_CURST_SHIFT (28U) +/*! CURST - Current State */ +#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) +/*! @} */ + +/*! @name STATUS2 - Status 2 Register */ +/*! @{ */ + +#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) +#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) +/*! NUMCNTF - Number of CONTROL faults (FLAGS[CONTROL_FLAG]) since the last POR */ +#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) + +#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) +#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) +/*! NUMILLSTF - Number of STATE faults (FLAGS[STATE_FLAG]) since the last POR */ +#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) + +#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) +#define CDOG_STATUS2_NUMILLA_SHIFT (16U) +/*! NUMILLA - Number of ADDRESS faults (FLAGS[ADDR_FLAG]) since the last POR */ +#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) +/*! @} */ + +/*! @name FLAGS - Flags Register */ +/*! @{ */ + +#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) +#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) +/*! TO_FLAG - TIMEOUT fault flag + * 0b0..A TIMEOUT fault has not occurred + * 0b1..A TIMEOUT fault has occurred + */ +#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) + +#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) +#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) +/*! MISCOM_FLAG - MISCOMPARE fault flag + * 0b0..A MISCOMPARE fault has not occurred + * 0b1..A MISCOMPARE fault has occurred + */ +#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) + +#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) +#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) +/*! SEQ_FLAG - SEQUENCE fault flag + * 0b0..A SEQUENCE fault has not occurred + * 0b1..A SEQUENCE fault has occurred + */ +#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) + +#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) +#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) +/*! CNT_FLAG - CONTROL fault flag + * 0b0..A CONTROL fault has not occurred + * 0b1..A CONTROL fault has occurred + */ +#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) + +#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) +#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) +/*! STATE_FLAG - STATE fault flag + * 0b0..A STATE fault has not occurred + * 0b1..A STATE fault has occurred + */ +#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) + +#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) +#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) +/*! ADDR_FLAG - ADDRESS fault flag + * 0b0..An ADDRESS fault has not occurred + * 0b1..An ADDRESS fault has occurred + */ +#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) + +#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) +#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) +/*! POR_FLAG - Power-on reset flag + * 0b0..A Power-on reset event has not occurred + * 0b1..A Power-on reset event has occurred + */ +#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) +/*! @} */ + +/*! @name PERSISTENT - Persistent Data Storage Register */ +/*! @{ */ + +#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) +#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) +/*! PERSIS - Persistent Storage */ +#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) +/*! @} */ + +/*! @name START - START Command Register */ +/*! @{ */ + +#define CDOG_START_STRT_MASK (0xFFFFFFFFU) +#define CDOG_START_STRT_SHIFT (0U) +/*! STRT - Start command */ +#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) +/*! @} */ + +/*! @name STOP - STOP Command Register */ +/*! @{ */ + +#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) +#define CDOG_STOP_STP_SHIFT (0U) +/*! STP - Stop command */ +#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) +/*! @} */ + +/*! @name RESTART - RESTART Command Register */ +/*! @{ */ + +#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) +#define CDOG_RESTART_RSTRT_SHIFT (0U) +/*! RSTRT - Restart command */ +#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) +/*! @} */ + +/*! @name ADD - ADD Command Register */ +/*! @{ */ + +#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) +#define CDOG_ADD_AD_SHIFT (0U) +/*! AD - ADD Write Value */ +#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) +/*! @} */ + +/*! @name ADD1 - ADD1 Command Register */ +/*! @{ */ + +#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) +#define CDOG_ADD1_AD1_SHIFT (0U) +/*! AD1 - ADD 1 */ +#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) +/*! @} */ + +/*! @name ADD16 - ADD16 Command Register */ +/*! @{ */ + +#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) +#define CDOG_ADD16_AD16_SHIFT (0U) +/*! AD16 - ADD 16 */ +#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) +/*! @} */ + +/*! @name ADD256 - ADD256 Command Register */ +/*! @{ */ + +#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) +#define CDOG_ADD256_AD256_SHIFT (0U) +/*! AD256 - ADD 256 */ +#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) +/*! @} */ + +/*! @name SUB - SUB Command Register */ +/*! @{ */ + +#define CDOG_SUB_SB_MASK (0xFFFFFFFFU) +#define CDOG_SUB_SB_SHIFT (0U) +/*! SB - Subtract Write Value */ +#define CDOG_SUB_SB(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK) +/*! @} */ + +/*! @name SUB1 - SUB1 Command Register */ +/*! @{ */ + +#define CDOG_SUB1_SB1_MASK (0xFFFFFFFFU) +#define CDOG_SUB1_SB1_SHIFT (0U) +/*! SB1 - Subtract 1 */ +#define CDOG_SUB1_SB1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK) +/*! @} */ + +/*! @name SUB16 - SUB16 Command Register */ +/*! @{ */ + +#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) +#define CDOG_SUB16_SB16_SHIFT (0U) +/*! SB16 - Subtract 16 */ +#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) +/*! @} */ + +/*! @name SUB256 - SUB256 Command Register */ +/*! @{ */ + +#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) +#define CDOG_SUB256_SB256_SHIFT (0U) +/*! SB256 - Subtract 256 */ +#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) +/*! @} */ + +/*! @name ASSERT16 - ASSERT16 Command Register */ +/*! @{ */ + +#define CDOG_ASSERT16_AST16_MASK (0xFFFFFFFFU) +#define CDOG_ASSERT16_AST16_SHIFT (0U) +/*! AST16 - ASSERT16 Command */ +#define CDOG_ASSERT16_AST16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CDOG_Register_Masks */ + + +/*! + * @} + */ /* end of group CDOG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CDOG_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CMC.h new file mode 100644 index 000000000..98cd746b1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CMC.h @@ -0,0 +1,848 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for CMC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_CMC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for CMC + * + * CMSIS Peripheral Access Layer for CMC + */ + +#if !defined(PERI_CMC_H_) +#define PERI_CMC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer + * @{ + */ + +/** CMC - Size of Registers Arrays */ +#define CMC_PMCTRL_COUNT 1u +#define CMC_MR_COUNT 1u +#define CMC_FM_COUNT 1u + +/** CMC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CKCTRL; /**< Clock Control, offset: 0x10 */ + __IO uint32_t CKSTAT; /**< Clock Status, offset: 0x14 */ + __IO uint32_t PMPROT; /**< Power Mode Protection, offset: 0x18 */ + __IO uint32_t GPMCTRL; /**< Global Power Mode Control, offset: 0x1C */ + __IO uint32_t PMCTRL[CMC_PMCTRL_COUNT]; /**< Power Mode Control, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[92]; + __I uint32_t SRS; /**< System Reset Status, offset: 0x80 */ + __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x84 */ + __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x88 */ + __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x8C */ + __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x90 */ + uint8_t RESERVED_2[12]; + __IO uint32_t MR[CMC_MR_COUNT]; /**< Mode, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t FM[CMC_FM_COUNT]; /**< Force Mode, array offset: 0xB0, array step: 0x4 */ + uint8_t RESERVED_4[44]; + __IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */ + uint8_t RESERVED_5[44]; + __IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DBGCTL; /**< Debug Control, offset: 0x120 */ +} CMC_Type; + +/* ---------------------------------------------------------------------------- + -- CMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Register_Masks CMC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define CMC_VERID_FEATURE_MASK (0xFFFFU) +#define CMC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define CMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK) + +#define CMC_VERID_MINOR_MASK (0xFF0000U) +#define CMC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define CMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK) + +#define CMC_VERID_MAJOR_MASK (0xFF000000U) +#define CMC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define CMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CKCTRL - Clock Control */ +/*! @{ */ + +#define CMC_CKCTRL_CKMODE_MASK (0xFU) +#define CMC_CKCTRL_CKMODE_SHIFT (0U) +/*! CKMODE - Clocking Mode + * 0b0000..Core clock is on + * 0b0001..Core clock is off + * 0b1111..Core, platform, and peripheral clocks are off, and core enters Low-Power mode + */ +#define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK) + +#define CMC_CKCTRL_LOCK_MASK (0x80000000U) +#define CMC_CKCTRL_LOCK_SHIFT (31U) +/*! LOCK - Lock + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_CKCTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK) +/*! @} */ + +/*! @name CKSTAT - Clock Status */ +/*! @{ */ + +#define CMC_CKSTAT_CKMODE_MASK (0xFU) +#define CMC_CKSTAT_CKMODE_SHIFT (0U) +/*! CKMODE - Low Power Status + * 0b0000..Core clock is on + * 0b0001..Core clock is off + * 0b1111..Core, platform, and peripheral clocks are off, and core enters Low-Power mode + */ +#define CMC_CKSTAT_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK) + +#define CMC_CKSTAT_WAKEUP_MASK (0xFF00U) +#define CMC_CKSTAT_WAKEUP_SHIFT (8U) +/*! WAKEUP - Wake-up Source */ +#define CMC_CKSTAT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK) + +#define CMC_CKSTAT_VALID_MASK (0x80000000U) +#define CMC_CKSTAT_VALID_SHIFT (31U) +/*! VALID - Clock Status Valid + * 0b0..Core clock not gated + * 0b1..Core clock was gated due to Low-Power mode entry + */ +#define CMC_CKSTAT_VALID(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK) +/*! @} */ + +/*! @name PMPROT - Power Mode Protection */ +/*! @{ */ + +#define CMC_PMPROT_LPMODE_MASK (0xFU) +#define CMC_PMPROT_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Not allowed + * 0b0001..Allowed + * 0b0010..Allowed + * 0b0011..Allowed + * 0b0100..Allowed + * 0b0101..Allowed + * 0b0110..Allowed + * 0b0111..Allowed + * 0b1000..Allowed + * 0b1001..Allowed + * 0b1010..Allowed + * 0b1011..Allowed + * 0b1100..Allowed + * 0b1101..Allowed + * 0b1110..Allowed + * 0b1111..Allowed + */ +#define CMC_PMPROT_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK) + +#define CMC_PMPROT_LOCK_MASK (0x80000000U) +#define CMC_PMPROT_LOCK_SHIFT (31U) +/*! LOCK - Lock Register + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_PMPROT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK) +/*! @} */ + +/*! @name GPMCTRL - Global Power Mode Control */ +/*! @{ */ + +#define CMC_GPMCTRL_LPMODE_MASK (0xFU) +#define CMC_GPMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode */ +#define CMC_GPMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK) +/*! @} */ + +/*! @name PMCTRL - Power Mode Control */ +/*! @{ */ + +#define CMC_PMCTRL_LPMODE_MASK (0xFU) +#define CMC_PMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Active/Sleep + * 0b0001..Deep Sleep + * 0b0011..Power Down + * 0b0111..Reserved + * 0b1111..Deep-Power Down + */ +#define CMC_PMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK) +/*! @} */ + +/*! @name SRS - System Reset Status */ +/*! @{ */ + +#define CMC_SRS_WAKEUP_MASK (0x1U) +#define CMC_SRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK) + +#define CMC_SRS_POR_MASK (0x2U) +#define CMC_SRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK) + +#define CMC_SRS_VD_MASK (0x4U) +#define CMC_SRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK) + +#define CMC_SRS_WARM_MASK (0x10U) +#define CMC_SRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK) + +#define CMC_SRS_FATAL_MASK (0x20U) +#define CMC_SRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK) + +#define CMC_SRS_PIN_MASK (0x100U) +#define CMC_SRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK) + +#define CMC_SRS_DAP_MASK (0x200U) +#define CMC_SRS_DAP_SHIFT (9U) +/*! DAP - Debug Access Port Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK) + +#define CMC_SRS_RSTACK_MASK (0x400U) +#define CMC_SRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK) + +#define CMC_SRS_LPACK_MASK (0x800U) +#define CMC_SRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK) + +#define CMC_SRS_SCG_MASK (0x1000U) +#define CMC_SRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK) + +#define CMC_SRS_WWDT0_MASK (0x2000U) +#define CMC_SRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK) + +#define CMC_SRS_SW_MASK (0x4000U) +#define CMC_SRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK) + +#define CMC_SRS_LOCKUP_MASK (0x8000U) +#define CMC_SRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK) + +#define CMC_SRS_CDOG0_MASK (0x4000000U) +#define CMC_SRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK) + +#define CMC_SRS_CDOG1_MASK (0x8000000U) +#define CMC_SRS_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG1_SHIFT)) & CMC_SRS_CDOG1_MASK) + +#define CMC_SRS_JTAG_MASK (0x10000000U) +#define CMC_SRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK) + +#define CMC_SRS_TAMPER_MASK (0x80000000U) +#define CMC_SRS_TAMPER_SHIFT (31U) +/*! TAMPER - Tamper Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_TAMPER_SHIFT)) & CMC_SRS_TAMPER_MASK) +/*! @} */ + +/*! @name RPC - Reset Pin Control */ +/*! @{ */ + +#define CMC_RPC_FILTCFG_MASK (0x1FU) +#define CMC_RPC_FILTCFG_SHIFT (0U) +/*! FILTCFG - Reset Filter Configuration */ +#define CMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK) + +#define CMC_RPC_FILTEN_MASK (0x100U) +#define CMC_RPC_FILTEN_SHIFT (8U) +/*! FILTEN - Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK) + +#define CMC_RPC_LPFEN_MASK (0x200U) +#define CMC_RPC_LPFEN_SHIFT (9U) +/*! LPFEN - Low-Power Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK) +/*! @} */ + +/*! @name SSRS - Sticky System Reset Status */ +/*! @{ */ + +#define CMC_SSRS_WAKEUP_MASK (0x1U) +#define CMC_SSRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK) + +#define CMC_SSRS_POR_MASK (0x2U) +#define CMC_SSRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK) + +#define CMC_SSRS_VD_MASK (0x4U) +#define CMC_SSRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK) + +#define CMC_SSRS_WARM_MASK (0x10U) +#define CMC_SSRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK) + +#define CMC_SSRS_FATAL_MASK (0x20U) +#define CMC_SSRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK) + +#define CMC_SSRS_PIN_MASK (0x100U) +#define CMC_SSRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK) + +#define CMC_SSRS_DAP_MASK (0x200U) +#define CMC_SSRS_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK) + +#define CMC_SSRS_RSTACK_MASK (0x400U) +#define CMC_SSRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK) + +#define CMC_SSRS_LPACK_MASK (0x800U) +#define CMC_SSRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK) + +#define CMC_SSRS_SCG_MASK (0x1000U) +#define CMC_SSRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK) + +#define CMC_SSRS_WWDT0_MASK (0x2000U) +#define CMC_SSRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK) + +#define CMC_SSRS_SW_MASK (0x4000U) +#define CMC_SSRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK) + +#define CMC_SSRS_LOCKUP_MASK (0x8000U) +#define CMC_SSRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK) + +#define CMC_SSRS_CDOG0_MASK (0x4000000U) +#define CMC_SSRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK) + +#define CMC_SSRS_CDOG1_MASK (0x8000000U) +#define CMC_SSRS_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG1_SHIFT)) & CMC_SSRS_CDOG1_MASK) + +#define CMC_SSRS_JTAG_MASK (0x10000000U) +#define CMC_SSRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK) + +#define CMC_SSRS_TAMPER_MASK (0x80000000U) +#define CMC_SSRS_TAMPER_SHIFT (31U) +/*! TAMPER - Tamper Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_TAMPER_SHIFT)) & CMC_SSRS_TAMPER_MASK) +/*! @} */ + +/*! @name SRIE - System Reset Interrupt Enable */ +/*! @{ */ + +#define CMC_SRIE_PIN_MASK (0x100U) +#define CMC_SRIE_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK) + +#define CMC_SRIE_DAP_MASK (0x200U) +#define CMC_SRIE_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK) + +#define CMC_SRIE_LPACK_MASK (0x800U) +#define CMC_SRIE_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK) + +#define CMC_SRIE_SCG_MASK (0x1000U) +#define CMC_SRIE_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK) + +#define CMC_SRIE_WWDT0_MASK (0x2000U) +#define CMC_SRIE_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK) + +#define CMC_SRIE_SW_MASK (0x4000U) +#define CMC_SRIE_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK) + +#define CMC_SRIE_LOCKUP_MASK (0x8000U) +#define CMC_SRIE_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK) + +#define CMC_SRIE_CDOG0_MASK (0x4000000U) +#define CMC_SRIE_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK) + +#define CMC_SRIE_CDOG1_MASK (0x8000000U) +#define CMC_SRIE_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG1_SHIFT)) & CMC_SRIE_CDOG1_MASK) +/*! @} */ + +/*! @name SRIF - System Reset Interrupt Flag */ +/*! @{ */ + +#define CMC_SRIF_PIN_MASK (0x100U) +#define CMC_SRIF_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK) + +#define CMC_SRIF_DAP_MASK (0x200U) +#define CMC_SRIF_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK) + +#define CMC_SRIF_LPACK_MASK (0x800U) +#define CMC_SRIF_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK) + +#define CMC_SRIF_WWDT0_MASK (0x2000U) +#define CMC_SRIF_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK) + +#define CMC_SRIF_SW_MASK (0x4000U) +#define CMC_SRIF_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK) + +#define CMC_SRIF_LOCKUP_MASK (0x8000U) +#define CMC_SRIF_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK) + +#define CMC_SRIF_CDOG0_MASK (0x4000000U) +#define CMC_SRIF_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK) + +#define CMC_SRIF_CDOG1_MASK (0x8000000U) +#define CMC_SRIF_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG1_SHIFT)) & CMC_SRIF_CDOG1_MASK) +/*! @} */ + +/*! @name MR - Mode */ +/*! @{ */ + +#define CMC_MR_ISPMODE_n_MASK (0x1U) +#define CMC_MR_ISPMODE_n_SHIFT (0U) +/*! ISPMODE_n - In System Programming Mode */ +#define CMC_MR_ISPMODE_n(x) (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK) +/*! @} */ + +/*! @name FM - Force Mode */ +/*! @{ */ + +#define CMC_FM_FORCECFG_MASK (0x1U) +#define CMC_FM_FORCECFG_SHIFT (0U) +/*! FORCECFG - Boot Configuration + * 0b0..No effect + * 0b1..Asserts + */ +#define CMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK) +/*! @} */ + +/*! @name FLASHCR - Flash Control */ +/*! @{ */ + +#define CMC_FLASHCR_FLASHDIS_MASK (0x1U) +#define CMC_FLASHCR_FLASHDIS_SHIFT (0U) +/*! FLASHDIS - Flash Disable + * 0b0..No effect + * 0b1..Flash memory is disabled + */ +#define CMC_FLASHCR_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK) + +#define CMC_FLASHCR_FLASHDOZE_MASK (0x2U) +#define CMC_FLASHCR_FLASHDOZE_SHIFT (1U) +/*! FLASHDOZE - Flash Doze + * 0b0..No effect + * 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0) + */ +#define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK) + +#define CMC_FLASHCR_FLASHWAKE_MASK (0x4U) +#define CMC_FLASHCR_FLASHWAKE_SHIFT (2U) +/*! FLASHWAKE - Flash Wake + * 0b0..No effect + * 0b1..Flash memory is not disabled during flash memory accesses + */ +#define CMC_FLASHCR_FLASHWAKE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHWAKE_SHIFT)) & CMC_FLASHCR_FLASHWAKE_MASK) +/*! @} */ + +/*! @name CORECTL - Core Control */ +/*! @{ */ + +#define CMC_CORECTL_NPIE_MASK (0x1U) +#define CMC_CORECTL_NPIE_SHIFT (0U) +/*! NPIE - Non-maskable Pin Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_CORECTL_NPIE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK) +/*! @} */ + +/*! @name DBGCTL - Debug Control */ +/*! @{ */ + +#define CMC_DBGCTL_SOD_MASK (0x1U) +#define CMC_DBGCTL_SOD_SHIFT (0U) +/*! SOD - Sleep Or Debug + * 0b0..Remains enabled + * 0b1..Disabled + */ +#define CMC_DBGCTL_SOD(x) (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMC_Register_Masks */ + + +/*! + * @} + */ /* end of group CMC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CMC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CRC.h new file mode 100644 index 000000000..25495ee8c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CRC.h @@ -0,0 +1,437 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for CRC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_CRC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for CRC + * + * CMSIS Peripheral Access Layer for CRC + */ + +#if !defined(PERI_CRC_H_) +#define PERI_CRC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ + } ACCESS8BIT; + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< Data, offset: 0x0 */ + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ + } GPOLY_ACCESS8BIT; + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< Polynomial, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ + } CTRL_ACCESS8BIT; + __IO uint32_t CTRL; /**< Control, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATALL - CRC_DATALL register */ +/*! @{ */ + +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) +/*! @} */ + +/*! @name DATALU - CRC_DATALU register */ +/*! @{ */ + +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) +/*! @} */ + +/*! @name DATAHL - CRC_DATAHL register */ +/*! @{ */ + +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) +/*! @} */ + +/*! @name DATAHU - CRC_DATAHU register */ +/*! @{ */ + +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) +/*! @} */ + +/*! @name DATAL - CRC_DATAL register */ +/*! @{ */ + +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) +/*! @} */ + +/*! @name DATAH - CRC_DATAH register */ +/*! @{ */ + +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +/*! LL - Lower Part of Low Byte */ +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) + +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +/*! LU - Upper Part of Low Byte */ +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) + +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +/*! HL - Lower Part of High Byte */ +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) + +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +/*! HU - Upper Part of High Byte */ +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) +/*! @} */ + +/*! @name GPOLYLL - CRC_GPOLYLL register */ +/*! @{ */ + +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) +/*! @} */ + +/*! @name GPOLYLU - CRC_GPOLYLU register */ +/*! @{ */ + +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) +/*! @} */ + +/*! @name GPOLYHL - CRC_GPOLYHL register */ +/*! @{ */ + +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) +/*! @} */ + +/*! @name GPOLYHU - CRC_GPOLYHU register */ +/*! @{ */ + +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) +/*! @} */ + +/*! @name GPOLYL - CRC_GPOLYL register */ +/*! @{ */ + +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) +/*! @} */ + +/*! @name GPOLYH - CRC_GPOLYH register */ +/*! @{ */ + +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) +/*! @} */ + +/*! @name GPOLY - Polynomial */ +/*! @{ */ + +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +/*! LOW - Low Half-Word */ +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) + +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +/*! HIGH - High Half-Word */ +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) +/*! @} */ + +/*! @name CTRLHU - CRC_CTRLHU register */ +/*! @{ */ + +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) + +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) + +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) + +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) + +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) + +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) + +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) + +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) + +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CRC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CTIMER.h new file mode 100644 index 000000000..62f2d1c66 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_CTIMER.h @@ -0,0 +1,714 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for CTIMER +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_CTIMER.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for CTIMER + * + * CMSIS Peripheral Access Layer for CTIMER + */ + +#if !defined(PERI_CTIMER_H_) +#define PERI_CTIMER_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Size of Registers Arrays */ +#define CTIMER_MR_COUNT 4u +#define CTIMER_CR_COUNT 4u +#define CTIMER_MSR_COUNT 4u + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt, offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control, offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control, offset: 0x14 */ + __IO uint32_t MR[CTIMER_MR_COUNT]; /**< Match, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control, offset: 0x28 */ + __I uint32_t CR[CTIMER_CR_COUNT]; /**< Capture, array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match, offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control, offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control, offset: 0x74 */ + __IO uint32_t MSR[CTIMER_MSR_COUNT]; /**< Match Shadow, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt Flag for Match Channel 0 Event */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt Flag for Match Channel 1 Event */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt Flag for Match Channel 2 Event */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt Flag for Match Channel 3 Event */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt Flag for Capture Channel 0 Event */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt Flag for Capture Channel 1 Event */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt Flag for Capture Channel 2 Event */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt Flag for Capture Channel 3 Event */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) + +#define CTIMER_TCR_AGCEN_MASK (0x10U) +#define CTIMER_TCR_AGCEN_SHIFT (4U) +/*! AGCEN - Allow Global Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK) + +#define CTIMER_TCR_ATCEN_MASK (0x20U) +#define CTIMER_TCR_ATCEN_SHIFT (5U) +/*! ATCEN - Allow Trigger Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer Counter Value */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale Reload Value */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale Counter Value */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer Counter Match Value */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/*! @name CCR - Capture Control */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate Interrupt on Channel 0 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate Interrupt on Channel 1 Capture Event + * 0b0..Does not generates + * 0b1..Generates + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate Interrupt on Channel 2 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate Interrupt on Channel 3 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer Counter Capture Value */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/*! @name EMR - External Match */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter Timer Mode + * 0b00..Timer mode + * 0b01..Counter mode rising edge + * 0b10..Counter mode falling edge + * 0b11..Counter mode dual edge + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select + * 0b00..Channel 0, CAPn[0] for CTIMERn + * 0b01..Channel 1, CAPn[1] for CTIMERn + * 0b10..Channel 2, CAPn[2] for CTIMERn + * 0b11..Channel 3, CAPn[3] for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Capture Channel Enable */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge Select + * 0b000..Capture channel 0 rising edge + * 0b001..Capture channel 0 falling edge + * 0b010..Capture channel 1 rising edge + * 0b011..Capture channel 1 falling edge + * 0b100..Capture channel 2 rising edge + * 0b101..Capture channel 2 falling edge + * 0b110..Capture channel 3 rising edge + * 0b111..Capture channel 3 falling edge + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM Mode Enable for Channel 0 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM Mode Enable for Channel 1 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM Mode Enable for Channel 2 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM Mode Enable for Channel 3 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow */ +/*! @{ */ + +#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) +/*! MATCH_SHADOW - Timer Counter Match Shadow Value */ +#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_CTIMER_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_DEBUGMAILBOX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_DEBUGMAILBOX.h new file mode 100644 index 000000000..7187c6c1f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_DEBUGMAILBOX.h @@ -0,0 +1,258 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for DEBUGMAILBOX +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_DEBUGMAILBOX.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for DEBUGMAILBOX + * + * CMSIS Peripheral Access Layer for DEBUGMAILBOX + */ + +#if !defined(PERI_DEBUGMAILBOX_H_) +#define PERI_DEBUGMAILBOX_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- DEBUGMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEBUGMAILBOX_Peripheral_Access_Layer DEBUGMAILBOX Peripheral Access Layer + * @{ + */ + +/** DEBUGMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< Command and Status Word, offset: 0x0 */ + __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification, offset: 0xFC */ +} DEBUGMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DEBUGMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEBUGMAILBOX_Register_Masks DEBUGMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - Command and Status Word */ +/*! @{ */ + +#define DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Resynchronization Request + * 0b0..No request + * 0b1..Request for resynchronization + */ +#define DEBUGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DEBUGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request Pending + * 0b0..No request pending + * 0b1..Request for resynchronization pending + */ +#define DEBUGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGMAILBOX_CSW_REQ_PENDING_MASK) + +#define DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - DBGMB Overrun Error + * 0b0..No overrun + * 0b1..Overrun occurred + */ +#define DEBUGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB Overrun Error + * 0b0..No overrun + * 0b1..Overrun occurred + */ +#define DEBUGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DEBUGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset + * 0b0..No effect + * 0b1..Reset + */ +#define DEBUGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGMAILBOX_CSW_SOFT_RESET_MASK) + +#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Chip Reset Request + * 0b0..No effect + * 0b1..Reset + */ +#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - Request Value */ +/*! @{ */ + +#define DEBUGMAILBOX_REQUEST_REQUEST_MASK (0xFFFFFFFFU) +#define DEBUGMAILBOX_REQUEST_REQUEST_SHIFT (0U) +/*! REQUEST - Request Value */ +#define DEBUGMAILBOX_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGMAILBOX_REQUEST_REQUEST_MASK) +/*! @} */ + +/*! @name RETURN - Return Value */ +/*! @{ */ + +#define DEBUGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DEBUGMAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - Return Value */ +#define DEBUGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_RETURN_RET_SHIFT)) & DEBUGMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define DEBUGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DEBUGMAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification Value */ +#define DEBUGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_ID_ID_SHIFT)) & DEBUGMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DEBUGMAILBOX_Register_Masks */ + + +/*! + * @} + */ /* end of group DEBUGMAILBOX_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_DEBUGMAILBOX_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_DIGTMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_DIGTMP.h new file mode 100644 index 000000000..7b4adc27a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_DIGTMP.h @@ -0,0 +1,959 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for DIGTMP +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_DIGTMP.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for DIGTMP + * + * CMSIS Peripheral Access Layer for DIGTMP + */ + +#if !defined(PERI_DIGTMP_H_) +#define PERI_DIGTMP_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- DIGTMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DIGTMP_Peripheral_Access_Layer DIGTMP Peripheral Access Layer + * @{ + */ + +/** DIGTMP - Size of Registers Arrays */ +#define DIGTMP_PGFR_COUNT 6u + +/** DIGTMP - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t LR; /**< Lock, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t TSR; /**< Tamper Seconds, offset: 0x20 */ + __IO uint32_t TER; /**< Tamper Enable, offset: 0x24 */ + uint8_t RESERVED_1[4]; + __IO uint32_t PPR; /**< Pin Polarity, offset: 0x2C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PGFR[DIGTMP_PGFR_COUNT]; /**< Pin Glitch Filter, array offset: 0x40, array step: 0x4 */ +} DIGTMP_Type; + +/* ---------------------------------------------------------------------------- + -- DIGTMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DIGTMP_Register_Masks DIGTMP Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define DIGTMP_CR_SWR_MASK (0x1U) +#define DIGTMP_CR_SWR_SHIFT (0U) +/*! SWR - Software Reset + * 0b0..No effect + * 0b1..Perform a software reset + */ +#define DIGTMP_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_SWR_SHIFT)) & DIGTMP_CR_SWR_MASK) + +#define DIGTMP_CR_DEN_MASK (0x2U) +#define DIGTMP_CR_DEN_SHIFT (1U) +/*! DEN - Digital Tamper Enable + * 0b0..Disables TDET clock and prescaler + * 0b1..Enables TDET clock and prescaler + */ +#define DIGTMP_CR_DEN(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DEN_SHIFT)) & DIGTMP_CR_DEN_MASK) + +#define DIGTMP_CR_TFSR_MASK (0x4U) +#define DIGTMP_CR_TFSR_SHIFT (2U) +/*! TFSR - Tamper Force System Reset + * 0b0..Do not force chip reset + * 0b1..Force chip reset + */ +#define DIGTMP_CR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_TFSR_SHIFT)) & DIGTMP_CR_TFSR_MASK) + +#define DIGTMP_CR_UM_MASK (0x8U) +#define DIGTMP_CR_UM_SHIFT (3U) +/*! UM - Update Mode + * 0b0..No effect + * 0b1..Allows the clearing of interrupts + */ +#define DIGTMP_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_UM_SHIFT)) & DIGTMP_CR_UM_MASK) + +#define DIGTMP_CR_DISTAM_MASK (0x100U) +#define DIGTMP_CR_DISTAM_SHIFT (8U) +/*! DISTAM - Disable Prescaler On Tamper + * 0b0..No effect + * 0b1..Automatically disables the prescaler after tamper detection + */ +#define DIGTMP_CR_DISTAM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DISTAM_SHIFT)) & DIGTMP_CR_DISTAM_MASK) + +#define DIGTMP_CR_DPR_MASK (0xFFFE0000U) +#define DIGTMP_CR_DPR_SHIFT (17U) +/*! DPR - Digital Tamper Prescaler */ +#define DIGTMP_CR_DPR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DPR_SHIFT)) & DIGTMP_CR_DPR_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define DIGTMP_SR_DTF_MASK (0x1U) +#define DIGTMP_SR_DTF_SHIFT (0U) +/*! DTF - Digital Tamper Flag + * 0b0..TDET tampering not detected + * 0b1..TDET tampering detected + */ +#define DIGTMP_SR_DTF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_DTF_SHIFT)) & DIGTMP_SR_DTF_MASK) + +#define DIGTMP_SR_TAF_MASK (0x2U) +#define DIGTMP_SR_TAF_SHIFT (1U) +/*! TAF - Tamper Acknowledge Flag + * 0b0..Digital Tamper Flag (SR[DTF]) is clear or chip reset has not occurred after Digital Tamper Flag (SR[DTF]) was set. + * 0b1..Chip reset has occurred after Digital Tamper Flag (SR[DTF]) was set. + */ +#define DIGTMP_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TAF_SHIFT)) & DIGTMP_SR_TAF_MASK) + +#define DIGTMP_SR_TIF0_MASK (0x4U) +#define DIGTMP_SR_TIF0_SHIFT (2U) +/*! TIF0 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF0_SHIFT)) & DIGTMP_SR_TIF0_MASK) + +#define DIGTMP_SR_TIF1_MASK (0x8U) +#define DIGTMP_SR_TIF1_SHIFT (3U) +/*! TIF1 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF1_SHIFT)) & DIGTMP_SR_TIF1_MASK) + +#define DIGTMP_SR_TIF2_MASK (0x10U) +#define DIGTMP_SR_TIF2_SHIFT (4U) +/*! TIF2 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF2_SHIFT)) & DIGTMP_SR_TIF2_MASK) + +#define DIGTMP_SR_TIF3_MASK (0x20U) +#define DIGTMP_SR_TIF3_SHIFT (5U) +/*! TIF3 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF3_SHIFT)) & DIGTMP_SR_TIF3_MASK) + +#define DIGTMP_SR_TIF4_MASK (0x40U) +#define DIGTMP_SR_TIF4_SHIFT (6U) +/*! TIF4 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF4_SHIFT)) & DIGTMP_SR_TIF4_MASK) + +#define DIGTMP_SR_TIF5_MASK (0x80U) +#define DIGTMP_SR_TIF5_SHIFT (7U) +/*! TIF5 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF5_SHIFT)) & DIGTMP_SR_TIF5_MASK) + +#define DIGTMP_SR_TIF6_MASK (0x100U) +#define DIGTMP_SR_TIF6_SHIFT (8U) +/*! TIF6 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF6_SHIFT)) & DIGTMP_SR_TIF6_MASK) + +#define DIGTMP_SR_TIF7_MASK (0x200U) +#define DIGTMP_SR_TIF7_SHIFT (9U) +/*! TIF7 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF7_SHIFT)) & DIGTMP_SR_TIF7_MASK) + +#define DIGTMP_SR_TIF8_MASK (0x400U) +#define DIGTMP_SR_TIF8_SHIFT (10U) +/*! TIF8 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF8_SHIFT)) & DIGTMP_SR_TIF8_MASK) + +#define DIGTMP_SR_TIF9_MASK (0x800U) +#define DIGTMP_SR_TIF9_SHIFT (11U) +/*! TIF9 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF9_SHIFT)) & DIGTMP_SR_TIF9_MASK) + +#define DIGTMP_SR_TIF10_MASK (0x1000U) +#define DIGTMP_SR_TIF10_SHIFT (12U) +/*! TIF10 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF10(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF10_SHIFT)) & DIGTMP_SR_TIF10_MASK) + +#define DIGTMP_SR_TPF0_MASK (0x10000U) +#define DIGTMP_SR_TPF0_SHIFT (16U) +/*! TPF0 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF0_SHIFT)) & DIGTMP_SR_TPF0_MASK) + +#define DIGTMP_SR_TPF1_MASK (0x20000U) +#define DIGTMP_SR_TPF1_SHIFT (17U) +/*! TPF1 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF1_SHIFT)) & DIGTMP_SR_TPF1_MASK) + +#define DIGTMP_SR_TPF2_MASK (0x40000U) +#define DIGTMP_SR_TPF2_SHIFT (18U) +/*! TPF2 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF2_SHIFT)) & DIGTMP_SR_TPF2_MASK) + +#define DIGTMP_SR_TPF3_MASK (0x80000U) +#define DIGTMP_SR_TPF3_SHIFT (19U) +/*! TPF3 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF3_SHIFT)) & DIGTMP_SR_TPF3_MASK) + +#define DIGTMP_SR_TPF4_MASK (0x100000U) +#define DIGTMP_SR_TPF4_SHIFT (20U) +/*! TPF4 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF4_SHIFT)) & DIGTMP_SR_TPF4_MASK) + +#define DIGTMP_SR_TPF5_MASK (0x200000U) +#define DIGTMP_SR_TPF5_SHIFT (21U) +/*! TPF5 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF5_SHIFT)) & DIGTMP_SR_TPF5_MASK) +/*! @} */ + +/*! @name LR - Lock */ +/*! @{ */ + +#define DIGTMP_LR_CRL_MASK (0x10U) +#define DIGTMP_LR_CRL_SHIFT (4U) +/*! CRL - Control Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_CRL_SHIFT)) & DIGTMP_LR_CRL_MASK) + +#define DIGTMP_LR_SRL_MASK (0x20U) +#define DIGTMP_LR_SRL_SHIFT (5U) +/*! SRL - Status Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_SRL_SHIFT)) & DIGTMP_LR_SRL_MASK) + +#define DIGTMP_LR_LRL_MASK (0x40U) +#define DIGTMP_LR_LRL_SHIFT (6U) +/*! LRL - Lock Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_LRL_SHIFT)) & DIGTMP_LR_LRL_MASK) + +#define DIGTMP_LR_IEL_MASK (0x80U) +#define DIGTMP_LR_IEL_SHIFT (7U) +/*! IEL - Interrupt Enable Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_IEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_IEL_SHIFT)) & DIGTMP_LR_IEL_MASK) + +#define DIGTMP_LR_TSL_MASK (0x100U) +#define DIGTMP_LR_TSL_SHIFT (8U) +/*! TSL - Tamper Seconds Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_TSL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TSL_SHIFT)) & DIGTMP_LR_TSL_MASK) + +#define DIGTMP_LR_TEL_MASK (0x200U) +#define DIGTMP_LR_TEL_SHIFT (9U) +/*! TEL - Tamper Enable Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_TEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TEL_SHIFT)) & DIGTMP_LR_TEL_MASK) + +#define DIGTMP_LR_PPL_MASK (0x800U) +#define DIGTMP_LR_PPL_SHIFT (11U) +/*! PPL - Pin Polarity Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_PPL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PPL_SHIFT)) & DIGTMP_LR_PPL_MASK) + +#define DIGTMP_LR_GFL0_MASK (0x10000U) +#define DIGTMP_LR_GFL0_SHIFT (16U) +/*! GFL0 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL0_SHIFT)) & DIGTMP_LR_GFL0_MASK) + +#define DIGTMP_LR_GFL1_MASK (0x20000U) +#define DIGTMP_LR_GFL1_SHIFT (17U) +/*! GFL1 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL1_SHIFT)) & DIGTMP_LR_GFL1_MASK) + +#define DIGTMP_LR_GFL2_MASK (0x40000U) +#define DIGTMP_LR_GFL2_SHIFT (18U) +/*! GFL2 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL2_SHIFT)) & DIGTMP_LR_GFL2_MASK) + +#define DIGTMP_LR_GFL3_MASK (0x80000U) +#define DIGTMP_LR_GFL3_SHIFT (19U) +/*! GFL3 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL3_SHIFT)) & DIGTMP_LR_GFL3_MASK) + +#define DIGTMP_LR_GFL4_MASK (0x100000U) +#define DIGTMP_LR_GFL4_SHIFT (20U) +/*! GFL4 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL4_SHIFT)) & DIGTMP_LR_GFL4_MASK) + +#define DIGTMP_LR_GFL5_MASK (0x200000U) +#define DIGTMP_LR_GFL5_SHIFT (21U) +/*! GFL5 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL5_SHIFT)) & DIGTMP_LR_GFL5_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define DIGTMP_IER_DTIE_MASK (0x1U) +#define DIGTMP_IER_DTIE_SHIFT (0U) +/*! DTIE - Digital Tamper Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_DTIE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_DTIE_SHIFT)) & DIGTMP_IER_DTIE_MASK) + +#define DIGTMP_IER_TIIE0_MASK (0x4U) +#define DIGTMP_IER_TIIE0_SHIFT (2U) +/*! TIIE0 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE0_SHIFT)) & DIGTMP_IER_TIIE0_MASK) + +#define DIGTMP_IER_TIIE1_MASK (0x8U) +#define DIGTMP_IER_TIIE1_SHIFT (3U) +/*! TIIE1 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE1_SHIFT)) & DIGTMP_IER_TIIE1_MASK) + +#define DIGTMP_IER_TIIE2_MASK (0x10U) +#define DIGTMP_IER_TIIE2_SHIFT (4U) +/*! TIIE2 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE2_SHIFT)) & DIGTMP_IER_TIIE2_MASK) + +#define DIGTMP_IER_TIIE3_MASK (0x20U) +#define DIGTMP_IER_TIIE3_SHIFT (5U) +/*! TIIE3 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE3_SHIFT)) & DIGTMP_IER_TIIE3_MASK) + +#define DIGTMP_IER_TIIE4_MASK (0x40U) +#define DIGTMP_IER_TIIE4_SHIFT (6U) +/*! TIIE4 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE4_SHIFT)) & DIGTMP_IER_TIIE4_MASK) + +#define DIGTMP_IER_TIIE5_MASK (0x80U) +#define DIGTMP_IER_TIIE5_SHIFT (7U) +/*! TIIE5 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE5_SHIFT)) & DIGTMP_IER_TIIE5_MASK) + +#define DIGTMP_IER_TIIE6_MASK (0x100U) +#define DIGTMP_IER_TIIE6_SHIFT (8U) +/*! TIIE6 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE6_SHIFT)) & DIGTMP_IER_TIIE6_MASK) + +#define DIGTMP_IER_TIIE7_MASK (0x200U) +#define DIGTMP_IER_TIIE7_SHIFT (9U) +/*! TIIE7 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE7_SHIFT)) & DIGTMP_IER_TIIE7_MASK) + +#define DIGTMP_IER_TIIE8_MASK (0x400U) +#define DIGTMP_IER_TIIE8_SHIFT (10U) +/*! TIIE8 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE8_SHIFT)) & DIGTMP_IER_TIIE8_MASK) + +#define DIGTMP_IER_TIIE9_MASK (0x800U) +#define DIGTMP_IER_TIIE9_SHIFT (11U) +/*! TIIE9 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE9_SHIFT)) & DIGTMP_IER_TIIE9_MASK) + +#define DIGTMP_IER_TIIE10_MASK (0x1000U) +#define DIGTMP_IER_TIIE10_SHIFT (12U) +/*! TIIE10 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE10(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE10_SHIFT)) & DIGTMP_IER_TIIE10_MASK) + +#define DIGTMP_IER_TPIE0_MASK (0x10000U) +#define DIGTMP_IER_TPIE0_SHIFT (16U) +/*! TPIE0 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE0_SHIFT)) & DIGTMP_IER_TPIE0_MASK) + +#define DIGTMP_IER_TPIE1_MASK (0x20000U) +#define DIGTMP_IER_TPIE1_SHIFT (17U) +/*! TPIE1 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE1_SHIFT)) & DIGTMP_IER_TPIE1_MASK) + +#define DIGTMP_IER_TPIE2_MASK (0x40000U) +#define DIGTMP_IER_TPIE2_SHIFT (18U) +/*! TPIE2 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE2_SHIFT)) & DIGTMP_IER_TPIE2_MASK) + +#define DIGTMP_IER_TPIE3_MASK (0x80000U) +#define DIGTMP_IER_TPIE3_SHIFT (19U) +/*! TPIE3 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE3_SHIFT)) & DIGTMP_IER_TPIE3_MASK) + +#define DIGTMP_IER_TPIE4_MASK (0x100000U) +#define DIGTMP_IER_TPIE4_SHIFT (20U) +/*! TPIE4 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE4_SHIFT)) & DIGTMP_IER_TPIE4_MASK) + +#define DIGTMP_IER_TPIE5_MASK (0x200000U) +#define DIGTMP_IER_TPIE5_SHIFT (21U) +/*! TPIE5 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE5_SHIFT)) & DIGTMP_IER_TPIE5_MASK) +/*! @} */ + +/*! @name TSR - Tamper Seconds */ +/*! @{ */ + +#define DIGTMP_TSR_TTS_MASK (0xFFFFFFFFU) +#define DIGTMP_TSR_TTS_SHIFT (0U) +/*! TTS - Tamper Time Seconds */ +#define DIGTMP_TSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TSR_TTS_SHIFT)) & DIGTMP_TSR_TTS_MASK) +/*! @} */ + +/*! @name TER - Tamper Enable */ +/*! @{ */ + +#define DIGTMP_TER_TIE0_MASK (0x4U) +#define DIGTMP_TER_TIE0_SHIFT (2U) +/*! TIE0 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE0_SHIFT)) & DIGTMP_TER_TIE0_MASK) + +#define DIGTMP_TER_TIE1_MASK (0x8U) +#define DIGTMP_TER_TIE1_SHIFT (3U) +/*! TIE1 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE1_SHIFT)) & DIGTMP_TER_TIE1_MASK) + +#define DIGTMP_TER_TIE2_MASK (0x10U) +#define DIGTMP_TER_TIE2_SHIFT (4U) +/*! TIE2 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE2_SHIFT)) & DIGTMP_TER_TIE2_MASK) + +#define DIGTMP_TER_TIE3_MASK (0x20U) +#define DIGTMP_TER_TIE3_SHIFT (5U) +/*! TIE3 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE3_SHIFT)) & DIGTMP_TER_TIE3_MASK) + +#define DIGTMP_TER_TIE4_MASK (0x40U) +#define DIGTMP_TER_TIE4_SHIFT (6U) +/*! TIE4 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE4_SHIFT)) & DIGTMP_TER_TIE4_MASK) + +#define DIGTMP_TER_TIE5_MASK (0x80U) +#define DIGTMP_TER_TIE5_SHIFT (7U) +/*! TIE5 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE5_SHIFT)) & DIGTMP_TER_TIE5_MASK) + +#define DIGTMP_TER_TIE6_MASK (0x100U) +#define DIGTMP_TER_TIE6_SHIFT (8U) +/*! TIE6 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE6_SHIFT)) & DIGTMP_TER_TIE6_MASK) + +#define DIGTMP_TER_TIE7_MASK (0x200U) +#define DIGTMP_TER_TIE7_SHIFT (9U) +/*! TIE7 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE7_SHIFT)) & DIGTMP_TER_TIE7_MASK) + +#define DIGTMP_TER_TIE8_MASK (0x400U) +#define DIGTMP_TER_TIE8_SHIFT (10U) +/*! TIE8 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE8_SHIFT)) & DIGTMP_TER_TIE8_MASK) + +#define DIGTMP_TER_TIE9_MASK (0x800U) +#define DIGTMP_TER_TIE9_SHIFT (11U) +/*! TIE9 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE9_SHIFT)) & DIGTMP_TER_TIE9_MASK) + +#define DIGTMP_TER_TIE10_MASK (0x1000U) +#define DIGTMP_TER_TIE10_SHIFT (12U) +/*! TIE10 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE10(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE10_SHIFT)) & DIGTMP_TER_TIE10_MASK) + +#define DIGTMP_TER_TPE0_MASK (0x10000U) +#define DIGTMP_TER_TPE0_SHIFT (16U) +/*! TPE0 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE0_SHIFT)) & DIGTMP_TER_TPE0_MASK) + +#define DIGTMP_TER_TPE1_MASK (0x20000U) +#define DIGTMP_TER_TPE1_SHIFT (17U) +/*! TPE1 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE1_SHIFT)) & DIGTMP_TER_TPE1_MASK) + +#define DIGTMP_TER_TPE2_MASK (0x40000U) +#define DIGTMP_TER_TPE2_SHIFT (18U) +/*! TPE2 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE2_SHIFT)) & DIGTMP_TER_TPE2_MASK) + +#define DIGTMP_TER_TPE3_MASK (0x80000U) +#define DIGTMP_TER_TPE3_SHIFT (19U) +/*! TPE3 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE3_SHIFT)) & DIGTMP_TER_TPE3_MASK) + +#define DIGTMP_TER_TPE4_MASK (0x100000U) +#define DIGTMP_TER_TPE4_SHIFT (20U) +/*! TPE4 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE4_SHIFT)) & DIGTMP_TER_TPE4_MASK) + +#define DIGTMP_TER_TPE5_MASK (0x200000U) +#define DIGTMP_TER_TPE5_SHIFT (21U) +/*! TPE5 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE5_SHIFT)) & DIGTMP_TER_TPE5_MASK) +/*! @} */ + +/*! @name PPR - Pin Polarity */ +/*! @{ */ + +#define DIGTMP_PPR_TPP0_MASK (0x1U) +#define DIGTMP_PPR_TPP0_SHIFT (0U) +/*! TPP0 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP0_SHIFT)) & DIGTMP_PPR_TPP0_MASK) + +#define DIGTMP_PPR_TPP1_MASK (0x2U) +#define DIGTMP_PPR_TPP1_SHIFT (1U) +/*! TPP1 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP1_SHIFT)) & DIGTMP_PPR_TPP1_MASK) + +#define DIGTMP_PPR_TPP2_MASK (0x4U) +#define DIGTMP_PPR_TPP2_SHIFT (2U) +/*! TPP2 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP2_SHIFT)) & DIGTMP_PPR_TPP2_MASK) + +#define DIGTMP_PPR_TPP3_MASK (0x8U) +#define DIGTMP_PPR_TPP3_SHIFT (3U) +/*! TPP3 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP3_SHIFT)) & DIGTMP_PPR_TPP3_MASK) + +#define DIGTMP_PPR_TPP4_MASK (0x10U) +#define DIGTMP_PPR_TPP4_SHIFT (4U) +/*! TPP4 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK) + +#define DIGTMP_PPR_TPP5_MASK (0x20U) +#define DIGTMP_PPR_TPP5_SHIFT (5U) +/*! TPP5 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP5_SHIFT)) & DIGTMP_PPR_TPP5_MASK) + +#define DIGTMP_PPR_TPID0_MASK (0x10000U) +#define DIGTMP_PPR_TPID0_SHIFT (16U) +/*! TPID0 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID0_SHIFT)) & DIGTMP_PPR_TPID0_MASK) + +#define DIGTMP_PPR_TPID1_MASK (0x20000U) +#define DIGTMP_PPR_TPID1_SHIFT (17U) +/*! TPID1 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID1_SHIFT)) & DIGTMP_PPR_TPID1_MASK) + +#define DIGTMP_PPR_TPID2_MASK (0x40000U) +#define DIGTMP_PPR_TPID2_SHIFT (18U) +/*! TPID2 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID2_SHIFT)) & DIGTMP_PPR_TPID2_MASK) + +#define DIGTMP_PPR_TPID3_MASK (0x80000U) +#define DIGTMP_PPR_TPID3_SHIFT (19U) +/*! TPID3 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID3_SHIFT)) & DIGTMP_PPR_TPID3_MASK) + +#define DIGTMP_PPR_TPID4_MASK (0x100000U) +#define DIGTMP_PPR_TPID4_SHIFT (20U) +/*! TPID4 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID4_SHIFT)) & DIGTMP_PPR_TPID4_MASK) + +#define DIGTMP_PPR_TPID5_MASK (0x200000U) +#define DIGTMP_PPR_TPID5_SHIFT (21U) +/*! TPID5 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID5_SHIFT)) & DIGTMP_PPR_TPID5_MASK) +/*! @} */ + +/*! @name PGFR - Pin Glitch Filter */ +/*! @{ */ + +#define DIGTMP_PGFR_GFW_MASK (0x3FU) +#define DIGTMP_PGFR_GFW_SHIFT (0U) +/*! GFW - Glitch Filter Width */ +#define DIGTMP_PGFR_GFW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFW_SHIFT)) & DIGTMP_PGFR_GFW_MASK) + +#define DIGTMP_PGFR_GFP_MASK (0x40U) +#define DIGTMP_PGFR_GFP_SHIFT (6U) +/*! GFP - Glitch Filter Prescaler + * 0b0..256 Hz prescaler clock + * 0b1..16.384 kHz clock + */ +#define DIGTMP_PGFR_GFP(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFP_SHIFT)) & DIGTMP_PGFR_GFP_MASK) + +#define DIGTMP_PGFR_GFE_MASK (0x80U) +#define DIGTMP_PGFR_GFE_SHIFT (7U) +/*! GFE - Glitch Filter Enable + * 0b0..Bypasses + * 0b1..Enables + */ +#define DIGTMP_PGFR_GFE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFE_SHIFT)) & DIGTMP_PGFR_GFE_MASK) + +#define DIGTMP_PGFR_TPSW_MASK (0x300U) +#define DIGTMP_PGFR_TPSW_SHIFT (8U) +/*! TPSW - Tamper Pin Sample Width + * 0b00..Continuous monitoring, pin sampling disabled + * 0b01..2 cycles for pull enable and 1 cycle for input buffer enable + * 0b10..4 cycles for pull enable and 2 cycles for input buffer enable + * 0b11..8 cycles for pull enable and 4 cycles for input buffer enable + */ +#define DIGTMP_PGFR_TPSW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSW_SHIFT)) & DIGTMP_PGFR_TPSW_MASK) + +#define DIGTMP_PGFR_TPSF_MASK (0xC00U) +#define DIGTMP_PGFR_TPSF_SHIFT (10U) +/*! TPSF - Tamper Pin Sample Frequency + * 0b00..Every 8 cycles + * 0b01..Every 32 cycles + * 0b10..Every 128 cycles + * 0b11..Every 512 cycles + */ +#define DIGTMP_PGFR_TPSF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSF_SHIFT)) & DIGTMP_PGFR_TPSF_MASK) + +#define DIGTMP_PGFR_TPE_MASK (0x1000000U) +#define DIGTMP_PGFR_TPE_SHIFT (24U) +/*! TPE - Tamper Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_PGFR_TPE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPE_SHIFT)) & DIGTMP_PGFR_TPE_MASK) + +#define DIGTMP_PGFR_TPS_MASK (0x2000000U) +#define DIGTMP_PGFR_TPS_SHIFT (25U) +/*! TPS - Tamper Pull Select + * 0b0..Asserts + * 0b1..Negates + */ +#define DIGTMP_PGFR_TPS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPS_SHIFT)) & DIGTMP_PGFR_TPS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DIGTMP_Register_Masks */ + + +/*! + * @} + */ /* end of group DIGTMP_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_DIGTMP_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_DMA.h new file mode 100644 index 000000000..bfa917adb --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_DMA.h @@ -0,0 +1,1089 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for DMA +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_DMA.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for DMA + * + * CMSIS Peripheral Access Layer for DMA + */ + +#if !defined(PERI_DMA_H_) +#define PERI_DMA_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +#if !defined(DMA_REQUEST_SOURCE_T_) +#define DMA_REQUEST_SOURCE_T_ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestDisabled = 0U, /**< Disabled */ + kDma0RequestWUU0 = 1U, /**< WUU Wake up event */ + kDma0RequestMuxFlexCan0DmaRequest = 2U, /**< CAN0 DMA request */ + kDma0RequestLPI2C2Rx = 3U, /**< LPI2C2 Receive request */ + kDma0RequestLPI2C2Tx = 4U, /**< LPI2C2 Transmit request */ + kDma0RequestLPI2C3Rx = 5U, /**< LPI2C3 Receive request */ + kDma0RequestLPI2C3Tx = 6U, /**< LPI2C3 Transmit request */ + kDma0RequestMuxI3c0Rx = 7U, /**< I3C0 Receive request */ + kDma0RequestMuxI3c0Tx = 8U, /**< I3C0 Transmit request */ + kDma0RequestLPI2C0Rx = 11U, /**< LPI2C0 Receive request */ + kDma0RequestLPI2C0Tx = 12U, /**< LPI2C0 Transmit request */ + kDma0RequestLPI2C1Rx = 13U, /**< LPI2C1 Receive request */ + kDma0RequestLPI2C1Tx = 14U, /**< LPI2C1 Transmit request */ + kDma0RequestLPSPI0Rx = 15U, /**< LPSPI0 Receive request */ + kDma0RequestLPSPI0Tx = 16U, /**< LPSPI0 Transmit request */ + kDma0RequestLPSPI1Rx = 17U, /**< LPSPI1 Receive request */ + kDma0RequestLPSPI1Tx = 18U, /**< LPSPI1 Transmit request */ + kDma0RequestLPUART0Rx = 21U, /**< LPUART0 Receive request */ + kDma0RequestLPUART0Tx = 22U, /**< LPUART0 Transmit request */ + kDma0RequestLPUART1Rx = 23U, /**< LPUART1 Receive request */ + kDma0RequestLPUART1Tx = 24U, /**< LPUART1 Transmit request */ + kDma0RequestLPUART2Rx = 25U, /**< LPUART2 Receive request */ + kDma0RequestLPUART2Tx = 26U, /**< LPUART2 Transmit request */ + kDma0RequestLPUART3Rx = 27U, /**< LPUART3 Receive request */ + kDma0RequestLPUART3Tx = 28U, /**< LPUART3 Transmit request */ + kDma0RequestLPUART4Rx = 29U, /**< LPUART4 Receive request */ + kDma0RequestLPUART4Tx = 30U, /**< LPUART4 Transmit request */ + kDma0RequestMuxCtimer0M0 = 31U, /**< CTIMER0 Match channel 0 request */ + kDma0RequestMuxCtimer0M1 = 32U, /**< CTIMER0 Match channel 1 request */ + kDma0RequestMuxCtimer1M0 = 33U, /**< CTIMER1 Match channel 0 request */ + kDma0RequestMuxCtimer1M1 = 34U, /**< CTIMER1 Match channel 1 request */ + kDma0RequestMuxCtimer2M0 = 35U, /**< CTIMER2 Match channel 0 request */ + kDma0RequestMuxCtimer2M1 = 36U, /**< CTIMER2 Match channel 1 request */ + kDma0RequestMuxCtimer3M0 = 37U, /**< CTIMER3 Match channel 0 request */ + kDma0RequestMuxCtimer3M1 = 38U, /**< CTIMER3 Match channel 1 request */ + kDma0RequestMuxCtimer4M0 = 39U, /**< CTIMER4 Match channel 0 request */ + kDma0RequestMuxCtimer4M1 = 40U, /**< CTIMER4 Match channel 1 request */ + kDma0RequestMuxFlexPWM0ReqCapt0 = 41U, /**< FlexPWM0 capture0 request */ + kDma0RequestMuxFlexPWM0ReqCapt1 = 42U, /**< FlexPWM0 capture1 request */ + kDma0RequestMuxFlexPWM0ReqCapt2 = 43U, /**< FlexPWM0 capture2 request */ + kDma0RequestMuxFlexPWM0ReqCapt3 = 44U, /**< FlexPWM0 capture3 request */ + kDma0RequestMuxFlexPWM0ReqVal0 = 45U, /**< FlexPWM0 value0 request */ + kDma0RequestMuxFlexPWM0ReqVal1 = 46U, /**< FlexPWM0 value1 request */ + kDma0RequestMuxFlexPWM0ReqVal2 = 47U, /**< FlexPWM0 value2 request */ + kDma0RequestMuxFlexPWM0ReqVal3 = 48U, /**< FlexPWM0 value3 request */ + kDma0RequestMuxLptmr0 = 49U, /**< LPTMR0 Counter match event */ + kDma0RequestMuxAdc0FifoRequest = 51U, /**< ADC0 FIFO request */ + kDma0RequestMuxAdc1FifoRequest = 52U, /**< ADC1 FIFO request */ + kDma0RequestMuxHsCmp0DmaRequest = 53U, /**< CMP0 DMA_request */ + kDma0RequestMuxHsCmp1DmaRequest = 54U, /**< CMP1 DMA_request */ + kDma0RequestMuxDac0FifoRequest = 56U, /**< DAC0 FIFO request */ + kDma0RequestMuxGpio0PinEventRequest0 = 60U, /**< GPIO0 Pin event request 0 */ + kDma0RequestMuxGpio1PinEventRequest0 = 61U, /**< GPIO1 Pin event request 0 */ + kDma0RequestMuxGpio2PinEventRequest0 = 62U, /**< GPIO2 Pin event request 0 */ + kDma0RequestMuxGpio3PinEventRequest0 = 63U, /**< GPIO3 Pin event request 0 */ + kDma0RequestMuxGpio4PinEventRequest0 = 64U, /**< GPIO4 Pin event request 0 */ + kDma0RequestMuxEqdc0 = 65U, /**< EQDC0 DMA request for new buffered value */ + kDma0RequestMuxEqdc1 = 66U, /**< EQDC1 DMA request for new buffered value */ + kDma0RequestMuxFlexIO0ShiftRegister0Request = 71U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister1Request = 72U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister2Request = 73U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister3Request = 74U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma0RequestMuxFlexPWM1ReqCapt0 = 79U, /**< FlexPWM1 capture0 request */ + kDma0RequestMuxFlexPWM1ReqCapt1 = 80U, /**< FlexPWM1 capture1 request */ + kDma0RequestMuxFlexPWM1ReqCapt2 = 81U, /**< FlexPWM1 capture2 request */ + kDma0RequestMuxFlexPWM1ReqCapt3 = 82U, /**< FlexPWM1 capture3 request */ + kDma0RequestMuxFlexPWM1ReqVal0 = 83U, /**< FlexPWM1 value0 request */ + kDma0RequestMuxFlexPWM1ReqVal1 = 84U, /**< FlexPWM1 value1 request */ + kDma0RequestMuxFlexPWM1ReqVal2 = 85U, /**< FlexPWM1 value2 request */ + kDma0RequestMuxFlexPWM1ReqVal3 = 86U, /**< FlexPWM1 value2 request */ + kDma0RequestMuxFlexCan1DmaRequest = 87U, /**< CAN1 DMA request */ + kDma0RequestLPUART5Rx = 102U, /**< LPUART5 Receive request */ + kDma0RequestLPUART5Tx = 103U, /**< LPUART5 Transmit request */ + kDma0RequestSGI0Datain = 119U, /**< SGI0 DATAIN request */ + kDma0RequestSGI0Dataout = 120U, /**< SGI0 DATOUT request */ +} dma_request_source_t; + +/* @} */ +#endif /* DMA_REQUEST_SOURCE_T_ */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Size of Registers Arrays */ +#define DMA_MP_GRPRI_COUNT 8u +#define DMA_CH_COUNT 8u + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ + __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ + __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ + __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ + uint8_t RESERVED_0[240]; + __IO uint32_t CH_GRPRI[DMA_MP_GRPRI_COUNT]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[3808]; + struct { /* offset: 0x1000, array step: 0x1000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */ + uint8_t RESERVED_0[8]; + __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */ + __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */ + __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */ + union { /* offset: 0x1028, array step: 0x1000 */ + __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */ + __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */ + }; + __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */ + __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */ + __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */ + union { /* offset: 0x1036, array step: 0x1000 */ + __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */ + __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */ + }; + __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */ + __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */ + union { /* offset: 0x103E, array step: 0x1000 */ + __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */ + __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */ + }; + uint8_t RESERVED_1[4032]; + } CH[DMA_CH_COUNT]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name MP_CSR - Management Page Control */ +/*! @{ */ + +#define DMA_MP_CSR_EDBG_MASK (0x2U) +#define DMA_MP_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode disabled + * 0b1..Debug mode is enabled. + */ +#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) + +#define DMA_MP_CSR_ERCA_MASK (0x4U) +#define DMA_MP_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round-robin channel arbitration disabled + * 0b1..Round-robin channel arbitration enabled + */ +#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) + +#define DMA_MP_CSR_HAE_MASK (0x10U) +#define DMA_MP_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT field to be set to 1 + */ +#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) + +#define DMA_MP_CSR_HALT_MASK (0x20U) +#define DMA_MP_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels + */ +#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) + +#define DMA_MP_CSR_GCLC_MASK (0x40U) +#define DMA_MP_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking disabled for all channels + * 0b1..Channel linking available and controlled by each channel's link settings + */ +#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) + +#define DMA_MP_CSR_GMRC_MASK (0x80U) +#define DMA_MP_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Initiator ID Replication Control + * 0b0..Initiator ID replication disabled for all channels + * 0b1..Initiator ID replication available and controlled by each channel's CHn_SBR[EMI] setting + */ +#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) + +#define DMA_MP_CSR_ECX_MASK (0x100U) +#define DMA_MP_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer With Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) + +#define DMA_MP_CSR_CX_MASK (0x200U) +#define DMA_MP_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) + +#define DMA_MP_CSR_ACTIVE_ID_MASK (0x7000000U) +#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active Channel ID */ +#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) + +#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_MP_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle + * 0b1..eDMA is executing a channel + */ +#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name MP_ES - Management Page Error Status */ +/*! @{ */ + +#define DMA_MP_ES_DBE_MASK (0x1U) +#define DMA_MP_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was a bus error on a destination write + */ +#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) + +#define DMA_MP_ES_SBE_MASK (0x2U) +#define DMA_MP_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was a bus error on a source read + */ +#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) + +#define DMA_MP_ES_SGE_MASK (0x4U) +#define DMA_MP_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) + +#define DMA_MP_ES_NCE_MASK (0x8U) +#define DMA_MP_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) + +#define DMA_MP_ES_DOE_MASK (0x10U) +#define DMA_MP_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) + +#define DMA_MP_ES_DAE_MASK (0x20U) +#define DMA_MP_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) + +#define DMA_MP_ES_SOE_MASK (0x40U) +#define DMA_MP_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) + +#define DMA_MP_ES_SAE_MASK (0x80U) +#define DMA_MP_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) + +#define DMA_MP_ES_ECX_MASK (0x100U) +#define DMA_MP_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) + +#define DMA_MP_ES_ERRCHN_MASK (0x7000000U) +#define DMA_MP_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) + +#define DMA_MP_ES_VLD_MASK (0x80000000U) +#define DMA_MP_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No CHn_ES[ERR] fields are set to 1 + * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared + */ +#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) +/*! @} */ + +/*! @name MP_INT - Management Page Interrupt Request Status */ +/*! @{ */ + +#define DMA_MP_INT_INT_MASK (0xFFU) +#define DMA_MP_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request Status */ +#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) +/*! @} */ + +/*! @name MP_HRS - Management Page Hardware Request Status */ +/*! @{ */ + +#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) +#define DMA_MP_HRS_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status */ +#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group */ +/*! @{ */ + +#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) +#define DMA_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration Group For Channel n */ +#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA_CH_GRPRI */ +#define DMA_CH_GRPRI_COUNT (8U) + +/*! @name CH_CSR - Channel Control and Status */ +/*! @{ */ + +#define DMA_CH_CSR_ERQ_MASK (0x1U) +#define DMA_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..DMA hardware request signal for corresponding channel disabled + * 0b1..DMA hardware request signal for corresponding channel enabled + */ +#define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) + +#define DMA_CH_CSR_EARQ_MASK (0x2U) +#define DMA_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel + * 0b1..Enable asynchronous DMA request for the channel + */ +#define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) + +#define DMA_CH_CSR_EEI_MASK (0x4U) +#define DMA_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..Error signal for corresponding channel does not generate error interrupt + * 0b1..Assertion of error signal for corresponding channel generates error interrupt request + */ +#define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) + +#define DMA_CH_CSR_EBW_MASK (0x8U) +#define DMA_CH_CSR_EBW_SHIFT (3U) +/*! EBW - Enable Buffered Writes + * 0b0..Buffered writes on system bus disabled + * 0b1..Buffered writes on system bus enabled + */ +#define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK) + +#define DMA_CH_CSR_DONE_MASK (0x40000000U) +#define DMA_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) + +#define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of DMA_CH_CSR */ +#define DMA_CH_CSR_COUNT (8U) + +/*! @name CH_ES - Channel Error Status */ +/*! @{ */ + +#define DMA_CH_ES_DBE_MASK (0x1U) +#define DMA_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was bus error on destination write + */ +#define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) + +#define DMA_CH_ES_SBE_MASK (0x2U) +#define DMA_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was bus error on source read + */ +#define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) + +#define DMA_CH_ES_SGE_MASK (0x4U) +#define DMA_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) + +#define DMA_CH_ES_NCE_MASK (0x8U) +#define DMA_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields + */ +#define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) + +#define DMA_CH_ES_DOE_MASK (0x10U) +#define DMA_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) + +#define DMA_CH_ES_DAE_MASK (0x20U) +#define DMA_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) + +#define DMA_CH_ES_SOE_MASK (0x40U) +#define DMA_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) + +#define DMA_CH_ES_SAE_MASK (0x80U) +#define DMA_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) + +#define DMA_CH_ES_ERR_MASK (0x80000000U) +#define DMA_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of DMA_CH_ES */ +#define DMA_CH_ES_COUNT (8U) + +/*! @name CH_INT - Channel Interrupt Status */ +/*! @{ */ + +#define DMA_CH_INT_INT_MASK (0x1U) +#define DMA_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..Interrupt request for corresponding channel cleared + * 0b1..Interrupt request for corresponding channel active + */ +#define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) +/*! @} */ + +/* The count of DMA_CH_INT */ +#define DMA_CH_INT_COUNT (8U) + +/*! @name CH_SBR - Channel System Bus */ +/*! @{ */ + +#define DMA_CH_SBR_MID_MASK (0xFU) +#define DMA_CH_SBR_MID_SHIFT (0U) +/*! MID - Initiator ID */ +#define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) + +#define DMA_CH_SBR_PAL_MASK (0x8000U) +#define DMA_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) + +#define DMA_CH_SBR_EMI_MASK (0x10000U) +#define DMA_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Initiator ID Replication + * 0b0..Initiator ID replication is disabled + * 0b1..Initiator ID replication is enabled + */ +#define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) +/*! @} */ + +/* The count of DMA_CH_SBR */ +#define DMA_CH_SBR_COUNT (8U) + +/*! @name CH_PRI - Channel Priority */ +/*! @{ */ + +#define DMA_CH_PRI_APL_MASK (0x7U) +#define DMA_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) + +#define DMA_CH_PRI_DPA_MASK (0x40000000U) +#define DMA_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel can suspend a lower-priority channel + * 0b1..Channel cannot suspend any other channel, regardless of channel priority + */ +#define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) + +#define DMA_CH_PRI_ECP_MASK (0x80000000U) +#define DMA_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel cannot be suspended by a higher-priority channel's service request + * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request + */ +#define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of DMA_CH_PRI */ +#define DMA_CH_PRI_COUNT (8U) + +/*! @name CH_MUX - Channel Multiplexor Configuration */ +/*! @{ */ + +#define DMA_CH_MUX_SRC_MASK (0x7FU) +#define DMA_CH_MUX_SRC_SHIFT (0U) +/*! SRC - Service Request Source */ +#define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK) +/*! @} */ + +/* The count of DMA_CH_MUX */ +#define DMA_CH_MUX_COUNT (8U) + +/*! @name TCD_SADDR - TCD Source Address */ +/*! @{ */ + +#define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_SADDR */ +#define DMA_TCD_SADDR_COUNT (8U) + +/*! @name TCD_SOFF - TCD Signed Source Address Offset */ +/*! @{ */ + +#define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source Address Signed Offset */ +#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_SOFF */ +#define DMA_TCD_SOFF_COUNT (8U) + +/*! @name TCD_ATTR - TCD Transfer Attributes */ +/*! @{ */ + +#define DMA_TCD_ATTR_DSIZE_MASK (0x7U) +#define DMA_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination Data Transfer Size */ +#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) + +#define DMA_TCD_ATTR_DMOD_MASK (0xF8U) +#define DMA_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo */ +#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) + +#define DMA_TCD_ATTR_SSIZE_MASK (0x700U) +#define DMA_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source Data Transfer Size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110.. + * 0b111.. + */ +#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) + +#define DMA_TCD_ATTR_SMOD_MASK (0xF800U) +#define DMA_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature disabled + */ +#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_TCD_ATTR */ +#define DMA_TCD_ATTR_COUNT (8U) + +/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFNO */ +#define DMA_TCD_NBYTES_MLOFFNO_COUNT (8U) + +/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFYES */ +#define DMA_TCD_NBYTES_MLOFFYES_COUNT (8U) + +/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ +/*! @{ */ + +#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of DMA_TCD_SLAST_SDA */ +#define DMA_TCD_SLAST_SDA_COUNT (8U) + +/*! @name TCD_DADDR - TCD Destination Address */ +/*! @{ */ + +#define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_DADDR */ +#define DMA_TCD_DADDR_COUNT (8U) + +/*! @name TCD_DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ + +#define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_DOFF */ +#define DMA_TCD_DOFF_COUNT (8U) + +/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) + +#define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKNO */ +#define DMA_TCD_CITER_ELINKNO_COUNT (8U) + +/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) + +#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0xE00U) +#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) + +#define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKYES */ +#define DMA_TCD_CITER_ELINKYES_COUNT (8U) + +/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ +/*! @{ */ + +#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ +#define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of DMA_TCD_DLAST_SGA */ +#define DMA_TCD_DLAST_SGA_COUNT (8U) + +/*! @name TCD_CSR - TCD Control and Status */ +/*! @{ */ + +#define DMA_TCD_CSR_START_MASK (0x1U) +#define DMA_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..Channel not explicitly started + * 0b1..Channel explicitly started via a software-initiated service request + */ +#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) + +#define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) +#define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable Interrupt If Major count complete + * 0b0..End-of-major loop interrupt disabled + * 0b1..End-of-major loop interrupt enabled + */ +#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) + +#define DMA_TCD_CSR_INTHALF_MASK (0x4U) +#define DMA_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable Interrupt If Major Counter Half-complete + * 0b0..Halfway point interrupt disabled + * 0b1..Halfway point interrupt enabled + */ +#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) + +#define DMA_TCD_CSR_DREQ_MASK (0x8U) +#define DMA_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..No operation + * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests + */ +#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) + +#define DMA_TCD_CSR_ESG_MASK (0x10U) +#define DMA_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..Current channel's TCD is normal format + * 0b1..Current channel's TCD specifies scatter/gather format. + */ +#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) + +#define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) +#define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable Link When Major Loop Complete + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) + +#define DMA_TCD_CSR_EEOP_MASK (0x40U) +#define DMA_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable End-Of-Packet Processing + * 0b0..End-of-packet operation disabled + * 0b1..End-of-packet hardware input signal enabled + */ +#define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) + +#define DMA_TCD_CSR_ESDA_MASK (0x80U) +#define DMA_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable Store Destination Address + * 0b0..Ability to store destination address to system memory disabled + * 0b1..Ability to store destination address to system memory enabled + */ +#define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) + +#define DMA_TCD_CSR_MAJORLINKCH_MASK (0x700U) +#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number */ +#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) + +#define DMA_TCD_CSR_BWC_MASK (0xC000U) +#define DMA_TCD_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01.. + * 0b10..eDMA engine stalls for 4 cycles after each R/W + * 0b11..eDMA engine stalls for 8 cycles after each R/W + */ +#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_TCD_CSR */ +#define DMA_TCD_CSR_COUNT (8U) + +/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) + +#define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKNO */ +#define DMA_TCD_BITER_ELINKNO_COUNT (8U) + +/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) + +#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0xE00U) +#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) + +#define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKYES */ +#define DMA_TCD_BITER_ELINKYES_COUNT (8U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_DMA_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_EIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_EIM.h new file mode 100644 index 000000000..16a26f2fd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_EIM.h @@ -0,0 +1,287 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for EIM +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_EIM.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for EIM + * + * CMSIS Peripheral Access Layer for EIM + */ + +#if !defined(PERI_EIM_H_) +#define PERI_EIM_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +#if !defined(EIM_MEMORY_CHANNEL_T_) +#define EIM_MEMORY_CHANNEL_T_ +/*! + * @addtogroup eim_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_memory_channel + * + * Defines the structure for the EIM resource collections. + */ + +typedef enum _eim_memory_channel +{ + kEIM_MemoryChannelRAMA0 = 0U, /**< Memory RAMA0 */ +} eim_memory_channel_t; + +/* @} */ +#endif /* EIM_MEMORY_CHANNEL_T_ */ + +#if !defined(EIM_ERROR_INJECTION_CHANNEL_ENABLE_T_) +#define EIM_ERROR_INJECTION_CHANNEL_ENABLE_T_ +/*! + * @addtogroup eim_error_injection_channel_enable + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_error_injection_channel_enable + * + * Defines the structure for the EIM error injection resource collections. + */ + +typedef enum _eim_error_injection_channel_enable +{ + kEIM_MemoryChannelRAMAEnable = 0x80000000U, /**< Memory channel 0(RAMA0) error injection enable */ +} eim_error_injection_channel_enable_t; + +/* @} */ +#endif /* EIM_ERROR_INJECTION_CHANNEL_ENABLE_T_ */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ + __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ + uint8_t RESERVED_0[248]; + __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ + __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name EIMCR - Error Injection Module Configuration Register */ +/*! @{ */ + +#define EIM_EIMCR_GEIEN_MASK (0x1U) +#define EIM_EIMCR_GEIEN_SHIFT (0U) +/*! GEIEN - Global Error Injection Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) +/*! @} */ + +/*! @name EICHEN - Error Injection Channel Enable register */ +/*! @{ */ + +#define EIM_EICHEN_EICH0EN_MASK (0x80000000U) +#define EIM_EICHEN_EICH0EN_SHIFT (31U) +/*! EICH0EN - Error Injection Channel 0 Enable + * 0b0..Error injection is disabled on Error Injection Channel 0 + * 0b1..Error injection is enabled on Error Injection Channel 0 + */ +#define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) +/*! @} */ + +/*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ +/*! @{ */ + +#define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ +/*! @{ */ + +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Field */ +#define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_EIM_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_EQDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_EQDC.h new file mode 100644 index 000000000..18faacd46 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_EQDC.h @@ -0,0 +1,1046 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for EQDC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_EQDC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for EQDC + * + * CMSIS Peripheral Access Layer for EQDC + */ + +#if !defined(PERI_EQDC_H_) +#define PERI_EQDC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- EQDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EQDC_Peripheral_Access_Layer EQDC Peripheral Access Layer + * @{ + */ + +/** EQDC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x2 */ + __IO uint16_t FILT; /**< Input Filter Register, offset: 0x4 */ + __I uint16_t LASTEDGE; /**< Last Edge Time Register, offset: 0x6 */ + __I uint16_t POSDPER; /**< Position Difference Period Counter Register, offset: 0x8 */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer Register, offset: 0xA */ + __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xC */ + __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0xE */ + __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x10 */ + __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x12 */ + __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x14 */ + __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x16 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold Register, offset: 0x18 */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold Register, offset: 0x1A */ + __I uint16_t REVH; /**< Revolution Hold Register, offset: 0x1C */ + __IO uint16_t REV; /**< Revolution Counter Register, offset: 0x1E */ + __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x20 */ + __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x22 */ + __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x24 */ + __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x26 */ + __IO uint16_t UCOMP0; /**< Upper Position Compare Register 0, offset: 0x28 */ + __IO uint16_t LCOMP0; /**< Lower Position Compare Register 0, offset: 0x2A */ + union { /* offset: 0x2C */ + __O uint16_t UCOMP1; /**< Upper Position Compare 1, offset: 0x2C */ + __I uint16_t UPOSH1; /**< Upper Position Holder Register 1, offset: 0x2C */ + }; + union { /* offset: 0x2E */ + __O uint16_t LCOMP1; /**< Lower Position Compare 1, offset: 0x2E */ + __I uint16_t LPOSH1; /**< Lower Position Holder Register 1, offset: 0x2E */ + }; + union { /* offset: 0x30 */ + __O uint16_t UCOMP2; /**< Upper Position Compare 2, offset: 0x30 */ + __I uint16_t UPOSH2; /**< Upper Position Holder Register 3, offset: 0x30 */ + }; + union { /* offset: 0x32 */ + __O uint16_t LCOMP2; /**< Lower Position Compare 2, offset: 0x32 */ + __I uint16_t LPOSH2; /**< Lower Position Holder Register 2, offset: 0x32 */ + }; + union { /* offset: 0x34 */ + __O uint16_t UCOMP3; /**< Upper Position Compare 3, offset: 0x34 */ + __I uint16_t UPOSH3; /**< Upper Position Holder Register 3, offset: 0x34 */ + }; + union { /* offset: 0x36 */ + __O uint16_t LCOMP3; /**< Lower Position Compare 3, offset: 0x36 */ + __I uint16_t LPOSH3; /**< Lower Position Holder Register 3, offset: 0x36 */ + }; + __IO uint16_t INTCTRL; /**< Interrupt Control Register, offset: 0x38 */ + __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x3A */ + __IO uint16_t IMR; /**< Input Monitor Register, offset: 0x3C */ + __IO uint16_t TST; /**< Test Register, offset: 0x3E */ + uint8_t RESERVED_0[16]; + __I uint16_t UVERID; /**< Upper VERID, offset: 0x50 */ + __I uint16_t LVERID; /**< Lower VERID, offset: 0x52 */ +} EQDC_Type; + +/* ---------------------------------------------------------------------------- + -- EQDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EQDC_Register_Masks EQDC Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define EQDC_CTRL_LDOK_MASK (0x1U) +#define EQDC_CTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0..No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers) + * 0b1..Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2[LDMOD]. + */ +#define EQDC_CTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_LDOK_SHIFT)) & EQDC_CTRL_LDOK_MASK) + +#define EQDC_CTRL_DMAEN_MASK (0x2U) +#define EQDC_CTRL_DMAEN_SHIFT (1U) +/*! DMAEN - DMA Enable + * 0b0..DMA is disabled + * 0b1..DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare + * registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and + * modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. + * After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be + * loaded into inner-set which in turn triggers DMA again. + */ +#define EQDC_CTRL_DMAEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_DMAEN_SHIFT)) & EQDC_CTRL_DMAEN_MASK) + +#define EQDC_CTRL_WDE_MASK (0x4U) +#define EQDC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDE_SHIFT)) & EQDC_CTRL_WDE_MASK) + +#define EQDC_CTRL_WDIE_MASK (0x8U) +#define EQDC_CTRL_WDIE_SHIFT (3U) +/*! WDIE - Watchdog Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_WDIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIE_SHIFT)) & EQDC_CTRL_WDIE_MASK) + +#define EQDC_CTRL_WDIRQ_MASK (0x10U) +#define EQDC_CTRL_WDIRQ_SHIFT (4U) +/*! WDIRQ - Watchdog Timeout Interrupt Request + * 0b0..No Watchdog timeout interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ +#define EQDC_CTRL_WDIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIRQ_SHIFT)) & EQDC_CTRL_WDIRQ_MASK) + +#define EQDC_CTRL_XNE_MASK (0x20U) +#define EQDC_CTRL_XNE_SHIFT (5U) +/*! XNE - Select Positive/Negative Edge of INDEX/PRESET Pulse + * 0b0..Use positive edge of INDEX/PRESET pulse + * 0b1..Use negative edge of INDEX/PRESET pulse + */ +#define EQDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XNE_SHIFT)) & EQDC_CTRL_XNE_MASK) + +#define EQDC_CTRL_XIP_MASK (0x40U) +#define EQDC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..INDEX pulse does not initialize the position counter + * 0b1..INDEX pulse initializes the position counter + */ +#define EQDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIP_SHIFT)) & EQDC_CTRL_XIP_MASK) + +#define EQDC_CTRL_XIE_MASK (0x80U) +#define EQDC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX/PRESET Pulse Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIE_SHIFT)) & EQDC_CTRL_XIE_MASK) + +#define EQDC_CTRL_XIRQ_MASK (0x100U) +#define EQDC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX/PRESET Pulse Interrupt Request + * 0b0..INDEX/PRESET pulse has not occurred + * 0b1..INDEX/PRESET pulse has occurred + */ +#define EQDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIRQ_SHIFT)) & EQDC_CTRL_XIRQ_MASK) + +#define EQDC_CTRL_PH1_MASK (0x200U) +#define EQDC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Single Phase Mode + * 0b0..Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + * 0b1..Single phase mode, bypass the quadrature decoder, refer to CTRL2[CMODE] description + */ +#define EQDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_PH1_SHIFT)) & EQDC_CTRL_PH1_MASK) + +#define EQDC_CTRL_REV_MASK (0x400U) +#define EQDC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT + * 0b1..Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD + */ +#define EQDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_REV_SHIFT)) & EQDC_CTRL_REV_MASK) + +#define EQDC_CTRL_SWIP_MASK (0x800U) +#define EQDC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define EQDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_SWIP_SHIFT)) & EQDC_CTRL_SWIP_MASK) + +#define EQDC_CTRL_HNE_MASK (0x1000U) +#define EQDC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME/ENABLE Input + * 0b0..When CTRL[OPMODE] = 0,use HOME positive edge to trigger initialization of position counters. When + * CTRL[OPMODE] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters + * 0b1..When CTRL[OPMODE] = 0,use HOME negative edge to trigger initialization of position counters. When + * CTRL[OPMODE] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters + */ +#define EQDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HNE_SHIFT)) & EQDC_CTRL_HNE_MASK) + +#define EQDC_CTRL_HIP_MASK (0x2000U) +#define EQDC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counter UPOS/LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define EQDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIP_SHIFT)) & EQDC_CTRL_HIP_MASK) + +#define EQDC_CTRL_HIE_MASK (0x4000U) +#define EQDC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME/ENABLE Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIE_SHIFT)) & EQDC_CTRL_HIE_MASK) + +#define EQDC_CTRL_HIRQ_MASK (0x8000U) +#define EQDC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME/ENABLE Signal Transition Interrupt Request + * 0b0..No transition on the HOME/ENABLE signal has occurred + * 0b1..A transition on the HOME/ENABLE signal has occurred + */ +#define EQDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIRQ_SHIFT)) & EQDC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define EQDC_CTRL2_UPDHLD_MASK (0x1U) +#define EQDC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers */ +#define EQDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDHLD_SHIFT)) & EQDC_CTRL2_UPDHLD_MASK) + +#define EQDC_CTRL2_UPDPOS_MASK (0x2U) +#define EQDC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers */ +#define EQDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDPOS_SHIFT)) & EQDC_CTRL2_UPDPOS_MASK) + +#define EQDC_CTRL2_OPMODE_MASK (0x4U) +#define EQDC_CTRL2_OPMODE_SHIFT (2U) +/*! OPMODE - Operation Mode Select + * 0b0..Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME. + * 0b1..Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In + * this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, + * when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising + * edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization + * also need referring to bit CTRL[REV]). + */ +#define EQDC_CTRL2_OPMODE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OPMODE_SHIFT)) & EQDC_CTRL2_OPMODE_MASK) + +#define EQDC_CTRL2_LDMOD_MASK (0x8U) +#define EQDC_CTRL2_LDMOD_SHIFT (3U) +/*! LDMOD - Buffered Register Load (Update) Mode Select + * 0b0..Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set. + * 0b1..Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set. + */ +#define EQDC_CTRL2_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_LDMOD_SHIFT)) & EQDC_CTRL2_LDMOD_MASK) + +#define EQDC_CTRL2_REVMOD_MASK (0x100U) +#define EQDC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV) + */ +#define EQDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_REVMOD_SHIFT)) & EQDC_CTRL2_REVMOD_MASK) + +#define EQDC_CTRL2_OUTCTL_MASK (0x200U) +#define EQDC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POS_MATCH[x](x range is 0-3) is asserted when the Position Counter is equal to according compare value + * (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value + * (UCOMPx/LCOMPx)(x range is 0-3) + * 0b1..All POS_MATCH[x](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read + */ +#define EQDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OUTCTL_SHIFT)) & EQDC_CTRL2_OUTCTL_MASK) + +#define EQDC_CTRL2_PMEN_MASK (0x400U) +#define EQDC_CTRL2_PMEN_SHIFT (10U) +/*! PMEN - Period measurement function enable + * 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read. + * 0b1..Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read. + */ +#define EQDC_CTRL2_PMEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_PMEN_SHIFT)) & EQDC_CTRL2_PMEN_MASK) + +#define EQDC_CTRL2_EMIP_MASK (0x800U) +#define EQDC_CTRL2_EMIP_SHIFT (11U) +/*! EMIP - Enables/disables the position counter to be initialized by Index Event Edge Mark + * 0b0..disables the position counter to be initialized by Index Event Edge Mark + * 0b1..enables the position counter to be initialized by Index Event Edge Mark. + */ +#define EQDC_CTRL2_EMIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_EMIP_SHIFT)) & EQDC_CTRL2_EMIP_MASK) + +#define EQDC_CTRL2_INITPOS_MASK (0x1000U) +#define EQDC_CTRL2_INITPOS_SHIFT (12U) +/*! INITPOS - Initial Position Register + * 0b0..Don't initialize position counter on rising edge of TRIGGER + * 0b1..Initialize position counter on rising edge of TRIGGER + */ +#define EQDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_INITPOS_SHIFT)) & EQDC_CTRL2_INITPOS_MASK) + +#define EQDC_CTRL2_ONCE_MASK (0x2000U) +#define EQDC_CTRL2_ONCE_SHIFT (13U) +/*! ONCE - Count Once + * 0b0..Position counter counts repeatedly + * 0b1..Position counter counts until roll-over or roll-under, then stop. + */ +#define EQDC_CTRL2_ONCE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_ONCE_SHIFT)) & EQDC_CTRL2_ONCE_MASK) + +#define EQDC_CTRL2_CMODE_MASK (0xC000U) +#define EQDC_CTRL2_CMODE_SHIFT (14U) +/*! CMODE - Counting Mode */ +#define EQDC_CTRL2_CMODE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_CMODE_SHIFT)) & EQDC_CTRL2_CMODE_MASK) +/*! @} */ + +/*! @name FILT - Input Filter Register */ +/*! @{ */ + +#define EQDC_FILT_FILT_PER_MASK (0xFFU) +#define EQDC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define EQDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_PER_SHIFT)) & EQDC_FILT_FILT_PER_MASK) + +#define EQDC_FILT_FILT_CNT_MASK (0x700U) +#define EQDC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define EQDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CNT_SHIFT)) & EQDC_FILT_FILT_CNT_MASK) + +#define EQDC_FILT_FILT_CS_MASK (0x800U) +#define EQDC_FILT_FILT_CS_SHIFT (11U) +/*! FILT_CS - Filter Clock Source selection + * 0b0..Peripheral Clock + * 0b1..Prescaled peripheral clock by PRSC + */ +#define EQDC_FILT_FILT_CS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CS_SHIFT)) & EQDC_FILT_FILT_CS_MASK) + +#define EQDC_FILT_PRSC_MASK (0xF000U) +#define EQDC_FILT_PRSC_SHIFT (12U) +/*! PRSC - Prescaler */ +#define EQDC_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_PRSC_SHIFT)) & EQDC_FILT_PRSC_MASK) +/*! @} */ + +/*! @name LASTEDGE - Last Edge Time Register */ +/*! @{ */ + +#define EQDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define EQDC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter */ +#define EQDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGE_LASTEDGE_SHIFT)) & EQDC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter Register */ +/*! @{ */ + +#define EQDC_POSDPER_POSDPER_MASK (0xFFFFU) +#define EQDC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period */ +#define EQDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPER_POSDPER_SHIFT)) & EQDC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer Register */ +/*! @{ */ + +#define EQDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define EQDC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer */ +#define EQDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERBFR_POSDPERBFR_SHIFT)) & EQDC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ + +#define EQDC_UPOS_POS_MASK (0xFFFFU) +#define EQDC_UPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define EQDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOS_POS_SHIFT)) & EQDC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ + +#define EQDC_LPOS_POS_MASK (0xFFFFU) +#define EQDC_LPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define EQDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOS_POS_SHIFT)) & EQDC_LPOS_POS_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter Register */ +/*! @{ */ + +#define EQDC_POSD_POSD_MASK (0xFFFFU) +#define EQDC_POSD_POSD_SHIFT (0U) +/*! POSD - POSD */ +#define EQDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSD_POSD_SHIFT)) & EQDC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ + +#define EQDC_POSDH_POSDH_MASK (0xFFFFU) +#define EQDC_POSDH_POSDH_SHIFT (0U) +/*! POSDH - POSDH */ +#define EQDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDH_POSDH_SHIFT)) & EQDC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ + +#define EQDC_UPOSH_POSH_MASK (0xFFFFU) +#define EQDC_UPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define EQDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH_POSH_SHIFT)) & EQDC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ + +#define EQDC_LPOSH_LPOSH_MASK (0xFFFFU) +#define EQDC_LPOSH_LPOSH_SHIFT (0U) +/*! LPOSH - POSH */ +#define EQDC_LPOSH_LPOSH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH_LPOSH_SHIFT)) & EQDC_LPOSH_LPOSH_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold Register */ +/*! @{ */ + +#define EQDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define EQDC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold */ +#define EQDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGEH_LASTEDGEH_SHIFT)) & EQDC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold Register */ +/*! @{ */ + +#define EQDC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define EQDC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold */ +#define EQDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERH_POSDPERH_SHIFT)) & EQDC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold Register */ +/*! @{ */ + +#define EQDC_REVH_REVH_MASK (0xFFFFU) +#define EQDC_REVH_REVH_SHIFT (0U) +/*! REVH - REVH */ +#define EQDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_REVH_REVH_SHIFT)) & EQDC_REVH_REVH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter Register */ +/*! @{ */ + +#define EQDC_REV_REV_MASK (0xFFFFU) +#define EQDC_REV_REV_SHIFT (0U) +/*! REV - REV */ +#define EQDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << EQDC_REV_REV_SHIFT)) & EQDC_REV_REV_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization Register */ +/*! @{ */ + +#define EQDC_UINIT_INIT_MASK (0xFFFFU) +#define EQDC_UINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define EQDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UINIT_INIT_SHIFT)) & EQDC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization Register */ +/*! @{ */ + +#define EQDC_LINIT_INIT_MASK (0xFFFFU) +#define EQDC_LINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define EQDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LINIT_INIT_SHIFT)) & EQDC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus Register */ +/*! @{ */ + +#define EQDC_UMOD_MOD_MASK (0xFFFFU) +#define EQDC_UMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define EQDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UMOD_MOD_SHIFT)) & EQDC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus Register */ +/*! @{ */ + +#define EQDC_LMOD_MOD_MASK (0xFFFFU) +#define EQDC_LMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define EQDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LMOD_MOD_SHIFT)) & EQDC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP0 - Upper Position Compare Register 0 */ +/*! @{ */ + +#define EQDC_UCOMP0_UCOMP0_MASK (0xFFFFU) +#define EQDC_UCOMP0_UCOMP0_SHIFT (0U) +/*! UCOMP0 - UCOMP0 */ +#define EQDC_UCOMP0_UCOMP0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP0_UCOMP0_SHIFT)) & EQDC_UCOMP0_UCOMP0_MASK) +/*! @} */ + +/*! @name LCOMP0 - Lower Position Compare Register 0 */ +/*! @{ */ + +#define EQDC_LCOMP0_LCOMP0_MASK (0xFFFFU) +#define EQDC_LCOMP0_LCOMP0_SHIFT (0U) +/*! LCOMP0 - LCOMP0 */ +#define EQDC_LCOMP0_LCOMP0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP0_LCOMP0_SHIFT)) & EQDC_LCOMP0_LCOMP0_MASK) +/*! @} */ + +/*! @name UCOMP1 - Upper Position Compare 1 */ +/*! @{ */ + +#define EQDC_UCOMP1_UCOMP1_MASK (0xFFFFU) +#define EQDC_UCOMP1_UCOMP1_SHIFT (0U) +/*! UCOMP1 - UCOMP1 */ +#define EQDC_UCOMP1_UCOMP1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP1_UCOMP1_SHIFT)) & EQDC_UCOMP1_UCOMP1_MASK) +/*! @} */ + +/*! @name UPOSH1 - Upper Position Holder Register 1 */ +/*! @{ */ + +#define EQDC_UPOSH1_UPOSH1_MASK (0xFFFFU) +#define EQDC_UPOSH1_UPOSH1_SHIFT (0U) +/*! UPOSH1 - UPOSH1 */ +#define EQDC_UPOSH1_UPOSH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH1_UPOSH1_SHIFT)) & EQDC_UPOSH1_UPOSH1_MASK) +/*! @} */ + +/*! @name LCOMP1 - Lower Position Compare 1 */ +/*! @{ */ + +#define EQDC_LCOMP1_LCOMP1_MASK (0xFFFFU) +#define EQDC_LCOMP1_LCOMP1_SHIFT (0U) +/*! LCOMP1 - LCOMP1 */ +#define EQDC_LCOMP1_LCOMP1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP1_LCOMP1_SHIFT)) & EQDC_LCOMP1_LCOMP1_MASK) +/*! @} */ + +/*! @name LPOSH1 - Lower Position Holder Register 1 */ +/*! @{ */ + +#define EQDC_LPOSH1_LPOSH1_MASK (0xFFFFU) +#define EQDC_LPOSH1_LPOSH1_SHIFT (0U) +/*! LPOSH1 - LPOSH1 */ +#define EQDC_LPOSH1_LPOSH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH1_LPOSH1_SHIFT)) & EQDC_LPOSH1_LPOSH1_MASK) +/*! @} */ + +/*! @name UCOMP2 - Upper Position Compare 2 */ +/*! @{ */ + +#define EQDC_UCOMP2_UCOMP2_MASK (0xFFFFU) +#define EQDC_UCOMP2_UCOMP2_SHIFT (0U) +/*! UCOMP2 - UCOMP2 */ +#define EQDC_UCOMP2_UCOMP2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP2_UCOMP2_SHIFT)) & EQDC_UCOMP2_UCOMP2_MASK) +/*! @} */ + +/*! @name UPOSH2 - Upper Position Holder Register 3 */ +/*! @{ */ + +#define EQDC_UPOSH2_UPOSH2_MASK (0xFFFFU) +#define EQDC_UPOSH2_UPOSH2_SHIFT (0U) +/*! UPOSH2 - UPOSH2 */ +#define EQDC_UPOSH2_UPOSH2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH2_UPOSH2_SHIFT)) & EQDC_UPOSH2_UPOSH2_MASK) +/*! @} */ + +/*! @name LCOMP2 - Lower Position Compare 2 */ +/*! @{ */ + +#define EQDC_LCOMP2_LCOMP2_MASK (0xFFFFU) +#define EQDC_LCOMP2_LCOMP2_SHIFT (0U) +/*! LCOMP2 - LCOMP2 */ +#define EQDC_LCOMP2_LCOMP2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP2_LCOMP2_SHIFT)) & EQDC_LCOMP2_LCOMP2_MASK) +/*! @} */ + +/*! @name LPOSH2 - Lower Position Holder Register 2 */ +/*! @{ */ + +#define EQDC_LPOSH2_LPOSH2_MASK (0xFFFFU) +#define EQDC_LPOSH2_LPOSH2_SHIFT (0U) +/*! LPOSH2 - LPOSH2 */ +#define EQDC_LPOSH2_LPOSH2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH2_LPOSH2_SHIFT)) & EQDC_LPOSH2_LPOSH2_MASK) +/*! @} */ + +/*! @name UCOMP3 - Upper Position Compare 3 */ +/*! @{ */ + +#define EQDC_UCOMP3_UCOMP3_MASK (0xFFFFU) +#define EQDC_UCOMP3_UCOMP3_SHIFT (0U) +/*! UCOMP3 - UCOMP3 */ +#define EQDC_UCOMP3_UCOMP3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP3_UCOMP3_SHIFT)) & EQDC_UCOMP3_UCOMP3_MASK) +/*! @} */ + +/*! @name UPOSH3 - Upper Position Holder Register 3 */ +/*! @{ */ + +#define EQDC_UPOSH3_UPOSH3_MASK (0xFFFFU) +#define EQDC_UPOSH3_UPOSH3_SHIFT (0U) +/*! UPOSH3 - UPOSH3 */ +#define EQDC_UPOSH3_UPOSH3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH3_UPOSH3_SHIFT)) & EQDC_UPOSH3_UPOSH3_MASK) +/*! @} */ + +/*! @name LCOMP3 - Lower Position Compare 3 */ +/*! @{ */ + +#define EQDC_LCOMP3_LCOMP3_MASK (0xFFFFU) +#define EQDC_LCOMP3_LCOMP3_SHIFT (0U) +/*! LCOMP3 - LCOMP3 */ +#define EQDC_LCOMP3_LCOMP3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP3_LCOMP3_SHIFT)) & EQDC_LCOMP3_LCOMP3_MASK) +/*! @} */ + +/*! @name LPOSH3 - Lower Position Holder Register 3 */ +/*! @{ */ + +#define EQDC_LPOSH3_LPOSH3_MASK (0xFFFFU) +#define EQDC_LPOSH3_LPOSH3_SHIFT (0U) +/*! LPOSH3 - LPOSH3 */ +#define EQDC_LPOSH3_LPOSH3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH3_LPOSH3_SHIFT)) & EQDC_LPOSH3_LPOSH3_MASK) +/*! @} */ + +/*! @name INTCTRL - Interrupt Control Register */ +/*! @{ */ + +#define EQDC_INTCTRL_SABIE_MASK (0x1U) +#define EQDC_INTCTRL_SABIE_SHIFT (0U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_SABIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIE_SHIFT)) & EQDC_INTCTRL_SABIE_MASK) + +#define EQDC_INTCTRL_SABIRQ_MASK (0x2U) +#define EQDC_INTCTRL_SABIRQ_SHIFT (1U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred + */ +#define EQDC_INTCTRL_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIRQ_SHIFT)) & EQDC_INTCTRL_SABIRQ_MASK) + +#define EQDC_INTCTRL_DIRIE_MASK (0x4U) +#define EQDC_INTCTRL_DIRIE_SHIFT (2U) +/*! DIRIE - Count direction change interrupt enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_DIRIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIE_SHIFT)) & EQDC_INTCTRL_DIRIE_MASK) + +#define EQDC_INTCTRL_DIRIRQ_MASK (0x8U) +#define EQDC_INTCTRL_DIRIRQ_SHIFT (3U) +/*! DIRIRQ - Count direction change interrupt + * 0b0..Count direction unchanged + * 0b1..Count direction changed + */ +#define EQDC_INTCTRL_DIRIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIRQ_SHIFT)) & EQDC_INTCTRL_DIRIRQ_MASK) + +#define EQDC_INTCTRL_RUIE_MASK (0x10U) +#define EQDC_INTCTRL_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_RUIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIE_SHIFT)) & EQDC_INTCTRL_RUIE_MASK) + +#define EQDC_INTCTRL_RUIRQ_MASK (0x20U) +#define EQDC_INTCTRL_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define EQDC_INTCTRL_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIRQ_SHIFT)) & EQDC_INTCTRL_RUIRQ_MASK) + +#define EQDC_INTCTRL_ROIE_MASK (0x40U) +#define EQDC_INTCTRL_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_ROIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIE_SHIFT)) & EQDC_INTCTRL_ROIE_MASK) + +#define EQDC_INTCTRL_ROIRQ_MASK (0x80U) +#define EQDC_INTCTRL_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ +#define EQDC_INTCTRL_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIRQ_SHIFT)) & EQDC_INTCTRL_ROIRQ_MASK) + +#define EQDC_INTCTRL_CMP0IE_MASK (0x100U) +#define EQDC_INTCTRL_CMP0IE_SHIFT (8U) +/*! CMP0IE - Compare 0 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP0IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IE_SHIFT)) & EQDC_INTCTRL_CMP0IE_MASK) + +#define EQDC_INTCTRL_CMP0IRQ_MASK (0x200U) +#define EQDC_INTCTRL_CMP0IRQ_SHIFT (9U) +/*! CMP0IRQ - Compare 0 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP0 value) + * 0b1..COMP match has occurred (the position counter matches the COMP0 value) + */ +#define EQDC_INTCTRL_CMP0IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IRQ_SHIFT)) & EQDC_INTCTRL_CMP0IRQ_MASK) + +#define EQDC_INTCTRL_CMP1IE_MASK (0x400U) +#define EQDC_INTCTRL_CMP1IE_SHIFT (10U) +/*! CMP1IE - Compare1 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP1IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IE_SHIFT)) & EQDC_INTCTRL_CMP1IE_MASK) + +#define EQDC_INTCTRL_CMP1IRQ_MASK (0x800U) +#define EQDC_INTCTRL_CMP1IRQ_SHIFT (11U) +/*! CMP1IRQ - Compare1 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP1 value) + * 0b1..COMP1 match has occurred (the position counter matches the COMP1 value) + */ +#define EQDC_INTCTRL_CMP1IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IRQ_SHIFT)) & EQDC_INTCTRL_CMP1IRQ_MASK) + +#define EQDC_INTCTRL_CMP2IE_MASK (0x1000U) +#define EQDC_INTCTRL_CMP2IE_SHIFT (12U) +/*! CMP2IE - Compare2 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP2IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IE_SHIFT)) & EQDC_INTCTRL_CMP2IE_MASK) + +#define EQDC_INTCTRL_CMP2IRQ_MASK (0x2000U) +#define EQDC_INTCTRL_CMP2IRQ_SHIFT (13U) +/*! CMP2IRQ - Compare2 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP2 value) + * 0b1..COMP2 match has occurred (the position counter matches the COMP2 value) + */ +#define EQDC_INTCTRL_CMP2IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IRQ_SHIFT)) & EQDC_INTCTRL_CMP2IRQ_MASK) + +#define EQDC_INTCTRL_CMP3IE_MASK (0x4000U) +#define EQDC_INTCTRL_CMP3IE_SHIFT (14U) +/*! CMP3IE - Compare3 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP3IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IE_SHIFT)) & EQDC_INTCTRL_CMP3IE_MASK) + +#define EQDC_INTCTRL_CMP3IRQ_MASK (0x8000U) +#define EQDC_INTCTRL_CMP3IRQ_SHIFT (15U) +/*! CMP3IRQ - Compare3 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP3 value) + * 0b1..COMP3 match has occurred (the position counter matches the COMP3 value) + */ +#define EQDC_INTCTRL_CMP3IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IRQ_SHIFT)) & EQDC_INTCTRL_CMP3IRQ_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ + +#define EQDC_WTR_WDOG_MASK (0xFFFFU) +#define EQDC_WTR_WDOG_SHIFT (0U) +/*! WDOG - WDOG */ +#define EQDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << EQDC_WTR_WDOG_SHIFT)) & EQDC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor Register */ +/*! @{ */ + +#define EQDC_IMR_HOME_ENABLE_MASK (0x1U) +#define EQDC_IMR_HOME_ENABLE_SHIFT (0U) +/*! HOME_ENABLE - HOME_ENABLE */ +#define EQDC_IMR_HOME_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_HOME_ENABLE_SHIFT)) & EQDC_IMR_HOME_ENABLE_MASK) + +#define EQDC_IMR_INDEX_PRESET_MASK (0x2U) +#define EQDC_IMR_INDEX_PRESET_SHIFT (1U) +/*! INDEX_PRESET - INDEX_PRESET */ +#define EQDC_IMR_INDEX_PRESET(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_INDEX_PRESET_SHIFT)) & EQDC_IMR_INDEX_PRESET_MASK) + +#define EQDC_IMR_PHB_MASK (0x4U) +#define EQDC_IMR_PHB_SHIFT (2U) +/*! PHB - PHB */ +#define EQDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHB_SHIFT)) & EQDC_IMR_PHB_MASK) + +#define EQDC_IMR_PHA_MASK (0x8U) +#define EQDC_IMR_PHA_SHIFT (3U) +/*! PHA - PHA */ +#define EQDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHA_SHIFT)) & EQDC_IMR_PHA_MASK) + +#define EQDC_IMR_FHOM_ENA_MASK (0x10U) +#define EQDC_IMR_FHOM_ENA_SHIFT (4U) +/*! FHOM_ENA - filter operation on HOME/ENABLE input */ +#define EQDC_IMR_FHOM_ENA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FHOM_ENA_SHIFT)) & EQDC_IMR_FHOM_ENA_MASK) + +#define EQDC_IMR_FIND_PRE_MASK (0x20U) +#define EQDC_IMR_FIND_PRE_SHIFT (5U) +/*! FIND_PRE - filter operation on INDEX/PRESET input */ +#define EQDC_IMR_FIND_PRE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FIND_PRE_SHIFT)) & EQDC_IMR_FIND_PRE_MASK) + +#define EQDC_IMR_FPHB_MASK (0x40U) +#define EQDC_IMR_FPHB_SHIFT (6U) +/*! FPHB - filter operation on PHASEB input */ +#define EQDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHB_SHIFT)) & EQDC_IMR_FPHB_MASK) + +#define EQDC_IMR_FPHA_MASK (0x80U) +#define EQDC_IMR_FPHA_SHIFT (7U) +/*! FPHA - filter operation on PHASEA input */ +#define EQDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHA_SHIFT)) & EQDC_IMR_FPHA_MASK) + +#define EQDC_IMR_CMPF0_MASK (0x100U) +#define EQDC_IMR_CMPF0_SHIFT (8U) +/*! CMPF0 - Position Compare 0 Flag Output + * 0b0..When the position counter is less than value of COMP0 register + * 0b1..When the position counter is greater or equal than value of COMP0 register + */ +#define EQDC_IMR_CMPF0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMPF0_SHIFT)) & EQDC_IMR_CMPF0_MASK) + +#define EQDC_IMR_CMP1F_MASK (0x200U) +#define EQDC_IMR_CMP1F_SHIFT (9U) +/*! CMP1F - Position Compare1 Flag Output + * 0b0..When the position counter is less than value of COMP1 register + * 0b1..When the position counter is greater or equal than value of COMP1 register + */ +#define EQDC_IMR_CMP1F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP1F_SHIFT)) & EQDC_IMR_CMP1F_MASK) + +#define EQDC_IMR_CMP2F_MASK (0x400U) +#define EQDC_IMR_CMP2F_SHIFT (10U) +/*! CMP2F - Position Compare2 Flag Output + * 0b0..When the position counter is less than value of COMP2 register + * 0b1..When the position counter is greater or equal than value of COMP2 register + */ +#define EQDC_IMR_CMP2F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP2F_SHIFT)) & EQDC_IMR_CMP2F_MASK) + +#define EQDC_IMR_CMP3F_MASK (0x800U) +#define EQDC_IMR_CMP3F_SHIFT (11U) +/*! CMP3F - Position Compare3 Flag Output + * 0b0..When the position counter value is less than value of COMP3 register + * 0b1..When the position counter is greater or equal than value of COMP3 register + */ +#define EQDC_IMR_CMP3F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP3F_SHIFT)) & EQDC_IMR_CMP3F_MASK) + +#define EQDC_IMR_DIRH_MASK (0x4000U) +#define EQDC_IMR_DIRH_SHIFT (14U) +/*! DIRH - Count Direction Flag Hold */ +#define EQDC_IMR_DIRH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIRH_SHIFT)) & EQDC_IMR_DIRH_MASK) + +#define EQDC_IMR_DIR_MASK (0x8000U) +#define EQDC_IMR_DIR_SHIFT (15U) +/*! DIR - Count Direction Flag Output + * 0b0..Current count was in the down direction + * 0b1..Current count was in the up direction + */ +#define EQDC_IMR_DIR(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIR_SHIFT)) & EQDC_IMR_DIR_MASK) +/*! @} */ + +/*! @name TST - Test Register */ +/*! @{ */ + +#define EQDC_TST_TEST_COUNT_MASK (0xFFU) +#define EQDC_TST_TEST_COUNT_SHIFT (0U) +/*! TEST_COUNT - TEST_COUNT */ +#define EQDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_COUNT_SHIFT)) & EQDC_TST_TEST_COUNT_MASK) + +#define EQDC_TST_TEST_PERIOD_MASK (0x1F00U) +#define EQDC_TST_TEST_PERIOD_SHIFT (8U) +/*! TEST_PERIOD - TEST_PERIOD */ +#define EQDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_PERIOD_SHIFT)) & EQDC_TST_TEST_PERIOD_MASK) + +#define EQDC_TST_QDN_MASK (0x2000U) +#define EQDC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Generates a positive quadrature decoder signal + * 0b1..Generates a negative quadrature decoder signal + */ +#define EQDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_QDN_SHIFT)) & EQDC_TST_QDN_MASK) + +#define EQDC_TST_TCE_MASK (0x4000U) +#define EQDC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TCE_SHIFT)) & EQDC_TST_TCE_MASK) + +#define EQDC_TST_TEN_MASK (0x8000U) +#define EQDC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEN_SHIFT)) & EQDC_TST_TEN_MASK) +/*! @} */ + +/*! @name UVERID - Upper VERID */ +/*! @{ */ + +#define EQDC_UVERID_UVERID_MASK (0xFFFFU) +#define EQDC_UVERID_UVERID_SHIFT (0U) +/*! UVERID - UVERID */ +#define EQDC_UVERID_UVERID(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UVERID_UVERID_SHIFT)) & EQDC_UVERID_UVERID_MASK) +/*! @} */ + +/*! @name LVERID - Lower VERID */ +/*! @{ */ + +#define EQDC_LVERID_LVERID_MASK (0xFFFFU) +#define EQDC_LVERID_LVERID_SHIFT (0U) +/*! LVERID - LVERID */ +#define EQDC_LVERID_LVERID(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LVERID_LVERID_SHIFT)) & EQDC_LVERID_LVERID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EQDC_Register_Masks */ + + +/*! + * @} + */ /* end of group EQDC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_EQDC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_ERM.h new file mode 100644 index 000000000..269aa0b2a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_ERM.h @@ -0,0 +1,333 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for ERM +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_ERM.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for ERM + * + * CMSIS Peripheral Access Layer for ERM + */ + +#if !defined(PERI_ERM_H_) +#define PERI_ERM_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +#if !defined(ERM_MEMORY_CHANNEL_T_) +#define ERM_MEMORY_CHANNEL_T_ +/*! + * @addtogroup erm_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the erm_memory_channel + * + * Defines the structure for the ERM resource collections. + */ + +typedef enum _erm_memory_channel +{ + kERM_MemoryChannelRAMA0 = 0U, /**< Memory RAMA0 */ + kERM_MemoryChannelFLASH = 1U, /**< Memory FLASH */ +} erm_memory_channel_t; + +/* @} */ +#endif /* ERM_MEMORY_CHANNEL_T_ */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ERM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer + * @{ + */ + +/** ERM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ + uint8_t RESERVED_1[236]; + __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */ + __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */ + __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ +} ERM_Type; + +/* ---------------------------------------------------------------------------- + -- ERM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Register_Masks ERM Register Masks + * @{ + */ + +/*! @name CR0 - ERM Configuration Register 0 */ +/*! @{ */ + +#define ERM_CR0_ENCIE1_MASK (0x4000000U) +#define ERM_CR0_ENCIE1_SHIFT (26U) +/*! ENCIE1 - ENCIE1 + * 0b0..Interrupt notification of Memory 1 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 1 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) + +#define ERM_CR0_ESCIE1_MASK (0x8000000U) +#define ERM_CR0_ESCIE1_SHIFT (27U) +/*! ESCIE1 - ESCIE1 + * 0b0..Interrupt notification of Memory 1 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 1 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) + +#define ERM_CR0_ENCIE0_MASK (0x40000000U) +#define ERM_CR0_ENCIE0_SHIFT (30U) +/*! ENCIE0 - ENCIE0 + * 0b0..Interrupt notification of Memory 0 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 0 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) + +#define ERM_CR0_ESCIE0_MASK (0x80000000U) +#define ERM_CR0_ESCIE0_SHIFT (31U) +/*! ESCIE0 - ESCIE0 + * 0b0..Interrupt notification of Memory 0 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 0 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) +/*! @} */ + +/*! @name SR0 - ERM Status Register 0 */ +/*! @{ */ + +#define ERM_SR0_NCE1_MASK (0x4000000U) +#define ERM_SR0_NCE1_SHIFT (26U) +/*! NCE1 - NCE1 + * 0b0..No non-correctable error event on Memory 1 detected. + * 0b1..Non-correctable error event on Memory 1 detected. + */ +#define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) + +#define ERM_SR0_SBC1_MASK (0x8000000U) +#define ERM_SR0_SBC1_SHIFT (27U) +/*! SBC1 - SBC1 + * 0b0..No single-bit correction event on Memory 1 detected. + * 0b1..Single-bit correction event on Memory 1 detected. + */ +#define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) + +#define ERM_SR0_NCE0_MASK (0x40000000U) +#define ERM_SR0_NCE0_SHIFT (30U) +/*! NCE0 - NCE0 + * 0b0..No non-correctable error event on Memory 0 detected. + * 0b1..Non-correctable error event on Memory 0 detected. + */ +#define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) + +#define ERM_SR0_SBC0_MASK (0x80000000U) +#define ERM_SR0_SBC0_SHIFT (31U) +/*! SBC0 - SBC0 + * 0b0..No single-bit correction event on Memory 0 detected. + * 0b1..Single-bit correction event on Memory 0 detected. + */ +#define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) +/*! @} */ + +/*! @name EAR0 - ERM Memory 0 Error Address Register */ +/*! @{ */ + +#define ERM_EAR0_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR0_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK) +/*! @} */ + +/*! @name SYN0 - ERM Memory 0 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN0_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN0_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ERM_Register_Masks */ + + +/*! + * @} + */ /* end of group ERM_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_ERM_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FLEXIO.h new file mode 100644 index 000000000..96a840351 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FLEXIO.h @@ -0,0 +1,945 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for FLEXIO +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_FLEXIO.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for FLEXIO + * + * CMSIS Peripheral Access Layer for FLEXIO + */ + +#if !defined(PERI_FLEXIO_H_) +#define PERI_FLEXIO_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Size of Registers Arrays */ +#define FLEXIO_SHIFTCTL_COUNT 4u +#define FLEXIO_SHIFTCFG_COUNT 4u +#define FLEXIO_SHIFTBUF_COUNT 4u +#define FLEXIO_SHIFTBUFBIS_COUNT 4u +#define FLEXIO_SHIFTBUFBYS_COUNT 4u +#define FLEXIO_SHIFTBUFBBS_COUNT 4u +#define FLEXIO_TIMCTL_COUNT 4u +#define FLEXIO_TIMCFG_COUNT 4u +#define FLEXIO_TIMCMP_COUNT 4u +#define FLEXIO_SHIFTBUFNBS_COUNT 4u +#define FLEXIO_SHIFTBUFHWS_COUNT 4u +#define FLEXIO_SHIFTBUFNIS_COUNT 4u +#define FLEXIO_SHIFTBUFOES_COUNT 4u +#define FLEXIO_SHIFTBUFEOS_COUNT 4u +#define FLEXIO_SHIFTBUFHBS_COUNT 4u + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ + uint8_t RESERVED_4[4]; + __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ + __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ + __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ + __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ + __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ + __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ + __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ + __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ + __IO uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __IO uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __IO uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __IO uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SHIFTCTL[FLEXIO_SHIFTCTL_COUNT]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __IO uint32_t SHIFTCFG[FLEXIO_SHIFTCFG_COUNT]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_7[240]; + __IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __IO uint32_t SHIFTBUFBYS[FLEXIO_SHIFTBUFBYS_COUNT]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __IO uint32_t SHIFTBUFBBS[FLEXIO_SHIFTBUFBBS_COUNT]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_11[112]; + __IO uint32_t TIMCTL[FLEXIO_TIMCTL_COUNT]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_12[112]; + __IO uint32_t TIMCFG[FLEXIO_TIMCFG_COUNT]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_13[112]; + __IO uint32_t TIMCMP[FLEXIO_TIMCMP_COUNT]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_14[368]; + __IO uint32_t SHIFTBUFNBS[FLEXIO_SHIFTBUFNBS_COUNT]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_15[112]; + __IO uint32_t SHIFTBUFHWS[FLEXIO_SHIFTBUFHWS_COUNT]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_16[112]; + __IO uint32_t SHIFTBUFNIS[FLEXIO_SHIFTBUFNIS_COUNT]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ + uint8_t RESERVED_17[112]; + __IO uint32_t SHIFTBUFOES[FLEXIO_SHIFTBUFOES_COUNT]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_18[112]; + __IO uint32_t SHIFTBUFEOS[FLEXIO_SHIFTBUFEOS_COUNT]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_19[112]; + __IO uint32_t SHIFTBUFHBS[FLEXIO_SHIFTBUFHBS_COUNT]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..State, logic, and parallel modes supported + * 0b0000000000000010..Pin control registers supported + * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) + +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) + +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +/*! SHIFTER - Shifter Number */ +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) + +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +/*! TIMER - Timer Number */ +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) + +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +/*! PIN - Pin Number */ +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) + +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger Number */ +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FLEXIO Control */ +/*! @{ */ + +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FLEXIO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) + +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) + +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Normal + * 0b1..Fast + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) + +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) + +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State */ +/*! @{ */ + +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +/*! PDI - Pin Data Input */ +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status */ +/*! @{ */ + +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +/*! SSF - Shifter Status Flag + * 0b0000..Clear + * 0b0000..No effect + * 0b0001..Clear the flag + * 0b0001..Set + */ +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error */ +/*! @{ */ + +#define FLEXIO_SHIFTERR_SEF_MASK (0xFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +/*! SEF - Shifter Error Flag + * 0b0000..Clear + * 0b0000..No effect + * 0b0001..Clear the flag + * 0b0001..Set + */ +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Flag */ +/*! @{ */ + +#define FLEXIO_TIMSTAT_TSF_MASK (0xFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +/*! TSF - Timer Status Flag + * 0b0000..Clear + * 0b0000..No effect + * 0b0001..Clear the flag + * 0b0001..Set + */ +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +/*! SSIE - Shifter Status Interrupt Enable */ +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +/*! SEIE - Shifter Error Interrupt Enable */ +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TIMIEN_TEIE_MASK (0xFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +/*! TEIE - Timer Status Interrupt Enable */ +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +/*! SSDE - Shifter Status DMA Enable */ +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name TIMERSDEN - Timer Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFU) +#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) +/*! TSDE - Timer Status DMA Enable */ +#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State */ +/*! @{ */ + +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +/*! STATE - Current State Pointer */ +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name TRGSTAT - Trigger Status */ +/*! @{ */ + +#define FLEXIO_TRGSTAT_ETSF_MASK (0xFU) +#define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) +/*! ETSF - External Trigger Status Flag + * 0b0000..Clear + * 0b0000..No effect + * 0b0001..Clear the flag + * 0b0001..Set + */ +#define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) +/*! @} */ + +/*! @name TRIGIEN - External Trigger Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TRIGIEN_TRIE_MASK (0xFU) +#define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) +/*! TRIE - External Trigger Interrupt Enable */ +#define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) +/*! @} */ + +/*! @name PINSTAT - Pin Status */ +/*! @{ */ + +#define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) +#define FLEXIO_PINSTAT_PSF_SHIFT (0U) +/*! PSF - Pin Status Flag + * 0b00000000000000000000000000000000..Clear + * 0b00000000000000000000000000000000..No effect + * 0b00000000000000000000000000000001..Clear the flag + * 0b00000000000000000000000000000001..Set + */ +#define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) +/*! @} */ + +/*! @name PINIEN - Pin Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINIEN_PSIE_SHIFT (0U) +/*! PSIE - Pin Status Interrupt Enable */ +#define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) +/*! @} */ + +/*! @name PINREN - Pin Rising Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINREN_PRE_SHIFT (0U) +/*! PRE - Pin Rising Edge */ +#define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) +/*! @} */ + +/*! @name PINFEN - Pin Falling Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINFEN_PFE_SHIFT (0U) +/*! PFE - Pin Falling Edge */ +#define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) +/*! @} */ + +/*! @name PINOUTD - Pin Output Data */ +/*! @{ */ + +#define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTD_OUTD_SHIFT (0U) +/*! OUTD - Output Data */ +#define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) +/*! @} */ + +/*! @name PINOUTE - Pin Output Enable */ +/*! @{ */ + +#define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTE_OUTE_SHIFT (0U) +/*! OUTE - Output Enable */ +#define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) +/*! @} */ + +/*! @name PINOUTDIS - Pin Output Disable */ +/*! @{ */ + +#define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) +/*! OUTDIS - Output Disable */ +#define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) +/*! @} */ + +/*! @name PINOUTCLR - Pin Output Clear */ +/*! @{ */ + +#define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) +/*! OUTCLR - Output Clear */ +#define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) +/*! @} */ + +/*! @name PINOUTSET - Pin Output Set */ +/*! @{ */ + +#define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) +/*! OUTSET - Output Set */ +#define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) +/*! @} */ + +/*! @name PINOUTTOG - Pin Output Toggle */ +/*! @{ */ + +#define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) +/*! OUTTOG - Output Toggle */ +#define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control */ +/*! @{ */ + +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disable + * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer + * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer + * 0b011..Reserved + * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer + * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents + * 0b110..State mode; SHIFTBUF contents store programmable state attributes + * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) + +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) + +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Shifter Pin Select */ +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) + +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open-drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) + +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Positive edge + * 0b1..Negative edge + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) + +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +/*! TIMSEL - Timer Select */ +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/*! @name SHIFTCFG - Shifter Configuration */ +/*! @{ */ + +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start + * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable + * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift + * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, + * Receiver and Match Store modes set error flag + * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, + * Receiver and Match Store modes set error flag + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) + +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop + * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes + * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, + * Receiver and Match Store modes store receive data on the configured shift edge + * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) + +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter n+1 output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) + +#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) +#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) +/*! LATST - Late Store + * 0b0..Store the pre-shift register state + * 0b1..Store the post-shift register state + */ +#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) + +#define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) +#define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) +/*! SSIZE - Shifter Size + * 0b0..32-bit + * 0b1..24-bit + */ +#define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) + +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +/*! PWIDTH - Parallel Width */ +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/*! @name SHIFTBUF - Shifter Buffer */ +/*! @{ */ + +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +/*! SHIFTBUF - Shift Buffer */ +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +/*! SHIFTBUFBIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +/*! SHIFTBUFBYS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +/*! SHIFTBUFBBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/*! @name TIMCTL - Timer Control */ +/*! @{ */ + +#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b000..Timer disabled + * 0b001..Dual 8-bit counters baud mode + * 0b010..Dual 8-bit counters PWM high mode + * 0b011..Single 16-bit counter mode + * 0b100..Single 16-bit counter disable mode + * 0b101..Dual 8-bit counters word mode + * 0b110..Dual 8-bit counters PWM low mode + * 0b111..Single 16-bit input capture mode + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) + +#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) +#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) +/*! ONETIM - Timer One Time Operation + * 0b0..Generate the timer enable event as normal + * 0b1..Block the timer enable event unless the timer status flag is clear + */ +#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) + +#define FLEXIO_TIMCTL_PININS_MASK (0x40U) +#define FLEXIO_TIMCTL_PININS_SHIFT (6U) +/*! PININS - Timer Pin Input Select + * 0b0..PINSEL selects timer pin input and output + * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL + */ +#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) + +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) + +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Timer Pin Select */ +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) + +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open-drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) + +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External + * 0b1..Internal + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) + +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) + +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select */ +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/*! @name TIMCFG - Timer Configuration */ +/*! @{ */ + +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) + +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop + * 0b00..Disabled + * 0b01..Enabled on timer compare + * 0b10..Enabled on timer disable + * 0b11..Enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) + +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on timer n-1 enable + * 0b010..Timer enabled on trigger high + * 0b011..Timer enabled on trigger high and pin high + * 0b100..Timer enabled on pin rising edge + * 0b101..Timer enabled on pin rising edge and trigger high + * 0b110..Timer enabled on trigger rising edge + * 0b111..Timer enabled on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) + +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on timer n-1 disable + * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) + * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low + * 0b100..Timer disabled on pin rising or falling edge + * 0b101..Timer disabled on pin rising or falling edge provided trigger is high + * 0b110..Timer disabled on trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) + +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Never reset timer + * 0b001..Timer reset on timer output high. + * 0b010..Timer reset on timer pin equal to timer output + * 0b011..Timer reset on timer trigger equal to timer output + * 0b100..Timer reset on timer pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on trigger rising edge + * 0b111..Timer reset on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) + +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output + * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output + * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input + * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input + * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output + * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output + * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input + * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) + +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Logic one when enabled; not affected by timer reset + * 0b01..Logic zero when enabled; not affected by timer reset + * 0b10..Logic one when enabled and on timer reset + * 0b11..Logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/*! @name TIMCMP - Timer Compare */ +/*! @{ */ + +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +/*! CMP - Timer Compare Value */ +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +/*! SHIFTBUFNBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +/*! SHIFTBUFHWS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +/*! SHIFTBUFNIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) +/*! SHIFTBUFOES - Shift Buffer */ +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) +/*! @} */ + +/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) +/*! SHIFTBUFEOS - Shift Buffer */ +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) +/*! @} */ + +/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) +/*! SHIFTBUFHBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FLEXIO_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FMC.h new file mode 100644 index 000000000..56ffb3b34 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FMC.h @@ -0,0 +1,309 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for FMC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_FMC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for FMC + * + * CMSIS Peripheral Access Layer for FMC + */ + +#if !defined(PERI_FMC_H_) +#define PERI_FMC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t REMAP; /**< Data Remap, offset: 0x20 */ + uint8_t RESERVED_1[988]; + __IO uint32_t FCCR; /**< Flash Cache Control Register, offset: 0x400 */ + __IO uint32_t FCAR; /**< Flash Cache Access Register, offset: 0x404 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FCTG; /**< Flash Cache Tag, offset: 0x40C */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCLN0; /**< Flash Cache Line Num0, offset: 0x420 */ + __IO uint32_t FCLN1; /**< Flash Cache Line Num1, offset: 0x424 */ + __IO uint32_t FCLN2; /**< Flash Cache Line Num2, offset: 0x428 */ + __IO uint32_t FCLN3; /**< Flash Cache Line Num3, offset: 0x42C */ +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/*! @name REMAP - Data Remap */ +/*! @{ */ + +#define FMC_REMAP_REMAPLK_MASK (0x1U) +#define FMC_REMAP_REMAPLK_SHIFT (0U) +/*! REMAPLK - Remap Lock Enable + * 0b0..Lock disabled: can write to REMAP + * 0b1..Lock enabled: cannot write to REMAP + */ +#define FMC_REMAP_REMAPLK(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_REMAPLK_SHIFT)) & FMC_REMAP_REMAPLK_MASK) + +#define FMC_REMAP_LIM_MASK (0x7F0000U) +#define FMC_REMAP_LIM_SHIFT (16U) +/*! LIM - LIM Remapping Address */ +#define FMC_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIM_SHIFT)) & FMC_REMAP_LIM_MASK) + +#define FMC_REMAP_LIMDP_MASK (0x7F000000U) +#define FMC_REMAP_LIMDP_SHIFT (24U) +/*! LIMDP - LIMDP Remapping Address */ +#define FMC_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIMDP_SHIFT)) & FMC_REMAP_LIMDP_MASK) +/*! @} */ + +/*! @name FCCR - Flash Cache Control Register */ +/*! @{ */ + +#define FMC_FCCR_WAY_LOCK_MASK (0xFU) +#define FMC_FCCR_WAY_LOCK_SHIFT (0U) +/*! WAY_LOCK - Cache Way Lock */ +#define FMC_FCCR_WAY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCCR_WAY_LOCK_SHIFT)) & FMC_FCCR_WAY_LOCK_MASK) + +#define FMC_FCCR_LOCK_MASK (0x80000000U) +#define FMC_FCCR_LOCK_SHIFT (31U) +/*! LOCK - Lock Flash Cache Control + * 0b0..Unlock flash cache + * 0b1..Lock flash cache + */ +#define FMC_FCCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCCR_LOCK_SHIFT)) & FMC_FCCR_LOCK_MASK) +/*! @} */ + +/*! @name FCAR - Flash Cache Access Register */ +/*! @{ */ + +#define FMC_FCAR_CACHES_WAY_NUM_MASK (0x3U) +#define FMC_FCAR_CACHES_WAY_NUM_SHIFT (0U) +/*! CACHES_WAY_NUM - Flash Cache Way Number + * 0b00..way0 + * 0b01..way1 + * 0b10..way2 + * 0b11..way3 + */ +#define FMC_FCAR_CACHES_WAY_NUM(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCAR_CACHES_WAY_NUM_SHIFT)) & FMC_FCAR_CACHES_WAY_NUM_MASK) + +#define FMC_FCAR_CACHES_SET_NUM_MASK (0x10U) +#define FMC_FCAR_CACHES_SET_NUM_SHIFT (4U) +/*! CACHES_SET_NUM - Flash Cache Set Number */ +#define FMC_FCAR_CACHES_SET_NUM(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCAR_CACHES_SET_NUM_SHIFT)) & FMC_FCAR_CACHES_SET_NUM_MASK) + +#define FMC_FCAR_TYPE_MASK (0xC0000000U) +#define FMC_FCAR_TYPE_SHIFT (30U) +/*! TYPE - Operation of cache type + * 0b00..No access. + * 0b01..Read flash cache - the associated tag, valid and the content of the cache line specified by + * CACHES_SET_NUM and CACHES_WAY_NUM of FCAR are copied to FCTG and FCLN0-3. + * 0b10..Write flash cache - the associated tag, valid and the content of the flash cache line specified by + * CACHES_SET_NUM and CACHES_WAY_NUM of FCAR are modified based on FCTG and FCLN0-3. + * 0b11..No access. + */ +#define FMC_FCAR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCAR_TYPE_SHIFT)) & FMC_FCAR_TYPE_MASK) +/*! @} */ + +/*! @name FCTG - Flash Cache Tag */ +/*! @{ */ + +#define FMC_FCTG_VALID_MASK (0x1U) +#define FMC_FCTG_VALID_SHIFT (0U) +/*! VALID - Cache line Valid + * 0b0..Tag is invalid. Cache line's cache hit cannot be triggered by flash read operation. + * 0b1..Tag is valid. Cache line's cache hit can be triggered by flash read operation. + */ +#define FMC_FCTG_VALID(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTG_VALID_SHIFT)) & FMC_FCTG_VALID_MASK) + +#define FMC_FCTG_ADDRESS_MASK (0xFFFFC0U) +#define FMC_FCTG_ADDRESS_SHIFT (6U) +/*! ADDRESS - Cache line Tag, which corresponds to flash address[23:6] */ +#define FMC_FCTG_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTG_ADDRESS_SHIFT)) & FMC_FCTG_ADDRESS_MASK) +/*! @} */ + +/*! @name FCLN0 - Flash Cache Line Num0 */ +/*! @{ */ + +#define FMC_FCLN0_DATAWxSyLM_MASK (0xFFFFFFFFU) +#define FMC_FCLN0_DATAWxSyLM_SHIFT (0U) +/*! DATAWxSyLM - Cache Line Data[31:0] */ +#define FMC_FCLN0_DATAWxSyLM(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCLN0_DATAWxSyLM_SHIFT)) & FMC_FCLN0_DATAWxSyLM_MASK) +/*! @} */ + +/*! @name FCLN1 - Flash Cache Line Num1 */ +/*! @{ */ + +#define FMC_FCLN1_DATAWxSyML_MASK (0xFFFFFFFFU) +#define FMC_FCLN1_DATAWxSyML_SHIFT (0U) +/*! DATAWxSyML - Cache Line Data[63:32] */ +#define FMC_FCLN1_DATAWxSyML(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCLN1_DATAWxSyML_SHIFT)) & FMC_FCLN1_DATAWxSyML_MASK) +/*! @} */ + +/*! @name FCLN2 - Flash Cache Line Num2 */ +/*! @{ */ + +#define FMC_FCLN2_DATAWxSyMU_MASK (0xFFFFFFFFU) +#define FMC_FCLN2_DATAWxSyMU_SHIFT (0U) +/*! DATAWxSyMU - Cache Line Data[95:64] */ +#define FMC_FCLN2_DATAWxSyMU(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCLN2_DATAWxSyMU_SHIFT)) & FMC_FCLN2_DATAWxSyMU_MASK) +/*! @} */ + +/*! @name FCLN3 - Flash Cache Line Num3 */ +/*! @{ */ + +#define FMC_FCLN3_DATAWxSyUM_MASK (0xFFFFFFFFU) +#define FMC_FCLN3_DATAWxSyUM_SHIFT (0U) +/*! DATAWxSyUM - Cache Line Data[127:96] */ +#define FMC_FCLN3_DATAWxSyUM(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCLN3_DATAWxSyUM_SHIFT)) & FMC_FCLN3_DATAWxSyUM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMC_Register_Masks */ + + +/*! + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FMC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FMU.h new file mode 100644 index 000000000..82431dcf6 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FMU.h @@ -0,0 +1,378 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for FMU +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_FMU.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for FMU + * + * CMSIS Peripheral Access Layer for FMU + */ + +#if !defined(PERI_FMU_H_) +#define PERI_FMU_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer + * @{ + */ + +/** FMU - Size of Registers Arrays */ +#define FMU_FCCOB_COUNT 8u + +/** FMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FCCOB[FMU_FCCOB_COUNT]; /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */ +} FMU_Type; + +/* ---------------------------------------------------------------------------- + -- FMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Register_Masks FMU Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMU_FSTAT_FAIL_MASK (0x1U) +#define FMU_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMU_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK) + +#define FMU_FSTAT_CMDABT_MASK (0x4U) +#define FMU_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMU_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK) + +#define FMU_FSTAT_PVIOL_MASK (0x10U) +#define FMU_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMU_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK) + +#define FMU_FSTAT_ACCERR_MASK (0x20U) +#define FMU_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMU_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK) + +#define FMU_FSTAT_CWSABT_MASK (0x40U) +#define FMU_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMU_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK) + +#define FMU_FSTAT_CCIF_MASK (0x80U) +#define FMU_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command, initialization, or power mode recovery in progress + * 0b1..Flash command, initialization, or power mode recovery has completed + */ +#define FMU_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK) + +#define FMU_FSTAT_CMDPRT_MASK (0x300U) +#define FMU_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command protection level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMU_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK) + +#define FMU_FSTAT_CMDP_MASK (0x800U) +#define FMU_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command protection status flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMU_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK) + +#define FMU_FSTAT_CMDDID_MASK (0xF000U) +#define FMU_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command domain ID */ +#define FMU_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK) + +#define FMU_FSTAT_DFDIF_MASK (0x10000U) +#define FMU_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access + */ +#define FMU_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK) + +#define FMU_FSTAT_SALV_USED_MASK (0x20000U) +#define FMU_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMU_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK) + +#define FMU_FSTAT_PEWEN_MASK (0x3000000U) +#define FMU_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMU_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK) + +#define FMU_FSTAT_PERDY_MASK (0x80000000U) +#define FMU_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program-Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation not stalled + * 0b1..Program or sector erase command operation ready to execute + */ +#define FMU_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMU_FCNFG_CCIE_MASK (0x80U) +#define FMU_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled + */ +#define FMU_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK) + +#define FMU_FCNFG_ERSREQ_MASK (0x100U) +#define FMU_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMU_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK) + +#define FMU_FCNFG_DFDIE_MASK (0x10000U) +#define FMU_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled + */ +#define FMU_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK) + +#define FMU_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMU_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK) + +#define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMU_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMU_FCTRL_RWSC_MASK (0xFU) +#define FMU_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control */ +#define FMU_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK) + +#define FMU_FCTRL_LSACTIVE_MASK (0x100U) +#define FMU_FCTRL_LSACTIVE_SHIFT (8U) +/*! LSACTIVE - Low speed active mode + * 0b0..Full speed active mode requested + * 0b1..Low speed active mode requested + */ +#define FMU_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_LSACTIVE_SHIFT)) & FMU_FCTRL_LSACTIVE_MASK) + +#define FMU_FCTRL_FDFD_MASK (0x10000U) +#define FMU_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt + * request is generated if the DFDIE bit is set. + */ +#define FMU_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK) + +#define FMU_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMU_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMU_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FCCOB - Flash Common Command Object Registers */ +/*! @{ */ + +#define FMU_FCCOB_CCOBn_MASK (0xFFFFFFFFU) +#define FMU_FCCOB_CCOBn_SHIFT (0U) +/*! CCOBn - CCOBn */ +#define FMU_FCCOB_CCOBn(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMU_Register_Masks */ + + +/*! + * @} + */ /* end of group FMU_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FMU_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FREQME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FREQME.h new file mode 100644 index 000000000..3a30c0d0c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_FREQME.h @@ -0,0 +1,369 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for FREQME +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_FREQME.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for FREQME + * + * CMSIS Peripheral Access Layer for FREQME + */ + +#if !defined(PERI_FREQME_H_) +#define PERI_FREQME_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- FREQME Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer + * @{ + */ + +/** FREQME - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + __I uint32_t CTRL_R; /**< Control (in Read mode), offset: 0x0 */ + __O uint32_t CTRL_W; /**< Control (in Write mode), offset: 0x0 */ + }; + __IO uint32_t CTRLSTAT; /**< Control Status, offset: 0x4 */ + __IO uint32_t MIN; /**< Minimum, offset: 0x8 */ + __IO uint32_t MAX; /**< Maximum, offset: 0xC */ +} FREQME_Type; + +/* ---------------------------------------------------------------------------- + -- FREQME Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Register_Masks FREQME Register Masks + * @{ + */ + +/*! @name CTRL_R - Control (in Read mode) */ +/*! @{ */ + +#define FREQME_CTRL_R_RESULT_MASK (0x7FFFFFFFU) +#define FREQME_CTRL_R_RESULT_SHIFT (0U) +#define FREQME_CTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK) + +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Complete + * 0b1..In progress + */ +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRL_W - Control (in Write mode) */ +/*! @{ */ + +#define FREQME_CTRL_W_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRL_W_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Clock Scaling Factor */ +#define FREQME_CTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK) + +#define FREQME_CTRL_W_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRL_W_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Width Measurement Mode Select + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK) + +#define FREQME_CTRL_W_PULSE_POL_MASK (0x200U) +#define FREQME_CTRL_W_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK) + +#define FREQME_CTRL_W_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRL_W_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Terminates measurement + * 0b1..Initiates measurement + */ +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRLSTAT - Control Status */ +/*! @{ */ + +#define FREQME_CTRLSTAT_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRLSTAT_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Scale */ +#define FREQME_CTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK) + +#define FREQME_CTRLSTAT_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRLSTAT_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Mode + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK) + +#define FREQME_CTRLSTAT_PULSE_POL_MASK (0x200U) +#define FREQME_CTRLSTAT_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_STAT_MASK (0x1000000U) +#define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT (24U) +/*! LT_MIN_STAT - Less Than Minimum Results Status + * 0b0..Greater than MIN[MIN_VALUE] + * 0b1..Less than MIN[MIN_VALUE] + */ +#define FREQME_CTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_STAT_MASK (0x2000000U) +#define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT (25U) +/*! GT_MAX_STAT - Greater Than Maximum Result Status + * 0b0..Less than MAX[MAX_VALUE] + * 0b1..Greater than MAX[MAX_VALUE] + */ +#define FREQME_CTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U) +#define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT (26U) +/*! RESULT_READY_STAT - Result Ready Status + * 0b0..Not complete + * 0b1..Complete + */ +#define FREQME_CTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK) + +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement in Progress Status + * 0b0..Not in progress + * 0b1..In progress + */ +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name MIN - Minimum */ +/*! @{ */ + +#define FREQME_MIN_MIN_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MIN_MIN_VALUE_SHIFT (0U) +/*! MIN_VALUE - Minimum Value */ +#define FREQME_MIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK) +/*! @} */ + +/*! @name MAX - Maximum */ +/*! @{ */ + +#define FREQME_MAX_MAX_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MAX_MAX_VALUE_SHIFT (0U) +/*! MAX_VALUE - Maximum Value */ +#define FREQME_MAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FREQME_Register_Masks */ + + +/*! + * @} + */ /* end of group FREQME_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_FREQME_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_GLIKEY.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_GLIKEY.h new file mode 100644 index 000000000..532391b00 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_GLIKEY.h @@ -0,0 +1,355 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for GLIKEY +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_GLIKEY.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for GLIKEY + * + * CMSIS Peripheral Access Layer for GLIKEY + */ + +#if !defined(PERI_GLIKEY_H_) +#define PERI_GLIKEY_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- GLIKEY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GLIKEY_Peripheral_Access_Layer GLIKEY Peripheral Access Layer + * @{ + */ + +/** GLIKEY - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL_0; /**< Control Register 0 SFR, offset: 0x0 */ + __IO uint32_t CTRL_1; /**< Control Register 1 SFR, offset: 0x4 */ + __IO uint32_t INTR_CTRL; /**< Interrupt Control, offset: 0x8 */ + __I uint32_t STATUS; /**< Status, offset: 0xC */ + uint8_t RESERVED_0[236]; + __I uint32_t VERSION; /**< IP Version, offset: 0xFC */ +} GLIKEY_Type; + +/* ---------------------------------------------------------------------------- + -- GLIKEY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GLIKEY_Register_Masks GLIKEY Register Masks + * @{ + */ + +/*! @name CTRL_0 - Control Register 0 SFR */ +/*! @{ */ + +#define GLIKEY_CTRL_0_WRITE_INDEX_MASK (0xFFU) +#define GLIKEY_CTRL_0_WRITE_INDEX_SHIFT (0U) +/*! WRITE_INDEX - Write Index */ +#define GLIKEY_CTRL_0_WRITE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WRITE_INDEX_SHIFT)) & GLIKEY_CTRL_0_WRITE_INDEX_MASK) + +#define GLIKEY_CTRL_0_RESERVED15_MASK (0xFF00U) +#define GLIKEY_CTRL_0_RESERVED15_SHIFT (8U) +/*! RESERVED15 - Reserved for Future Use */ +#define GLIKEY_CTRL_0_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED15_SHIFT)) & GLIKEY_CTRL_0_RESERVED15_MASK) + +#define GLIKEY_CTRL_0_WR_EN_0_MASK (0x30000U) +#define GLIKEY_CTRL_0_WR_EN_0_SHIFT (16U) +/*! WR_EN_0 - Write Enable 0 */ +#define GLIKEY_CTRL_0_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WR_EN_0_SHIFT)) & GLIKEY_CTRL_0_WR_EN_0_MASK) + +#define GLIKEY_CTRL_0_SFT_RST_MASK (0x40000U) +#define GLIKEY_CTRL_0_SFT_RST_SHIFT (18U) +/*! SFT_RST - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0 + * 0b0..No effect + * 0b1..Triggers the soft reset + */ +#define GLIKEY_CTRL_0_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_SFT_RST_SHIFT)) & GLIKEY_CTRL_0_SFT_RST_MASK) + +#define GLIKEY_CTRL_0_RESERVED31_MASK (0xFFF80000U) +#define GLIKEY_CTRL_0_RESERVED31_SHIFT (19U) +/*! RESERVED31 - Reserved for Future Use */ +#define GLIKEY_CTRL_0_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED31_SHIFT)) & GLIKEY_CTRL_0_RESERVED31_MASK) +/*! @} */ + +/*! @name CTRL_1 - Control Register 1 SFR */ +/*! @{ */ + +#define GLIKEY_CTRL_1_READ_INDEX_MASK (0xFFU) +#define GLIKEY_CTRL_1_READ_INDEX_SHIFT (0U) +/*! READ_INDEX - Index status, Writing an index value to this register will request the block to return the lock status of this index. */ +#define GLIKEY_CTRL_1_READ_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_READ_INDEX_SHIFT)) & GLIKEY_CTRL_1_READ_INDEX_MASK) + +#define GLIKEY_CTRL_1_RESERVED15_MASK (0xFF00U) +#define GLIKEY_CTRL_1_RESERVED15_SHIFT (8U) +/*! RESERVED15 - Reserved for Future Use */ +#define GLIKEY_CTRL_1_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED15_SHIFT)) & GLIKEY_CTRL_1_RESERVED15_MASK) + +#define GLIKEY_CTRL_1_WR_EN_1_MASK (0x30000U) +#define GLIKEY_CTRL_1_WR_EN_1_SHIFT (16U) +/*! WR_EN_1 - Write Enable One */ +#define GLIKEY_CTRL_1_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_WR_EN_1_SHIFT)) & GLIKEY_CTRL_1_WR_EN_1_MASK) + +#define GLIKEY_CTRL_1_SFR_LOCK_MASK (0x3C0000U) +#define GLIKEY_CTRL_1_SFR_LOCK_SHIFT (18U) +/*! SFR_LOCK - LOCK register for GLIKEY */ +#define GLIKEY_CTRL_1_SFR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_SFR_LOCK_SHIFT)) & GLIKEY_CTRL_1_SFR_LOCK_MASK) + +#define GLIKEY_CTRL_1_RESERVED31_MASK (0xFFC00000U) +#define GLIKEY_CTRL_1_RESERVED31_SHIFT (22U) +/*! RESERVED31 - Reserved for Future Use */ +#define GLIKEY_CTRL_1_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED31_SHIFT)) & GLIKEY_CTRL_1_RESERVED31_MASK) +/*! @} */ + +/*! @name INTR_CTRL - Interrupt Control */ +/*! @{ */ + +#define GLIKEY_INTR_CTRL_INT_EN_MASK (0x1U) +#define GLIKEY_INTR_CTRL_INT_EN_SHIFT (0U) +/*! INT_EN - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port */ +#define GLIKEY_INTR_CTRL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_EN_SHIFT)) & GLIKEY_INTR_CTRL_INT_EN_MASK) + +#define GLIKEY_INTR_CTRL_INT_CLR_MASK (0x2U) +#define GLIKEY_INTR_CTRL_INT_CLR_SHIFT (1U) +/*! INT_CLR - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0 */ +#define GLIKEY_INTR_CTRL_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_CLR_SHIFT)) & GLIKEY_INTR_CTRL_INT_CLR_MASK) + +#define GLIKEY_INTR_CTRL_INT_SET_MASK (0x4U) +#define GLIKEY_INTR_CTRL_INT_SET_SHIFT (2U) +/*! INT_SET - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0 + * 0b0..No effect + * 0b1..Triggers interrupt + */ +#define GLIKEY_INTR_CTRL_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_SET_SHIFT)) & GLIKEY_INTR_CTRL_INT_SET_MASK) + +#define GLIKEY_INTR_CTRL_RESERVED31_MASK (0xFFFFFFF8U) +#define GLIKEY_INTR_CTRL_RESERVED31_SHIFT (3U) +/*! RESERVED31 - Reserved for Future Use */ +#define GLIKEY_INTR_CTRL_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_RESERVED31_SHIFT)) & GLIKEY_INTR_CTRL_RESERVED31_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define GLIKEY_STATUS_INT_STATUS_MASK (0x1U) +#define GLIKEY_STATUS_INT_STATUS_SHIFT (0U) +/*! INT_STATUS - Interrupt Status. + * 0b0..No effect + * 0b1..Triggers interrupt + */ +#define GLIKEY_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_INT_STATUS_SHIFT)) & GLIKEY_STATUS_INT_STATUS_MASK) + +#define GLIKEY_STATUS_LOCK_STATUS_MASK (0x2U) +#define GLIKEY_STATUS_LOCK_STATUS_SHIFT (1U) +/*! LOCK_STATUS - Provides the current lock status of indexes. + * 0b0..Current read index is not locked + * 0b1..Current read index is locked + */ +#define GLIKEY_STATUS_LOCK_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_LOCK_STATUS_SHIFT)) & GLIKEY_STATUS_LOCK_STATUS_MASK) + +#define GLIKEY_STATUS_ERROR_STATUS_MASK (0x1CU) +#define GLIKEY_STATUS_ERROR_STATUS_SHIFT (2U) +/*! ERROR_STATUS - Status of the Error + * 0b000..No error + * 0b001..FSM error has occurred + * 0b010..Write index out of the bound (OOB) error + * 0b011..Write index OOB and FSM error + * 0b100..Read index OOB error + * 0b110..Write index and read index OOB error + * 0b111..Read index OOB, write index OOB, and FSM error + */ +#define GLIKEY_STATUS_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_ERROR_STATUS_SHIFT)) & GLIKEY_STATUS_ERROR_STATUS_MASK) + +#define GLIKEY_STATUS_RESERVED18_MASK (0x7FFE0U) +#define GLIKEY_STATUS_RESERVED18_SHIFT (5U) +/*! RESERVED18 - Reserved for Future Use */ +#define GLIKEY_STATUS_RESERVED18(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_RESERVED18_SHIFT)) & GLIKEY_STATUS_RESERVED18_MASK) + +#define GLIKEY_STATUS_FSM_STATE_MASK (0xFFF80000U) +#define GLIKEY_STATUS_FSM_STATE_SHIFT (19U) +/*! FSM_STATE - Status of FSM */ +#define GLIKEY_STATUS_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_FSM_STATE_SHIFT)) & GLIKEY_STATUS_FSM_STATE_MASK) +/*! @} */ + +/*! @name VERSION - IP Version */ +/*! @{ */ + +#define GLIKEY_VERSION_RESERVED3_MASK (0xFU) +#define GLIKEY_VERSION_RESERVED3_SHIFT (0U) +/*! Reserved3 - Reserved */ +#define GLIKEY_VERSION_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED3_SHIFT)) & GLIKEY_VERSION_RESERVED3_MASK) + +#define GLIKEY_VERSION_RESERVED7_MASK (0xF0U) +#define GLIKEY_VERSION_RESERVED7_SHIFT (4U) +/*! Reserved7 - Reserved */ +#define GLIKEY_VERSION_RESERVED7(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED7_SHIFT)) & GLIKEY_VERSION_RESERVED7_MASK) + +#define GLIKEY_VERSION_RESERVED11_MASK (0xF00U) +#define GLIKEY_VERSION_RESERVED11_SHIFT (8U) +/*! Reserved11 - Reserved */ +#define GLIKEY_VERSION_RESERVED11(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED11_SHIFT)) & GLIKEY_VERSION_RESERVED11_MASK) + +#define GLIKEY_VERSION_RESERVED15_MASK (0xF000U) +#define GLIKEY_VERSION_RESERVED15_SHIFT (12U) +/*! Reserved15 - Reserved */ +#define GLIKEY_VERSION_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED15_SHIFT)) & GLIKEY_VERSION_RESERVED15_MASK) + +#define GLIKEY_VERSION_MILESTONE_MASK (0x30000U) +#define GLIKEY_VERSION_MILESTONE_SHIFT (16U) +/*! MILESTONE - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO. */ +#define GLIKEY_VERSION_MILESTONE(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_MILESTONE_SHIFT)) & GLIKEY_VERSION_MILESTONE_MASK) + +#define GLIKEY_VERSION_FSM_CONFIG_MASK (0x40000U) +#define GLIKEY_VERSION_FSM_CONFIG_SHIFT (18U) +/*! FSM_CONFIG - 0:4 step, 1:8 step */ +#define GLIKEY_VERSION_FSM_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_FSM_CONFIG_SHIFT)) & GLIKEY_VERSION_FSM_CONFIG_MASK) + +#define GLIKEY_VERSION_INDEX_CONFIG_MASK (0x7F80000U) +#define GLIKEY_VERSION_INDEX_CONFIG_SHIFT (19U) +/*! INDEX_CONFIG - Configured number of addressable indexes */ +#define GLIKEY_VERSION_INDEX_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_INDEX_CONFIG_SHIFT)) & GLIKEY_VERSION_INDEX_CONFIG_MASK) + +#define GLIKEY_VERSION_RESERVED31_MASK (0xF8000000U) +#define GLIKEY_VERSION_RESERVED31_SHIFT (27U) +/*! Reserved31 - Reserved for Future Use */ +#define GLIKEY_VERSION_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED31_SHIFT)) & GLIKEY_VERSION_RESERVED31_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GLIKEY_Register_Masks */ + + +/*! + * @} + */ /* end of group GLIKEY_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_GLIKEY_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_GPIO.h new file mode 100644 index 000000000..b13735339 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_GPIO.h @@ -0,0 +1,2695 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for GPIO +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_GPIO.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for GPIO + * + * CMSIS Peripheral Access Layer for GPIO + */ + +#if !defined(PERI_GPIO_H_) +#define PERI_GPIO_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Size of Registers Arrays */ +#define GPIO_PDR_COUNT 32u +#define GPIO_ICR_COUNT 32u +#define GPIO_ISFR_COUNT 1u + +/** GPIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[56]; + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __IO uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __IO uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __IO uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint8_t PDR[GPIO_PDR_COUNT]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[GPIO_ICR_COUNT]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __IO uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __IO uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ + uint8_t RESERVED_2[24]; + __IO uint32_t ISFR[GPIO_ISFR_COUNT]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define GPIO_VERID_FEATURE_MASK (0xFFFFU) +#define GPIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented + */ +#define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK) + +#define GPIO_VERID_MINOR_MASK (0xFF0000U) +#define GPIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define GPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK) + +#define GPIO_VERID_MAJOR_MASK (0xFF000000U) +#define GPIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define GPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define GPIO_PARAM_IRQNUM_MASK (0xFU) +#define GPIO_PARAM_IRQNUM_SHIFT (0U) +/*! IRQNUM - Interrupt Number */ +#define GPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK) +/*! @} */ + +/*! @name PDOR - Port Data Output */ +/*! @{ */ + +#define GPIO_PDOR_PDO0_MASK (0x1U) +#define GPIO_PDOR_PDO0_SHIFT (0U) +/*! PDO0 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK) + +#define GPIO_PDOR_PDO1_MASK (0x2U) +#define GPIO_PDOR_PDO1_SHIFT (1U) +/*! PDO1 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK) + +#define GPIO_PDOR_PDO2_MASK (0x4U) +#define GPIO_PDOR_PDO2_SHIFT (2U) +/*! PDO2 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK) + +#define GPIO_PDOR_PDO3_MASK (0x8U) +#define GPIO_PDOR_PDO3_SHIFT (3U) +/*! PDO3 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK) + +#define GPIO_PDOR_PDO4_MASK (0x10U) +#define GPIO_PDOR_PDO4_SHIFT (4U) +/*! PDO4 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK) + +#define GPIO_PDOR_PDO5_MASK (0x20U) +#define GPIO_PDOR_PDO5_SHIFT (5U) +/*! PDO5 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK) + +#define GPIO_PDOR_PDO6_MASK (0x40U) +#define GPIO_PDOR_PDO6_SHIFT (6U) +/*! PDO6 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK) + +#define GPIO_PDOR_PDO7_MASK (0x80U) +#define GPIO_PDOR_PDO7_SHIFT (7U) +/*! PDO7 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK) + +#define GPIO_PDOR_PDO8_MASK (0x100U) +#define GPIO_PDOR_PDO8_SHIFT (8U) +/*! PDO8 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK) + +#define GPIO_PDOR_PDO9_MASK (0x200U) +#define GPIO_PDOR_PDO9_SHIFT (9U) +/*! PDO9 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK) + +#define GPIO_PDOR_PDO10_MASK (0x400U) +#define GPIO_PDOR_PDO10_SHIFT (10U) +/*! PDO10 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK) + +#define GPIO_PDOR_PDO11_MASK (0x800U) +#define GPIO_PDOR_PDO11_SHIFT (11U) +/*! PDO11 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK) + +#define GPIO_PDOR_PDO12_MASK (0x1000U) +#define GPIO_PDOR_PDO12_SHIFT (12U) +/*! PDO12 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK) + +#define GPIO_PDOR_PDO13_MASK (0x2000U) +#define GPIO_PDOR_PDO13_SHIFT (13U) +/*! PDO13 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK) + +#define GPIO_PDOR_PDO14_MASK (0x4000U) +#define GPIO_PDOR_PDO14_SHIFT (14U) +/*! PDO14 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK) + +#define GPIO_PDOR_PDO15_MASK (0x8000U) +#define GPIO_PDOR_PDO15_SHIFT (15U) +/*! PDO15 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK) + +#define GPIO_PDOR_PDO16_MASK (0x10000U) +#define GPIO_PDOR_PDO16_SHIFT (16U) +/*! PDO16 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK) + +#define GPIO_PDOR_PDO17_MASK (0x20000U) +#define GPIO_PDOR_PDO17_SHIFT (17U) +/*! PDO17 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK) + +#define GPIO_PDOR_PDO18_MASK (0x40000U) +#define GPIO_PDOR_PDO18_SHIFT (18U) +/*! PDO18 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK) + +#define GPIO_PDOR_PDO19_MASK (0x80000U) +#define GPIO_PDOR_PDO19_SHIFT (19U) +/*! PDO19 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK) + +#define GPIO_PDOR_PDO20_MASK (0x100000U) +#define GPIO_PDOR_PDO20_SHIFT (20U) +/*! PDO20 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK) + +#define GPIO_PDOR_PDO21_MASK (0x200000U) +#define GPIO_PDOR_PDO21_SHIFT (21U) +/*! PDO21 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK) + +#define GPIO_PDOR_PDO22_MASK (0x400000U) +#define GPIO_PDOR_PDO22_SHIFT (22U) +/*! PDO22 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK) + +#define GPIO_PDOR_PDO23_MASK (0x800000U) +#define GPIO_PDOR_PDO23_SHIFT (23U) +/*! PDO23 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK) + +#define GPIO_PDOR_PDO24_MASK (0x1000000U) +#define GPIO_PDOR_PDO24_SHIFT (24U) +/*! PDO24 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK) + +#define GPIO_PDOR_PDO25_MASK (0x2000000U) +#define GPIO_PDOR_PDO25_SHIFT (25U) +/*! PDO25 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK) + +#define GPIO_PDOR_PDO26_MASK (0x4000000U) +#define GPIO_PDOR_PDO26_SHIFT (26U) +/*! PDO26 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK) + +#define GPIO_PDOR_PDO27_MASK (0x8000000U) +#define GPIO_PDOR_PDO27_SHIFT (27U) +/*! PDO27 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK) + +#define GPIO_PDOR_PDO28_MASK (0x10000000U) +#define GPIO_PDOR_PDO28_SHIFT (28U) +/*! PDO28 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK) + +#define GPIO_PDOR_PDO29_MASK (0x20000000U) +#define GPIO_PDOR_PDO29_SHIFT (29U) +/*! PDO29 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK) + +#define GPIO_PDOR_PDO30_MASK (0x40000000U) +#define GPIO_PDOR_PDO30_SHIFT (30U) +/*! PDO30 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK) + +#define GPIO_PDOR_PDO31_MASK (0x80000000U) +#define GPIO_PDOR_PDO31_SHIFT (31U) +/*! PDO31 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK) +/*! @} */ + +/*! @name PSOR - Port Set Output */ +/*! @{ */ + +#define GPIO_PSOR_PTSO0_MASK (0x1U) +#define GPIO_PSOR_PTSO0_SHIFT (0U) +/*! PTSO0 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK) + +#define GPIO_PSOR_PTSO1_MASK (0x2U) +#define GPIO_PSOR_PTSO1_SHIFT (1U) +/*! PTSO1 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK) + +#define GPIO_PSOR_PTSO2_MASK (0x4U) +#define GPIO_PSOR_PTSO2_SHIFT (2U) +/*! PTSO2 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK) + +#define GPIO_PSOR_PTSO3_MASK (0x8U) +#define GPIO_PSOR_PTSO3_SHIFT (3U) +/*! PTSO3 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK) + +#define GPIO_PSOR_PTSO4_MASK (0x10U) +#define GPIO_PSOR_PTSO4_SHIFT (4U) +/*! PTSO4 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK) + +#define GPIO_PSOR_PTSO5_MASK (0x20U) +#define GPIO_PSOR_PTSO5_SHIFT (5U) +/*! PTSO5 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK) + +#define GPIO_PSOR_PTSO6_MASK (0x40U) +#define GPIO_PSOR_PTSO6_SHIFT (6U) +/*! PTSO6 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK) + +#define GPIO_PSOR_PTSO7_MASK (0x80U) +#define GPIO_PSOR_PTSO7_SHIFT (7U) +/*! PTSO7 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK) + +#define GPIO_PSOR_PTSO8_MASK (0x100U) +#define GPIO_PSOR_PTSO8_SHIFT (8U) +/*! PTSO8 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK) + +#define GPIO_PSOR_PTSO9_MASK (0x200U) +#define GPIO_PSOR_PTSO9_SHIFT (9U) +/*! PTSO9 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK) + +#define GPIO_PSOR_PTSO10_MASK (0x400U) +#define GPIO_PSOR_PTSO10_SHIFT (10U) +/*! PTSO10 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK) + +#define GPIO_PSOR_PTSO11_MASK (0x800U) +#define GPIO_PSOR_PTSO11_SHIFT (11U) +/*! PTSO11 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK) + +#define GPIO_PSOR_PTSO12_MASK (0x1000U) +#define GPIO_PSOR_PTSO12_SHIFT (12U) +/*! PTSO12 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK) + +#define GPIO_PSOR_PTSO13_MASK (0x2000U) +#define GPIO_PSOR_PTSO13_SHIFT (13U) +/*! PTSO13 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK) + +#define GPIO_PSOR_PTSO14_MASK (0x4000U) +#define GPIO_PSOR_PTSO14_SHIFT (14U) +/*! PTSO14 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK) + +#define GPIO_PSOR_PTSO15_MASK (0x8000U) +#define GPIO_PSOR_PTSO15_SHIFT (15U) +/*! PTSO15 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK) + +#define GPIO_PSOR_PTSO16_MASK (0x10000U) +#define GPIO_PSOR_PTSO16_SHIFT (16U) +/*! PTSO16 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK) + +#define GPIO_PSOR_PTSO17_MASK (0x20000U) +#define GPIO_PSOR_PTSO17_SHIFT (17U) +/*! PTSO17 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK) + +#define GPIO_PSOR_PTSO18_MASK (0x40000U) +#define GPIO_PSOR_PTSO18_SHIFT (18U) +/*! PTSO18 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK) + +#define GPIO_PSOR_PTSO19_MASK (0x80000U) +#define GPIO_PSOR_PTSO19_SHIFT (19U) +/*! PTSO19 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK) + +#define GPIO_PSOR_PTSO20_MASK (0x100000U) +#define GPIO_PSOR_PTSO20_SHIFT (20U) +/*! PTSO20 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK) + +#define GPIO_PSOR_PTSO21_MASK (0x200000U) +#define GPIO_PSOR_PTSO21_SHIFT (21U) +/*! PTSO21 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK) + +#define GPIO_PSOR_PTSO22_MASK (0x400000U) +#define GPIO_PSOR_PTSO22_SHIFT (22U) +/*! PTSO22 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK) + +#define GPIO_PSOR_PTSO23_MASK (0x800000U) +#define GPIO_PSOR_PTSO23_SHIFT (23U) +/*! PTSO23 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK) + +#define GPIO_PSOR_PTSO24_MASK (0x1000000U) +#define GPIO_PSOR_PTSO24_SHIFT (24U) +/*! PTSO24 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK) + +#define GPIO_PSOR_PTSO25_MASK (0x2000000U) +#define GPIO_PSOR_PTSO25_SHIFT (25U) +/*! PTSO25 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK) + +#define GPIO_PSOR_PTSO26_MASK (0x4000000U) +#define GPIO_PSOR_PTSO26_SHIFT (26U) +/*! PTSO26 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK) + +#define GPIO_PSOR_PTSO27_MASK (0x8000000U) +#define GPIO_PSOR_PTSO27_SHIFT (27U) +/*! PTSO27 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK) + +#define GPIO_PSOR_PTSO28_MASK (0x10000000U) +#define GPIO_PSOR_PTSO28_SHIFT (28U) +/*! PTSO28 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK) + +#define GPIO_PSOR_PTSO29_MASK (0x20000000U) +#define GPIO_PSOR_PTSO29_SHIFT (29U) +/*! PTSO29 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK) + +#define GPIO_PSOR_PTSO30_MASK (0x40000000U) +#define GPIO_PSOR_PTSO30_SHIFT (30U) +/*! PTSO30 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK) + +#define GPIO_PSOR_PTSO31_MASK (0x80000000U) +#define GPIO_PSOR_PTSO31_SHIFT (31U) +/*! PTSO31 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK) +/*! @} */ + +/*! @name PCOR - Port Clear Output */ +/*! @{ */ + +#define GPIO_PCOR_PTCO0_MASK (0x1U) +#define GPIO_PCOR_PTCO0_SHIFT (0U) +/*! PTCO0 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK) + +#define GPIO_PCOR_PTCO1_MASK (0x2U) +#define GPIO_PCOR_PTCO1_SHIFT (1U) +/*! PTCO1 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK) + +#define GPIO_PCOR_PTCO2_MASK (0x4U) +#define GPIO_PCOR_PTCO2_SHIFT (2U) +/*! PTCO2 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK) + +#define GPIO_PCOR_PTCO3_MASK (0x8U) +#define GPIO_PCOR_PTCO3_SHIFT (3U) +/*! PTCO3 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK) + +#define GPIO_PCOR_PTCO4_MASK (0x10U) +#define GPIO_PCOR_PTCO4_SHIFT (4U) +/*! PTCO4 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK) + +#define GPIO_PCOR_PTCO5_MASK (0x20U) +#define GPIO_PCOR_PTCO5_SHIFT (5U) +/*! PTCO5 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK) + +#define GPIO_PCOR_PTCO6_MASK (0x40U) +#define GPIO_PCOR_PTCO6_SHIFT (6U) +/*! PTCO6 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK) + +#define GPIO_PCOR_PTCO7_MASK (0x80U) +#define GPIO_PCOR_PTCO7_SHIFT (7U) +/*! PTCO7 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK) + +#define GPIO_PCOR_PTCO8_MASK (0x100U) +#define GPIO_PCOR_PTCO8_SHIFT (8U) +/*! PTCO8 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK) + +#define GPIO_PCOR_PTCO9_MASK (0x200U) +#define GPIO_PCOR_PTCO9_SHIFT (9U) +/*! PTCO9 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK) + +#define GPIO_PCOR_PTCO10_MASK (0x400U) +#define GPIO_PCOR_PTCO10_SHIFT (10U) +/*! PTCO10 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK) + +#define GPIO_PCOR_PTCO11_MASK (0x800U) +#define GPIO_PCOR_PTCO11_SHIFT (11U) +/*! PTCO11 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK) + +#define GPIO_PCOR_PTCO12_MASK (0x1000U) +#define GPIO_PCOR_PTCO12_SHIFT (12U) +/*! PTCO12 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK) + +#define GPIO_PCOR_PTCO13_MASK (0x2000U) +#define GPIO_PCOR_PTCO13_SHIFT (13U) +/*! PTCO13 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK) + +#define GPIO_PCOR_PTCO14_MASK (0x4000U) +#define GPIO_PCOR_PTCO14_SHIFT (14U) +/*! PTCO14 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK) + +#define GPIO_PCOR_PTCO15_MASK (0x8000U) +#define GPIO_PCOR_PTCO15_SHIFT (15U) +/*! PTCO15 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK) + +#define GPIO_PCOR_PTCO16_MASK (0x10000U) +#define GPIO_PCOR_PTCO16_SHIFT (16U) +/*! PTCO16 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK) + +#define GPIO_PCOR_PTCO17_MASK (0x20000U) +#define GPIO_PCOR_PTCO17_SHIFT (17U) +/*! PTCO17 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK) + +#define GPIO_PCOR_PTCO18_MASK (0x40000U) +#define GPIO_PCOR_PTCO18_SHIFT (18U) +/*! PTCO18 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK) + +#define GPIO_PCOR_PTCO19_MASK (0x80000U) +#define GPIO_PCOR_PTCO19_SHIFT (19U) +/*! PTCO19 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK) + +#define GPIO_PCOR_PTCO20_MASK (0x100000U) +#define GPIO_PCOR_PTCO20_SHIFT (20U) +/*! PTCO20 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK) + +#define GPIO_PCOR_PTCO21_MASK (0x200000U) +#define GPIO_PCOR_PTCO21_SHIFT (21U) +/*! PTCO21 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK) + +#define GPIO_PCOR_PTCO22_MASK (0x400000U) +#define GPIO_PCOR_PTCO22_SHIFT (22U) +/*! PTCO22 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK) + +#define GPIO_PCOR_PTCO23_MASK (0x800000U) +#define GPIO_PCOR_PTCO23_SHIFT (23U) +/*! PTCO23 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK) + +#define GPIO_PCOR_PTCO24_MASK (0x1000000U) +#define GPIO_PCOR_PTCO24_SHIFT (24U) +/*! PTCO24 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK) + +#define GPIO_PCOR_PTCO25_MASK (0x2000000U) +#define GPIO_PCOR_PTCO25_SHIFT (25U) +/*! PTCO25 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK) + +#define GPIO_PCOR_PTCO26_MASK (0x4000000U) +#define GPIO_PCOR_PTCO26_SHIFT (26U) +/*! PTCO26 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK) + +#define GPIO_PCOR_PTCO27_MASK (0x8000000U) +#define GPIO_PCOR_PTCO27_SHIFT (27U) +/*! PTCO27 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK) + +#define GPIO_PCOR_PTCO28_MASK (0x10000000U) +#define GPIO_PCOR_PTCO28_SHIFT (28U) +/*! PTCO28 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK) + +#define GPIO_PCOR_PTCO29_MASK (0x20000000U) +#define GPIO_PCOR_PTCO29_SHIFT (29U) +/*! PTCO29 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK) + +#define GPIO_PCOR_PTCO30_MASK (0x40000000U) +#define GPIO_PCOR_PTCO30_SHIFT (30U) +/*! PTCO30 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK) + +#define GPIO_PCOR_PTCO31_MASK (0x80000000U) +#define GPIO_PCOR_PTCO31_SHIFT (31U) +/*! PTCO31 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK) +/*! @} */ + +/*! @name PTOR - Port Toggle Output */ +/*! @{ */ + +#define GPIO_PTOR_PTTO0_MASK (0x1U) +#define GPIO_PTOR_PTTO0_SHIFT (0U) +/*! PTTO0 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK) + +#define GPIO_PTOR_PTTO1_MASK (0x2U) +#define GPIO_PTOR_PTTO1_SHIFT (1U) +/*! PTTO1 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK) + +#define GPIO_PTOR_PTTO2_MASK (0x4U) +#define GPIO_PTOR_PTTO2_SHIFT (2U) +/*! PTTO2 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK) + +#define GPIO_PTOR_PTTO3_MASK (0x8U) +#define GPIO_PTOR_PTTO3_SHIFT (3U) +/*! PTTO3 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK) + +#define GPIO_PTOR_PTTO4_MASK (0x10U) +#define GPIO_PTOR_PTTO4_SHIFT (4U) +/*! PTTO4 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK) + +#define GPIO_PTOR_PTTO5_MASK (0x20U) +#define GPIO_PTOR_PTTO5_SHIFT (5U) +/*! PTTO5 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK) + +#define GPIO_PTOR_PTTO6_MASK (0x40U) +#define GPIO_PTOR_PTTO6_SHIFT (6U) +/*! PTTO6 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK) + +#define GPIO_PTOR_PTTO7_MASK (0x80U) +#define GPIO_PTOR_PTTO7_SHIFT (7U) +/*! PTTO7 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK) + +#define GPIO_PTOR_PTTO8_MASK (0x100U) +#define GPIO_PTOR_PTTO8_SHIFT (8U) +/*! PTTO8 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK) + +#define GPIO_PTOR_PTTO9_MASK (0x200U) +#define GPIO_PTOR_PTTO9_SHIFT (9U) +/*! PTTO9 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK) + +#define GPIO_PTOR_PTTO10_MASK (0x400U) +#define GPIO_PTOR_PTTO10_SHIFT (10U) +/*! PTTO10 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK) + +#define GPIO_PTOR_PTTO11_MASK (0x800U) +#define GPIO_PTOR_PTTO11_SHIFT (11U) +/*! PTTO11 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK) + +#define GPIO_PTOR_PTTO12_MASK (0x1000U) +#define GPIO_PTOR_PTTO12_SHIFT (12U) +/*! PTTO12 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK) + +#define GPIO_PTOR_PTTO13_MASK (0x2000U) +#define GPIO_PTOR_PTTO13_SHIFT (13U) +/*! PTTO13 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK) + +#define GPIO_PTOR_PTTO14_MASK (0x4000U) +#define GPIO_PTOR_PTTO14_SHIFT (14U) +/*! PTTO14 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK) + +#define GPIO_PTOR_PTTO15_MASK (0x8000U) +#define GPIO_PTOR_PTTO15_SHIFT (15U) +/*! PTTO15 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK) + +#define GPIO_PTOR_PTTO16_MASK (0x10000U) +#define GPIO_PTOR_PTTO16_SHIFT (16U) +/*! PTTO16 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK) + +#define GPIO_PTOR_PTTO17_MASK (0x20000U) +#define GPIO_PTOR_PTTO17_SHIFT (17U) +/*! PTTO17 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK) + +#define GPIO_PTOR_PTTO18_MASK (0x40000U) +#define GPIO_PTOR_PTTO18_SHIFT (18U) +/*! PTTO18 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK) + +#define GPIO_PTOR_PTTO19_MASK (0x80000U) +#define GPIO_PTOR_PTTO19_SHIFT (19U) +/*! PTTO19 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK) + +#define GPIO_PTOR_PTTO20_MASK (0x100000U) +#define GPIO_PTOR_PTTO20_SHIFT (20U) +/*! PTTO20 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK) + +#define GPIO_PTOR_PTTO21_MASK (0x200000U) +#define GPIO_PTOR_PTTO21_SHIFT (21U) +/*! PTTO21 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK) + +#define GPIO_PTOR_PTTO22_MASK (0x400000U) +#define GPIO_PTOR_PTTO22_SHIFT (22U) +/*! PTTO22 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK) + +#define GPIO_PTOR_PTTO23_MASK (0x800000U) +#define GPIO_PTOR_PTTO23_SHIFT (23U) +/*! PTTO23 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK) + +#define GPIO_PTOR_PTTO24_MASK (0x1000000U) +#define GPIO_PTOR_PTTO24_SHIFT (24U) +/*! PTTO24 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK) + +#define GPIO_PTOR_PTTO25_MASK (0x2000000U) +#define GPIO_PTOR_PTTO25_SHIFT (25U) +/*! PTTO25 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK) + +#define GPIO_PTOR_PTTO26_MASK (0x4000000U) +#define GPIO_PTOR_PTTO26_SHIFT (26U) +/*! PTTO26 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK) + +#define GPIO_PTOR_PTTO27_MASK (0x8000000U) +#define GPIO_PTOR_PTTO27_SHIFT (27U) +/*! PTTO27 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK) + +#define GPIO_PTOR_PTTO28_MASK (0x10000000U) +#define GPIO_PTOR_PTTO28_SHIFT (28U) +/*! PTTO28 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK) + +#define GPIO_PTOR_PTTO29_MASK (0x20000000U) +#define GPIO_PTOR_PTTO29_SHIFT (29U) +/*! PTTO29 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK) + +#define GPIO_PTOR_PTTO30_MASK (0x40000000U) +#define GPIO_PTOR_PTTO30_SHIFT (30U) +/*! PTTO30 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK) + +#define GPIO_PTOR_PTTO31_MASK (0x80000000U) +#define GPIO_PTOR_PTTO31_SHIFT (31U) +/*! PTTO31 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK) +/*! @} */ + +/*! @name PDIR - Port Data Input */ +/*! @{ */ + +#define GPIO_PDIR_PDI0_MASK (0x1U) +#define GPIO_PDIR_PDI0_SHIFT (0U) +/*! PDI0 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK) + +#define GPIO_PDIR_PDI1_MASK (0x2U) +#define GPIO_PDIR_PDI1_SHIFT (1U) +/*! PDI1 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK) + +#define GPIO_PDIR_PDI2_MASK (0x4U) +#define GPIO_PDIR_PDI2_SHIFT (2U) +/*! PDI2 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK) + +#define GPIO_PDIR_PDI3_MASK (0x8U) +#define GPIO_PDIR_PDI3_SHIFT (3U) +/*! PDI3 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK) + +#define GPIO_PDIR_PDI4_MASK (0x10U) +#define GPIO_PDIR_PDI4_SHIFT (4U) +/*! PDI4 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK) + +#define GPIO_PDIR_PDI5_MASK (0x20U) +#define GPIO_PDIR_PDI5_SHIFT (5U) +/*! PDI5 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK) + +#define GPIO_PDIR_PDI6_MASK (0x40U) +#define GPIO_PDIR_PDI6_SHIFT (6U) +/*! PDI6 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK) + +#define GPIO_PDIR_PDI7_MASK (0x80U) +#define GPIO_PDIR_PDI7_SHIFT (7U) +/*! PDI7 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK) + +#define GPIO_PDIR_PDI8_MASK (0x100U) +#define GPIO_PDIR_PDI8_SHIFT (8U) +/*! PDI8 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK) + +#define GPIO_PDIR_PDI9_MASK (0x200U) +#define GPIO_PDIR_PDI9_SHIFT (9U) +/*! PDI9 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK) + +#define GPIO_PDIR_PDI10_MASK (0x400U) +#define GPIO_PDIR_PDI10_SHIFT (10U) +/*! PDI10 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK) + +#define GPIO_PDIR_PDI11_MASK (0x800U) +#define GPIO_PDIR_PDI11_SHIFT (11U) +/*! PDI11 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK) + +#define GPIO_PDIR_PDI12_MASK (0x1000U) +#define GPIO_PDIR_PDI12_SHIFT (12U) +/*! PDI12 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK) + +#define GPIO_PDIR_PDI13_MASK (0x2000U) +#define GPIO_PDIR_PDI13_SHIFT (13U) +/*! PDI13 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK) + +#define GPIO_PDIR_PDI14_MASK (0x4000U) +#define GPIO_PDIR_PDI14_SHIFT (14U) +/*! PDI14 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK) + +#define GPIO_PDIR_PDI15_MASK (0x8000U) +#define GPIO_PDIR_PDI15_SHIFT (15U) +/*! PDI15 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK) + +#define GPIO_PDIR_PDI16_MASK (0x10000U) +#define GPIO_PDIR_PDI16_SHIFT (16U) +/*! PDI16 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK) + +#define GPIO_PDIR_PDI17_MASK (0x20000U) +#define GPIO_PDIR_PDI17_SHIFT (17U) +/*! PDI17 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK) + +#define GPIO_PDIR_PDI18_MASK (0x40000U) +#define GPIO_PDIR_PDI18_SHIFT (18U) +/*! PDI18 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK) + +#define GPIO_PDIR_PDI19_MASK (0x80000U) +#define GPIO_PDIR_PDI19_SHIFT (19U) +/*! PDI19 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK) + +#define GPIO_PDIR_PDI20_MASK (0x100000U) +#define GPIO_PDIR_PDI20_SHIFT (20U) +/*! PDI20 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK) + +#define GPIO_PDIR_PDI21_MASK (0x200000U) +#define GPIO_PDIR_PDI21_SHIFT (21U) +/*! PDI21 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK) + +#define GPIO_PDIR_PDI22_MASK (0x400000U) +#define GPIO_PDIR_PDI22_SHIFT (22U) +/*! PDI22 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK) + +#define GPIO_PDIR_PDI23_MASK (0x800000U) +#define GPIO_PDIR_PDI23_SHIFT (23U) +/*! PDI23 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK) + +#define GPIO_PDIR_PDI24_MASK (0x1000000U) +#define GPIO_PDIR_PDI24_SHIFT (24U) +/*! PDI24 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK) + +#define GPIO_PDIR_PDI25_MASK (0x2000000U) +#define GPIO_PDIR_PDI25_SHIFT (25U) +/*! PDI25 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK) + +#define GPIO_PDIR_PDI26_MASK (0x4000000U) +#define GPIO_PDIR_PDI26_SHIFT (26U) +/*! PDI26 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK) + +#define GPIO_PDIR_PDI27_MASK (0x8000000U) +#define GPIO_PDIR_PDI27_SHIFT (27U) +/*! PDI27 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK) + +#define GPIO_PDIR_PDI28_MASK (0x10000000U) +#define GPIO_PDIR_PDI28_SHIFT (28U) +/*! PDI28 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK) + +#define GPIO_PDIR_PDI29_MASK (0x20000000U) +#define GPIO_PDIR_PDI29_SHIFT (29U) +/*! PDI29 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK) + +#define GPIO_PDIR_PDI30_MASK (0x40000000U) +#define GPIO_PDIR_PDI30_SHIFT (30U) +/*! PDI30 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK) + +#define GPIO_PDIR_PDI31_MASK (0x80000000U) +#define GPIO_PDIR_PDI31_SHIFT (31U) +/*! PDI31 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK) +/*! @} */ + +/*! @name PDDR - Port Data Direction */ +/*! @{ */ + +#define GPIO_PDDR_PDD0_MASK (0x1U) +#define GPIO_PDDR_PDD0_SHIFT (0U) +/*! PDD0 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK) + +#define GPIO_PDDR_PDD1_MASK (0x2U) +#define GPIO_PDDR_PDD1_SHIFT (1U) +/*! PDD1 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK) + +#define GPIO_PDDR_PDD2_MASK (0x4U) +#define GPIO_PDDR_PDD2_SHIFT (2U) +/*! PDD2 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK) + +#define GPIO_PDDR_PDD3_MASK (0x8U) +#define GPIO_PDDR_PDD3_SHIFT (3U) +/*! PDD3 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK) + +#define GPIO_PDDR_PDD4_MASK (0x10U) +#define GPIO_PDDR_PDD4_SHIFT (4U) +/*! PDD4 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK) + +#define GPIO_PDDR_PDD5_MASK (0x20U) +#define GPIO_PDDR_PDD5_SHIFT (5U) +/*! PDD5 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK) + +#define GPIO_PDDR_PDD6_MASK (0x40U) +#define GPIO_PDDR_PDD6_SHIFT (6U) +/*! PDD6 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK) + +#define GPIO_PDDR_PDD7_MASK (0x80U) +#define GPIO_PDDR_PDD7_SHIFT (7U) +/*! PDD7 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK) + +#define GPIO_PDDR_PDD8_MASK (0x100U) +#define GPIO_PDDR_PDD8_SHIFT (8U) +/*! PDD8 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK) + +#define GPIO_PDDR_PDD9_MASK (0x200U) +#define GPIO_PDDR_PDD9_SHIFT (9U) +/*! PDD9 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK) + +#define GPIO_PDDR_PDD10_MASK (0x400U) +#define GPIO_PDDR_PDD10_SHIFT (10U) +/*! PDD10 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK) + +#define GPIO_PDDR_PDD11_MASK (0x800U) +#define GPIO_PDDR_PDD11_SHIFT (11U) +/*! PDD11 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK) + +#define GPIO_PDDR_PDD12_MASK (0x1000U) +#define GPIO_PDDR_PDD12_SHIFT (12U) +/*! PDD12 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK) + +#define GPIO_PDDR_PDD13_MASK (0x2000U) +#define GPIO_PDDR_PDD13_SHIFT (13U) +/*! PDD13 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK) + +#define GPIO_PDDR_PDD14_MASK (0x4000U) +#define GPIO_PDDR_PDD14_SHIFT (14U) +/*! PDD14 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK) + +#define GPIO_PDDR_PDD15_MASK (0x8000U) +#define GPIO_PDDR_PDD15_SHIFT (15U) +/*! PDD15 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK) + +#define GPIO_PDDR_PDD16_MASK (0x10000U) +#define GPIO_PDDR_PDD16_SHIFT (16U) +/*! PDD16 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK) + +#define GPIO_PDDR_PDD17_MASK (0x20000U) +#define GPIO_PDDR_PDD17_SHIFT (17U) +/*! PDD17 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK) + +#define GPIO_PDDR_PDD18_MASK (0x40000U) +#define GPIO_PDDR_PDD18_SHIFT (18U) +/*! PDD18 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK) + +#define GPIO_PDDR_PDD19_MASK (0x80000U) +#define GPIO_PDDR_PDD19_SHIFT (19U) +/*! PDD19 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK) + +#define GPIO_PDDR_PDD20_MASK (0x100000U) +#define GPIO_PDDR_PDD20_SHIFT (20U) +/*! PDD20 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK) + +#define GPIO_PDDR_PDD21_MASK (0x200000U) +#define GPIO_PDDR_PDD21_SHIFT (21U) +/*! PDD21 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK) + +#define GPIO_PDDR_PDD22_MASK (0x400000U) +#define GPIO_PDDR_PDD22_SHIFT (22U) +/*! PDD22 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK) + +#define GPIO_PDDR_PDD23_MASK (0x800000U) +#define GPIO_PDDR_PDD23_SHIFT (23U) +/*! PDD23 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK) + +#define GPIO_PDDR_PDD24_MASK (0x1000000U) +#define GPIO_PDDR_PDD24_SHIFT (24U) +/*! PDD24 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK) + +#define GPIO_PDDR_PDD25_MASK (0x2000000U) +#define GPIO_PDDR_PDD25_SHIFT (25U) +/*! PDD25 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK) + +#define GPIO_PDDR_PDD26_MASK (0x4000000U) +#define GPIO_PDDR_PDD26_SHIFT (26U) +/*! PDD26 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK) + +#define GPIO_PDDR_PDD27_MASK (0x8000000U) +#define GPIO_PDDR_PDD27_SHIFT (27U) +/*! PDD27 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK) + +#define GPIO_PDDR_PDD28_MASK (0x10000000U) +#define GPIO_PDDR_PDD28_SHIFT (28U) +/*! PDD28 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK) + +#define GPIO_PDDR_PDD29_MASK (0x20000000U) +#define GPIO_PDDR_PDD29_SHIFT (29U) +/*! PDD29 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK) + +#define GPIO_PDDR_PDD30_MASK (0x40000000U) +#define GPIO_PDDR_PDD30_SHIFT (30U) +/*! PDD30 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK) + +#define GPIO_PDDR_PDD31_MASK (0x80000000U) +#define GPIO_PDDR_PDD31_SHIFT (31U) +/*! PDD31 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK) +/*! @} */ + +/*! @name PIDR - Port Input Disable */ +/*! @{ */ + +#define GPIO_PIDR_PID0_MASK (0x1U) +#define GPIO_PIDR_PID0_SHIFT (0U) +/*! PID0 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK) + +#define GPIO_PIDR_PID1_MASK (0x2U) +#define GPIO_PIDR_PID1_SHIFT (1U) +/*! PID1 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK) + +#define GPIO_PIDR_PID2_MASK (0x4U) +#define GPIO_PIDR_PID2_SHIFT (2U) +/*! PID2 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK) + +#define GPIO_PIDR_PID3_MASK (0x8U) +#define GPIO_PIDR_PID3_SHIFT (3U) +/*! PID3 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK) + +#define GPIO_PIDR_PID4_MASK (0x10U) +#define GPIO_PIDR_PID4_SHIFT (4U) +/*! PID4 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK) + +#define GPIO_PIDR_PID5_MASK (0x20U) +#define GPIO_PIDR_PID5_SHIFT (5U) +/*! PID5 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK) + +#define GPIO_PIDR_PID6_MASK (0x40U) +#define GPIO_PIDR_PID6_SHIFT (6U) +/*! PID6 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK) + +#define GPIO_PIDR_PID7_MASK (0x80U) +#define GPIO_PIDR_PID7_SHIFT (7U) +/*! PID7 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK) + +#define GPIO_PIDR_PID8_MASK (0x100U) +#define GPIO_PIDR_PID8_SHIFT (8U) +/*! PID8 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK) + +#define GPIO_PIDR_PID9_MASK (0x200U) +#define GPIO_PIDR_PID9_SHIFT (9U) +/*! PID9 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK) + +#define GPIO_PIDR_PID10_MASK (0x400U) +#define GPIO_PIDR_PID10_SHIFT (10U) +/*! PID10 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK) + +#define GPIO_PIDR_PID11_MASK (0x800U) +#define GPIO_PIDR_PID11_SHIFT (11U) +/*! PID11 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK) + +#define GPIO_PIDR_PID12_MASK (0x1000U) +#define GPIO_PIDR_PID12_SHIFT (12U) +/*! PID12 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK) + +#define GPIO_PIDR_PID13_MASK (0x2000U) +#define GPIO_PIDR_PID13_SHIFT (13U) +/*! PID13 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK) + +#define GPIO_PIDR_PID14_MASK (0x4000U) +#define GPIO_PIDR_PID14_SHIFT (14U) +/*! PID14 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK) + +#define GPIO_PIDR_PID15_MASK (0x8000U) +#define GPIO_PIDR_PID15_SHIFT (15U) +/*! PID15 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK) + +#define GPIO_PIDR_PID16_MASK (0x10000U) +#define GPIO_PIDR_PID16_SHIFT (16U) +/*! PID16 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK) + +#define GPIO_PIDR_PID17_MASK (0x20000U) +#define GPIO_PIDR_PID17_SHIFT (17U) +/*! PID17 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK) + +#define GPIO_PIDR_PID18_MASK (0x40000U) +#define GPIO_PIDR_PID18_SHIFT (18U) +/*! PID18 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK) + +#define GPIO_PIDR_PID19_MASK (0x80000U) +#define GPIO_PIDR_PID19_SHIFT (19U) +/*! PID19 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK) + +#define GPIO_PIDR_PID20_MASK (0x100000U) +#define GPIO_PIDR_PID20_SHIFT (20U) +/*! PID20 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK) + +#define GPIO_PIDR_PID21_MASK (0x200000U) +#define GPIO_PIDR_PID21_SHIFT (21U) +/*! PID21 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK) + +#define GPIO_PIDR_PID22_MASK (0x400000U) +#define GPIO_PIDR_PID22_SHIFT (22U) +/*! PID22 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK) + +#define GPIO_PIDR_PID23_MASK (0x800000U) +#define GPIO_PIDR_PID23_SHIFT (23U) +/*! PID23 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK) + +#define GPIO_PIDR_PID24_MASK (0x1000000U) +#define GPIO_PIDR_PID24_SHIFT (24U) +/*! PID24 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK) + +#define GPIO_PIDR_PID25_MASK (0x2000000U) +#define GPIO_PIDR_PID25_SHIFT (25U) +/*! PID25 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK) + +#define GPIO_PIDR_PID26_MASK (0x4000000U) +#define GPIO_PIDR_PID26_SHIFT (26U) +/*! PID26 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK) + +#define GPIO_PIDR_PID27_MASK (0x8000000U) +#define GPIO_PIDR_PID27_SHIFT (27U) +/*! PID27 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK) + +#define GPIO_PIDR_PID28_MASK (0x10000000U) +#define GPIO_PIDR_PID28_SHIFT (28U) +/*! PID28 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK) + +#define GPIO_PIDR_PID29_MASK (0x20000000U) +#define GPIO_PIDR_PID29_SHIFT (29U) +/*! PID29 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK) + +#define GPIO_PIDR_PID30_MASK (0x40000000U) +#define GPIO_PIDR_PID30_SHIFT (30U) +/*! PID30 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK) + +#define GPIO_PIDR_PID31_MASK (0x80000000U) +#define GPIO_PIDR_PID31_SHIFT (31U) +/*! PID31 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK) +/*! @} */ + +/*! @name PDR - Pin Data */ +/*! @{ */ + +#define GPIO_PDR_PD_MASK (0x1U) +#define GPIO_PDR_PD_SHIFT (0U) +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one + */ +#define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK) +/*! @} */ + +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ +/*! @{ */ + +#define GPIO_ICR_IRQC_MASK (0xF0000U) +#define GPIO_ICR_IRQC_SHIFT (16U) +/*! IRQC - Interrupt Configuration + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers + * to generate the output trigger for use by other peripherals) + * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other + * enabled triggers to generate the output trigger for use by other peripherals) + * 0b1111..Reserved + */ +#define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK) + +#define GPIO_ICR_ISF_MASK (0x1000000U) +#define GPIO_ICR_ISF_SHIFT (24U) +/*! ISF - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK) +/*! @} */ + +/*! @name GICLR - Global Interrupt Control Low */ +/*! @{ */ + +#define GPIO_GICLR_GIWE0_MASK (0x1U) +#define GPIO_GICLR_GIWE0_SHIFT (0U) +/*! GIWE0 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK) + +#define GPIO_GICLR_GIWE1_MASK (0x2U) +#define GPIO_GICLR_GIWE1_SHIFT (1U) +/*! GIWE1 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK) + +#define GPIO_GICLR_GIWE2_MASK (0x4U) +#define GPIO_GICLR_GIWE2_SHIFT (2U) +/*! GIWE2 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK) + +#define GPIO_GICLR_GIWE3_MASK (0x8U) +#define GPIO_GICLR_GIWE3_SHIFT (3U) +/*! GIWE3 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK) + +#define GPIO_GICLR_GIWE4_MASK (0x10U) +#define GPIO_GICLR_GIWE4_SHIFT (4U) +/*! GIWE4 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK) + +#define GPIO_GICLR_GIWE5_MASK (0x20U) +#define GPIO_GICLR_GIWE5_SHIFT (5U) +/*! GIWE5 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK) + +#define GPIO_GICLR_GIWE6_MASK (0x40U) +#define GPIO_GICLR_GIWE6_SHIFT (6U) +/*! GIWE6 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK) + +#define GPIO_GICLR_GIWE7_MASK (0x80U) +#define GPIO_GICLR_GIWE7_SHIFT (7U) +/*! GIWE7 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK) + +#define GPIO_GICLR_GIWE8_MASK (0x100U) +#define GPIO_GICLR_GIWE8_SHIFT (8U) +/*! GIWE8 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK) + +#define GPIO_GICLR_GIWE9_MASK (0x200U) +#define GPIO_GICLR_GIWE9_SHIFT (9U) +/*! GIWE9 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK) + +#define GPIO_GICLR_GIWE10_MASK (0x400U) +#define GPIO_GICLR_GIWE10_SHIFT (10U) +/*! GIWE10 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK) + +#define GPIO_GICLR_GIWE11_MASK (0x800U) +#define GPIO_GICLR_GIWE11_SHIFT (11U) +/*! GIWE11 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK) + +#define GPIO_GICLR_GIWE12_MASK (0x1000U) +#define GPIO_GICLR_GIWE12_SHIFT (12U) +/*! GIWE12 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK) + +#define GPIO_GICLR_GIWE13_MASK (0x2000U) +#define GPIO_GICLR_GIWE13_SHIFT (13U) +/*! GIWE13 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK) + +#define GPIO_GICLR_GIWE14_MASK (0x4000U) +#define GPIO_GICLR_GIWE14_SHIFT (14U) +/*! GIWE14 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK) + +#define GPIO_GICLR_GIWE15_MASK (0x8000U) +#define GPIO_GICLR_GIWE15_SHIFT (15U) +/*! GIWE15 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK) + +#define GPIO_GICLR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICLR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK) +/*! @} */ + +/*! @name GICHR - Global Interrupt Control High */ +/*! @{ */ + +#define GPIO_GICHR_GIWE16_MASK (0x1U) +#define GPIO_GICHR_GIWE16_SHIFT (0U) +/*! GIWE16 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK) + +#define GPIO_GICHR_GIWE17_MASK (0x2U) +#define GPIO_GICHR_GIWE17_SHIFT (1U) +/*! GIWE17 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK) + +#define GPIO_GICHR_GIWE18_MASK (0x4U) +#define GPIO_GICHR_GIWE18_SHIFT (2U) +/*! GIWE18 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK) + +#define GPIO_GICHR_GIWE19_MASK (0x8U) +#define GPIO_GICHR_GIWE19_SHIFT (3U) +/*! GIWE19 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK) + +#define GPIO_GICHR_GIWE20_MASK (0x10U) +#define GPIO_GICHR_GIWE20_SHIFT (4U) +/*! GIWE20 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK) + +#define GPIO_GICHR_GIWE21_MASK (0x20U) +#define GPIO_GICHR_GIWE21_SHIFT (5U) +/*! GIWE21 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK) + +#define GPIO_GICHR_GIWE22_MASK (0x40U) +#define GPIO_GICHR_GIWE22_SHIFT (6U) +/*! GIWE22 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK) + +#define GPIO_GICHR_GIWE23_MASK (0x80U) +#define GPIO_GICHR_GIWE23_SHIFT (7U) +/*! GIWE23 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK) + +#define GPIO_GICHR_GIWE24_MASK (0x100U) +#define GPIO_GICHR_GIWE24_SHIFT (8U) +/*! GIWE24 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK) + +#define GPIO_GICHR_GIWE25_MASK (0x200U) +#define GPIO_GICHR_GIWE25_SHIFT (9U) +/*! GIWE25 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK) + +#define GPIO_GICHR_GIWE26_MASK (0x400U) +#define GPIO_GICHR_GIWE26_SHIFT (10U) +/*! GIWE26 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK) + +#define GPIO_GICHR_GIWE27_MASK (0x800U) +#define GPIO_GICHR_GIWE27_SHIFT (11U) +/*! GIWE27 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK) + +#define GPIO_GICHR_GIWE28_MASK (0x1000U) +#define GPIO_GICHR_GIWE28_SHIFT (12U) +/*! GIWE28 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK) + +#define GPIO_GICHR_GIWE29_MASK (0x2000U) +#define GPIO_GICHR_GIWE29_SHIFT (13U) +/*! GIWE29 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK) + +#define GPIO_GICHR_GIWE30_MASK (0x4000U) +#define GPIO_GICHR_GIWE30_SHIFT (14U) +/*! GIWE30 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK) + +#define GPIO_GICHR_GIWE31_MASK (0x8000U) +#define GPIO_GICHR_GIWE31_SHIFT (15U) +/*! GIWE31 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK) + +#define GPIO_GICHR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICHR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK) +/*! @} */ + +/*! @name ISFR - Interrupt Status Flag */ +/*! @{ */ + +#define GPIO_ISFR_ISF0_MASK (0x1U) +#define GPIO_ISFR_ISF0_SHIFT (0U) +/*! ISF0 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK) + +#define GPIO_ISFR_ISF1_MASK (0x2U) +#define GPIO_ISFR_ISF1_SHIFT (1U) +/*! ISF1 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK) + +#define GPIO_ISFR_ISF2_MASK (0x4U) +#define GPIO_ISFR_ISF2_SHIFT (2U) +/*! ISF2 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK) + +#define GPIO_ISFR_ISF3_MASK (0x8U) +#define GPIO_ISFR_ISF3_SHIFT (3U) +/*! ISF3 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK) + +#define GPIO_ISFR_ISF4_MASK (0x10U) +#define GPIO_ISFR_ISF4_SHIFT (4U) +/*! ISF4 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK) + +#define GPIO_ISFR_ISF5_MASK (0x20U) +#define GPIO_ISFR_ISF5_SHIFT (5U) +/*! ISF5 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK) + +#define GPIO_ISFR_ISF6_MASK (0x40U) +#define GPIO_ISFR_ISF6_SHIFT (6U) +/*! ISF6 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK) + +#define GPIO_ISFR_ISF7_MASK (0x80U) +#define GPIO_ISFR_ISF7_SHIFT (7U) +/*! ISF7 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK) + +#define GPIO_ISFR_ISF8_MASK (0x100U) +#define GPIO_ISFR_ISF8_SHIFT (8U) +/*! ISF8 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK) + +#define GPIO_ISFR_ISF9_MASK (0x200U) +#define GPIO_ISFR_ISF9_SHIFT (9U) +/*! ISF9 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK) + +#define GPIO_ISFR_ISF10_MASK (0x400U) +#define GPIO_ISFR_ISF10_SHIFT (10U) +/*! ISF10 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK) + +#define GPIO_ISFR_ISF11_MASK (0x800U) +#define GPIO_ISFR_ISF11_SHIFT (11U) +/*! ISF11 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK) + +#define GPIO_ISFR_ISF12_MASK (0x1000U) +#define GPIO_ISFR_ISF12_SHIFT (12U) +/*! ISF12 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK) + +#define GPIO_ISFR_ISF13_MASK (0x2000U) +#define GPIO_ISFR_ISF13_SHIFT (13U) +/*! ISF13 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK) + +#define GPIO_ISFR_ISF14_MASK (0x4000U) +#define GPIO_ISFR_ISF14_SHIFT (14U) +/*! ISF14 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK) + +#define GPIO_ISFR_ISF15_MASK (0x8000U) +#define GPIO_ISFR_ISF15_SHIFT (15U) +/*! ISF15 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK) + +#define GPIO_ISFR_ISF16_MASK (0x10000U) +#define GPIO_ISFR_ISF16_SHIFT (16U) +/*! ISF16 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK) + +#define GPIO_ISFR_ISF17_MASK (0x20000U) +#define GPIO_ISFR_ISF17_SHIFT (17U) +/*! ISF17 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK) + +#define GPIO_ISFR_ISF18_MASK (0x40000U) +#define GPIO_ISFR_ISF18_SHIFT (18U) +/*! ISF18 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK) + +#define GPIO_ISFR_ISF19_MASK (0x80000U) +#define GPIO_ISFR_ISF19_SHIFT (19U) +/*! ISF19 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK) + +#define GPIO_ISFR_ISF20_MASK (0x100000U) +#define GPIO_ISFR_ISF20_SHIFT (20U) +/*! ISF20 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK) + +#define GPIO_ISFR_ISF21_MASK (0x200000U) +#define GPIO_ISFR_ISF21_SHIFT (21U) +/*! ISF21 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK) + +#define GPIO_ISFR_ISF22_MASK (0x400000U) +#define GPIO_ISFR_ISF22_SHIFT (22U) +/*! ISF22 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK) + +#define GPIO_ISFR_ISF23_MASK (0x800000U) +#define GPIO_ISFR_ISF23_SHIFT (23U) +/*! ISF23 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK) + +#define GPIO_ISFR_ISF24_MASK (0x1000000U) +#define GPIO_ISFR_ISF24_SHIFT (24U) +/*! ISF24 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK) + +#define GPIO_ISFR_ISF25_MASK (0x2000000U) +#define GPIO_ISFR_ISF25_SHIFT (25U) +/*! ISF25 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK) + +#define GPIO_ISFR_ISF26_MASK (0x4000000U) +#define GPIO_ISFR_ISF26_SHIFT (26U) +/*! ISF26 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK) + +#define GPIO_ISFR_ISF27_MASK (0x8000000U) +#define GPIO_ISFR_ISF27_SHIFT (27U) +/*! ISF27 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK) + +#define GPIO_ISFR_ISF28_MASK (0x10000000U) +#define GPIO_ISFR_ISF28_SHIFT (28U) +/*! ISF28 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK) + +#define GPIO_ISFR_ISF29_MASK (0x20000000U) +#define GPIO_ISFR_ISF29_SHIFT (29U) +/*! ISF29 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK) + +#define GPIO_ISFR_ISF30_MASK (0x40000000U) +#define GPIO_ISFR_ISF30_SHIFT (30U) +/*! ISF30 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK) + +#define GPIO_ISFR_ISF31_MASK (0x80000000U) +#define GPIO_ISFR_ISF31_SHIFT (31U) +/*! ISF31 - Interrupt Status Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_GPIO_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_I3C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_I3C.h new file mode 100644 index 000000000..1e0c8a315 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_I3C.h @@ -0,0 +1,2513 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for I3C +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_I3C.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for I3C + * + * CMSIS Peripheral Access Layer for I3C + */ + +#if !defined(PERI_I3C_H_) +#define PERI_I3C_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- I3C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer + * @{ + */ + +/** I3C - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ + __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ + __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ + __IO uint32_t SCTRL; /**< Target Control, offset: 0xC */ + __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ + __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ + __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ + __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ + __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ + __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ + __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ + __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ + __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ + uint8_t RESERVED_2[8]; + union { /* offset: 0x54 */ + __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ + __O uint32_t SWDATAH1; /**< Target Write Data Halfword, offset: 0x54 */ + }; + uint8_t RESERVED_3[4]; + __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ + __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ + __IO uint32_t SDYNADDR; /**< Target Dynamic Address, offset: 0x64 */ + __IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */ + __IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */ + __IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ + __IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */ + __IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */ + __I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */ + __IO uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ + __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ + __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ + __IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */ + __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ + __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ + __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ + __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ + __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ + __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ + __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ + __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ + __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ + __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ + uint8_t RESERVED_5[4]; + __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ + union { /* offset: 0xCC */ + __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ + __O uint32_t MWDATAH1; /**< Controller Write Halfword Data (to Bus), offset: 0xCC */ + }; + union { /* offset: 0xD0 */ + __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ + __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ + }; + __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ + union { /* offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ + }; + __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ + uint8_t RESERVED_6[4]; + __IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */ + uint8_t RESERVED_7[52]; + __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ + uint8_t RESERVED_8[32]; + __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ + __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ + uint8_t RESERVED_9[3764]; + __I uint32_t SID; /**< Target Module ID, offset: 0xFFC */ +} I3C_Type; + +/* ---------------------------------------------------------------------------- + -- I3C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Register_Masks I3C Register Masks + * @{ + */ + +/*! @name MCONFIG - Controller Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_MSTENA_MASK (0x3U) +#define I3C_MCONFIG_MSTENA_SHIFT (0U) +/*! MSTENA - Controller Enable + * 0b00..CONTROLLER_OFF + * 0b01..CONTROLLER_ON + * 0b10..CONTROLLER_CAPABLE + * 0b11..I2C_CONTROLLER_MODE + */ +#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) + +#define I3C_MCONFIG_DISTO_MASK (0x8U) +#define I3C_MCONFIG_DISTO_SHIFT (3U) +/*! DISTO - Disable Timeout + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) + +#define I3C_MCONFIG_HKEEP_MASK (0x30U) +#define I3C_MCONFIG_HKEEP_SHIFT (4U) +/*! HKEEP - High-Keeper + * 0b00..None + * 0b01..WIRED_IN + * 0b10..PASSIVE_SDA (I2C mode, no clock stretches mode) + * 0b11..PASSIVE_ON_SDA_SCL + */ +#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) + +#define I3C_MCONFIG_ODSTOP_MASK (0x40U) +#define I3C_MCONFIG_ODSTOP_SHIFT (6U) +/*! ODSTOP - Open-drain Stop + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) + +#define I3C_MCONFIG_PPBAUD_MASK (0xF00U) +#define I3C_MCONFIG_PPBAUD_SHIFT (8U) +/*! PPBAUD - Push-Pull Baud Rate */ +#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) + +#define I3C_MCONFIG_PPLOW_MASK (0xF000U) +#define I3C_MCONFIG_PPLOW_SHIFT (12U) +/*! PPLOW - Push-Pull Low */ +#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) + +#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) +#define I3C_MCONFIG_ODBAUD_SHIFT (16U) +/*! ODBAUD - Open-drain Baud Rate */ +#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) + +#define I3C_MCONFIG_ODHPP_MASK (0x1000000U) +#define I3C_MCONFIG_ODHPP_SHIFT (24U) +/*! ODHPP - Open-drain High Push-Pull + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) + +#define I3C_MCONFIG_SKEW_MASK (0xE000000U) +#define I3C_MCONFIG_SKEW_SHIFT (25U) +/*! SKEW - Skew */ +#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) + +#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) +#define I3C_MCONFIG_I2CBAUD_SHIFT (28U) +/*! I2CBAUD - I2C Baud Rate */ +#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) +/*! @} */ + +/*! @name SCONFIG - Target Configuration */ +/*! @{ */ + +#define I3C_SCONFIG_SLVENA_MASK (0x1U) +#define I3C_SCONFIG_SLVENA_SHIFT (0U) +/*! SLVENA - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) + +#define I3C_SCONFIG_NACK_MASK (0x2U) +#define I3C_SCONFIG_NACK_SHIFT (1U) +/*! NACK - Not Acknowledge + * 0b0..Always disable NACK mode + * 0b1..Always enable NACK mode (works normally) + */ +#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) + +#define I3C_SCONFIG_MATCHSS_MASK (0x4U) +#define I3C_SCONFIG_MATCHSS_SHIFT (2U) +/*! MATCHSS - Match Start or Stop + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) + +#define I3C_SCONFIG_S0IGNORE_MASK (0x8U) +#define I3C_SCONFIG_S0IGNORE_SHIFT (3U) +/*! S0IGNORE - Ignore TE0 or TE1 Errors + * 0b0..Do not ignore TE0 or TE1 errors + * 0b1..Ignore TE0 or TE1 errors + */ +#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) + +#define I3C_SCONFIG_HDROK_MASK (0x10U) +#define I3C_SCONFIG_HDROK_SHIFT (4U) +/*! HDROK - HDR OK + * 0b0..Disable HDR OK + * 0b1..Enable HDR OK + */ +#define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK) + +#define I3C_SCONFIG_OFFLINE_MASK (0x200U) +#define I3C_SCONFIG_OFFLINE_SHIFT (9U) +/*! OFFLINE - Offline + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) + +#define I3C_SCONFIG_BAMATCH_MASK (0x3F0000U) +#define I3C_SCONFIG_BAMATCH_SHIFT (16U) +/*! BAMATCH - Bus Available Match */ +#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) + +#define I3C_SCONFIG_SADDR_MASK (0xFE000000U) +#define I3C_SCONFIG_SADDR_SHIFT (25U) +/*! SADDR - Static Address */ +#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) +/*! @} */ + +/*! @name SSTATUS - Target Status */ +/*! @{ */ + +#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) +#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) +/*! STNOTSTOP - Status not Stop + * 0b0..In STOP condition + * 0b1..Busy + */ +#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) + +#define I3C_SSTATUS_STMSG_MASK (0x2U) +#define I3C_SSTATUS_STMSG_SHIFT (1U) +/*! STMSG - Status Message + * 0b0..Idle + * 0b1..Busy + */ +#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) + +#define I3C_SSTATUS_STCCCH_MASK (0x4U) +#define I3C_SSTATUS_STCCCH_SHIFT (2U) +/*! STCCCH - Status Common Command Code Handler + * 0b0..No CCC message handled + * 0b1..Handled automatically + */ +#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) + +#define I3C_SSTATUS_STREQRD_MASK (0x8U) +#define I3C_SSTATUS_STREQRD_SHIFT (3U) +/*! STREQRD - Status Request Read + * 0b0..Not an SDR read + * 0b1..SDR read from this target or an IBI is being pushed out + */ +#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) + +#define I3C_SSTATUS_STREQWR_MASK (0x10U) +#define I3C_SSTATUS_STREQWR_SHIFT (4U) +/*! STREQWR - Status Request Write + * 0b0..Not an SDR write + * 0b1..SDR write data from the controller, but not in ENTDAA mode + */ +#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) + +#define I3C_SSTATUS_STDAA_MASK (0x20U) +#define I3C_SSTATUS_STDAA_SHIFT (5U) +/*! STDAA - Status Dynamic Address Assignment + * 0b0..Not in ENTDAA mode + * 0b1..In ENTDAA mode + */ +#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) + +#define I3C_SSTATUS_STHDR_MASK (0x40U) +#define I3C_SSTATUS_STHDR_SHIFT (6U) +/*! STHDR - Status High Data Rate + * 0b0..I3C bus not in HDR-DDR mode + * 0b1..I3C bus in HDR-DDR mode + */ +#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) + +#define I3C_SSTATUS_START_MASK (0x100U) +#define I3C_SSTATUS_START_SHIFT (8U) +/*! START - Start Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) + +#define I3C_SSTATUS_MATCHED_MASK (0x200U) +#define I3C_SSTATUS_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Flag + * 0b0..Header not matched + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Header matched + */ +#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) + +#define I3C_SSTATUS_STOP_MASK (0x400U) +#define I3C_SSTATUS_STOP_SHIFT (10U) +/*! STOP - Stop Flag + * 0b0..No Stopped state detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Stopped state detected + */ +#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) + +#define I3C_SSTATUS_RX_PEND_MASK (0x800U) +#define I3C_SSTATUS_RX_PEND_SHIFT (11U) +/*! RX_PEND - Received Message Pending + * 0b0..No received message pending + * 0b1..Received message pending + */ +#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) + +#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer Not Full + * 0b0..Transmit buffer full + * 0b1..Transmit buffer not full + */ +#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) + +#define I3C_SSTATUS_DACHG_MASK (0x2000U) +#define I3C_SSTATUS_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Flag + * 0b0..No DA change detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..DA change detected + */ +#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) + +#define I3C_SSTATUS_CCC_MASK (0x4000U) +#define I3C_SSTATUS_CCC_SHIFT (14U) +/*! CCC - Common Command Code Flag + * 0b0..CCC not received + * 0b0..No effect + * 0b1..CCC received + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) + +#define I3C_SSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_SSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error Warning */ +#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) + +#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) +#define I3C_SSTATUS_HDRMATCH_SHIFT (16U) +/*! HDRMATCH - High Data Rate Command Match Flag + * 0b0..Did not match + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Matched the I3C dynamic address + */ +#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) + +#define I3C_SSTATUS_CHANDLED_MASK (0x20000U) +#define I3C_SSTATUS_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code Handled Flag + * 0b0..CCC handling not in progress + * 0b0..No effect + * 0b1..CCC handling in progress + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) + +#define I3C_SSTATUS_EVENT_MASK (0x40000U) +#define I3C_SSTATUS_EVENT_SHIFT (18U) +/*! EVENT - Event Flag + * 0b0..No effect + * 0b0..No event occurred + * 0b1..Clear the flag + * 0b1..IBI, CR, or HJ occurred + */ +#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) + +#define I3C_SSTATUS_EVDET_MASK (0x300000U) +#define I3C_SSTATUS_EVDET_SHIFT (20U) +/*! EVDET - Event Details + * 0b00..NONE (no event or no pending event) + * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) + * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again + * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) + */ +#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) + +#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) +#define I3C_SSTATUS_IBIDIS_SHIFT (24U) +/*! IBIDIS - In-Band Interrupts Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) + +#define I3C_SSTATUS_MRDIS_MASK (0x2000000U) +#define I3C_SSTATUS_MRDIS_SHIFT (25U) +/*! MRDIS - Controller Requests Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) + +#define I3C_SSTATUS_HJDIS_MASK (0x8000000U) +#define I3C_SSTATUS_HJDIS_SHIFT (27U) +/*! HJDIS - Hot-Join Disabled + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) + +#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) +#define I3C_SSTATUS_ACTSTATE_SHIFT (28U) +/*! ACTSTATE - Activity State from Common Command Codes (CCC) + * 0b00..NO_LATENCY (normal bus operations) + * 0b01..LATENCY_1MS (1 ms of latency) + * 0b10..LATENCY_100MS (100 ms of latency) + * 0b11..LATENCY_10S (10 seconds of latency) + */ +#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) + +#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) +#define I3C_SSTATUS_TIMECTRL_SHIFT (30U) +/*! TIMECTRL - Time Control + * 0b00..NO_TIME_CONTROL (no time control is enabled) + * 0b01..SYNC_MODE (Synchronous mode is enabled) + * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) + * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) + */ +#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) +/*! @} */ + +/*! @name SCTRL - Target Control */ +/*! @{ */ + +#define I3C_SCTRL_EVENT_MASK (0x3U) +#define I3C_SCTRL_EVENT_SHIFT (0U) +/*! EVENT - Event + * 0b00..NORMAL_MODE + * 0b01..IBI + * 0b10..CONTROLLER_REQUEST + * 0b11..HOT_JOIN_REQUEST + */ +#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) + +#define I3C_SCTRL_EXTDATA_MASK (0x8U) +#define I3C_SCTRL_EXTDATA_SHIFT (3U) +/*! EXTDATA - Extended Data + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) + +#define I3C_SCTRL_IBIDATA_MASK (0xFF00U) +#define I3C_SCTRL_IBIDATA_SHIFT (8U) +/*! IBIDATA - In-Band Interrupt Data */ +#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) + +#define I3C_SCTRL_PENDINT_MASK (0xF0000U) +#define I3C_SCTRL_PENDINT_SHIFT (16U) +/*! PENDINT - Pending Interrupt */ +#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) + +#define I3C_SCTRL_ACTSTATE_MASK (0x300000U) +#define I3C_SCTRL_ACTSTATE_SHIFT (20U) +/*! ACTSTATE - Activity State of Target */ +#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) + +#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) +#define I3C_SCTRL_VENDINFO_SHIFT (24U) +/*! VENDINFO - Vendor Information */ +#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) +/*! @} */ + +/*! @name SINTSET - Target Interrupt Set */ +/*! @{ */ + +#define I3C_SINTSET_START_MASK (0x100U) +#define I3C_SINTSET_START_SHIFT (8U) +/*! START - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) + +#define I3C_SINTSET_MATCHED_MASK (0x200U) +#define I3C_SINTSET_MATCHED_SHIFT (9U) +/*! MATCHED - Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) + +#define I3C_SINTSET_STOP_MASK (0x400U) +#define I3C_SINTSET_STOP_SHIFT (10U) +/*! STOP - Stop Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) + +#define I3C_SINTSET_RXPEND_MASK (0x800U) +#define I3C_SINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) + +#define I3C_SINTSET_TXSEND_MASK (0x1000U) +#define I3C_SINTSET_TXSEND_SHIFT (12U) +/*! TXSEND - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) + +#define I3C_SINTSET_DACHG_MASK (0x2000U) +#define I3C_SINTSET_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) + +#define I3C_SINTSET_CCC_MASK (0x4000U) +#define I3C_SINTSET_CCC_SHIFT (14U) +/*! CCC - Common Command Code (CCC) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) + +#define I3C_SINTSET_ERRWARN_MASK (0x8000U) +#define I3C_SINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) + +#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTSET_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - Double Data Rate Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) + +#define I3C_SINTSET_CHANDLED_MASK (0x20000U) +#define I3C_SINTSET_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code (CCC) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) + +#define I3C_SINTSET_EVENT_MASK (0x40000U) +#define I3C_SINTSET_EVENT_SHIFT (18U) +/*! EVENT - Event Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) +/*! @} */ + +/*! @name SINTCLR - Target Interrupt Clear */ +/*! @{ */ + +#define I3C_SINTCLR_START_MASK (0x100U) +#define I3C_SINTCLR_START_SHIFT (8U) +/*! START - START Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) + +#define I3C_SINTCLR_MATCHED_MASK (0x200U) +#define I3C_SINTCLR_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) + +#define I3C_SINTCLR_STOP_MASK (0x400U) +#define I3C_SINTCLR_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) + +#define I3C_SINTCLR_RXPEND_MASK (0x800U) +#define I3C_SINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) + +#define I3C_SINTCLR_TXSEND_MASK (0x1000U) +#define I3C_SINTCLR_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) + +#define I3C_SINTCLR_DACHG_MASK (0x2000U) +#define I3C_SINTCLR_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) + +#define I3C_SINTCLR_CCC_MASK (0x4000U) +#define I3C_SINTCLR_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) + +#define I3C_SINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_SINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) + +#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) + +#define I3C_SINTCLR_CHANDLED_MASK (0x20000U) +#define I3C_SINTCLR_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) + +#define I3C_SINTCLR_EVENT_MASK (0x40000U) +#define I3C_SINTCLR_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) +/*! @} */ + +/*! @name SINTMASKED - Target Interrupt Mask */ +/*! @{ */ + +#define I3C_SINTMASKED_START_MASK (0x100U) +#define I3C_SINTMASKED_START_SHIFT (8U) +/*! START - START Interrupt Mask */ +#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) + +#define I3C_SINTMASKED_MATCHED_MASK (0x200U) +#define I3C_SINTMASKED_MATCHED_SHIFT (9U) +/*! MATCHED - MATCHED Interrupt Mask */ +#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) + +#define I3C_SINTMASKED_STOP_MASK (0x400U) +#define I3C_SINTMASKED_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Mask */ +#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) + +#define I3C_SINTMASKED_RXPEND_MASK (0x800U) +#define I3C_SINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) + +#define I3C_SINTMASKED_TXSEND_MASK (0x1000U) +#define I3C_SINTMASKED_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Mask */ +#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) + +#define I3C_SINTMASKED_DACHG_MASK (0x2000U) +#define I3C_SINTMASKED_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Mask */ +#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) + +#define I3C_SINTMASKED_CCC_MASK (0x4000U) +#define I3C_SINTMASKED_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Mask */ +#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) + +#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_SINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask */ +#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) + +#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Mask */ +#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) + +#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) +#define I3C_SINTMASKED_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Mask */ +#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) + +#define I3C_SINTMASKED_EVENT_MASK (0x40000U) +#define I3C_SINTMASKED_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Mask */ +#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) +/*! @} */ + +/*! @name SERRWARN - Target Errors and Warnings */ +/*! @{ */ + +#define I3C_SERRWARN_ORUN_MASK (0x1U) +#define I3C_SERRWARN_ORUN_SHIFT (0U) +/*! ORUN - Overrun Error Flag + * 0b0..No effect + * 0b0..No overrun error + * 0b1..Clear the flag + * 0b1..Overrun error + */ +#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) + +#define I3C_SERRWARN_URUN_MASK (0x2U) +#define I3C_SERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error Flag + * 0b0..No effect + * 0b0..No underrun error + * 0b1..Clear the flag + * 0b1..Underrun error + */ +#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) + +#define I3C_SERRWARN_URUNNACK_MASK (0x4U) +#define I3C_SERRWARN_URUNNACK_SHIFT (2U) +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error Flag + * 0b0..No effect + * 0b0..No underrun; not acknowledged error + * 0b1..Clear the flag + * 0b1..Underrun; not acknowledged error + */ +#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) + +#define I3C_SERRWARN_TERM_MASK (0x8U) +#define I3C_SERRWARN_TERM_SHIFT (3U) +/*! TERM - Terminated Error Flag + * 0b0..No effect + * 0b0..No terminated error + * 0b1..Clear the flag + * 0b1..Terminated error + */ +#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) + +#define I3C_SERRWARN_INVSTART_MASK (0x10U) +#define I3C_SERRWARN_INVSTART_SHIFT (4U) +/*! INVSTART - Invalid Start Error Flag + * 0b0..No effect + * 0b0..No invalid start error + * 0b1..Clear the flag + * 0b1..Invalid start error + */ +#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) + +#define I3C_SERRWARN_SPAR_MASK (0x100U) +#define I3C_SERRWARN_SPAR_SHIFT (8U) +/*! SPAR - SDR Parity Error Flag + * 0b0..No SDR parity error + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..SDR parity error + */ +#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) + +#define I3C_SERRWARN_HPAR_MASK (0x200U) +#define I3C_SERRWARN_HPAR_SHIFT (9U) +/*! HPAR - HDR Parity Error Flag + * 0b0..No HDR parity error + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..HDR parity error + */ +#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) + +#define I3C_SERRWARN_HCRC_MASK (0x400U) +#define I3C_SERRWARN_HCRC_SHIFT (10U) +/*! HCRC - HDR-DDR CRC Error Flag + * 0b0..No HDR-DDR CRC error occurred + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..HDR-DDR CRC error occurred + */ +#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) + +#define I3C_SERRWARN_S0S1_MASK (0x800U) +#define I3C_SERRWARN_S0S1_SHIFT (11U) +/*! S0S1 - TE0 or TE1 Error Flag + * 0b0..No TE0 or TE1 error occurred + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..TE0 or TE1 error occurred + */ +#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) + +#define I3C_SERRWARN_OREAD_MASK (0x10000U) +#define I3C_SERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Over-Read Error Flag + * 0b0..No effect + * 0b0..No over-read error + * 0b1..Clear the flag + * 0b1..Over-read error + */ +#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) + +#define I3C_SERRWARN_OWRITE_MASK (0x20000U) +#define I3C_SERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Over-Write Error Flag + * 0b0..No effect + * 0b0..No overwrite error + * 0b1..Clear the flag + * 0b1..Overwrite error + */ +#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) +/*! @} */ + +/*! @name SDMACTRL - Target DMA Control */ +/*! @{ */ + +#define I3C_SDMACTRL_DMAFB_MASK (0x3U) +#define I3C_SDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA Read (From-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) + +#define I3C_SDMACTRL_DMATB_MASK (0xCU) +#define I3C_SDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA Write (To-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) + +#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - Width of DMA Operations + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) + * 0b11.. + */ +#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name SDATACTRL - Target Data Control */ +/*! @{ */ + +#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) + +#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) + +#define I3C_SDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_SDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Cannot be changed + * 0b1..Can be changed + */ +#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) + +#define I3C_SDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_SDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Default (trigger when 1 less than full or less) + */ +#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) + +#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_SDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty (default) + * 0b01..Trigger when 1/4 or more full + * 0b10..Trigger when 1/2 or more full + * 0b11..Trigger when 3/4 or more full + */ +#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) + +#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Count of Entries in Transmit */ +#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) + +#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Count of Entries in Receive */ +#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) + +#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_SDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) + +#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name SWDATAB - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB_DATA_MASK (0xFFU) +#define I3C_SWDATAB_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) + +#define I3C_SWDATAB_END_MASK (0x100U) +#define I3C_SWDATAB_END_SHIFT (8U) +/*! END - End + * 0b0..Not the end + * 0b1..End + */ +#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) + +#define I3C_SWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_SWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End Also + * 0b0..Not the end + * 0b1..End + */ +#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name SWDATABE - Target Write Data Byte End */ +/*! @{ */ + +#define I3C_SWDATABE_DATA_MASK (0xFFU) +#define I3C_SWDATABE_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH_DATA0_MASK (0xFFU) +#define I3C_SWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) + +#define I3C_SWDATAH_DATA1_MASK (0xFF00U) +#define I3C_SWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) + +#define I3C_SWDATAH_END_MASK (0x10000U) +#define I3C_SWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) +/*! @} */ + +/*! @name SWDATAHE - Target Write Data Halfword End */ +/*! @{ */ + +#define I3C_SWDATAHE_DATA0_MASK (0xFFU) +#define I3C_SWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) + +#define I3C_SWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_SWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name SRDATAB - Target Read Data Byte */ +/*! @{ */ + +#define I3C_SRDATAB_DATA0_MASK (0xFFU) +#define I3C_SRDATAB_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) +/*! @} */ + +/*! @name SRDATAH - Target Read Data Halfword */ +/*! @{ */ + +#define I3C_SRDATAH_LSB_MASK (0xFFU) +#define I3C_SRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) + +#define I3C_SRDATAH_MSB_MASK (0xFF00U) +#define I3C_SRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) +/*! @} */ + +/*! @name SWDATAB1 - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB1_DATA_MASK (0xFFU) +#define I3C_SWDATAB1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH1 - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH1_DATA_MASK (0xFFFFU) +#define I3C_SWDATAH1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAH1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK) +/*! @} */ + +/*! @name SCAPABILITIES2 - Target Capabilities 2 */ +/*! @{ */ + +#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) +#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) +/*! MAPCNT - Map Count */ +#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) + +#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) +#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) +/*! I2C10B - I2C 10-bit Address + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) + +#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) +#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) +/*! I2CDEVID - I2C Device ID + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) + +#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) +#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) +/*! IBIEXT - In-Band Interrupt EXTDATA + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) + +#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) +#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) +/*! IBIXREG - In-Band Interrupt Extended Register + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) + +#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) +#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) +/*! SLVRST - Target Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) + +#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) +#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) +/*! GROUP - Group + * 0b00..v1.1 group addressing not supported + * 0b01..One group supported + * 0b10..Two groups supported + * 0b11..Three groups supported + */ +#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) + +#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) +#define I3C_SCAPABILITIES2_AASA_SHIFT (21U) +/*! AASA - SETAASA + * 0b0..SETAASA not supported + * 0b1..SETAASA supported + */ +#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) + +#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) +#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) +/*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable + * 0b0..Not subscriber capable + * 0b1..Subscriber capable + */ +#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) + +#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) +#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) +/*! SSTWR - Target-Target(s)-Tunnel Write Capable + * 0b0..Not write capable + * 0b1..Write capable + */ +#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) +/*! @} */ + +/*! @name SCAPABILITIES - Target Capabilities */ +/*! @{ */ + +#define I3C_SCAPABILITIES_IDENA_MASK (0x3U) +#define I3C_SCAPABILITIES_IDENA_SHIFT (0U) +/*! IDENA - ID 48b Handler + * 0b00..Application + * 0b01..Hardware + * 0b10..Hardware, but the I3C module instance handles ID 48b + * 0b11..A part number register (PARTNO) + */ +#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) + +#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) +#define I3C_SCAPABILITIES_IDREG_SHIFT (2U) +/*! IDREG - ID Register + * 0b0000..All ID register features disabled + * 0b1xxx..A Bus Characteristics Register (BCR) is available + * 0bx1xx..A Device Characteristic Register (DCR) is available + * 0bxx1x..An ID Random field is available + * 0bxxx1..ID Instance is a register; used if there is no PARTNO register + */ +#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) + +#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) +#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) +/*! HDRSUPP - High Data Rate Support + * 0b00..No HDR modes supported + * 0b01..DDR mode supported + */ +#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) + +#define I3C_SCAPABILITIES_MASTER_MASK (0x200U) +#define I3C_SCAPABILITIES_MASTER_SHIFT (9U) +/*! MASTER - Controller + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) + +#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) +#define I3C_SCAPABILITIES_SADDR_SHIFT (10U) +/*! SADDR - Static Address + * 0b00..No static address + * 0b01..Static address is fixed in hardware + * 0b10..Hardware controls the static address dynamically (for example, from the pin strap) + * 0b11..SCONFIG register supplies the static address + */ +#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) + +#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) +#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) +/*! CCCHANDLE - Common Command Codes Handling + * 0b0000..All handling features disabled + * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] + * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] + * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed + * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items + */ +#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) + +#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) +#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) +/*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events + * 0b00000..Application cannot generate IBI, CR, or HJ + * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing + * 0bx1xxx..Application can generate a Hot-Join event + * 0bxx1xx..Application can generate a controller request for a secondary controller + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register + * 0bxxxx1..Application can generate an IBI + */ +#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) + +#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) +#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) +/*! TIMECTRL - Time Control + * 0b0..No time control supported + * 0b1..At least one time-control type supported + */ +#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) + +#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) +#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) +/*! EXTFIFO - External FIFO + * 0b000..No external FIFO available + * 0b001..Standard available or free external FIFO + * 0b010..Request track external FIFO + */ +#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) + +#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) +#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) +/*! FIFOTX - FIFO Transmit + * 0b00..Two + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) + +#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) +#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) +/*! FIFORX - FIFO Receive + * 0b00..Two or three + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) + +#define I3C_SCAPABILITIES_INT_MASK (0x40000000U) +#define I3C_SCAPABILITIES_INT_SHIFT (30U) +/*! INT - Interrupts + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) + +#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) +#define I3C_SCAPABILITIES_DMA_SHIFT (31U) +/*! DMA - Direct Memory Access + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) +/*! @} */ + +/*! @name SDYNADDR - Target Dynamic Address */ +/*! @{ */ + +#define I3C_SDYNADDR_DAVALID_MASK (0x1U) +#define I3C_SDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b0..DANOTASSIGNED: a dynamic address is not assigned + * 0b1..DAASSIGNED: a dynamic address is assigned + */ +#define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) + +#define I3C_SDYNADDR_DADDR_MASK (0xFEU) +#define I3C_SDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK) + +#define I3C_SDYNADDR_MAPSA_MASK (0x1000U) +#define I3C_SDYNADDR_MAPSA_SHIFT (12U) +/*! MAPSA - Map a Static Address */ +#define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK) + +#define I3C_SDYNADDR_SA10B_MASK (0xE000U) +#define I3C_SDYNADDR_SA10B_SHIFT (13U) +/*! SA10B - 10-Bit Static Address */ +#define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) + +#define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) +#define I3C_SDYNADDR_KEY_SHIFT (16U) +/*! KEY - Key */ +#define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK) +/*! @} */ + +/*! @name SMAXLIMITS - Target Maximum Limits */ +/*! @{ */ + +#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) +#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) +/*! MAXRD - Maximum Read Length */ +#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) + +#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) +#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) +/*! MAXWR - Maximum Write Length */ +#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) +/*! @} */ + +/*! @name SIDPARTNO - Target ID Part Number */ +/*! @{ */ + +#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) +#define I3C_SIDPARTNO_PARTNO_SHIFT (0U) +/*! PARTNO - Part Number */ +#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) +/*! @} */ + +/*! @name SIDEXT - Target ID Extension */ +/*! @{ */ + +#define I3C_SIDEXT_DCR_MASK (0xFF00U) +#define I3C_SIDEXT_DCR_SHIFT (8U) +/*! DCR - Device Characteristic Register */ +#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) + +#define I3C_SIDEXT_BCR_MASK (0xFF0000U) +#define I3C_SIDEXT_BCR_SHIFT (16U) +/*! BCR - Bus Characteristics Register */ +#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) +/*! @} */ + +/*! @name SVENDORID - Target Vendor ID */ +/*! @{ */ + +#define I3C_SVENDORID_VID_MASK (0x7FFFU) +#define I3C_SVENDORID_VID_SHIFT (0U) +/*! VID - Vendor ID */ +#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) +/*! @} */ + +/*! @name STCCLOCK - Target Time Control Clock */ +/*! @{ */ + +#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) +#define I3C_STCCLOCK_ACCURACY_SHIFT (0U) +/*! ACCURACY - Clock Accuracy */ +#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) + +#define I3C_STCCLOCK_FREQ_MASK (0xFF00U) +#define I3C_STCCLOCK_FREQ_SHIFT (8U) +/*! FREQ - Clock Frequency */ +#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) +/*! @} */ + +/*! @name SMSGMAPADDR - Target Message Map Address */ +/*! @{ */ + +#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) +#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) +/*! MAPLAST - Matched Address Index */ +#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) + +#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) +#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) +/*! LASTSTATIC - Last Static Address Matched + * 0b0..I3C dynamic address + * 0b1..I2C static address + */ +#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) +#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) +/*! MAPLASTM1 - Matched Previous Address Index 1 */ +#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) +#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) +/*! MAPLASTM2 - Matched Previous Index 2 */ +#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) +/*! @} */ + +/*! @name MCONFIG_EXT - Controller Extended Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK (0x30000U) +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT (16U) +/*! I3C_CAS_DEL - I3C CAS Delay After START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 3/2 + */ +#define I3C_MCONFIG_EXT_I3C_CAS_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK) + +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK (0xC0000U) +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT (18U) +/*! I3C_CASR_DEL - I3C CAS Delay After Repeated START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 1 1/2 + */ +#define I3C_MCONFIG_EXT_I3C_CASR_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK) +/*! @} */ + +/*! @name MCTRL - Controller Control */ +/*! @{ */ + +#define I3C_MCTRL_REQUEST_MASK (0x7U) +#define I3C_MCTRL_REQUEST_SHIFT (0U) +/*! REQUEST - Request + * 0b000..NONE + * 0b001..EMITSTARTADDR + * 0b010..EMITSTOP + * 0b011..IBIACKNACK + * 0b100..PROCESSDAA + * 0b101.. + * 0b110..Force Exit and Target Reset + * 0b111..AUTOIBI + */ +#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) + +#define I3C_MCTRL_TYPE_MASK (0x30U) +#define I3C_MCTRL_TYPE_SHIFT (4U) +/*! TYPE - Bus Type with EmitStartAddr + * 0b00..I3C + * 0b01..I2C + * 0b10..DDR + * 0b11.. + */ +#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) + +#define I3C_MCTRL_IBIRESP_MASK (0xC0U) +#define I3C_MCTRL_IBIRESP_SHIFT (6U) +/*! IBIRESP - In-Band Interrupt Response + * 0b00..ACK (acknowledge) + * 0b01..NACK (reject) + * 0b10..Acknowledge with mandatory byte + * 0b11..Manual + */ +#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) + +#define I3C_MCTRL_DIR_MASK (0x100U) +#define I3C_MCTRL_DIR_SHIFT (8U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) + +#define I3C_MCTRL_ADDR_MASK (0xFE00U) +#define I3C_MCTRL_ADDR_SHIFT (9U) +/*! ADDR - Address */ +#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) + +#define I3C_MCTRL_RDTERM_MASK (0xFF0000U) +#define I3C_MCTRL_RDTERM_SHIFT (16U) +/*! RDTERM - Read Terminate Counter */ +#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) +/*! @} */ + +/*! @name MSTATUS - Controller Status */ +/*! @{ */ + +#define I3C_MSTATUS_STATE_MASK (0x7U) +#define I3C_MSTATUS_STATE_SHIFT (0U) +/*! STATE - State of the Controller + * 0b000..IDLE (bus has stopped) + * 0b001..SLVREQ (target request) + * 0b010..MSGSDR + * 0b011..NORMACT + * 0b100..MSGDDR + * 0b101..DAA + * 0b110..IBIACK + * 0b111..IBIRCV + */ +#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) + +#define I3C_MSTATUS_BETWEEN_MASK (0x10U) +#define I3C_MSTATUS_BETWEEN_SHIFT (4U) +/*! BETWEEN - Between + * 0b0..Inactive (for other cases) + * 0b1..Active + */ +#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) + +#define I3C_MSTATUS_NACKED_MASK (0x20U) +#define I3C_MSTATUS_NACKED_SHIFT (5U) +/*! NACKED - Not Acknowledged + * 0b0..Not NACKed + * 0b1..NACKed (not acknowledged) + */ +#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) + +#define I3C_MSTATUS_IBITYPE_MASK (0xC0U) +#define I3C_MSTATUS_IBITYPE_SHIFT (6U) +/*! IBITYPE - In-Band Interrupt (IBI) Type + * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) + * 0b01..IBI + * 0b10..CR + * 0b11..HJ + */ +#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) + +#define I3C_MSTATUS_SLVSTART_MASK (0x100U) +#define I3C_MSTATUS_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Flag + * 0b0..No effect + * 0b0..Target not requesting START + * 0b1..Clear the flag + * 0b1..Target requesting START + */ +#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) + +#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) +#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Flag + * 0b0..No effect + * 0b0..Not done + * 0b1..Clear the flag + * 0b1..Done + */ +#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) + +#define I3C_MSTATUS_COMPLETE_MASK (0x400U) +#define I3C_MSTATUS_COMPLETE_SHIFT (10U) +/*! COMPLETE - Complete Flag + * 0b0..No effect + * 0b0..Not complete + * 0b1..Clear the flag + * 0b1..Complete + */ +#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) + +#define I3C_MSTATUS_RXPEND_MASK (0x800U) +#define I3C_MSTATUS_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND + * 0b0..No receive message pending + * 0b1..Receive message pending + */ +#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) + +#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TX Buffer or FIFO Not Full + * 0b0..Receive buffer or FIFO full + * 0b1..Receive buffer or FIFO not full + */ +#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) + +#define I3C_MSTATUS_IBIWON_MASK (0x2000U) +#define I3C_MSTATUS_IBIWON_SHIFT (13U) +/*! IBIWON - In-Band Interrupt (IBI) Won Flag + * 0b0..No IBI arbitration won + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..IBI arbitration won + */ +#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) + +#define I3C_MSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_MSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning + * 0b0..No error or warning + * 0b1..Error or warning + */ +#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) + +#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) +#define I3C_MSTATUS_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Module is now Controller Flag + * 0b0..No effect + * 0b0..Not a controller + * 0b1..Clear the flag + * 0b1..Controller + */ +#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) + +#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) +#define I3C_MSTATUS_IBIADDR_SHIFT (24U) +/*! IBIADDR - IBI Address */ +#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) +/*! @} */ + +/*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */ +/*! @{ */ + +#define I3C_MIBIRULES_ADDR0_MASK (0x3FU) +#define I3C_MIBIRULES_ADDR0_SHIFT (0U) +/*! ADDR0 - ADDR0 */ +#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) + +#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) +#define I3C_MIBIRULES_ADDR1_SHIFT (6U) +/*! ADDR1 - ADDR1 */ +#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) + +#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) +#define I3C_MIBIRULES_ADDR2_SHIFT (12U) +/*! ADDR2 - ADDR2 */ +#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) + +#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) +#define I3C_MIBIRULES_ADDR3_SHIFT (18U) +/*! ADDR3 - ADDR3 */ +#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) + +#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) +#define I3C_MIBIRULES_ADDR4_SHIFT (24U) +/*! ADDR4 - ADDR4 */ +#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) + +#define I3C_MIBIRULES_MSB0_MASK (0x40000000U) +#define I3C_MIBIRULES_MSB0_SHIFT (30U) +/*! MSB0 - Most Significant Address Bit is 0 + * 0b0..MSB is not 0 + * 0b1..MSB is 0 + */ +#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) + +#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) +#define I3C_MIBIRULES_NOBYTE_SHIFT (31U) +/*! NOBYTE - No IBI byte + * 0b0..With mandatory IBI byte + * 0b1..Without mandatory IBI byte + */ +#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) +/*! @} */ + +/*! @name MINTSET - Controller Interrupt Set */ +/*! @{ */ + +#define I3C_MINTSET_SLVSTART_MASK (0x100U) +#define I3C_MINTSET_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) + +#define I3C_MINTSET_MCTRLDONE_MASK (0x200U) +#define I3C_MINTSET_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) + +#define I3C_MINTSET_COMPLETE_MASK (0x400U) +#define I3C_MINTSET_COMPLETE_SHIFT (10U) +/*! COMPLETE - Completed Message Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) + +#define I3C_MINTSET_RXPEND_MASK (0x800U) +#define I3C_MINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Pending Interrupt Enable */ +#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) + +#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTSET_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) + +#define I3C_MINTSET_IBIWON_MASK (0x2000U) +#define I3C_MINTSET_IBIWON_SHIFT (13U) +/*! IBIWON - IBI Won Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) + +#define I3C_MINTSET_ERRWARN_MASK (0x8000U) +#define I3C_MINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) + +#define I3C_MINTSET_NOWMASTER_MASK (0x80000U) +#define I3C_MINTSET_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Now Controller Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTCLR - Controller Interrupt Clear */ +/*! @{ */ + +#define I3C_MINTCLR_SLVSTART_MASK (0x100U) +#define I3C_MINTCLR_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt enable cleared + */ +#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) + +#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) +#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt enable cleared + */ +#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) + +#define I3C_MINTCLR_COMPLETE_MASK (0x400U) +#define I3C_MINTCLR_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt enable cleared + */ +#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) + +#define I3C_MINTCLR_RXPEND_MASK (0x800U) +#define I3C_MINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt enable cleared + */ +#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) + +#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt enable cleared + */ +#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) + +#define I3C_MINTCLR_IBIWON_MASK (0x2000U) +#define I3C_MINTCLR_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt enable cleared + */ +#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) + +#define I3C_MINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_MINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt enable cleared + */ +#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) + +#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) +#define I3C_MINTCLR_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt enable cleared + */ +#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTMASKED - Controller Interrupt Mask */ +/*! @{ */ + +#define I3C_MINTMASKED_SLVSTART_MASK (0x100U) +#define I3C_MINTMASKED_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) + +#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) +#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) + +#define I3C_MINTMASKED_COMPLETE_MASK (0x400U) +#define I3C_MINTMASKED_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) + +#define I3C_MINTMASKED_RXPEND_MASK (0x800U) +#define I3C_MINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) + +#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) + +#define I3C_MINTMASKED_IBIWON_MASK (0x2000U) +#define I3C_MINTMASKED_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) + +#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_MINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) + +#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) +#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) +/*! @} */ + +/*! @name MERRWARN - Controller Errors and Warnings */ +/*! @{ */ + +#define I3C_MERRWARN_URUN_MASK (0x2U) +#define I3C_MERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) + +#define I3C_MERRWARN_NACK_MASK (0x4U) +#define I3C_MERRWARN_NACK_SHIFT (2U) +/*! NACK - Not Acknowledge Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) + +#define I3C_MERRWARN_WRABT_MASK (0x8U) +#define I3C_MERRWARN_WRABT_SHIFT (3U) +/*! WRABT - Write Abort Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) + +#define I3C_MERRWARN_TERM_MASK (0x10U) +#define I3C_MERRWARN_TERM_SHIFT (4U) +/*! TERM - Terminate Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) + +#define I3C_MERRWARN_HPAR_MASK (0x200U) +#define I3C_MERRWARN_HPAR_SHIFT (9U) +/*! HPAR - High Data Rate Parity Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) + +#define I3C_MERRWARN_HCRC_MASK (0x400U) +#define I3C_MERRWARN_HCRC_SHIFT (10U) +/*! HCRC - High Data Rate CRC Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) + +#define I3C_MERRWARN_OREAD_MASK (0x10000U) +#define I3C_MERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Overread Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) + +#define I3C_MERRWARN_OWRITE_MASK (0x20000U) +#define I3C_MERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Overwrite Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) + +#define I3C_MERRWARN_MSGERR_MASK (0x40000U) +#define I3C_MERRWARN_MSGERR_SHIFT (18U) +/*! MSGERR - Message Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) + +#define I3C_MERRWARN_INVREQ_MASK (0x80000U) +#define I3C_MERRWARN_INVREQ_SHIFT (19U) +/*! INVREQ - Invalid Request Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) + +#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) +#define I3C_MERRWARN_TIMEOUT_SHIFT (20U) +/*! TIMEOUT - Timeout Error Flag + * 0b0..No effect + * 0b0..No error + * 0b1..Clear the flag + * 0b1..Error + */ +#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) +/*! @} */ + +/*! @name MDMACTRL - Controller DMA Control */ +/*! @{ */ + +#define I3C_MDMACTRL_DMAFB_MASK (0x3U) +#define I3C_MDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA from Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) + +#define I3C_MDMACTRL_DMATB_MASK (0xCU) +#define I3C_MDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA to Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame (ended by DMA or terminated) + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) + +#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - DMA Width + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) + * 0b11.. + */ +#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name MDATACTRL - Controller Data Control */ +/*! @{ */ + +#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) + +#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) + +#define I3C_MDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_MDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Locked + * 0b1..Unlocked + */ +#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) + +#define I3C_MDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_MDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Trigger when 1 less than full or less (default) + */ +#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) + +#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_MDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty (default) + * 0b01..Trigger when 1/4 full or more + * 0b10..Trigger when 1/2 full or more + * 0b11..Trigger when 3/4 full or more + */ +#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) + +#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Transmit Entry Count */ +#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) + +#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Entry Count */ +#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) + +#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_MDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) + +#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name MWDATAB - Controller Write Data Byte */ +/*! @{ */ + +#define I3C_MWDATAB_VALUE_MASK (0xFFU) +#define I3C_MWDATAB_VALUE_SHIFT (0U) +/*! VALUE - Data Byte */ +#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) + +#define I3C_MWDATAB_END_MASK (0x100U) +#define I3C_MWDATAB_END_SHIFT (8U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) + +#define I3C_MWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_MWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End of Message ALSO + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name MWDATABE - Controller Write Data Byte End */ +/*! @{ */ + +#define I3C_MWDATABE_VALUE_MASK (0xFFU) +#define I3C_MWDATABE_VALUE_SHIFT (0U) +/*! VALUE - Data */ +#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH - Controller Write Data Halfword */ +/*! @{ */ + +#define I3C_MWDATAH_DATA0_MASK (0xFFU) +#define I3C_MWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) + +#define I3C_MWDATAH_DATA1_MASK (0xFF00U) +#define I3C_MWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) + +#define I3C_MWDATAH_END_MASK (0x10000U) +#define I3C_MWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) +/*! @} */ + +/*! @name MWDATAHE - Controller Write Data Halfword End */ +/*! @{ */ + +#define I3C_MWDATAHE_DATA0_MASK (0xFFU) +#define I3C_MWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) + +#define I3C_MWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_MWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name MRDATAB - Controller Read Data Byte */ +/*! @{ */ + +#define I3C_MRDATAB_VALUE_MASK (0xFFU) +#define I3C_MRDATAB_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) +/*! @} */ + +/*! @name MRDATAH - Controller Read Data Halfword */ +/*! @{ */ + +#define I3C_MRDATAH_LSB_MASK (0xFFU) +#define I3C_MRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) + +#define I3C_MRDATAH_MSB_MASK (0xFF00U) +#define I3C_MRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) +/*! @} */ + +/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAB1_VALUE_MASK (0xFFU) +#define I3C_MWDATAB1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH1 - Controller Write Halfword Data (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAH1_VALUE_MASK (0xFFFFU) +#define I3C_MWDATAH1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAH1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) +#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) +#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) +/*! ADDR - Address */ +#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) +#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) +/*! END - End of SDR Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) + +#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) +#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) +/*! I2C - I2C + * 0b0..I3C message + * 0b1..I2C message + */ +#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) + +#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) +#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) +/*! LEN - Length */ +#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_SDR - Controller Read Message in SDR mode */ +/*! @{ */ + +#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_SDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U) +/*! ADDRCMD - Address Command */ +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) +#define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U) +/*! LEN - Length of Message */ +#define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK) + +#define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) +#define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */ +/*! @{ */ + +#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_DDR - Controller Read Message in DDR mode */ +/*! @{ */ + +#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_DDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) +/*! @} */ + +/*! @name MDYNADDR - Controller Dynamic Address */ +/*! @{ */ + +#define I3C_MDYNADDR_DAVALID_MASK (0x1U) +#define I3C_MDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b0..No valid DA assigned + * 0b1..Valid DA assigned + */ +#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) + +#define I3C_MDYNADDR_DADDR_MASK (0xFEU) +#define I3C_MDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) +/*! @} */ + +/*! @name SMAPCTRL0 - Map Feature Control 0 */ +/*! @{ */ + +#define I3C_SMAPCTRL0_ENA_MASK (0x1U) +#define I3C_SMAPCTRL0_ENA_SHIFT (0U) +/*! ENA - Enable Primary Dynamic Address + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) + +#define I3C_SMAPCTRL0_DA_MASK (0xFEU) +#define I3C_SMAPCTRL0_DA_SHIFT (1U) +/*! DA - Dynamic Address */ +#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) + +#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) +#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) +/*! CAUSE - Cause + * 0b000..No information (this value occurs when not configured to write DA) + * 0b001..Set using ENTDAA + * 0b010..Set using SETDASA, SETAASA, or SETNEWDA + * 0b011..Cleared using RSTDAA + * 0b100..Auto MAP change happened last + */ +#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) +/*! @} */ + +/*! @name IBIEXT1 - Extended IBI Data 1 */ +/*! @{ */ + +#define I3C_IBIEXT1_CNT_MASK (0x7U) +#define I3C_IBIEXT1_CNT_SHIFT (0U) +/*! CNT - Count */ +#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) + +#define I3C_IBIEXT1_MAX_MASK (0x70U) +#define I3C_IBIEXT1_MAX_SHIFT (4U) +/*! MAX - Maximum */ +#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) + +#define I3C_IBIEXT1_EXT1_MASK (0xFF00U) +#define I3C_IBIEXT1_EXT1_SHIFT (8U) +/*! EXT1 - Extra Byte 1 */ +#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) + +#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) +#define I3C_IBIEXT1_EXT2_SHIFT (16U) +/*! EXT2 - Extra Byte 2 */ +#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) + +#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) +#define I3C_IBIEXT1_EXT3_SHIFT (24U) +/*! EXT3 - Extra Byte 3 */ +#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) +/*! @} */ + +/*! @name IBIEXT2 - Extended IBI Data 2 */ +/*! @{ */ + +#define I3C_IBIEXT2_EXT4_MASK (0xFFU) +#define I3C_IBIEXT2_EXT4_SHIFT (0U) +/*! EXT4 - Extra Byte 4 */ +#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) + +#define I3C_IBIEXT2_EXT5_MASK (0xFF00U) +#define I3C_IBIEXT2_EXT5_SHIFT (8U) +/*! EXT5 - Extra Byte 5 */ +#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) + +#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) +#define I3C_IBIEXT2_EXT6_SHIFT (16U) +/*! EXT6 - Extra Byte 6 */ +#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) + +#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) +#define I3C_IBIEXT2_EXT7_SHIFT (24U) +/*! EXT7 - Extra Byte 7 */ +#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) +/*! @} */ + +/*! @name SID - Target Module ID */ +/*! @{ */ + +#define I3C_SID_ID_MASK (0xFFFFFFFFU) +#define I3C_SID_ID_SHIFT (0U) +/*! ID - ID */ +#define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I3C_Register_Masks */ + + +/*! + * @} + */ /* end of group I3C_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_I3C_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_INPUTMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_INPUTMUX.h new file mode 100644 index 000000000..3b943a6e2 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_INPUTMUX.h @@ -0,0 +1,6279 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for INPUTMUX +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_INPUTMUX.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for INPUTMUX + * + * CMSIS Peripheral Access Layer for INPUTMUX + */ + +#if !defined(PERI_INPUTMUX_H_) +#define PERI_INPUTMUX_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Size of Registers Arrays */ +#define INPUTMUX_CTIMERA_COUNT 4u +#define INPUTMUX_CTIMERB_COUNT 4u +#define INPUTMUX_CTIMERC_COUNT 4u +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_COUNT 8u +#define INPUTMUX_CTIMERD_COUNT 4u +#define INPUTMUX_CTIMERE_COUNT 4u +#define INPUTMUX_AOI1_INPUTM_COUNT 16u +#define INPUTMUX_ADC0_TRIGM_COUNT 4u +#define INPUTMUX_ADC2_TRIGM_COUNT 4u +#define INPUTMUX_ADC1_TRIGM_COUNT 4u +#define INPUTMUX_ADC3_TRIGM_COUNT 4u +#define INPUTMUX_FLEXPWM0_FAULT_COUNT 4u +#define INPUTMUX_FLEXPWM1_FAULT_COUNT 4u +#define INPUTMUX_AOI0_INPUTK_COUNT 16u +#define INPUTMUX_EXT_TRIGN_COUNT 8u +#define INPUTMUX_FLEXIO_TRIGN_COUNT 4u +#define INPUTMUX_TRIGFILP_COUNT 12u + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t CTIMER0CAP[INPUTMUX_CTIMERA_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x20, array step: 0x4 */ + __IO uint32_t TIMER0TRIG; /**< Trigger register for TIMER0, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CTIMER1CAP[INPUTMUX_CTIMERB_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x40, array step: 0x4 */ + __IO uint32_t TIMER1TRIG; /**< Trigger register for TIMER1, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CTIMER2CAP[INPUTMUX_CTIMERC_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x60, array step: 0x4 */ + __IO uint32_t TIMER2TRIG; /**< Trigger register for TIMER2 inputs, offset: 0x70 */ + uint8_t RESERVED_3[44]; + __IO uint32_t SMARTDMA_TRIG[INPUTMUX_SMARTDMA_TRIGGER_INPUTN_COUNT]; /**< SmartDMA Trigger Input Connections, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_4[192]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TAR; /**< Selection for frequency measurement reference clock, offset: 0x184 */ + uint8_t RESERVED_5[24]; + __IO uint32_t CTIMER3CAP[INPUTMUX_CTIMERD_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x1A0, array step: 0x4 */ + __IO uint32_t TIMER3TRIG; /**< Trigger register for TIMER3, offset: 0x1B0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CTIMER4CAP[INPUTMUX_CTIMERE_COUNT]; /**< Capture select register for CTIMER inputs, array offset: 0x1C0, array step: 0x4 */ + __IO uint32_t TIMER4TRIG; /**< Trigger register for TIMER4, offset: 0x1D0 */ + uint8_t RESERVED_7[44]; + __IO uint32_t AOI1_INPUT[INPUTMUX_AOI1_INPUTM_COUNT]; /**< AOI1 trigger input connections 0, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[32]; + __IO uint32_t CMP0_TRIG; /**< CMP0 input connections, offset: 0x260 */ + uint8_t RESERVED_9[28]; + __IO uint32_t ADC0_TRIG[INPUTMUX_ADC0_TRIGM_COUNT]; /**< ADC Trigger input connections, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_10[16]; + __IO uint32_t ADC2_TRIG[INPUTMUX_ADC2_TRIGM_COUNT]; /**< ADC Trigger input connections, array offset: 0x2A0, array step: 0x4 */ + uint8_t RESERVED_11[16]; + __IO uint32_t ADC1_TRIG[INPUTMUX_ADC1_TRIGM_COUNT]; /**< ADC Trigger input connections, array offset: 0x2C0, array step: 0x4 */ + uint8_t RESERVED_12[16]; + __IO uint32_t ADC3_TRIG[INPUTMUX_ADC3_TRIGM_COUNT]; /**< ADC Trigger input connections, array offset: 0x2E0, array step: 0x4 */ + uint8_t RESERVED_13[16]; + __IO uint32_t DAC0_TRIG; /**< DAC0 Trigger input connections., offset: 0x300 */ + uint8_t RESERVED_14[92]; + __IO uint32_t QDC0_TRIG; /**< QDC0 Trigger Input Connections, offset: 0x360 */ + __IO uint32_t QDC0_HOME; /**< QDC0 Trigger Input Connections, offset: 0x364 */ + __IO uint32_t QDC0_INDEX; /**< QDC0 Trigger Input Connections, offset: 0x368 */ + __IO uint32_t QDC0_PHASEB; /**< QDC0 Trigger Input Connections, offset: 0x36C */ + __IO uint32_t QDC0_PHASEA; /**< QDC0 Trigger Input Connections, offset: 0x370 */ + __IO uint32_t QDC0_ICAP1; /**< QDC0 Trigger Input Connections, offset: 0x374 */ + __IO uint32_t QDC0_ICAP2; /**< QDC0 Trigger Input Connections, offset: 0x378 */ + __IO uint32_t QDC0_ICAP3; /**< QDC0 Trigger Input Connections, offset: 0x37C */ + __IO uint32_t QDC1_TRIG; /**< QDC1 Trigger Input Connections, offset: 0x380 */ + __IO uint32_t QDC1_HOME; /**< QDC1 Trigger Input Connections, offset: 0x384 */ + __IO uint32_t QDC1_INDEX; /**< QDC1 Trigger Input Connections, offset: 0x388 */ + __IO uint32_t QDC1_PHASEB; /**< QDC1 Trigger Input Connections, offset: 0x38C */ + __IO uint32_t QDC1_PHASEA; /**< QDC1 Trigger Input Connections, offset: 0x390 */ + __IO uint32_t QDC1_ICAP1; /**< QDC1 Trigger Input Connections, offset: 0x394 */ + __IO uint32_t QDC1_ICAP2; /**< QDC1 Trigger Input Connections, offset: 0x398 */ + __IO uint32_t QDC1_ICAP3; /**< QDC1 Trigger Input Connections, offset: 0x39C */ + __IO uint32_t FLEXPWM0_SM0_EXTA0; /**< PWM0 input trigger connections, offset: 0x3A0 */ + __IO uint32_t FLEXPWM0_SM0_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3A4 */ + __IO uint32_t FLEXPWM0_SM1_EXTA; /**< PWM0 input trigger connections, offset: 0x3A8 */ + __IO uint32_t FLEXPWM0_SM1_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3AC */ + __IO uint32_t FLEXPWM0_SM2_EXTA; /**< PWM0 input trigger connections, offset: 0x3B0 */ + __IO uint32_t FLEXPWM0_SM2_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3B4 */ + __IO uint32_t FLEXPWM0_SM3_EXTA0; /**< PWM0 input trigger connections, offset: 0x3B8 */ + __IO uint32_t FLEXPWM0_SM3_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3BC */ + __IO uint32_t FLEXPWM0_FAULT[INPUTMUX_FLEXPWM0_FAULT_COUNT]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C0, array step: 0x4 */ + __IO uint32_t FLEXPWM0_FORCE; /**< PWM0 input trigger connections, offset: 0x3D0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t FLEXPWM1_SM0_EXTA0; /**< PWM1 input trigger connections, offset: 0x3E0 */ + __IO uint32_t FLEXPWM1_SM0_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3E4 */ + __IO uint32_t FLEXPWM1_SM1_EXTA; /**< PWM1 input trigger connections, offset: 0x3E8 */ + __IO uint32_t FLEXPWM1_SM1_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3EC */ + __IO uint32_t FLEXPWM1_SM2_EXTA; /**< PWM1 input trigger connections, offset: 0x3F0 */ + __IO uint32_t FLEXPWM1_SM2_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3F4 */ + __IO uint32_t FLEXPWM1_SM3_EXTA0; /**< PWM1 input trigger connections, offset: 0x3F8 */ + __IO uint32_t FLEXPWM1_SM3_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3FC */ + __IO uint32_t FLEXPWM1_FAULT[INPUTMUX_FLEXPWM1_FAULT_COUNT]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x400, array step: 0x4 */ + __IO uint32_t FLEXPWM1_FORCE; /**< PWM1 input trigger connections, offset: 0x410 */ + uint8_t RESERVED_16[12]; + __IO uint32_t PWM0_EXT_CLK; /**< PWM0 external clock trigger, offset: 0x420 */ + __IO uint32_t PWM1_EXT_CLK; /**< PWM1 external clock trigger, offset: 0x424 */ + uint8_t RESERVED_17[24]; + __IO uint32_t AOI0_INPUT[INPUTMUX_AOI0_INPUTK_COUNT]; /**< AOI0 trigger input connections 0, array offset: 0x440, array step: 0x4 */ + __IO uint32_t USBFS_TRIG; /**< USB-FS trigger input connections, offset: 0x480 */ + uint8_t RESERVED_18[60]; + __IO uint32_t EXT_TRIG[INPUTMUX_EXT_TRIGN_COUNT]; /**< EXT trigger connections, array offset: 0x4C0, array step: 0x4 */ + __IO uint32_t CMP1_TRIG; /**< CMP1 input connections, offset: 0x4E0 */ + uint8_t RESERVED_19[28]; + __IO uint32_t CMP2_TRIG; /**< CMP2 input connections, offset: 0x500 */ + uint8_t RESERVED_20[60]; + __IO uint32_t LPI2C2_TRIG; /**< LPI2C2 trigger input connections, offset: 0x540 */ + uint8_t RESERVED_21[28]; + __IO uint32_t LPI2C3_TRIG; /**< LPI2C3 trigger input connections, offset: 0x560 */ + uint8_t RESERVED_22[60]; + __IO uint32_t LPI2C0_TRIG; /**< LPI2C0 trigger input connections, offset: 0x5A0 */ + uint8_t RESERVED_23[28]; + __IO uint32_t LPI2C1_TRIG; /**< LPI2C1 trigger input connections, offset: 0x5C0 */ + uint8_t RESERVED_24[28]; + __IO uint32_t LPSPI0_TRIG; /**< LPSPI0 trigger input connections, offset: 0x5E0 */ + uint8_t RESERVED_25[28]; + __IO uint32_t LPSPI1_TRIG; /**< LPSPI1 trigger input connections, offset: 0x600 */ + uint8_t RESERVED_26[28]; + __IO uint32_t LPUART0r; /**< LPUART0 trigger input connections, offset: 0x620, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART0' */ + uint8_t RESERVED_27[28]; + __IO uint32_t LPUART1r; /**< LPUART1 trigger input connections, offset: 0x640, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART1' */ + uint8_t RESERVED_28[28]; + __IO uint32_t LPUART2r; /**< LPUART2 trigger input connections, offset: 0x660, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART2' */ + uint8_t RESERVED_29[28]; + __IO uint32_t LPUART3r; /**< LPUART3 trigger input connections, offset: 0x680, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART3' */ + uint8_t RESERVED_30[28]; + __IO uint32_t LPUART4r; /**< LPUART4 trigger input connections, offset: 0x6A0, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART4' */ + uint8_t RESERVED_31[28]; + __IO uint32_t LPUART5r; /**< LPUART5 trigger input connections, offset: 0x6C0, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART5' */ + uint8_t RESERVED_32[28]; + __IO uint32_t FLEXIO_TRIG[INPUTMUX_FLEXIO_TRIGN_COUNT]; /**< FlexIO Trigger Input Connections, array offset: 0x6E0, array step: 0x4 */ + uint8_t RESERVED_33[784]; + __IO uint32_t TRIGFIL_PRSC; /**< Trigger filter prescaller, offset: 0xA00 */ + __I uint32_t TRIGFIL_STAT0; /**< Trigger filter stat, offset: 0xA04 */ + uint8_t RESERVED_34[8]; + __IO uint32_t TRIGFIL[INPUTMUX_TRIGFILP_COUNT]; /**< TRIGFIL control, array offset: 0xA10, array step: 0x4 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name CTIMERA_CTIMER0CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER0 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer1_MAT1 input is selected + * 0b0100010..CTimer1_MAT2 input is selected + * 0b0100011..CTimer1_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + */ +#define INPUTMUX_CTIMERA_CTIMER0CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT)) & INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERA_CTIMER0CAP */ +#define INPUTMUX_CTIMERA_CTIMER0CAP_COUNT (4U) + +/*! @name TIMER0TRIG - Trigger register for TIMER0 */ +/*! @{ */ + +#define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER0 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer1_MAT1 input is selected + * 0b0100010..CTimer1_MAT2 input is selected + * 0b0100011..CTimer1_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + */ +#define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMERB_CTIMER1CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER1 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + */ +#define INPUTMUX_CTIMERB_CTIMER1CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT)) & INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERB_CTIMER1CAP */ +#define INPUTMUX_CTIMERB_CTIMER1CAP_COUNT (4U) + +/*! @name TIMER1TRIG - Trigger register for TIMER1 */ +/*! @{ */ + +#define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER1 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + */ +#define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMERC_CTIMER2CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER2 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + */ +#define INPUTMUX_CTIMERC_CTIMER2CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT)) & INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERC_CTIMER2CAP */ +#define INPUTMUX_CTIMERC_CTIMER2CAP_COUNT (4U) + +/*! @name TIMER2TRIG - Trigger register for TIMER2 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER2 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + */ +#define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK) +/*! @} */ + +/*! @name SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG - SmartDMA Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_SHIFT (0U) +/*! INP - Input number for SmartDMA. + * 0b0000000..Reserved + * 0b0000001..GPIO P0_16 input is selected + * 0b0000010..GPIO P0_17 input is selected + * 0b0000011..GPIO P1_8 input is selected + * 0b0000100..GPIO P1_9 input is selected + * 0b0000101..GPIO P1_10 input is selected + * 0b0000110..GPIO P1_11 input is selected + * 0b0000111..GPIO P1_12 input is selected + * 0b0001000..GPIO P1_13 input is selected + * 0b0001001..GPIO P2_0 input is selected + * 0b0001010..GPIO P2_1 input is selected + * 0b0001011..GPIO P2_2 input is selected + * 0b0001100..GPIO P2_3 input is selected + * 0b0001101..GPIO P2_6 input is selected + * 0b0001110..GPIO P3_8 input is selected + * 0b0001111..GPIO P3_9 input is selected + * 0b0010000..GPIO P3_10 input is selected + * 0b0010001..GPIO P3_11 input is selected + * 0b0010010..GPIO P3_12 input is seclected + * 0b0010011..GPIO0 Pin Event Trig input is selected + * 0b0010100..GPIO1 Pin Event Trig input is selected + * 0b0010101..GPIO2 Pin Event Trig input is selected + * 0b0010110..GPIO3 Pin Event Trig input is selected + * 0b0010111..GPIO4 Pin Event Trig input is selected + * 0b0011000..ARM_TXEV input is selected + * 0b0011001..AOI0_OUT0 input is selected + * 0b0011010..AOI1_OUT1 input is selected + * 0b0011011..DMA_IRQ input is selected + * 0b0011100..MAU_IRQ input is selected + * 0b0011101..WUU_IRQ input is selected + * 0b0011110..CTimer0_MAT2 input is selected + * 0b0011111..CTimer0_MAT3 input is selected + * 0b0100000..CTimer1_MAT2 input is selected + * 0b0100001..CTimer1_MAT3 input is selected + * 0b0100010..CTimer2_MAT2 input is selected + * 0b0100011..CTimer2_MAT3 input is selected + * 0b0100100..CTimer3_MAT2 input is selected + * 0b0100101..CTimer3_MAT3 input is selected + * 0b0100110..CTimer4_MAT2 input is selected + * 0b0100111..CTimer4_MAT3 input is selected + * 0b0101000..OSTIMER_IRQ input is selected + * 0b0101001..PWM0_IRQ input is selected + * 0b0101010..PWM1_IRQ input is selected + * 0b0101011..QDC0_IRQ input is selected + * 0b0101100..QDC1_IRQ input is selected + * 0b0101101..RTC_Alarm_IRQ input is selected + * 0b0101110..RTC_1Hz_IRQ input is selected + * 0b0101111..uTICK_IRQ input is selected + * 0b0110000..WDT_IRQ input is selected + * 0b0110001..Wakeup_Timer_IRQ input is selected + * 0b0110010..CAN0_IRQ input is selected + * 0b0110011..CAN1_IRQ input is selected + * 0b0110100..FlexIO_IRQ input is selected + * 0b0110101..FlexIO_Shifer0_DMA_Req input is selected + * 0b0110110..FlexIO_Shifer1_DMA_Req input is selected + * 0b0110111..FlexIO_Shifer2_DMA_Req input is selected + * 0b0111000..FlexIO_Shifer3_DMA_Req input is selected + * 0b0111001..I3C0_IRQ input is selected + * 0b0111010..LPI2C0_IRQ input is selected + * 0b0111011..LPI2C1_IRQ input is selected + * 0b0111100..LPSPI0_IRQ input is selected + * 0b0111101..LPSPI1_IRQ input is selected + * 0b0111110..LPUART0_IRQ input is selected + * 0b0111111..LPUART1_IRQ input is selected + * 0b1000000..LPUART2_IRQ input is selected + * 0b1000001..LPUART3_IRQ input is selected + * 0b1000010..USB0_SOF input is selected + * 0b1000011..Reserved + * 0b1000100..ADC0_IRQ input is selected + * 0b1000101..ADC1_IRQ input is selected + * 0b1000110..ADC2_IRQ input is selected + * 0b1000111..ADC3_IRQ input is selected + * 0b1001000..CMP0_IRQ input is selected + * 0b1001001..CMP1_IRQ input is selected + * 0b1001010..CMP2_IRQ input is selected + * 0b1001011..CMP0_OUT input is selected + * 0b1001100..CMP1_OUT input is selected + * 0b1001101..CMP2_OUT input is selected + * 0b1001110..DAC0_IRQ input is selected + * 0b1001111..SLCD_IRQ input is selected + */ +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_SHIFT)) & INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG */ +#define INPUTMUX_SMARTDMA_TRIGGER_INPUTN_SMARTDMA_TRIG_COUNT (8U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_INP_MASK (0x7FU) +#define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b0000000..Reserved + * 0b0000001..clk_in input is selected + * 0b0000010..FRO_OSC_12M input is selected + * 0b0000011..fro_hf_div input is selected + * 0b0000100..Reserved + * 0b0000101..clk_16k[1] input is selected + * 0b0000110..SLOW_CLK input is selected + * 0b0000111..FREQME_CLK_IN0 input is selected + * 0b0001000..FREQME_CLK_IN1 input is selected input is selected + * 0b0001001..AOI0_OUT0 input is selected + * 0b0001010..AOI0_OUT1 + * 0b0001011..PWM0_SM0_MUX_TRIG0 + * 0b0001100..PWM0_SM0_MUX_TRIG1 + * 0b0001101..PWM0_SM1_MUX_TRIG0 + * 0b0001110..PWM0_SM1_MUX_TRIG1 + * 0b0001111..PWM0_SM2_MUX_TRIG0 + * 0b0010000..PWM0_SM2_MUX_TRIG1 + * 0b0010001..PWM0_SM3_MUX_TRIG0 + * 0b0010010..PWM0_SM3_MUX_TRIG1 + * 0b0010011..Reserved + * 0b0010100..Reserved + * 0b0010101..Reserved + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..Reserved + * 0b0011001..Reserved + * 0b0011010..Reserved + * 0b0011011..Reserved + * 0b0011100..Reserved + * 0b0011101..Reserved + * 0b0011110..Reserved + * 0b0011111..Reserved + * 0b0100000..AOI1_OUT0 input is selected + * 0b0100001..AOI1_OUT1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0100101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0100111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b0101001..PWM1_SM3_MUX_TRIG1 input is selected + * 0b0111111..Reserved(NO Clock) + */ +#define INPUTMUX_FREQMEAS_REF_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_TAR - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TAR_INP_MASK (0x7FU) +#define INPUTMUX_FREQMEAS_TAR_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b0000000..Reserved + * 0b0000001..clk_in input is selected + * 0b0000010..FRO_OSC_12M input is selected + * 0b0000011..fro_hf_div input is selected + * 0b0000100..Reserved + * 0b0000101..clk_16k[1] input is selected + * 0b0000110..SLOW_CLK input is selected + * 0b0000111..FREQME_CLK_IN0 input is selected + * 0b0001000..FREQME_CLK_IN1 input is selected input is selected + * 0b0001001..AOI0_OUT0 input is selected + * 0b0001010..AOI0_OUT1 + * 0b0001011..PWM0_SM0_MUX_TRIG0 + * 0b0001100..PWM0_SM0_MUX_TRIG1 + * 0b0001101..PWM0_SM1_MUX_TRIG0 + * 0b0001110..PWM0_SM1_MUX_TRIG1 + * 0b0001111..PWM0_SM2_MUX_TRIG0 + * 0b0010000..PWM0_SM2_MUX_TRIG1 + * 0b0010001..PWM0_SM3_MUX_TRIG0 + * 0b0010010..PWM0_SM3_MUX_TRIG1 + * 0b0010011..Reserved + * 0b0010100..Reserved + * 0b0010101..Reserved + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..Reserved + * 0b0011001..Reserved + * 0b0011010..Reserved + * 0b0011011..Reserved + * 0b0011100..Reserved + * 0b0011101..Reserved + * 0b0011110..Reserved + * 0b0011111..Reserved + * 0b0100000..AOI1_OUT0 input is selected + * 0b0100001..AOI1_OUT1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0100101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0100111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b0101001..PWM1_SM3_MUX_TRIG1 input is selected + * 0b0111111..Reserved(NO Clock) + */ +#define INPUTMUX_FREQMEAS_TAR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK) +/*! @} */ + +/*! @name CTIMERD_CTIMER3CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERD_CTIMER3CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERD_CTIMER3CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER3 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer2_MAT1 input is selected + * 0b1010000..CTimer2_MAT2 input is selected + * 0b1010001..CTimer2_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + * 0b1110001..TRIG_IN0 input is selected + * 0b1110010..TRIG_IN1 input is selected + * 0b1110011..TRIG_IN2 input is selected + * 0b1110100..TRIG_IN3 input is selected + * 0b1110101..TRIG_IN4 input is selected + * 0b1110110..TRIG_IN5 input is selected + * 0b1110111..TRIG_IN6 input is selected + * 0b1111000..TRIG_IN7 input is selected + * 0b1111001..TRIG_IN8 input is selected + * 0b1111010..TRIG_IN9 input is selected + * 0b1111011..TRIG_IN10 input is selected + * 0b1111100..TRIG_IN11 input is selected + */ +#define INPUTMUX_CTIMERD_CTIMER3CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERD_CTIMER3CAP_INP_SHIFT)) & INPUTMUX_CTIMERD_CTIMER3CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERD_CTIMER3CAP */ +#define INPUTMUX_CTIMERD_CTIMER3CAP_COUNT (4U) + +/*! @name TIMER3TRIG - Trigger register for TIMER3 */ +/*! @{ */ + +#define INPUTMUX_TIMER3TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER3TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER3 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer2_MAT1 input is selected + * 0b1010000..CTimer2_MAT2 input is selected + * 0b1010001..CTimer2_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + * 0b1110001..TRIG_IN0 input is selected + * 0b1110010..TRIG_IN1 input is selected + * 0b1110011..TRIG_IN2 input is selected + * 0b1110100..TRIG_IN3 input is selected + * 0b1110101..TRIG_IN4 input is selected + * 0b1110110..TRIG_IN5 input is selected + * 0b1110111..TRIG_IN6 input is selected + * 0b1111000..TRIG_IN7 input is selected + * 0b1111001..TRIG_IN8 input is selected + * 0b1111010..TRIG_IN9 input is selected + * 0b1111011..TRIG_IN10 input is selected + * 0b1111100..TRIG_IN11 input is selected + */ +#define INPUTMUX_TIMER3TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_INP_SHIFT)) & INPUTMUX_TIMER3TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMERE_CTIMER4CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERE_CTIMER4CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERE_CTIMER4CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER4 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer2_MAT1 input is selected + * 0b1010000..CTimer2_MAT2 input is selected + * 0b1010001..CTimer2_MAT3 input is selected + * 0b1010010..CTimer3_MAT1 input is selected + * 0b1010011..CTimer3_MAT2 input is selected + * 0b1010100..CTimer3_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + * 0b1110001..TRIG_IN0 input is selected + * 0b1110010..TRIG_IN1 input is selected + * 0b1110011..TRIG_IN2 input is selected + * 0b1110100..TRIG_IN3 input is selected + * 0b1110101..TRIG_IN4 input is selected + * 0b1110110..TRIG_IN5 input is selected + * 0b1110111..TRIG_IN6 input is selected + * 0b1111000..TRIG_IN7 input is selected + * 0b1111001..TRIG_IN8 input is selected + * 0b1111010..TRIG_IN9 input is selected + * 0b1111011..TRIG_IN10 input is selected + * 0b1111100..TRIG_IN11 input is selected + */ +#define INPUTMUX_CTIMERE_CTIMER4CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERE_CTIMER4CAP_INP_SHIFT)) & INPUTMUX_CTIMERE_CTIMER4CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERE_CTIMER4CAP */ +#define INPUTMUX_CTIMERE_CTIMER4CAP_COUNT (4U) + +/*! @name TIMER4TRIG - Trigger register for TIMER4 */ +/*! @{ */ + +#define INPUTMUX_TIMER4TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER4TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER4 + * 0b0000000..Reserved + * 0b0000001..CT_INP0 input is selected + * 0b0000010..CT_INP1 input is selected + * 0b0000011..CT_INP2 input is selected + * 0b0000100..CT_INP3 input is selected + * 0b0000101..CT_INP4 input is selected + * 0b0000110..CT_INP5 input is selected + * 0b0000111..CT_INP6 input is selected + * 0b0001000..CT_INP7 input is selected + * 0b0001001..CT_INP8 input is selected + * 0b0001010..CT_INP9 input is selected + * 0b0001011..CT_INP10 input is selected + * 0b0001100..CT_INP11 input is selected + * 0b0001101..CT_INP12 input is selected + * 0b0001110..CT_INP13 input is selected + * 0b0001111..CT_INP14 input is selected + * 0b0010000..CT_INP15 input is selected + * 0b0010001..CT_INP16 input is selected + * 0b0010010..CT_INP17 input is selected + * 0b0010011..CT_INP18 input is selected + * 0b0010100..CT_INP19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..CMP2_OUT is selected + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer2_MAT1 input is selected + * 0b1010000..CTimer2_MAT2 input is selected + * 0b1010001..CTimer2_MAT3 input is selected + * 0b1010010..CTimer3_MAT1 input is selected + * 0b1010011..CTimer3_MAT2 input is selected + * 0b1010100..CTimer3_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * 0b1100010..LPUART5 Received Data Word input is selected + * 0b1100011..LPUART5 Transmitted Data Word input is selected + * 0b1100100..LPUART5 Receive Line Idle input is selected + * 0b1100101..Reserved + * 0b1100110..Reserved + * 0b1100111..Reserved + * 0b1101000..Reserved + * 0b1101001..ADC2_tcomp[0] input is selected + * 0b1101010..ADC2_tcomp[1] input is selected + * 0b1101011..ADC2_tcomp[2] input is selected + * 0b1101100..ADC2_tcomp[3] input is selected + * 0b1101101..ADC3_tcomp[0] input is selected + * 0b1101110..ADC3_tcomp[1] input is selected + * 0b1101111..ADC3_tcomp[2] input is selected + * 0b1110000..ADC3_tcomp[3] input is selected + * 0b1110001..TRIG_IN0 input is selected + * 0b1110010..TRIG_IN1 input is selected + * 0b1110011..TRIG_IN2 input is selected + * 0b1110100..TRIG_IN3 input is selected + * 0b1110101..TRIG_IN4 input is selected + * 0b1110110..TRIG_IN5 input is selected + * 0b1110111..TRIG_IN6 input is selected + * 0b1111000..TRIG_IN7 input is selected + * 0b1111001..TRIG_IN8 input is selected + * 0b1111010..TRIG_IN9 input is selected + * 0b1111011..TRIG_IN10 input is selected + * 0b1111100..TRIG_IN11 input is selected + */ +#define INPUTMUX_TIMER4TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_INP_SHIFT)) & INPUTMUX_TIMER4TRIG_INP_MASK) +/*! @} */ + +/*! @name AOI1_INPUTM_AOI1_INPUT - AOI1 trigger input connections 0 */ +/*! @{ */ + +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_MASK (0x7FU) +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_SHIFT (0U) +/*! INP - AOI0 trigger input connections + * 0b0000000..Reserved + * 0b0000001..ADC0_tcomp[0] input is selected + * 0b0000010..ADC0_tcomp[1] input is selected + * 0b0000011..ADC0_tcomp[2] input is selected + * 0b0000100..ADC0_tcomp[3] input is selected + * 0b0000101..CMP0_OUT input is selected + * 0b0000110..CMP1_OUT input is selected + * 0b0000111..CMP2_OUT input is selected + * 0b0001000..CTimer0_MAT0 input is selected + * 0b0001001..CTimer0_MAT1 input is selected + * 0b0001010..CTimer0_MAT2 input is selected + * 0b0001011..CTimer0_MAT3 input is selected + * 0b0001100..CTimer1_MAT0 + * 0b0001101..CTimer1_MAT1 input is selected + * 0b0001110..CTimer1_MAT2 input is selected + * 0b0001111..CTimer1_MAT3 input is selected + * 0b0010000..CTimer2_MAT0 input is selected + * 0b0010001..CTimer2_MAT1 input is selected + * 0b0010010..CTimer2_MAT2 input is selected + * 0b0010011..CTimer2_MAT3 input is selected + * 0b0010100..LPTMR0 input is selected + * 0b0010101..Reserved + * 0b0010110..QDC0_CMP_FLAG0 input is selected + * 0b0010111..QDC0_CMP_FLAG1 input is selected + * 0b0011000..QDC0_CMP_FLAG2 input is selected + * 0b0011001..QDC0_CMP_FLAG3 input is selected + * 0b0011010..QDC0_POS_MATCH0 input is selected + * 0b0011011..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0100010..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100011..TRIG_IN0 input is selected + * 0b0100100..TRIG_IN1 input is selected + * 0b0100101..TRIG_IN2 input is selected + * 0b0100110..TRIG_IN3 input is selected + * 0b0100111..TRIG_IN4 input is selected + * 0b0101000..TRIG_IN5 input is selected + * 0b0101001..TRIG_IN6 input is selected + * 0b0101010..TRIG_IN7 input is selected + * 0b0101011..TRIG_IN8 input is selected + * 0b0101100..TRIG_IN9 input is selected + * 0b0101101..TRIG_IN10 input is selected + * 0b0101110..TRIG_IN11 input is selected + * 0b0101111..GPIO0 Pin Event Trig 0 input is selected + * 0b0110000..GPIO1 Pin Event Trig 0 input is selected + * 0b0110001..GPIO2 Pin Event Trig 0 input is selected + * 0b0110010..GPIO3 Pin Event Trig 0 input is selected + * 0b0110011..GPIO4 Pin Event Trig 0 input is selected + * 0b0110100..ADC1_tcomp[0] input is selected + * 0b0110101..ADC1_tcomp[1] input is selected + * 0b0110110..ADC1_tcomp[2] input is selected + * 0b0110111..ADC1_tcomp[3] input is selected + * 0b0111000..CTimer3_MAT0 input is selected + * 0b0111001..CTimer3_MAT1 input is selected + * 0b0111010..CTimer3_MAT2 input is selected + * 0b0111011..CTimer3_MAT3 input is selected + * 0b0111100..CTimer4_MAT0 input is selected + * 0b0111101..CTimer4_MAT1 input is selected + * 0b0111110..CTimer4_MAT2 input is selected + * 0b0111111..CTimer4_MAT3 input is selected + * 0b1000000..FlexIO CH0 input is selected + * 0b1000001..FlexIO CH1 input is selected + * 0b1000010..FlexIO CH2 input is selected + * 0b1000011..FlexIO CH3 input is selected + * 0b1000100..QDC1_CMP_FLAG0 input is selected + * 0b1000101..QDC1_CMP_FLAG1 input is selected + * 0b1000110..QDC1_CMP_FLAG2 input is selected + * 0b1000111..QDC1_CMP_FLAG3 input is selected + * 0b1001000..QDC1_POS_MATCH0 input is selected + * 0b1001001..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1001010..PWM1_SM0_MUX_TRIG1 input is selected + * 0b1001011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1001100..PWM1_SM1_MUX_TRIG1 input is selected + * 0b1001101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1001110..PWM1_SM2_MUX_TRIG1 input is selected + * 0b1001111..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1010000..PWM1_SM3_MUX_TRIG1 input is selected + * 0b1010001..PWM0_SM0_A_Output + * 0b1010010..PWM0_SM0_B_Output + * 0b1010011..PWM0_SM1_A_Output + * 0b1010100..PWM0_SM1_B_Output + * 0b1010101..PWM0_SM2_A_Output + * 0b1010110..PWM0_SM2_B_Output + * 0b1010111..PWM0_SM3_A_Output + * 0b1011000..PWM0_SM3_B_Output + * 0b1011001..ADC2_tcomp[0] input is selected + * 0b1011010..ADC2_tcomp[1] input is selected + * 0b1011011..ADC2_tcomp[2] input is selected + * 0b1011100..ADC2_tcomp[3] input is selected + * 0b1011101..ADC3_tcomp[0] input is selected + * 0b1011110..ADC3_tcomp[1] input is selected + * 0b1011111..ADC3_tcomp[2] input is selected + * 0b1100000..ADC3_tcomp[3] input is selected + */ +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_SHIFT)) & INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_AOI1_INPUTM_AOI1_INPUT */ +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_COUNT (16U) + +/*! @name CMP0_TRIG - CMP0 input connections */ +/*! @{ */ + +#define INPUTMUX_CMP0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP1_OUT input is selected + * 0b000111..CMP2_OUT input is selected + * 0b001000..CTimer0_MAT0 input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer1_MAT0 + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer2_MAT0 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..LPTMR0 input is selected + * 0b001111..Reserved + * 0b010000..QDC0_POS_MATCH0 + * 0b010001..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010010..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010101..PWM0_SM2_MUX_TRIG0 input is selected + * 0b010110..PWM0_SM2_MUX_TRIG1 input is selected + * 0b010111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011000..PWM0_SM3_MUX_TRIG1 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..CTimer3_MAT0 + * 0b101000..CTimer3_MAT1 + * 0b101001..CTimer4_MAT0 input is selected + * 0b101010..CTimer4_MAT1 input is selected + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..QDC1_POS_MATCH0 input is selected + * 0b110000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + */ +#define INPUTMUX_CMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC0 trigger inputs + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..QDC0_POS_MATCH0 input is selected + * 0b010010..PWM0_SM0_OUT_TRIG0 input is selected + * 0b010011..PWM0_SM0_OUT_TRIG1 input is selected + * 0b010100..PWM0_SM1_OUT_TRIG0 input is selected + * 0b010101..PWM0_SM1_OUT_TRIG1 input is selected + * 0b010110..PWM0_SM2_OUT_TRIG0 input is selected + * 0b010111..PWM0_SM2_OUT_TRIG1 input is selected + * 0b011000..PWM0_SM3_OUT_TRIG0 input is selected + * 0b011001..PWM0_SM3_OUT_TRIG1 input is selected + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..Reserved + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC1_tcomp[0] input is selected + * 0b100110..ADC1_tcomp[1] input is selected + * 0b100111..ADC1_tcomp[2] input is selected + * 0b101000..ADC1_tcomp[3] input is selected + * 0b101001..CTimer3_MAT0 input is selected + * 0b101010..CTimer3_MAT1 input is selected + * 0b101011..CTimer4_MAT0 input is selected + * 0b101100..CTimer4_MAT1 input is selected + * 0b101101..FlexIO CH0 input is selected + * 0b101110..FlexIO CH1 input is selected + * 0b101111..FlexIO CH2 input is selected + * 0b110000..FlexIO CH3 input is selected + * 0b110001..QDC1_POS_MATCH0 input is selected + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT (4U) + +/*! @name ADC2_TRIGM_ADC2_TRIG - ADC Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC2_TRIGM_ADC2_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC2_TRIGM_ADC2_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC2 trigger inputs + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..QDC0_POS_MATCH0 input is selected + * 0b010010..PWM0_SM0_OUT_TRIG0 input is selected + * 0b010011..PWM0_SM0_OUT_TRIG1 input is selected + * 0b010100..PWM0_SM1_OUT_TRIG0 input is selected + * 0b010101..PWM0_SM1_OUT_TRIG1 input is selected + * 0b010110..PWM0_SM2_OUT_TRIG0 input is selected + * 0b010111..PWM0_SM2_OUT_TRIG1 input is selected + * 0b011000..PWM0_SM3_OUT_TRIG0 input is selected + * 0b011001..PWM0_SM3_OUT_TRIG1 input is selected + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..Reserved + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC3_tcomp[0] input is selected + * 0b100110..ADC3_tcomp[1] input is selected + * 0b100111..ADC3_tcomp[2] input is selected + * 0b101000..ADC3_tcomp[3] input is selected + * 0b101001..CTimer3_MAT0 input is selected + * 0b101010..CTimer3_MAT1 input is selected + * 0b101011..CTimer4_MAT0 input is selected + * 0b101100..CTimer4_MAT1 input is selected + * 0b101101..FlexIO CH0 input is selected + * 0b101110..FlexIO CH1 input is selected + * 0b101111..FlexIO CH2 input is selected + * 0b110000..FlexIO CH3 input is selected + * 0b110001..QDC1_POS_MATCH0 input is selected + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_ADC2_TRIGM_ADC2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC2_TRIGM_ADC2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC2_TRIGM_ADC2_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC2_TRIGM_ADC2_TRIG */ +#define INPUTMUX_ADC2_TRIGM_ADC2_TRIG_COUNT (4U) + +/*! @name ADC1_TRIGM_ADC1_TRIG - ADC Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC1 trigger inputs + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..QDC0_POS_MATCH0 input is selected + * 0b010010..PWM0_SM0_OUT_TRIG0 input is selected + * 0b010011..PWM0_SM0_OUT_TRIG1 input is selected + * 0b010100..PWM0_SM1_OUT_TRIG0 input is selected + * 0b010101..PWM0_SM1_OUT_TRIG1 input is selected + * 0b010110..PWM0_SM2_OUT_TRIG0 input is selected + * 0b010111..PWM0_SM2_OUT_TRIG1 input is selected + * 0b011000..PWM0_SM3_OUT_TRIG0 input is selected + * 0b011001..PWM0_SM3_OUT_TRIG1 input is selected + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..Reserved + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC0_tcomp[0] input is selected + * 0b100110..ADC0_tcomp[1] input is selected + * 0b100111..ADC0_tcomp[2] input is selected + * 0b101000..ADC0_tcomp[3] input is selected + * 0b101001..CTimer3_MAT0 input is selected + * 0b101010..CTimer3_MAT1 input is selected + * 0b101011..CTimer4_MAT0 input is selected + * 0b101100..CTimer4_MAT1 input is selected + * 0b101101..FlexIO CH0 input is selected + * 0b101110..FlexIO CH1 input is selected + * 0b101111..FlexIO CH2 input is selected + * 0b110000..FlexIO CH3 input is selected + * 0b110001..QDC1_POS_MATCH0 input is selected + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC1_TRIGM_ADC1_TRIG */ +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_COUNT (4U) + +/*! @name ADC3_TRIGM_ADC3_TRIG - ADC Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC3_TRIGM_ADC3_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC3_TRIGM_ADC3_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC3 trigger inputs + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..QDC0_POS_MATCH0 input is selected + * 0b010010..PWM0_SM0_OUT_TRIG0 input is selected + * 0b010011..PWM0_SM0_OUT_TRIG1 input is selected + * 0b010100..PWM0_SM1_OUT_TRIG0 input is selected + * 0b010101..PWM0_SM1_OUT_TRIG1 input is selected + * 0b010110..PWM0_SM2_OUT_TRIG0 input is selected + * 0b010111..PWM0_SM2_OUT_TRIG1 input is selected + * 0b011000..PWM0_SM3_OUT_TRIG0 input is selected + * 0b011001..PWM0_SM3_OUT_TRIG1 input is selected + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..Reserved + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC2_tcomp[0] input is selected + * 0b100110..ADC2_tcomp[1] input is selected + * 0b100111..ADC2_tcomp[2] input is selected + * 0b101000..ADC2_tcomp[3] input is selected + * 0b101001..CTimer3_MAT0 input is selected + * 0b101010..CTimer3_MAT1 input is selected + * 0b101011..CTimer4_MAT0 input is selected + * 0b101100..CTimer4_MAT1 input is selected + * 0b101101..FlexIO CH0 input is selected + * 0b101110..FlexIO CH1 input is selected + * 0b101111..FlexIO CH2 input is selected + * 0b110000..FlexIO CH3 input is selected + * 0b110001..QDC1_POS_MATCH0 input is selected + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_ADC3_TRIGM_ADC3_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC3_TRIGM_ADC3_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC3_TRIGM_ADC3_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC3_TRIGM_ADC3_TRIG */ +#define INPUTMUX_ADC3_TRIGM_ADC3_TRIG_COUNT (4U) + +/*! @name DAC0_TRIG - DAC0 Trigger input connections. */ +/*! @{ */ + +#define INPUTMUX_DAC0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - DAC0 trigger input + * 0b000000..Reserved + * 0b000001..ARM_TXEV + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..Reserved + * 0b010010..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010011..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010101..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010110..Reserved + * 0b010111..Reserved + * 0b011000..Reserved + * 0b011001..Reserved + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..WUU input is selected + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC0_tcomp[0] input is selected + * 0b100110..ADC0_tcomp[1] input is selected + * 0b100111..ADC1_tcomp[0] input is selected + * 0b101000..ADC1_tcomp[1] input is selected + * 0b101001..CTimer3_MAT0 input is selected + * 0b101010..CTimer3_MAT1 input is selected + * 0b101011..CTimer4_MAT0 input is selected + * 0b101100..CTimer4_MAT1 input is selected + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..Reserved + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..Reserved + * 0b111010..ADC2_tcomp[0] input is selected + * 0b111011..ADC2_tcomp[1] input is selected + * 0b111100..ADC3_tcomp[0] input is selected + * 0b111101..ADC3_tcomp[1] input is selected + */ +#define INPUTMUX_DAC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name QDC0_TRIG - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_TRIG_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_TRIG_INP_SHIFT)) & INPUTMUX_QDC0_TRIG_INP_MASK) +/*! @} */ + +/*! @name QDC0_HOME - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_HOME_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_HOME_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_HOME_INP_SHIFT)) & INPUTMUX_QDC0_HOME_INP_MASK) +/*! @} */ + +/*! @name QDC0_INDEX - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_INDEX_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_INDEX_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_INDEX_INP_SHIFT)) & INPUTMUX_QDC0_INDEX_INP_MASK) +/*! @} */ + +/*! @name QDC0_PHASEB - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_PHASEB_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_PHASEB_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEB_INP_SHIFT)) & INPUTMUX_QDC0_PHASEB_INP_MASK) +/*! @} */ + +/*! @name QDC0_PHASEA - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_PHASEA_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_PHASEA_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEA_INP_SHIFT)) & INPUTMUX_QDC0_PHASEA_INP_MASK) +/*! @} */ + +/*! @name QDC0_ICAP1 - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_ICAP1_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_ICAP1_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_ICAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP1_INP_SHIFT)) & INPUTMUX_QDC0_ICAP1_INP_MASK) +/*! @} */ + +/*! @name QDC0_ICAP2 - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_ICAP2_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_ICAP2_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_ICAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP2_INP_SHIFT)) & INPUTMUX_QDC0_ICAP2_INP_MASK) +/*! @} */ + +/*! @name QDC0_ICAP3 - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_ICAP3_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_ICAP3_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC0_ICAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP3_INP_SHIFT)) & INPUTMUX_QDC0_ICAP3_INP_MASK) +/*! @} */ + +/*! @name QDC1_TRIG - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_TRIG_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_TRIG_INP_SHIFT)) & INPUTMUX_QDC1_TRIG_INP_MASK) +/*! @} */ + +/*! @name QDC1_HOME - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_HOME_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_HOME_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_HOME_INP_SHIFT)) & INPUTMUX_QDC1_HOME_INP_MASK) +/*! @} */ + +/*! @name QDC1_INDEX - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_INDEX_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_INDEX_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..>CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_INDEX_INP_SHIFT)) & INPUTMUX_QDC1_INDEX_INP_MASK) +/*! @} */ + +/*! @name QDC1_PHASEB - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_PHASEB_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_PHASEB_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 inout is selected + */ +#define INPUTMUX_QDC1_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_PHASEB_INP_SHIFT)) & INPUTMUX_QDC1_PHASEB_INP_MASK) +/*! @} */ + +/*! @name QDC1_PHASEA - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_PHASEA_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_PHASEA_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_PHASEA_INP_SHIFT)) & INPUTMUX_QDC1_PHASEA_INP_MASK) +/*! @} */ + +/*! @name QDC1_ICAP1 - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_ICAP1_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_ICAP1_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_ICAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP1_INP_SHIFT)) & INPUTMUX_QDC1_ICAP1_INP_MASK) +/*! @} */ + +/*! @name QDC1_ICAP2 - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_ICAP2_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_ICAP2_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_ICAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP2_INP_SHIFT)) & INPUTMUX_QDC1_ICAP2_INP_MASK) +/*! @} */ + +/*! @name QDC1_ICAP3 - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_ICAP3_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_ICAP3_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..CMP2_OUT input is selected + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1000101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_QDC1_ICAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP3_INP_SHIFT)) & INPUTMUX_QDC1_ICAP3_INP_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM0_EXTA0 - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM0_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM1_EXTA - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM1_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM2_EXTA - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM2_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM3_EXTA0 - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM3_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM3_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM3_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_FAULT - PWM0 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FAULT_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_FORCE - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM1_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM0_EXTA0 - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM0_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM1_EXTA - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM1_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM2_EXTA - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM2_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM3_EXTA0 - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM3_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM3_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM3_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_FAULT - PWM1 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM1 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_FORCE - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM1 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..PWM0_SM3_MUX_TRIG0 input is selected + * 0b111101..PWM0_SM3_MUX_TRIG1 input is selected + */ +#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM0_EXT_CLK - PWM0 external clock trigger */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0xFU) +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM + * 0b0000..Reserved + * 0b0001..clk_16k[1] input is selected + * 0b0010..clk_in input is selected + * 0b0011..AOI0_OUT0 input is selected + * 0b0100..AOI0_OUT1 input is selected + * 0b0101..EXTTRIG_IN0 input is selected + * 0b0110..EXTTRIG_IN7 input is selected + * 0b0111..AOI1_OUT0 input is selected + * 0b1000..AOI1_OUT1 input is selected + */ +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM1_EXT_CLK - PWM1 external clock trigger */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK (0xFU) +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM + * 0b0000..Reserved + * 0b0001..clk_16k[1] input is selected + * 0b0010..clk_in input is selected + * 0b0011..AOI0_OUT0 input is selected + * 0b0100..AOI0_OUT1 input is selected + * 0b0101..EXTTRIG_IN0 input is selected + * 0b0110..EXTTRIG_IN7 input is selected + * 0b0111..AOI1_OUT0 input is selected + * 0b1000..AOI1_OUT1 input is selected + */ +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name AOI0_INPUTK_AOI0_INPUT - AOI0 trigger input connections 0 */ +/*! @{ */ + +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_MASK (0x7FU) +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_SHIFT (0U) +/*! INP - AOI0 trigger input connections + * 0b0000000..Reserved + * 0b0000001..ADC0_tcomp[0] input is selected + * 0b0000010..ADC0_tcomp[1] input is selected + * 0b0000011..ADC0_tcomp[2] input is selected + * 0b0000100..ADC0_tcomp[3] input is selected + * 0b0000101..CMP0_OUT input is selected + * 0b0000110..CMP1_OUT input is selected + * 0b0000111..CMP2_OUT input is selected + * 0b0001000..CTimer0_MAT0 input is selected + * 0b0001001..CTimer0_MAT1 input is selected + * 0b0001010..CTimer0_MAT2 input is selected + * 0b0001011..CTimer0_MAT3 input is selected + * 0b0001100..CTimer1_MAT0 input is selected + * 0b0001101..CTimer1_MAT1 input is selected + * 0b0001110..CTimer1_MAT2 input is selected + * 0b0001111..CTimer1_MAT3 input is selected + * 0b0010000..CTimer2_MAT0 input is selected + * 0b0010001..CTimer2_MAT1 input is selected + * 0b0010010..CTimer2_MAT2 input is selected + * 0b0010011..CTimer2_MAT3 input is selected + * 0b0010100..LPTMR0 input is selected + * 0b0010101..Reserved + * 0b0010110..QDC0_CMP_FLAG0 input is selected + * 0b0010111..QDC0_CMP_FLAG1 input is selected + * 0b0011000..QDC0_CMP_FLAG2 input is selected + * 0b0011001..QDC0_CMP_FLAG3 input is selected + * 0b0011010..QDC0_POS_MATCH0 input is selected + * 0b0011011..PWM0_SM0_MUX_TRIG0 0 input is selected + * 0b0011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0100010..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100011..TRIG_IN0 input is selected + * 0b0100100..TRIG_IN1 input is selected + * 0b0100101..TRIG_IN2 input is selected + * 0b0100110..TRIG_IN3 input is selected + * 0b0100111..TRIG_IN4 input is selected + * 0b0101000..TRIG_IN5 input is selected + * 0b0101001..TRIG_IN6 input is selected + * 0b0101010..TRIG_IN7 input is selected + * 0b0101011..TRIG_IN8 input is selected + * 0b0101100..TRIG_IN9 input is selected + * 0b0101101..TRIG_IN10 input is selected + * 0b0101110..TRIG_IN11 input is selected + * 0b0101111..GPIO0 Pin Event Trig 0 input is selected + * 0b0110000..GPIO1 Pin Event Trig 0 input is selected + * 0b0110001..GPIO2 Pin Event Trig 0 input is selected + * 0b0110010..GPIO3 Pin Event Trig 0 input is selected + * 0b0110011..GPIO4 Pin Event Trig 0 input is selected + * 0b0110100..ADC1_tcomp[0] input is selected + * 0b0110101..ADC1_tcomp[1] input is selected + * 0b0110110..ADC1_tcomp[2] input is selected + * 0b0110111..ADC1_tcomp[3] input is selected + * 0b0111000..CTimer3_MAT0 input is selected + * 0b0111001..CTimer3_MAT1 input is selected + * 0b0111010..CTimer3_MAT2 input is selected + * 0b0111011..CTimer3_MAT3 input is selected + * 0b0111100..CTimer4_MAT0 input is selected + * 0b0111101..CTimer4_MAT1 input is selected + * 0b0111110..CTimer4_MAT2 input is selected + * 0b0111111..CTimer4_MAT3 input is selected + * 0b1000000..FlexIO CH0 input is selected + * 0b1000001..FlexIO CH1 input is selected + * 0b1000010..FlexIO CH2 input is selected + * 0b1000011..FlexIO CH3 input is selected + * 0b1000100..QDC1_CMP_FLAG0 input is selected + * 0b1000101..QDC1_CMP_FLAG1 input is selected + * 0b1000110..QDC1_CMP_FLAG2 input is selected + * 0b1000111..QDC1_CMP_FLAG3 input is selected + * 0b1001000..QDC1_POS_MATCH0 input is selected + * 0b1001001..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1001010..PWM1_SM0_MUX_TRIG1 input is selected + * 0b1001011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1001100..PWM1_SM1_MUX_TRIG1 input is selected + * 0b1001101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1001110..PWM1_SM2_MUX_TRIG1 input is selected + * 0b1001111..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1010000..PWM1_SM3_MUX_TRIG1 input is selected + * 0b1010001..PWM0_SM0_A_Output + * 0b1010010..PWM0_SM0_B_Output + * 0b1010011..PWM0_SM1_A_Output + * 0b1010100..PWM0_SM1_B_Output + * 0b1010101..PWM0_SM2_A_Output + * 0b1010110..PWM0_SM2_B_Output + * 0b1010111..PWM0_SM3_A_Output + * 0b1011000..PWM0_SM3_B_Output + * 0b1011001..ADC2_tcomp[0] input is selected + * 0b1011010..ADC2_tcomp[1] input is selected + * 0b1011011..ADC2_tcomp[2] input is selected + * 0b1011100..ADC2_tcomp[3] input is selected + * 0b1011101..ADC3_tcomp[0] input is selected + * 0b1011110..ADC3_tcomp[1] input is selected + * 0b1011111..ADC3_tcomp[2] input is selected + * 0b1100000..ADC3_tcomp[3] input is selected + */ +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_SHIFT)) & INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_AOI0_INPUTK_AOI0_INPUT */ +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_COUNT (16U) + +/*! @name USBFS_TRIG - USB-FS trigger input connections */ +/*! @{ */ + +#define INPUTMUX_USBFS_TRIG_INP_MASK (0xFU) +#define INPUTMUX_USBFS_TRIG_INP_SHIFT (0U) +/*! INP - USB-FS trigger input connections. + * 0b0000..Reserved + * 0b0001..LPUART0 lpuart_trg_txdata input is selected + * 0b0010..LPUART1 lpuart_trg_txdata input is selected + * 0b0011..LPUART2 lpuart_trg_txdata input is selected + * 0b0100..LPUART3 lpuart_trg_txdata input is selected + * 0b0101..LPUART4 lpuart_trg_txdata input is selected + * 0b0110..LPUART5 lpuart_trg_txdata input is selected + */ +#define INPUTMUX_USBFS_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_USBFS_TRIG_INP_SHIFT)) & INPUTMUX_USBFS_TRIG_INP_MASK) +/*! @} */ + +/*! @name EXT_TRIGN_EXT_TRIG - EXT trigger connections */ +/*! @{ */ + +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK (0x1FU) +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT (0U) +/*! INP - EXT trigger input connections + * 0b00000..Reserved + * 0b00001..Reserved + * 0b00010..AOI0_OUT0 input is selected + * 0b00011..AOI0_OUT1 input is selected + * 0b00100..AOI0_OUT2 input is selected + * 0b00101..AOI0_OUT3 input is selected + * 0b00110..CMP0_OUT input is selected + * 0b00111..CMP1_OUT input is selected + * 0b01000..CMP2_OUT input is selected + * 0b01001..LPUART0 ipp_do_lpuart_txd input is selected + * 0b01010..LPUART1 ipp_do_lpuart_txd input is selected + * 0b01011..LPUART2 ipp_do_lpuart_txd input is selected + * 0b01100..LPUART3 ipp_do_lpuart_txd input is selected + * 0b01101..LPUART4 ipp_do_lpuart_txd input is selected + * 0b01110..AOI1_OUT0 input is selected + * 0b01111..AOI1_OUT1 input is selected + * 0b10000..AOI1_OUT2 input is selected + * 0b10001..RTC_1Hz_CLK input is selected + * 0b10010..LPUART5 ipp_do_lpuart_txd input is selected + */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_EXT_TRIGN_EXT_TRIG */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_COUNT (8U) + +/*! @name CMP1_TRIG - CMP1 input connections */ +/*! @{ */ + +#define INPUTMUX_CMP1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP1 input trigger + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP2_OUT input is selected + * 0b001000..CTimer0_MAT0 input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer1_MAT0 + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer2_MAT0 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..LPTMR0 input is selected + * 0b001111..Reserved + * 0b010000..QDC0_POS_MATCH0 + * 0b010001..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010010..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010101..PWM0_SM2_MUX_TRIG0 input is selected + * 0b010110..PWM0_SM2_MUX_TRIG1 input is selected + * 0b010111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011000..PWM0_SM3_MUX_TRIG1 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..CTimer3_MAT0 + * 0b101000..CTimer3_MAT1 + * 0b101001..CTimer4_MAT0 input is selected + * 0b101010..CTimer4_MAT1 input is selected + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..QDC1_POS_MATCH0 input is selected + * 0b110000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + */ +#define INPUTMUX_CMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name CMP2_TRIG - CMP2 input connections */ +/*! @{ */ + +#define INPUTMUX_CMP2_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP2 input trigger + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CTimer0_MAT0 input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer1_MAT0 + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer2_MAT0 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..LPTMR0 input is selected + * 0b001111..Reserved + * 0b010000..QDC0_POS_MATCH0 input is selected + * 0b010001..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010010..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010101..PWM0_SM2_MUX_TRIG0 input is selected + * 0b010110..PWM0_SM2_MUX_TRIG1 input is selected + * 0b010111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011000..PWM0_SM3_MUX_TRIG1 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..CTimer3_MAT0 + * 0b101000..CTimer3_MAT1 + * 0b101001..CTimer4_MAT0 input is selected + * 0b101010..CTimer4_MAT1 input is selected + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..QDC1_POS_MATCH0 input is selected + * 0b110000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + */ +#define INPUTMUX_CMP2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP2_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name LPI2C2_TRIG - LPI2C2 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPI2C2_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPI2C2_TRIG_INP_SHIFT (0U) +/*! INP - LPI2C2 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPI2C2_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C2_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C2_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPI2C3_TRIG - LPI2C3 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPI2C3_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPI2C3_TRIG_INP_SHIFT (0U) +/*! INP - LPI2C3 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPI2C3_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C3_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C3_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPI2C0_TRIG - LPI2C0 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPI2C0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPI2C0_TRIG_INP_SHIFT (0U) +/*! INP - LPI2C0 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPI2C0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C0_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C0_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPI2C1_TRIG - LPI2C1 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPI2C1_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPI2C1_TRIG_INP_SHIFT (0U) +/*! INP - LPI2C1 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPI2C1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C1_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C1_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPSPI0_TRIG - LPSPI0 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPSPI0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPSPI0_TRIG_INP_SHIFT (0U) +/*! INP - LPSPI0 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT1 input is selected + * 0b001010..CTimer0_MAT2 input is selected + * 0b001011..CTimer1_MAT1 input is selected + * 0b001100..CTimer1_MAT2 input is selected + * 0b001101..CTimer2_MAT1 input is selected + * 0b001110..CTimer2_MAT2 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPSPI0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI0_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI0_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPSPI1_TRIG - LPSPI1 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPSPI1_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPSPI1_TRIG_INP_SHIFT (0U) +/*! INP - LPSPI1 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT1 input is selected + * 0b001010..CTimer0_MAT2 input is selected + * 0b001011..CTimer1_MAT1 input is selected + * 0b001100..CTimer1_MAT2 input is selected + * 0b001101..CTimer2_MAT1 input is selected + * 0b001110..CTimer2_MAT2 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPSPI1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI1_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI1_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPUART0 - LPUART0 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART0_INP_MASK (0x3FU) +#define INPUTMUX_LPUART0_INP_SHIFT (0U) +/*! INP - LPUART0 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPUART0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART0_INP_SHIFT)) & INPUTMUX_LPUART0_INP_MASK) +/*! @} */ + +/*! @name LPUART1 - LPUART1 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART1_INP_MASK (0x3FU) +#define INPUTMUX_LPUART1_INP_SHIFT (0U) +/*! INP - LPUART1 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPUART1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART1_INP_SHIFT)) & INPUTMUX_LPUART1_INP_MASK) +/*! @} */ + +/*! @name LPUART2 - LPUART2 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART2_INP_MASK (0x3FU) +#define INPUTMUX_LPUART2_INP_SHIFT (0U) +/*! INP - LPUART2 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPUART2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART2_INP_SHIFT)) & INPUTMUX_LPUART2_INP_MASK) +/*! @} */ + +/*! @name LPUART3 - LPUART3 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART3_INP_MASK (0x3FU) +#define INPUTMUX_LPUART3_INP_SHIFT (0U) +/*! INP - LPUART3 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPUART3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART3_INP_SHIFT)) & INPUTMUX_LPUART3_INP_MASK) +/*! @} */ + +/*! @name LPUART4 - LPUART4 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART4_INP_MASK (0x3FU) +#define INPUTMUX_LPUART4_INP_SHIFT (0U) +/*! INP - LPUART4 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPUART4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART4_INP_SHIFT)) & INPUTMUX_LPUART4_INP_MASK) +/*! @} */ + +/*! @name LPUART5 - LPUART5 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART5_INP_MASK (0x3FU) +#define INPUTMUX_LPUART5_INP_SHIFT (0U) +/*! INP - LPUART5 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..CMP2_OUT input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + */ +#define INPUTMUX_LPUART5_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART5_INP_SHIFT)) & INPUTMUX_LPUART5_INP_MASK) +/*! @} */ + +/*! @name FLEXIO_TRIGN_FLEXIO_TRIG - FlexIO Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT (0U) +/*! INP - Input number for FlexIO0. + * 0b0000000..Reserved + * 0b0000001..AOI0_OUT0 input is selected + * 0b0000010..AOI0_OUT1 input is selected + * 0b0000011..AOI0_OUT2 input is selected + * 0b0000100..AOI0_OUT3 input is selected + * 0b0000101..ADC0_tcomp[0] input is selected + * 0b0000110..ADC0_tcomp[1] input is selected + * 0b0000111..ADC0_tcomp[2] input is selected + * 0b0001000..ADC0_tcomp[3] input is selected + * 0b0001001..CMP0_OUT input is selected + * 0b0001010..CMP1_OUT input is selected + * 0b0001011..CMP2_OUT input is selected + * 0b0001100..CTimer0_MAT1 input is selected + * 0b0001101..CTimer0_MAT2 input is selected + * 0b0001110..CTimer1_MAT1 input is selected + * 0b0001111..CTimer1_MAT2 input is selected + * 0b0010000..CTimer2_MAT1 input is selected + * 0b0010001..CTimer2_MAT2 input is selected + * 0b0010010..LPTMR0 input is selected + * 0b0010011..Reserved + * 0b0010100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010111..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..GPIO0 Pin Event Trig 0 input is selected + * 0b0100001..GPIO1 Pin Event Trig 0 input is selected + * 0b0100010..GPIO2 Pin Event Trig 0 input is selected + * 0b0100011..GPIO3 Pin Event Trig 0 input is selected + * 0b0100100..GPIO4 Pin Event Trig 0 input is selected + * 0b0100101..WUU input is selected + * 0b0100110..LPI2C0 Master End of Packet + * 0b0100111..LPI2C0 Slave End of Packet + * 0b0101000..LPI2C1 Master End of Packet + * 0b0101001..LPI2C1 Slave End of Packet + * 0b0101010..LPSPI0 End of Frame + * 0b0101011..LPSPI0 Received Data Word + * 0b0101100..LPSPI1 End of Frame + * 0b0101101..LPSPI1 Received Data Word + * 0b0101110..LPUART0 Received Data Word + * 0b0101111..LPUART0 Transmitted Data Word + * 0b0110000..LPUART0 Receive Line Idle + * 0b0110001..LPUART1 Received Data Word + * 0b0110010..LPUART1 Transmitted Data Word + * 0b0110011..LPUART1 Receive Line Idle + * 0b0110100..LPUART2 Received Data Word + * 0b0110101..LPUART2 Transmitted Data Word + * 0b0110110..LPUART2 Receive Line Idle + * 0b0110111..LPUART3 Received Data Word + * 0b0111000..LPUART3 Transmitted Data Word + * 0b0111001..LPUART3 Receive Line Idle + * 0b0111010..LPUART4 Received Data Word + * 0b0111011..LPUART4 Transmitted Data Word + * 0b0111100..LPUART4 Receive Line Idle + * 0b0111101..AOI1_OUT0 input is selected + * 0b0111110..AOI1_OUT1 input is selected + * 0b0111111..AOI1_OUT2 input is selected + * 0b1000000..AOI1_OUT3 input is selected + * 0b1000001..ADC1_tcomp[0] input is selected + * 0b1000010..ADC1_tcomp[1] input is selected + * 0b1000011..ADC1_tcomp[2] input is selected + * 0b1000100..ADC1_tcomp[3] input is selected + * 0b1000101..CTimer3_MAT2 input is selected + * 0b1000110..CTimer3_MAT3 input is selected + * 0b1000111..CTimer4_MAT2 input is selected + * 0b1001000..CTimer4_MAT3 input is selected + * 0b1001001..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1001010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1001011..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1001100..PWM1_SM3_MUX_TRIG0 input is selected + * 0b1001101..LPI2C2 Master End of Packet + * 0b1001110..LPI2C2 Slave End of Packet + * 0b1001111..LPI2C3 Master End of Packet + * 0b1010000..LPI2C3 Slave End of Packet + */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_COUNT (4U) + +/*! @name TRIGFIL_PRSC - Trigger filter prescaller */ +/*! @{ */ + +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_MASK (0x3U) +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_SHIFT (0U) +/*! FILT_SCALE_VAL - Filter Prescaller Value + * 0b00..Bypass the clock + * 0b01..Divide 2 + * 0b10..Divide 4 + * 0b11..Divide 8 + */ +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_SHIFT)) & INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_VAL_MASK) + +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_MASK (0x80000000U) +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_SHIFT (31U) +/*! FILT_SCALE_EN - Enable trigger filter prescaller + * 0b0..Disable prescaller + * 0b1..Enabled prescaller + */ +#define INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_SHIFT)) & INPUTMUX_TRIGFIL_PRSC_FILT_SCALE_EN_MASK) +/*! @} */ + +/*! @name TRIGFIL_STAT0 - Trigger filter stat */ +/*! @{ */ + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_MASK (0x1U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_SHIFT (0U) +/*! TRIG_IN0_VAL - TRIG_IN value + * 0b0..TRIG_IN0 is 0 + * 0b1..TRIG_IN0 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN0_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_MASK (0x2U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_SHIFT (1U) +/*! TRIG_IN1_VAL - TRIG_IN value + * 0b0..TRIG_IN1 is 0 + * 0b1..TRIG_IN1 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN1_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_MASK (0x4U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_SHIFT (2U) +/*! TRIG_IN2_VAL - TRIG_IN value + * 0b0..TRIG_IN2 is 0 + * 0b1..TRIG_IN2 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN2_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_MASK (0x8U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_SHIFT (3U) +/*! TRIG_IN3_VAL - TRIG_IN value + * 0b0..TRIG_IN3 is 0 + * 0b1..TRIG_IN3 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN3_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_MASK (0x10U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_SHIFT (4U) +/*! TRIG_IN4_VAL - TRIG_IN value + * 0b0..TRIG_IN4 is 0 + * 0b1..TRIG_IN4 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN4_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_MASK (0x20U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_SHIFT (5U) +/*! TRIG_IN5_VAL - TRIG_IN value + * 0b0..TRIG_IN5 is 0 + * 0b1..TRIG_IN5 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN5_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_MASK (0x40U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_SHIFT (6U) +/*! TRIG_IN6_VAL - TRIG_IN value + * 0b0..TRIG_IN6 is 0 + * 0b1..TRIG_IN6 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN6_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_MASK (0x80U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_SHIFT (7U) +/*! TRIG_IN7_VAL - TRIG_IN value + * 0b0..TRIG_IN7 is 0 + * 0b1..TRIG_IN7 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN7_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_MASK (0x100U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_SHIFT (8U) +/*! TRIG_IN8_VAL - TRIG_IN value + * 0b0..TRIG_IN8 is 0 + * 0b1..TRIG_IN8 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN8_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_MASK (0x200U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_SHIFT (9U) +/*! TRIG_IN9_VAL - TRIG_IN value + * 0b0..TRIG_IN9 is 0 + * 0b1..TRIG_IN9 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN9_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_MASK (0x400U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_SHIFT (10U) +/*! TRIG_IN10_VAL - TRIG_IN value + * 0b0..TRIG_IN10 is 0 + * 0b1..TRIG_IN10 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN10_VAL_MASK) + +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_MASK (0x800U) +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_SHIFT (11U) +/*! TRIG_IN11_VAL - TRIG_IN value + * 0b0..TRIG_IN11 is 0 + * 0b1..TRIG_IN11 is 1 + */ +#define INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_SHIFT)) & INPUTMUX_TRIGFIL_STAT0_TRIG_IN11_VAL_MASK) +/*! @} */ + +/*! @name TRIGFILP_TRIGFIL - TRIGFIL control */ +/*! @{ */ + +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_MASK (0xFFU) +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_SHIFT)) & INPUTMUX_TRIGFILP_TRIGFIL_FILT_PER_MASK) + +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_MASK (0x700U) +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_SHIFT)) & INPUTMUX_TRIGFILP_TRIGFIL_FILT_CNT_MASK) +/*! @} */ + +/* The count of INPUTMUX_TRIGFILP_TRIGFIL */ +#define INPUTMUX_TRIGFILP_TRIGFIL_COUNT (12U) + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_INPUTMUX_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LCD.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LCD.h new file mode 100644 index 000000000..031fa07cd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LCD.h @@ -0,0 +1,1434 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for LCD +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_LCD.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for LCD + * + * CMSIS Peripheral Access Layer for LCD + */ + +#if !defined(PERI_LCD_H_) +#define PERI_LCD_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer + * @{ + */ + +/** LCD - Size of Registers Arrays */ +#define LCD_PEN_COUNT 2u +#define LCD_BPEN_COUNT 2u +#define LCD_WF_ACCESS_WF8BIT_WF8B_COUNT 48u +#define LCD_WF_ACCESS_WF32BIT_WF_COUNT 12u + +/** LCD - Register Layout Typedef */ +typedef struct { + __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */ + __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */ + __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */ + __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */ + __IO uint32_t PEN[LCD_PEN_COUNT]; /**< LCD Pin Enable register 0..LCD Pin Enable register 1, array offset: 0x10, array step: 0x4 */ + __IO uint32_t BPEN[LCD_BPEN_COUNT]; /**< LCD Back Plane Enable register 0..LCD Back Plane Enable register 1, array offset: 0x18, array step: 0x4 */ + union { /* offset: 0x20 */ + __IO uint8_t WF8B[LCD_WF_ACCESS_WF8BIT_WF8B_COUNT]; /**< LCD Waveform 0 Register..LCD Waveform 47 Register, array offset: 0x20, array step: 0x1 */ + __IO uint32_t WF[LCD_WF_ACCESS_WF32BIT_WF_COUNT]; /**< LCD Waveform 3 to 0 Register..LCD Waveform 47 to 44 Register, array offset: 0x20, array step: 0x4 */ + }; +} LCD_Type; + +/* ---------------------------------------------------------------------------- + -- LCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCD_Register_Masks LCD Register Masks + * @{ + */ + +/*! @name GCR - LCD General Control Register */ +/*! @{ */ + +#define LCD_GCR_DUTY_MASK (0x3U) +#define LCD_GCR_DUTY_SHIFT (0U) +/*! DUTY - LCD duty select + * 0b00..Use 1 BP (1/1 duty cycle). + * 0b01..Use 2 BP (1/2 duty cycle). + * 0b10..Use 3 BP (1/3 duty cycle). + * 0b11..Use 4 BP (1/4 duty cycle).(Default) + */ +#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_DUTY_SHIFT)) & LCD_GCR_DUTY_MASK) + +#define LCD_GCR_LCLK_MASK (0x38U) +#define LCD_GCR_LCLK_SHIFT (3U) +/*! LCLK - LCD Clock Prescaler */ +#define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCLK_SHIFT)) & LCD_GCR_LCLK_MASK) + +#define LCD_GCR_LCDLP_MASK (0x40U) +#define LCD_GCR_LCDLP_SHIFT (6U) +/*! LCDLP - LCD Low Power Waveform + * 0b0..LCD driver drives standard waveforms. + * 0b1..LCD driver drives low-power waveforms. + */ +#define LCD_GCR_LCDLP(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDLP_SHIFT)) & LCD_GCR_LCDLP_MASK) + +#define LCD_GCR_LCDEN_MASK (0x80U) +#define LCD_GCR_LCDEN_SHIFT (7U) +/*! LCDEN - LCD Driver Enable */ +#define LCD_GCR_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDEN_SHIFT)) & LCD_GCR_LCDEN_MASK) + +#define LCD_GCR_LCDSTP_MASK (0x100U) +#define LCD_GCR_LCDSTP_SHIFT (8U) +/*! LCDSTP - LCD Stop + * 0b0..Allows the LCD driver to continue running during Stop mode. + * 0b1..Disables the LCD driver when MCU enters Stop mode. + */ +#define LCD_GCR_LCDSTP(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDSTP_SHIFT)) & LCD_GCR_LCDSTP_MASK) + +#define LCD_GCR_LCDDOZE_MASK (0x200U) +#define LCD_GCR_LCDDOZE_SHIFT (9U) +/*! LCDDOZE - LCD Doze enable + * 0b0..Allows the LCD driver to continue running during Doze mode. + * 0b1..Disables the LCD driver when MCU enters Doze mode. + */ +#define LCD_GCR_LCDDOZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDDOZE_SHIFT)) & LCD_GCR_LCDDOZE_MASK) + +#define LCD_GCR_FDCIEN_MASK (0x4000U) +#define LCD_GCR_FDCIEN_SHIFT (14U) +/*! FDCIEN - LCD Fault Detection Complete Interrupt Enable + * 0b0..No interrupt request is generated by this event. + * 0b1..When a fault is detected and FDCF bit is set, this event causes an interrupt request. + */ +#define LCD_GCR_FDCIEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_FDCIEN_SHIFT)) & LCD_GCR_FDCIEN_MASK) + +#define LCD_GCR_LCDIEN_MASK (0x8000U) +#define LCD_GCR_LCDIEN_SHIFT (15U) +/*! LCDIEN - LCD Frame Frequency Interrupt Enable + * 0b0..No interrupt request is generated by this event. + * 0b1..When LCDIF bit is set, this event causes an interrupt request. + */ +#define LCD_GCR_LCDIEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDIEN_SHIFT)) & LCD_GCR_LCDIEN_MASK) + +#define LCD_GCR_SHCYCLE_MASK (0x10000U) +#define LCD_GCR_SHCYCLE_SHIFT (16U) +/*! SHCYCLE - Sample & Hold Cycle Select + * 0b0..Sample & hold phase clock period is 64 LCD clock (16kHz) period / 32 LCD clock (8kHz) period. + * 0b1..Sample & hold phase clock period is 128 LCD clk (16kHz) period / 64 LCD clock (8kHz) period. + */ +#define LCD_GCR_SHCYCLE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_SHCYCLE_SHIFT)) & LCD_GCR_SHCYCLE_MASK) + +#define LCD_GCR_SHEN_MASK (0x800000U) +#define LCD_GCR_SHEN_SHIFT (23U) +/*! SHEN - Sample & Hold Mode Enable + * 0b0..Sample & hold is disabled. + * 0b1..Sample & hold is enabled. + */ +#define LCD_GCR_SHEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_SHEN_SHIFT)) & LCD_GCR_SHEN_MASK) + +#define LCD_GCR_VLL1TRIM_MASK (0xF000000U) +#define LCD_GCR_VLL1TRIM_SHIFT (24U) +/*! VLL1TRIM - Level 1 Voltage Trim */ +#define LCD_GCR_VLL1TRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_VLL1TRIM_SHIFT)) & LCD_GCR_VLL1TRIM_MASK) + +#define LCD_GCR_VLL2TRIM_MASK (0xF0000000U) +#define LCD_GCR_VLL2TRIM_SHIFT (28U) +/*! VLL2TRIM - Level 2 Voltage Trim */ +#define LCD_GCR_VLL2TRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_VLL2TRIM_SHIFT)) & LCD_GCR_VLL2TRIM_MASK) +/*! @} */ + +/*! @name AR - LCD Auxiliary Register */ +/*! @{ */ + +#define LCD_AR_BRATE_MASK (0x7U) +#define LCD_AR_BRATE_SHIFT (0U) +/*! BRATE - Blink-rate configuration */ +#define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BRATE_SHIFT)) & LCD_AR_BRATE_MASK) + +#define LCD_AR_BMODE_MASK (0x8U) +#define LCD_AR_BMODE_SHIFT (3U) +/*! BMODE - Blink mode + * 0b0..Display blank during the blink period. + * 0b1..Display alternate display during blink period. + */ +#define LCD_AR_BMODE(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BMODE_SHIFT)) & LCD_AR_BMODE_MASK) + +#define LCD_AR_BLANK_MASK (0x20U) +#define LCD_AR_BLANK_SHIFT (5U) +/*! BLANK - Blank display mode + * 0b0..Normal or alternate display mode. + * 0b1..Blank display mode. + */ +#define LCD_AR_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLANK_SHIFT)) & LCD_AR_BLANK_MASK) + +#define LCD_AR_ALT_MASK (0x40U) +#define LCD_AR_ALT_SHIFT (6U) +/*! ALT - Alternate display mode + * 0b0..Normal display mode. + * 0b1..Alternate display mode. + */ +#define LCD_AR_ALT(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_ALT_SHIFT)) & LCD_AR_ALT_MASK) + +#define LCD_AR_BLINK_MASK (0x80U) +#define LCD_AR_BLINK_SHIFT (7U) +/*! BLINK - Blink command + * 0b0..Disables blinking. + * 0b1..Starts blinking at blinking frequency specified by LCD blink rate calculation. + */ +#define LCD_AR_BLINK(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLINK_SHIFT)) & LCD_AR_BLINK_MASK) + +#define LCD_AR_LCDIF_MASK (0x8000U) +#define LCD_AR_LCDIF_SHIFT (15U) +/*! LCDIF - LCD Frame Frequency Interrupt flag + * 0b0..Frame frequency interrupt condition has not occurred. + * 0b1..Start of SLCD frame has occurred. + */ +#define LCD_AR_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_LCDIF_SHIFT)) & LCD_AR_LCDIF_MASK) +/*! @} */ + +/*! @name FDCR - LCD Fault Detect Control Register */ +/*! @{ */ + +#define LCD_FDCR_FDPINID_MASK (0x3FU) +#define LCD_FDCR_FDPINID_SHIFT (0U) +/*! FDPINID - Fault Detect Pin ID */ +#define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPINID_SHIFT)) & LCD_FDCR_FDPINID_MASK) + +#define LCD_FDCR_FDBPEN_MASK (0x40U) +#define LCD_FDCR_FDBPEN_SHIFT (6U) +/*! FDBPEN - Fault Detect Back Plane Enable + * 0b0..Type of the selected pin under fault detect test is front plane. + * 0b1..Type of the selected pin under fault detect test is back plane. + */ +#define LCD_FDCR_FDBPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDBPEN_SHIFT)) & LCD_FDCR_FDBPEN_MASK) + +#define LCD_FDCR_FDEN_MASK (0x80U) +#define LCD_FDCR_FDEN_SHIFT (7U) +/*! FDEN - Fault Detect Enable + * 0b0..Disable fault detection. + * 0b1..Enable fault detection. + */ +#define LCD_FDCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDEN_SHIFT)) & LCD_FDCR_FDEN_MASK) + +#define LCD_FDCR_FDSWW_MASK (0xE00U) +#define LCD_FDCR_FDSWW_SHIFT (9U) +/*! FDSWW - Fault Detect Sample Window Width + * 0b000..Sample window width is 4 sample clock cycles. + * 0b001..Sample window width is 8 sample clock cycles. + * 0b010..Sample window width is 16 sample clock cycles. + * 0b011..Sample window width is 32 sample clock cycles. + * 0b100..Sample window width is 64 sample clock cycles. + * 0b101..Sample window width is 128 sample clock cycles. + * 0b110..Sample window width is 256 sample clock cycles. + * 0b111..Sample window width is 512 sample clock cycles. + */ +#define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDSWW_SHIFT)) & LCD_FDCR_FDSWW_MASK) + +#define LCD_FDCR_FDPRS_MASK (0x7000U) +#define LCD_FDCR_FDPRS_SHIFT (12U) +/*! FDPRS - Fault Detect Clock Prescaler + * 0b000..1/1 bus clock. + * 0b001..1/2 bus clock. + * 0b010..1/4 bus clock. + * 0b011..1/8 bus clock. + * 0b100..1/16 bus clock. + * 0b101..1/32 bus clock. + * 0b110..1/64 bus clock. + * 0b111..1/128 bus clock. + */ +#define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPRS_SHIFT)) & LCD_FDCR_FDPRS_MASK) +/*! @} */ + +/*! @name FDSR - LCD Fault Detect Status Register */ +/*! @{ */ + +#define LCD_FDSR_FDCNT_MASK (0xFFU) +#define LCD_FDSR_FDCNT_SHIFT (0U) +/*! FDCNT - Fault Detect Counter */ +#define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCNT_SHIFT)) & LCD_FDSR_FDCNT_MASK) + +#define LCD_FDSR_FDCF_MASK (0x8000U) +#define LCD_FDSR_FDCF_SHIFT (15U) +/*! FDCF - Fault Detection Complete Flag + * 0b0..Fault detection is not completed. + * 0b1..Fault detection is completed. + */ +#define LCD_FDSR_FDCF(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCF_SHIFT)) & LCD_FDSR_FDCF_MASK) +/*! @} */ + +/*! @name PEN - LCD Pin Enable register 0..LCD Pin Enable register 1 */ +/*! @{ */ + +#define LCD_PEN_PIN_0_EN_MASK (0x1U) +#define LCD_PEN_PIN_0_EN_SHIFT (0U) +/*! PIN_0_EN - LCD Pin 0 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_0_EN_SHIFT)) & LCD_PEN_PIN_0_EN_MASK) + +#define LCD_PEN_PIN_32_EN_MASK (0x1U) +#define LCD_PEN_PIN_32_EN_SHIFT (0U) +/*! PIN_32_EN - LCD Pin 32 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_32_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_32_EN_SHIFT)) & LCD_PEN_PIN_32_EN_MASK) + +#define LCD_PEN_PIN_1_EN_MASK (0x2U) +#define LCD_PEN_PIN_1_EN_SHIFT (1U) +/*! PIN_1_EN - LCD Pin 1 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_1_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_1_EN_SHIFT)) & LCD_PEN_PIN_1_EN_MASK) + +#define LCD_PEN_PIN_33_EN_MASK (0x2U) +#define LCD_PEN_PIN_33_EN_SHIFT (1U) +/*! PIN_33_EN - LCD Pin 33 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_33_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_33_EN_SHIFT)) & LCD_PEN_PIN_33_EN_MASK) + +#define LCD_PEN_PIN_2_EN_MASK (0x4U) +#define LCD_PEN_PIN_2_EN_SHIFT (2U) +/*! PIN_2_EN - LCD Pin 2 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_2_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_2_EN_SHIFT)) & LCD_PEN_PIN_2_EN_MASK) + +#define LCD_PEN_PIN_34_EN_MASK (0x4U) +#define LCD_PEN_PIN_34_EN_SHIFT (2U) +/*! PIN_34_EN - LCD Pin 34 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_34_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_34_EN_SHIFT)) & LCD_PEN_PIN_34_EN_MASK) + +#define LCD_PEN_PIN_3_EN_MASK (0x8U) +#define LCD_PEN_PIN_3_EN_SHIFT (3U) +/*! PIN_3_EN - LCD Pin 3 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_3_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_3_EN_SHIFT)) & LCD_PEN_PIN_3_EN_MASK) + +#define LCD_PEN_PIN_35_EN_MASK (0x8U) +#define LCD_PEN_PIN_35_EN_SHIFT (3U) +/*! PIN_35_EN - LCD Pin 35 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_35_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_35_EN_SHIFT)) & LCD_PEN_PIN_35_EN_MASK) + +#define LCD_PEN_PIN_4_EN_MASK (0x10U) +#define LCD_PEN_PIN_4_EN_SHIFT (4U) +/*! PIN_4_EN - LCD Pin 4 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_4_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_4_EN_SHIFT)) & LCD_PEN_PIN_4_EN_MASK) + +#define LCD_PEN_PIN_36_EN_MASK (0x10U) +#define LCD_PEN_PIN_36_EN_SHIFT (4U) +/*! PIN_36_EN - LCD Pin 36 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_36_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_36_EN_SHIFT)) & LCD_PEN_PIN_36_EN_MASK) + +#define LCD_PEN_PIN_5_EN_MASK (0x20U) +#define LCD_PEN_PIN_5_EN_SHIFT (5U) +/*! PIN_5_EN - LCD Pin 5 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_5_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_5_EN_SHIFT)) & LCD_PEN_PIN_5_EN_MASK) + +#define LCD_PEN_PIN_37_EN_MASK (0x20U) +#define LCD_PEN_PIN_37_EN_SHIFT (5U) +/*! PIN_37_EN - LCD Pin 37 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_37_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_37_EN_SHIFT)) & LCD_PEN_PIN_37_EN_MASK) + +#define LCD_PEN_PIN_6_EN_MASK (0x40U) +#define LCD_PEN_PIN_6_EN_SHIFT (6U) +/*! PIN_6_EN - LCD Pin 6 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_6_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_6_EN_SHIFT)) & LCD_PEN_PIN_6_EN_MASK) + +#define LCD_PEN_PIN_38_EN_MASK (0x40U) +#define LCD_PEN_PIN_38_EN_SHIFT (6U) +/*! PIN_38_EN - LCD Pin 38 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_38_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_38_EN_SHIFT)) & LCD_PEN_PIN_38_EN_MASK) + +#define LCD_PEN_PIN_7_EN_MASK (0x80U) +#define LCD_PEN_PIN_7_EN_SHIFT (7U) +/*! PIN_7_EN - LCD Pin 7 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_7_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_7_EN_SHIFT)) & LCD_PEN_PIN_7_EN_MASK) + +#define LCD_PEN_PIN_39_EN_MASK (0x80U) +#define LCD_PEN_PIN_39_EN_SHIFT (7U) +/*! PIN_39_EN - LCD Pin 39 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_39_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_39_EN_SHIFT)) & LCD_PEN_PIN_39_EN_MASK) + +#define LCD_PEN_PIN_8_EN_MASK (0x100U) +#define LCD_PEN_PIN_8_EN_SHIFT (8U) +/*! PIN_8_EN - LCD Pin 8 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_8_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_8_EN_SHIFT)) & LCD_PEN_PIN_8_EN_MASK) + +#define LCD_PEN_PIN_40_EN_MASK (0x100U) +#define LCD_PEN_PIN_40_EN_SHIFT (8U) +/*! PIN_40_EN - LCD Pin 40 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_40_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_40_EN_SHIFT)) & LCD_PEN_PIN_40_EN_MASK) + +#define LCD_PEN_PIN_9_EN_MASK (0x200U) +#define LCD_PEN_PIN_9_EN_SHIFT (9U) +/*! PIN_9_EN - LCD Pin 9 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_9_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_9_EN_SHIFT)) & LCD_PEN_PIN_9_EN_MASK) + +#define LCD_PEN_PIN_41_EN_MASK (0x200U) +#define LCD_PEN_PIN_41_EN_SHIFT (9U) +/*! PIN_41_EN - LCD Pin 41 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_41_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_41_EN_SHIFT)) & LCD_PEN_PIN_41_EN_MASK) + +#define LCD_PEN_PIN_10_EN_MASK (0x400U) +#define LCD_PEN_PIN_10_EN_SHIFT (10U) +/*! PIN_10_EN - LCD Pin 10 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_10_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_10_EN_SHIFT)) & LCD_PEN_PIN_10_EN_MASK) + +#define LCD_PEN_PIN_42_EN_MASK (0x400U) +#define LCD_PEN_PIN_42_EN_SHIFT (10U) +/*! PIN_42_EN - LCD Pin 42 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_42_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_42_EN_SHIFT)) & LCD_PEN_PIN_42_EN_MASK) + +#define LCD_PEN_PIN_11_EN_MASK (0x800U) +#define LCD_PEN_PIN_11_EN_SHIFT (11U) +/*! PIN_11_EN - LCD Pin 11 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_11_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_11_EN_SHIFT)) & LCD_PEN_PIN_11_EN_MASK) + +#define LCD_PEN_PIN_43_EN_MASK (0x800U) +#define LCD_PEN_PIN_43_EN_SHIFT (11U) +/*! PIN_43_EN - LCD Pin 43 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_43_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_43_EN_SHIFT)) & LCD_PEN_PIN_43_EN_MASK) + +#define LCD_PEN_PIN_12_EN_MASK (0x1000U) +#define LCD_PEN_PIN_12_EN_SHIFT (12U) +/*! PIN_12_EN - LCD Pin 12 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_12_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_12_EN_SHIFT)) & LCD_PEN_PIN_12_EN_MASK) + +#define LCD_PEN_PIN_44_EN_MASK (0x1000U) +#define LCD_PEN_PIN_44_EN_SHIFT (12U) +/*! PIN_44_EN - LCD Pin 44 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_44_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_44_EN_SHIFT)) & LCD_PEN_PIN_44_EN_MASK) + +#define LCD_PEN_PIN_13_EN_MASK (0x2000U) +#define LCD_PEN_PIN_13_EN_SHIFT (13U) +/*! PIN_13_EN - LCD Pin 13 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_13_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_13_EN_SHIFT)) & LCD_PEN_PIN_13_EN_MASK) + +#define LCD_PEN_PIN_45_EN_MASK (0x2000U) +#define LCD_PEN_PIN_45_EN_SHIFT (13U) +/*! PIN_45_EN - LCD Pin 45 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_45_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_45_EN_SHIFT)) & LCD_PEN_PIN_45_EN_MASK) + +#define LCD_PEN_PIN_14_EN_MASK (0x4000U) +#define LCD_PEN_PIN_14_EN_SHIFT (14U) +/*! PIN_14_EN - LCD Pin 14 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_14_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_14_EN_SHIFT)) & LCD_PEN_PIN_14_EN_MASK) + +#define LCD_PEN_PIN_46_EN_MASK (0x4000U) +#define LCD_PEN_PIN_46_EN_SHIFT (14U) +/*! PIN_46_EN - LCD Pin 46 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_46_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_46_EN_SHIFT)) & LCD_PEN_PIN_46_EN_MASK) + +#define LCD_PEN_PIN_15_EN_MASK (0x8000U) +#define LCD_PEN_PIN_15_EN_SHIFT (15U) +/*! PIN_15_EN - LCD Pin 15 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_15_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_15_EN_SHIFT)) & LCD_PEN_PIN_15_EN_MASK) + +#define LCD_PEN_PIN_47_EN_MASK (0x8000U) +#define LCD_PEN_PIN_47_EN_SHIFT (15U) +/*! PIN_47_EN - LCD Pin 47 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_47_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_47_EN_SHIFT)) & LCD_PEN_PIN_47_EN_MASK) + +#define LCD_PEN_PIN_16_EN_MASK (0x10000U) +#define LCD_PEN_PIN_16_EN_SHIFT (16U) +/*! PIN_16_EN - LCD Pin 16 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_16_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_16_EN_SHIFT)) & LCD_PEN_PIN_16_EN_MASK) + +#define LCD_PEN_PIN_17_EN_MASK (0x20000U) +#define LCD_PEN_PIN_17_EN_SHIFT (17U) +/*! PIN_17_EN - LCD Pin 17 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_17_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_17_EN_SHIFT)) & LCD_PEN_PIN_17_EN_MASK) + +#define LCD_PEN_PIN_18_EN_MASK (0x40000U) +#define LCD_PEN_PIN_18_EN_SHIFT (18U) +/*! PIN_18_EN - LCD Pin 18 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_18_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_18_EN_SHIFT)) & LCD_PEN_PIN_18_EN_MASK) + +#define LCD_PEN_PIN_19_EN_MASK (0x80000U) +#define LCD_PEN_PIN_19_EN_SHIFT (19U) +/*! PIN_19_EN - LCD Pin 19 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_19_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_19_EN_SHIFT)) & LCD_PEN_PIN_19_EN_MASK) + +#define LCD_PEN_PIN_20_EN_MASK (0x100000U) +#define LCD_PEN_PIN_20_EN_SHIFT (20U) +/*! PIN_20_EN - LCD Pin 20 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_20_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_20_EN_SHIFT)) & LCD_PEN_PIN_20_EN_MASK) + +#define LCD_PEN_PIN_21_EN_MASK (0x200000U) +#define LCD_PEN_PIN_21_EN_SHIFT (21U) +/*! PIN_21_EN - LCD Pin 21 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_21_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_21_EN_SHIFT)) & LCD_PEN_PIN_21_EN_MASK) + +#define LCD_PEN_PIN_22_EN_MASK (0x400000U) +#define LCD_PEN_PIN_22_EN_SHIFT (22U) +/*! PIN_22_EN - LCD Pin 22 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_22_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_22_EN_SHIFT)) & LCD_PEN_PIN_22_EN_MASK) + +#define LCD_PEN_PIN_23_EN_MASK (0x800000U) +#define LCD_PEN_PIN_23_EN_SHIFT (23U) +/*! PIN_23_EN - LCD Pin 23 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_23_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_23_EN_SHIFT)) & LCD_PEN_PIN_23_EN_MASK) + +#define LCD_PEN_PIN_24_EN_MASK (0x1000000U) +#define LCD_PEN_PIN_24_EN_SHIFT (24U) +/*! PIN_24_EN - LCD Pin 24 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_24_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_24_EN_SHIFT)) & LCD_PEN_PIN_24_EN_MASK) + +#define LCD_PEN_PIN_25_EN_MASK (0x2000000U) +#define LCD_PEN_PIN_25_EN_SHIFT (25U) +/*! PIN_25_EN - LCD Pin 25 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_25_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_25_EN_SHIFT)) & LCD_PEN_PIN_25_EN_MASK) + +#define LCD_PEN_PIN_26_EN_MASK (0x4000000U) +#define LCD_PEN_PIN_26_EN_SHIFT (26U) +/*! PIN_26_EN - LCD Pin 26 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_26_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_26_EN_SHIFT)) & LCD_PEN_PIN_26_EN_MASK) + +#define LCD_PEN_PIN_27_EN_MASK (0x8000000U) +#define LCD_PEN_PIN_27_EN_SHIFT (27U) +/*! PIN_27_EN - LCD Pin 27 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_27_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_27_EN_SHIFT)) & LCD_PEN_PIN_27_EN_MASK) + +#define LCD_PEN_PIN_28_EN_MASK (0x10000000U) +#define LCD_PEN_PIN_28_EN_SHIFT (28U) +/*! PIN_28_EN - LCD Pin 28 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_28_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_28_EN_SHIFT)) & LCD_PEN_PIN_28_EN_MASK) + +#define LCD_PEN_PIN_29_EN_MASK (0x20000000U) +#define LCD_PEN_PIN_29_EN_SHIFT (29U) +/*! PIN_29_EN - LCD Pin 29 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_29_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_29_EN_SHIFT)) & LCD_PEN_PIN_29_EN_MASK) + +#define LCD_PEN_PIN_30_EN_MASK (0x40000000U) +#define LCD_PEN_PIN_30_EN_SHIFT (30U) +/*! PIN_30_EN - LCD Pin 30 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_30_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_30_EN_SHIFT)) & LCD_PEN_PIN_30_EN_MASK) + +#define LCD_PEN_PIN_31_EN_MASK (0x80000000U) +#define LCD_PEN_PIN_31_EN_SHIFT (31U) +/*! PIN_31_EN - LCD Pin 31 Enable + * 0b0..Pin Disable + * 0b1..Pin Enable + */ +#define LCD_PEN_PIN_31_EN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PIN_31_EN_SHIFT)) & LCD_PEN_PIN_31_EN_MASK) +/*! @} */ + +/*! @name BPEN - LCD Back Plane Enable register 0..LCD Back Plane Enable register 1 */ +/*! @{ */ + +#define LCD_BPEN_PIN_0_BPEN_MASK (0x1U) +#define LCD_BPEN_PIN_0_BPEN_SHIFT (0U) +/*! PIN_0_BPEN - LCD Pin 0 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_0_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_0_BPEN_SHIFT)) & LCD_BPEN_PIN_0_BPEN_MASK) + +#define LCD_BPEN_PIN_32_BPEN_MASK (0x1U) +#define LCD_BPEN_PIN_32_BPEN_SHIFT (0U) +/*! PIN_32_BPEN - LCD Pin 32 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_32_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_32_BPEN_SHIFT)) & LCD_BPEN_PIN_32_BPEN_MASK) + +#define LCD_BPEN_PIN_1_BPEN_MASK (0x2U) +#define LCD_BPEN_PIN_1_BPEN_SHIFT (1U) +/*! PIN_1_BPEN - LCD Pin 1 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_1_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_1_BPEN_SHIFT)) & LCD_BPEN_PIN_1_BPEN_MASK) + +#define LCD_BPEN_PIN_33_BPEN_MASK (0x2U) +#define LCD_BPEN_PIN_33_BPEN_SHIFT (1U) +/*! PIN_33_BPEN - LCD Pin 33 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_33_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_33_BPEN_SHIFT)) & LCD_BPEN_PIN_33_BPEN_MASK) + +#define LCD_BPEN_PIN_2_BPEN_MASK (0x4U) +#define LCD_BPEN_PIN_2_BPEN_SHIFT (2U) +/*! PIN_2_BPEN - LCD Pin 2 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_2_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_2_BPEN_SHIFT)) & LCD_BPEN_PIN_2_BPEN_MASK) + +#define LCD_BPEN_PIN_34_BPEN_MASK (0x4U) +#define LCD_BPEN_PIN_34_BPEN_SHIFT (2U) +/*! PIN_34_BPEN - LCD Pin 34 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_34_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_34_BPEN_SHIFT)) & LCD_BPEN_PIN_34_BPEN_MASK) + +#define LCD_BPEN_PIN_3_BPEN_MASK (0x8U) +#define LCD_BPEN_PIN_3_BPEN_SHIFT (3U) +/*! PIN_3_BPEN - LCD Pin 3 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_3_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_3_BPEN_SHIFT)) & LCD_BPEN_PIN_3_BPEN_MASK) + +#define LCD_BPEN_PIN_35_BPEN_MASK (0x8U) +#define LCD_BPEN_PIN_35_BPEN_SHIFT (3U) +/*! PIN_35_BPEN - LCD Pin 35 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_35_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_35_BPEN_SHIFT)) & LCD_BPEN_PIN_35_BPEN_MASK) + +#define LCD_BPEN_PIN_4_BPEN_MASK (0x10U) +#define LCD_BPEN_PIN_4_BPEN_SHIFT (4U) +/*! PIN_4_BPEN - LCD Pin 4 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_4_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_4_BPEN_SHIFT)) & LCD_BPEN_PIN_4_BPEN_MASK) + +#define LCD_BPEN_PIN_36_BPEN_MASK (0x10U) +#define LCD_BPEN_PIN_36_BPEN_SHIFT (4U) +/*! PIN_36_BPEN - LCD Pin 36 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_36_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_36_BPEN_SHIFT)) & LCD_BPEN_PIN_36_BPEN_MASK) + +#define LCD_BPEN_PIN_5_BPEN_MASK (0x20U) +#define LCD_BPEN_PIN_5_BPEN_SHIFT (5U) +/*! PIN_5_BPEN - LCD Pin 5 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_5_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_5_BPEN_SHIFT)) & LCD_BPEN_PIN_5_BPEN_MASK) + +#define LCD_BPEN_PIN_37_BPEN_MASK (0x20U) +#define LCD_BPEN_PIN_37_BPEN_SHIFT (5U) +/*! PIN_37_BPEN - LCD Pin 37 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_37_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_37_BPEN_SHIFT)) & LCD_BPEN_PIN_37_BPEN_MASK) + +#define LCD_BPEN_PIN_6_BPEN_MASK (0x40U) +#define LCD_BPEN_PIN_6_BPEN_SHIFT (6U) +/*! PIN_6_BPEN - LCD Pin 6 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_6_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_6_BPEN_SHIFT)) & LCD_BPEN_PIN_6_BPEN_MASK) + +#define LCD_BPEN_PIN_38_BPEN_MASK (0x40U) +#define LCD_BPEN_PIN_38_BPEN_SHIFT (6U) +/*! PIN_38_BPEN - LCD Pin 38 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_38_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_38_BPEN_SHIFT)) & LCD_BPEN_PIN_38_BPEN_MASK) + +#define LCD_BPEN_PIN_7_BPEN_MASK (0x80U) +#define LCD_BPEN_PIN_7_BPEN_SHIFT (7U) +/*! PIN_7_BPEN - LCD Pin 7 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_7_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_7_BPEN_SHIFT)) & LCD_BPEN_PIN_7_BPEN_MASK) + +#define LCD_BPEN_PIN_39_BPEN_MASK (0x80U) +#define LCD_BPEN_PIN_39_BPEN_SHIFT (7U) +/*! PIN_39_BPEN - LCD Pin 39 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_39_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_39_BPEN_SHIFT)) & LCD_BPEN_PIN_39_BPEN_MASK) + +#define LCD_BPEN_PIN_8_BPEN_MASK (0x100U) +#define LCD_BPEN_PIN_8_BPEN_SHIFT (8U) +/*! PIN_8_BPEN - LCD Pin 8 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_8_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_8_BPEN_SHIFT)) & LCD_BPEN_PIN_8_BPEN_MASK) + +#define LCD_BPEN_PIN_40_BPEN_MASK (0x100U) +#define LCD_BPEN_PIN_40_BPEN_SHIFT (8U) +/*! PIN_40_BPEN - LCD Pin 40 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_40_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_40_BPEN_SHIFT)) & LCD_BPEN_PIN_40_BPEN_MASK) + +#define LCD_BPEN_PIN_9_BPEN_MASK (0x200U) +#define LCD_BPEN_PIN_9_BPEN_SHIFT (9U) +/*! PIN_9_BPEN - LCD Pin 9 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_9_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_9_BPEN_SHIFT)) & LCD_BPEN_PIN_9_BPEN_MASK) + +#define LCD_BPEN_PIN_41_BPEN_MASK (0x200U) +#define LCD_BPEN_PIN_41_BPEN_SHIFT (9U) +/*! PIN_41_BPEN - LCD Pin 41 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_41_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_41_BPEN_SHIFT)) & LCD_BPEN_PIN_41_BPEN_MASK) + +#define LCD_BPEN_PIN_10_BPEN_MASK (0x400U) +#define LCD_BPEN_PIN_10_BPEN_SHIFT (10U) +/*! PIN_10_BPEN - LCD Pin 10 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_10_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_10_BPEN_SHIFT)) & LCD_BPEN_PIN_10_BPEN_MASK) + +#define LCD_BPEN_PIN_42_BPEN_MASK (0x400U) +#define LCD_BPEN_PIN_42_BPEN_SHIFT (10U) +/*! PIN_42_BPEN - LCD Pin 42 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_42_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_42_BPEN_SHIFT)) & LCD_BPEN_PIN_42_BPEN_MASK) + +#define LCD_BPEN_PIN_11_BPEN_MASK (0x800U) +#define LCD_BPEN_PIN_11_BPEN_SHIFT (11U) +/*! PIN_11_BPEN - LCD Pin 11 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_11_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_11_BPEN_SHIFT)) & LCD_BPEN_PIN_11_BPEN_MASK) + +#define LCD_BPEN_PIN_43_BPEN_MASK (0x800U) +#define LCD_BPEN_PIN_43_BPEN_SHIFT (11U) +/*! PIN_43_BPEN - LCD Pin 43 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_43_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_43_BPEN_SHIFT)) & LCD_BPEN_PIN_43_BPEN_MASK) + +#define LCD_BPEN_PIN_12_BPEN_MASK (0x1000U) +#define LCD_BPEN_PIN_12_BPEN_SHIFT (12U) +/*! PIN_12_BPEN - LCD Pin 12 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_12_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_12_BPEN_SHIFT)) & LCD_BPEN_PIN_12_BPEN_MASK) + +#define LCD_BPEN_PIN_44_BPEN_MASK (0x1000U) +#define LCD_BPEN_PIN_44_BPEN_SHIFT (12U) +/*! PIN_44_BPEN - LCD Pin 44 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_44_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_44_BPEN_SHIFT)) & LCD_BPEN_PIN_44_BPEN_MASK) + +#define LCD_BPEN_PIN_13_BPEN_MASK (0x2000U) +#define LCD_BPEN_PIN_13_BPEN_SHIFT (13U) +/*! PIN_13_BPEN - LCD Pin 13 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_13_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_13_BPEN_SHIFT)) & LCD_BPEN_PIN_13_BPEN_MASK) + +#define LCD_BPEN_PIN_45_BPEN_MASK (0x2000U) +#define LCD_BPEN_PIN_45_BPEN_SHIFT (13U) +/*! PIN_45_BPEN - LCD Pin 45 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_45_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_45_BPEN_SHIFT)) & LCD_BPEN_PIN_45_BPEN_MASK) + +#define LCD_BPEN_PIN_14_BPEN_MASK (0x4000U) +#define LCD_BPEN_PIN_14_BPEN_SHIFT (14U) +/*! PIN_14_BPEN - LCD Pin 14 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_14_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_14_BPEN_SHIFT)) & LCD_BPEN_PIN_14_BPEN_MASK) + +#define LCD_BPEN_PIN_46_BPEN_MASK (0x4000U) +#define LCD_BPEN_PIN_46_BPEN_SHIFT (14U) +/*! PIN_46_BPEN - LCD Pin 46 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_46_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_46_BPEN_SHIFT)) & LCD_BPEN_PIN_46_BPEN_MASK) + +#define LCD_BPEN_PIN_15_BPEN_MASK (0x8000U) +#define LCD_BPEN_PIN_15_BPEN_SHIFT (15U) +/*! PIN_15_BPEN - LCD Pin 15 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_15_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_15_BPEN_SHIFT)) & LCD_BPEN_PIN_15_BPEN_MASK) + +#define LCD_BPEN_PIN_47_BPEN_MASK (0x8000U) +#define LCD_BPEN_PIN_47_BPEN_SHIFT (15U) +/*! PIN_47_BPEN - LCD Pin 47 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_47_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_47_BPEN_SHIFT)) & LCD_BPEN_PIN_47_BPEN_MASK) + +#define LCD_BPEN_PIN_16_BPEN_MASK (0x10000U) +#define LCD_BPEN_PIN_16_BPEN_SHIFT (16U) +/*! PIN_16_BPEN - LCD Pin 16 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_16_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_16_BPEN_SHIFT)) & LCD_BPEN_PIN_16_BPEN_MASK) + +#define LCD_BPEN_PIN_17_BPEN_MASK (0x20000U) +#define LCD_BPEN_PIN_17_BPEN_SHIFT (17U) +/*! PIN_17_BPEN - LCD Pin 17 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_17_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_17_BPEN_SHIFT)) & LCD_BPEN_PIN_17_BPEN_MASK) + +#define LCD_BPEN_PIN_18_BPEN_MASK (0x40000U) +#define LCD_BPEN_PIN_18_BPEN_SHIFT (18U) +/*! PIN_18_BPEN - LCD Pin 18 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_18_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_18_BPEN_SHIFT)) & LCD_BPEN_PIN_18_BPEN_MASK) + +#define LCD_BPEN_PIN_19_BPEN_MASK (0x80000U) +#define LCD_BPEN_PIN_19_BPEN_SHIFT (19U) +/*! PIN_19_BPEN - LCD Pin 19 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_19_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_19_BPEN_SHIFT)) & LCD_BPEN_PIN_19_BPEN_MASK) + +#define LCD_BPEN_PIN_20_BPEN_MASK (0x100000U) +#define LCD_BPEN_PIN_20_BPEN_SHIFT (20U) +/*! PIN_20_BPEN - LCD Pin 20 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_20_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_20_BPEN_SHIFT)) & LCD_BPEN_PIN_20_BPEN_MASK) + +#define LCD_BPEN_PIN_21_BPEN_MASK (0x200000U) +#define LCD_BPEN_PIN_21_BPEN_SHIFT (21U) +/*! PIN_21_BPEN - LCD Pin 21 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_21_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_21_BPEN_SHIFT)) & LCD_BPEN_PIN_21_BPEN_MASK) + +#define LCD_BPEN_PIN_22_BPEN_MASK (0x400000U) +#define LCD_BPEN_PIN_22_BPEN_SHIFT (22U) +/*! PIN_22_BPEN - LCD Pin 22 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_22_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_22_BPEN_SHIFT)) & LCD_BPEN_PIN_22_BPEN_MASK) + +#define LCD_BPEN_PIN_23_BPEN_MASK (0x800000U) +#define LCD_BPEN_PIN_23_BPEN_SHIFT (23U) +/*! PIN_23_BPEN - LCD Pin 23 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_23_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_23_BPEN_SHIFT)) & LCD_BPEN_PIN_23_BPEN_MASK) + +#define LCD_BPEN_PIN_24_BPEN_MASK (0x1000000U) +#define LCD_BPEN_PIN_24_BPEN_SHIFT (24U) +/*! PIN_24_BPEN - LCD Pin 24 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_24_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_24_BPEN_SHIFT)) & LCD_BPEN_PIN_24_BPEN_MASK) + +#define LCD_BPEN_PIN_25_BPEN_MASK (0x2000000U) +#define LCD_BPEN_PIN_25_BPEN_SHIFT (25U) +/*! PIN_25_BPEN - LCD Pin 25 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_25_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_25_BPEN_SHIFT)) & LCD_BPEN_PIN_25_BPEN_MASK) + +#define LCD_BPEN_PIN_26_BPEN_MASK (0x4000000U) +#define LCD_BPEN_PIN_26_BPEN_SHIFT (26U) +/*! PIN_26_BPEN - LCD Pin 26 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_26_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_26_BPEN_SHIFT)) & LCD_BPEN_PIN_26_BPEN_MASK) + +#define LCD_BPEN_PIN_27_BPEN_MASK (0x8000000U) +#define LCD_BPEN_PIN_27_BPEN_SHIFT (27U) +/*! PIN_27_BPEN - LCD Pin 27 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_27_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_27_BPEN_SHIFT)) & LCD_BPEN_PIN_27_BPEN_MASK) + +#define LCD_BPEN_PIN_28_BPEN_MASK (0x10000000U) +#define LCD_BPEN_PIN_28_BPEN_SHIFT (28U) +/*! PIN_28_BPEN - LCD Pin 28 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_28_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_28_BPEN_SHIFT)) & LCD_BPEN_PIN_28_BPEN_MASK) + +#define LCD_BPEN_PIN_29_BPEN_MASK (0x20000000U) +#define LCD_BPEN_PIN_29_BPEN_SHIFT (29U) +/*! PIN_29_BPEN - LCD Pin 29 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_29_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_29_BPEN_SHIFT)) & LCD_BPEN_PIN_29_BPEN_MASK) + +#define LCD_BPEN_PIN_30_BPEN_MASK (0x40000000U) +#define LCD_BPEN_PIN_30_BPEN_SHIFT (30U) +/*! PIN_30_BPEN - LCD Pin 30 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_30_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_30_BPEN_SHIFT)) & LCD_BPEN_PIN_30_BPEN_MASK) + +#define LCD_BPEN_PIN_31_BPEN_MASK (0x80000000U) +#define LCD_BPEN_PIN_31_BPEN_SHIFT (31U) +/*! PIN_31_BPEN - LCD Pin 31 Back Plane Enable + * 0b0..Pin as Front Plane + * 0b1..Pin as Back Plane + */ +#define LCD_BPEN_PIN_31_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_PIN_31_BPEN_SHIFT)) & LCD_BPEN_PIN_31_BPEN_MASK) +/*! @} */ + +/*! @name WF8B - LCD Waveform 0 Register..LCD Waveform 47 Register */ +/*! @{ */ + +#define LCD_WF8B_WF_MASK (0xFFU) +#define LCD_WF8B_WF_SHIFT (0U) +/*! WF - Pin Waveform */ +#define LCD_WF8B_WF(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_WF_SHIFT)) & LCD_WF8B_WF_MASK) +/*! @} */ + +/* The count of LCD_WF8B */ +#define LCD_WF8B_COUNT (48U) + +/*! @name WF - LCD Waveform 3 to 0 Register..LCD Waveform 47 to 44 Register */ +/*! @{ */ + +#define LCD_WF_WF0_MASK (0xFFU) +#define LCD_WF_WF0_SHIFT (0U) +/*! WF0 - Waveform Pin 0 */ +#define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF0_SHIFT)) & LCD_WF_WF0_MASK) + +#define LCD_WF_WF4_MASK (0xFFU) +#define LCD_WF_WF4_SHIFT (0U) +/*! WF4 - Waveform Pin 4 */ +#define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF4_SHIFT)) & LCD_WF_WF4_MASK) + +#define LCD_WF_WF8_MASK (0xFFU) +#define LCD_WF_WF8_SHIFT (0U) +/*! WF8 - Waveform Pin 8 */ +#define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF8_SHIFT)) & LCD_WF_WF8_MASK) + +#define LCD_WF_WF12_MASK (0xFFU) +#define LCD_WF_WF12_SHIFT (0U) +/*! WF12 - Waveform Pin 12 */ +#define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF12_SHIFT)) & LCD_WF_WF12_MASK) + +#define LCD_WF_WF16_MASK (0xFFU) +#define LCD_WF_WF16_SHIFT (0U) +/*! WF16 - Waveform Pin 16 */ +#define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF16_SHIFT)) & LCD_WF_WF16_MASK) + +#define LCD_WF_WF20_MASK (0xFFU) +#define LCD_WF_WF20_SHIFT (0U) +/*! WF20 - Waveform Pin 20 */ +#define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF20_SHIFT)) & LCD_WF_WF20_MASK) + +#define LCD_WF_WF24_MASK (0xFFU) +#define LCD_WF_WF24_SHIFT (0U) +/*! WF24 - Waveform Pin 24 */ +#define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF24_SHIFT)) & LCD_WF_WF24_MASK) + +#define LCD_WF_WF28_MASK (0xFFU) +#define LCD_WF_WF28_SHIFT (0U) +/*! WF28 - Waveform Pin 28 */ +#define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF28_SHIFT)) & LCD_WF_WF28_MASK) + +#define LCD_WF_WF32_MASK (0xFFU) +#define LCD_WF_WF32_SHIFT (0U) +/*! WF32 - Waveform Pin 32 */ +#define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF32_SHIFT)) & LCD_WF_WF32_MASK) + +#define LCD_WF_WF36_MASK (0xFFU) +#define LCD_WF_WF36_SHIFT (0U) +/*! WF36 - Waveform Pin 36 */ +#define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF36_SHIFT)) & LCD_WF_WF36_MASK) + +#define LCD_WF_WF40_MASK (0xFFU) +#define LCD_WF_WF40_SHIFT (0U) +/*! WF40 - Waveform Pin 40 */ +#define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF40_SHIFT)) & LCD_WF_WF40_MASK) + +#define LCD_WF_WF44_MASK (0xFFU) +#define LCD_WF_WF44_SHIFT (0U) +/*! WF44 - Waveform Pin 44 */ +#define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF44_SHIFT)) & LCD_WF_WF44_MASK) + +#define LCD_WF_WF1_MASK (0xFF00U) +#define LCD_WF_WF1_SHIFT (8U) +/*! WF1 - Waveform Pin 1 */ +#define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF1_SHIFT)) & LCD_WF_WF1_MASK) + +#define LCD_WF_WF5_MASK (0xFF00U) +#define LCD_WF_WF5_SHIFT (8U) +/*! WF5 - Waveform Pin 5 */ +#define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF5_SHIFT)) & LCD_WF_WF5_MASK) + +#define LCD_WF_WF9_MASK (0xFF00U) +#define LCD_WF_WF9_SHIFT (8U) +/*! WF9 - Waveform Pin 9 */ +#define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF9_SHIFT)) & LCD_WF_WF9_MASK) + +#define LCD_WF_WF13_MASK (0xFF00U) +#define LCD_WF_WF13_SHIFT (8U) +/*! WF13 - Waveform Pin 13 */ +#define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF13_SHIFT)) & LCD_WF_WF13_MASK) + +#define LCD_WF_WF17_MASK (0xFF00U) +#define LCD_WF_WF17_SHIFT (8U) +/*! WF17 - Waveform Pin 17 */ +#define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF17_SHIFT)) & LCD_WF_WF17_MASK) + +#define LCD_WF_WF21_MASK (0xFF00U) +#define LCD_WF_WF21_SHIFT (8U) +/*! WF21 - Waveform Pin 21 */ +#define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF21_SHIFT)) & LCD_WF_WF21_MASK) + +#define LCD_WF_WF25_MASK (0xFF00U) +#define LCD_WF_WF25_SHIFT (8U) +/*! WF25 - Waveform Pin 25 */ +#define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF25_SHIFT)) & LCD_WF_WF25_MASK) + +#define LCD_WF_WF29_MASK (0xFF00U) +#define LCD_WF_WF29_SHIFT (8U) +/*! WF29 - Waveform Pin 29 */ +#define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF29_SHIFT)) & LCD_WF_WF29_MASK) + +#define LCD_WF_WF33_MASK (0xFF00U) +#define LCD_WF_WF33_SHIFT (8U) +/*! WF33 - Waveform Pin 33 */ +#define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF33_SHIFT)) & LCD_WF_WF33_MASK) + +#define LCD_WF_WF37_MASK (0xFF00U) +#define LCD_WF_WF37_SHIFT (8U) +/*! WF37 - Waveform Pin 37 */ +#define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF37_SHIFT)) & LCD_WF_WF37_MASK) + +#define LCD_WF_WF41_MASK (0xFF00U) +#define LCD_WF_WF41_SHIFT (8U) +/*! WF41 - Waveform Pin 41 */ +#define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF41_SHIFT)) & LCD_WF_WF41_MASK) + +#define LCD_WF_WF45_MASK (0xFF00U) +#define LCD_WF_WF45_SHIFT (8U) +/*! WF45 - Waveform Pin 45 */ +#define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF45_SHIFT)) & LCD_WF_WF45_MASK) + +#define LCD_WF_WF2_MASK (0xFF0000U) +#define LCD_WF_WF2_SHIFT (16U) +/*! WF2 - Waveform Pin 2 */ +#define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF2_SHIFT)) & LCD_WF_WF2_MASK) + +#define LCD_WF_WF6_MASK (0xFF0000U) +#define LCD_WF_WF6_SHIFT (16U) +/*! WF6 - Waveform Pin 6 */ +#define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF6_SHIFT)) & LCD_WF_WF6_MASK) + +#define LCD_WF_WF10_MASK (0xFF0000U) +#define LCD_WF_WF10_SHIFT (16U) +/*! WF10 - Waveform Pin 10 */ +#define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF10_SHIFT)) & LCD_WF_WF10_MASK) + +#define LCD_WF_WF14_MASK (0xFF0000U) +#define LCD_WF_WF14_SHIFT (16U) +/*! WF14 - Waveform Pin 14 */ +#define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF14_SHIFT)) & LCD_WF_WF14_MASK) + +#define LCD_WF_WF18_MASK (0xFF0000U) +#define LCD_WF_WF18_SHIFT (16U) +/*! WF18 - Waveform Pin 18 */ +#define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF18_SHIFT)) & LCD_WF_WF18_MASK) + +#define LCD_WF_WF22_MASK (0xFF0000U) +#define LCD_WF_WF22_SHIFT (16U) +/*! WF22 - Waveform Pin 22 */ +#define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF22_SHIFT)) & LCD_WF_WF22_MASK) + +#define LCD_WF_WF26_MASK (0xFF0000U) +#define LCD_WF_WF26_SHIFT (16U) +/*! WF26 - Waveform Pin 26 */ +#define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF26_SHIFT)) & LCD_WF_WF26_MASK) + +#define LCD_WF_WF30_MASK (0xFF0000U) +#define LCD_WF_WF30_SHIFT (16U) +/*! WF30 - Waveform Pin 30 */ +#define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF30_SHIFT)) & LCD_WF_WF30_MASK) + +#define LCD_WF_WF34_MASK (0xFF0000U) +#define LCD_WF_WF34_SHIFT (16U) +/*! WF34 - Waveform Pin 34 */ +#define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF34_SHIFT)) & LCD_WF_WF34_MASK) + +#define LCD_WF_WF38_MASK (0xFF0000U) +#define LCD_WF_WF38_SHIFT (16U) +/*! WF38 - Waveform Pin 38 */ +#define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF38_SHIFT)) & LCD_WF_WF38_MASK) + +#define LCD_WF_WF42_MASK (0xFF0000U) +#define LCD_WF_WF42_SHIFT (16U) +/*! WF42 - Waveform Pin 42 */ +#define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF42_SHIFT)) & LCD_WF_WF42_MASK) + +#define LCD_WF_WF46_MASK (0xFF0000U) +#define LCD_WF_WF46_SHIFT (16U) +/*! WF46 - Waveform Pin 46 */ +#define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF46_SHIFT)) & LCD_WF_WF46_MASK) + +#define LCD_WF_WF3_MASK (0xFF000000U) +#define LCD_WF_WF3_SHIFT (24U) +/*! WF3 - Waveform Pin 3 */ +#define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF3_SHIFT)) & LCD_WF_WF3_MASK) + +#define LCD_WF_WF7_MASK (0xFF000000U) +#define LCD_WF_WF7_SHIFT (24U) +/*! WF7 - Waveform Pin 7 */ +#define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF7_SHIFT)) & LCD_WF_WF7_MASK) + +#define LCD_WF_WF11_MASK (0xFF000000U) +#define LCD_WF_WF11_SHIFT (24U) +/*! WF11 - Waveform Pin 11 */ +#define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF11_SHIFT)) & LCD_WF_WF11_MASK) + +#define LCD_WF_WF15_MASK (0xFF000000U) +#define LCD_WF_WF15_SHIFT (24U) +/*! WF15 - Waveform Pin 15 */ +#define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF15_SHIFT)) & LCD_WF_WF15_MASK) + +#define LCD_WF_WF19_MASK (0xFF000000U) +#define LCD_WF_WF19_SHIFT (24U) +/*! WF19 - Waveform Pin 19 */ +#define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF19_SHIFT)) & LCD_WF_WF19_MASK) + +#define LCD_WF_WF23_MASK (0xFF000000U) +#define LCD_WF_WF23_SHIFT (24U) +/*! WF23 - Waveform Pin 23 */ +#define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF23_SHIFT)) & LCD_WF_WF23_MASK) + +#define LCD_WF_WF27_MASK (0xFF000000U) +#define LCD_WF_WF27_SHIFT (24U) +/*! WF27 - Waveform Pin 27 */ +#define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF27_SHIFT)) & LCD_WF_WF27_MASK) + +#define LCD_WF_WF31_MASK (0xFF000000U) +#define LCD_WF_WF31_SHIFT (24U) +/*! WF31 - Waveform Pin 31 */ +#define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF31_SHIFT)) & LCD_WF_WF31_MASK) + +#define LCD_WF_WF35_MASK (0xFF000000U) +#define LCD_WF_WF35_SHIFT (24U) +/*! WF35 - Waveform Pin 35 */ +#define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF35_SHIFT)) & LCD_WF_WF35_MASK) + +#define LCD_WF_WF39_MASK (0xFF000000U) +#define LCD_WF_WF39_SHIFT (24U) +/*! WF39 - Waveform Pin 39 */ +#define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF39_SHIFT)) & LCD_WF_WF39_MASK) + +#define LCD_WF_WF43_MASK (0xFF000000U) +#define LCD_WF_WF43_SHIFT (24U) +/*! WF43 - Waveform Pin 43 */ +#define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF43_SHIFT)) & LCD_WF_WF43_MASK) + +#define LCD_WF_WF47_MASK (0xFF000000U) +#define LCD_WF_WF47_SHIFT (24U) +/*! WF47 - Waveform Pin 47 */ +#define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x)) << LCD_WF_WF47_SHIFT)) & LCD_WF_WF47_MASK) +/*! @} */ + +/* The count of LCD_WF */ +#define LCD_WF_COUNT (12U) + + +/*! + * @} + */ /* end of group LCD_Register_Masks */ + + +/*! + * @} + */ /* end of group LCD_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LCD_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPCMP.h new file mode 100644 index 000000000..4ae9a3a2e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPCMP.h @@ -0,0 +1,854 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPCMP +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_LPCMP.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for LPCMP + * + * CMSIS Peripheral Access Layer for LPCMP + */ + +#if !defined(PERI_LPCMP_H_) +#define PERI_LPCMP_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPCMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer + * @{ + */ + +/** LPCMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ + __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ + __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DCR; /**< DAC Control, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t CSR; /**< Comparator Status, offset: 0x20 */ + __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ + __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ + __IO uint32_t RRCSR; /**< Round Robin Control and Status, offset: 0x2C */ + __IO uint32_t RRSR; /**< Round Robin Status, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */ +} LPCMP_Type; + +/* ---------------------------------------------------------------------------- + -- LPCMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Register_Masks LPCMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPCMP_VERID_FEATURE_MASK (0xFFFFU) +#define LPCMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000001..Round robin feature + */ +#define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) + +#define LPCMP_VERID_MINOR_MASK (0xFF0000U) +#define LPCMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) + +#define LPCMP_VERID_MAJOR_MASK (0xFF000000U) +#define LPCMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPCMP_PARAM_DAC_RES_MASK (0xFU) +#define LPCMP_PARAM_DAC_RES_SHIFT (0U) +/*! DAC_RES - DAC Resolution + * 0b0000..4-bit DAC + * 0b0001..6-bit DAC + * 0b0010..8-bit DAC + * 0b0011..10-bit DAC + * 0b0100..12-bit DAC + * 0b0101..14-bit DAC + * 0b0110..16-bit DAC + */ +#define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) +/*! @} */ + +/*! @name CCR0 - Comparator Control Register 0 */ +/*! @{ */ + +#define LPCMP_CCR0_CMP_EN_MASK (0x1U) +#define LPCMP_CCR0_CMP_EN_SHIFT (0U) +/*! CMP_EN - Comparator Enable + * 0b0..Disable (The analog logic remains off and consumes no power.) + * 0b1..Enable + */ +#define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) + +#define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U) +#define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U) +/*! CMP_STOP_EN - Comparator Deep sleep Mode Enable + * 0b0..Disables the analog comparator regardless of CMP_EN. + * 0b1..Allows CMP_EN to enable the analog comparator. + */ +#define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK) +/*! @} */ + +/*! @name CCR1 - Comparator Control Register 1 */ +/*! @{ */ + +#define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) +#define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) +/*! WINDOW_EN - Windowing Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) + +#define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) +#define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) +/*! SAMPLE_EN - Sampling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) + +#define LPCMP_CCR1_DMA_EN_MASK (0x4U) +#define LPCMP_CCR1_DMA_EN_SHIFT (2U) +/*! DMA_EN - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) + +#define LPCMP_CCR1_COUT_INV_MASK (0x8U) +#define LPCMP_CCR1_COUT_INV_SHIFT (3U) +/*! COUT_INV - Comparator Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) + +#define LPCMP_CCR1_COUT_SEL_MASK (0x10U) +#define LPCMP_CCR1_COUT_SEL_SHIFT (4U) +/*! COUT_SEL - Comparator Output Select + * 0b0..Use COUT (filtered) + * 0b1..Use COUTA (unfiltered) + */ +#define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) + +#define LPCMP_CCR1_COUT_PEN_MASK (0x20U) +#define LPCMP_CCR1_COUT_PEN_SHIFT (5U) +/*! COUT_PEN - Comparator Output Pin Enable + * 0b0..Not available + * 0b1..Available + */ +#define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) + +#define LPCMP_CCR1_COUTA_OWEN_MASK (0x40U) +#define LPCMP_CCR1_COUTA_OWEN_SHIFT (6U) +/*! COUTA_OWEN - COUTA_OW Enable + * 0b0..COUTA holds the last sampled value. + * 0b1..Enables the COUTA signal value to be defined by COUTA_OW. + */ +#define LPCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK) + +#define LPCMP_CCR1_COUTA_OW_MASK (0x80U) +#define LPCMP_CCR1_COUTA_OW_SHIFT (7U) +/*! COUTA_OW - COUTA Output Level for Closed Window + * 0b0..COUTA is 0 + * 0b1..COUTA is 1 + */ +#define LPCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK) + +#define LPCMP_CCR1_WINDOW_INV_MASK (0x100U) +#define LPCMP_CCR1_WINDOW_INV_SHIFT (8U) +/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK) + +#define LPCMP_CCR1_WINDOW_CLS_MASK (0x200U) +#define LPCMP_CCR1_WINDOW_CLS_SHIFT (9U) +/*! WINDOW_CLS - COUT Event Window Close + * 0b0..COUT event cannot close the window + * 0b1..COUT event can close the window + */ +#define LPCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK) + +#define LPCMP_CCR1_EVT_SEL_MASK (0xC00U) +#define LPCMP_CCR1_EVT_SEL_SHIFT (10U) +/*! EVT_SEL - COUT Event Select + * 0b00..Rising edge + * 0b01..Falling edge + * 0b1x..Both edges + */ +#define LPCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK) + +#define LPCMP_CCR1_FUNC_CLK_SEL_MASK (0x3000U) +#define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT (12U) +/*! FUNC_CLK_SEL - Functional Clock Source Select + * 0b00..Select functional clock source 0 + * 0b01..Select functional clock source 1 + * 0b10..Select functional clock source 2 + * 0b11..Select functional clock source 3 + */ +#define LPCMP_CCR1_FUNC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK) + +#define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) +#define LPCMP_CCR1_FILT_CNT_SHIFT (16U) +/*! FILT_CNT - Filter Sample Count + * 0b000..Filter is bypassed: COUT = COUTA + * 0b001..1 consecutive sample (Comparator output is simply sampled.) + * 0b010..2 consecutive samples + * 0b011..3 consecutive samples + * 0b100..4 consecutive samples + * 0b101..5 consecutive samples + * 0b110..6 consecutive samples + * 0b111..7 consecutive samples + */ +#define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) + +#define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) +#define LPCMP_CCR1_FILT_PER_SHIFT (24U) +/*! FILT_PER - Filter Sample Period */ +#define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) +/*! @} */ + +/*! @name CCR2 - Comparator Control Register 2 */ +/*! @{ */ + +#define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) +#define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) +/*! CMP_HPMD - CMP High Power Mode Select + * 0b0..Low power (speed) comparison mode + * 0b1..High power (speed) comparison mode + */ +#define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) + +#define LPCMP_CCR2_CMP_NPMD_MASK (0x2U) +#define LPCMP_CCR2_CMP_NPMD_SHIFT (1U) +/*! CMP_NPMD - CMP Nano Power Mode Select + * 0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator. + * 0b1..Enables CMP Nano power mode. + */ +#define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK) + +#define LPCMP_CCR2_HYSTCTR_MASK (0x30U) +#define LPCMP_CCR2_HYSTCTR_SHIFT (4U) +/*! HYSTCTR - Comparator Hysteresis Control + * 0b00..Level 0: Analog comparator hysteresis 0 mV. + * 0b01..Level 1: Analog comparator hysteresis 10 mV. + * 0b10..Level 2: Analog comparator hysteresis 20 mV. + * 0b11..Level 3: Analog comparator hysteresis 30 mV. + */ +#define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) + +#define LPCMP_CCR2_PSEL_MASK (0x70000U) +#define LPCMP_CCR2_PSEL_SHIFT (16U) +/*! PSEL - Plus Input MUX Select + * 0b000..Input 0p + * 0b001..Input 1p + * 0b010..Input 2p + * 0b011..Input 3p + * 0b100..Input 4p + * 0b101..Input 5p + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) + +#define LPCMP_CCR2_MSEL_MASK (0x700000U) +#define LPCMP_CCR2_MSEL_SHIFT (20U) +/*! MSEL - Minus Input MUX Select + * 0b000..Input 0m + * 0b001..Input 1m + * 0b010..Input 2m + * 0b011..Input 3m + * 0b100..Input 4m + * 0b101..Input 5m + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) +/*! @} */ + +/*! @name DCR - DAC Control */ +/*! @{ */ + +#define LPCMP_DCR_DAC_EN_MASK (0x1U) +#define LPCMP_DCR_DAC_EN_SHIFT (0U) +/*! DAC_EN - DAC Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) + +#define LPCMP_DCR_DAC_HPMD_MASK (0x2U) +#define LPCMP_DCR_DAC_HPMD_SHIFT (1U) +/*! DAC_HPMD - DAC High Power Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) + +#define LPCMP_DCR_VRSEL_MASK (0x100U) +#define LPCMP_DCR_VRSEL_SHIFT (8U) +/*! VRSEL - DAC Reference High Voltage Source Select + * 0b0..VREFH0 + * 0b1..VREFH1 + */ +#define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) + +#define LPCMP_DCR_DAC_DATA_MASK (0xFF0000U) +#define LPCMP_DCR_DAC_DATA_SHIFT (16U) +/*! DAC_DATA - DAC Output Voltage Select */ +#define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPCMP_IER_CFR_IE_MASK (0x1U) +#define LPCMP_IER_CFR_IE_SHIFT (0U) +/*! CFR_IE - Comparator Flag Rising Interrupt Enable + * 0b0..Disables the comparator flag rising interrupt. + * 0b1..Enables the comparator flag rising interrupt when CFR is set. + */ +#define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) + +#define LPCMP_IER_CFF_IE_MASK (0x2U) +#define LPCMP_IER_CFF_IE_SHIFT (1U) +/*! CFF_IE - Comparator Flag Falling Interrupt Enable + * 0b0..Disables the comparator flag falling interrupt. + * 0b1..Enables the comparator flag falling interrupt when CFF is set. + */ +#define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) + +#define LPCMP_IER_RRF_IE_MASK (0x4U) +#define LPCMP_IER_RRF_IE_SHIFT (2U) +/*! RRF_IE - Round-Robin Flag Interrupt Enable + * 0b0..Disables the round-robin flag interrupt. + * 0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel. + */ +#define LPCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK) +/*! @} */ + +/*! @name CSR - Comparator Status */ +/*! @{ */ + +#define LPCMP_CSR_CFR_MASK (0x1U) +#define LPCMP_CSR_CFR_SHIFT (0U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) + +#define LPCMP_CSR_CFF_MASK (0x2U) +#define LPCMP_CSR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) + +#define LPCMP_CSR_RRF_MASK (0x4U) +#define LPCMP_CSR_RRF_SHIFT (2U) +/*! RRF - Round-Robin Flag + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK) + +#define LPCMP_CSR_COUT_MASK (0x100U) +#define LPCMP_CSR_COUT_SHIFT (8U) +/*! COUT - Analog Comparator Output */ +#define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) +/*! @} */ + +/*! @name RRCR0 - Round Robin Control Register 0 */ +/*! @{ */ + +#define LPCMP_RRCR0_RR_EN_MASK (0x1U) +#define LPCMP_RRCR0_RR_EN_SHIFT (0U) +/*! RR_EN - Round-Robin Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) + +#define LPCMP_RRCR0_RR_TRG_SEL_MASK (0x2U) +#define LPCMP_RRCR0_RR_TRG_SEL_SHIFT (1U) +/*! RR_TRG_SEL - Round-Robin Trigger Select + * 0b0..External trigger + * 0b1..Internal trigger + */ +#define LPCMP_RRCR0_RR_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK) + +#define LPCMP_RRCR0_RR_EXTTRG_SEL_MASK (0x3CU) +#define LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT (2U) +/*! RR_EXTTRG_SEL - External Trigger Source Select + * 0b0000..Select external trigger source 0 + * 0b0001..Select external trigger source 1 + * 0b0010..Select external trigger source 2 + * 0b0011..Select external trigger source 3 + * 0b0100..Select external trigger source 4 + * 0b0101..Select external trigger source 5 + * 0b0110..Select external trigger source 6 + * 0b0111..Select external trigger source 7 + * 0b1000..Select external trigger source 8 + * 0b1001..Select external trigger source 9 + * 0b1010..Select external trigger source 10 + * 0b1011..Select external trigger source 11 + * 0b1100..Select external trigger source 12 + * 0b1101..Select external trigger source 13 + * 0b1110..Select external trigger source 14 + * 0b1111..Select external trigger source 15 + */ +#define LPCMP_RRCR0_RR_EXTTRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_EXTTRG_SEL_MASK) + +#define LPCMP_RRCR0_RR_NSAM_MASK (0x300U) +#define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) +/*! RR_NSAM - Number of Sample Clocks + * 0b00..0 clock + * 0b01..1 clock + * 0b10..2 clocks + * 0b11..3 clocks + */ +#define LPCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK) + +#define LPCMP_RRCR0_RR_CLK_SEL_MASK (0x3000U) +#define LPCMP_RRCR0_RR_CLK_SEL_SHIFT (12U) +/*! RR_CLK_SEL - Round Robin Clock Source Select + * 0b00..Select Round Robin clock Source 0 + * 0b01..Select Round Robin clock Source 1 + * 0b10..Select Round Robin clock Source 2 + * 0b11..Select Round Robin clock Source 3 + */ +#define LPCMP_RRCR0_RR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK) + +#define LPCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) +#define LPCMP_RRCR0_RR_INITMOD_SHIFT (16U) +/*! RR_INITMOD - Initialization Delay Modulus + * 0b000000..63 cycles (same as 111111b) + * 0b000001-0b111111..1 to 63 cycles + */ +#define LPCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK (0xF000000U) +#define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT (24U) +/*! RR_SAMPLE_CNT - Number of Sample for One Channel + * 0b0000..1 samples + * 0b0001..2 samples + * 0b0010..3 samples + * 0b0011..4 samples + * 0b0100..5 samples + * 0b0101..6 samples + * 0b0110..7 samples + * 0b0111..8 samples + * 0b1000..9 samples + * 0b1001..10 samples + * 0b1010..11 samples + * 0b1011..12 samples + * 0b1100..13 samples + * 0b1101..14 samples + * 0b1110..15 samples + * 0b1111..16 samples + */ +#define LPCMP_RRCR0_RR_SAMPLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK (0xF0000000U) +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT (28U) +/*! RR_SAMPLE_THRESHOLD - Sample Time Threshold + * 0b0000..At least 1 sampled "1", the final result is "1" + * 0b0001..At least 2 sampled "1", the final result is "1" + * 0b0010..At least 3 sampled "1", the final result is "1" + * 0b0011..At least 4 sampled "1", the final result is "1" + * 0b0100..At least 5 sampled "1", the final result is "1" + * 0b0101..At least 6 sampled "1", the final result is "1" + * 0b0110..At least 7 sampled "1", the final result is "1" + * 0b0111..At least 8 sampled "1", the final result is "1" + * 0b1000..At least 9 sampled "1", the final result is "1" + * 0b1001..At least 10 sampled "1", the final result is "1" + * 0b1010..At least 11 sampled "1", the final result is "1" + * 0b1011..At least 12 sampled "1", the final result is "1" + * 0b1100..At least 13 sampled "1", the final result is "1" + * 0b1101..At least 14 sampled "1", the final result is "1" + * 0b1110..At least 15 sampled "1", the final result is "1" + * 0b1111..At least 16 sampled "1", the final result is "1" + */ +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK) +/*! @} */ + +/*! @name RRCR1 - Round Robin Control Register 1 */ +/*! @{ */ + +#define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) +#define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) +/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) + +#define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) +#define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) +/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) + +#define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) +#define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) +/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) + +#define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) +#define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) +/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) + +#define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) +#define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) +/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) + +#define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) +#define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) +/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) + +#define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) +#define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) +/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) + +#define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) +#define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) +/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) + +#define LPCMP_RRCR1_FIXP_MASK (0x10000U) +#define LPCMP_RRCR1_FIXP_SHIFT (16U) +/*! FIXP - Fixed Port + * 0b0..Fix the plus port. Sweep only the inputs to the minus port. + * 0b1..Fix the minus port. Sweep only the inputs to the plus port. + */ +#define LPCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK) + +#define LPCMP_RRCR1_FIXCH_MASK (0x700000U) +#define LPCMP_RRCR1_FIXCH_SHIFT (20U) +/*! FIXCH - Fixed Channel Select + * 0b000..Channel 0 + * 0b001..Channel 1 + * 0b010..Channel 2 + * 0b011..Channel 3 + * 0b100..Channel 4 + * 0b101..Channel 5 + * 0b110..Channel 6 + * 0b111..Channel 7 + */ +#define LPCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK) +/*! @} */ + +/*! @name RRCSR - Round Robin Control and Status */ +/*! @{ */ + +#define LPCMP_RRCSR_RR_CH0OUT_MASK (0x1U) +#define LPCMP_RRCSR_RR_CH0OUT_SHIFT (0U) +/*! RR_CH0OUT - Comparison Result for Channel 0 */ +#define LPCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK) + +#define LPCMP_RRCSR_RR_CH1OUT_MASK (0x2U) +#define LPCMP_RRCSR_RR_CH1OUT_SHIFT (1U) +/*! RR_CH1OUT - Comparison Result for Channel 1 */ +#define LPCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK) + +#define LPCMP_RRCSR_RR_CH2OUT_MASK (0x4U) +#define LPCMP_RRCSR_RR_CH2OUT_SHIFT (2U) +/*! RR_CH2OUT - Comparison Result for Channel 2 */ +#define LPCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK) + +#define LPCMP_RRCSR_RR_CH3OUT_MASK (0x8U) +#define LPCMP_RRCSR_RR_CH3OUT_SHIFT (3U) +/*! RR_CH3OUT - Comparison Result for Channel 3 */ +#define LPCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK) + +#define LPCMP_RRCSR_RR_CH4OUT_MASK (0x10U) +#define LPCMP_RRCSR_RR_CH4OUT_SHIFT (4U) +/*! RR_CH4OUT - Comparison Result for Channel 4 */ +#define LPCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK) + +#define LPCMP_RRCSR_RR_CH5OUT_MASK (0x20U) +#define LPCMP_RRCSR_RR_CH5OUT_SHIFT (5U) +/*! RR_CH5OUT - Comparison Result for Channel 5 */ +#define LPCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK) + +#define LPCMP_RRCSR_RR_CH6OUT_MASK (0x40U) +#define LPCMP_RRCSR_RR_CH6OUT_SHIFT (6U) +/*! RR_CH6OUT - Comparison Result for Channel 6 */ +#define LPCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK) + +#define LPCMP_RRCSR_RR_CH7OUT_MASK (0x80U) +#define LPCMP_RRCSR_RR_CH7OUT_SHIFT (7U) +/*! RR_CH7OUT - Comparison Result for Channel 7 */ +#define LPCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK) +/*! @} */ + +/*! @name RRSR - Round Robin Status */ +/*! @{ */ + +#define LPCMP_RRSR_RR_CH0F_MASK (0x1U) +#define LPCMP_RRSR_RR_CH0F_SHIFT (0U) +/*! RR_CH0F - Channel 0 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) + +#define LPCMP_RRSR_RR_CH1F_MASK (0x2U) +#define LPCMP_RRSR_RR_CH1F_SHIFT (1U) +/*! RR_CH1F - Channel 1 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) + +#define LPCMP_RRSR_RR_CH2F_MASK (0x4U) +#define LPCMP_RRSR_RR_CH2F_SHIFT (2U) +/*! RR_CH2F - Channel 2 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) + +#define LPCMP_RRSR_RR_CH3F_MASK (0x8U) +#define LPCMP_RRSR_RR_CH3F_SHIFT (3U) +/*! RR_CH3F - Channel 3 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) + +#define LPCMP_RRSR_RR_CH4F_MASK (0x10U) +#define LPCMP_RRSR_RR_CH4F_SHIFT (4U) +/*! RR_CH4F - Channel 4 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) + +#define LPCMP_RRSR_RR_CH5F_MASK (0x20U) +#define LPCMP_RRSR_RR_CH5F_SHIFT (5U) +/*! RR_CH5F - Channel 5 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) + +#define LPCMP_RRSR_RR_CH6F_MASK (0x40U) +#define LPCMP_RRSR_RR_CH6F_SHIFT (6U) +/*! RR_CH6F - Channel 6 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) + +#define LPCMP_RRSR_RR_CH7F_MASK (0x80U) +#define LPCMP_RRSR_RR_CH7F_SHIFT (7U) +/*! RR_CH7F - Channel 7 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) +/*! @} */ + +/*! @name RRCR2 - Round Robin Control Register 2 */ +/*! @{ */ + +#define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU) +#define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U) +/*! RR_TIMER_RELOAD - Number of Sample Clocks */ +#define LPCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK) + +#define LPCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U) +#define LPCMP_RRCR2_RR_TIMER_EN_SHIFT (31U) +/*! RR_TIMER_EN - Round-Robin Internal Timer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPCMP_Register_Masks */ + + +/*! + * @} + */ /* end of group LPCMP_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPCMP_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPDAC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPDAC.h new file mode 100644 index 000000000..3d1bbefb4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPDAC.h @@ -0,0 +1,532 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPDAC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_LPDAC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for LPDAC + * + * CMSIS Peripheral Access Layer for LPDAC + */ + +#if !defined(PERI_LPDAC_H_) +#define PERI_LPDAC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPDAC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer + * @{ + */ + +/** LPDAC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version Identifier, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t DATA; /**< Data, offset: 0x8 */ + __IO uint32_t GCR; /**< Global Control, offset: 0xC */ + __IO uint32_t FCR; /**< DAC FIFO Control, offset: 0x10 */ + __I uint32_t FPR; /**< DAC FIFO Pointer, offset: 0x14 */ + __IO uint32_t FSR; /**< FIFO Status, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x20 */ + __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ + __IO uint32_t TCR; /**< Trigger Control, offset: 0x28 */ + __IO uint32_t PCR; /**< Periodic Trigger Control, offset: 0x2C */ +} LPDAC_Type; + +/* ---------------------------------------------------------------------------- + -- LPDAC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPDAC_Register_Masks LPDAC Register Masks + * @{ + */ + +/*! @name VERID - Version Identifier */ +/*! @{ */ + +#define LPDAC_VERID_FEATURE_MASK (0xFFFFU) +#define LPDAC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number */ +#define LPDAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK) + +#define LPDAC_VERID_MINOR_MASK (0xFF0000U) +#define LPDAC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPDAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK) + +#define LPDAC_VERID_MAJOR_MASK (0xFF000000U) +#define LPDAC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPDAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPDAC_PARAM_FIFOSZ_MASK (0x7U) +#define LPDAC_PARAM_FIFOSZ_SHIFT (0U) +/*! FIFOSZ - FIFO Size + * 0b000..Reserved + * 0b001..FIFO depth is 4 + * 0b010..FIFO depth is 8 + * 0b011..FIFO depth is 16 + * 0b100..FIFO depth is 32 + * 0b101..FIFO depth is 64 + * 0b110..FIFO depth is 128 + * 0b111..FIFO depth is 256 + */ +#define LPDAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPDAC_DATA_DATA_MASK (0xFFFU) +#define LPDAC_DATA_DATA_SHIFT (0U) +/*! DATA - FIFO Entry or Buffer Entry */ +#define LPDAC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK) +/*! @} */ + +/*! @name GCR - Global Control */ +/*! @{ */ + +#define LPDAC_GCR_DACEN_MASK (0x1U) +#define LPDAC_GCR_DACEN_SHIFT (0U) +/*! DACEN - DAC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_GCR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK) + +#define LPDAC_GCR_DACRFS_MASK (0x6U) +#define LPDAC_GCR_DACRFS_SHIFT (1U) +/*! DACRFS - DAC Reference Select + * 0b00..Selects VREFH0 as the reference voltage. + * 0b01..Selects VREFH1 as the reference voltage. + * 0b10..Selects VREFH2 as the reference voltage. + * 0b11..Reserved. + */ +#define LPDAC_GCR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK) + +#define LPDAC_GCR_FIFOEN_MASK (0x8U) +#define LPDAC_GCR_FIFOEN_SHIFT (3U) +/*! FIFOEN - FIFO Enable + * 0b0..Disables FIFO mode and enables Buffer mode. Any data written to DATA[DATA] goes to buffer then goes to conversion. + * 0b1..Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion. + */ +#define LPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK) + +#define LPDAC_GCR_SWMD_MASK (0x10U) +#define LPDAC_GCR_SWMD_SHIFT (4U) +/*! SWMD - Swing Back Mode + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_GCR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK) + +#define LPDAC_GCR_TRGSEL_MASK (0x20U) +#define LPDAC_GCR_TRGSEL_SHIFT (5U) +/*! TRGSEL - DAC Trigger Select + * 0b0..Hardware trigger + * 0b1..Software trigger + */ +#define LPDAC_GCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK) + +#define LPDAC_GCR_PTGEN_MASK (0x40U) +#define LPDAC_GCR_PTGEN_SHIFT (6U) +/*! PTGEN - DAC Periodic Trigger Mode Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_GCR_PTGEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_PTGEN_SHIFT)) & LPDAC_GCR_PTGEN_MASK) + +#define LPDAC_GCR_LATCH_CYC_MASK (0xF00U) +#define LPDAC_GCR_LATCH_CYC_SHIFT (8U) +/*! LATCH_CYC - RCLK Cycles Before Data Latch */ +#define LPDAC_GCR_LATCH_CYC(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LATCH_CYC_SHIFT)) & LPDAC_GCR_LATCH_CYC_MASK) + +#define LPDAC_GCR_BUF_EN_MASK (0x20000U) +#define LPDAC_GCR_BUF_EN_SHIFT (17U) +/*! BUF_EN - Buffer Enable + * 0b0..Not used + * 0b1..Used + */ +#define LPDAC_GCR_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_EN_SHIFT)) & LPDAC_GCR_BUF_EN_MASK) + +#define LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK (0x100000U) +#define LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT (20U) +/*! IREF_PTAT_EXT_SEL - External On-Chip PTAT Current Reference Select + * 0b0..Not selected + * 0b1..Selected + */ +#define LPDAC_GCR_IREF_PTAT_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK) + +#define LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK (0x200000U) +#define LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT (21U) +/*! IREF_ZTC_EXT_SEL - External On-Chip ZTC Current Reference Select + * 0b0..Not selected + * 0b1..Selected + */ +#define LPDAC_GCR_IREF_ZTC_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK) + +#define LPDAC_GCR_BUF_SPD_CTRL_MASK (0x800000U) +#define LPDAC_GCR_BUF_SPD_CTRL_SHIFT (23U) +/*! BUF_SPD_CTRL - OPAMP as Buffer, Speed Control Signal + * 0b0..Lower Low-Power mode + * 0b1..Low-Power mode + */ +#define LPDAC_GCR_BUF_SPD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_SPD_CTRL_SHIFT)) & LPDAC_GCR_BUF_SPD_CTRL_MASK) +/*! @} */ + +/*! @name FCR - DAC FIFO Control */ +/*! @{ */ + +#define LPDAC_FCR_WML_MASK (0xFU) +#define LPDAC_FCR_WML_SHIFT (0U) +/*! WML - Watermark Level */ +#define LPDAC_FCR_WML(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK) +/*! @} */ + +/*! @name FPR - DAC FIFO Pointer */ +/*! @{ */ + +#define LPDAC_FPR_FIFO_RPT_MASK (0xFU) +#define LPDAC_FPR_FIFO_RPT_SHIFT (0U) +/*! FIFO_RPT - FIFO Read Pointer */ +#define LPDAC_FPR_FIFO_RPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK) + +#define LPDAC_FPR_FIFO_WPT_MASK (0xF0000U) +#define LPDAC_FPR_FIFO_WPT_SHIFT (16U) +/*! FIFO_WPT - FIFO Write Pointer */ +#define LPDAC_FPR_FIFO_WPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPDAC_FSR_FULL_MASK (0x1U) +#define LPDAC_FSR_FULL_SHIFT (0U) +/*! FULL - FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define LPDAC_FSR_FULL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK) + +#define LPDAC_FSR_EMPTY_MASK (0x2U) +#define LPDAC_FSR_EMPTY_SHIFT (1U) +/*! EMPTY - FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define LPDAC_FSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK) + +#define LPDAC_FSR_WM_MASK (0x4U) +#define LPDAC_FSR_WM_SHIFT (2U) +/*! WM - FIFO Watermark Status Flag + * 0b0..Data in FIFO is more than watermark level + * 0b1..Data in FIFO is less than or equal to watermark level + */ +#define LPDAC_FSR_WM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK) + +#define LPDAC_FSR_SWBK_MASK (0x8U) +#define LPDAC_FSR_SWBK_SHIFT (3U) +/*! SWBK - Swing Back One Cycle Complete Flag + * 0b0..No swing back cycle has completed since the last time the flag was cleared + * 0b1..At least one swing back cycle has occurred since the last time the flag was cleared + */ +#define LPDAC_FSR_SWBK(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK) + +#define LPDAC_FSR_OF_MASK (0x40U) +#define LPDAC_FSR_OF_SHIFT (6U) +/*! OF - FIFO Overflow Flag + * 0b0..No overflow has occurred since the last time the flag was cleared + * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared + */ +#define LPDAC_FSR_OF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK) + +#define LPDAC_FSR_UF_MASK (0x80U) +#define LPDAC_FSR_UF_SHIFT (7U) +/*! UF - FIFO Underflow Flag + * 0b0..No underflow has occurred since the last time the flag was cleared + * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared + */ +#define LPDAC_FSR_UF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK) + +#define LPDAC_FSR_PTGCOCO_MASK (0x100U) +#define LPDAC_FSR_PTGCOCO_SHIFT (8U) +/*! PTGCOCO - Period Trigger Mode Conversion Complete Flag + * 0b0..Not completed or not started + * 0b1..Completed + */ +#define LPDAC_FSR_PTGCOCO(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_PTGCOCO_SHIFT)) & LPDAC_FSR_PTGCOCO_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPDAC_IER_FULL_IE_MASK (0x1U) +#define LPDAC_IER_FULL_IE_SHIFT (0U) +/*! FULL_IE - FIFO Full Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_FULL_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK) + +#define LPDAC_IER_EMPTY_IE_MASK (0x2U) +#define LPDAC_IER_EMPTY_IE_SHIFT (1U) +/*! EMPTY_IE - FIFO Empty Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_EMPTY_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK) + +#define LPDAC_IER_WM_IE_MASK (0x4U) +#define LPDAC_IER_WM_IE_SHIFT (2U) +/*! WM_IE - FIFO Watermark Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_WM_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK) + +#define LPDAC_IER_SWBK_IE_MASK (0x8U) +#define LPDAC_IER_SWBK_IE_SHIFT (3U) +/*! SWBK_IE - Swing Back One Cycle Complete Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_SWBK_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK) + +#define LPDAC_IER_OF_IE_MASK (0x40U) +#define LPDAC_IER_OF_IE_SHIFT (6U) +/*! OF_IE - FIFO Overflow Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_OF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK) + +#define LPDAC_IER_UF_IE_MASK (0x80U) +#define LPDAC_IER_UF_IE_SHIFT (7U) +/*! UF_IE - FIFO Underflow Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_UF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK) + +#define LPDAC_IER_PTGCOCO_IE_MASK (0x100U) +#define LPDAC_IER_PTGCOCO_IE_SHIFT (8U) +/*! PTGCOCO_IE - PTG Mode Conversion Complete Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_PTGCOCO_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_PTGCOCO_IE_SHIFT)) & LPDAC_IER_PTGCOCO_IE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPDAC_DER_EMPTY_DMAEN_MASK (0x2U) +#define LPDAC_DER_EMPTY_DMAEN_SHIFT (1U) +/*! EMPTY_DMAEN - FIFO Empty DMA Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_DER_EMPTY_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK) + +#define LPDAC_DER_WM_DMAEN_MASK (0x4U) +#define LPDAC_DER_WM_DMAEN_SHIFT (2U) +/*! WM_DMAEN - FIFO Watermark DMA Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_DER_WM_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK) +/*! @} */ + +/*! @name RCR - Reset Control */ +/*! @{ */ + +#define LPDAC_RCR_SWRST_MASK (0x1U) +#define LPDAC_RCR_SWRST_SHIFT (0U) +/*! SWRST - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define LPDAC_RCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK) + +#define LPDAC_RCR_FIFORST_MASK (0x2U) +#define LPDAC_RCR_FIFORST_SHIFT (1U) +/*! FIFORST - FIFO Reset + * 0b0..No effect + * 0b1..FIFO reset + */ +#define LPDAC_RCR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK) +/*! @} */ + +/*! @name TCR - Trigger Control */ +/*! @{ */ + +#define LPDAC_TCR_SWTRG_MASK (0x1U) +#define LPDAC_TCR_SWTRG_SHIFT (0U) +/*! SWTRG - Software Trigger + * 0b0..Not valid + * 0b1..Valid + */ +#define LPDAC_TCR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK) +/*! @} */ + +/*! @name PCR - Periodic Trigger Control */ +/*! @{ */ + +#define LPDAC_PCR_PTG_NUM_MASK (0xFFFFU) +#define LPDAC_PCR_PTG_NUM_SHIFT (0U) +/*! PTG_NUM - Periodic Trigger Number */ +#define LPDAC_PCR_PTG_NUM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_NUM_SHIFT)) & LPDAC_PCR_PTG_NUM_MASK) + +#define LPDAC_PCR_PTG_PERIOD_MASK (0xFFFF0000U) +#define LPDAC_PCR_PTG_PERIOD_SHIFT (16U) +/*! PTG_PERIOD - Periodic Trigger Period Width */ +#define LPDAC_PCR_PTG_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_PERIOD_SHIFT)) & LPDAC_PCR_PTG_PERIOD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPDAC_Register_Masks */ + + +/*! + * @} + */ /* end of group LPDAC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPDAC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPI2C.h new file mode 100644 index 000000000..36b187df0 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPI2C.h @@ -0,0 +1,1461 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPI2C +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_LPI2C.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for LPI2C + * + * CMSIS Peripheral Access Layer for LPI2C + */ + +#if !defined(PERI_LPI2C_H_) +#define PERI_LPI2C_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ + __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ + __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ + __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ + __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ + __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_7[148]; + __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ + __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ + __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ + __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ + __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ + __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ + uint8_t RESERVED_12[4]; + __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Controller only, with standard feature set + * 0b0000000000000011..Controller and target, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) + +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) + +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +/*! MTXFIFO - Controller Transmit FIFO Size */ +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) + +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +/*! MRXFIFO - Controller Receive FIFO Size */ +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Controller Control */ +/*! @{ */ + +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Controller Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) + +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..No effect + * 0b1..Reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) + +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) + +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) + +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset transmit FIFO + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) + +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset receive FIFO + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Controller Status */ +/*! @{ */ + +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) + +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) + +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..No Stop or repeated Start generated + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Stop or repeated Start generated + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) + +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Stop condition generated + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) + +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..No effect + * 0b0..No unexpected NACK detected + * 0b1..Clear the flag + * 0b1..Unexpected NACK detected + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) + +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Controller did not lose arbitration + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Controller lost arbitration + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) + +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..FIFO error + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) + +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..No effect + * 0b0..Pin low timeout did not occur + * 0b1..Clear the flag + * 0b1..Pin low timeout occurred + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) + +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Matching data not received + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Matching data received + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) + +#define LPI2C_MSR_STF_MASK (0x8000U) +#define LPI2C_MSR_STF_SHIFT (15U) +/*! STF - Start Flag + * 0b0..No effect + * 0b0..Start condition not detected + * 0b1..Clear the flag + * 0b1..Start condition detected + */ +#define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) + +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Controller Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) + +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Controller Interrupt Enable */ +/*! @{ */ + +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) + +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) + +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) + +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) + +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) + +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) + +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) + +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) + +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +#define LPI2C_MIER_STIE_MASK (0x8000U) +#define LPI2C_MIER_STIE_SHIFT (15U) +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) +/*! @} */ + +/*! @name MDER - Controller DMA Enable */ +/*! @{ */ + +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) + +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Controller Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) + +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) + +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) + +#define LPI2C_MCFGR0_HRDIR_MASK (0x8U) +#define LPI2C_MCFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..HREQ pin is input (for LPI2C controller) + * 0b1..HREQ pin is output (for LPI2C target) + */ +#define LPI2C_MCFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK) + +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) + +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless MSR[DMF] is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +#define LPI2C_MCFGR0_RELAX_MASK (0x10000U) +#define LPI2C_MCFGR0_RELAX_SHIFT (16U) +/*! RELAX - Relaxed Mode + * 0b0..Normal transfer + * 0b1..Relaxed transfer + */ +#define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) + +#define LPI2C_MCFGR0_ABORT_MASK (0x20000U) +#define LPI2C_MCFGR0_ABORT_SHIFT (17U) +/*! ABORT - Abort Transfer + * 0b0..Normal transfer + * 0b1..Abort existing transfer and do not start a new one + */ +#define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) +/*! @} */ + +/*! @name MCFGR1 - Controller Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) + +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic Stop Generation + * 0b0..No effect + * 0b1..Stop automatically generated + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) + +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - Ignore NACK + * 0b0..No effect + * 0b1..Treat a received NACK as an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) + +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..SCL + * 0b1..SCL or SDA + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) + +#define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) +#define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition + */ +#define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) + +#define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) +#define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle + */ +#define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) + +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) + +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..Two-pin open drain mode + * 0b001..Two-pin output only mode (Ultra-Fast mode) + * 0b010..Two-pin push-pull mode + * 0b011..Four-pin push-pull mode + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target + * 0b110..Two-pin push-pull mode with separate LPI2C target + * 0b111..Four-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Controller Configuration 2 */ +/*! @{ */ + +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +/*! BUSIDLE - Bus Idle Timeout */ +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) + +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) + +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Controller Configuration 3 */ +/*! @{ */ + +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +/*! PINLOW - Pin Low Timeout */ +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Controller Data Match */ +/*! @{ */ + +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) + +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +/*! MATCH1 - Match 1 Value */ +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Controller Clock Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) + +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) + +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) + +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Controller Clock Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) + +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) + +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) + +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Controller FIFO Control */ +/*! @{ */ + +#define LPI2C_MFCR_TXWATER_MASK (0x3U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) + +#define LPI2C_MFCR_RXWATER_MASK (0x30000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Controller FIFO Status */ +/*! @{ */ + +#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) + +#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Controller Transmit Data */ +/*! @{ */ + +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) + +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit the value in DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate Stop condition on I2C bus + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Controller Receive Data */ +/*! @{ */ + +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) + +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name MRDROR - Controller Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_MRDROR_DATA_MASK (0xFFU) +#define LPI2C_MRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) + +#define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Target Control */ +/*! @{ */ + +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) + +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) + +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) + +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) + +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..STDR is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) + +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..SRDR is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Target Status */ +/*! @{ */ + +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) + +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) + +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) + +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) + +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..No effect + * 0b0..No repeated Start detected + * 0b1..Clear the flag + * 0b1..Repeated Start detected + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) + +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Stop detected + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) + +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b0..No effect + * 0b1..Bit error occurred + * 0b1..Clear the flag + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) + +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..FIFO error + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) + +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..ADDR0 matching address not received + * 0b1..ADDR0 matching address received + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) + +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) + +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) + +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) + +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Target Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) + +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Target Interrupt Enable */ +/*! @{ */ + +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) + +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) + +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) + +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) + +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) + +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) + +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) + +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) + +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) + +#define LPI2C_SIER_AM1IE_MASK (0x2000U) +#define LPI2C_SIER_AM1IE_SHIFT (13U) +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) + +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) + +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Target DMA Enable */ +/*! @{ */ + +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) + +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) + +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +#define LPI2C_SDER_RSDE_MASK (0x100U) +#define LPI2C_SDER_RSDE_SHIFT (8U) +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) + +#define LPI2C_SDER_SDDE_MASK (0x200U) +#define LPI2C_SDER_SDDE_SHIFT (9U) +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) +/*! @} */ + +/*! @name SCFGR0 - Target Configuration 0 */ +/*! @{ */ + +#define LPI2C_SCFGR0_RDREQ_MASK (0x1U) +#define LPI2C_SCFGR0_RDREQ_SHIFT (0U) +/*! RDREQ - Read Request + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) + +#define LPI2C_SCFGR0_RDACK_MASK (0x2U) +#define LPI2C_SCFGR0_RDACK_SHIFT (1U) +/*! RDACK - Read Acknowledge Flag + * 0b0..Read Request not acknowledged + * 0b1..Read Request acknowledged + */ +#define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) +/*! @} */ + +/*! @name SCFGR1 - Target Configuration 1 */ +/*! @{ */ + +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) + +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) + +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) + +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) + +#define LPI2C_SCFGR1_RXNACK_MASK (0x10U) +#define LPI2C_SCFGR1_RXNACK_SHIFT (4U) +/*! RXNACK - Receive NACK + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] + */ +#define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) + +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) + +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) + +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..SSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..SSR[TDF] is set whenever STDR is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) + +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Return received data, clear SSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear SSR[RDF] when SSR[AFV] is not set + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) + +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) + +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - HS Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) + +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +#define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) +#define LPI2C_SCFGR1_RXALL_SHIFT (24U) +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) + +#define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) +#define LPI2C_SCFGR1_RSCFG_SHIFT (25U) +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition + */ +#define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) + +#define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) +#define LPI2C_SCFGR1_SDCFG_SHIFT (26U) +/*! SDCFG - Stop Detect Configuration + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition + */ +#define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Target Configuration 2 */ +/*! @{ */ + +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +/*! CLKHOLD - Clock Hold Time */ +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) + +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) + +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) + +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Target Address Match */ +/*! @{ */ + +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +/*! ADDR0 - Address 0 Value */ +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) + +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +/*! ADDR1 - Address 1 Value */ +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Target Address Status */ +/*! @{ */ + +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +/*! RADDR - Received Address */ +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) + +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Target Transmit ACK */ +/*! @{ */ + +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Transmit ACK + * 0b1..Transmit NACK + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Target Transmit Data */ +/*! @{ */ + +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Target Receive Data */ +/*! @{ */ + +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +/*! DATA - Received Data */ +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) + +#define LPI2C_SRDR_RADDR_MASK (0x700U) +#define LPI2C_SRDR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) + +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) + +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + +/*! @name SRDROR - Target Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_SRDROR_DATA_MASK (0xFFU) +#define LPI2C_SRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) + +#define LPI2C_SRDROR_RADDR_MASK (0x700U) +#define LPI2C_SRDROR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) + +#define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) + +#define LPI2C_SRDROR_SOF_MASK (0x8000U) +#define LPI2C_SRDROR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First + */ +#define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPI2C_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPSPI.h new file mode 100644 index 000000000..250142421 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPSPI.h @@ -0,0 +1,893 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPSPI +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_LPSPI.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for LPSPI + * + * CMSIS Peripheral Access Layer for LPSPI + */ + +#if !defined(PERI_LPSPI_H_) +#define PERI_LPSPI_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Size of Registers Arrays */ +#define LPSPI_TDBR_COUNT 128u +#define LPSPI_RDBR_COUNT 128u + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ + __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ + __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_5[896]; + __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ + __O uint32_t TDBR[LPSPI_TDBR_COUNT]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ + __I uint32_t RDBR[LPSPI_RDBR_COUNT]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) + +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) + +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) + +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) + +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +/*! PCSNUM - PCS Number */ +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) + +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) + +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) + +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) + +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) + +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) + +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..No effect + * 0b0..Not complete + * 0b1..Clear the flag + * 0b1..Complete + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) + +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..No effect + * 0b0..Not complete + * 0b1..Clear the flag + * 0b1..Complete + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) + +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..No effect + * 0b0..Not complete + * 0b1..Clear the flag + * 0b1..Complete + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) + +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..No effect + * 0b0..No underrun + * 0b1..Clear the flag + * 0b1..Underrun + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) + +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..No effect + * 0b0..No overflow + * 0b1..Clear the flag + * 0b1..Overflow + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) + +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..No effect + * 0b0..No match + * 0b1..Clear the flag + * 0b1..Match + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) + +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) + +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) + +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) + +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) + +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) + +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) + +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) + +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) + +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) + +#define LPSPI_DER_FCDE_MASK (0x200U) +#define LPSPI_DER_FCDE_SHIFT (9U) +/*! FCDE - Frame Complete DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration 0 */ +/*! @{ */ + +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) + +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) + +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..HREQ pin + * 0b1..Input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) + +#define LPSPI_CFGR0_HRDIR_MASK (0x8U) +#define LPSPI_CFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..Input + * 0b1..Output + */ +#define LPSPI_CFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK) + +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) + +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration 1 */ +/*! @{ */ + +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Controller Mode + * 0b0..Peripheral mode + * 0b1..Controller mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) + +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..SCK edge + * 0b1..Delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) + +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) + +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) + +#define LPSPI_CFGR1_PARTIAL_MASK (0x10U) +#define LPSPI_CFGR1_PARTIAL_SHIFT (4U) +/*! PARTIAL - Partial Enable + * 0b0..Discard + * 0b1..Store + */ +#define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) + +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..Active low + * 0b0001..Active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) + +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001.. + * 0b010..Match first data word with compare word + * 0b011..Match any data word with compare word + * 0b100..Sequential match, first data word + * 0b101..Sequential match, any data word + * 0b110..Match first data word (masked) with compare word (masked) + * 0b111..Match any data word (masked) with compare word (masked) + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) + +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) + +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Configuration + * 0b0..Retain last value + * 0b1..3-stated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) + +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] configured for chip select function + * 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match 0 */ +/*! @{ */ + +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match 1 */ +/*! @{ */ + +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +/*! MATCH1 - Match 1 Value */ +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration */ +/*! @{ */ + +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +/*! SCKDIV - SCK Divider */ +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) + +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +/*! DBT - Delay Between Transfers */ +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) + +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +/*! PCSSCK - PCS-to-SCK Delay */ +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) + +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +/*! SCKPCS - SCK-to-PCS Delay */ +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name CCR1 - Clock Configuration 1 */ +/*! @{ */ + +#define LPSPI_CCR1_SCKSET_MASK (0xFFU) +#define LPSPI_CCR1_SCKSET_SHIFT (0U) +/*! SCKSET - SCK Setup */ +#define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) + +#define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) +#define LPSPI_CCR1_SCKHLD_SHIFT (8U) +/*! SCKHLD - SCK Hold */ +#define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) + +#define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) +#define LPSPI_CCR1_PCSPCS_SHIFT (16U) +/*! PCSPCS - PCS to PCS Delay */ +#define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) + +#define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) +#define LPSPI_CCR1_SCKSCK_SHIFT (24U) +/*! SCKSCK - SCK Inter-Frame Delay */ +#define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control */ +/*! @{ */ + +#define LPSPI_FCR_TXWATER_MASK (0x3U) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) + +#define LPSPI_FCR_RXWATER_MASK (0x30000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPSPI_FSR_TXCOUNT_MASK (0x7U) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) + +#define LPSPI_FSR_RXCOUNT_MASK (0x70000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command */ +/*! @{ */ + +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +/*! FRAMESZ - Frame Size */ +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) + +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1-bit transfer + * 0b01..2-bit transfer + * 0b10..4-bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) + +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) + +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Mask receive data + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) + +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) + +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) + +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Disable byte swap + * 0b1..Enable byte swap + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) + +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..MSB first + * 0b1..LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) + +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using PCS[0] + * 0b01..Transfer using PCS[1] + * 0b10..Transfer using PCS[2] + * 0b11..Transfer using PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) + +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) + +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Captured + * 0b1..Changed + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) + +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..Inactive low + * 0b1..Inactive high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start of Frame + * 0b0..Subsequent data word or RX FIFO is empty (RXEMPTY=1). + * 0b1..First data word + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) + +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + +/*! @name RDROR - Receive Data Read Only */ +/*! @{ */ + +#define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) +/*! @} */ + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TCBR_DATA_SHIFT (0U) +/*! DATA - Command Data */ +#define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) +/*! @} */ + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) +/*! @} */ + +/*! @name RDBR - Receive Data Burst */ +/*! @{ */ + +#define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPSPI_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPTMR.h new file mode 100644 index 000000000..15f71ebe8 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPTMR.h @@ -0,0 +1,312 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPTMR +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_LPTMR.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for LPTMR + * + * CMSIS Peripheral Access Layer for LPTMR + */ + +#if !defined(PERI_LPTMR_H_) +#define PERI_LPTMR_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ + __IO uint32_t CMR; /**< Compare, offset: 0x8 */ + __IO uint32_t CNR; /**< Counter, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Control Status */ +/*! @{ */ + +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) + +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +/*! TMS - Timer Mode Select + * 0b0..Time Counter + * 0b1..Pulse Counter + */ +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) + +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +/*! TFC - Timer Free-Running Counter + * 0b0..Reset when TCF asserts + * 0b1..Reset on overflow + */ +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) + +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +/*! TPP - Timer Pin Polarity + * 0b0..Active-high + * 0b1..Active-low + */ +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) + +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +/*! TPS - Timer Pin Select + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 + */ +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) + +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) + +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +/*! TCF - Timer Compare Flag + * 0b0..CNR != (CMR + 1) + * 0b0..No effect + * 0b1..CNR = (CMR + 1) + * 0b1..Clear the flag + */ +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +#define LPTMR_CSR_TDRE_MASK (0x100U) +#define LPTMR_CSR_TDRE_SHIFT (8U) +/*! TDRE - Timer DMA Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) +/*! @} */ + +/*! @name PSR - Prescaler and Glitch Filter */ +/*! @{ */ + +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +/*! PCS - Prescaler and Glitch Filter Clock Select + * 0b00..Clock 0 + * 0b01..Clock 1 + * 0b10..Clock 2 + * 0b11..Clock 3 + */ +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) + +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass + */ +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) + +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges + */ +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) +/*! @} */ + +/*! @name CMR - Compare */ +/*! @{ */ + +#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +/*! COMPARE - Compare Value */ +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) +/*! @} */ + +/*! @name CNR - Counter */ +/*! @{ */ + +#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +/*! COUNTER - Counter Value */ +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPTMR_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPUART.h new file mode 100644 index 000000000..42ea77acf --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_LPUART.h @@ -0,0 +1,1166 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPUART +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_LPUART.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for LPUART + * + * CMSIS Peripheral Access Layer for LPUART + */ + +#if !defined(PERI_LPUART_H_) +#define PERI_LPUART_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ + __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ + __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ + __IO uint32_t STAT; /**< Status, offset: 0x14 */ + __IO uint32_t CTRL; /**< Control, offset: 0x18 */ + __IO uint32_t DATA; /**< Data, offset: 0x1C */ + __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ + __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ + __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ + __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ + __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with MODEM and IrDA support + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) + +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) + +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) + +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - Global */ +/*! @{ */ + +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - Pin Configuration */ +/*! @{ */ + +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger disabled + * 0b01..Input trigger used instead of the RXD pin input + * 0b10..Input trigger used instead of the CTS_B pin input + * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - Baud Rate */ +/*! @{ */ + +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +/*! SBR - Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) + +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit + * 0b1..Two stop bits + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) + +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) + +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) + +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) + +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Rising edge + * 0b1..Both rising and falling edges + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) + +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address match wake-up + * 0b01..Idle match wake-up + * 0b10..Match on and match off + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) + +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) + +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) + +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) + +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Results in an OSR of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) + * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) + * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) + * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) + * 0b00111..Results in an OSR of 8 + * 0b01000..Results in an OSR of 9 + * 0b01001..Results in an OSR of 10 + * 0b01010..Results in an OSR of 11 + * 0b01011..Results in an OSR of 12 + * 0b01100..Results in an OSR of 13 + * 0b01101..Results in an OSR of 14 + * 0b01110..Results in an OSR of 15 + * 0b01111..Results in an OSR of 16 + * 0b10000..Results in an OSR of 17 + * 0b10001..Results in an OSR of 18 + * 0b10010..Results in an OSR of 19 + * 0b10011..Results in an OSR of 20 + * 0b10100..Results in an OSR of 21 + * 0b10101..Results in an OSR of 22 + * 0b10110..Results in an OSR of 23 + * 0b10111..Results in an OSR of 24 + * 0b11000..Results in an OSR of 25 + * 0b11001..Results in an OSR of 26 + * 0b11010..Results in an OSR of 27 + * 0b11011..Results in an OSR of 28 + * 0b11100..Results in an OSR of 29 + * 0b11101..Results in an OSR of 30 + * 0b11110..Results in an OSR of 31 + * 0b11111..Results in an OSR of 32 + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) + +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-Bit Mode Select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters + * 0b1..Receiver and transmitter use 10-bit data characters + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) + +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) + +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define LPUART_STAT_LBKFE_MASK (0x1U) +#define LPUART_STAT_LBKFE_SHIFT (0U) +/*! LBKFE - LIN Break Flag Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) + +#define LPUART_STAT_AME_MASK (0x2U) +#define LPUART_STAT_AME_SHIFT (1U) +/*! AME - Address Mark Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) + +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..No effect + * 0b0..Not equal to MA2 + * 0b1..Clear the flag + * 0b1..Equal to MA2 + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) + +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..No effect + * 0b0..Not equal to MA1 + * 0b1..Clear the flag + * 0b1..Equal to MA1 + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) + +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No effect + * 0b0..No parity error detected + * 0b1..Clear the flag + * 0b1..Parity error detected + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) + +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No effect + * 0b0..No framing error detected (this does not guarantee that the framing is correct) + * 0b1..Clear the flag + * 0b1..Framing error detected + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) + +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No effect + * 0b0..No noise detected + * 0b1..Clear the flag + * 0b1..Noise detected + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) + +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No effect + * 0b0..No overrun + * 0b1..Clear the flag + * 0b1..Receive overrun (new LPUART data is lost) + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) + +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..Idle line detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Idle line not detected + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) + +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Equal to or less than watermark + * 0b1..Greater than watermark + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) + +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active + * 0b1..Transmitter idle + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) + +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Greater than watermark + * 0b1..Equal to or less than watermark + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) + +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..Idle, waiting for a start bit + * 0b1..Receiver active (RXD pin input not idle) + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) + +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) + +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..9 to 13 bit times + * 0b1..12 to 15 bit times + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) + +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..STAT[IDLE] does not become 1 + * 0b1..STAT[IDLE] becomes 1 + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) + +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Inverted + * 0b1..Not inverted + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) + +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) + +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..No effect + * 0b0..Not occurred + * 0b1..Clear the flag + * 0b1..Occurred + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) + +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity + * 0b1..Odd parity + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) + +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) + +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..After the start bit + * 0b1..After the stop bit + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) + +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) + +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit Or 8-Bit Mode Select + * 0b0..8-bit + * 0b1..9-bit + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) + +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Internal Loopback mode + * 0b1..Single-wire mode + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) + +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) + +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation: RXD and TXD use separate pins + * 0b1..Loop mode or Single-Wire mode + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) + +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) + +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..8-bit to 10-bit + * 0b1..7-bit + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) + +#define LPUART_CTRL_SWAP_MASK (0x1000U) +#define LPUART_CTRL_SWAP_SHIFT (12U) +/*! SWAP - TXD and RXD Pin Swap + * 0b0..Use the standard way + * 0b1..Swap + */ +#define LPUART_CTRL_SWAP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SWAP_SHIFT)) & LPUART_CTRL_SWAP_MASK) + +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 (MA2F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) + +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 (MA1F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) + +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation + * 0b1..Queue break character(s) to be sent + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) + +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wake-Up Control + * 0b0..Normal receiver operation + * 0b1..LPUART receiver in standby, waiting for a wake-up condition + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) + +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) + +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) + +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) + +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) + +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) + +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) + +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) + +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) + +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) + +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) + +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Not inverted + * 0b1..Inverted + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) + +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..Input + * 0b1..Output + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) + +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +/*! R9T8 - Receive Bit 9 Transmit Bit 8 */ +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) + +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +/*! R8T9 - Receive Bit 8 Transmit Bit 9 */ +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) + +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) + +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) + +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) + +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) + +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) + +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) + +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) + +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) + +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) + +#define LPUART_DATA_LINBRK_MASK (0x400U) +#define LPUART_DATA_LINBRK_SHIFT (10U) +/*! LINBRK - LIN Break + * 0b0..Not detected + * 0b1..Detected + */ +#define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) + +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Not idle + * 0b1..Idle + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) + +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Valid data + * 0b1..Invalid data and empty + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) + +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error Transmit Special Character + * 0b0..Received without a frame error on reads or transmits a normal character on writes + * 0b1..Received with a frame error on reads or transmits an idle or break character on writes + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) + +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - Parity Error + * 0b0..Received without a parity error + * 0b1..Received with a parity error + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) + +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - Noisy Data Received + * 0b0..Received without noise + * 0b1..Received with noise + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - Match Address */ +/*! @{ */ + +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +/*! MA1 - Match Address 1 */ +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) + +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +/*! MA2 - Match Address 2 */ +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - MODEM IrDA */ +/*! @{ */ + +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter CTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) + +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) + +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter RTS Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) + +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) + +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..Sampled at the start of each character + * 0b1..Sampled when the transmitter is idle + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) + +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..The CTS_B pin + * 0b1..An internal connection to the receiver address match result + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) + +#define LPUART_MODIR_RTSWATER_MASK (0x300U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +/*! RTSWATER - Receive RTS Configuration */ +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) + +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter Narrow Pulse + * 0b00..1 / OSR + * 0b01..2 / OSR + * 0b10..3 / OSR + * 0b11..4 / OSR + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) + +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - IR Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - FIFO */ +/*! @{ */ + +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) + +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) + +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) + +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) + +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) + +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) + +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) + +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) + +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) + +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver FIFO Underflow Flag + * 0b0..No effect + * 0b0..No underflow + * 0b1..Clear the flag + * 0b1..Underflow + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) + +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter FIFO Overflow Flag + * 0b0..No effect + * 0b0..No overflow + * 0b1..Clear the flag + * 0b1..Overflow + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) + +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) + +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - Watermark */ +/*! @{ */ + +#define LPUART_WATER_TXWATER_MASK (0x3U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit Watermark */ +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) + +#define LPUART_WATER_TXCOUNT_MASK (0x700U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +/*! TXCOUNT - Transmit Counter */ +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) + +#define LPUART_WATER_RXWATER_MASK (0x30000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +/*! RXWATER - Receive Watermark */ +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) + +#define LPUART_WATER_RXCOUNT_MASK (0x7000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Counter */ +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + +/*! @name DATARO - Data Read-Only */ +/*! @{ */ + +#define LPUART_DATARO_DATA_MASK (0xFFFFU) +#define LPUART_DATARO_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_LPUART_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_MRCC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_MRCC.h new file mode 100644 index 000000000..17d9254e9 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_MRCC.h @@ -0,0 +1,3710 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for MRCC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_MRCC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for MRCC + * + * CMSIS Peripheral Access Layer for MRCC + */ + +#if !defined(PERI_MRCC_H_) +#define PERI_MRCC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- MRCC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRCC_Peripheral_Access_Layer MRCC Peripheral Access Layer + * @{ + */ + +/** MRCC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MRCC_GLB_RST0; /**< Peripheral Reset Control 0, offset: 0x0 */ + __O uint32_t MRCC_GLB_RST0_SET; /**< Peripheral Reset Control Set 0, offset: 0x4 */ + __O uint32_t MRCC_GLB_RST0_CLR; /**< Peripheral Reset Control Clear 0, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t MRCC_GLB_RST1; /**< Peripheral Reset Control 1, offset: 0x10 */ + __O uint32_t MRCC_GLB_RST1_SET; /**< Peripheral Reset Control Set 1, offset: 0x14 */ + __O uint32_t MRCC_GLB_RST1_CLR; /**< Peripheral Reset Control Clear 1, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MRCC_GLB_RST2; /**< Peripheral Reset Control 2, offset: 0x20 */ + __O uint32_t MRCC_GLB_RST2_SET; /**< Peripheral Reset Control Set 2, offset: 0x24 */ + __O uint32_t MRCC_GLB_RST2_CLR; /**< Peripheral Reset Control Clear 2, offset: 0x28 */ + uint8_t RESERVED_2[20]; + __IO uint32_t MRCC_GLB_CC0; /**< AHB Clock Control 0, offset: 0x40 */ + __O uint32_t MRCC_GLB_CC0_SET; /**< AHB Clock Control Set 0, offset: 0x44 */ + __O uint32_t MRCC_GLB_CC0_CLR; /**< AHB Clock Control Clear 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MRCC_GLB_CC1; /**< AHB Clock Control 1, offset: 0x50 */ + __O uint32_t MRCC_GLB_CC1_SET; /**< AHB Clock Control Set 1, offset: 0x54 */ + __O uint32_t MRCC_GLB_CC1_CLR; /**< AHB Clock Control Clear 1, offset: 0x58 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MRCC_GLB_CC2; /**< AHB Clock Control 2, offset: 0x60 */ + __O uint32_t MRCC_GLB_CC2_SET; /**< AHB Clock Control Set 2, offset: 0x64 */ + __O uint32_t MRCC_GLB_CC2_CLR; /**< AHB Clock Control Clear 2, offset: 0x68 */ + uint8_t RESERVED_5[20]; + __IO uint32_t MRCC_GLB_ACC0; /**< Control Automatic Clock Gating 0, offset: 0x80 */ + __IO uint32_t MRCC_GLB_ACC1; /**< Control Automatic Clock Gating 1, offset: 0x84 */ + __IO uint32_t MRCC_GLB_ACC2; /**< Control Automatic Clock Gating 2, offset: 0x88 */ + uint8_t RESERVED_6[20]; + __IO uint32_t MRCC_I3C0_FCLK_CLKSEL; /**< I3C0_FCLK clock selection control, offset: 0xA0 */ + __IO uint32_t MRCC_I3C0_FCLK_CLKDIV; /**< I3C0_FCLK clock divider control, offset: 0xA4 */ + __IO uint32_t MRCC_CTIMER0_CLKSEL; /**< CTIMER0 clock selection control, offset: 0xA8 */ + __IO uint32_t MRCC_CTIMER0_CLKDIV; /**< CTIMER0 clock divider control, offset: 0xAC */ + __IO uint32_t MRCC_CTIMER1_CLKSEL; /**< CTIMER1 clock selection control, offset: 0xB0 */ + __IO uint32_t MRCC_CTIMER1_CLKDIV; /**< CTIMER1 clock divider control, offset: 0xB4 */ + __IO uint32_t MRCC_CTIMER2_CLKSEL; /**< CTIMER2 clock selection control, offset: 0xB8 */ + __IO uint32_t MRCC_CTIMER2_CLKDIV; /**< CTIMER2 clock divider control, offset: 0xBC */ + __IO uint32_t MRCC_CTIMER3_CLKSEL; /**< CTIMER3 clock selection control, offset: 0xC0 */ + __IO uint32_t MRCC_CTIMER3_CLKDIV; /**< CTIMER3 clock divider control, offset: 0xC4 */ + __IO uint32_t MRCC_CTIMER4_CLKSEL; /**< CTIMER4 clock selection control, offset: 0xC8 */ + __IO uint32_t MRCC_CTIMER4_CLKDIV; /**< CTIMER4 clock divider control, offset: 0xCC */ + uint8_t RESERVED_7[4]; + __IO uint32_t MRCC_WWDT0_CLKDIV; /**< WWDT0 clock divider control, offset: 0xD4 */ + __IO uint32_t MRCC_FLEXIO0_CLKSEL; /**< FLEXIO0 clock selection control, offset: 0xD8 */ + __IO uint32_t MRCC_FLEXIO0_CLKDIV; /**< FLEXIO0 clock divider control, offset: 0xDC */ + __IO uint32_t MRCC_LPI2C0_CLKSEL; /**< LPI2C0 clock selection control, offset: 0xE0 */ + __IO uint32_t MRCC_LPI2C0_CLKDIV; /**< LPI2C0 clock divider control, offset: 0xE4 */ + __IO uint32_t MRCC_LPI2C1_CLKSEL; /**< LPI2C1 clock selection control, offset: 0xE8 */ + __IO uint32_t MRCC_LPI2C1_CLKDIV; /**< LPI2C1 clock divider control, offset: 0xEC */ + __IO uint32_t MRCC_LPSPI0_CLKSEL; /**< LPSPI0 clock selection control, offset: 0xF0 */ + __IO uint32_t MRCC_LPSPI0_CLKDIV; /**< LPSPI0 clock divider control, offset: 0xF4 */ + __IO uint32_t MRCC_LPSPI1_CLKSEL; /**< LPSPI1 clock selection control, offset: 0xF8 */ + __IO uint32_t MRCC_LPSPI1_CLKDIV; /**< LPSPI1 clock divider control, offset: 0xFC */ + __IO uint32_t MRCC_LPUART0_CLKSEL; /**< LPUART0 clock selection control, offset: 0x100 */ + __IO uint32_t MRCC_LPUART0_CLKDIV; /**< LPUART0 clock divider control, offset: 0x104 */ + __IO uint32_t MRCC_LPUART1_CLKSEL; /**< LPUART1 clock selection control, offset: 0x108 */ + __IO uint32_t MRCC_LPUART1_CLKDIV; /**< LPUART1 clock divider control, offset: 0x10C */ + __IO uint32_t MRCC_LPUART2_CLKSEL; /**< LPUART2 clock selection control, offset: 0x110 */ + __IO uint32_t MRCC_LPUART2_CLKDIV; /**< LPUART2 clock divider control, offset: 0x114 */ + __IO uint32_t MRCC_LPUART3_CLKSEL; /**< LPUART3 clock selection control, offset: 0x118 */ + __IO uint32_t MRCC_LPUART3_CLKDIV; /**< LPUART3 clock divider control, offset: 0x11C */ + __IO uint32_t MRCC_LPUART4_CLKSEL; /**< LPUART4 clock selection control, offset: 0x120 */ + __IO uint32_t MRCC_LPUART4_CLKDIV; /**< LPUART4 clock divider control, offset: 0x124 */ + __IO uint32_t MRCC_USB0_CLKSEL; /**< USB0 clock selection control, offset: 0x128 */ + __IO uint32_t MRCC_USB0_CLKDIV; /**< USB0 clock divider control, offset: 0x12C */ + __IO uint32_t MRCC_LPTMR0_CLKSEL; /**< LPTMR0 clock selection control, offset: 0x130 */ + __IO uint32_t MRCC_LPTMR0_CLKDIV; /**< LPTMR0 clock divider control, offset: 0x134 */ + __IO uint32_t MRCC_OSTIMER0_CLKSEL; /**< OSTIMER0 clock selection control, offset: 0x138 */ + uint8_t RESERVED_8[4]; + __IO uint32_t MRCC_ADC_CLKSEL; /**< ADCx clock selection control, offset: 0x140 */ + __IO uint32_t MRCC_ADC_CLKDIV; /**< ADCx clock divider control, offset: 0x144 */ + uint8_t RESERVED_9[4]; + __IO uint32_t MRCC_CMP0_FUNC_CLKDIV; /**< CMP0_FUNC clock divider control, offset: 0x14C */ + __IO uint32_t MRCC_CMP0_RR_CLKSEL; /**< CMP0_RR clock selection control, offset: 0x150 */ + __IO uint32_t MRCC_CMP0_RR_CLKDIV; /**< CMP0_RR clock divider control, offset: 0x154 */ + uint8_t RESERVED_10[4]; + __IO uint32_t MRCC_CMP1_FUNC_CLKDIV; /**< CMP1_FUNC clock divider control, offset: 0x15C */ + __IO uint32_t MRCC_CMP1_RR_CLKSEL; /**< CMP1_RR clock selection control, offset: 0x160 */ + __IO uint32_t MRCC_CMP1_RR_CLKDIV; /**< CMP1_RR clock divider control, offset: 0x164 */ + uint8_t RESERVED_11[4]; + __IO uint32_t MRCC_CMP2_FUNC_CLKDIV; /**< CMP2_FUNC clock divider control, offset: 0x16C */ + __IO uint32_t MRCC_CMP2_RR_CLKSEL; /**< CMP2_RR clock selection control, offset: 0x170 */ + __IO uint32_t MRCC_CMP2_RR_CLKDIV; /**< CMP2_RR clock divider control, offset: 0x174 */ + __IO uint32_t MRCC_DAC0_CLKSEL; /**< DAC0 clock selection control, offset: 0x178 */ + __IO uint32_t MRCC_DAC0_CLKDIV; /**< DAC0 clock divider control, offset: 0x17C */ + __IO uint32_t MRCC_FLEXCAN0_CLKSEL; /**< FLEXCAN0 clock selection control, offset: 0x180 */ + __IO uint32_t MRCC_FLEXCAN0_CLKDIV; /**< FLEXCAN0 clock divider control, offset: 0x184 */ + __IO uint32_t MRCC_FLEXCAN1_CLKSEL; /**< FLEXCAN1 clock selection control, offset: 0x188 */ + __IO uint32_t MRCC_FLEXCAN1_CLKDIV; /**< FLEXCAN1 clock divider control, offset: 0x18C */ + __IO uint32_t MRCC_LPI2C2_CLKSEL; /**< LPI2C2 clock selection control, offset: 0x190 */ + __IO uint32_t MRCC_LPI2C2_CLKDIV; /**< LPI2C2 clock divider control, offset: 0x194 */ + __IO uint32_t MRCC_LPI2C3_CLKSEL; /**< LPI2C3 clock selection control, offset: 0x198 */ + __IO uint32_t MRCC_LPI2C3_CLKDIV; /**< LPI2C3 clock divider control, offset: 0x19C */ + __IO uint32_t MRCC_LPUART5_CLKSEL; /**< LPUART5 clock selection control, offset: 0x1A0 */ + __IO uint32_t MRCC_LPUART5_CLKDIV; /**< LPUART5 clock divider control, offset: 0x1A4 */ + __IO uint32_t MRCC_DBG_TRACE_CLKSEL; /**< DBG_TRACE clock selection control, offset: 0x1A8 */ + __IO uint32_t MRCC_DBG_TRACE_CLKDIV; /**< DBG_TRACE clock divider control, offset: 0x1AC */ + __IO uint32_t MRCC_CLKOUT_CLKSEL; /**< CLKOUT clock selection control, offset: 0x1B0 */ + __IO uint32_t MRCC_CLKOUT_CLKDIV; /**< CLKOUT clock divider control, offset: 0x1B4 */ + __IO uint32_t MRCC_SYSTICK_CLKSEL; /**< SYSTICK clock selection control, offset: 0x1B8 */ + __IO uint32_t MRCC_SYSTICK_CLKDIV; /**< SYSTICK clock divider control, offset: 0x1BC */ +} MRCC_Type; + +/* ---------------------------------------------------------------------------- + -- MRCC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRCC_Register_Masks MRCC Register Masks + * @{ + */ + +/*! @name MRCC_GLB_RST0 - Peripheral Reset Control 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK (0x1U) +#define MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT (0U) +/*! INPUTMUX0 - INPUTMUX0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK) + +#define MRCC_MRCC_GLB_RST0_I3C0_MASK (0x2U) +#define MRCC_MRCC_GLB_RST0_I3C0_SHIFT (1U) +/*! I3C0 - I3C0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_I3C0_SHIFT)) & MRCC_MRCC_GLB_RST0_I3C0_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER0_MASK (0x4U) +#define MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT (2U) +/*! CTIMER0 - CTIMER0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER0_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER1_MASK (0x8U) +#define MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT (3U) +/*! CTIMER1 - CTIMER1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER1_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER2_MASK (0x10U) +#define MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER2_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER3_MASK (0x20U) +#define MRCC_MRCC_GLB_RST0_CTIMER3_SHIFT (5U) +/*! CTIMER3 - CTIMER3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER3_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER3_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER4_MASK (0x40U) +#define MRCC_MRCC_GLB_RST0_CTIMER4_SHIFT (6U) +/*! CTIMER4 - CTIMER4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER4_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER4_MASK) + +#define MRCC_MRCC_GLB_RST0_FREQME_MASK (0x80U) +#define MRCC_MRCC_GLB_RST0_FREQME_SHIFT (7U) +/*! FREQME - FREQME + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FREQME_SHIFT)) & MRCC_MRCC_GLB_RST0_FREQME_MASK) + +#define MRCC_MRCC_GLB_RST0_UTICK0_MASK (0x100U) +#define MRCC_MRCC_GLB_RST0_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_RST0_UTICK0_MASK) + +#define MRCC_MRCC_GLB_RST0_SMARTDMA0_MASK (0x400U) +#define MRCC_MRCC_GLB_RST0_SMARTDMA0_SHIFT (10U) +/*! SMARTDMA0 - SMARTDMA0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_SMARTDMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_SMARTDMA0_SHIFT)) & MRCC_MRCC_GLB_RST0_SMARTDMA0_MASK) + +#define MRCC_MRCC_GLB_RST0_DMA0_MASK (0x800U) +#define MRCC_MRCC_GLB_RST0_DMA0_SHIFT (11U) +/*! DMA0 - DMA0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_DMA0_SHIFT)) & MRCC_MRCC_GLB_RST0_DMA0_MASK) + +#define MRCC_MRCC_GLB_RST0_AOI0_MASK (0x1000U) +#define MRCC_MRCC_GLB_RST0_AOI0_SHIFT (12U) +/*! AOI0 - AOI0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_AOI0_SHIFT)) & MRCC_MRCC_GLB_RST0_AOI0_MASK) + +#define MRCC_MRCC_GLB_RST0_CRC0_MASK (0x2000U) +#define MRCC_MRCC_GLB_RST0_CRC0_SHIFT (13U) +/*! CRC0 - CRC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CRC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CRC0_SHIFT)) & MRCC_MRCC_GLB_RST0_CRC0_MASK) + +#define MRCC_MRCC_GLB_RST0_EIM0_MASK (0x4000U) +#define MRCC_MRCC_GLB_RST0_EIM0_SHIFT (14U) +/*! EIM0 - EIM0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_EIM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_EIM0_SHIFT)) & MRCC_MRCC_GLB_RST0_EIM0_MASK) + +#define MRCC_MRCC_GLB_RST0_ERM0_MASK (0x8000U) +#define MRCC_MRCC_GLB_RST0_ERM0_SHIFT (15U) +/*! ERM0 - ERM0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_ERM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_ERM0_SHIFT)) & MRCC_MRCC_GLB_RST0_ERM0_MASK) + +#define MRCC_MRCC_GLB_RST0_AOI1_MASK (0x20000U) +#define MRCC_MRCC_GLB_RST0_AOI1_SHIFT (17U) +/*! AOI1 - AOI1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_AOI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_AOI1_SHIFT)) & MRCC_MRCC_GLB_RST0_AOI1_MASK) + +#define MRCC_MRCC_GLB_RST0_FLEXIO0_MASK (0x40000U) +#define MRCC_MRCC_GLB_RST0_FLEXIO0_SHIFT (18U) +/*! FLEXIO0 - FLEXIO0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_FLEXIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FLEXIO0_SHIFT)) & MRCC_MRCC_GLB_RST0_FLEXIO0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPI2C0_MASK (0x80000U) +#define MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT (19U) +/*! LPI2C0 - LPI2C0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPI2C0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPI2C1_MASK (0x100000U) +#define MRCC_MRCC_GLB_RST0_LPI2C1_SHIFT (20U) +/*! LPI2C1 - LPI2C1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPI2C1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPSPI0_MASK (0x200000U) +#define MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT (21U) +/*! LPSPI0 - LPSPI0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPSPI1_MASK (0x400000U) +#define MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT (22U) +/*! LPSPI1 - LPSPI1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART0_MASK (0x800000U) +#define MRCC_MRCC_GLB_RST0_LPUART0_SHIFT (23U) +/*! LPUART0 - LPUART0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART1_MASK (0x1000000U) +#define MRCC_MRCC_GLB_RST0_LPUART1_SHIFT (24U) +/*! LPUART1 - LPUART1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART2_MASK (0x2000000U) +#define MRCC_MRCC_GLB_RST0_LPUART2_SHIFT (25U) +/*! LPUART2 - LPUART2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART2_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART3_MASK (0x4000000U) +#define MRCC_MRCC_GLB_RST0_LPUART3_SHIFT (26U) +/*! LPUART3 - LPUART3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART3_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART4_MASK (0x8000000U) +#define MRCC_MRCC_GLB_RST0_LPUART4_SHIFT (27U) +/*! LPUART4 - LPUART4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART4_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART4_MASK) + +#define MRCC_MRCC_GLB_RST0_USB0_MASK (0x10000000U) +#define MRCC_MRCC_GLB_RST0_USB0_SHIFT (28U) +/*! USB0 - USB0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_USB0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_USB0_SHIFT)) & MRCC_MRCC_GLB_RST0_USB0_MASK) + +#define MRCC_MRCC_GLB_RST0_QDC0_MASK (0x20000000U) +#define MRCC_MRCC_GLB_RST0_QDC0_SHIFT (29U) +/*! QDC0 - QDC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_QDC0_SHIFT)) & MRCC_MRCC_GLB_RST0_QDC0_MASK) + +#define MRCC_MRCC_GLB_RST0_QDC1_MASK (0x40000000U) +#define MRCC_MRCC_GLB_RST0_QDC1_SHIFT (30U) +/*! QDC1 - QDC1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_QDC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_QDC1_SHIFT)) & MRCC_MRCC_GLB_RST0_QDC1_MASK) + +#define MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK (0x80000000U) +#define MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT (31U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST0_SET - Peripheral Reset Control Set 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST0_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST0_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST0_CLR - Peripheral Reset Control Clear 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST0_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST0_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST1 - Peripheral Reset Control 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST1_FLEXPWM1_MASK (0x1U) +#define MRCC_MRCC_GLB_RST1_FLEXPWM1_SHIFT (0U) +/*! FLEXPWM1 - FLEXPWM1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_RST1_FLEXPWM1_MASK) + +#define MRCC_MRCC_GLB_RST1_OSTIMER0_MASK (0x2U) +#define MRCC_MRCC_GLB_RST1_OSTIMER0_SHIFT (1U) +/*! OSTIMER0 - OSTIMER0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST1_OSTIMER0_MASK) + +#define MRCC_MRCC_GLB_RST1_ADC0_MASK (0x4U) +#define MRCC_MRCC_GLB_RST1_ADC0_SHIFT (2U) +/*! ADC0 - ADC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC0_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC0_MASK) + +#define MRCC_MRCC_GLB_RST1_ADC1_MASK (0x8U) +#define MRCC_MRCC_GLB_RST1_ADC1_SHIFT (3U) +/*! ADC1 - ADC1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC1_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC1_MASK) + +#define MRCC_MRCC_GLB_RST1_CMP1_MASK (0x20U) +#define MRCC_MRCC_GLB_RST1_CMP1_SHIFT (5U) +/*! CMP1 - CMP1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CMP1_SHIFT)) & MRCC_MRCC_GLB_RST1_CMP1_MASK) + +#define MRCC_MRCC_GLB_RST1_CMP2_MASK (0x40U) +#define MRCC_MRCC_GLB_RST1_CMP2_SHIFT (6U) +/*! CMP2 - CMP2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_CMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CMP2_SHIFT)) & MRCC_MRCC_GLB_RST1_CMP2_MASK) + +#define MRCC_MRCC_GLB_RST1_DAC0_MASK (0x80U) +#define MRCC_MRCC_GLB_RST1_DAC0_SHIFT (7U) +/*! DAC0 - DAC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_DAC0_SHIFT)) & MRCC_MRCC_GLB_RST1_DAC0_MASK) + +#define MRCC_MRCC_GLB_RST1_OPAMP0_MASK (0x100U) +#define MRCC_MRCC_GLB_RST1_OPAMP0_SHIFT (8U) +/*! OPAMP0 - OPAMP0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP0_MASK) + +#define MRCC_MRCC_GLB_RST1_OPAMP1_MASK (0x200U) +#define MRCC_MRCC_GLB_RST1_OPAMP1_SHIFT (9U) +/*! OPAMP1 - OPAMP1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP1_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP1_MASK) + +#define MRCC_MRCC_GLB_RST1_OPAMP2_MASK (0x400U) +#define MRCC_MRCC_GLB_RST1_OPAMP2_SHIFT (10U) +/*! OPAMP2 - OPAMP2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP2_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP2_MASK) + +#define MRCC_MRCC_GLB_RST1_OPAMP3_MASK (0x800U) +#define MRCC_MRCC_GLB_RST1_OPAMP3_SHIFT (11U) +/*! OPAMP3 - OPAMP3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OPAMP3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP3_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP3_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT0_MASK (0x1000U) +#define MRCC_MRCC_GLB_RST1_PORT0_SHIFT (12U) +/*! PORT0 - PORT0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT0_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT0_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT1_MASK (0x2000U) +#define MRCC_MRCC_GLB_RST1_PORT1_SHIFT (13U) +/*! PORT1 - PORT1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT1_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT1_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT2_MASK (0x4000U) +#define MRCC_MRCC_GLB_RST1_PORT2_SHIFT (14U) +/*! PORT2 - PORT2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT2_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT2_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT3_MASK (0x8000U) +#define MRCC_MRCC_GLB_RST1_PORT3_SHIFT (15U) +/*! PORT3 - PORT3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT3_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT3_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT4_MASK (0x10000U) +#define MRCC_MRCC_GLB_RST1_PORT4_SHIFT (16U) +/*! PORT4 - PORT4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT4_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT4_MASK) + +#define MRCC_MRCC_GLB_RST1_SLCD0_MASK (0x20000U) +#define MRCC_MRCC_GLB_RST1_SLCD0_SHIFT (17U) +/*! SLCD0 - SLCD0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_SLCD0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_SLCD0_SHIFT)) & MRCC_MRCC_GLB_RST1_SLCD0_MASK) + +#define MRCC_MRCC_GLB_RST1_FLEXCAN0_MASK (0x40000U) +#define MRCC_MRCC_GLB_RST1_FLEXCAN0_SHIFT (18U) +/*! FLEXCAN0 - FLEXCAN0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_RST1_FLEXCAN0_MASK) + +#define MRCC_MRCC_GLB_RST1_FLEXCAN1_MASK (0x80000U) +#define MRCC_MRCC_GLB_RST1_FLEXCAN1_SHIFT (19U) +/*! FLEXCAN1 - FLEXCAN1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_FLEXCAN1_SHIFT)) & MRCC_MRCC_GLB_RST1_FLEXCAN1_MASK) + +#define MRCC_MRCC_GLB_RST1_LPI2C2_MASK (0x100000U) +#define MRCC_MRCC_GLB_RST1_LPI2C2_SHIFT (20U) +/*! LPI2C2 - LPI2C2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_LPI2C2_SHIFT)) & MRCC_MRCC_GLB_RST1_LPI2C2_MASK) + +#define MRCC_MRCC_GLB_RST1_LPI2C3_MASK (0x200000U) +#define MRCC_MRCC_GLB_RST1_LPI2C3_SHIFT (21U) +/*! LPI2C3 - LPI2C3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_LPI2C3_SHIFT)) & MRCC_MRCC_GLB_RST1_LPI2C3_MASK) + +#define MRCC_MRCC_GLB_RST1_LPUART5_MASK (0x400000U) +#define MRCC_MRCC_GLB_RST1_LPUART5_SHIFT (22U) +/*! LPUART5 - LPUART5 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_LPUART5(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_LPUART5_SHIFT)) & MRCC_MRCC_GLB_RST1_LPUART5_MASK) + +#define MRCC_MRCC_GLB_RST1_PKC0_MASK (0x1000000U) +#define MRCC_MRCC_GLB_RST1_PKC0_SHIFT (24U) +/*! PKC0 - PKC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PKC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PKC0_SHIFT)) & MRCC_MRCC_GLB_RST1_PKC0_MASK) + +#define MRCC_MRCC_GLB_RST1_TRNG0_MASK (0x4000000U) +#define MRCC_MRCC_GLB_RST1_TRNG0_SHIFT (26U) +/*! TRNG0 - TRNG0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_TRNG0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_TRNG0_SHIFT)) & MRCC_MRCC_GLB_RST1_TRNG0_MASK) + +#define MRCC_MRCC_GLB_RST1_ADC2_MASK (0x10000000U) +#define MRCC_MRCC_GLB_RST1_ADC2_SHIFT (28U) +/*! ADC2 - ADC2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_ADC2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC2_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC2_MASK) + +#define MRCC_MRCC_GLB_RST1_ADC3_MASK (0x20000000U) +#define MRCC_MRCC_GLB_RST1_ADC3_SHIFT (29U) +/*! ADC3 - ADC3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_ADC3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC3_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC3_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST1_SET - Peripheral Reset Control Set 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST1_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST1_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST1_CLR - Peripheral Reset Control Clear 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST1_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST1_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST2 - Peripheral Reset Control 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST2_GPIO0_MASK (0x10U) +#define MRCC_MRCC_GLB_RST2_GPIO0_SHIFT (4U) +/*! GPIO0 - GPIO0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO0_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO0_MASK) + +#define MRCC_MRCC_GLB_RST2_GPIO1_MASK (0x20U) +#define MRCC_MRCC_GLB_RST2_GPIO1_SHIFT (5U) +/*! GPIO1 - GPIO1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO1_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO1_MASK) + +#define MRCC_MRCC_GLB_RST2_GPIO2_MASK (0x40U) +#define MRCC_MRCC_GLB_RST2_GPIO2_SHIFT (6U) +/*! GPIO2 - GPIO2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO2_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO2_MASK) + +#define MRCC_MRCC_GLB_RST2_GPIO3_MASK (0x80U) +#define MRCC_MRCC_GLB_RST2_GPIO3_SHIFT (7U) +/*! GPIO3 - GPIO3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO3_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO3_MASK) + +#define MRCC_MRCC_GLB_RST2_GPIO4_MASK (0x100U) +#define MRCC_MRCC_GLB_RST2_GPIO4_SHIFT (8U) +/*! GPIO4 - GPIO4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_GPIO4_SHIFT)) & MRCC_MRCC_GLB_RST2_GPIO4_MASK) + +#define MRCC_MRCC_GLB_RST2_MAU0_MASK (0x200U) +#define MRCC_MRCC_GLB_RST2_MAU0_SHIFT (9U) +/*! MAU0 - MAU0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST2_MAU0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_MAU0_SHIFT)) & MRCC_MRCC_GLB_RST2_MAU0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST2_SET - Peripheral Reset Control Set 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST2_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST2_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST2_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST2_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST2_CLR - Peripheral Reset Control Clear 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST2_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST2_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST2_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST2_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST2_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC0 - AHB Clock Control 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK (0x1U) +#define MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT (0U) +/*! INPUTMUX0 - INPUTMUX0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK) + +#define MRCC_MRCC_GLB_CC0_I3C0_MASK (0x2U) +#define MRCC_MRCC_GLB_CC0_I3C0_SHIFT (1U) +/*! I3C0 - I3C0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_I3C0_SHIFT)) & MRCC_MRCC_GLB_CC0_I3C0_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER0_MASK (0x4U) +#define MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT (2U) +/*! CTIMER0 - CTIMER0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER0_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER1_MASK (0x8U) +#define MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT (3U) +/*! CTIMER1 - CTIMER1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER1_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER2_MASK (0x10U) +#define MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER2_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER3_MASK (0x20U) +#define MRCC_MRCC_GLB_CC0_CTIMER3_SHIFT (5U) +/*! CTIMER3 - CTIMER3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER3_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER3_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER4_MASK (0x40U) +#define MRCC_MRCC_GLB_CC0_CTIMER4_SHIFT (6U) +/*! CTIMER4 - CTIMER4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER4_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER4_MASK) + +#define MRCC_MRCC_GLB_CC0_FREQME_MASK (0x80U) +#define MRCC_MRCC_GLB_CC0_FREQME_SHIFT (7U) +/*! FREQME - FREQME + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_CC0_FREQME_MASK) + +#define MRCC_MRCC_GLB_CC0_UTICK0_MASK (0x100U) +#define MRCC_MRCC_GLB_CC0_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_CC0_UTICK0_MASK) + +#define MRCC_MRCC_GLB_CC0_WWDT0_MASK (0x200U) +#define MRCC_MRCC_GLB_CC0_WWDT0_SHIFT (9U) +/*! WWDT0 - WWDT0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_CC0_WWDT0_MASK) + +#define MRCC_MRCC_GLB_CC0_SMARTDMA0_MASK (0x400U) +#define MRCC_MRCC_GLB_CC0_SMARTDMA0_SHIFT (10U) +/*! SMARTDMA0 - SMARTDMA0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_SMARTDMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_SMARTDMA0_SHIFT)) & MRCC_MRCC_GLB_CC0_SMARTDMA0_MASK) + +#define MRCC_MRCC_GLB_CC0_DMA0_MASK (0x800U) +#define MRCC_MRCC_GLB_CC0_DMA0_SHIFT (11U) +/*! DMA0 - DMA0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_DMA0_SHIFT)) & MRCC_MRCC_GLB_CC0_DMA0_MASK) + +#define MRCC_MRCC_GLB_CC0_AOI0_MASK (0x1000U) +#define MRCC_MRCC_GLB_CC0_AOI0_SHIFT (12U) +/*! AOI0 - AOI0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_CC0_AOI0_MASK) + +#define MRCC_MRCC_GLB_CC0_CRC0_MASK (0x2000U) +#define MRCC_MRCC_GLB_CC0_CRC0_SHIFT (13U) +/*! CRC0 - CRC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CRC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CRC0_SHIFT)) & MRCC_MRCC_GLB_CC0_CRC0_MASK) + +#define MRCC_MRCC_GLB_CC0_EIM0_MASK (0x4000U) +#define MRCC_MRCC_GLB_CC0_EIM0_SHIFT (14U) +/*! EIM0 - EIM0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_EIM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_EIM0_SHIFT)) & MRCC_MRCC_GLB_CC0_EIM0_MASK) + +#define MRCC_MRCC_GLB_CC0_ERM0_MASK (0x8000U) +#define MRCC_MRCC_GLB_CC0_ERM0_SHIFT (15U) +/*! ERM0 - ERM0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_ERM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_ERM0_SHIFT)) & MRCC_MRCC_GLB_CC0_ERM0_MASK) + +#define MRCC_MRCC_GLB_CC0_AOI1_MASK (0x20000U) +#define MRCC_MRCC_GLB_CC0_AOI1_SHIFT (17U) +/*! AOI1 - AOI1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_AOI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_AOI1_SHIFT)) & MRCC_MRCC_GLB_CC0_AOI1_MASK) + +#define MRCC_MRCC_GLB_CC0_FLEXIO0_MASK (0x40000U) +#define MRCC_MRCC_GLB_CC0_FLEXIO0_SHIFT (18U) +/*! FLEXIO0 - FLEXIO0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FLEXIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FLEXIO0_SHIFT)) & MRCC_MRCC_GLB_CC0_FLEXIO0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPI2C0_MASK (0x80000U) +#define MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT (19U) +/*! LPI2C0 - LPI2C0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPI2C0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPI2C1_MASK (0x100000U) +#define MRCC_MRCC_GLB_CC0_LPI2C1_SHIFT (20U) +/*! LPI2C1 - LPI2C1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPI2C1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPSPI0_MASK (0x200000U) +#define MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT (21U) +/*! LPSPI0 - LPSPI0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPSPI1_MASK (0x400000U) +#define MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT (22U) +/*! LPSPI1 - LPSPI1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART0_MASK (0x800000U) +#define MRCC_MRCC_GLB_CC0_LPUART0_SHIFT (23U) +/*! LPUART0 - LPUART0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART1_MASK (0x1000000U) +#define MRCC_MRCC_GLB_CC0_LPUART1_SHIFT (24U) +/*! LPUART1 - LPUART1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART2_MASK (0x2000000U) +#define MRCC_MRCC_GLB_CC0_LPUART2_SHIFT (25U) +/*! LPUART2 - LPUART2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART2_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART3_MASK (0x4000000U) +#define MRCC_MRCC_GLB_CC0_LPUART3_SHIFT (26U) +/*! LPUART3 - LPUART3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART3_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART4_MASK (0x8000000U) +#define MRCC_MRCC_GLB_CC0_LPUART4_SHIFT (27U) +/*! LPUART4 - LPUART4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART4_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART4_MASK) + +#define MRCC_MRCC_GLB_CC0_USB0_MASK (0x10000000U) +#define MRCC_MRCC_GLB_CC0_USB0_SHIFT (28U) +/*! USB0 - USB0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_USB0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_USB0_SHIFT)) & MRCC_MRCC_GLB_CC0_USB0_MASK) + +#define MRCC_MRCC_GLB_CC0_QDC0_MASK (0x20000000U) +#define MRCC_MRCC_GLB_CC0_QDC0_SHIFT (29U) +/*! QDC0 - QDC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_CC0_QDC0_MASK) + +#define MRCC_MRCC_GLB_CC0_QDC1_MASK (0x40000000U) +#define MRCC_MRCC_GLB_CC0_QDC1_SHIFT (30U) +/*! QDC1 - QDC1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_QDC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_QDC1_SHIFT)) & MRCC_MRCC_GLB_CC0_QDC1_MASK) + +#define MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK (0x80000000U) +#define MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT (31U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC0_SET - AHB Clock Control Set 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC0_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC0_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC0_CLR - AHB Clock Control Clear 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC0_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC0_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC1 - AHB Clock Control 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK (0x1U) +#define MRCC_MRCC_GLB_CC1_FLEXPWM1_SHIFT (0U) +/*! FLEXPWM1 - FLEXPWM1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_CC1_FLEXPWM1_MASK) + +#define MRCC_MRCC_GLB_CC1_OSTIMER0_MASK (0x2U) +#define MRCC_MRCC_GLB_CC1_OSTIMER0_SHIFT (1U) +/*! OSTIMER0 - OSTIMER0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC1_OSTIMER0_MASK) + +#define MRCC_MRCC_GLB_CC1_ADC0_MASK (0x4U) +#define MRCC_MRCC_GLB_CC1_ADC0_SHIFT (2U) +/*! ADC0 - ADC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC0_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC0_MASK) + +#define MRCC_MRCC_GLB_CC1_ADC1_MASK (0x8U) +#define MRCC_MRCC_GLB_CC1_ADC1_SHIFT (3U) +/*! ADC1 - ADC1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC1_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC1_MASK) + +#define MRCC_MRCC_GLB_CC1_CMP0_MASK (0x10U) +#define MRCC_MRCC_GLB_CC1_CMP0_SHIFT (4U) +/*! CMP0 - CMP0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP0_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP0_MASK) + +#define MRCC_MRCC_GLB_CC1_CMP1_MASK (0x20U) +#define MRCC_MRCC_GLB_CC1_CMP1_SHIFT (5U) +/*! CMP1 - CMP1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP1_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP1_MASK) + +#define MRCC_MRCC_GLB_CC1_CMP2_MASK (0x40U) +#define MRCC_MRCC_GLB_CC1_CMP2_SHIFT (6U) +/*! CMP2 - CMP2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_CMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP2_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP2_MASK) + +#define MRCC_MRCC_GLB_CC1_DAC0_MASK (0x80U) +#define MRCC_MRCC_GLB_CC1_DAC0_SHIFT (7U) +/*! DAC0 - DAC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_DAC0_SHIFT)) & MRCC_MRCC_GLB_CC1_DAC0_MASK) + +#define MRCC_MRCC_GLB_CC1_OPAMP0_MASK (0x100U) +#define MRCC_MRCC_GLB_CC1_OPAMP0_SHIFT (8U) +/*! OPAMP0 - OPAMP0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP0_MASK) + +#define MRCC_MRCC_GLB_CC1_OPAMP1_MASK (0x200U) +#define MRCC_MRCC_GLB_CC1_OPAMP1_SHIFT (9U) +/*! OPAMP1 - OPAMP1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP1_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP1_MASK) + +#define MRCC_MRCC_GLB_CC1_OPAMP2_MASK (0x400U) +#define MRCC_MRCC_GLB_CC1_OPAMP2_SHIFT (10U) +/*! OPAMP2 - OPAMP2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP2_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP2_MASK) + +#define MRCC_MRCC_GLB_CC1_OPAMP3_MASK (0x800U) +#define MRCC_MRCC_GLB_CC1_OPAMP3_SHIFT (11U) +/*! OPAMP3 - OPAMP3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OPAMP3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP3_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP3_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT0_MASK (0x1000U) +#define MRCC_MRCC_GLB_CC1_PORT0_SHIFT (12U) +/*! PORT0 - PORT0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT0_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT0_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT1_MASK (0x2000U) +#define MRCC_MRCC_GLB_CC1_PORT1_SHIFT (13U) +/*! PORT1 - PORT1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT1_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT1_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT2_MASK (0x4000U) +#define MRCC_MRCC_GLB_CC1_PORT2_SHIFT (14U) +/*! PORT2 - PORT2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT2_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT2_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT3_MASK (0x8000U) +#define MRCC_MRCC_GLB_CC1_PORT3_SHIFT (15U) +/*! PORT3 - PORT3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT3_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT4_MASK (0x10000U) +#define MRCC_MRCC_GLB_CC1_PORT4_SHIFT (16U) +/*! PORT4 - PORT4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT4_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT4_MASK) + +#define MRCC_MRCC_GLB_CC1_SLCD0_MASK (0x20000U) +#define MRCC_MRCC_GLB_CC1_SLCD0_SHIFT (17U) +/*! SLCD0 - SLCD0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_SLCD0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_SLCD0_SHIFT)) & MRCC_MRCC_GLB_CC1_SLCD0_MASK) + +#define MRCC_MRCC_GLB_CC1_FLEXCAN0_MASK (0x40000U) +#define MRCC_MRCC_GLB_CC1_FLEXCAN0_SHIFT (18U) +/*! FLEXCAN0 - FLEXCAN0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_CC1_FLEXCAN0_MASK) + +#define MRCC_MRCC_GLB_CC1_FLEXCAN1_MASK (0x80000U) +#define MRCC_MRCC_GLB_CC1_FLEXCAN1_SHIFT (19U) +/*! FLEXCAN1 - FLEXCAN1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_FLEXCAN1_SHIFT)) & MRCC_MRCC_GLB_CC1_FLEXCAN1_MASK) + +#define MRCC_MRCC_GLB_CC1_LPI2C2_MASK (0x100000U) +#define MRCC_MRCC_GLB_CC1_LPI2C2_SHIFT (20U) +/*! LPI2C2 - LPI2C2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_LPI2C2_SHIFT)) & MRCC_MRCC_GLB_CC1_LPI2C2_MASK) + +#define MRCC_MRCC_GLB_CC1_LPI2C3_MASK (0x200000U) +#define MRCC_MRCC_GLB_CC1_LPI2C3_SHIFT (21U) +/*! LPI2C3 - LPI2C3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_LPI2C3_SHIFT)) & MRCC_MRCC_GLB_CC1_LPI2C3_MASK) + +#define MRCC_MRCC_GLB_CC1_LPUART5_MASK (0x400000U) +#define MRCC_MRCC_GLB_CC1_LPUART5_SHIFT (22U) +/*! LPUART5 - LPUART5 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_LPUART5(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_LPUART5_SHIFT)) & MRCC_MRCC_GLB_CC1_LPUART5_MASK) + +#define MRCC_MRCC_GLB_CC1_TDET0_MASK (0x800000U) +#define MRCC_MRCC_GLB_CC1_TDET0_SHIFT (23U) +/*! TDET0 - TDET0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_TDET0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_TDET0_SHIFT)) & MRCC_MRCC_GLB_CC1_TDET0_MASK) + +#define MRCC_MRCC_GLB_CC1_PKC0_MASK (0x1000000U) +#define MRCC_MRCC_GLB_CC1_PKC0_SHIFT (24U) +/*! PKC0 - PKC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PKC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PKC0_SHIFT)) & MRCC_MRCC_GLB_CC1_PKC0_MASK) + +#define MRCC_MRCC_GLB_CC1_SGI0_MASK (0x2000000U) +#define MRCC_MRCC_GLB_CC1_SGI0_SHIFT (25U) +/*! SGI0 - SGI0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_SGI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_SGI0_SHIFT)) & MRCC_MRCC_GLB_CC1_SGI0_MASK) + +#define MRCC_MRCC_GLB_CC1_TRNG0_MASK (0x4000000U) +#define MRCC_MRCC_GLB_CC1_TRNG0_SHIFT (26U) +/*! TRNG0 - TRNG0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_TRNG0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_TRNG0_SHIFT)) & MRCC_MRCC_GLB_CC1_TRNG0_MASK) + +#define MRCC_MRCC_GLB_CC1_UDF0_MASK (0x8000000U) +#define MRCC_MRCC_GLB_CC1_UDF0_SHIFT (27U) +/*! UDF0 - UDF0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_UDF0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_UDF0_SHIFT)) & MRCC_MRCC_GLB_CC1_UDF0_MASK) + +#define MRCC_MRCC_GLB_CC1_ADC2_MASK (0x10000000U) +#define MRCC_MRCC_GLB_CC1_ADC2_SHIFT (28U) +/*! ADC2 - ADC2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_ADC2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC2_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC2_MASK) + +#define MRCC_MRCC_GLB_CC1_ADC3_MASK (0x20000000U) +#define MRCC_MRCC_GLB_CC1_ADC3_SHIFT (29U) +/*! ADC3 - ADC3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_ADC3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC3_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC3_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC1_SET - AHB Clock Control Set 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC1_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC1_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC1_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC1_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC1_CLR - AHB Clock Control Clear 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC1_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC1_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC1_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC1_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC2 - AHB Clock Control 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC2_RAMA_MASK (0x2U) +#define MRCC_MRCC_GLB_CC2_RAMA_SHIFT (1U) +/*! RAMA - RAMA + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_RAMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_RAMA_SHIFT)) & MRCC_MRCC_GLB_CC2_RAMA_MASK) + +#define MRCC_MRCC_GLB_CC2_RAMB_MASK (0x4U) +#define MRCC_MRCC_GLB_CC2_RAMB_SHIFT (2U) +/*! RAMB - RAMB + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_RAMB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_RAMB_SHIFT)) & MRCC_MRCC_GLB_CC2_RAMB_MASK) + +#define MRCC_MRCC_GLB_CC2_RAMC_MASK (0x8U) +#define MRCC_MRCC_GLB_CC2_RAMC_SHIFT (3U) +/*! RAMC - RAMC + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_RAMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_RAMC_SHIFT)) & MRCC_MRCC_GLB_CC2_RAMC_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO0_MASK (0x10U) +#define MRCC_MRCC_GLB_CC2_GPIO0_SHIFT (4U) +/*! GPIO0 - GPIO0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO0_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO0_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO1_MASK (0x20U) +#define MRCC_MRCC_GLB_CC2_GPIO1_SHIFT (5U) +/*! GPIO1 - GPIO1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO1_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO1_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO2_MASK (0x40U) +#define MRCC_MRCC_GLB_CC2_GPIO2_SHIFT (6U) +/*! GPIO2 - GPIO2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO2_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO2_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO3_MASK (0x80U) +#define MRCC_MRCC_GLB_CC2_GPIO3_SHIFT (7U) +/*! GPIO3 - GPIO3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO3_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO3_MASK) + +#define MRCC_MRCC_GLB_CC2_GPIO4_MASK (0x100U) +#define MRCC_MRCC_GLB_CC2_GPIO4_SHIFT (8U) +/*! GPIO4 - GPIO4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_GPIO4_SHIFT)) & MRCC_MRCC_GLB_CC2_GPIO4_MASK) + +#define MRCC_MRCC_GLB_CC2_MAU0_MASK (0x200U) +#define MRCC_MRCC_GLB_CC2_MAU0_SHIFT (9U) +/*! MAU0 - MAU0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_MAU0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_MAU0_SHIFT)) & MRCC_MRCC_GLB_CC2_MAU0_MASK) + +#define MRCC_MRCC_GLB_CC2_ROMC_MASK (0x400U) +#define MRCC_MRCC_GLB_CC2_ROMC_SHIFT (10U) +/*! ROMC - ROMC + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC2_ROMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_ROMC_SHIFT)) & MRCC_MRCC_GLB_CC2_ROMC_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC2_SET - AHB Clock Control Set 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC2_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC2_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC2_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC2_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC2_CLR - AHB Clock Control Clear 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC2_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC2_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC2_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC2_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC2_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_ACC0 - Control Automatic Clock Gating 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK (0x1U) +#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT (0U) +/*! INPUTMUX0 - INPUTMUX0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK) + +#define MRCC_MRCC_GLB_ACC0_I3C0_MASK (0x2U) +#define MRCC_MRCC_GLB_ACC0_I3C0_SHIFT (1U) +/*! I3C0 - I3C0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_I3C0_SHIFT)) & MRCC_MRCC_GLB_ACC0_I3C0_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER0_MASK (0x4U) +#define MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT (2U) +/*! CTIMER0 - CTIMER0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER0_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER1_MASK (0x8U) +#define MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT (3U) +/*! CTIMER1 - CTIMER1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER1_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER2_MASK (0x10U) +#define MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER2_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER3_MASK (0x20U) +#define MRCC_MRCC_GLB_ACC0_CTIMER3_SHIFT (5U) +/*! CTIMER3 - CTIMER3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER3_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER3_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER4_MASK (0x40U) +#define MRCC_MRCC_GLB_ACC0_CTIMER4_SHIFT (6U) +/*! CTIMER4 - CTIMER4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER4_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER4_MASK) + +#define MRCC_MRCC_GLB_ACC0_FREQME_MASK (0x80U) +#define MRCC_MRCC_GLB_ACC0_FREQME_SHIFT (7U) +/*! FREQME - FREQME + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_ACC0_FREQME_MASK) + +#define MRCC_MRCC_GLB_ACC0_UTICK0_MASK (0x100U) +#define MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_ACC0_UTICK0_MASK) + +#define MRCC_MRCC_GLB_ACC0_WWDT0_MASK (0x200U) +#define MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT (9U) +/*! WWDT0 - WWDT0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_ACC0_WWDT0_MASK) + +#define MRCC_MRCC_GLB_ACC0_SMARTDMA0_MASK (0x400U) +#define MRCC_MRCC_GLB_ACC0_SMARTDMA0_SHIFT (10U) +/*! SMARTDMA0 - SMARTDMA0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_SMARTDMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_SMARTDMA0_SHIFT)) & MRCC_MRCC_GLB_ACC0_SMARTDMA0_MASK) + +#define MRCC_MRCC_GLB_ACC0_DMA0_MASK (0x800U) +#define MRCC_MRCC_GLB_ACC0_DMA0_SHIFT (11U) +/*! DMA0 - DMA0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_DMA0_SHIFT)) & MRCC_MRCC_GLB_ACC0_DMA0_MASK) + +#define MRCC_MRCC_GLB_ACC0_AOI0_MASK (0x1000U) +#define MRCC_MRCC_GLB_ACC0_AOI0_SHIFT (12U) +/*! AOI0 - AOI0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_AOI0_MASK) + +#define MRCC_MRCC_GLB_ACC0_CRC0_MASK (0x2000U) +#define MRCC_MRCC_GLB_ACC0_CRC0_SHIFT (13U) +/*! CRC0 - CRC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CRC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CRC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CRC0_MASK) + +#define MRCC_MRCC_GLB_ACC0_EIM0_MASK (0x4000U) +#define MRCC_MRCC_GLB_ACC0_EIM0_SHIFT (14U) +/*! EIM0 - EIM0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_EIM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_EIM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_EIM0_MASK) + +#define MRCC_MRCC_GLB_ACC0_ERM0_MASK (0x8000U) +#define MRCC_MRCC_GLB_ACC0_ERM0_SHIFT (15U) +/*! ERM0 - ERM0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_ERM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_ERM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_ERM0_MASK) + +#define MRCC_MRCC_GLB_ACC0_AOI1_MASK (0x20000U) +#define MRCC_MRCC_GLB_ACC0_AOI1_SHIFT (17U) +/*! AOI1 - AOI1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_AOI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_AOI1_SHIFT)) & MRCC_MRCC_GLB_ACC0_AOI1_MASK) + +#define MRCC_MRCC_GLB_ACC0_FLEXIO0_MASK (0x40000U) +#define MRCC_MRCC_GLB_ACC0_FLEXIO0_SHIFT (18U) +/*! FLEXIO0 - FLEXIO0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FLEXIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FLEXIO0_SHIFT)) & MRCC_MRCC_GLB_ACC0_FLEXIO0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPI2C0_MASK (0x80000U) +#define MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT (19U) +/*! LPI2C0 - LPI2C0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPI2C0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPI2C1_MASK (0x100000U) +#define MRCC_MRCC_GLB_ACC0_LPI2C1_SHIFT (20U) +/*! LPI2C1 - LPI2C1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPI2C1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPSPI0_MASK (0x200000U) +#define MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT (21U) +/*! LPSPI0 - LPSPI0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPSPI1_MASK (0x400000U) +#define MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT (22U) +/*! LPSPI1 - LPSPI1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART0_MASK (0x800000U) +#define MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT (23U) +/*! LPUART0 - LPUART0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART1_MASK (0x1000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT (24U) +/*! LPUART1 - LPUART1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART2_MASK (0x2000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT (25U) +/*! LPUART2 - LPUART2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART2_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART3_MASK (0x4000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART3_SHIFT (26U) +/*! LPUART3 - LPUART3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART3_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART4_MASK (0x8000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART4_SHIFT (27U) +/*! LPUART4 - LPUART4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART4_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART4_MASK) + +#define MRCC_MRCC_GLB_ACC0_USB0_MASK (0x10000000U) +#define MRCC_MRCC_GLB_ACC0_USB0_SHIFT (28U) +/*! USB0 - USB0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_USB0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_USB0_SHIFT)) & MRCC_MRCC_GLB_ACC0_USB0_MASK) + +#define MRCC_MRCC_GLB_ACC0_QDC0_MASK (0x20000000U) +#define MRCC_MRCC_GLB_ACC0_QDC0_SHIFT (29U) +/*! QDC0 - QDC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_QDC0_MASK) + +#define MRCC_MRCC_GLB_ACC0_QDC1_MASK (0x40000000U) +#define MRCC_MRCC_GLB_ACC0_QDC1_SHIFT (30U) +/*! QDC1 - QDC1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_QDC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_QDC1_SHIFT)) & MRCC_MRCC_GLB_ACC0_QDC1_MASK) + +#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK (0x80000000U) +#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT (31U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK) +/*! @} */ + +/*! @name MRCC_GLB_ACC1 - Control Automatic Clock Gating 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_ACC1_FLEXPWM1_MASK (0x1U) +#define MRCC_MRCC_GLB_ACC1_FLEXPWM1_SHIFT (0U) +/*! FLEXPWM1 - FLEXPWM1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_ACC1_FLEXPWM1_MASK) + +#define MRCC_MRCC_GLB_ACC1_OSTIMER0_MASK (0x2U) +#define MRCC_MRCC_GLB_ACC1_OSTIMER0_SHIFT (1U) +/*! OSTIMER0 - OSTIMER0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC1_OSTIMER0_MASK) + +#define MRCC_MRCC_GLB_ACC1_ADC0_MASK (0x4U) +#define MRCC_MRCC_GLB_ACC1_ADC0_SHIFT (2U) +/*! ADC0 - ADC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC0_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC0_MASK) + +#define MRCC_MRCC_GLB_ACC1_ADC1_MASK (0x8U) +#define MRCC_MRCC_GLB_ACC1_ADC1_SHIFT (3U) +/*! ADC1 - ADC1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC1_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC1_MASK) + +#define MRCC_MRCC_GLB_ACC1_CMP0_MASK (0x10U) +#define MRCC_MRCC_GLB_ACC1_CMP0_SHIFT (4U) +/*! CMP0 - CMP0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP0_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP0_MASK) + +#define MRCC_MRCC_GLB_ACC1_CMP1_MASK (0x20U) +#define MRCC_MRCC_GLB_ACC1_CMP1_SHIFT (5U) +/*! CMP1 - CMP1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP1_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP1_MASK) + +#define MRCC_MRCC_GLB_ACC1_CMP2_MASK (0x40U) +#define MRCC_MRCC_GLB_ACC1_CMP2_SHIFT (6U) +/*! CMP2 - CMP2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_CMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP2_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP2_MASK) + +#define MRCC_MRCC_GLB_ACC1_DAC0_MASK (0x80U) +#define MRCC_MRCC_GLB_ACC1_DAC0_SHIFT (7U) +/*! DAC0 - DAC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_DAC0_SHIFT)) & MRCC_MRCC_GLB_ACC1_DAC0_MASK) + +#define MRCC_MRCC_GLB_ACC1_OPAMP0_MASK (0x100U) +#define MRCC_MRCC_GLB_ACC1_OPAMP0_SHIFT (8U) +/*! OPAMP0 - OPAMP0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP0_MASK) + +#define MRCC_MRCC_GLB_ACC1_OPAMP1_MASK (0x200U) +#define MRCC_MRCC_GLB_ACC1_OPAMP1_SHIFT (9U) +/*! OPAMP1 - OPAMP1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP1_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP1_MASK) + +#define MRCC_MRCC_GLB_ACC1_OPAMP2_MASK (0x400U) +#define MRCC_MRCC_GLB_ACC1_OPAMP2_SHIFT (10U) +/*! OPAMP2 - OPAMP2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP2_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP2_MASK) + +#define MRCC_MRCC_GLB_ACC1_OPAMP3_MASK (0x800U) +#define MRCC_MRCC_GLB_ACC1_OPAMP3_SHIFT (11U) +/*! OPAMP3 - OPAMP3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OPAMP3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP3_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP3_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT0_MASK (0x1000U) +#define MRCC_MRCC_GLB_ACC1_PORT0_SHIFT (12U) +/*! PORT0 - PORT0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT0_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT0_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT1_MASK (0x2000U) +#define MRCC_MRCC_GLB_ACC1_PORT1_SHIFT (13U) +/*! PORT1 - PORT1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT1_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT1_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT2_MASK (0x4000U) +#define MRCC_MRCC_GLB_ACC1_PORT2_SHIFT (14U) +/*! PORT2 - PORT2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT2_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT2_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT3_MASK (0x8000U) +#define MRCC_MRCC_GLB_ACC1_PORT3_SHIFT (15U) +/*! PORT3 - PORT3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT3_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT4_MASK (0x10000U) +#define MRCC_MRCC_GLB_ACC1_PORT4_SHIFT (16U) +/*! PORT4 - PORT4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT4_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT4_MASK) + +#define MRCC_MRCC_GLB_ACC1_SLCD0_MASK (0x20000U) +#define MRCC_MRCC_GLB_ACC1_SLCD0_SHIFT (17U) +/*! SLCD0 - SLCD0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_SLCD0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_SLCD0_SHIFT)) & MRCC_MRCC_GLB_ACC1_SLCD0_MASK) + +#define MRCC_MRCC_GLB_ACC1_FLEXCAN0_MASK (0x40000U) +#define MRCC_MRCC_GLB_ACC1_FLEXCAN0_SHIFT (18U) +/*! FLEXCAN0 - FLEXCAN0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_ACC1_FLEXCAN0_MASK) + +#define MRCC_MRCC_GLB_ACC1_FLEXCAN1_MASK (0x80000U) +#define MRCC_MRCC_GLB_ACC1_FLEXCAN1_SHIFT (19U) +/*! FLEXCAN1 - FLEXCAN1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_FLEXCAN1_SHIFT)) & MRCC_MRCC_GLB_ACC1_FLEXCAN1_MASK) + +#define MRCC_MRCC_GLB_ACC1_LPI2C2_MASK (0x100000U) +#define MRCC_MRCC_GLB_ACC1_LPI2C2_SHIFT (20U) +/*! LPI2C2 - LPI2C2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_LPI2C2_SHIFT)) & MRCC_MRCC_GLB_ACC1_LPI2C2_MASK) + +#define MRCC_MRCC_GLB_ACC1_LPI2C3_MASK (0x200000U) +#define MRCC_MRCC_GLB_ACC1_LPI2C3_SHIFT (21U) +/*! LPI2C3 - LPI2C3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_LPI2C3_SHIFT)) & MRCC_MRCC_GLB_ACC1_LPI2C3_MASK) + +#define MRCC_MRCC_GLB_ACC1_LPUART5_MASK (0x400000U) +#define MRCC_MRCC_GLB_ACC1_LPUART5_SHIFT (22U) +/*! LPUART5 - LPUART5 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_LPUART5(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_LPUART5_SHIFT)) & MRCC_MRCC_GLB_ACC1_LPUART5_MASK) + +#define MRCC_MRCC_GLB_ACC1_PKC0_MASK (0x1000000U) +#define MRCC_MRCC_GLB_ACC1_PKC0_SHIFT (24U) +/*! PKC0 - PKC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PKC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PKC0_SHIFT)) & MRCC_MRCC_GLB_ACC1_PKC0_MASK) + +#define MRCC_MRCC_GLB_ACC1_SGI0_MASK (0x2000000U) +#define MRCC_MRCC_GLB_ACC1_SGI0_SHIFT (25U) +/*! SGI0 - SGI0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_SGI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_SGI0_SHIFT)) & MRCC_MRCC_GLB_ACC1_SGI0_MASK) + +#define MRCC_MRCC_GLB_ACC1_TRNG0_MASK (0x4000000U) +#define MRCC_MRCC_GLB_ACC1_TRNG0_SHIFT (26U) +/*! TRNG0 - TRNG0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_TRNG0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_TRNG0_SHIFT)) & MRCC_MRCC_GLB_ACC1_TRNG0_MASK) + +#define MRCC_MRCC_GLB_ACC1_UDF0_MASK (0x8000000U) +#define MRCC_MRCC_GLB_ACC1_UDF0_SHIFT (27U) +/*! UDF0 - UDF0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_UDF0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_UDF0_SHIFT)) & MRCC_MRCC_GLB_ACC1_UDF0_MASK) + +#define MRCC_MRCC_GLB_ACC1_ADC2_MASK (0x10000000U) +#define MRCC_MRCC_GLB_ACC1_ADC2_SHIFT (28U) +/*! ADC2 - ADC2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_ADC2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC2_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC2_MASK) + +#define MRCC_MRCC_GLB_ACC1_ADC3_MASK (0x20000000U) +#define MRCC_MRCC_GLB_ACC1_ADC3_SHIFT (29U) +/*! ADC3 - ADC3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_ADC3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC3_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC3_MASK) +/*! @} */ + +/*! @name MRCC_GLB_ACC2 - Control Automatic Clock Gating 2 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_ACC2_RAMA_MASK (0x2U) +#define MRCC_MRCC_GLB_ACC2_RAMA_SHIFT (1U) +/*! RAMA - RAMA + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_RAMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_RAMA_SHIFT)) & MRCC_MRCC_GLB_ACC2_RAMA_MASK) + +#define MRCC_MRCC_GLB_ACC2_RAMB_MASK (0x4U) +#define MRCC_MRCC_GLB_ACC2_RAMB_SHIFT (2U) +/*! RAMB - RAMB + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_RAMB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_RAMB_SHIFT)) & MRCC_MRCC_GLB_ACC2_RAMB_MASK) + +#define MRCC_MRCC_GLB_ACC2_RAMC_MASK (0x8U) +#define MRCC_MRCC_GLB_ACC2_RAMC_SHIFT (3U) +/*! RAMC - RAMC + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_RAMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_RAMC_SHIFT)) & MRCC_MRCC_GLB_ACC2_RAMC_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO0_MASK (0x10U) +#define MRCC_MRCC_GLB_ACC2_GPIO0_SHIFT (4U) +/*! GPIO0 - GPIO0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO0_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO0_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO1_MASK (0x20U) +#define MRCC_MRCC_GLB_ACC2_GPIO1_SHIFT (5U) +/*! GPIO1 - GPIO1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO1_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO1_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO2_MASK (0x40U) +#define MRCC_MRCC_GLB_ACC2_GPIO2_SHIFT (6U) +/*! GPIO2 - GPIO2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO2_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO2_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO3_MASK (0x80U) +#define MRCC_MRCC_GLB_ACC2_GPIO3_SHIFT (7U) +/*! GPIO3 - GPIO3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO3_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO3_MASK) + +#define MRCC_MRCC_GLB_ACC2_GPIO4_MASK (0x100U) +#define MRCC_MRCC_GLB_ACC2_GPIO4_SHIFT (8U) +/*! GPIO4 - GPIO4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_GPIO4_SHIFT)) & MRCC_MRCC_GLB_ACC2_GPIO4_MASK) + +#define MRCC_MRCC_GLB_ACC2_MAU0_MASK (0x200U) +#define MRCC_MRCC_GLB_ACC2_MAU0_SHIFT (9U) +/*! MAU0 - MAU0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_MAU0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_MAU0_SHIFT)) & MRCC_MRCC_GLB_ACC2_MAU0_MASK) + +#define MRCC_MRCC_GLB_ACC2_ROMC_MASK (0x400U) +#define MRCC_MRCC_GLB_ACC2_ROMC_SHIFT (10U) +/*! ROMC - ROMC + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC2_ROMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC2_ROMC_SHIFT)) & MRCC_MRCC_GLB_ACC2_ROMC_MASK) +/*! @} */ + +/*! @name MRCC_I3C0_FCLK_CLKSEL - I3C0_FCLK clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_I3C0_FCLK_CLKDIV - I3C0_FCLK clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER0_CLKSEL - CTIMER0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CTIMER0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER0_CLKDIV - CTIMER0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER1_CLKSEL - CTIMER1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CTIMER1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER1_CLKDIV - CTIMER1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER2_CLKSEL - CTIMER2 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CTIMER2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER2_CLKDIV - CTIMER2 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER3_CLKSEL - CTIMER3 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER3_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER3_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CTIMER3_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER3_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER3_CLKDIV - CTIMER3 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER3_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER3_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER3_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER3_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER3_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER3_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER3_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER3_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER3_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER3_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER3_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER3_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER4_CLKSEL - CTIMER4 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER4_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER4_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CTIMER4_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER4_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER4_CLKDIV - CTIMER4 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER4_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER4_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER4_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER4_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER4_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER4_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER4_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER4_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER4_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER4_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER4_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER4_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_WWDT0_CLKDIV - WWDT0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_WWDT0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_WWDT0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_WWDT0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_FLEXIO0_CLKSEL - FLEXIO0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXIO0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_FLEXIO0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_FLEXIO0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_FLEXIO0_CLKDIV - FLEXIO0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXIO0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_FLEXIO0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_FLEXIO0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_FLEXIO0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_FLEXIO0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_FLEXIO0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_FLEXIO0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_FLEXIO0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_FLEXIO0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C0_CLKSEL - LPI2C0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPI2C0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C0_CLKDIV - LPI2C0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C1_CLKSEL - LPI2C1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPI2C1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C1_CLKDIV - LPI2C1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI0_CLKSEL - LPSPI0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPSPI0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI0_CLKDIV - LPSPI0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPSPI0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPSPI0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPSPI0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI1_CLKSEL - LPSPI1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPSPI1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI1_CLKDIV - LPSPI1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPSPI1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPSPI1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPSPI1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART0_CLKSEL - LPUART0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART0_CLKDIV - LPUART0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART1_CLKSEL - LPUART1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART1_CLKDIV - LPUART1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART2_CLKSEL - LPUART2 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART2_CLKDIV - LPUART2 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART3_CLKSEL - LPUART3 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART3_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART3_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART3_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART3_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART3_CLKDIV - LPUART3 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART3_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART3_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART3_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART3_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART3_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART3_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART3_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART3_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART3_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART4_CLKSEL - LPUART4 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART4_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART4_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART4_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART4_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART4_CLKDIV - LPUART4 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART4_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART4_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART4_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART4_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART4_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART4_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART4_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART4_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART4_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART4_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART4_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART4_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART4_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART4_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART4_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART4_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_USB0_CLKSEL - USB0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_USB0_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_USB0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b00..PLL1_CLK + * 0b01..CLK_48M + * 0b10..CLK_IN + * 0b11..Reserved(NO Clock) + */ +#define MRCC_MRCC_USB0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_USB0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_USB0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_USB0_CLKDIV - USB0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_USB0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_USB0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_USB0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_USB0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_USB0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_USB0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_USB0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_USB0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_USB0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_USB0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_USB0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_USB0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_USB0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_USB0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_USB0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_USB0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_USB0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_USB0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_USB0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_USB0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPTMR0_CLKSEL - LPTMR0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPTMR0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPTMR0_CLKDIV - LPTMR0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPTMR0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPTMR0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPTMR0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_OSTIMER0_CLKSEL - OSTIMER0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b00..CLK_16K + * 0b10..CLK_1M + * 0b11..Reserved2(NO Clock) + */ +#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_ADC_CLKSEL - ADCx clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_ADC_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_ADC_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b001..FRO_HF_GATED + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_ADC_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_ADC_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_ADC_CLKDIV - ADCx clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_ADC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_ADC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_ADC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_ADC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_ADC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_ADC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_ADC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_ADC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_ADC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_ADC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_ADC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_ADC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_ADC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP0_FUNC_CLKDIV - CMP0_FUNC clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP0_RR_CLKSEL - CMP0_RR clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CMP0_RR_CLKDIV - CMP0_RR clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP1_FUNC_CLKDIV - CMP1_FUNC clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP1_RR_CLKSEL - CMP1_RR clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CMP1_RR_CLKDIV - CMP1_RR clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP2_FUNC_CLKDIV - CMP2_FUNC clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP2_FUNC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP2_RR_CLKSEL - CMP2_RR clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CMP2_RR_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CMP2_RR_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CMP2_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CMP2_RR_CLKDIV - CMP2_RR clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP2_RR_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP2_RR_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP2_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP2_RR_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP2_RR_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP2_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP2_RR_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP2_RR_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP2_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP2_RR_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_DAC0_CLKSEL - DAC0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_DAC0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_DAC0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_DAC0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_DAC0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_DAC0_CLKDIV - DAC0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_DAC0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_DAC0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_DAC0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_DAC0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_DAC0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_DAC0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_DAC0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_DAC0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_DAC0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_DAC0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_DAC0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_DAC0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_DAC0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_DAC0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_DAC0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_DAC0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_FLEXCAN0_CLKSEL - FLEXCAN0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b001..FRO_HF_GATED + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b110..PLL1_CLK + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_FLEXCAN0_CLKDIV - FLEXCAN0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_FLEXCAN1_CLKSEL - FLEXCAN1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXCAN1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_FLEXCAN1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b001..FRO_HF_GATED + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b110..PLL1_CLK + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_FLEXCAN1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_FLEXCAN1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_FLEXCAN1_CLKDIV - FLEXCAN1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXCAN1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_FLEXCAN1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_FLEXCAN1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_FLEXCAN1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_FLEXCAN1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_FLEXCAN1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_FLEXCAN1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_FLEXCAN1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_FLEXCAN1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_FLEXCAN1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_FLEXCAN1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_FLEXCAN1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_FLEXCAN1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_FLEXCAN1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_FLEXCAN1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_FLEXCAN1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C2_CLKSEL - LPI2C2 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C2_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C2_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPI2C2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C2_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C2_CLKDIV - LPI2C2 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C2_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C2_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C2_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C2_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C2_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C2_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C2_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C2_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C2_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C3_CLKSEL - LPI2C3 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C3_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C3_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPI2C3_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C3_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C3_CLKDIV - LPI2C3 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C3_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C3_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C3_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C3_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C3_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C3_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C3_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C3_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C3_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C3_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C3_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C3_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART5_CLKSEL - LPUART5 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART5_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART5_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_LF_DIV + * 0b010..FRO_HF_DIV + * 0b011..CLK_IN + * 0b100..CLK_16K + * 0b101..CLK_1M + * 0b110..PLL1_CLK_DIV + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_LPUART5_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART5_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART5_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART5_CLKDIV - LPUART5 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART5_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART5_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART5_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART5_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART5_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART5_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART5_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART5_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART5_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART5_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART5_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART5_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART5_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART5_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART5_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART5_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART5_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART5_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART5_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART5_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_DBG_TRACE_CLKSEL - DBG_TRACE clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b00..CPU_CLK + * 0b01..CLK_1M + * 0b10..CLK_16K + * 0b11..Reserved1(NO Clock) + */ +#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_DBG_TRACE_CLKDIV - DBG_TRACE clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CLKOUT_CLKSEL - CLKOUT clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b000..FRO_12M + * 0b001..FRO_HF_DIV + * 0b010..CLK_IN + * 0b011..CLK_16K + * 0b101..PLL1_CLK + * 0b110..SLOW_CLK + * 0b111..Reserved(NO Clock) + */ +#define MRCC_MRCC_CLKOUT_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CLKOUT_CLKDIV - CLKOUT clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CLKOUT_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CLKOUT_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CLKOUT_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_SYSTICK_CLKSEL - SYSTICK clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_SYSTICK_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_SYSTICK_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b00..CPU_CLK + * 0b01..CLK_1M + * 0b10..CLK_16K + * 0b11..Reserved1(NO Clock) + */ +#define MRCC_MRCC_SYSTICK_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_SYSTICK_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_SYSTICK_CLKDIV - SYSTICK clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_SYSTICK_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_SYSTICK_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_SYSTICK_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_SYSTICK_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_SYSTICK_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_SYSTICK_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_SYSTICK_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_SYSTICK_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_SYSTICK_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRCC_Register_Masks */ + + +/*! + * @} + */ /* end of group MRCC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_MRCC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_OPAMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_OPAMP.h new file mode 100644 index 000000000..af919c558 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_OPAMP.h @@ -0,0 +1,237 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for OPAMP +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_OPAMP.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for OPAMP + * + * CMSIS Peripheral Access Layer for OPAMP + */ + +#if !defined(PERI_OPAMP_H_) +#define PERI_OPAMP_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- OPAMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OPAMP_Peripheral_Access_Layer OPAMP Peripheral Access Layer + * @{ + */ + +/** OPAMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t OPAMP_CTRL; /**< OPAMP Control, offset: 0x8 */ +} OPAMP_Type; + +/* ---------------------------------------------------------------------------- + -- OPAMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OPAMP_Register_Masks OPAMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define OPAMP_VERID_FEATURE_MASK (0xFFFFU) +#define OPAMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define OPAMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_FEATURE_SHIFT)) & OPAMP_VERID_FEATURE_MASK) + +#define OPAMP_VERID_MINOR_MASK (0xFF0000U) +#define OPAMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define OPAMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MINOR_SHIFT)) & OPAMP_VERID_MINOR_MASK) + +#define OPAMP_VERID_MAJOR_MASK (0xFF000000U) +#define OPAMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define OPAMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MAJOR_SHIFT)) & OPAMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define OPAMP_PARAM_PARAM_MASK (0xFFFFFFFFU) +#define OPAMP_PARAM_PARAM_SHIFT (0U) +/*! PARAM - Parameters */ +#define OPAMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_PARAM_PARAM_SHIFT)) & OPAMP_PARAM_PARAM_MASK) +/*! @} */ + +/*! @name OPAMP_CTRL - OPAMP Control */ +/*! @{ */ + +#define OPAMP_OPAMP_CTRL_OPA_EN_MASK (0x1U) +#define OPAMP_OPAMP_CTRL_OPA_EN_SHIFT (0U) +/*! OPA_EN - OPAMP Enable + * 0b0..Disable + * 0b1..Enable + */ +#define OPAMP_OPAMP_CTRL_OPA_EN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTRL_OPA_EN_SHIFT)) & OPAMP_OPAMP_CTRL_OPA_EN_MASK) + +#define OPAMP_OPAMP_CTRL_OPA_CC_SEL_MASK (0x30U) +#define OPAMP_OPAMP_CTRL_OPA_CC_SEL_SHIFT (4U) +/*! OPA_CC_SEL - Compensation capcitor config selection + * 0b00..Fit 2X gains + * 0b01..Fit 4X gains + * 0b10..Fit 8X gains + * 0b11..Fit 16X gains + */ +#define OPAMP_OPAMP_CTRL_OPA_CC_SEL(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTRL_OPA_CC_SEL_SHIFT)) & OPAMP_OPAMP_CTRL_OPA_CC_SEL_MASK) + +#define OPAMP_OPAMP_CTRL_OPA_BC_SEL_MASK (0xC0U) +#define OPAMP_OPAMP_CTRL_OPA_BC_SEL_SHIFT (6U) +/*! OPA_BC_SEL - Bias current config selection + * 0b00..Default value. Keep power consumption constant + * 0b01..Reduce power consumption to 1/4 + * 0b10..Reduce power consumption to 1/2 + * 0b11..Double the power consumption + */ +#define OPAMP_OPAMP_CTRL_OPA_BC_SEL(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTRL_OPA_BC_SEL_SHIFT)) & OPAMP_OPAMP_CTRL_OPA_BC_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OPAMP_Register_Masks */ + + +/*! + * @} + */ /* end of group OPAMP_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_OPAMP_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_OSTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_OSTIMER.h new file mode 100644 index 000000000..5732b8ae5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_OSTIMER.h @@ -0,0 +1,266 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for OSTIMER +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_OSTIMER.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for OSTIMER + * + * CMSIS Peripheral Access Layer for OSTIMER + */ + +#if !defined(PERI_OSTIMER_H_) +#define PERI_OSTIMER_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Local Capture Low for CPU, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Local Capture High for CPU, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Local Match Low for CPU, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Local Match High for CPU, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OSTIMER Control for CPU, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Local Capture Low for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Local Capture High for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Local Match Low for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Local Match High for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OSTIMER Control for CPU */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - Interrupt Flag */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - Interrupt or Wake-Up Request + * 0b0..Interrupts blocked + * 0b1..Interrupts enabled + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - EVTimer Match Write Ready */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) + +#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK (0x8U) +#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT (3U) +/*! DEBUG_EN - Debug Enable + * 0b0..Disables + * 0b1..Enables + */ +#define OSTIMER_OSEVENT_CTRL_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT)) & OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_OSTIMER_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_PKC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_PKC.h new file mode 100644 index 000000000..7659f54ab --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_PKC.h @@ -0,0 +1,657 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for PKC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_PKC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for PKC + * + * CMSIS Peripheral Access Layer for PKC + */ + +#if !defined(PERI_PKC_H_) +#define PERI_PKC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PKC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer + * @{ + */ + +/** PKC - Register Layout Typedef */ +typedef struct { + __I uint32_t PKC_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t PKC_CTRL; /**< Control Register, offset: 0x4 */ + __IO uint32_t PKC_CFG; /**< Configuration register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PKC_MODE1; /**< Mode register, parameter set 1, offset: 0x10 */ + __IO uint32_t PKC_XYPTR1; /**< X+Y pointer register, parameter set 1, offset: 0x14 */ + __IO uint32_t PKC_ZRPTR1; /**< Z+R pointer register, parameter set 1, offset: 0x18 */ + __IO uint32_t PKC_LEN1; /**< Length register, parameter set 1, offset: 0x1C */ + __IO uint32_t PKC_MODE2; /**< Mode register, parameter set 2, offset: 0x20 */ + __IO uint32_t PKC_XYPTR2; /**< X+Y pointer register, parameter set 2, offset: 0x24 */ + __IO uint32_t PKC_ZRPTR2; /**< Z+R pointer register, parameter set 2, offset: 0x28 */ + __IO uint32_t PKC_LEN2; /**< Length register, parameter set 2, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PKC_UPTR; /**< Universal pointer FUP program, offset: 0x40 */ + __IO uint32_t PKC_UPTRT; /**< Universal pointer FUP table, offset: 0x44 */ + __IO uint32_t PKC_ULEN; /**< Universal pointer length, offset: 0x48 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PKC_MCDATA; /**< MC pattern data interface, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __I uint32_t PKC_VERSION; /**< PKC version register, offset: 0x60 */ + uint8_t RESERVED_4[3916]; + __O uint32_t PKC_SOFT_RST; /**< Software reset, offset: 0xFB0 */ + uint8_t RESERVED_5[12]; + __I uint32_t PKC_ACCESS_ERR; /**< Access Error, offset: 0xFC0 */ + __O uint32_t PKC_ACCESS_ERR_CLR; /**< Clear Access Error, offset: 0xFC4 */ + uint8_t RESERVED_6[16]; + __O uint32_t PKC_INT_CLR_ENABLE; /**< Interrupt enable clear, offset: 0xFD8 */ + __O uint32_t PKC_INT_SET_ENABLE; /**< Interrupt enable set, offset: 0xFDC */ + __I uint32_t PKC_INT_STATUS; /**< Interrupt status, offset: 0xFE0 */ + __I uint32_t PKC_INT_ENABLE; /**< Interrupt enable, offset: 0xFE4 */ + __O uint32_t PKC_INT_CLR_STATUS; /**< Interrupt status clear, offset: 0xFE8 */ + __O uint32_t PKC_INT_SET_STATUS; /**< Interrupt status set, offset: 0xFEC */ + uint8_t RESERVED_7[12]; + __I uint32_t PKC_MODULE_ID; /**< Module ID, offset: 0xFFC */ +} PKC_Type; + +/* ---------------------------------------------------------------------------- + -- PKC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Register_Masks PKC Register Masks + * @{ + */ + +/*! @name PKC_STATUS - Status Register */ +/*! @{ */ + +#define PKC_PKC_STATUS_ACTIV_MASK (0x1U) +#define PKC_PKC_STATUS_ACTIV_SHIFT (0U) +/*! ACTIV - PKC ACTIV */ +#define PKC_PKC_STATUS_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK) + +#define PKC_PKC_STATUS_CARRY_MASK (0x2U) +#define PKC_PKC_STATUS_CARRY_SHIFT (1U) +/*! CARRY - Carry overflow flag */ +#define PKC_PKC_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK) + +#define PKC_PKC_STATUS_ZERO_MASK (0x4U) +#define PKC_PKC_STATUS_ZERO_SHIFT (2U) +/*! ZERO - Zero result flag */ +#define PKC_PKC_STATUS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK) + +#define PKC_PKC_STATUS_GOANY_MASK (0x8U) +#define PKC_PKC_STATUS_GOANY_SHIFT (3U) +/*! GOANY - Combined GO status flag */ +#define PKC_PKC_STATUS_GOANY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK) + +#define PKC_PKC_STATUS_LOCKED_MASK (0x60U) +#define PKC_PKC_STATUS_LOCKED_SHIFT (5U) +/*! LOCKED - Parameter set locked */ +#define PKC_PKC_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK) +/*! @} */ + +/*! @name PKC_CTRL - Control Register */ +/*! @{ */ + +#define PKC_PKC_CTRL_RESET_MASK (0x1U) +#define PKC_PKC_CTRL_RESET_SHIFT (0U) +/*! RESET - PKC reset control bit */ +#define PKC_PKC_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK) + +#define PKC_PKC_CTRL_STOP_MASK (0x2U) +#define PKC_PKC_CTRL_STOP_SHIFT (1U) +/*! STOP - Freeze PKC calculation */ +#define PKC_PKC_CTRL_STOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK) + +#define PKC_PKC_CTRL_GOD1_MASK (0x4U) +#define PKC_PKC_CTRL_GOD1_SHIFT (2U) +/*! GOD1 - Control bit to start direct operation using parameter set 1 */ +#define PKC_PKC_CTRL_GOD1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK) + +#define PKC_PKC_CTRL_GOD2_MASK (0x8U) +#define PKC_PKC_CTRL_GOD2_SHIFT (3U) +/*! GOD2 - Control bit to start direct operation using parameter set 2 */ +#define PKC_PKC_CTRL_GOD2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK) + +#define PKC_PKC_CTRL_GOM1_MASK (0x10U) +#define PKC_PKC_CTRL_GOM1_SHIFT (4U) +/*! GOM1 - Control bit to start MC pattern using parameter set 1 */ +#define PKC_PKC_CTRL_GOM1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK) + +#define PKC_PKC_CTRL_GOM2_MASK (0x20U) +#define PKC_PKC_CTRL_GOM2_SHIFT (5U) +/*! GOM2 - Control bit to start MC pattern using parameter set 2 */ +#define PKC_PKC_CTRL_GOM2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK) + +#define PKC_PKC_CTRL_GOU_MASK (0x40U) +#define PKC_PKC_CTRL_GOU_SHIFT (6U) +/*! GOU - Control bit to start pipe operation */ +#define PKC_PKC_CTRL_GOU(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK) + +#define PKC_PKC_CTRL_GF2CONV_MASK (0x80U) +#define PKC_PKC_CTRL_GF2CONV_SHIFT (7U) +/*! GF2CONV - Convert to GF2 calculation modes */ +#define PKC_PKC_CTRL_GF2CONV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK) + +#define PKC_PKC_CTRL_CLRCACHE_MASK (0x100U) +#define PKC_PKC_CTRL_CLRCACHE_SHIFT (8U) +/*! CLRCACHE - Clear universal pointer cache */ +#define PKC_PKC_CTRL_CLRCACHE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK) + +#define PKC_PKC_CTRL_CACHE_EN_MASK (0x200U) +#define PKC_PKC_CTRL_CACHE_EN_SHIFT (9U) +/*! CACHE_EN - Enable universal pointer cache */ +#define PKC_PKC_CTRL_CACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK) + +#define PKC_PKC_CTRL_REDMUL_MASK (0xC00U) +#define PKC_PKC_CTRL_REDMUL_SHIFT (10U) +/*! REDMUL - Reduced multiplier mode + * 0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b01..Reserved - Error Generated if selected + * 0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b11..Reserved - Error Generated if selected + */ +#define PKC_PKC_CTRL_REDMUL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK) +/*! @} */ + +/*! @name PKC_CFG - Configuration register */ +/*! @{ */ + +#define PKC_PKC_CFG_IDLEOP_MASK (0x1U) +#define PKC_PKC_CFG_IDLEOP_SHIFT (0U) +#define PKC_PKC_CFG_IDLEOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK) + +#define PKC_PKC_CFG_RFU1_MASK (0x2U) +#define PKC_PKC_CFG_RFU1_SHIFT (1U) +#define PKC_PKC_CFG_RFU1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK) + +#define PKC_PKC_CFG_RFU2_MASK (0x4U) +#define PKC_PKC_CFG_RFU2_SHIFT (2U) +#define PKC_PKC_CFG_RFU2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK) + +#define PKC_PKC_CFG_CLKRND_MASK (0x8U) +#define PKC_PKC_CFG_CLKRND_SHIFT (3U) +#define PKC_PKC_CFG_CLKRND(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK) + +#define PKC_PKC_CFG_REDMULNOISE_MASK (0x10U) +#define PKC_PKC_CFG_REDMULNOISE_SHIFT (4U) +#define PKC_PKC_CFG_REDMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK) + +#define PKC_PKC_CFG_RNDDLY_MASK (0xE0U) +#define PKC_PKC_CFG_RNDDLY_SHIFT (5U) +#define PKC_PKC_CFG_RNDDLY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK) + +#define PKC_PKC_CFG_SBXNOISE_MASK (0x100U) +#define PKC_PKC_CFG_SBXNOISE_SHIFT (8U) +#define PKC_PKC_CFG_SBXNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK) + +#define PKC_PKC_CFG_ALPNOISE_MASK (0x200U) +#define PKC_PKC_CFG_ALPNOISE_SHIFT (9U) +#define PKC_PKC_CFG_ALPNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK) + +#define PKC_PKC_CFG_FMULNOISE_MASK (0x400U) +#define PKC_PKC_CFG_FMULNOISE_SHIFT (10U) +#define PKC_PKC_CFG_FMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK) +/*! @} */ + +/*! @name PKC_MODE1 - Mode register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_MODE1_MODE_MASK (0xFFU) +#define PKC_PKC_MODE1_MODE_SHIFT (0U) +/*! MODE - Calculation Mode / MC Start address */ +#define PKC_PKC_MODE1_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK) +/*! @} */ + +/*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_XYPTR1_XPTR_MASK (0xFFFFU) +#define PKC_PKC_XYPTR1_XPTR_SHIFT (0U) +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR1_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK) + +#define PKC_PKC_XYPTR1_YPTR_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR1_YPTR_SHIFT (16U) +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR1_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR1_ZPTR_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR1_ZPTR_SHIFT (0U) +/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR1_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK) + +#define PKC_PKC_ZRPTR1_RPTR_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR1_RPTR_SHIFT (16U) +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ +#define PKC_PKC_ZRPTR1_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK) +/*! @} */ + +/*! @name PKC_LEN1 - Length register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_LEN1_LEN_MASK (0xFFFFU) +#define PKC_PKC_LEN1_LEN_SHIFT (0U) +/*! LEN - Operand length */ +#define PKC_PKC_LEN1_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK) + +#define PKC_PKC_LEN1_MCLEN_MASK (0xFFFF0000U) +#define PKC_PKC_LEN1_MCLEN_SHIFT (16U) +/*! MCLEN - Loop counter for microcode pattern */ +#define PKC_PKC_LEN1_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK) +/*! @} */ + +/*! @name PKC_MODE2 - Mode register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_MODE2_MODE_MASK (0xFFU) +#define PKC_PKC_MODE2_MODE_SHIFT (0U) +/*! MODE - Calculation Mode / MC Start address */ +#define PKC_PKC_MODE2_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK) +/*! @} */ + +/*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_XYPTR2_XPTR_MASK (0xFFFFU) +#define PKC_PKC_XYPTR2_XPTR_SHIFT (0U) +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR2_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK) + +#define PKC_PKC_XYPTR2_YPTR_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR2_YPTR_SHIFT (16U) +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR2_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR2_ZPTR_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR2_ZPTR_SHIFT (0U) +/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR2_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPTR_SHIFT)) & PKC_PKC_ZRPTR2_ZPTR_MASK) + +#define PKC_PKC_ZRPTR2_RPTR_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR2_RPTR_SHIFT (16U) +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ +#define PKC_PKC_ZRPTR2_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK) +/*! @} */ + +/*! @name PKC_LEN2 - Length register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_LEN2_LEN_MASK (0xFFFFU) +#define PKC_PKC_LEN2_LEN_SHIFT (0U) +/*! LEN - Operand length */ +#define PKC_PKC_LEN2_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK) + +#define PKC_PKC_LEN2_MCLEN_MASK (0xFFFF0000U) +#define PKC_PKC_LEN2_MCLEN_SHIFT (16U) +/*! MCLEN - Loop counter for microcode pattern */ +#define PKC_PKC_LEN2_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK) +/*! @} */ + +/*! @name PKC_UPTR - Universal pointer FUP program */ +/*! @{ */ + +#define PKC_PKC_UPTR_PTR_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTR_PTR_SHIFT (0U) +/*! PTR - Pointer to start address of PKC FUP program */ +#define PKC_PKC_UPTR_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK) +/*! @} */ + +/*! @name PKC_UPTRT - Universal pointer FUP table */ +/*! @{ */ + +#define PKC_PKC_UPTRT_PTR_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTRT_PTR_SHIFT (0U) +/*! PTR - Pointer to start address of PKC FUP table */ +#define PKC_PKC_UPTRT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK) +/*! @} */ + +/*! @name PKC_ULEN - Universal pointer length */ +/*! @{ */ + +#define PKC_PKC_ULEN_LEN_MASK (0xFFU) +#define PKC_PKC_ULEN_LEN_SHIFT (0U) +/*! LEN - Length of universal pointer calculation */ +#define PKC_PKC_ULEN_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK) +/*! @} */ + +/*! @name PKC_MCDATA - MC pattern data interface */ +/*! @{ */ + +#define PKC_PKC_MCDATA_MCDATA_MASK (0xFFFFFFFFU) +#define PKC_PKC_MCDATA_MCDATA_SHIFT (0U) +/*! MCDATA - Microcode read/write data */ +#define PKC_PKC_MCDATA_MCDATA(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK) +/*! @} */ + +/*! @name PKC_VERSION - PKC version register */ +/*! @{ */ + +#define PKC_PKC_VERSION_MULSIZE_MASK (0x3U) +#define PKC_PKC_VERSION_MULSIZE_SHIFT (0U) +/*! MULSIZE + * 0b01..Reserved + * 0b10..64-bit multiplier + * 0b11..Reserved + */ +#define PKC_PKC_VERSION_MULSIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK) + +#define PKC_PKC_VERSION_MCAVAIL_MASK (0x4U) +#define PKC_PKC_VERSION_MCAVAIL_SHIFT (2U) +#define PKC_PKC_VERSION_MCAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK) + +#define PKC_PKC_VERSION_UPAVAIL_MASK (0x8U) +#define PKC_PKC_VERSION_UPAVAIL_SHIFT (3U) +#define PKC_PKC_VERSION_UPAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK) + +#define PKC_PKC_VERSION_UPCACHEAVAIL_MASK (0x10U) +#define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT (4U) +#define PKC_PKC_VERSION_UPCACHEAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK) + +#define PKC_PKC_VERSION_GF2AVAIL_MASK (0x20U) +#define PKC_PKC_VERSION_GF2AVAIL_SHIFT (5U) +#define PKC_PKC_VERSION_GF2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK) + +#define PKC_PKC_VERSION_PARAMNUM_MASK (0xC0U) +#define PKC_PKC_VERSION_PARAMNUM_SHIFT (6U) +#define PKC_PKC_VERSION_PARAMNUM(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK) + +#define PKC_PKC_VERSION_SBX0AVAIL_MASK (0x100U) +#define PKC_PKC_VERSION_SBX0AVAIL_SHIFT (8U) +#define PKC_PKC_VERSION_SBX0AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX1AVAIL_MASK (0x200U) +#define PKC_PKC_VERSION_SBX1AVAIL_SHIFT (9U) +#define PKC_PKC_VERSION_SBX1AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX2AVAIL_MASK (0x400U) +#define PKC_PKC_VERSION_SBX2AVAIL_SHIFT (10U) +#define PKC_PKC_VERSION_SBX2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX3AVAIL_MASK (0x800U) +#define PKC_PKC_VERSION_SBX3AVAIL_SHIFT (11U) +#define PKC_PKC_VERSION_SBX3AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK) + +#define PKC_PKC_VERSION_MCRECONF_SIZE_MASK (0xFF000U) +#define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT (12U) +#define PKC_PKC_VERSION_MCRECONF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK) +/*! @} */ + +/*! @name PKC_SOFT_RST - Software reset */ +/*! @{ */ + +#define PKC_PKC_SOFT_RST_SOFT_RST_MASK (0x1U) +#define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT (0U) +#define PKC_PKC_SOFT_RST_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR - Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT (0U) +/*! APB_NOTAV - APB Error */ +#define PKC_PKC_ACCESS_ERR_APB_NOTAV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK) + +#define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK (0x2U) +#define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT (1U) +/*! APB_WRGMD - APB Error */ +#define PKC_PKC_ACCESS_ERR_APB_WRGMD(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK) + +#define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK (0xF0U) +#define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT (4U) +#define PKC_PKC_ACCESS_ERR_APB_MASTER(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK) + +#define PKC_PKC_ACCESS_ERR_AHB_MASK (0x400U) +#define PKC_PKC_ACCESS_ERR_AHB_SHIFT (10U) +/*! AHB - AHB Error */ +#define PKC_PKC_ACCESS_ERR_AHB(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK) + +#define PKC_PKC_ACCESS_ERR_PKCC_MASK (0x10000U) +#define PKC_PKC_ACCESS_ERR_PKCC_SHIFT (16U) +#define PKC_PKC_ACCESS_ERR_PKCC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK) + +#define PKC_PKC_ACCESS_ERR_FDET_MASK (0x20000U) +#define PKC_PKC_ACCESS_ERR_FDET_SHIFT (17U) +#define PKC_PKC_ACCESS_ERR_FDET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK) + +#define PKC_PKC_ACCESS_ERR_CTRL_MASK (0x40000U) +#define PKC_PKC_ACCESS_ERR_CTRL_SHIFT (18U) +#define PKC_PKC_ACCESS_ERR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK) + +#define PKC_PKC_ACCESS_ERR_UCRC_MASK (0x80000U) +#define PKC_PKC_ACCESS_ERR_UCRC_SHIFT (19U) +#define PKC_PKC_ACCESS_ERR_UCRC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT (0U) +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT (0U) +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_ENABLE - Interrupt enable set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT (0U) +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_STATUS - Interrupt status */ +/*! @{ */ + +#define PKC_PKC_INT_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT (0U) +/*! INT_PDONE - End-of-computation status flag */ +#define PKC_PKC_INT_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_ENABLE - Interrupt enable */ +/*! @{ */ + +#define PKC_PKC_INT_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT (0U) +/*! EN_PDONE - PDONE interrupt enable flag */ +#define PKC_PKC_INT_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_STATUS - Interrupt status clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT (0U) +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_STATUS - Interrupt status set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT (0U) +#define PKC_PKC_INT_SET_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_MODULE_ID - Module ID */ +/*! @{ */ + +#define PKC_PKC_MODULE_ID_SIZE_MASK (0xFFU) +#define PKC_PKC_MODULE_ID_SIZE_SHIFT (0U) +#define PKC_PKC_MODULE_ID_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK) + +#define PKC_PKC_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT (8U) +#define PKC_PKC_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK) + +#define PKC_PKC_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT (12U) +#define PKC_PKC_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK) + +#define PKC_PKC_MODULE_ID_ID_MASK (0xFFFF0000U) +#define PKC_PKC_MODULE_ID_ID_SHIFT (16U) +#define PKC_PKC_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PKC_Register_Masks */ + + +/*! + * @} + */ /* end of group PKC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PKC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_PORT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_PORT.h new file mode 100644 index 000000000..612667815 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_PORT.h @@ -0,0 +1,635 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for PORT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_PORT.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for PORT + * + * CMSIS Peripheral Access Layer for PORT + */ + +#if !defined(PERI_PORT_H_) +#define PERI_PORT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Size of Registers Arrays */ +#define PORT_PCR_COUNT 32u + +/** PORT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t GPCLR; /**< Global Pin Control Low, offset: 0x10 */ + __IO uint32_t GPCHR; /**< Global Pin Control High, offset: 0x14 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CONFIG; /**< Configuration, offset: 0x20 */ + uint8_t RESERVED_2[60]; + __IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT3, PORT4 (missing on PORT2) */ + __IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT3, PORT4 (missing on PORT2) */ + uint8_t RESERVED_3[24]; + __IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PORT_VERID_FEATURE_MASK (0xFFFFU) +#define PORT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + */ +#define PORT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK) + +#define PORT_VERID_MINOR_MASK (0xFF0000U) +#define PORT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PORT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK) + +#define PORT_VERID_MAJOR_MASK (0xFF000000U) +#define PORT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PORT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name GPCLR - Global Pin Control Low */ +/*! @{ */ + +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) + +#define PORT_GPCLR_GPWE0_MASK (0x10000U) +#define PORT_GPCLR_GPWE0_SHIFT (16U) +/*! GPWE0 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK) + +#define PORT_GPCLR_GPWE1_MASK (0x20000U) +#define PORT_GPCLR_GPWE1_SHIFT (17U) +/*! GPWE1 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK) + +#define PORT_GPCLR_GPWE2_MASK (0x40000U) +#define PORT_GPCLR_GPWE2_SHIFT (18U) +/*! GPWE2 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK) + +#define PORT_GPCLR_GPWE3_MASK (0x80000U) +#define PORT_GPCLR_GPWE3_SHIFT (19U) +/*! GPWE3 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK) + +#define PORT_GPCLR_GPWE4_MASK (0x100000U) +#define PORT_GPCLR_GPWE4_SHIFT (20U) +/*! GPWE4 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK) + +#define PORT_GPCLR_GPWE5_MASK (0x200000U) +#define PORT_GPCLR_GPWE5_SHIFT (21U) +/*! GPWE5 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK) + +#define PORT_GPCLR_GPWE6_MASK (0x400000U) +#define PORT_GPCLR_GPWE6_SHIFT (22U) +/*! GPWE6 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK) + +#define PORT_GPCLR_GPWE7_MASK (0x800000U) +#define PORT_GPCLR_GPWE7_SHIFT (23U) +/*! GPWE7 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK) + +#define PORT_GPCLR_GPWE8_MASK (0x1000000U) +#define PORT_GPCLR_GPWE8_SHIFT (24U) +/*! GPWE8 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK) + +#define PORT_GPCLR_GPWE9_MASK (0x2000000U) +#define PORT_GPCLR_GPWE9_SHIFT (25U) +/*! GPWE9 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK) + +#define PORT_GPCLR_GPWE10_MASK (0x4000000U) +#define PORT_GPCLR_GPWE10_SHIFT (26U) +/*! GPWE10 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK) + +#define PORT_GPCLR_GPWE11_MASK (0x8000000U) +#define PORT_GPCLR_GPWE11_SHIFT (27U) +/*! GPWE11 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK) + +#define PORT_GPCLR_GPWE12_MASK (0x10000000U) +#define PORT_GPCLR_GPWE12_SHIFT (28U) +/*! GPWE12 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK) + +#define PORT_GPCLR_GPWE13_MASK (0x20000000U) +#define PORT_GPCLR_GPWE13_SHIFT (29U) +/*! GPWE13 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK) + +#define PORT_GPCLR_GPWE14_MASK (0x40000000U) +#define PORT_GPCLR_GPWE14_SHIFT (30U) +/*! GPWE14 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK) + +#define PORT_GPCLR_GPWE15_MASK (0x80000000U) +#define PORT_GPCLR_GPWE15_SHIFT (31U) +/*! GPWE15 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK) +/*! @} */ + +/*! @name GPCHR - Global Pin Control High */ +/*! @{ */ + +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) + +#define PORT_GPCHR_GPWE16_MASK (0x10000U) +#define PORT_GPCHR_GPWE16_SHIFT (16U) +/*! GPWE16 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK) + +#define PORT_GPCHR_GPWE17_MASK (0x20000U) +#define PORT_GPCHR_GPWE17_SHIFT (17U) +/*! GPWE17 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK) + +#define PORT_GPCHR_GPWE18_MASK (0x40000U) +#define PORT_GPCHR_GPWE18_SHIFT (18U) +/*! GPWE18 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK) + +#define PORT_GPCHR_GPWE19_MASK (0x80000U) +#define PORT_GPCHR_GPWE19_SHIFT (19U) +/*! GPWE19 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK) + +#define PORT_GPCHR_GPWE20_MASK (0x100000U) +#define PORT_GPCHR_GPWE20_SHIFT (20U) +/*! GPWE20 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK) + +#define PORT_GPCHR_GPWE21_MASK (0x200000U) +#define PORT_GPCHR_GPWE21_SHIFT (21U) +/*! GPWE21 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK) + +#define PORT_GPCHR_GPWE22_MASK (0x400000U) +#define PORT_GPCHR_GPWE22_SHIFT (22U) +/*! GPWE22 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK) + +#define PORT_GPCHR_GPWE23_MASK (0x800000U) +#define PORT_GPCHR_GPWE23_SHIFT (23U) +/*! GPWE23 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK) + +#define PORT_GPCHR_GPWE24_MASK (0x1000000U) +#define PORT_GPCHR_GPWE24_SHIFT (24U) +/*! GPWE24 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK) + +#define PORT_GPCHR_GPWE25_MASK (0x2000000U) +#define PORT_GPCHR_GPWE25_SHIFT (25U) +/*! GPWE25 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK) + +#define PORT_GPCHR_GPWE26_MASK (0x4000000U) +#define PORT_GPCHR_GPWE26_SHIFT (26U) +/*! GPWE26 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK) + +#define PORT_GPCHR_GPWE27_MASK (0x8000000U) +#define PORT_GPCHR_GPWE27_SHIFT (27U) +/*! GPWE27 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK) + +#define PORT_GPCHR_GPWE28_MASK (0x10000000U) +#define PORT_GPCHR_GPWE28_SHIFT (28U) +/*! GPWE28 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK) + +#define PORT_GPCHR_GPWE29_MASK (0x20000000U) +#define PORT_GPCHR_GPWE29_SHIFT (29U) +/*! GPWE29 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK) + +#define PORT_GPCHR_GPWE30_MASK (0x40000000U) +#define PORT_GPCHR_GPWE30_SHIFT (30U) +/*! GPWE30 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK) + +#define PORT_GPCHR_GPWE31_MASK (0x80000000U) +#define PORT_GPCHR_GPWE31_SHIFT (31U) +/*! GPWE31 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK) +/*! @} */ + +/*! @name CONFIG - Configuration */ +/*! @{ */ + +#define PORT_CONFIG_RANGE_MASK (0x1U) +#define PORT_CONFIG_RANGE_SHIFT (0U) +/*! RANGE - Port Voltage Range + * 0b0..1.71 V-3.6 V + * 0b1..2.70 V-3.6 V + */ +#define PORT_CONFIG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK) +/*! @} */ + +/*! @name CALIB0 - Calibration 0 */ +/*! @{ */ + +#define PORT_CALIB0_NCAL_MASK (0x3FU) +#define PORT_CALIB0_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB0_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK) + +#define PORT_CALIB0_PCAL_MASK (0x3F0000U) +#define PORT_CALIB0_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB0_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK) +/*! @} */ + +/*! @name CALIB1 - Calibration 1 */ +/*! @{ */ + +#define PORT_CALIB1_NCAL_MASK (0x3FU) +#define PORT_CALIB1_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB1_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK) + +#define PORT_CALIB1_PCAL_MASK (0x3F0000U) +#define PORT_CALIB1_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK) +/*! @} */ + +/*! @name PCR - Pin Control 0..Pin Control 31 */ +/*! @{ */ + +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +/*! PS - Pull Select + * 0b0..Enables internal pulldown resistor + * 0b1..Enables internal pullup resistor + */ +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) + +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +/*! PE - Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) + +#define PORT_PCR_PV_MASK (0x4U) +#define PORT_PCR_PV_SHIFT (2U) +/*! PV - Pull Value + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_PV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK) + +#define PORT_PCR_SRE_MASK (0x8U) +#define PORT_PCR_SRE_SHIFT (3U) +/*! SRE - Slew Rate Enable + * 0b0..Fast + * 0b1..Slow + */ +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) + +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +/*! PFE - Passive Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) + +#define PORT_PCR_ODE_MASK (0x20U) +#define PORT_PCR_ODE_SHIFT (5U) +/*! ODE - Open Drain Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) + +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +/*! DSE - Drive Strength Enable + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) + +#define PORT_PCR_DSE1_MASK (0x80U) +#define PORT_PCR_DSE1_SHIFT (7U) +/*! DSE1 - Drive Strength Enable + * 0b0..Normal + * 0b1..Double + */ +#define PORT_PCR_DSE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE1_SHIFT)) & PORT_PCR_DSE1_MASK) + +#define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */ +#define PORT_PCR_MUX_SHIFT (8U) +/*! MUX - Pin Multiplex Control + * 0b0000..Alternative 0 (GPIO) + * 0b0001..Alternative 1 (chip-specific) + * 0b0010..Alternative 2 (chip-specific) + * 0b0011..Alternative 3 (chip-specific) + * 0b0100..Alternative 4 (chip-specific) + * 0b0101..Alternative 5 (chip-specific) + * 0b0110..Alternative 6 (chip-specific) + * 0b0111..Alternative 7 (chip-specific) + * 0b1000..Alternative 8 (chip-specific) + * 0b1001..Alternative 9 (chip-specific) + * 0b1010..Alternative 10 (chip-specific) + * 0b1011..Alternative 11 (chip-specific) + * 0b1100..Alternative 12 (chip-specific) + * 0b1101..Alternative 13 (chip-specific) + */ +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */ + +#define PORT_PCR_IBE_MASK (0x1000U) +#define PORT_PCR_IBE_SHIFT (12U) +/*! IBE - Input Buffer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK) + +#define PORT_PCR_INV_MASK (0x2000U) +#define PORT_PCR_INV_SHIFT (13U) +/*! INV - Invert Input + * 0b0..Does not invert + * 0b1..Inverts + */ +#define PORT_PCR_INV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK) + +#define PORT_PCR_LK_MASK (0x8000U) +#define PORT_PCR_LK_SHIFT (15U) +/*! LK - Lock Register + * 0b0..Does not lock + * 0b1..Locks + */ +#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PORT_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_PWM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_PWM.h new file mode 100644 index 000000000..e9173e79e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_PWM.h @@ -0,0 +1,1388 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for PWM +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_PWM.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for PWM + * + * CMSIS Peripheral Access Layer for PWM + */ + +#if !defined(PERI_PWM_H_) +#define PERI_PWM_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Size of Registers Arrays */ +#define PWM_SM_DISMAP_COUNT 1u +#define PWM_SM_COUNT 4u + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + uint8_t RESERVED_1[2]; + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + uint8_t RESERVED_2[2]; + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + uint8_t RESERVED_3[2]; + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + uint8_t RESERVED_4[2]; + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + uint8_t RESERVED_5[2]; + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + uint8_t RESERVED_6[2]; + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[PWM_SM_DISMAP_COUNT]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + uint8_t RESERVED_7[2]; + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + uint8_t RESERVED_8[8]; + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + uint8_t RESERVED_9[16]; + __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-3] */ + uint8_t RESERVED_10[4]; + __IO uint16_t CAPTFILTX; /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60 */ + } SM[PWM_SM_COUNT]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ + +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +/*! CNT - Counter Register Bits */ +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ + +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +/*! INIT - Initial Count Register Bits */ +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it forces the clock to logic 0. + * 0b11..Reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) + +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it forces the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) + +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - Force Select + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the eFlexPWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the eFlexPWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) + +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +/*! FORCE - Force Initialization */ +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) + +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - Force Enable + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) + +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload + * occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) + +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +/*! PWMX_INIT - PWM_X Initial Value */ +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) + +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +/*! PWM45_INIT - PWM45 Initial Value */ +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) + +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +/*! PWM23_INIT - PWM23 Initial Value */ +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) + +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) + +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +/*! DBGEN - Debug Enable */ +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) + +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWM_X Double Switching Enable + * 0b0..PWM_X double pulse disabled. + * 0b1..PWM_X double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) + +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) + +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B + * 0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses. + * 0b1..DBLPWM is split to PWM_A and PWM_B. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) + +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..Prescaler 1 + * 0b001..Prescaler 2 + * 0b010..Prescaler 4 + * 0b011..Prescaler 8 + * 0b100..Prescaler 16 + * 0b101..Prescaler 32 + * 0b110..Prescaler 64 + * 0b111..Prescaler 128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) + +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A + * output that is high at the end of a period maintains this state until a match with VAL3 clears the output + * in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) + +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +/*! DT - Deadtime */ +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) + +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) + +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) + +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ + +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +/*! VAL0 - Value 0 */ +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ + +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +/*! VAL1 - Value 1 */ +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ + +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +/*! VAL2 - Value 2 */ +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ + +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +/*! VAL3 - Value 3 */ +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ + +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +/*! VAL4 - Value 4 */ +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ + +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +/*! VAL5 - Value 5 */ +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ + +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) + +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) + +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) + +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) + +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) + +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) + +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +/*! PWMX_IN - PWM_X Input */ +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) + +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +/*! PWMB_IN - PWM_B Input */ +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) + +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +/*! PWMA_IN - PWM_A Input */ +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ + +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) + +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +/*! CFX0 - Capture Flag X0 */ +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) + +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +/*! CFX1 - Capture Flag X1 */ +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) + +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) + +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) + +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ + +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) + +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) + +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) + +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) + +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ + +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +/*! CX0DE - Capture X0 FIFO DMA Enable */ +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) + +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +/*! CX1DE - Capture X1 FIFO DMA Enable */ +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) + +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CX1DE], or + * DMAEN[CX0DE] to be set to determine which watermark(s) the DMA request is sensitive. + * 0b10..A local synchronization (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) + +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) + +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..Enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ + +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. + * 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value. + * 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value. + * 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value. + * 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value. + * 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) + +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger Frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) + +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Mux Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. + * 0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) + +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Mux Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. + * 0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0 */ +/*! @{ */ + +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +/*! DIS0A - PWM_A Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) + +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +/*! DIS0B - PWM_B Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) + +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +/*! DIS0X - PWM_X Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (1U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ + +#define PWM_DTCNT0_DTCNT0_MASK (0x7FFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +/*! DTCNT0 - Deadtime Count Register 0 */ +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ + +#define PWM_DTCNT1_DTCNT1_MASK (0x7FFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +/*! DTCNT1 - Deadtime Count Register 1 */ +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ + +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) + +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) + +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) + +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) + +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) + +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) + +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +/*! CFXWM - Capture X FIFOs Water Mark */ +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) + +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +/*! CX0CNT - Capture X0 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) + +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +/*! CX1CNT - Capture X1 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ + +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +/*! EDGCMPX - Edge Compare X */ +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) + +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +/*! EDGCNTX - Edge Counter X */ +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ + +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +/*! CAPTVAL0 - Capture Value 0 */ +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +/*! CVAL0CYC - Capture Value 0 Cycle */ +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ + +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +/*! CAPTVAL1 - Capture Value 1 */ +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +/*! CVAL1CYC - Capture Value 1 Cycle */ +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name PHASEDLY - Phase Delay Register */ +/*! @{ */ + +#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) +#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) +/*! PHASEDLY - Initial Count Register Bits */ +#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) +/*! @} */ + +/* The count of PWM_PHASEDLY */ +#define PWM_PHASEDLY_COUNT (4U) + +/*! @name CAPTFILTX - Capture PWM_X Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) +/*! CAPTX_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) + +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) +/*! CAPTX_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTX */ +#define PWM_CAPTFILTX_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ + +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) + +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) + +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ + +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) + +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) + +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) + +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ + +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) + +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) + +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) + +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) + +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) + +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) + +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) + +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ + +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) + +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] used by the deadtime logic. + * 0b11..PWM0_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) + +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) + +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] used by the deadtime logic. + * 0b11..PWM1_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) + +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) + +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] used by the deadtime logic. + * 0b11..PWM2_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) + +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) + +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] used by the deadtime logic. + * 0b11..PWM3_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ + +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) + +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +/*! CLDOK - Clear Load Okay */ +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) + +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM counter is stopped, but PWM outputs hold the current state. + * 0b0001..PWM counter is started in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) + +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ + +#define PWM_MCTRL2_WRPROT_MASK (0xCU) +#define PWM_MCTRL2_WRPROT_SHIFT (2U) +/*! WRPROT - Write protect + * 0b00..Write protection off (default). + * 0b01..Write protection on. + * 0b10..Write protection off and locked until chip reset. + * 0b11..Write protection on and locked until chip reset. + */ +#define PWM_MCTRL2_WRPROT(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK) + +#define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK (0xC0U) +#define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT (6U) +/*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig + * 0b00..Stretch count is zero, no stretch. + * 0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period. + * 0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period. + * 0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period. + */ +#define PWM_MCTRL2_STRETCH_CNT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ + +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) + +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard + * to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be + * cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input + * signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in + * DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and + * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) + +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If + * neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled + * by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without + * regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition + * cannot be cleared. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) + +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ + +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) + +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) + +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +/*! FFPIN - Filtered Fault Pins */ +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) + +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ + +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Fault Filter Period */ +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) + +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Fault Filter Count */ +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) + +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals are stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ + +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ + +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_PWM_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_RTC.h new file mode 100644 index 000000000..1469fb7ed --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_RTC.h @@ -0,0 +1,391 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for RTC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_RTC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for RTC + * + * CMSIS Peripheral Access Layer for RTC + */ + +#if !defined(PERI_RTC_H_) +#define PERI_RTC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t TSR; /**< RTC Time Seconds, offset: 0x0 */ + __IO uint32_t TPR; /**< RTC Time Prescaler, offset: 0x4 */ + __IO uint32_t TAR; /**< RTC Time Alarm, offset: 0x8 */ + __IO uint32_t TCR; /**< RTC Time Compensation, offset: 0xC */ + __IO uint32_t CR; /**< RTC Control, offset: 0x10 */ + __IO uint32_t SR; /**< RTC Status, offset: 0x14 */ + __IO uint32_t LR; /**< RTC Lock, offset: 0x18 */ + __IO uint32_t IER; /**< RTC Interrupt Enable, offset: 0x1C */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name TSR - RTC Time Seconds */ +/*! @{ */ + +#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) +#define RTC_TSR_TSR_SHIFT (0U) +/*! TSR - Time Seconds Register */ +#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) +/*! @} */ + +/*! @name TPR - RTC Time Prescaler */ +/*! @{ */ + +#define RTC_TPR_TPR_MASK (0xFFFFU) +#define RTC_TPR_TPR_SHIFT (0U) +/*! TPR - Time Prescaler Register */ +#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) +/*! @} */ + +/*! @name TAR - RTC Time Alarm */ +/*! @{ */ + +#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) +#define RTC_TAR_TAR_SHIFT (0U) +/*! TAR - Time Alarm Register */ +#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) +/*! @} */ + +/*! @name TCR - RTC Time Compensation */ +/*! @{ */ + +#define RTC_TCR_TCR_MASK (0xFFU) +#define RTC_TCR_TCR_SHIFT (0U) +/*! TCR - Time Compensation Register + * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. + * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. + * 0b01111110..Time Prescaler Register overflows every 32642 clock cycles. + * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles. + * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. + * 0b10000001..Time Prescaler Register overflows every 32895 clock cycles. + * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. + */ +#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) + +#define RTC_TCR_CIR_MASK (0xFF00U) +#define RTC_TCR_CIR_SHIFT (8U) +/*! CIR - Compensation Interval Register */ +#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) + +#define RTC_TCR_TCV_MASK (0xFF0000U) +#define RTC_TCR_TCV_SHIFT (16U) +/*! TCV - Time Compensation Value */ +#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) + +#define RTC_TCR_CIC_MASK (0xFF000000U) +#define RTC_TCR_CIC_SHIFT (24U) +/*! CIC - Compensation Interval Counter */ +#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) +/*! @} */ + +/*! @name CR - RTC Control */ +/*! @{ */ + +#define RTC_CR_SWR_MASK (0x1U) +#define RTC_CR_SWR_SHIFT (0U) +/*! SWR - Software Reset + * 0b0..No effect. + * 0b1..Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. + */ +#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) + +#define RTC_CR_UM_MASK (0x8U) +#define RTC_CR_UM_SHIFT (3U) +/*! UM - Update Mode + * 0b0..Registers cannot be written when locked. + * 0b1..Registers can be written when locked under limited conditions. + */ +#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) + +#define RTC_CR_LPOS_MASK (0x80U) +#define RTC_CR_LPOS_SHIFT (7U) +/*! LPOS - LPO Select + * 0b0..RTC prescaler increments using 32.768 kHz clock. + * 0b1..RTC prescaler increments using 16.384 kHz LPO. Bit [0] of the prescaler is ignored. + */ +#define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK) +/*! @} */ + +/*! @name SR - RTC Status */ +/*! @{ */ + +#define RTC_SR_TIF_MASK (0x1U) +#define RTC_SR_TIF_SHIFT (0U) +/*! TIF - Time Invalid Flag + * 0b0..Time is valid. + * 0b1..Time is invalid and time counter is read as zero. + */ +#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) + +#define RTC_SR_TOF_MASK (0x2U) +#define RTC_SR_TOF_SHIFT (1U) +/*! TOF - Time Overflow Flag + * 0b0..Time overflow has not occurred. + * 0b1..Time overflow has occurred and time counter reads as zero. + */ +#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) + +#define RTC_SR_TAF_MASK (0x4U) +#define RTC_SR_TAF_SHIFT (2U) +/*! TAF - Time Alarm Flag + * 0b0..Time alarm has not occurred. + * 0b1..Time alarm has occurred. + */ +#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) + +#define RTC_SR_TCE_MASK (0x10U) +#define RTC_SR_TCE_SHIFT (4U) +/*! TCE - Time Counter Enable + * 0b0..Disables. + * 0b1..Enables. + */ +#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) +/*! @} */ + +/*! @name LR - RTC Lock */ +/*! @{ */ + +#define RTC_LR_TCL_MASK (0x8U) +#define RTC_LR_TCL_SHIFT (3U) +/*! TCL - Time Compensation Lock + * 0b0..Time Compensation Register is locked and writes are ignored. + * 0b1..Time Compensation Register is not locked and writes complete as normal. + */ +#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) + +#define RTC_LR_CRL_MASK (0x10U) +#define RTC_LR_CRL_SHIFT (4U) +/*! CRL - Control Register Lock + * 0b0..Control Register is locked and writes are ignored. + * 0b1..Control Register is not locked and writes complete as normal. + */ +#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) + +#define RTC_LR_SRL_MASK (0x20U) +#define RTC_LR_SRL_SHIFT (5U) +/*! SRL - Status Register Lock + * 0b0..Status Register is locked and writes are ignored. + * 0b1..Status Register is not locked and writes complete as normal. + */ +#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) + +#define RTC_LR_LRL_MASK (0x40U) +#define RTC_LR_LRL_SHIFT (6U) +/*! LRL - Lock Register Lock + * 0b0..Lock Register is locked and writes are ignored. + * 0b1..Lock Register is not locked and writes complete as normal. + */ +#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) +/*! @} */ + +/*! @name IER - RTC Interrupt Enable */ +/*! @{ */ + +#define RTC_IER_TIIE_MASK (0x1U) +#define RTC_IER_TIIE_SHIFT (0U) +/*! TIIE - Time Invalid Interrupt Enable + * 0b0..No interrupt is generated. + * 0b1..An interrupt is generated. + */ +#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) + +#define RTC_IER_TOIE_MASK (0x2U) +#define RTC_IER_TOIE_SHIFT (1U) +/*! TOIE - Time Overflow Interrupt Enable + * 0b0..No interrupt is generated. + * 0b1..An interrupt is generated. + */ +#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) + +#define RTC_IER_TAIE_MASK (0x4U) +#define RTC_IER_TAIE_SHIFT (2U) +/*! TAIE - Time Alarm Interrupt Enable + * 0b0..No interrupt is generated. + * 0b1..An interrupt is generated. + */ +#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) + +#define RTC_IER_TSIE_MASK (0x10U) +#define RTC_IER_TSIE_SHIFT (4U) +/*! TSIE - Time Seconds Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) + +#define RTC_IER_TSIC_MASK (0x70000U) +#define RTC_IER_TSIC_SHIFT (16U) +/*! TSIC - Timer Seconds Interrupt Configuration + * 0b000..1 Hz. + * 0b001..2 Hz. + * 0b010..4 Hz. + * 0b011..8 Hz. + * 0b100..16 Hz. + * 0b101..32 Hz. + * 0b110..64 Hz. + * 0b111..128 Hz. + */ +#define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_RTC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SCG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SCG.h new file mode 100644 index 000000000..7c44376ea --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SCG.h @@ -0,0 +1,1120 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for SCG +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_SCG.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for SCG + * + * CMSIS Peripheral Access Layer for SCG + */ + +#if !defined(PERI_SCG_H_) +#define PERI_SCG_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer + * @{ + */ + +/** SCG - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t TRIM_LOCK; /**< Trim Lock, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< Clock Status, offset: 0x10 */ + __IO uint32_t RCCR; /**< Run Clock Control, offset: 0x14 */ + uint8_t RESERVED_1[232]; + __IO uint32_t SOSCCSR; /**< SOSC Control Status, offset: 0x100 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOSCCFG; /**< SOSC Configuration, offset: 0x108 */ + uint8_t RESERVED_3[244]; + __IO uint32_t SIRCCSR; /**< SIRC Control Status, offset: 0x200 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration, offset: 0x20C */ + __IO uint32_t SIRCTRIM; /**< SIRC Trim, offset: 0x210 */ + uint8_t RESERVED_5[4]; + __IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status, offset: 0x218 */ + uint8_t RESERVED_6[228]; + __IO uint32_t FIRCCSR; /**< FIRC Control Status, offset: 0x300 */ + uint8_t RESERVED_7[4]; + __IO uint32_t FIRCCFG; /**< FIRC Configuration, offset: 0x308 */ + uint8_t RESERVED_8[4]; + __IO uint32_t FIRCTRIM; /**< FIRC Trim, offset: 0x310 */ + uint8_t RESERVED_9[236]; + __IO uint32_t ROSCCSR; /**< ROSC Control Status, offset: 0x400 */ + uint8_t RESERVED_10[508]; + __IO uint32_t SPLLCSR; /**< SPLL Control Status, offset: 0x600 */ + __IO uint32_t SPLLCTRL; /**< SPLL Control, offset: 0x604 */ + __I uint32_t SPLLSTAT; /**< SPLL Status, offset: 0x608 */ + __IO uint32_t SPLLNDIV; /**< SPLL N Divider, offset: 0x60C */ + __IO uint32_t SPLLMDIV; /**< SPLL M Divider, offset: 0x610 */ + __IO uint32_t SPLLPDIV; /**< SPLL P Divider, offset: 0x614 */ + __IO uint32_t SPLLLOCK_CNFG; /**< SPLL LOCK Configuration, offset: 0x618 */ + uint8_t RESERVED_11[4]; + __I uint32_t SPLLSSCGSTAT; /**< SPLL SSCG Status, offset: 0x620 */ + __IO uint32_t SPLLSSCG0; /**< SPLL Spread Spectrum Control 0, offset: 0x624 */ + __IO uint32_t SPLLSSCG1; /**< SPLL Spread Spectrum Control 1, offset: 0x628 */ + uint8_t RESERVED_12[468]; + __IO uint32_t LDOCSR; /**< LDO Control and Status, offset: 0x800 */ +} SCG_Type; + +/* ---------------------------------------------------------------------------- + -- SCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Register_Masks SCG Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) +#define SCG_VERID_VERSION_SHIFT (0U) +/*! VERSION - SCG Version Number */ +#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define SCG_PARAM_SOSCCLKPRES_MASK (0x2U) +#define SCG_PARAM_SOSCCLKPRES_SHIFT (1U) +/*! SOSCCLKPRES - SOSC Clock Present + * 0b0..SOSC clock source is not present + * 0b1..SOSC clock source is present + */ +#define SCG_PARAM_SOSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK) + +#define SCG_PARAM_SIRCCLKPRES_MASK (0x4U) +#define SCG_PARAM_SIRCCLKPRES_SHIFT (2U) +/*! SIRCCLKPRES - SIRC Clock Present + * 0b0..SIRC clock source is not present + * 0b1..SIRC clock source is present + */ +#define SCG_PARAM_SIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK) + +#define SCG_PARAM_FIRCCLKPRES_MASK (0x8U) +#define SCG_PARAM_FIRCCLKPRES_SHIFT (3U) +/*! FIRCCLKPRES - FIRC Clock Present + * 0b0..FIRC clock source is not present + * 0b1..FIRC clock source is present + */ +#define SCG_PARAM_FIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK) + +#define SCG_PARAM_ROSCCLKPRES_MASK (0x10U) +#define SCG_PARAM_ROSCCLKPRES_SHIFT (4U) +/*! ROSCCLKPRES - ROSC Clock Present + * 0b0..ROSC clock source is not present + * 0b1..ROSC clock source is present + */ +#define SCG_PARAM_ROSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK) + +#define SCG_PARAM_SPLLCLKPRES_MASK (0x40U) +#define SCG_PARAM_SPLLCLKPRES_SHIFT (6U) +/*! SPLLCLKPRES - SPLL Clock Present + * 0b0..SPLL clock source is not present + * 0b1..SPLL clock source is present + */ +#define SCG_PARAM_SPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SPLLCLKPRES_SHIFT)) & SCG_PARAM_SPLLCLKPRES_MASK) +/*! @} */ + +/*! @name TRIM_LOCK - Trim Lock */ +/*! @{ */ + +#define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK (0x1U) +#define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT (0U) +/*! TRIM_UNLOCK - TRIM_UNLOCK + * 0b0..SCG Trim Registers locked and not writable. + * 0b1..SCG Trim registers unlocked and writable. + */ +#define SCG_TRIM_LOCK_TRIM_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK) + +#define SCG_TRIM_LOCK_IFR_DISABLE_MASK (0x2U) +#define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT (1U) +/*! IFR_DISABLE - IFR_DISABLE + * 0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. + * 0b1..IFR write access to SCG trim registers during system reset is blocked. + */ +#define SCG_TRIM_LOCK_IFR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK) + +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK (0xFFFF0000U) +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT (16U) +/*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */ +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK) +/*! @} */ + +/*! @name CSR - Clock Status */ +/*! @{ */ + +#define SCG_CSR_SCS_MASK (0x7000000U) +#define SCG_CSR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b001..SOSC + * 0b010..SIRC + * 0b011..FIRC + * 0b100..ROSC + * 0b110..SPLL + */ +#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) +/*! @} */ + +/*! @name RCCR - Run Clock Control */ +/*! @{ */ + +#define SCG_RCCR_SCS_MASK (0x7000000U) +#define SCG_RCCR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b001..SOSC + * 0b010..SIRC + * 0b011..FIRC + * 0b100..ROSC + * 0b110..SPLL + */ +#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) +/*! @} */ + +/*! @name SOSCCSR - SOSC Control Status */ +/*! @{ */ + +#define SCG_SOSCCSR_SOSCEN_MASK (0x1U) +#define SCG_SOSCCSR_SOSCEN_SHIFT (0U) +/*! SOSCEN - SOSC Enable + * 0b0..SOSC is disabled + * 0b1..SOSC is enabled + */ +#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) + +#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) +#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) +/*! SOSCSTEN - SOSC Stop Enable + * 0b0..SOSC is disabled in Deep Sleep mode + * 0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set + */ +#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) + +#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) +#define SCG_SOSCCSR_SOSCCM_SHIFT (16U) +/*! SOSCCM - SOSC Clock Monitor Enable + * 0b0..SOSC Clock Monitor is disabled + * 0b1..SOSC Clock Monitor is enabled + */ +#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) + +#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) +#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) +/*! SOSCCMRE - SOSC Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) + +#define SCG_SOSCCSR_LK_MASK (0x800000U) +#define SCG_SOSCCSR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..This Control Status Register can be written + * 0b1..This Control Status Register cannot be written + */ +#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) + +#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) +#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) +/*! SOSCVLD - SOSC Valid + * 0b0..SOSC is not enabled or clock is not valid + * 0b1..SOSC is enabled and output clock is valid + */ +#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) + +#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) +#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) +/*! SOSCSEL - SOSC Selected + * 0b0..SOSC is not the system clock source + * 0b1..SOSC is the system clock source + */ +#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) + +#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) +#define SCG_SOSCCSR_SOSCERR_SHIFT (26U) +/*! SOSCERR - SOSC Clock Error + * 0b0..SOSC Clock Monitor is disabled or has not detected an error + * 0b1..SOSC Clock Monitor is enabled and detected an error + */ +#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) + +#define SCG_SOSCCSR_SOSCVLD_IE_MASK (0x40000000U) +#define SCG_SOSCCSR_SOSCVLD_IE_SHIFT (30U) +/*! SOSCVLD_IE - SOSC Valid Interrupt Enable + * 0b0..SOSCVLD interrupt is not enabled + * 0b1..SOSCVLD interrupt is enabled + */ +#define SCG_SOSCCSR_SOSCVLD_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK) +/*! @} */ + +/*! @name SOSCCFG - SOSC Configuration */ +/*! @{ */ + +#define SCG_SOSCCFG_EREFS_MASK (0x4U) +#define SCG_SOSCCFG_EREFS_SHIFT (2U) +/*! EREFS - External Reference Select + * 0b0..External reference clock selected. + * 0b1..Internal crystal oscillator of OSC selected. + */ +#define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) + +#define SCG_SOSCCFG_RANGE_MASK (0x30U) +#define SCG_SOSCCFG_RANGE_SHIFT (4U) +/*! RANGE - SOSC Range Select + * 0b00..Frequency range select of 8-16 MHz. + * 0b01..Frequency range select of 16-25 MHz. + * 0b10..Frequency range select of 25-40 MHz. + * 0b11..Frequency range select of 40-50 MHz. + */ +#define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) +/*! @} */ + +/*! @name SIRCCSR - SIRC Control Status */ +/*! @{ */ + +#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) +#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) +/*! SIRCSTEN - SIRC Stop Enable + * 0b0..SIRC is disabled in Deep Sleep mode + * 0b1..SIRC is enabled in Deep Sleep mode + */ +#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) + +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK (0x20U) +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT (5U) +/*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable + * 0b0..SIRC clock to peripherals is disabled + * 0b1..SIRC clock to peripherals is enabled + */ +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) + +#define SCG_SIRCCSR_SIRCTREN_MASK (0x100U) +#define SCG_SIRCCSR_SIRCTREN_SHIFT (8U) +/*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1) + * 0b0..Disables trimming SIRC to an external clock source + * 0b1..Enables trimming SIRC to an external clock source + */ +#define SCG_SIRCCSR_SIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK) + +#define SCG_SIRCCSR_SIRCTRUP_MASK (0x200U) +#define SCG_SIRCCSR_SIRCTRUP_SHIFT (9U) +/*! SIRCTRUP - SIRC Trim Update + * 0b0..Disables SIRC trimming updates + * 0b1..Enables SIRC trimming updates + */ +#define SCG_SIRCCSR_SIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK) + +#define SCG_SIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_SIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - SIRC TRIM LOCK + * 0b0..SIRC auto trim not locked to target frequency range + * 0b1..SIRC auto trim locked to target frequency range + */ +#define SCG_SIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK) + +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..SIRC Coarse Auto Trim NOT Bypassed + * 0b1..SIRC Coarse Auto Trim Bypassed + */ +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_SIRCCSR_LK_MASK (0x800000U) +#define SCG_SIRCCSR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) + +#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) +#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) +/*! SIRCVLD - SIRC Valid + * 0b0..SIRC is not enabled or clock is not valid + * 0b1..SIRC is enabled and output clock is valid + */ +#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) + +#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) +#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) +/*! SIRCSEL - SIRC Selected + * 0b0..SIRC is not the system clock source + * 0b1..SIRC is the system clock source + */ +#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) + +#define SCG_SIRCCSR_SIRCERR_MASK (0x4000000U) +#define SCG_SIRCCSR_SIRCERR_SHIFT (26U) +/*! SIRCERR - SIRC Clock Error + * 0b0..Error not detected with the SIRC trimming + * 0b1..Error detected with the SIRC trimming + */ +#define SCG_SIRCCSR_SIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK) + +#define SCG_SIRCCSR_SIRCERR_IE_MASK (0x8000000U) +#define SCG_SIRCCSR_SIRCERR_IE_SHIFT (27U) +/*! SIRCERR_IE - SIRC Clock Error Interrupt Enable + * 0b0..SIRCERR interrupt is not enabled + * 0b1..SIRCERR interrupt is enabled + */ +#define SCG_SIRCCSR_SIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK) +/*! @} */ + +/*! @name SIRCTCFG - SIRC Trim Configuration */ +/*! @{ */ + +#define SCG_SIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_SIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..Reserved + * 0b01..Reserved + * 0b10..SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. + * 0b11..Reserved + */ +#define SCG_SIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK) + +#define SCG_SIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_SIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - SIRC Trim Pre-divider */ +#define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name SIRCTRIM - SIRC Trim */ +/*! @{ */ + +#define SCG_SIRCTRIM_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCTRIM_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCTRIM_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK) + +#define SCG_SIRCTRIM_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCTRIM_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCTRIM_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK) + +#define SCG_SIRCTRIM_TCTRIM_MASK (0x1F0000U) +#define SCG_SIRCTRIM_TCTRIM_SHIFT (16U) +/*! TCTRIM - Trim Temp */ +#define SCG_SIRCTRIM_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK) + +#define SCG_SIRCTRIM_FVCHTRIM_MASK (0x1F000000U) +#define SCG_SIRCTRIM_FVCHTRIM_SHIFT (24U) +#define SCG_SIRCTRIM_FVCHTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK) +/*! @} */ + +/*! @name SIRCSTAT - SIRC Auto-trimming Status */ +/*! @{ */ + +#define SCG_SIRCSTAT_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCSTAT_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCSTAT_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK) + +#define SCG_SIRCSTAT_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCSTAT_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCSTAT_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK) +/*! @} */ + +/*! @name FIRCCSR - FIRC Control Status */ +/*! @{ */ + +#define SCG_FIRCCSR_FIRCEN_MASK (0x1U) +#define SCG_FIRCCSR_FIRCEN_SHIFT (0U) +/*! FIRCEN - FIRC Enable + * 0b0..FIRC is disabled + * 0b1..FIRC is enabled + */ +#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) + +#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) +#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) +/*! FIRCSTEN - FIRC Stop Enable + * 0b0..FIRC is disabled in Deep Sleep mode + * 0b1..FIRC is enabled in Deep Sleep mode + */ +#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) + +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK (0x10U) +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT (4U) +/*! FIRC_SCLK_PERIPH_EN - FIRC 45 MHz Clock to peripherals Enable + * 0b0..FIRC 45 MHz to peripherals is disabled + * 0b1..FIRC 45 MHz to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK (0x20U) +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT (5U) +/*! FIRC_FCLK_PERIPH_EN - FRO_HF Clock to peripherals Enable + * 0b0..FRO_HF to peripherals is disabled + * 0b1..FRO_HF to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_LK_MASK (0x800000U) +#define SCG_FIRCCSR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) + +#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) +#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) +/*! FIRCVLD - FIRC Valid status + * 0b0..FIRC is not enabled or clock is not valid. + * 0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. + */ +#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) + +#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) +#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) +/*! FIRCSEL - FIRC Selected + * 0b0..FIRC is not the system clock source + * 0b1..FIRC is the system clock source + */ +#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) + +#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) +#define SCG_FIRCCSR_FIRCERR_SHIFT (26U) +/*! FIRCERR - FIRC Clock Error + * 0b0..Error not detected with the FIRC trimming + * 0b1..Error detected with the FIRC trimming + */ +#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) + +#define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) +#define SCG_FIRCCSR_FIRCERR_IE_SHIFT (27U) +/*! FIRCERR_IE - FIRC Clock Error Interrupt Enable + * 0b0..FIRCERR interrupt is not enabled + * 0b1..FIRCERR interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_IE_MASK (0x40000000U) +#define SCG_FIRCCSR_FIRCACC_IE_SHIFT (30U) +/*! FIRCACC_IE - FIRC Accurate Interrupt Enable + * 0b0..FIRCACC interrupt is not enabled + * 0b1..FIRCACC interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCACC_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_MASK (0x80000000U) +#define SCG_FIRCCSR_FIRCACC_SHIFT (31U) +/*! FIRCACC - FIRC Frequency Accurate + * 0b0..FIRC is not enabled or clock is not accurate. + * 0b1..FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock. + */ +#define SCG_FIRCCSR_FIRCACC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK) +/*! @} */ + +/*! @name FIRCCFG - FIRC Configuration */ +/*! @{ */ + +#define SCG_FIRCCFG_FREQ_SEL_MASK (0xEU) +#define SCG_FIRCCFG_FREQ_SEL_SHIFT (1U) +/*! FREQ_SEL - Frequency select + * 0b001..45 MHz FIRC clock selected, divided from 180 MHz + * 0b010..80MHz FIRC clock selected + * 0b011..60 MHz FIRC clock selected + * 0b100..120MHz FIRC clock selected + * 0b101..90 MHz FIRC clock selected + * 0b110..240MHz FIRC clock selected + * 0b111..180 MHz FIRC clock selected + */ +#define SCG_FIRCCFG_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_FREQ_SEL_SHIFT)) & SCG_FIRCCFG_FREQ_SEL_MASK) +/*! @} */ + +/*! @name FIRCTRIM - FIRC Trim */ +/*! @{ */ + +#define SCG_FIRCTRIM_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCTRIM_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCTRIM_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK) + +#define SCG_FIRCTRIM_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCTRIM_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCTRIM_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK) + +#define SCG_FIRCTRIM_TRIMTEMP_MASK (0xF0000U) +#define SCG_FIRCTRIM_TRIMTEMP_SHIFT (16U) +/*! TRIMTEMP - Trim Temperature */ +#define SCG_FIRCTRIM_TRIMTEMP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP_MASK) + +#define SCG_FIRCTRIM_TRIMSTART_MASK (0x3F000000U) +#define SCG_FIRCTRIM_TRIMSTART_SHIFT (24U) +/*! TRIMSTART - Trim Start */ +#define SCG_FIRCTRIM_TRIMSTART(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK) +/*! @} */ + +/*! @name ROSCCSR - ROSC Control Status */ +/*! @{ */ + +#define SCG_ROSCCSR_LK_MASK (0x800000U) +#define SCG_ROSCCSR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) + +#define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) +#define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) +/*! ROSCVLD - ROSC Valid + * 0b0..ROSC is not enabled or clock is not valid + * 0b1..ROSC is enabled and output clock is valid + */ +#define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) + +#define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) +#define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) +/*! ROSCSEL - ROSC Selected + * 0b0..ROSC is not the system clock source + * 0b1..ROSC is the system clock source + */ +#define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) + +#define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) +#define SCG_ROSCCSR_ROSCERR_SHIFT (26U) +/*! ROSCERR - ROSC Clock Error + * 0b0..ROSC Clock has not detected an error + * 0b1..ROSC Clock has detected an error + */ +#define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) +/*! @} */ + +/*! @name SPLLCSR - SPLL Control Status */ +/*! @{ */ + +#define SCG_SPLLCSR_SPLLPWREN_MASK (0x1U) +#define SCG_SPLLCSR_SPLLPWREN_SHIFT (0U) +/*! SPLLPWREN - SPLL Power Enable + * 0b0..SPLL clock is powered off + * 0b1..SPLL clock is powered on + */ +#define SCG_SPLLCSR_SPLLPWREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLPWREN_SHIFT)) & SCG_SPLLCSR_SPLLPWREN_MASK) + +#define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) +#define SCG_SPLLCSR_SPLLCLKEN_SHIFT (1U) +/*! SPLLCLKEN - SPLL Clock Enable + * 0b0..SPLL clock is disabled + * 0b1..SPLL clock is enabled + */ +#define SCG_SPLLCSR_SPLLCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK) + +#define SCG_SPLLCSR_SPLLSTEN_MASK (0x4U) +#define SCG_SPLLCSR_SPLLSTEN_SHIFT (2U) +/*! SPLLSTEN - SPLL Stop Enable + * 0b0..SPLL is disabled in Deep Sleep mode + * 0b1..SPLL is enabled in Deep Sleep mode + */ +#define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK) + +#define SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) +#define SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) +/*! FRM_CLOCKSTABLE - Free running mode clock stable + * 0b0..Free running mode clock stable is disabled + * 0b1..Free running mode clock stable is enabled + */ +#define SCG_SPLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK) + +#define SCG_SPLLCSR_SPLLCM_MASK (0x10000U) +#define SCG_SPLLCSR_SPLLCM_SHIFT (16U) +/*! SPLLCM - SPLL Clock Monitor + * 0b0..SPLL Clock Monitor is disabled + * 0b1..SPLL Clock Monitor is enabled + */ +#define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCM_SHIFT)) & SCG_SPLLCSR_SPLLCM_MASK) + +#define SCG_SPLLCSR_SPLLCMRE_MASK (0x20000U) +#define SCG_SPLLCSR_SPLLCMRE_SHIFT (17U) +/*! SPLLCMRE - SPLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCMRE_SHIFT)) & SCG_SPLLCSR_SPLLCMRE_MASK) + +#define SCG_SPLLCSR_LK_MASK (0x800000U) +#define SCG_SPLLCSR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK) + +#define SCG_SPLLCSR_SPLL_LOCK_MASK (0x1000000U) +#define SCG_SPLLCSR_SPLL_LOCK_SHIFT (24U) +/*! SPLL_LOCK - SPLL LOCK + * 0b0..SPLL is not powered on or not locked + * 0b1..SPLL is locked + */ +#define SCG_SPLLCSR_SPLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_MASK) + +#define SCG_SPLLCSR_SPLLSEL_MASK (0x2000000U) +#define SCG_SPLLCSR_SPLLSEL_SHIFT (25U) +/*! SPLLSEL - SPLL Selected + * 0b0..SPLL is not the system clock source + * 0b1..SPLL is the system clock source + */ +#define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK) + +#define SCG_SPLLCSR_SPLLERR_MASK (0x4000000U) +#define SCG_SPLLCSR_SPLLERR_SHIFT (26U) +/*! SPLLERR - SPLL Clock Error + * 0b0..SPLL Clock Monitor is disabled or has not detected an error + * 0b1..SPLL Clock Monitor is enabled and detected an error + */ +#define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK) + +#define SCG_SPLLCSR_SPLL_LOCK_IE_MASK (0x40000000U) +#define SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT (30U) +/*! SPLL_LOCK_IE - SPLL LOCK Interrupt Enable + * 0b0..SPLL_LOCK interrupt is not enabled + * 0b1..SPLL_LOCK interrupt is enabled + */ +#define SCG_SPLLCSR_SPLL_LOCK_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_IE_MASK) +/*! @} */ + +/*! @name SPLLCTRL - SPLL Control */ +/*! @{ */ + +#define SCG_SPLLCTRL_SELR_MASK (0xFU) +#define SCG_SPLLCTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R (resistor) value. */ +#define SCG_SPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK) + +#define SCG_SPLLCTRL_SELI_MASK (0x3F0U) +#define SCG_SPLLCTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I (interation) value. */ +#define SCG_SPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELI_SHIFT)) & SCG_SPLLCTRL_SELI_MASK) + +#define SCG_SPLLCTRL_SELP_MASK (0x7C00U) +#define SCG_SPLLCTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P (proportional) value. */ +#define SCG_SPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELP_SHIFT)) & SCG_SPLLCTRL_SELP_MASK) + +#define SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - Bypass of the divide-by-2 divider + * 0b0..Use the divide-by-2 divider in the post-divider. + * 0b1..Bypass of the divide-by-2 divider in the post-divider. + */ +#define SCG_SPLLCTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) + +#define SCG_SPLLCTRL_LIMUPOFF_MASK (0x20000U) +#define SCG_SPLLCTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - Up Limiter. + * 0b0..Application set to non Spectrum and Fractional applications. + * 0b1..Application set to Spectrum and Fractional applications. + */ +#define SCG_SPLLCTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_LIMUPOFF_SHIFT)) & SCG_SPLLCTRL_LIMUPOFF_MASK) + +#define SCG_SPLLCTRL_BANDDIRECT_MASK (0x40000U) +#define SCG_SPLLCTRL_BANDDIRECT_SHIFT (18U) +/*! BANDDIRECT - Control of the bandwidth of the PLL. + * 0b0..The bandwidth is changed synchronously with the feedback-divider + * 0b1..Modifies the bandwidth of the PLL directly + */ +#define SCG_SPLLCTRL_BANDDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BANDDIRECT_SHIFT)) & SCG_SPLLCTRL_BANDDIRECT_MASK) + +#define SCG_SPLLCTRL_BYPASSPREDIV_MASK (0x80000U) +#define SCG_SPLLCTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - Bypass of the pre-divider. + * 0b0..Use the pre-divider + * 0b1..Bypass of the pre-divider + */ +#define SCG_SPLLCTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPREDIV_MASK) + +#define SCG_SPLLCTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - Bypass of the post-divider. + * 0b0..Use the post-divider + * 0b1..Bypass of the post-divider + */ +#define SCG_SPLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) + +#define SCG_SPLLCTRL_FRM_MASK (0x400000U) +#define SCG_SPLLCTRL_FRM_SHIFT (22U) +/*! FRM - Free Running Mode Enable + * 0b0..Free running mode disabled + * 0b1..Free running mode enabled + */ +#define SCG_SPLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_FRM_SHIFT)) & SCG_SPLLCTRL_FRM_MASK) + +#define SCG_SPLLCTRL_SOURCE_MASK (0x6000000U) +#define SCG_SPLLCTRL_SOURCE_SHIFT (25U) +/*! SOURCE - Clock Source + * 0b00..SOSC + * 0b01..FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock. + * 0b10..ROSC + * 0b11..SIRC 12 MHz clock + */ +#define SCG_SPLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SOURCE_SHIFT)) & SCG_SPLLCTRL_SOURCE_MASK) +/*! @} */ + +/*! @name SPLLSTAT - SPLL Status */ +/*! @{ */ + +#define SCG_SPLLSTAT_NDIVACK_MASK (0x2U) +#define SCG_SPLLSTAT_NDIVACK_SHIFT (1U) +/*! NDIVACK - Pre-divider (N) ratio change acknowledge + * 0b0..The Pre-divider (N) ratio change is not accepted by the analog PLL. + * 0b1..The Pre-divider (N) ratio change is accepted by the analog PLL. + */ +#define SCG_SPLLSTAT_NDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_NDIVACK_SHIFT)) & SCG_SPLLSTAT_NDIVACK_MASK) + +#define SCG_SPLLSTAT_MDIVACK_MASK (0x4U) +#define SCG_SPLLSTAT_MDIVACK_SHIFT (2U) +/*! MDIVACK - Feedback (M) divider ratio change acknowledge + * 0b0..The Feedback (M) ratio change is not accepted by the analog PLL. + * 0b1..The Feedback (M) ratio change is accepted by the analog PLL. + */ +#define SCG_SPLLSTAT_MDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_MDIVACK_SHIFT)) & SCG_SPLLSTAT_MDIVACK_MASK) + +#define SCG_SPLLSTAT_PDIVACK_MASK (0x8U) +#define SCG_SPLLSTAT_PDIVACK_SHIFT (3U) +/*! PDIVACK - Post-divider (P) ratio change acknowledge + * 0b0..The Post-divider (P) ratio change is not accepted by the analog PLL + * 0b1..The Post-divider (P) ratio change is accepted by the analog PLL + */ +#define SCG_SPLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_PDIVACK_SHIFT)) & SCG_SPLLSTAT_PDIVACK_MASK) + +#define SCG_SPLLSTAT_FRMDET_MASK (0x10U) +#define SCG_SPLLSTAT_FRMDET_SHIFT (4U) +/*! FRMDET - Free running detector (active high) + * 0b0..Free running is not detected + * 0b1..Free running is detected + */ +#define SCG_SPLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_FRMDET_SHIFT)) & SCG_SPLLSTAT_FRMDET_MASK) +/*! @} */ + +/*! @name SPLLNDIV - SPLL N Divider */ +/*! @{ */ + +#define SCG_SPLLNDIV_NDIV_MASK (0xFFU) +#define SCG_SPLLNDIV_NDIV_SHIFT (0U) +/*! NDIV - Pre-divider divider ratio (N-divider). */ +#define SCG_SPLLNDIV_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NDIV_SHIFT)) & SCG_SPLLNDIV_NDIV_MASK) + +#define SCG_SPLLNDIV_NREQ_MASK (0x80000000U) +#define SCG_SPLLNDIV_NREQ_SHIFT (31U) +/*! NREQ - Pre-divider ratio change request. + * 0b0..Pre-divider ratio change is not requested + * 0b1..Pre-divider ratio change is requested + */ +#define SCG_SPLLNDIV_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NREQ_SHIFT)) & SCG_SPLLNDIV_NREQ_MASK) +/*! @} */ + +/*! @name SPLLMDIV - SPLL M Divider */ +/*! @{ */ + +#define SCG_SPLLMDIV_MDIV_MASK (0xFFFFU) +#define SCG_SPLLMDIV_MDIV_SHIFT (0U) +/*! MDIV - Feedback divider ratio (M-divider). */ +#define SCG_SPLLMDIV_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MDIV_SHIFT)) & SCG_SPLLMDIV_MDIV_MASK) + +#define SCG_SPLLMDIV_MREQ_MASK (0x80000000U) +#define SCG_SPLLMDIV_MREQ_SHIFT (31U) +/*! MREQ - Feedback ratio change request. + * 0b0..Feedback ratio change is not requested + * 0b1..Feedback ratio change is requested + */ +#define SCG_SPLLMDIV_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MREQ_SHIFT)) & SCG_SPLLMDIV_MREQ_MASK) +/*! @} */ + +/*! @name SPLLPDIV - SPLL P Divider */ +/*! @{ */ + +#define SCG_SPLLPDIV_PDIV_MASK (0x1FU) +#define SCG_SPLLPDIV_PDIV_SHIFT (0U) +/*! PDIV - Post-divider divider ratio (P-divider) */ +#define SCG_SPLLPDIV_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PDIV_SHIFT)) & SCG_SPLLPDIV_PDIV_MASK) + +#define SCG_SPLLPDIV_PREQ_MASK (0x80000000U) +#define SCG_SPLLPDIV_PREQ_SHIFT (31U) +/*! PREQ - Post-divider ratio change request + * 0b0..Post-divider ratio change is not requested + * 0b1..Post-divider ratio change is requested + */ +#define SCG_SPLLPDIV_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PREQ_SHIFT)) & SCG_SPLLPDIV_PREQ_MASK) +/*! @} */ + +/*! @name SPLLLOCK_CNFG - SPLL LOCK Configuration */ +/*! @{ */ + +#define SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK (0x1FFFFU) +#define SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) +/*! LOCK_TIME - Configures the number of reference clocks to count before SPLL is considered locked. */ +#define SCG_SPLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK) +/*! @} */ + +/*! @name SPLLSSCGSTAT - SPLL SSCG Status */ +/*! @{ */ + +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK (0x1U) +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT (0U) +/*! SS_MDIV_ACK - SS_MDIV change acknowledge + * 0b0..The SS_MDIV, MF, MR, MC ratio change is not accepted by the analog PLL + * 0b1..The SS_MDIV, MF, MR, MC ratio change is accepted by the analog PLL + */ +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK) +/*! @} */ + +/*! @name SPLLSSCG0 - SPLL Spread Spectrum Control 0 */ +/*! @{ */ + +#define SCG_SPLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) +#define SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT (0U) +/*! SS_MDIV_LSB - SS_MDIV[31:0] */ +#define SCG_SPLLSSCG0_SS_MDIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_SPLLSSCG0_SS_MDIV_LSB_MASK) +/*! @} */ + +/*! @name SPLLSSCG1 - SPLL Spread Spectrum Control 1 */ +/*! @{ */ + +#define SCG_SPLLSSCG1_SS_MDIV_MSB_MASK (0x1U) +#define SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT (0U) +/*! SS_MDIV_MSB - SS_MDIV[32] */ +#define SCG_SPLLSSCG1_SS_MDIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) + +#define SCG_SPLLSSCG1_SS_MDIV_REQ_MASK (0x2U) +#define SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT (1U) +/*! SS_MDIV_REQ - SS_MDIV[32:0] change request. + * 0b0..SS_MDIV change is not requested + * 0b1..SS_MDIV change is requested + */ +#define SCG_SPLLSSCG1_SS_MDIV_REQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_REQ_MASK) + +#define SCG_SPLLSSCG1_MF_MASK (0x1CU) +#define SCG_SPLLSSCG1_MF_SHIFT (2U) +/*! MF - Modulation Frequency Control */ +#define SCG_SPLLSSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MF_SHIFT)) & SCG_SPLLSSCG1_MF_MASK) + +#define SCG_SPLLSSCG1_MR_MASK (0xE0U) +#define SCG_SPLLSSCG1_MR_SHIFT (5U) +/*! MR - Modulation Depth Control */ +#define SCG_SPLLSSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MR_SHIFT)) & SCG_SPLLSSCG1_MR_MASK) + +#define SCG_SPLLSSCG1_MC_MASK (0x300U) +#define SCG_SPLLSSCG1_MC_SHIFT (8U) +/*! MC - Modulation Waveform Control */ +#define SCG_SPLLSSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MC_SHIFT)) & SCG_SPLLSSCG1_MC_MASK) + +#define SCG_SPLLSSCG1_DITHER_MASK (0x400U) +#define SCG_SPLLSSCG1_DITHER_SHIFT (10U) +/*! DITHER - Dither Enable + * 0b0..Dither is not enabled + * 0b1..Dither is enabled + */ +#define SCG_SPLLSSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_DITHER_SHIFT)) & SCG_SPLLSSCG1_DITHER_MASK) + +#define SCG_SPLLSSCG1_SEL_SS_MDIV_MASK (0x800U) +#define SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT (11U) +/*! SEL_SS_MDIV - SS_MDIV select. + * 0b0..Feedback divider ratio is MDIV[15:0] + * 0b1..Feedback divider ratio is SS_MDIV[32:0] + */ +#define SCG_SPLLSSCG1_SEL_SS_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) + +#define SCG_SPLLSSCG1_SS_PD_MASK (0x80000000U) +#define SCG_SPLLSSCG1_SS_PD_SHIFT (31U) +/*! SS_PD - SSCG Power Down + * 0b0..SSCG is powered on + * 0b1..SSCG is powered off + */ +#define SCG_SPLLSSCG1_SS_PD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_PD_SHIFT)) & SCG_SPLLSSCG1_SS_PD_MASK) +/*! @} */ + +/*! @name LDOCSR - LDO Control and Status */ +/*! @{ */ + +#define SCG_LDOCSR_LDOEN_MASK (0x1U) +#define SCG_LDOCSR_LDOEN_SHIFT (0U) +/*! LDOEN - LDO Enable + * 0b0..LDO is disabled + * 0b1..LDO is enabled + */ +#define SCG_LDOCSR_LDOEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOEN_SHIFT)) & SCG_LDOCSR_LDOEN_MASK) + +#define SCG_LDOCSR_VOUT_SEL_MASK (0xEU) +#define SCG_LDOCSR_VOUT_SEL_SHIFT (1U) +/*! VOUT_SEL - LDO output voltage select + * 0b000..VOUT = 1V + * 0b001..VOUT = 1V + * 0b010..VOUT = 1V + * 0b011..VOUT = 1.05V + * 0b100..VOUT = 1.1V + * 0b101..VOUT = 1.15V + * 0b110..VOUT = 1.2V + * 0b111..VOUT = 1.25V + */ +#define SCG_LDOCSR_VOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_SEL_SHIFT)) & SCG_LDOCSR_VOUT_SEL_MASK) + +#define SCG_LDOCSR_LDOBYPASS_MASK (0x10U) +#define SCG_LDOCSR_LDOBYPASS_SHIFT (4U) +/*! LDOBYPASS - LDO Bypass + * 0b0..LDO is not bypassed + * 0b1..LDO is bypassed + */ +#define SCG_LDOCSR_LDOBYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOBYPASS_SHIFT)) & SCG_LDOCSR_LDOBYPASS_MASK) + +#define SCG_LDOCSR_VOUT_OK_MASK (0x80000000U) +#define SCG_LDOCSR_VOUT_OK_SHIFT (31U) +/*! VOUT_OK - LDO VOUT OK Inform. + * 0b0..LDO output VOUT is not OK + * 0b1..LDO output VOUT is OK + */ +#define SCG_LDOCSR_VOUT_OK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SCG_Register_Masks */ + + +/*! + * @} + */ /* end of group SCG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SCG_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SGI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SGI.h new file mode 100644 index 000000000..56aea5977 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SGI.h @@ -0,0 +1,1562 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for SGI +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_SGI.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for SGI + * + * CMSIS Peripheral Access Layer for SGI + */ + +#if !defined(PERI_SGI_H_) +#define PERI_SGI_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SGI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SGI_Peripheral_Access_Layer SGI Peripheral Access Layer + * @{ + */ + +/** SGI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[512]; + __IO uint32_t SGI_DATIN0A; /**< Input Data register 0 - Word-3, offset: 0x200 */ + __IO uint32_t SGI_DATIN0B; /**< Input Data register 0 - Word-2, offset: 0x204 */ + __IO uint32_t SGI_DATIN0C; /**< Input Data register 0 - Word-1, offset: 0x208 */ + __IO uint32_t SGI_DATIN0D; /**< Input Data register 0 - Word-0, offset: 0x20C */ + __IO uint32_t SGI_DATIN1A; /**< Input Data register 1 - Word-3, offset: 0x210 */ + __IO uint32_t SGI_DATIN1B; /**< Input Data register 1 - Word-2, offset: 0x214 */ + __IO uint32_t SGI_DATIN1C; /**< Input Data register 1 - Word-1, offset: 0x218 */ + __IO uint32_t SGI_DATIN1D; /**< Input Data register 1 - Word-0, offset: 0x21C */ + __IO uint32_t SGI_DATIN2A; /**< Input Data register 2 - Word-3, offset: 0x220 */ + __IO uint32_t SGI_DATIN2B; /**< Input Data register 2 - Word-2, offset: 0x224 */ + __IO uint32_t SGI_DATIN2C; /**< Input Data register 2 - Word-1, offset: 0x228 */ + __IO uint32_t SGI_DATIN2D; /**< Input Data register 2 - Word-0, offset: 0x22C */ + __IO uint32_t SGI_DATIN3A; /**< Input Data register 3 - Word-3, offset: 0x230 */ + __IO uint32_t SGI_DATIN3B; /**< Input Data register 3 - Word-2, offset: 0x234 */ + __IO uint32_t SGI_DATIN3C; /**< Input Data register 3 - Word-1, offset: 0x238 */ + __IO uint32_t SGI_DATIN3D; /**< Input Data register 3 - Word-0, offset: 0x23C */ + __IO uint32_t SGI_KEY0A; /**< Input Key register 0 - Word-3, offset: 0x240 */ + __IO uint32_t SGI_KEY0B; /**< Input Key register 0 - Word-2, offset: 0x244 */ + __IO uint32_t SGI_KEY0C; /**< Input Key register 0 - Word-1, offset: 0x248 */ + __IO uint32_t SGI_KEY0D; /**< Input Key register 0 - Word-0, offset: 0x24C */ + __IO uint32_t SGI_KEY1A; /**< Input Key register 1 - Word-3, offset: 0x250 */ + __IO uint32_t SGI_KEY1B; /**< Input Key register 1 - Word-2, offset: 0x254 */ + __IO uint32_t SGI_KEY1C; /**< Input Key register 1 - Word-1, offset: 0x258 */ + __IO uint32_t SGI_KEY1D; /**< Input Key register 1 - Word-0, offset: 0x25C */ + __IO uint32_t SGI_KEY2A; /**< Input Key register 2 - Word-3, offset: 0x260 */ + __IO uint32_t SGI_KEY2B; /**< Input Key register 2 - Word-2, offset: 0x264 */ + __IO uint32_t SGI_KEY2C; /**< Input Key register 2 - Word-1, offset: 0x268 */ + __IO uint32_t SGI_KEY2D; /**< Input Key register 2 - Word-0, offset: 0x26C */ + __IO uint32_t SGI_KEY3A; /**< Input Key register 3 - Word-3, offset: 0x270 */ + __IO uint32_t SGI_KEY3B; /**< Input Key register 3 - Word-2, offset: 0x274 */ + __IO uint32_t SGI_KEY3C; /**< Input Key register 3 - Word-1, offset: 0x278 */ + __IO uint32_t SGI_KEY3D; /**< Input Key register 3 - Word-0, offset: 0x27C */ + __IO uint32_t SGI_KEY4A; /**< Input Key register 4 - Word-3, offset: 0x280 */ + __IO uint32_t SGI_KEY4B; /**< Input Key register 4 - Word-2, offset: 0x284 */ + __IO uint32_t SGI_KEY4C; /**< Input Key register 4 - Word-1, offset: 0x288 */ + __IO uint32_t SGI_KEY4D; /**< Input Key register 4 - Word-0, offset: 0x28C */ + __IO uint32_t SGI_KEY5A; /**< Input Key register 5 - Word-3, offset: 0x290 */ + __IO uint32_t SGI_KEY5B; /**< Input Key register 5 - Word-2, offset: 0x294 */ + __IO uint32_t SGI_KEY5C; /**< Input Key register 5 - Word-1, offset: 0x298 */ + __IO uint32_t SGI_KEY5D; /**< Input Key register 5 - Word-0, offset: 0x29C */ + __IO uint32_t SGI_KEY6A; /**< Input Key register 6 - Word-3, offset: 0x2A0 */ + __IO uint32_t SGI_KEY6B; /**< Input Key register 6 - Word-2, offset: 0x2A4 */ + __IO uint32_t SGI_KEY6C; /**< Input Key register 6 - Word-1, offset: 0x2A8 */ + __IO uint32_t SGI_KEY6D; /**< Input Key register 6 - Word-0, offset: 0x2AC */ + __IO uint32_t SGI_KEY7A; /**< Input Key register 7 - Word-3, offset: 0x2B0 */ + __IO uint32_t SGI_KEY7B; /**< Input Key register 7 - Word-2, offset: 0x2B4 */ + __IO uint32_t SGI_KEY7C; /**< Input Key register 7 - Word-1, offset: 0x2B8 */ + __IO uint32_t SGI_KEY7D; /**< Input Key register 7 - Word-0, offset: 0x2BC */ + __IO uint32_t SGI_DATOUTA; /**< Output Data register - Word-3, offset: 0x2C0 */ + __IO uint32_t SGI_DATOUTB; /**< Output Data register - Word-2, offset: 0x2C4 */ + __IO uint32_t SGI_DATOUTC; /**< Output Data register - Word-1, offset: 0x2C8 */ + __IO uint32_t SGI_DATOUTD; /**< Output Data register - Word-0, offset: 0x2CC */ + uint8_t RESERVED_1[2352]; + __IO uint32_t SGI_STATUS; /**< Status register, offset: 0xC00 */ + __IO uint32_t SGI_COUNT; /**< Calculation counter, offset: 0xC04 */ + __IO uint32_t SGI_KEYCHK; /**< Key checksum register, offset: 0xC08 */ + uint8_t RESERVED_2[244]; + __IO uint32_t SGI_CTRL; /**< SGI Control register, offset: 0xD00 */ + __IO uint32_t SGI_CTRL2; /**< SGI Control register 2, offset: 0xD04 */ + __IO uint32_t SGI_DUMMY_CTRL; /**< Configuration of dummy controls, offset: 0xD08 */ + __IO uint32_t SGI_SFR_SW_MASK; /**< Sofware Assisted Masking register, offset: 0xD0C */ + __IO uint32_t SGI_SFRSEED; /**< SFRSEED register for SFRMASK feature, offset: 0xD10 */ + __IO uint32_t SGI_SHA2_CTRL; /**< SHA Control Register, offset: 0xD14 */ + __IO uint32_t SGI_SHA_FIFO; /**< SHA FIFO lower-bank low, offset: 0xD18 */ + __I uint32_t SGI_CONFIG; /**< SHA Configuration Reg, offset: 0xD1C */ + __I uint32_t SGI_CONFIG2; /**< SHA Configuration 2 Reg, offset: 0xD20 */ + __IO uint32_t SGI_AUTO_MODE; /**< SGI Auto Mode Control register, offset: 0xD24 */ + __IO uint32_t SGI_AUTO_DMA_CTRL; /**< SGI Auto Mode Control register, offset: 0xD28 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SGI_PRNG_SW_SEED; /**< SGI internal PRNG SW seeding register, offset: 0xD30 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SGI_KEY_CTRL; /**< SGI Key Control SFR, offset: 0xD40 */ + uint8_t RESERVED_5[12]; + __I uint32_t SGI_KEY_WRAP; /**< Wrapped key read SFR, offset: 0xD50 */ + uint8_t RESERVED_6[436]; + __I uint32_t SGI_VERSION; /**< SGI Version, offset: 0xF08 */ + uint8_t RESERVED_7[180]; + __IO uint32_t SGI_ACCESS_ERR; /**< Access Error, offset: 0xFC0 */ + __IO uint32_t SGI_ACCESS_ERR_CLR; /**< Clear Access Error, offset: 0xFC4 */ + uint8_t RESERVED_8[24]; + __I uint32_t SGI_INT_STATUS; /**< Interrupt status, offset: 0xFE0 */ + __IO uint32_t SGI_INT_ENABLE; /**< Interrupt enable, offset: 0xFE4 */ + __IO uint32_t SGI_INT_STATUS_CLR; /**< Interrupt status clear, offset: 0xFE8 */ + __IO uint32_t SGI_INT_STATUS_SET; /**< Interrupt status set, offset: 0xFEC */ + uint8_t RESERVED_9[12]; + __I uint32_t SGI_MODULE_ID; /**< Module ID, offset: 0xFFC */ +} SGI_Type; + +/* ---------------------------------------------------------------------------- + -- SGI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SGI_Register_Masks SGI Register Masks + * @{ + */ + +/*! @name SGI_DATIN0A - Input Data register 0 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_DATIN0A_DATIN0A_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN0A_DATIN0A_SHIFT (0U) +/*! DATIN0A - Input Data register */ +#define SGI_SGI_DATIN0A_DATIN0A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN0A_DATIN0A_SHIFT)) & SGI_SGI_DATIN0A_DATIN0A_MASK) +/*! @} */ + +/*! @name SGI_DATIN0B - Input Data register 0 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_DATIN0B_DATIN0B_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN0B_DATIN0B_SHIFT (0U) +/*! DATIN0B - Input Data register */ +#define SGI_SGI_DATIN0B_DATIN0B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN0B_DATIN0B_SHIFT)) & SGI_SGI_DATIN0B_DATIN0B_MASK) +/*! @} */ + +/*! @name SGI_DATIN0C - Input Data register 0 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_DATIN0C_DATIN0C_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN0C_DATIN0C_SHIFT (0U) +/*! DATIN0C - Input Data register */ +#define SGI_SGI_DATIN0C_DATIN0C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN0C_DATIN0C_SHIFT)) & SGI_SGI_DATIN0C_DATIN0C_MASK) +/*! @} */ + +/*! @name SGI_DATIN0D - Input Data register 0 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_DATIN0D_DATIN0D_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN0D_DATIN0D_SHIFT (0U) +/*! DATIN0D - Input Data register */ +#define SGI_SGI_DATIN0D_DATIN0D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN0D_DATIN0D_SHIFT)) & SGI_SGI_DATIN0D_DATIN0D_MASK) +/*! @} */ + +/*! @name SGI_DATIN1A - Input Data register 1 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_DATIN1A_DATIN1A_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN1A_DATIN1A_SHIFT (0U) +/*! DATIN1A - Input Data register */ +#define SGI_SGI_DATIN1A_DATIN1A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN1A_DATIN1A_SHIFT)) & SGI_SGI_DATIN1A_DATIN1A_MASK) +/*! @} */ + +/*! @name SGI_DATIN1B - Input Data register 1 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_DATIN1B_DATIN1B_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN1B_DATIN1B_SHIFT (0U) +/*! DATIN1B - Input Data register */ +#define SGI_SGI_DATIN1B_DATIN1B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN1B_DATIN1B_SHIFT)) & SGI_SGI_DATIN1B_DATIN1B_MASK) +/*! @} */ + +/*! @name SGI_DATIN1C - Input Data register 1 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_DATIN1C_DATIN1C_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN1C_DATIN1C_SHIFT (0U) +/*! DATIN1C - Input Data register */ +#define SGI_SGI_DATIN1C_DATIN1C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN1C_DATIN1C_SHIFT)) & SGI_SGI_DATIN1C_DATIN1C_MASK) +/*! @} */ + +/*! @name SGI_DATIN1D - Input Data register 1 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_DATIN1D_DATIN1D_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN1D_DATIN1D_SHIFT (0U) +/*! DATIN1D - Input Data register */ +#define SGI_SGI_DATIN1D_DATIN1D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN1D_DATIN1D_SHIFT)) & SGI_SGI_DATIN1D_DATIN1D_MASK) +/*! @} */ + +/*! @name SGI_DATIN2A - Input Data register 2 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_DATIN2A_DATIN2A_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN2A_DATIN2A_SHIFT (0U) +/*! DATIN2A - Input Data register */ +#define SGI_SGI_DATIN2A_DATIN2A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN2A_DATIN2A_SHIFT)) & SGI_SGI_DATIN2A_DATIN2A_MASK) +/*! @} */ + +/*! @name SGI_DATIN2B - Input Data register 2 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_DATIN2B_DATIN2B_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN2B_DATIN2B_SHIFT (0U) +/*! DATIN2B - Input Data register */ +#define SGI_SGI_DATIN2B_DATIN2B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN2B_DATIN2B_SHIFT)) & SGI_SGI_DATIN2B_DATIN2B_MASK) +/*! @} */ + +/*! @name SGI_DATIN2C - Input Data register 2 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_DATIN2C_DATIN2C_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN2C_DATIN2C_SHIFT (0U) +/*! DATIN2C - Input Data register */ +#define SGI_SGI_DATIN2C_DATIN2C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN2C_DATIN2C_SHIFT)) & SGI_SGI_DATIN2C_DATIN2C_MASK) +/*! @} */ + +/*! @name SGI_DATIN2D - Input Data register 2 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_DATIN2D_DATIN2D_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN2D_DATIN2D_SHIFT (0U) +/*! DATIN2D - Input Data register */ +#define SGI_SGI_DATIN2D_DATIN2D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN2D_DATIN2D_SHIFT)) & SGI_SGI_DATIN2D_DATIN2D_MASK) +/*! @} */ + +/*! @name SGI_DATIN3A - Input Data register 3 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_DATIN3A_DATIN3A_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN3A_DATIN3A_SHIFT (0U) +/*! DATIN3A - Input Data register */ +#define SGI_SGI_DATIN3A_DATIN3A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN3A_DATIN3A_SHIFT)) & SGI_SGI_DATIN3A_DATIN3A_MASK) +/*! @} */ + +/*! @name SGI_DATIN3B - Input Data register 3 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_DATIN3B_DATIN3B_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN3B_DATIN3B_SHIFT (0U) +/*! DATIN3B - Input Data register */ +#define SGI_SGI_DATIN3B_DATIN3B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN3B_DATIN3B_SHIFT)) & SGI_SGI_DATIN3B_DATIN3B_MASK) +/*! @} */ + +/*! @name SGI_DATIN3C - Input Data register 3 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_DATIN3C_DATIN3C_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN3C_DATIN3C_SHIFT (0U) +/*! DATIN3C - Input Data register */ +#define SGI_SGI_DATIN3C_DATIN3C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN3C_DATIN3C_SHIFT)) & SGI_SGI_DATIN3C_DATIN3C_MASK) +/*! @} */ + +/*! @name SGI_DATIN3D - Input Data register 3 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_DATIN3D_DATIN3D_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATIN3D_DATIN3D_SHIFT (0U) +/*! DATIN3D - Input Data register */ +#define SGI_SGI_DATIN3D_DATIN3D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATIN3D_DATIN3D_SHIFT)) & SGI_SGI_DATIN3D_DATIN3D_MASK) +/*! @} */ + +/*! @name SGI_KEY0A - Input Key register 0 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_KEY0A_KEY0A_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY0A_KEY0A_SHIFT (0U) +/*! KEY0A - Input Key register */ +#define SGI_SGI_KEY0A_KEY0A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY0A_KEY0A_SHIFT)) & SGI_SGI_KEY0A_KEY0A_MASK) +/*! @} */ + +/*! @name SGI_KEY0B - Input Key register 0 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_KEY0B_KEY0B_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY0B_KEY0B_SHIFT (0U) +/*! KEY0B - Input Key register */ +#define SGI_SGI_KEY0B_KEY0B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY0B_KEY0B_SHIFT)) & SGI_SGI_KEY0B_KEY0B_MASK) +/*! @} */ + +/*! @name SGI_KEY0C - Input Key register 0 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_KEY0C_KEY0C_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY0C_KEY0C_SHIFT (0U) +/*! KEY0C - Input Key register */ +#define SGI_SGI_KEY0C_KEY0C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY0C_KEY0C_SHIFT)) & SGI_SGI_KEY0C_KEY0C_MASK) +/*! @} */ + +/*! @name SGI_KEY0D - Input Key register 0 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_KEY0D_KEY0D_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY0D_KEY0D_SHIFT (0U) +/*! KEY0D - Input Key register */ +#define SGI_SGI_KEY0D_KEY0D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY0D_KEY0D_SHIFT)) & SGI_SGI_KEY0D_KEY0D_MASK) +/*! @} */ + +/*! @name SGI_KEY1A - Input Key register 1 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_KEY1A_KEY1A_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY1A_KEY1A_SHIFT (0U) +/*! KEY1A - Input Key register */ +#define SGI_SGI_KEY1A_KEY1A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY1A_KEY1A_SHIFT)) & SGI_SGI_KEY1A_KEY1A_MASK) +/*! @} */ + +/*! @name SGI_KEY1B - Input Key register 1 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_KEY1B_KEY1B_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY1B_KEY1B_SHIFT (0U) +/*! KEY1B - Input Key register */ +#define SGI_SGI_KEY1B_KEY1B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY1B_KEY1B_SHIFT)) & SGI_SGI_KEY1B_KEY1B_MASK) +/*! @} */ + +/*! @name SGI_KEY1C - Input Key register 1 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_KEY1C_KEY1C_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY1C_KEY1C_SHIFT (0U) +/*! KEY1C - Input Key register */ +#define SGI_SGI_KEY1C_KEY1C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY1C_KEY1C_SHIFT)) & SGI_SGI_KEY1C_KEY1C_MASK) +/*! @} */ + +/*! @name SGI_KEY1D - Input Key register 1 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_KEY1D_KEY1D_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY1D_KEY1D_SHIFT (0U) +/*! KEY1D - Input Key register */ +#define SGI_SGI_KEY1D_KEY1D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY1D_KEY1D_SHIFT)) & SGI_SGI_KEY1D_KEY1D_MASK) +/*! @} */ + +/*! @name SGI_KEY2A - Input Key register 2 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_KEY2A_KEY2A_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY2A_KEY2A_SHIFT (0U) +/*! KEY2A - Input Key register */ +#define SGI_SGI_KEY2A_KEY2A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY2A_KEY2A_SHIFT)) & SGI_SGI_KEY2A_KEY2A_MASK) +/*! @} */ + +/*! @name SGI_KEY2B - Input Key register 2 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_KEY2B_KEY2B_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY2B_KEY2B_SHIFT (0U) +/*! KEY2B - Input Key register */ +#define SGI_SGI_KEY2B_KEY2B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY2B_KEY2B_SHIFT)) & SGI_SGI_KEY2B_KEY2B_MASK) +/*! @} */ + +/*! @name SGI_KEY2C - Input Key register 2 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_KEY2C_KEY2C_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY2C_KEY2C_SHIFT (0U) +/*! KEY2C - Input Key register */ +#define SGI_SGI_KEY2C_KEY2C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY2C_KEY2C_SHIFT)) & SGI_SGI_KEY2C_KEY2C_MASK) +/*! @} */ + +/*! @name SGI_KEY2D - Input Key register 2 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_KEY2D_KEY2D_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY2D_KEY2D_SHIFT (0U) +/*! KEY2D - Input Key register */ +#define SGI_SGI_KEY2D_KEY2D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY2D_KEY2D_SHIFT)) & SGI_SGI_KEY2D_KEY2D_MASK) +/*! @} */ + +/*! @name SGI_KEY3A - Input Key register 3 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_KEY3A_KEY3A_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY3A_KEY3A_SHIFT (0U) +/*! KEY3A - Input Key register */ +#define SGI_SGI_KEY3A_KEY3A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY3A_KEY3A_SHIFT)) & SGI_SGI_KEY3A_KEY3A_MASK) +/*! @} */ + +/*! @name SGI_KEY3B - Input Key register 3 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_KEY3B_KEY3B_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY3B_KEY3B_SHIFT (0U) +/*! KEY3B - Input Key register */ +#define SGI_SGI_KEY3B_KEY3B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY3B_KEY3B_SHIFT)) & SGI_SGI_KEY3B_KEY3B_MASK) +/*! @} */ + +/*! @name SGI_KEY3C - Input Key register 3 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_KEY3C_KEY3C_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY3C_KEY3C_SHIFT (0U) +/*! KEY3C - Input Key register */ +#define SGI_SGI_KEY3C_KEY3C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY3C_KEY3C_SHIFT)) & SGI_SGI_KEY3C_KEY3C_MASK) +/*! @} */ + +/*! @name SGI_KEY3D - Input Key register 3 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_KEY3D_KEY3D_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY3D_KEY3D_SHIFT (0U) +/*! KEY3D - Input Key register */ +#define SGI_SGI_KEY3D_KEY3D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY3D_KEY3D_SHIFT)) & SGI_SGI_KEY3D_KEY3D_MASK) +/*! @} */ + +/*! @name SGI_KEY4A - Input Key register 4 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_KEY4A_KEY4A_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY4A_KEY4A_SHIFT (0U) +/*! KEY4A - Input Key register */ +#define SGI_SGI_KEY4A_KEY4A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY4A_KEY4A_SHIFT)) & SGI_SGI_KEY4A_KEY4A_MASK) +/*! @} */ + +/*! @name SGI_KEY4B - Input Key register 4 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_KEY4B_KEY4B_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY4B_KEY4B_SHIFT (0U) +/*! KEY4B - Input Key register */ +#define SGI_SGI_KEY4B_KEY4B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY4B_KEY4B_SHIFT)) & SGI_SGI_KEY4B_KEY4B_MASK) +/*! @} */ + +/*! @name SGI_KEY4C - Input Key register 4 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_KEY4C_KEY4C_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY4C_KEY4C_SHIFT (0U) +/*! KEY4C - Input Key register */ +#define SGI_SGI_KEY4C_KEY4C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY4C_KEY4C_SHIFT)) & SGI_SGI_KEY4C_KEY4C_MASK) +/*! @} */ + +/*! @name SGI_KEY4D - Input Key register 4 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_KEY4D_KEY4D_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY4D_KEY4D_SHIFT (0U) +/*! KEY4D - Input Key register */ +#define SGI_SGI_KEY4D_KEY4D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY4D_KEY4D_SHIFT)) & SGI_SGI_KEY4D_KEY4D_MASK) +/*! @} */ + +/*! @name SGI_KEY5A - Input Key register 5 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_KEY5A_KEY5A_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY5A_KEY5A_SHIFT (0U) +/*! KEY5A - Input Key register */ +#define SGI_SGI_KEY5A_KEY5A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY5A_KEY5A_SHIFT)) & SGI_SGI_KEY5A_KEY5A_MASK) +/*! @} */ + +/*! @name SGI_KEY5B - Input Key register 5 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_KEY5B_KEY5B_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY5B_KEY5B_SHIFT (0U) +/*! KEY5B - Input Key register */ +#define SGI_SGI_KEY5B_KEY5B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY5B_KEY5B_SHIFT)) & SGI_SGI_KEY5B_KEY5B_MASK) +/*! @} */ + +/*! @name SGI_KEY5C - Input Key register 5 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_KEY5C_KEY5C_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY5C_KEY5C_SHIFT (0U) +/*! KEY5C - Input Key register */ +#define SGI_SGI_KEY5C_KEY5C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY5C_KEY5C_SHIFT)) & SGI_SGI_KEY5C_KEY5C_MASK) +/*! @} */ + +/*! @name SGI_KEY5D - Input Key register 5 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_KEY5D_KEY5D_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY5D_KEY5D_SHIFT (0U) +/*! KEY5D - Input Key register */ +#define SGI_SGI_KEY5D_KEY5D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY5D_KEY5D_SHIFT)) & SGI_SGI_KEY5D_KEY5D_MASK) +/*! @} */ + +/*! @name SGI_KEY6A - Input Key register 6 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_KEY6A_KEY6A_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY6A_KEY6A_SHIFT (0U) +/*! KEY6A - Input Key register */ +#define SGI_SGI_KEY6A_KEY6A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY6A_KEY6A_SHIFT)) & SGI_SGI_KEY6A_KEY6A_MASK) +/*! @} */ + +/*! @name SGI_KEY6B - Input Key register 6 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_KEY6B_KEY6B_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY6B_KEY6B_SHIFT (0U) +/*! KEY6B - Input Key register */ +#define SGI_SGI_KEY6B_KEY6B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY6B_KEY6B_SHIFT)) & SGI_SGI_KEY6B_KEY6B_MASK) +/*! @} */ + +/*! @name SGI_KEY6C - Input Key register 6 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_KEY6C_KEY6C_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY6C_KEY6C_SHIFT (0U) +/*! KEY6C - Input Key register */ +#define SGI_SGI_KEY6C_KEY6C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY6C_KEY6C_SHIFT)) & SGI_SGI_KEY6C_KEY6C_MASK) +/*! @} */ + +/*! @name SGI_KEY6D - Input Key register 6 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_KEY6D_KEY6D_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY6D_KEY6D_SHIFT (0U) +/*! KEY6D - Input Key register */ +#define SGI_SGI_KEY6D_KEY6D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY6D_KEY6D_SHIFT)) & SGI_SGI_KEY6D_KEY6D_MASK) +/*! @} */ + +/*! @name SGI_KEY7A - Input Key register 7 - Word-3 */ +/*! @{ */ + +#define SGI_SGI_KEY7A_KEY7A_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY7A_KEY7A_SHIFT (0U) +/*! KEY7A - Input Key register */ +#define SGI_SGI_KEY7A_KEY7A(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY7A_KEY7A_SHIFT)) & SGI_SGI_KEY7A_KEY7A_MASK) +/*! @} */ + +/*! @name SGI_KEY7B - Input Key register 7 - Word-2 */ +/*! @{ */ + +#define SGI_SGI_KEY7B_KEY7B_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY7B_KEY7B_SHIFT (0U) +/*! KEY7B - Input Key register */ +#define SGI_SGI_KEY7B_KEY7B(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY7B_KEY7B_SHIFT)) & SGI_SGI_KEY7B_KEY7B_MASK) +/*! @} */ + +/*! @name SGI_KEY7C - Input Key register 7 - Word-1 */ +/*! @{ */ + +#define SGI_SGI_KEY7C_KEY7C_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY7C_KEY7C_SHIFT (0U) +/*! KEY7C - Input Key register */ +#define SGI_SGI_KEY7C_KEY7C(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY7C_KEY7C_SHIFT)) & SGI_SGI_KEY7C_KEY7C_MASK) +/*! @} */ + +/*! @name SGI_KEY7D - Input Key register 7 - Word-0 */ +/*! @{ */ + +#define SGI_SGI_KEY7D_KEY7D_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY7D_KEY7D_SHIFT (0U) +/*! KEY7D - Input Key register */ +#define SGI_SGI_KEY7D_KEY7D(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY7D_KEY7D_SHIFT)) & SGI_SGI_KEY7D_KEY7D_MASK) +/*! @} */ + +/*! @name SGI_DATOUTA - Output Data register - Word-3 */ +/*! @{ */ + +#define SGI_SGI_DATOUTA_DATOUTA_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATOUTA_DATOUTA_SHIFT (0U) +/*! DATOUTA - Output Data register */ +#define SGI_SGI_DATOUTA_DATOUTA(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATOUTA_DATOUTA_SHIFT)) & SGI_SGI_DATOUTA_DATOUTA_MASK) +/*! @} */ + +/*! @name SGI_DATOUTB - Output Data register - Word-2 */ +/*! @{ */ + +#define SGI_SGI_DATOUTB_DATOUTB_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATOUTB_DATOUTB_SHIFT (0U) +/*! DATOUTB - Output Data register */ +#define SGI_SGI_DATOUTB_DATOUTB(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATOUTB_DATOUTB_SHIFT)) & SGI_SGI_DATOUTB_DATOUTB_MASK) +/*! @} */ + +/*! @name SGI_DATOUTC - Output Data register - Word-1 */ +/*! @{ */ + +#define SGI_SGI_DATOUTC_DATOUTC_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATOUTC_DATOUTC_SHIFT (0U) +/*! DATOUTC - Output Data register */ +#define SGI_SGI_DATOUTC_DATOUTC(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATOUTC_DATOUTC_SHIFT)) & SGI_SGI_DATOUTC_DATOUTC_MASK) +/*! @} */ + +/*! @name SGI_DATOUTD - Output Data register - Word-0 */ +/*! @{ */ + +#define SGI_SGI_DATOUTD_DATOUTD_MASK (0xFFFFFFFFU) +#define SGI_SGI_DATOUTD_DATOUTD_SHIFT (0U) +/*! DATOUTD - Output Data register */ +#define SGI_SGI_DATOUTD_DATOUTD(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DATOUTD_DATOUTD_SHIFT)) & SGI_SGI_DATOUTD_DATOUTD_MASK) +/*! @} */ + +/*! @name SGI_STATUS - Status register */ +/*! @{ */ + +#define SGI_SGI_STATUS_BUSY_MASK (0x1U) +#define SGI_SGI_STATUS_BUSY_SHIFT (0U) +/*! BUSY + * 0b0..Not busy + * 0b1..Busy + */ +#define SGI_SGI_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_BUSY_SHIFT)) & SGI_SGI_STATUS_BUSY_MASK) + +#define SGI_SGI_STATUS_OFLOW_MASK (0x2U) +#define SGI_SGI_STATUS_OFLOW_SHIFT (1U) +/*! OFLOW - Overflow in INCR operation flag + * 0b0..Clear the flag + * 0b0..No overflow + * 0b1..No effect + * 0b1..Overflow + */ +#define SGI_SGI_STATUS_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_OFLOW_SHIFT)) & SGI_SGI_STATUS_OFLOW_MASK) + +#define SGI_SGI_STATUS_PRNG_RDY_MASK (0x4U) +#define SGI_SGI_STATUS_PRNG_RDY_SHIFT (2U) +/*! PRNG_RDY + * 0b0..Not ready + * 0b1..Ready + */ +#define SGI_SGI_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_PRNG_RDY_SHIFT)) & SGI_SGI_STATUS_PRNG_RDY_MASK) + +#define SGI_SGI_STATUS_ERROR_MASK (0x38U) +#define SGI_SGI_STATUS_ERROR_SHIFT (3U) +/*! ERROR - Error detected + * 0b000..Error (all values other than 0x05 indicate ERROR) + * 0b101..No error + */ +#define SGI_SGI_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_ERROR_SHIFT)) & SGI_SGI_STATUS_ERROR_MASK) + +#define SGI_SGI_STATUS_SHA2_BUSY_MASK (0x40U) +#define SGI_SGI_STATUS_SHA2_BUSY_SHIFT (6U) +/*! SHA2_BUSY + * 0b0..Not busy + * 0b1..Busy + */ +#define SGI_SGI_STATUS_SHA2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_SHA2_BUSY_SHIFT)) & SGI_SGI_STATUS_SHA2_BUSY_MASK) + +#define SGI_SGI_STATUS_IRQ_MASK (0x80U) +#define SGI_SGI_STATUS_IRQ_SHIFT (7U) +/*! IRQ + * 0b0..Clear the flag + * 0b0..No IRQ + * 0b1..IRQ + * 0b1..No effect + */ +#define SGI_SGI_STATUS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_IRQ_SHIFT)) & SGI_SGI_STATUS_IRQ_MASK) + +#define SGI_SGI_STATUS_SHA_FIFO_FULL_MASK (0x100U) +#define SGI_SGI_STATUS_SHA_FIFO_FULL_SHIFT (8U) +/*! SHA_FIFO_FULL + * 0b0..Not full + * 0b1..Full + */ +#define SGI_SGI_STATUS_SHA_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_SHA_FIFO_FULL_SHIFT)) & SGI_SGI_STATUS_SHA_FIFO_FULL_MASK) + +#define SGI_SGI_STATUS_SHA_FIFO_LEVEL_MASK (0x7E00U) +#define SGI_SGI_STATUS_SHA_FIFO_LEVEL_SHIFT (9U) +#define SGI_SGI_STATUS_SHA_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_SHA_FIFO_LEVEL_SHIFT)) & SGI_SGI_STATUS_SHA_FIFO_LEVEL_MASK) + +#define SGI_SGI_STATUS_SHA_ERROR_MASK (0x8000U) +#define SGI_SGI_STATUS_SHA_ERROR_SHIFT (15U) +/*! SHA_ERROR + * 0b0..No error + * 0b1..Error + */ +#define SGI_SGI_STATUS_SHA_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_SHA_ERROR_SHIFT)) & SGI_SGI_STATUS_SHA_ERROR_MASK) + +#define SGI_SGI_STATUS_KEY_READ_ERR_MASK (0x10000U) +#define SGI_SGI_STATUS_KEY_READ_ERR_SHIFT (16U) +/*! KEY_READ_ERR - KEY SFR READ ERROR, sticky, cleared only with reset or flush + * 0b0..No error + * 0b1..Error + */ +#define SGI_SGI_STATUS_KEY_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_KEY_READ_ERR_SHIFT)) & SGI_SGI_STATUS_KEY_READ_ERR_MASK) + +#define SGI_SGI_STATUS_KEY_UNWRAP_ERR_MASK (0x20000U) +#define SGI_SGI_STATUS_KEY_UNWRAP_ERR_SHIFT (17U) +/*! KEY_UNWRAP_ERR - KEY UNWRAP ERROR , sticky, cleared only with reset or flush + * 0b0..No error + * 0b1..Error + */ +#define SGI_SGI_STATUS_KEY_UNWRAP_ERR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_STATUS_KEY_UNWRAP_ERR_SHIFT)) & SGI_SGI_STATUS_KEY_UNWRAP_ERR_MASK) +/*! @} */ + +/*! @name SGI_COUNT - Calculation counter */ +/*! @{ */ + +#define SGI_SGI_COUNT_COUNT_MASK (0xFFFFU) +#define SGI_SGI_COUNT_COUNT_SHIFT (0U) +#define SGI_SGI_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_COUNT_COUNT_SHIFT)) & SGI_SGI_COUNT_COUNT_MASK) +/*! @} */ + +/*! @name SGI_KEYCHK - Key checksum register */ +/*! @{ */ + +#define SGI_SGI_KEYCHK_KEYCHKSUM_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEYCHK_KEYCHKSUM_SHIFT (0U) +/*! KEYCHKSUM - Key checksum (32-bit). */ +#define SGI_SGI_KEYCHK_KEYCHKSUM(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEYCHK_KEYCHKSUM_SHIFT)) & SGI_SGI_KEYCHK_KEYCHKSUM_MASK) +/*! @} */ + +/*! @name SGI_CTRL - SGI Control register */ +/*! @{ */ + +#define SGI_SGI_CTRL_START_MASK (0x1U) +#define SGI_SGI_CTRL_START_SHIFT (0U) +/*! START - Start crypto operation + * 0b0..Clr has no effect + * 0b1..Set to start operation + */ +#define SGI_SGI_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_START_SHIFT)) & SGI_SGI_CTRL_START_MASK) + +#define SGI_SGI_CTRL_DECRYPT_MASK (0x2U) +#define SGI_SGI_CTRL_DECRYPT_SHIFT (1U) +/*! DECRYPT - Sets Cipher direction(AES and DES) + * 0b0..Encryption + * 0b1..Decryption + */ +#define SGI_SGI_CTRL_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_DECRYPT_SHIFT)) & SGI_SGI_CTRL_DECRYPT_MASK) + +#define SGI_SGI_CTRL_AESKEYSZ_MASK (0xCU) +#define SGI_SGI_CTRL_AESKEYSZ_SHIFT (2U) +/*! AESKEYSZ + * 0b00..AES-128 + * 0b10..AES-256 + * 0b11..RFU (defaults to AES-128) + */ +#define SGI_SGI_CTRL_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_AESKEYSZ_SHIFT)) & SGI_SGI_CTRL_AESKEYSZ_MASK) + +#define SGI_SGI_CTRL_CRYPTO_OP_MASK (0x70U) +#define SGI_SGI_CTRL_CRYPTO_OP_SHIFT (4U) +/*! CRYPTO_OP - Sets 'Crypto Operation' type + * 0b000..AES + * 0b001..DES (If Included) + * 0b010..TDES (If Included) + * 0b011..GFMUL(If Included) + * 0b100..SHA2 (If Included) + * 0b101..CMAC (If Included) + * 0b110-0b111..others - RFU (Defaults to 1st available OP) + */ +#define SGI_SGI_CTRL_CRYPTO_OP(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_CRYPTO_OP_SHIFT)) & SGI_SGI_CTRL_CRYPTO_OP_MASK) + +#define SGI_SGI_CTRL_INSEL_MASK (0x780U) +#define SGI_SGI_CTRL_INSEL_SHIFT (7U) +/*! INSEL + * 0b0000..DATIN[0] + * 0b0001..DATIN[1]* + * 0b0010..DATIN[2]* + * 0b0011..DATIN[3]* + * 0b0100..DATIN[0] ^ DATOUT + * 0b0101..DATIN[1] ^ DATOUT* + * 0b0110..DATIN[2] ^ DATOUT* + * 0b0111..DATIN[3] ^ DATOUT* + * 0b1000..DATOUT + * 0b1001-0b1111..others - DATIN[0] * - only if DATIN[num] exists, else [0] + */ +#define SGI_SGI_CTRL_INSEL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_INSEL_SHIFT)) & SGI_SGI_CTRL_INSEL_MASK) + +#define SGI_SGI_CTRL_OUTSEL_MASK (0x3800U) +#define SGI_SGI_CTRL_OUTSEL_SHIFT (11U) +/*! OUTSEL + * 0b000..DATOUT = 'Kernel Res' + * 0b001..DATOUT = 'Kernel Res' ^ DATIN[0] + * 0b010..DATOUT = 'Kernel Res' ^ DATIN[1]* + * 0b011..DATOUT = 'Kernel Res' ^ DATIN[2]* + * 0b100..DATOUT = 'Kernel Res' ^DATIN[3]* + * 0b101-0b111..others - DATOUT = 'Kernel Res' * - only if DATIN[num] exists, else [0] + */ +#define SGI_SGI_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_OUTSEL_SHIFT)) & SGI_SGI_CTRL_OUTSEL_MASK) + +#define SGI_SGI_CTRL_DATOUT_RES_MASK (0xC000U) +#define SGI_SGI_CTRL_DATOUT_RES_SHIFT (14U) +/*! DATOUT_RES + * 0b00..END_UP + * 0b01..START_UP + * 0b10..TRIGGER_UP + * 0b11..NO_UP + */ +#define SGI_SGI_CTRL_DATOUT_RES(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_DATOUT_RES_SHIFT)) & SGI_SGI_CTRL_DATOUT_RES_MASK) + +#define SGI_SGI_CTRL_AES_EN_MASK (0x10000U) +#define SGI_SGI_CTRL_AES_EN_SHIFT (16U) +/*! AES_EN + * 0b0..AES disabled + * 0b1..AES enabled + */ +#define SGI_SGI_CTRL_AES_EN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_AES_EN_SHIFT)) & SGI_SGI_CTRL_AES_EN_MASK) + +#define SGI_SGI_CTRL_DES_EN_MASK (0x20000U) +#define SGI_SGI_CTRL_DES_EN_SHIFT (17U) +/*! DES_EN + * 0b0..DES disabled + * 0b1..DES enabled + */ +#define SGI_SGI_CTRL_DES_EN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_DES_EN_SHIFT)) & SGI_SGI_CTRL_DES_EN_MASK) + +#define SGI_SGI_CTRL_GCM_EN_MASK (0x40000U) +#define SGI_SGI_CTRL_GCM_EN_SHIFT (18U) +/*! GCM_EN + * 0b0..GFMUL disabled + * 0b1..GFMUL enabled + */ +#define SGI_SGI_CTRL_GCM_EN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_GCM_EN_SHIFT)) & SGI_SGI_CTRL_GCM_EN_MASK) + +#define SGI_SGI_CTRL_PRNG_EN_MASK (0x80000U) +#define SGI_SGI_CTRL_PRNG_EN_SHIFT (19U) +/*! PRNG_EN - PRNG Enable (only if SGI has internal PRNG) + * 0b0..PRNG Disabled + * 0b1..PRNG Enabled + */ +#define SGI_SGI_CTRL_PRNG_EN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_PRNG_EN_SHIFT)) & SGI_SGI_CTRL_PRNG_EN_MASK) + +#define SGI_SGI_CTRL_INKEYSEL_MASK (0x1F00000U) +#define SGI_SGI_CTRL_INKEYSEL_SHIFT (20U) +/*! INKEYSEL - Input key selection */ +#define SGI_SGI_CTRL_INKEYSEL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_INKEYSEL_SHIFT)) & SGI_SGI_CTRL_INKEYSEL_MASK) + +#define SGI_SGI_CTRL_TDESKEY_MASK (0x2000000U) +#define SGI_SGI_CTRL_TDESKEY_SHIFT (25U) +/*! TDESKEY + * 0b0..2-key TDES + * 0b1..3-key TDES + */ +#define SGI_SGI_CTRL_TDESKEY(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_TDESKEY_SHIFT)) & SGI_SGI_CTRL_TDESKEY_MASK) + +#define SGI_SGI_CTRL_AES_NO_KL_MASK (0x4000000U) +#define SGI_SGI_CTRL_AES_NO_KL_SHIFT (26U) +/*! AES_NO_KL + * 0b0..new AES key will be loaded + * 0b1..No AES key will be loaded, and previously loaded key will be used. + */ +#define SGI_SGI_CTRL_AES_NO_KL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_AES_NO_KL_SHIFT)) & SGI_SGI_CTRL_AES_NO_KL_MASK) + +#define SGI_SGI_CTRL_AES_SEL_MASK (0x8000000U) +#define SGI_SGI_CTRL_AES_SEL_SHIFT (27U) +/*! AES_SEL + * 0b0..First AES selected + * 0b1..Second AES selected (when enabled) + */ +#define SGI_SGI_CTRL_AES_SEL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL_AES_SEL_SHIFT)) & SGI_SGI_CTRL_AES_SEL_MASK) +/*! @} */ + +/*! @name SGI_CTRL2 - SGI Control register 2 */ +/*! @{ */ + +#define SGI_SGI_CTRL2_FLUSH_MASK (0x1U) +#define SGI_SGI_CTRL2_FLUSH_SHIFT (0U) +/*! FLUSH - Start Full SGI Flush + * 0b0..Clr has no effect + * 0b1..Set to start flush + */ +#define SGI_SGI_CTRL2_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_FLUSH_SHIFT)) & SGI_SGI_CTRL2_FLUSH_MASK) + +#define SGI_SGI_CTRL2_KEY_FLUSH_MASK (0x2U) +#define SGI_SGI_CTRL2_KEY_FLUSH_SHIFT (1U) +/*! KEY_FLUSH - Start KEY register-bank Flush + * 0b0..Clr has no effect + * 0b1..Set to start flush + */ +#define SGI_SGI_CTRL2_KEY_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_KEY_FLUSH_SHIFT)) & SGI_SGI_CTRL2_KEY_FLUSH_MASK) + +#define SGI_SGI_CTRL2_DATIN_FLUSH_MASK (0x4U) +#define SGI_SGI_CTRL2_DATIN_FLUSH_SHIFT (2U) +/*! DATIN_FLUSH - Start DATIN register-bank Flush + * 0b0..Clr has no effect + * 0b1..Set to start flush + */ +#define SGI_SGI_CTRL2_DATIN_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_DATIN_FLUSH_SHIFT)) & SGI_SGI_CTRL2_DATIN_FLUSH_MASK) + +#define SGI_SGI_CTRL2_INCR_MASK (0x8U) +#define SGI_SGI_CTRL2_INCR_SHIFT (3U) +/*! INCR - Increment(Triggered by SFR write) + * 0b0..INCR-On-Write disabled + * 0b1..INCR-On-Write enabled + */ +#define SGI_SGI_CTRL2_INCR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_INCR_SHIFT)) & SGI_SGI_CTRL2_INCR_MASK) + +#define SGI_SGI_CTRL2_XORWR_MASK (0x10U) +#define SGI_SGI_CTRL2_XORWR_SHIFT (4U) +/*! XORWR - Write-XOR control + * 0b0..XOR-On-Write disabled + * 0b1..XOR-On-Write enabled + */ +#define SGI_SGI_CTRL2_XORWR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_XORWR_SHIFT)) & SGI_SGI_CTRL2_XORWR_MASK) + +#define SGI_SGI_CTRL2_FLUSHWR_MASK (0x20U) +#define SGI_SGI_CTRL2_FLUSHWR_SHIFT (5U) +/*! FLUSHWR - Flush Write control + * 0b0..Flush-Write disabled + * 0b1..Flush-Write enabled + */ +#define SGI_SGI_CTRL2_FLUSHWR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_FLUSHWR_SHIFT)) & SGI_SGI_CTRL2_FLUSHWR_MASK) + +#define SGI_SGI_CTRL2_INCR_CIN_MASK (0x40U) +#define SGI_SGI_CTRL2_INCR_CIN_SHIFT (6U) +/*! INCR_CIN - Increment Carry-In control + * 0b0..Carry-In for INCR is 1 + * 0b1..Carry-In for INCR is overflow from previous INCR operation + */ +#define SGI_SGI_CTRL2_INCR_CIN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_INCR_CIN_SHIFT)) & SGI_SGI_CTRL2_INCR_CIN_MASK) + +#define SGI_SGI_CTRL2_SMASKEN_MASK (0x100U) +#define SGI_SGI_CTRL2_SMASKEN_SHIFT (8U) +/*! SMASKEN - SFRMASK Enable + * 0b0..SFRMASK feature Disabled + * 0b1..SFRMASK feature Enabled + */ +#define SGI_SGI_CTRL2_SMASKEN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_SMASKEN_SHIFT)) & SGI_SGI_CTRL2_SMASKEN_MASK) + +#define SGI_SGI_CTRL2_SMASKSTEP_MASK (0x200U) +#define SGI_SGI_CTRL2_SMASKSTEP_SHIFT (9U) +/*! SMASKSTEP - SFRSEED increment control + * 0b0..SFRSEED increments every regbank access + * 0b1..SFRSEED increments every regbank access PLUS when SFRSEED in read + */ +#define SGI_SGI_CTRL2_SMASKSTEP(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_SMASKSTEP_SHIFT)) & SGI_SGI_CTRL2_SMASKSTEP_MASK) + +#define SGI_SGI_CTRL2_SMASKSW_MASK (0x400U) +#define SGI_SGI_CTRL2_SMASKSW_SHIFT (10U) +/*! SMASKSW - SFRMASK MASK control + * 0b0..SFR MASK output directly controlled by HW mask generator + * 0b1..SFR MASK output directly controlled by SW + */ +#define SGI_SGI_CTRL2_SMASKSW(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_SMASKSW_SHIFT)) & SGI_SGI_CTRL2_SMASKSW_MASK) + +#define SGI_SGI_CTRL2_MOVEM_MASK (0xF000U) +#define SGI_SGI_CTRL2_MOVEM_SHIFT (12U) +/*! MOVEM - 4-bit optional input for MOVEM feature */ +#define SGI_SGI_CTRL2_MOVEM(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_MOVEM_SHIFT)) & SGI_SGI_CTRL2_MOVEM_MASK) + +#define SGI_SGI_CTRL2_KEYRES_MASK (0x1F0000U) +#define SGI_SGI_CTRL2_KEYRES_SHIFT (16U) +/*! KEYRES - Selects key registers to be updated when rkey=1 */ +#define SGI_SGI_CTRL2_KEYRES(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_KEYRES_SHIFT)) & SGI_SGI_CTRL2_KEYRES_MASK) + +#define SGI_SGI_CTRL2_RKEY_MASK (0x200000U) +#define SGI_SGI_CTRL2_RKEY_SHIFT (21U) +/*! RKEY - Crypto result location + * 0b0..DATOUT register bank + * 0b1..KEY register bank + */ +#define SGI_SGI_CTRL2_RKEY(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_RKEY_SHIFT)) & SGI_SGI_CTRL2_RKEY_MASK) + +#define SGI_SGI_CTRL2_BYTES_ORDER_MASK (0x400000U) +#define SGI_SGI_CTRL2_BYTES_ORDER_SHIFT (22U) +/*! BYTES_ORDER - Byte order of regbank read/write data + * 0b0..Normal + * 0b1..Swapped + */ +#define SGI_SGI_CTRL2_BYTES_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_BYTES_ORDER_SHIFT)) & SGI_SGI_CTRL2_BYTES_ORDER_MASK) + +#define SGI_SGI_CTRL2_GCM_INXOR_MASK (0x800000U) +#define SGI_SGI_CTRL2_GCM_INXOR_SHIFT (23U) +/*! GCM_INXOR - GCM INXOR + * 0b0..GCM INXOR disabled + * 0b1..GCM INXOR enabled + */ +#define SGI_SGI_CTRL2_GCM_INXOR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CTRL2_GCM_INXOR_SHIFT)) & SGI_SGI_CTRL2_GCM_INXOR_MASK) +/*! @} */ + +/*! @name SGI_DUMMY_CTRL - Configuration of dummy controls */ +/*! @{ */ + +#define SGI_SGI_DUMMY_CTRL_DDCTRL_MASK (0x3FFU) +#define SGI_SGI_DUMMY_CTRL_DDCTRL_SHIFT (0U) +#define SGI_SGI_DUMMY_CTRL_DDCTRL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DUMMY_CTRL_DDCTRL_SHIFT)) & SGI_SGI_DUMMY_CTRL_DDCTRL_MASK) + +#define SGI_SGI_DUMMY_CTRL_ADCTRL_MASK (0x3FF0000U) +#define SGI_SGI_DUMMY_CTRL_ADCTRL_SHIFT (16U) +#define SGI_SGI_DUMMY_CTRL_ADCTRL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_DUMMY_CTRL_ADCTRL_SHIFT)) & SGI_SGI_DUMMY_CTRL_ADCTRL_MASK) +/*! @} */ + +/*! @name SGI_SFR_SW_MASK - Sofware Assisted Masking register */ +/*! @{ */ + +#define SGI_SGI_SFR_SW_MASK_SFR_MASK_VAL_MASK (0xFFFFFFFFU) +#define SGI_SGI_SFR_SW_MASK_SFR_MASK_VAL_SHIFT (0U) +/*! SFR_MASK_VAL - Seed/mask used for sw level masking */ +#define SGI_SGI_SFR_SW_MASK_SFR_MASK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SFR_SW_MASK_SFR_MASK_VAL_SHIFT)) & SGI_SGI_SFR_SW_MASK_SFR_MASK_VAL_MASK) +/*! @} */ + +/*! @name SGI_SFRSEED - SFRSEED register for SFRMASK feature */ +/*! @{ */ + +#define SGI_SGI_SFRSEED_SFRSEED_MASK (0xFFFFFFFFU) +#define SGI_SGI_SFRSEED_SFRSEED_SHIFT (0U) +/*! SFRSEED - Seed/mask used for sw level masking */ +#define SGI_SGI_SFRSEED_SFRSEED(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SFRSEED_SFRSEED_SHIFT)) & SGI_SGI_SFRSEED_SFRSEED_MASK) +/*! @} */ + +/*! @name SGI_SHA2_CTRL - SHA Control Register */ +/*! @{ */ + +#define SGI_SGI_SHA2_CTRL_SHA2_EN_MASK (0x1U) +#define SGI_SGI_SHA2_CTRL_SHA2_EN_SHIFT (0U) +/*! SHA2_EN - SHA enable + * 0b0..SHA disabled + * 0b1..SHA enabled + */ +#define SGI_SGI_SHA2_CTRL_SHA2_EN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA2_CTRL_SHA2_EN_SHIFT)) & SGI_SGI_SHA2_CTRL_SHA2_EN_MASK) + +#define SGI_SGI_SHA2_CTRL_SHA2_MODE_MASK (0x2U) +#define SGI_SGI_SHA2_CTRL_SHA2_MODE_SHIFT (1U) +/*! SHA2_MODE - SHA mode normal or automatic + * 0b0..SHA NORM Mode + * 0b1..SHA AUTO Mode + */ +#define SGI_SGI_SHA2_CTRL_SHA2_MODE(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA2_CTRL_SHA2_MODE_SHIFT)) & SGI_SGI_SHA2_CTRL_SHA2_MODE_MASK) + +#define SGI_SGI_SHA2_CTRL_SHA2_SIZE_MASK (0xCU) +#define SGI_SGI_SHA2_CTRL_SHA2_SIZE_SHIFT (2U) +/*! SHA2_SIZE + * 0b00..SHA-224 + * 0b01..SHA-256 + * 0b10..SHA-384(or SHA-224 if SHA-256 only) + * 0b11..SHA-512 (or SHA-256 if SHA-256 only) + */ +#define SGI_SGI_SHA2_CTRL_SHA2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA2_CTRL_SHA2_SIZE_SHIFT)) & SGI_SGI_SHA2_CTRL_SHA2_SIZE_MASK) + +#define SGI_SGI_SHA2_CTRL_SHA2_LOW_LIM_MASK (0xF0U) +#define SGI_SGI_SHA2_CTRL_SHA2_LOW_LIM_SHIFT (4U) +/*! SHA2_LOW_LIM - SHA FIFO low limit */ +#define SGI_SGI_SHA2_CTRL_SHA2_LOW_LIM(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA2_CTRL_SHA2_LOW_LIM_SHIFT)) & SGI_SGI_SHA2_CTRL_SHA2_LOW_LIM_MASK) + +#define SGI_SGI_SHA2_CTRL_SHA2_HIGH_LIM_MASK (0xF00U) +#define SGI_SGI_SHA2_CTRL_SHA2_HIGH_LIM_SHIFT (8U) +/*! SHA2_HIGH_LIM - SHA FIFO high limit */ +#define SGI_SGI_SHA2_CTRL_SHA2_HIGH_LIM(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA2_CTRL_SHA2_HIGH_LIM_SHIFT)) & SGI_SGI_SHA2_CTRL_SHA2_HIGH_LIM_MASK) + +#define SGI_SGI_SHA2_CTRL_SHA2_COUNT_EN_MASK (0x1000U) +#define SGI_SGI_SHA2_CTRL_SHA2_COUNT_EN_SHIFT (12U) +/*! SHA2_COUNT_EN - SHA Calculation counter enable + * 0b0..SHA operation DOES NOT increment COUNT + * 0b1..SHA operation DOES increment count + */ +#define SGI_SGI_SHA2_CTRL_SHA2_COUNT_EN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA2_CTRL_SHA2_COUNT_EN_SHIFT)) & SGI_SGI_SHA2_CTRL_SHA2_COUNT_EN_MASK) + +#define SGI_SGI_SHA2_CTRL_HASH_RELOAD_MASK (0x2000U) +#define SGI_SGI_SHA2_CTRL_HASH_RELOAD_SHIFT (13U) +/*! HASH_RELOAD - SHA HASH reload + * 0b0..No HASH reload + * 0b1..HASH reload enabled + */ +#define SGI_SGI_SHA2_CTRL_HASH_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA2_CTRL_HASH_RELOAD_SHIFT)) & SGI_SGI_SHA2_CTRL_HASH_RELOAD_MASK) + +#define SGI_SGI_SHA2_CTRL_SHA2_STOP_MASK (0x4000U) +#define SGI_SGI_SHA2_CTRL_SHA2_STOP_SHIFT (14U) +/*! SHA2_STOP - STOP SHA AUTO mode + * 0b0..Keep running + * 0b1..Stop auto mode + */ +#define SGI_SGI_SHA2_CTRL_SHA2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA2_CTRL_SHA2_STOP_SHIFT)) & SGI_SGI_SHA2_CTRL_SHA2_STOP_MASK) + +#define SGI_SGI_SHA2_CTRL_NO_AUTO_INIT_MASK (0x8000U) +#define SGI_SGI_SHA2_CTRL_NO_AUTO_INIT_SHIFT (15U) +/*! NO_AUTO_INIT - SHA no automatic HASH initialisation + * 0b0..SHA automatic HASH initialisation + * 0b1..No SHA automatic HASH initialisation + */ +#define SGI_SGI_SHA2_CTRL_NO_AUTO_INIT(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA2_CTRL_NO_AUTO_INIT_SHIFT)) & SGI_SGI_SHA2_CTRL_NO_AUTO_INIT_MASK) +/*! @} */ + +/*! @name SGI_SHA_FIFO - SHA FIFO lower-bank low */ +/*! @{ */ + +#define SGI_SGI_SHA_FIFO_FIFO_MASK (0xFFFFFFFFU) +#define SGI_SGI_SHA_FIFO_FIFO_SHIFT (0U) +/*! FIFO - SHA FIFO register */ +#define SGI_SGI_SHA_FIFO_FIFO(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_SHA_FIFO_FIFO_SHIFT)) & SGI_SGI_SHA_FIFO_FIFO_MASK) +/*! @} */ + +/*! @name SGI_CONFIG - SHA Configuration Reg */ +/*! @{ */ + +#define SGI_SGI_CONFIG_ROW_MASK (0x1U) +#define SGI_SGI_CONFIG_ROW_SHIFT (0U) +/*! ROW - SGI Diversified for 'ROW' */ +#define SGI_SGI_CONFIG_ROW(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_ROW_SHIFT)) & SGI_SGI_CONFIG_ROW_MASK) + +#define SGI_SGI_CONFIG_CHINA_MASK (0x2U) +#define SGI_SGI_CONFIG_CHINA_SHIFT (1U) +/*! CHINA - SGI Diversified for 'CHINA' */ +#define SGI_SGI_CONFIG_CHINA(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_CHINA_SHIFT)) & SGI_SGI_CONFIG_CHINA_MASK) + +#define SGI_SGI_CONFIG_CC_MASK (0x4U) +#define SGI_SGI_CONFIG_CC_SHIFT (2U) +/*! CC - SGI Diversified for 'CC' */ +#define SGI_SGI_CONFIG_CC(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_CC_SHIFT)) & SGI_SGI_CONFIG_CC_MASK) + +#define SGI_SGI_CONFIG_HAS_AES_MASK (0x8U) +#define SGI_SGI_CONFIG_HAS_AES_SHIFT (3U) +/*! HAS_AES - HAS AES */ +#define SGI_SGI_CONFIG_HAS_AES(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_HAS_AES_SHIFT)) & SGI_SGI_CONFIG_HAS_AES_MASK) + +#define SGI_SGI_CONFIG_HAS_DES_MASK (0x10U) +#define SGI_SGI_CONFIG_HAS_DES_SHIFT (4U) +/*! HAS_DES - HAS DES */ +#define SGI_SGI_CONFIG_HAS_DES(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_HAS_DES_SHIFT)) & SGI_SGI_CONFIG_HAS_DES_MASK) + +#define SGI_SGI_CONFIG_HAS_SHA_MASK (0x20U) +#define SGI_SGI_CONFIG_HAS_SHA_SHIFT (5U) +/*! HAS_SHA - HAS SHA */ +#define SGI_SGI_CONFIG_HAS_SHA(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_HAS_SHA_SHIFT)) & SGI_SGI_CONFIG_HAS_SHA_MASK) + +#define SGI_SGI_CONFIG_HAS_MOVEM_MASK (0x40U) +#define SGI_SGI_CONFIG_HAS_MOVEM_SHIFT (6U) +/*! HAS_MOVEM - HAS MOVEM */ +#define SGI_SGI_CONFIG_HAS_MOVEM(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_HAS_MOVEM_SHIFT)) & SGI_SGI_CONFIG_HAS_MOVEM_MASK) + +#define SGI_SGI_CONFIG_HAS_CMAC_MASK (0x80U) +#define SGI_SGI_CONFIG_HAS_CMAC_SHIFT (7U) +/*! HAS_CMAC - HAS CMAC */ +#define SGI_SGI_CONFIG_HAS_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_HAS_CMAC_SHIFT)) & SGI_SGI_CONFIG_HAS_CMAC_MASK) + +#define SGI_SGI_CONFIG_HAS_GFMUL_MASK (0x100U) +#define SGI_SGI_CONFIG_HAS_GFMUL_SHIFT (8U) +/*! HAS_GFMUL - HAS GFMUL */ +#define SGI_SGI_CONFIG_HAS_GFMUL(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_HAS_GFMUL_SHIFT)) & SGI_SGI_CONFIG_HAS_GFMUL_MASK) + +#define SGI_SGI_CONFIG_INTERNAL_PRNG_MASK (0x200U) +#define SGI_SGI_CONFIG_INTERNAL_PRNG_SHIFT (9U) +/*! INTERNAL_PRNG - HAS INTERNAL PRNG */ +#define SGI_SGI_CONFIG_INTERNAL_PRNG(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_INTERNAL_PRNG_SHIFT)) & SGI_SGI_CONFIG_INTERNAL_PRNG_MASK) + +#define SGI_SGI_CONFIG_KEY_DIGEST_MASK (0x400U) +#define SGI_SGI_CONFIG_KEY_DIGEST_SHIFT (10U) +/*! KEY_DIGEST - HAS KEY DIGEST */ +#define SGI_SGI_CONFIG_KEY_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_KEY_DIGEST_SHIFT)) & SGI_SGI_CONFIG_KEY_DIGEST_MASK) + +#define SGI_SGI_CONFIG_COUNT_SIZE_MASK (0x800U) +#define SGI_SGI_CONFIG_COUNT_SIZE_SHIFT (11U) +/*! COUNT_SIZE - 0 - COUNT=16, 1 - COUNT=32 */ +#define SGI_SGI_CONFIG_COUNT_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_COUNT_SIZE_SHIFT)) & SGI_SGI_CONFIG_COUNT_SIZE_MASK) + +#define SGI_SGI_CONFIG_FA_MASK (0x2000U) +#define SGI_SGI_CONFIG_FA_SHIFT (13U) +/*! FA - HAS FA protection */ +#define SGI_SGI_CONFIG_FA(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_FA_SHIFT)) & SGI_SGI_CONFIG_FA_MASK) + +#define SGI_SGI_CONFIG_BUS_WIDTH_MASK (0x8000U) +#define SGI_SGI_CONFIG_BUS_WIDTH_SHIFT (15U) +/*! BUS_WIDTH - 0 - BUS_WIDTH=16, 1 - BUS_WIDTH=32 */ +#define SGI_SGI_CONFIG_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_BUS_WIDTH_SHIFT)) & SGI_SGI_CONFIG_BUS_WIDTH_MASK) + +#define SGI_SGI_CONFIG_NUM_DATIN_MASK (0x30000U) +#define SGI_SGI_CONFIG_NUM_DATIN_SHIFT (16U) +/*! NUM_DATIN - NUMBER OF DATIN REGBANKS */ +#define SGI_SGI_CONFIG_NUM_DATIN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_NUM_DATIN_SHIFT)) & SGI_SGI_CONFIG_NUM_DATIN_MASK) + +#define SGI_SGI_CONFIG_NUM_KEY_MASK (0x1C0000U) +#define SGI_SGI_CONFIG_NUM_KEY_SHIFT (18U) +/*! NUM_KEY - NUMBER OR KEY REGBANKS */ +#define SGI_SGI_CONFIG_NUM_KEY(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_NUM_KEY_SHIFT)) & SGI_SGI_CONFIG_NUM_KEY_MASK) + +#define SGI_SGI_CONFIG_EDC_MASK (0x200000U) +#define SGI_SGI_CONFIG_EDC_SHIFT (21U) +/*! EDC - DATIN to KERNEL End-to-end EDC is enabled */ +#define SGI_SGI_CONFIG_EDC(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_EDC_SHIFT)) & SGI_SGI_CONFIG_EDC_MASK) + +#define SGI_SGI_CONFIG_SHA_256_ONLY_MASK (0x1000000U) +#define SGI_SGI_CONFIG_SHA_256_ONLY_SHIFT (24U) +/*! SHA_256_ONLY - HAS SHA-256 ONLY */ +#define SGI_SGI_CONFIG_SHA_256_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_SHA_256_ONLY_SHIFT)) & SGI_SGI_CONFIG_SHA_256_ONLY_MASK) + +#define SGI_SGI_CONFIG_SPB_SUPPORT_MASK (0x2000000U) +#define SGI_SGI_CONFIG_SPB_SUPPORT_SHIFT (25U) +/*! SPB_SUPPORT - ID_CFG_SGI_SPB_SUPPORT is set */ +#define SGI_SGI_CONFIG_SPB_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_SPB_SUPPORT_SHIFT)) & SGI_SGI_CONFIG_SPB_SUPPORT_MASK) + +#define SGI_SGI_CONFIG_SPB_MASKING_MASK (0x4000000U) +#define SGI_SGI_CONFIG_SPB_MASKING_SHIFT (26U) +/*! SPB_MASKING - ID_CFG_SGI_SPB_MASKING is set */ +#define SGI_SGI_CONFIG_SPB_MASKING(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_SPB_MASKING_SHIFT)) & SGI_SGI_CONFIG_SPB_MASKING_MASK) + +#define SGI_SGI_CONFIG_SFR_SW_MASK_MASK (0x8000000U) +#define SGI_SGI_CONFIG_SFR_SW_MASK_SHIFT (27U) +/*! SFR_SW_MASK - ID_CFG_SGI_USE_SFR_SW_MASK is set */ +#define SGI_SGI_CONFIG_SFR_SW_MASK(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG_SFR_SW_MASK_SHIFT)) & SGI_SGI_CONFIG_SFR_SW_MASK_MASK) +/*! @} */ + +/*! @name SGI_CONFIG2 - SHA Configuration 2 Reg */ +/*! @{ */ + +#define SGI_SGI_CONFIG2_AES_USED_MASK (0xFU) +#define SGI_SGI_CONFIG2_AES_USED_SHIFT (0U) +/*! AES_USED + * 0b0000..Apollo + * 0b0001..Aegis + * 0b0010..Ayna + * 0b0011..Athenium + * 0b0100..Ajax + * 0b0101..Aegis_hs + * 0b0110..Athenium_hs + * 0b0111..ATE + * 0b1000..ATOM + * 0b1001..Asterix + * 0b1010-0b1111..RFU + */ +#define SGI_SGI_CONFIG2_AES_USED(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG2_AES_USED_SHIFT)) & SGI_SGI_CONFIG2_AES_USED_MASK) + +#define SGI_SGI_CONFIG2_AES_NUM_SBOXES_MASK (0x1F0U) +#define SGI_SGI_CONFIG2_AES_NUM_SBOXES_SHIFT (4U) +/*! AES_NUM_SBOXES - Number of AES sboxes */ +#define SGI_SGI_CONFIG2_AES_NUM_SBOXES(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG2_AES_NUM_SBOXES_SHIFT)) & SGI_SGI_CONFIG2_AES_NUM_SBOXES_MASK) + +#define SGI_SGI_CONFIG2_AES_KEYSIZE_MASK (0x600U) +#define SGI_SGI_CONFIG2_AES_KEYSIZE_SHIFT (9U) +/*! AES_KEYSIZE + * 0b00..128 0nly + * 0b10..256 only + * 0b11..All key sizes + */ +#define SGI_SGI_CONFIG2_AES_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG2_AES_KEYSIZE_SHIFT)) & SGI_SGI_CONFIG2_AES_KEYSIZE_MASK) + +#define SGI_SGI_CONFIG2_DES_USED_MASK (0xF0000U) +#define SGI_SGI_CONFIG2_DES_USED_SHIFT (16U) +/*! DES_USED + * 0b0000..Dakar + * 0b0001..Danube + * 0b0010..Depicta + * 0b0011..Digi + * 0b0100..Date + * 0b0101..Desert + * 0b0110-0b1111..RFU + */ +#define SGI_SGI_CONFIG2_DES_USED(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG2_DES_USED_SHIFT)) & SGI_SGI_CONFIG2_DES_USED_MASK) + +#define SGI_SGI_CONFIG2_DES_NUM_SBOXES_MASK (0x1F00000U) +#define SGI_SGI_CONFIG2_DES_NUM_SBOXES_SHIFT (20U) +/*! DES_NUM_SBOXES - Number of DES sboxes */ +#define SGI_SGI_CONFIG2_DES_NUM_SBOXES(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_CONFIG2_DES_NUM_SBOXES_SHIFT)) & SGI_SGI_CONFIG2_DES_NUM_SBOXES_MASK) +/*! @} */ + +/*! @name SGI_AUTO_MODE - SGI Auto Mode Control register */ +/*! @{ */ + +#define SGI_SGI_AUTO_MODE_AUTO_MODE_EN_MASK (0x1U) +#define SGI_SGI_AUTO_MODE_AUTO_MODE_EN_SHIFT (0U) +/*! AUTO_MODE_EN - auto_start_en + * 0b1..auto mode has been selected + */ +#define SGI_SGI_AUTO_MODE_AUTO_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_AUTO_MODE_AUTO_MODE_EN_SHIFT)) & SGI_SGI_AUTO_MODE_AUTO_MODE_EN_MASK) + +#define SGI_SGI_AUTO_MODE_AUTO_MODE_STOP_MASK (0x2U) +#define SGI_SGI_AUTO_MODE_AUTO_MODE_STOP_SHIFT (1U) +/*! AUTO_MODE_STOP - auto_mode_stop + * 0b1..exit auto mode as soon as the data has been emptied + */ +#define SGI_SGI_AUTO_MODE_AUTO_MODE_STOP(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_AUTO_MODE_AUTO_MODE_STOP_SHIFT)) & SGI_SGI_AUTO_MODE_AUTO_MODE_STOP_MASK) + +#define SGI_SGI_AUTO_MODE_INCR_MODE_MASK (0x30U) +#define SGI_SGI_AUTO_MODE_INCR_MODE_SHIFT (4U) +/*! INCR_MODE - CTR increment mode + * 0b00..2**32 increment mode + * 0b01..2**64 increment mode + * 0b10..2**96 increment mode + * 0b11..2**128 increment mode + */ +#define SGI_SGI_AUTO_MODE_INCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_AUTO_MODE_INCR_MODE_SHIFT)) & SGI_SGI_AUTO_MODE_INCR_MODE_MASK) + +#define SGI_SGI_AUTO_MODE_CMD_MASK (0xFF00U) +#define SGI_SGI_AUTO_MODE_CMD_SHIFT (8U) +/*! CMD - Auto mode of operation + * 0b00000000..ECB mode + * 0b00000001..CTR mode + * 0b00000010..CBC mode + * 0b00000011..CBCMAC mode + * 0b00010000..Key Wrap/Unwrap (128 bit key data) + * 0b00010001..Key Wrap/Unwrap (256 bit key data) + */ +#define SGI_SGI_AUTO_MODE_CMD(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_AUTO_MODE_CMD_SHIFT)) & SGI_SGI_AUTO_MODE_CMD_MASK) +/*! @} */ + +/*! @name SGI_AUTO_DMA_CTRL - SGI Auto Mode Control register */ +/*! @{ */ + +#define SGI_SGI_AUTO_DMA_CTRL_IFE_MASK (0x1U) +#define SGI_SGI_AUTO_DMA_CTRL_IFE_SHIFT (0U) +/*! IFE - Input FIFO DMA Enable + * 0b0..DMA handshake disabled + * 0b1..DMA handshake enabled + */ +#define SGI_SGI_AUTO_DMA_CTRL_IFE(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_AUTO_DMA_CTRL_IFE_SHIFT)) & SGI_SGI_AUTO_DMA_CTRL_IFE_MASK) + +#define SGI_SGI_AUTO_DMA_CTRL_OFE_MASK (0x100U) +#define SGI_SGI_AUTO_DMA_CTRL_OFE_SHIFT (8U) +/*! OFE - Ouput FIFO DMA Enable + * 0b0..DMA handshake disabled + * 0b1..DMA handshake enabled + */ +#define SGI_SGI_AUTO_DMA_CTRL_OFE(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_AUTO_DMA_CTRL_OFE_SHIFT)) & SGI_SGI_AUTO_DMA_CTRL_OFE_MASK) +/*! @} */ + +/*! @name SGI_PRNG_SW_SEED - SGI internal PRNG SW seeding register */ +/*! @{ */ + +#define SGI_SGI_PRNG_SW_SEED_SEED_MASK (0xFFFFFFFFU) +#define SGI_SGI_PRNG_SW_SEED_SEED_SHIFT (0U) +#define SGI_SGI_PRNG_SW_SEED_SEED(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_PRNG_SW_SEED_SEED_SHIFT)) & SGI_SGI_PRNG_SW_SEED_SEED_MASK) +/*! @} */ + +/*! @name SGI_KEY_CTRL - SGI Key Control SFR */ +/*! @{ */ + +#define SGI_SGI_KEY_CTRL_KEY_WO_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY_CTRL_KEY_WO_SHIFT (0U) +#define SGI_SGI_KEY_CTRL_KEY_WO(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY_CTRL_KEY_WO_SHIFT)) & SGI_SGI_KEY_CTRL_KEY_WO_MASK) +/*! @} */ + +/*! @name SGI_KEY_WRAP - Wrapped key read SFR */ +/*! @{ */ + +#define SGI_SGI_KEY_WRAP_KW_DATA_MASK (0xFFFFFFFFU) +#define SGI_SGI_KEY_WRAP_KW_DATA_SHIFT (0U) +/*! KW_DATA - Field contains wrapped key, auto-updated by HW for each word */ +#define SGI_SGI_KEY_WRAP_KW_DATA(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_KEY_WRAP_KW_DATA_SHIFT)) & SGI_SGI_KEY_WRAP_KW_DATA_MASK) +/*! @} */ + +/*! @name SGI_VERSION - SGI Version */ +/*! @{ */ + +#define SGI_SGI_VERSION_Z_MASK (0xFU) +#define SGI_SGI_VERSION_Z_SHIFT (0U) +/*! Z - Extended revision number in X.Y1Y2.Z, e.g. 1.20.3. */ +#define SGI_SGI_VERSION_Z(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_VERSION_Z_SHIFT)) & SGI_SGI_VERSION_Z_MASK) + +#define SGI_SGI_VERSION_Y2_MASK (0xF0U) +#define SGI_SGI_VERSION_Y2_SHIFT (4U) +/*! Y2 - Minor revision number 2 in X.Y1Y2.Z, e.g. 1.20.3. */ +#define SGI_SGI_VERSION_Y2(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_VERSION_Y2_SHIFT)) & SGI_SGI_VERSION_Y2_MASK) + +#define SGI_SGI_VERSION_Y1_MASK (0xF00U) +#define SGI_SGI_VERSION_Y1_SHIFT (8U) +/*! Y1 - Minor revision number 1 in X.Y1Y2.Z, e.g. 1.20.3. */ +#define SGI_SGI_VERSION_Y1(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_VERSION_Y1_SHIFT)) & SGI_SGI_VERSION_Y1_MASK) + +#define SGI_SGI_VERSION_X_MASK (0xF000U) +#define SGI_SGI_VERSION_X_SHIFT (12U) +/*! X - Major revision number in X.Y1Y2.Z, e.g. 1.20.3. */ +#define SGI_SGI_VERSION_X(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_VERSION_X_SHIFT)) & SGI_SGI_VERSION_X_MASK) + +#define SGI_SGI_VERSION_MILESTONE_MASK (0x30000U) +#define SGI_SGI_VERSION_MILESTONE_SHIFT (16U) +/*! MILESTONE + * 0b00..PREL + * 0b01..BR + * 0b10..SI + * 0b11..GO + */ +#define SGI_SGI_VERSION_MILESTONE(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_VERSION_MILESTONE_SHIFT)) & SGI_SGI_VERSION_MILESTONE_MASK) +/*! @} */ + +/*! @name SGI_ACCESS_ERR - Access Error */ +/*! @{ */ + +#define SGI_SGI_ACCESS_ERR_APB_NOTAV_MASK (0x1U) +#define SGI_SGI_ACCESS_ERR_APB_NOTAV_SHIFT (0U) +/*! APB_NOTAV - APB Error: address not available */ +#define SGI_SGI_ACCESS_ERR_APB_NOTAV(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_ACCESS_ERR_APB_NOTAV_SHIFT)) & SGI_SGI_ACCESS_ERR_APB_NOTAV_MASK) + +#define SGI_SGI_ACCESS_ERR_APB_WRGMD_MASK (0x2U) +#define SGI_SGI_ACCESS_ERR_APB_WRGMD_SHIFT (1U) +/*! APB_WRGMD - APB Error: Wrong access mode */ +#define SGI_SGI_ACCESS_ERR_APB_WRGMD(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_ACCESS_ERR_APB_WRGMD_SHIFT)) & SGI_SGI_ACCESS_ERR_APB_WRGMD_MASK) + +#define SGI_SGI_ACCESS_ERR_APB_MASTER_MASK (0xF0U) +#define SGI_SGI_ACCESS_ERR_APB_MASTER_SHIFT (4U) +#define SGI_SGI_ACCESS_ERR_APB_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_ACCESS_ERR_APB_MASTER_SHIFT)) & SGI_SGI_ACCESS_ERR_APB_MASTER_MASK) +/*! @} */ + +/*! @name SGI_ACCESS_ERR_CLR - Clear Access Error */ +/*! @{ */ + +#define SGI_SGI_ACCESS_ERR_CLR_ERR_CLR_MASK (0x1U) +#define SGI_SGI_ACCESS_ERR_CLR_ERR_CLR_SHIFT (0U) +/*! ERR_CLR - Write to reset SGI_ACCESS_ERR SFR. */ +#define SGI_SGI_ACCESS_ERR_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & SGI_SGI_ACCESS_ERR_CLR_ERR_CLR_MASK) +/*! @} */ + +/*! @name SGI_INT_STATUS - Interrupt status */ +/*! @{ */ + +#define SGI_SGI_INT_STATUS_INT_PDONE_MASK (0x1U) +#define SGI_SGI_INT_STATUS_INT_PDONE_SHIFT (0U) +#define SGI_SGI_INT_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_INT_STATUS_INT_PDONE_SHIFT)) & SGI_SGI_INT_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name SGI_INT_ENABLE - Interrupt enable */ +/*! @{ */ + +#define SGI_SGI_INT_ENABLE_INT_EN_MASK (0x1U) +#define SGI_SGI_INT_ENABLE_INT_EN_SHIFT (0U) +/*! INT_EN - Interrupt enable bit */ +#define SGI_SGI_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_INT_ENABLE_INT_EN_SHIFT)) & SGI_SGI_INT_ENABLE_INT_EN_MASK) +/*! @} */ + +/*! @name SGI_INT_STATUS_CLR - Interrupt status clear */ +/*! @{ */ + +#define SGI_SGI_INT_STATUS_CLR_INT_CLR_MASK (0x1U) +#define SGI_SGI_INT_STATUS_CLR_INT_CLR_SHIFT (0U) +/*! INT_CLR - Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0). */ +#define SGI_SGI_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_INT_STATUS_CLR_INT_CLR_SHIFT)) & SGI_SGI_INT_STATUS_CLR_INT_CLR_MASK) +/*! @} */ + +/*! @name SGI_INT_STATUS_SET - Interrupt status set */ +/*! @{ */ + +#define SGI_SGI_INT_STATUS_SET_INT_SET_MASK (0x1U) +#define SGI_SGI_INT_STATUS_SET_INT_SET_SHIFT (0U) +/*! INT_SET - Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI + * interrupt via software, e.g. for debug purposes. + */ +#define SGI_SGI_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_INT_STATUS_SET_INT_SET_SHIFT)) & SGI_SGI_INT_STATUS_SET_INT_SET_MASK) +/*! @} */ + +/*! @name SGI_MODULE_ID - Module ID */ +/*! @{ */ + +#define SGI_SGI_MODULE_ID_PLACEHOLDER_MASK (0xFFFFFFFFU) +#define SGI_SGI_MODULE_ID_PLACEHOLDER_SHIFT (0U) +/*! PLACEHOLDER - Module ID */ +#define SGI_SGI_MODULE_ID_PLACEHOLDER(x) (((uint32_t)(((uint32_t)(x)) << SGI_SGI_MODULE_ID_PLACEHOLDER_SHIFT)) & SGI_SGI_MODULE_ID_PLACEHOLDER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SGI_Register_Masks */ + + +/*! + * @} + */ /* end of group SGI_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SGI_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SMARTDMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SMARTDMA.h new file mode 100644 index 000000000..f9075eb11 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SMARTDMA.h @@ -0,0 +1,286 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for SMARTDMA +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_SMARTDMA.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for SMARTDMA + * + * CMSIS Peripheral Access Layer for SMARTDMA + */ + +#if !defined(PERI_SMARTDMA_H_) +#define PERI_SMARTDMA_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Peripheral_Access_Layer SMARTDMA Peripheral Access Layer + * @{ + */ + +/** SMARTDMA - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t BOOTADR; /**< Boot Address, offset: 0x20 */ + __IO uint32_t CTRL; /**< Control, offset: 0x24 */ + __I uint32_t PC; /**< Program Counter, offset: 0x28 */ + __I uint32_t SP; /**< Stack Pointer, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t ARM2EZH; /**< ARM to EZH Interrupt Control, offset: 0x40 */ + __IO uint32_t EZH2ARM; /**< EZH to ARM Trigger, offset: 0x44 */ + __IO uint32_t PENDTRAP; /**< Pending Trap Control, offset: 0x48 */ +} SMARTDMA_Type; + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Register_Masks SMARTDMA Register Masks + * @{ + */ + +/*! @name BOOTADR - Boot Address */ +/*! @{ */ + +#define SMARTDMA_BOOTADR_ADDR_MASK (0xFFFFFFFCU) +#define SMARTDMA_BOOTADR_ADDR_SHIFT (2U) +/*! ADDR - 32-bit boot address, the boot address should be 4-byte aligned. */ +#define SMARTDMA_BOOTADR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BOOTADR_ADDR_SHIFT)) & SMARTDMA_BOOTADR_ADDR_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define SMARTDMA_CTRL_START_MASK (0x1U) +#define SMARTDMA_CTRL_START_SHIFT (0U) +/*! START - Start Bit Ignition */ +#define SMARTDMA_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_START_SHIFT)) & SMARTDMA_CTRL_START_MASK) + +#define SMARTDMA_CTRL_EXF_MASK (0x2U) +#define SMARTDMA_CTRL_EXF_SHIFT (1U) +/*! EXF - External Flag */ +#define SMARTDMA_CTRL_EXF(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_EXF_SHIFT)) & SMARTDMA_CTRL_EXF_MASK) + +#define SMARTDMA_CTRL_ERRDIS_MASK (0x4U) +#define SMARTDMA_CTRL_ERRDIS_SHIFT (2U) +/*! ERRDIS - Error Disable */ +#define SMARTDMA_CTRL_ERRDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_ERRDIS_SHIFT)) & SMARTDMA_CTRL_ERRDIS_MASK) + +#define SMARTDMA_CTRL_BUFEN_MASK (0x8U) +#define SMARTDMA_CTRL_BUFEN_SHIFT (3U) +/*! BUFEN - Buffer Enable */ +#define SMARTDMA_CTRL_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_BUFEN_SHIFT)) & SMARTDMA_CTRL_BUFEN_MASK) + +#define SMARTDMA_CTRL_SYNCEN_MASK (0x10U) +#define SMARTDMA_CTRL_SYNCEN_SHIFT (4U) +/*! SYNCEN - Sync Enable */ +#define SMARTDMA_CTRL_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_SYNCEN_SHIFT)) & SMARTDMA_CTRL_SYNCEN_MASK) + +#define SMARTDMA_CTRL_WKEY_MASK (0xFFFF0000U) +#define SMARTDMA_CTRL_WKEY_SHIFT (16U) +/*! WKEY - Write Key */ +#define SMARTDMA_CTRL_WKEY(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_WKEY_SHIFT)) & SMARTDMA_CTRL_WKEY_MASK) +/*! @} */ + +/*! @name PC - Program Counter */ +/*! @{ */ + +#define SMARTDMA_PC_PC_MASK (0xFFFFFFFFU) +#define SMARTDMA_PC_PC_SHIFT (0U) +/*! PC - Program Counter */ +#define SMARTDMA_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PC_PC_SHIFT)) & SMARTDMA_PC_PC_MASK) +/*! @} */ + +/*! @name SP - Stack Pointer */ +/*! @{ */ + +#define SMARTDMA_SP_SP_MASK (0xFFFFFFFFU) +#define SMARTDMA_SP_SP_SHIFT (0U) +/*! SP - Stack Pointer */ +#define SMARTDMA_SP_SP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_SP_SP_SHIFT)) & SMARTDMA_SP_SP_MASK) +/*! @} */ + +/*! @name ARM2EZH - ARM to EZH Interrupt Control */ +/*! @{ */ + +#define SMARTDMA_ARM2EZH_IE_MASK (0x3U) +#define SMARTDMA_ARM2EZH_IE_SHIFT (0U) +/*! IE - Interrupt Enable */ +#define SMARTDMA_ARM2EZH_IE(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_IE_SHIFT)) & SMARTDMA_ARM2EZH_IE_MASK) + +#define SMARTDMA_ARM2EZH_GP_MASK (0xFFFFFFFCU) +#define SMARTDMA_ARM2EZH_GP_SHIFT (2U) +/*! GP - General purpose register bits */ +#define SMARTDMA_ARM2EZH_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_GP_SHIFT)) & SMARTDMA_ARM2EZH_GP_MASK) +/*! @} */ + +/*! @name EZH2ARM - EZH to ARM Trigger */ +/*! @{ */ + +#define SMARTDMA_EZH2ARM_GP_MASK (0xFFFFFFFFU) +#define SMARTDMA_EZH2ARM_GP_SHIFT (0U) +/*! GP - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH [1:0] == 2h */ +#define SMARTDMA_EZH2ARM_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EZH2ARM_GP_SHIFT)) & SMARTDMA_EZH2ARM_GP_MASK) +/*! @} */ + +/*! @name PENDTRAP - Pending Trap Control */ +/*! @{ */ + +#define SMARTDMA_PENDTRAP_STATUS_MASK (0xFFU) +#define SMARTDMA_PENDTRAP_STATUS_SHIFT (0U) +/*! STATUS - Status Flag or Pending Trap Request */ +#define SMARTDMA_PENDTRAP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_STATUS_SHIFT)) & SMARTDMA_PENDTRAP_STATUS_MASK) + +#define SMARTDMA_PENDTRAP_POL_MASK (0xFF00U) +#define SMARTDMA_PENDTRAP_POL_SHIFT (8U) +/*! POL - Polarity */ +#define SMARTDMA_PENDTRAP_POL(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_POL_SHIFT)) & SMARTDMA_PENDTRAP_POL_MASK) + +#define SMARTDMA_PENDTRAP_EN_MASK (0xFF0000U) +#define SMARTDMA_PENDTRAP_EN_SHIFT (16U) +/*! EN - Enable Pending Trap */ +#define SMARTDMA_PENDTRAP_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_EN_SHIFT)) & SMARTDMA_PENDTRAP_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SMARTDMA_Register_Masks */ + + +/*! + * @} + */ /* end of group SMARTDMA_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SMARTDMA_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SPC.h new file mode 100644 index 000000000..d4d194c3d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SPC.h @@ -0,0 +1,683 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for SPC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_SPC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for SPC + * + * CMSIS Peripheral Access Layer for SPC + */ + +#if !defined(PERI_SPC_H_) +#define PERI_SPC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer + * @{ + */ + +/** SPC - Size of Registers Arrays */ +#define SPC_PD_STATUS_COUNT 1u + +/** SPC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SC; /**< Status Control, offset: 0x10 */ + __IO uint32_t CNTRL; /**< SPC Regulator Control, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPREQ_CFG; /**< Low-Power Request Configuration, offset: 0x1C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PD_STATUS[SPC_PD_STATUS_COUNT]; /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SRAMCTL; /**< SRAM Control, offset: 0x40 */ + uint8_t RESERVED_4[16]; + __IO uint32_t SRAMRETLDO_REFTRIM; /**< SRAM Retention Reference Trim, offset: 0x54 */ + __IO uint32_t SRAMRETLDO_CNTRL; /**< SRAM Retention LDO Control, offset: 0x58 */ + uint8_t RESERVED_5[164]; + __IO uint32_t ACTIVE_CFG; /**< Active Power Mode Configuration, offset: 0x100 */ + __IO uint32_t ACTIVE_CFG1; /**< Active Power Mode Configuration 1, offset: 0x104 */ + __IO uint32_t LP_CFG; /**< Low-Power Mode Configuration, offset: 0x108 */ + __IO uint32_t LP_CFG1; /**< Low Power Mode Configuration 1, offset: 0x10C */ + uint8_t RESERVED_6[16]; + __IO uint32_t LPWKUP_DELAY; /**< Low Power Wake-Up Delay, offset: 0x120 */ + __IO uint32_t ACTIVE_VDELAY; /**< Active Voltage Trim Delay, offset: 0x124 */ + uint8_t RESERVED_7[8]; + __IO uint32_t VD_STAT; /**< Voltage Detect Status, offset: 0x130 */ + __IO uint32_t VD_CORE_CFG; /**< Core Voltage Detect Configuration, offset: 0x134 */ + __IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */ + uint8_t RESERVED_8[4]; + __IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */ + uint8_t RESERVED_9[444]; + uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */ +} SPC_Type; + +/* ---------------------------------------------------------------------------- + -- SPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Register_Masks SPC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define SPC_VERID_FEATURE_MASK (0xFFFFU) +#define SPC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features + */ +#define SPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK) + +#define SPC_VERID_MINOR_MASK (0xFF0000U) +#define SPC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define SPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK) + +#define SPC_VERID_MAJOR_MASK (0xFF000000U) +#define SPC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define SPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name SC - Status Control */ +/*! @{ */ + +#define SPC_SC_BUSY_MASK (0x1U) +#define SPC_SC_BUSY_SHIFT (0U) +/*! BUSY - SPC Busy Status Flag + * 0b0..Not busy + * 0b1..Busy + */ +#define SPC_SC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK) + +#define SPC_SC_SPC_LP_REQ_MASK (0x2U) +#define SPC_SC_SPC_LP_REQ_SHIFT (1U) +/*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag + * 0b0..No effect + * 0b0..SPC is in Active mode; the ACTIVE_CFG register has control + * 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register + * 0b1..Clear the flag + */ +#define SPC_SC_SPC_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK) + +#define SPC_SC_SPC_LP_MODE_MASK (0xF0U) +#define SPC_SC_SPC_LP_MODE_SHIFT (4U) +/*! SPC_LP_MODE - Power Domain Low-Power Mode Request + * 0b0000.. + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_SC_SPC_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK) + +#define SPC_SC_ISO_CLR_MASK (0x10000U) +#define SPC_SC_ISO_CLR_SHIFT (16U) +/*! ISO_CLR - Isolation Clear Flags */ +#define SPC_SC_ISO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK) +/*! @} */ + +/*! @name CNTRL - SPC Regulator Control */ +/*! @{ */ + +#define SPC_CNTRL_CORELDO_EN_MASK (0x1U) +#define SPC_CNTRL_CORELDO_EN_SHIFT (0U) +/*! CORELDO_EN - LDO_CORE Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_CORELDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_CORELDO_EN_SHIFT)) & SPC_CNTRL_CORELDO_EN_MASK) +/*! @} */ + +/*! @name LPREQ_CFG - Low-Power Request Configuration */ +/*! @{ */ + +#define SPC_LPREQ_CFG_LPREQOE_MASK (0x1U) +#define SPC_LPREQ_CFG_LPREQOE_SHIFT (0U) +/*! LPREQOE - Low-Power Request Output Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LPREQ_CFG_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK) + +#define SPC_LPREQ_CFG_LPREQPOL_MASK (0x2U) +#define SPC_LPREQ_CFG_LPREQPOL_SHIFT (1U) +/*! LPREQPOL - Low-Power Request Output Pin Polarity Control + * 0b0..High + * 0b1..Low + */ +#define SPC_LPREQ_CFG_LPREQPOL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK) + +#define SPC_LPREQ_CFG_LPREQOV_MASK (0xCU) +#define SPC_LPREQ_CFG_LPREQOV_SHIFT (2U) +/*! LPREQOV - Low-Power Request Output Override + * 0b00..Not forced + * 0b01.. + * 0b10..Forced low (ignore LPREQPOL settings) + * 0b11..Forced high (ignore LPREQPOL settings) + */ +#define SPC_LPREQ_CFG_LPREQOV(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK) +/*! @} */ + +/*! @name PD_STATUS - SPC Power Domain Mode Status */ +/*! @{ */ + +#define SPC_PD_STATUS_PD_LP_REQ_MASK (0x10U) +#define SPC_PD_STATUS_PD_LP_REQ_SHIFT (4U) +/*! PD_LP_REQ - Power Domain Low Power Request Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PD_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK) + +#define SPC_PD_STATUS_LP_MODE_MASK (0xF00U) +#define SPC_PD_STATUS_LP_MODE_SHIFT (8U) +/*! LP_MODE - Power Domain Low Power Mode Request + * 0b0000.. + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_PD_STATUS_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK) +/*! @} */ + +/*! @name SRAMCTL - SRAM Control */ +/*! @{ */ + +#define SPC_SRAMCTL_VSM_MASK (0x3U) +#define SPC_SRAMCTL_VSM_SHIFT (0U) +/*! VSM - Voltage Select Margin + * 0b00.. + * 0b01..1.0 V + * 0b10..1.1 V + * 0b11.. + */ +#define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK) + +#define SPC_SRAMCTL_REQ_MASK (0x40000000U) +#define SPC_SRAMCTL_REQ_SHIFT (30U) +/*! REQ - SRAM Voltage Update Request + * 0b0..Do not request + * 0b1..Request + */ +#define SPC_SRAMCTL_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK) + +#define SPC_SRAMCTL_ACK_MASK (0x80000000U) +#define SPC_SRAMCTL_ACK_SHIFT (31U) +/*! ACK - SRAM Voltage Update Request Acknowledge + * 0b0..Not acknowledged + * 0b1..Acknowledged + */ +#define SPC_SRAMCTL_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK) +/*! @} */ + +/*! @name SRAMRETLDO_REFTRIM - SRAM Retention Reference Trim */ +/*! @{ */ + +#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK (0x1FU) +#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT (0U) +/*! REFTRIM - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV. */ +#define SPC_SRAMRETLDO_REFTRIM_REFTRIM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT)) & SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) +/*! @} */ + +/*! @name SRAMRETLDO_CNTRL - SRAM Retention LDO Control */ +/*! @{ */ + +#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK (0x1U) +#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT (0U) +/*! SRAMLDO_ON - SRAM LDO Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK) + +#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK (0xF00U) +#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT (8U) +/*! SRAM_RET_EN - SRAM Retention */ +#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG - Active Power Mode Configuration */ +/*! @{ */ + +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00.. + * 0b01..Regulate to mid voltage (1.0 V) + * 0b10..Regulate to normal voltage (1.1 V) + * 0b11..Regulate to overdrive voltage (1.15 V) + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_BGMODE_MASK (0x300000U) +#define SPC_ACTIVE_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_ACTIVE_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK) + +#define SPC_ACTIVE_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Active Config Chip Control */ +#define SPC_ACTIVE_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LP_CFG - Low-Power Mode Configuration */ +/*! @{ */ + +#define SPC_LP_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_LP_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00..Reserved + * 0b01..Mid voltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.15 V) + */ +#define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_LP_CFG_SRAMLDO_DPD_ON_MASK (0x80000U) +#define SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT (19U) +/*! SRAMLDO_DPD_ON - SRAM_LDO Deep Power Low Power IREF Enable + * 0b0..Low Power IREF is disabled for power saving in Deep Power Down mode + * 0b1..Low Power IREF is enabled + */ +#define SPC_LP_CFG_SRAMLDO_DPD_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT)) & SPC_LP_CFG_SRAMLDO_DPD_ON_MASK) + +#define SPC_LP_CFG_BGMODE_MASK (0x300000U) +#define SPC_LP_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_LP_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK) + +#define SPC_LP_CFG_LP_IREFEN_MASK (0x800000U) +#define SPC_LP_CFG_LP_IREFEN_SHIFT (23U) +/*! LP_IREFEN - Low-Power IREF Enable + * 0b0..Disable for power saving in Deep Power Down mode + * 0b1..Enable + */ +#define SPC_LP_CFG_LP_IREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK) + +#define SPC_LP_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_LP_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK) + +#define SPC_LP_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_LP_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK) + +#define SPC_LP_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_LP_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK) +/*! @} */ + +/*! @name LP_CFG1 - Low Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_LP_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_LP_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Low-Power Configuration Chip Control */ +#define SPC_LP_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */ +/*! @{ */ + +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK (0xFFFFU) +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT (0U) +/*! LPWKUP_DELAY - Low-Power Wake-Up Delay */ +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK) +/*! @} */ + +/*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */ +/*! @{ */ + +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK (0xFFFFU) +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT (0U) +/*! ACTIVE_VDELAY - Active Voltage Delay */ +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK) +/*! @} */ + +/*! @name VD_STAT - Voltage Detect Status */ +/*! @{ */ + +#define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U) +#define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U) +/*! COREVDD_LVDF - Core Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Event detected + */ +#define SPC_VD_STAT_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U) +#define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U) +/*! SYSVDD_LVDF - System Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Event detected + */ +#define SPC_VD_STAT_SYSVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U) +#define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U) +/*! SYSVDD_HVDF - System HVD Flag + * 0b0..Event not detected + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Event detected + */ +#define SPC_VD_STAT_SYSVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK) +/*! @} */ + +/*! @name VD_CORE_CFG - Core Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - Core LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK) + +#define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - Core LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK) + +#define SPC_VD_CORE_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_CORE_CFG_LOCK_SHIFT (16U) +/*! LOCK - Core Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_CORE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK) +/*! @} */ + +/*! @name VD_SYS_CFG - System Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - System LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK) + +#define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - System LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK) + +#define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - System HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK) + +#define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - System HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) + +#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - System Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) + +#define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) +/*! LOCK - System Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_SYS_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK) +/*! @} */ + +/*! @name EVD_CFG - External Voltage Domain Configuration */ +/*! @{ */ + +#define SPC_EVD_CFG_EVDISO_MASK (0x7U) +#define SPC_EVD_CFG_EVDISO_SHIFT (0U) +/*! EVDISO - External Voltage Domain Isolation */ +#define SPC_EVD_CFG_EVDISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK) + +#define SPC_EVD_CFG_EVDLPISO_MASK (0x700U) +#define SPC_EVD_CFG_EVDLPISO_SHIFT (8U) +/*! EVDLPISO - External Voltage Domain Low-Power Isolation */ +#define SPC_EVD_CFG_EVDLPISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK) + +#define SPC_EVD_CFG_EVDSTAT_MASK (0x70000U) +#define SPC_EVD_CFG_EVDSTAT_SHIFT (16U) +/*! EVDSTAT - External Voltage Domain Status */ +#define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPC_Register_Masks */ + + +/*! + * @} + */ /* end of group SPC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SPC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SYSCON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SYSCON.h new file mode 100644 index 000000000..90b2cd210 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_SYSCON.h @@ -0,0 +1,1507 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for SYSCON +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_SYSCON.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for SYSCON + * + * CMSIS Peripheral Access Layer for SYSCON + */ + +#if !defined(PERI_SYSCON_H_) +#define PERI_SYSCON_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[512]; + __IO uint32_t REMAP; /**< AHB Matrix Remap Control, offset: 0x200 */ + uint8_t RESERVED_1[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix Priority Control, offset: 0x210 */ + uint8_t RESERVED_2[40]; + __IO uint32_t CPU0NSTCKCAL; /**< Non-Secure CPU0 System Tick Calibration, offset: 0x23C */ + uint8_t RESERVED_3[8]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x248 */ + __IO uint32_t PROTLVL; /**< Protect Level Control, offset: 0x24C */ + uint8_t RESERVED_4[296]; + __IO uint32_t SLOWCLKDIV; /**< SLOW_CLK Clock Divider, offset: 0x378 */ + __IO uint32_t BUSCLKDIV; /**< BUS_CLK Clock Divider, offset: 0x37C */ + __IO uint32_t AHBCLKDIV; /**< System Clock Divider, offset: 0x380 */ + uint8_t RESERVED_5[4]; + __IO uint32_t FROHFDIV; /**< FRO_HF_DIV Clock Divider, offset: 0x388 */ + __IO uint32_t FROLFDIV; /**< FRO_LF_DIV Clock Divider, offset: 0x38C */ + uint8_t RESERVED_6[84]; + __IO uint32_t PLL1CLKDIV; /**< PLL1_CLK_DIV Clock Divider, offset: 0x3E4 */ + uint8_t RESERVED_7[20]; + __IO uint32_t CLKUNLOCK; /**< Clock Configuration Unlock, offset: 0x3FC */ + __IO uint32_t NVM_CTRL; /**< NVM Control, offset: 0x400 */ + uint8_t RESERVED_8[16]; + __IO uint32_t SMARTDMAINT; /**< SmartDMA Interrupt Hijack, offset: 0x414 */ + uint8_t RESERVED_9[88]; + __IO uint32_t RAM_INTERLEAVE; /**< Controls RAM Interleave Integration, offset: 0x470 */ + uint8_t RESERVED_10[920]; + __I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_11[20]; + __IO uint32_t LPCAC_CTRL; /**< LPCAC Control, offset: 0x824 */ + uint8_t RESERVED_12[272]; + __IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0x938 */ + __IO uint32_t PWM1SUBCTL; /**< PWM1 Submodule Control, offset: 0x93C */ + __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0x940 */ + __IO uint32_t RAM_CTRL; /**< RAM Control, offset: 0x944 */ + uint8_t RESERVED_13[536]; + __IO uint32_t GRAY_CODE_LSB; /**< Gray to Binary Converter Gray Code [31:0], offset: 0xB60 */ + __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray Code [41:32], offset: 0xB64 */ + __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */ + __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */ + uint8_t RESERVED_14[684]; + __IO uint32_t MSFCFG; /**< MSF Configuration, offset: 0xE1C */ + uint8_t RESERVED_15[28]; + __I uint32_t ROP_STATE; /**< ROP State Register, offset: 0xE3C */ + uint8_t RESERVED_16[24]; + __IO uint32_t SRAM_XEN; /**< RAM XEN Control, offset: 0xE58 */ + __IO uint32_t SRAM_XEN_DP; /**< RAM XEN Control (Duplicate), offset: 0xE5C */ + uint8_t RESERVED_17[32]; + __I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0xE80 */ + __I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0xE84 */ + uint8_t RESERVED_18[280]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */ + uint8_t RESERVED_19[8]; + __IO uint32_t SWD_ACCESS_CPU0; /**< CPU0 Software Debug Access, offset: 0xFB4 */ + uint8_t RESERVED_20[8]; + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */ + uint8_t RESERVED_21[44]; + __I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */ + __I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip Revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name REMAP - AHB Matrix Remap Control */ +/*! @{ */ + +#define SYSCON_REMAP_CPU0_SBUS_MASK (0xCU) +#define SYSCON_REMAP_CPU0_SBUS_SHIFT (2U) +/*! CPU0_SBUS - RAMX0 address remap for CPU System bus + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is + * 0x20000000 + (system ram size - RAMX size)*1024. + */ +#define SYSCON_REMAP_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_CPU0_SBUS_SHIFT)) & SYSCON_REMAP_CPU0_SBUS_MASK) + +#define SYSCON_REMAP_SMARTDMA_I_MASK (0x30U) +#define SYSCON_REMAP_SMARTDMA_I_SHIFT (4U) +/*! SmartDMA_I - RAMX0 address remap for SmartDMA I-BUS + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_SMARTDMA_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_SMARTDMA_I_SHIFT)) & SYSCON_REMAP_SMARTDMA_I_MASK) + +#define SYSCON_REMAP_SMARTDMA_D_MASK (0xC0U) +#define SYSCON_REMAP_SMARTDMA_D_SHIFT (6U) +/*! SmartDMA_D - RAMX0 address remap for SmartDMA D-BUS + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_SMARTDMA_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_SMARTDMA_D_SHIFT)) & SYSCON_REMAP_SMARTDMA_D_MASK) + +#define SYSCON_REMAP_DMA0_MASK (0x300U) +#define SYSCON_REMAP_DMA0_SHIFT (8U) +/*! DMA0 - RAMX0 address remap for DMA0 + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_DMA0_SHIFT)) & SYSCON_REMAP_DMA0_MASK) + +#define SYSCON_REMAP_PKC_MASK (0x3000U) +#define SYSCON_REMAP_PKC_SHIFT (12U) +/*! PKC - RAMX0 address remap for PKC + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_PKC_SHIFT)) & SYSCON_REMAP_PKC_MASK) + +#define SYSCON_REMAP_USB0_MASK (0x3000000U) +#define SYSCON_REMAP_USB0_SHIFT (24U) +/*! USB0 - RAMX0 address remap for USB0 + * 0b00..RAMX0: alias space is disabled. + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_USB0_SHIFT)) & SYSCON_REMAP_USB0_MASK) + +#define SYSCON_REMAP_LOCK_MASK (0x80000000U) +#define SYSCON_REMAP_LOCK_SHIFT (31U) +/*! LOCK - This 1-bit field provides a mechanism to limit writes to this register to protect its + * contents. Once set, this bit remains asserted until a system reset. + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered until a system reset. + */ +#define SYSCON_REMAP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_LOCK_SHIFT)) & SYSCON_REMAP_LOCK_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix Priority Control */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT (0U) +/*! CPU0_CBUS - CPU0 C-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT (2U) +/*! CPU0_SBUS - CPU0 S-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_MASK (0x30U) +#define SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_SHIFT (4U) +/*! CPU1_CBUS_SmartDMA_I - SmartDMA-I bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_SHIFT)) & SYSCON_AHBMATPRIO_CPU1_CBUS_SMARTDMA_I_MASK) + +#define SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_SHIFT (6U) +/*! CPU1_SBUS_SmartDMA_D - SmartDMA-D bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_SHIFT)) & SYSCON_AHBMATPRIO_CPU1_SBUS_SMARTDMA_D_MASK) + +#define SYSCON_AHBMATPRIO_DMA0_MASK (0x300U) +#define SYSCON_AHBMATPRIO_DMA0_SHIFT (8U) +/*! DMA0 - DMA0 controller bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK) + +#define SYSCON_AHBMATPRIO_PKC_ELS_MASK (0x3000U) +#define SYSCON_AHBMATPRIO_PKC_ELS_SHIFT (12U) +/*! PKC_ELS - PKC and ELS bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PKC_ELS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PKC_ELS_SHIFT)) & SYSCON_AHBMATPRIO_PKC_ELS_MASK) + +#define SYSCON_AHBMATPRIO_USB_FS_ENET_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_USB_FS_ENET_SHIFT (24U) +/*! USB_FS_ENET - USB-FS bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_USB_FS_ENET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_USB_FS_ENET_SHIFT)) & SYSCON_AHBMATPRIO_USB_FS_ENET_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0xFFU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + * 0b0..Disable. + * 0b1..Enable. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PROTLVL - Protect Level Control */ +/*! @{ */ + +#define SYSCON_PROTLVL_PRIV_MASK (0x1U) +#define SYSCON_PROTLVL_PRIV_SHIFT (0U) +/*! PRIV - Control privileged access of EIM, ERM, Flexcan, MBC, SCG. + * 0b0..privileged access is disabled. the peripherals could be access in user mode. + * 0b1..privileged access is enabled. the peripherals could be access in privilege mode. + */ +#define SYSCON_PROTLVL_PRIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PROTLVL_PRIV_SHIFT)) & SYSCON_PROTLVL_PRIV_MASK) + +#define SYSCON_PROTLVL_LOCKNSMPU_MASK (0x10000U) +#define SYSCON_PROTLVL_LOCKNSMPU_SHIFT (16U) +/*! LOCKNSMPU - Control write access to Nonsecure MPU memory regions. + * 0b0..Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed. + * 0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and + * MPU_RLAR_A_NSn. All writes to the registers are ignored. + */ +#define SYSCON_PROTLVL_LOCKNSMPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PROTLVL_LOCKNSMPU_SHIFT)) & SYSCON_PROTLVL_LOCKNSMPU_MASK) + +#define SYSCON_PROTLVL_LOCK_MASK (0x80000000U) +#define SYSCON_PROTLVL_LOCK_SHIFT (31U) +/*! LOCK - This 1-bit field provides a mechanism to limit writes to this register to protect its + * contents. Once set, this bit remains asserted until a system reset. + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered until a system reset. + */ +#define SYSCON_PROTLVL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PROTLVL_LOCK_SHIFT)) & SYSCON_PROTLVL_LOCK_MASK) +/*! @} */ + +/*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */ +/*! @{ */ + +#define SYSCON_SLOWCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SLOWCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SLOWCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_DIV_SHIFT)) & SYSCON_SLOWCLKDIV_DIV_MASK) + +#define SYSCON_SLOWCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SLOWCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_SLOWCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK) + +#define SYSCON_SLOWCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SLOWCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define SYSCON_SLOWCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK) + +#define SYSCON_SLOWCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_SLOWCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name BUSCLKDIV - BUS_CLK Clock Divider */ +/*! @{ */ + +#define SYSCON_BUSCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_BUSCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_BUSCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_DIV_SHIFT)) & SYSCON_BUSCLKDIV_DIV_MASK) + +#define SYSCON_BUSCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_BUSCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_BUSCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_RESET_SHIFT)) & SYSCON_BUSCLKDIV_RESET_MASK) + +#define SYSCON_BUSCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_BUSCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define SYSCON_BUSCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_HALT_SHIFT)) & SYSCON_BUSCLKDIV_HALT_MASK) + +#define SYSCON_BUSCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_BUSCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_BUSCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BUSCLKDIV_UNSTAB_SHIFT)) & SYSCON_BUSCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name AHBCLKDIV - System Clock Divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF_DIV Clock Divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FROHFDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_FROHFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FROLFDIV - FRO_LF_DIV Clock Divider */ +/*! @{ */ + +#define SYSCON_FROLFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROLFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FROLFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_DIV_SHIFT)) & SYSCON_FROLFDIV_DIV_MASK) + +#define SYSCON_FROLFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROLFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_FROLFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_RESET_SHIFT)) & SYSCON_FROLFDIV_RESET_MASK) + +#define SYSCON_FROLFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROLFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define SYSCON_FROLFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_HALT_SHIFT)) & SYSCON_FROLFDIV_HALT_MASK) + +#define SYSCON_FROLFDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FROLFDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_FROLFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROLFDIV_UNSTAB_SHIFT)) & SYSCON_FROLFDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name PLL1CLKDIV - PLL1_CLK_DIV Clock Divider */ +/*! @{ */ + +#define SYSCON_PLL1CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLL1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLL1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKDIV_DIV_SHIFT)) & SYSCON_PLL1CLKDIV_DIV_MASK) + +#define SYSCON_PLL1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_PLL1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKDIV_RESET_SHIFT)) & SYSCON_PLL1CLKDIV_RESET_MASK) + +#define SYSCON_PLL1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define SYSCON_PLL1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKDIV_HALT_SHIFT)) & SYSCON_PLL1CLKDIV_HALT_MASK) + +#define SYSCON_PLL1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLL1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency is not stable + */ +#define SYSCON_PLL1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKDIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKUNLOCK - Clock Configuration Unlock */ +/*! @{ */ + +#define SYSCON_CLKUNLOCK_UNLOCK_MASK (0x1U) +#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U) +/*! UNLOCK - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, + * AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx) + * 0b0..Updates are allowed to all clock configuration registers + * 0b1..Freezes all clock configuration registers update. + */ +#define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK) +/*! @} */ + +/*! @name NVM_CTRL - NVM Control */ +/*! @{ */ + +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK (0x1U) +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT (0U) +/*! DIS_FLASH_SPEC - Flash speculation control + * 0b0..Enables flash speculation + * 0b1..Disables flash speculation + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK) + +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK (0x2U) +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT (1U) +/*! DIS_DATA_SPEC - Flash data speculation control + * 0b0..Enables data speculation + * 0b1..Disables data speculation + */ +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK) + +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK (0x400U) +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT (10U) +/*! FLASH_STALL_EN - FLASH stall on busy control + * 0b0..No stall on FLASH busy + * 0b1..Stall on FLASH busy + */ +#define SYSCON_NVM_CTRL_FLASH_STALL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK (0x10000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U) +/*! DIS_MBECC_ERR_INST + * 0b0..Enables bus error on multi-bit ECC error for instruction + * 0b1..Disables bus error on multi-bit ECC error for instruction + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK (0x20000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U) +/*! DIS_MBECC_ERR_DATA + * 0b0..Enables bus error on multi-bit ECC error for data + * 0b1..Disables bus error on multi-bit ECC error for data + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK) +/*! @} */ + +/*! @name SMARTDMAINT - SmartDMA Interrupt Hijack */ +/*! @{ */ + +#define SYSCON_SMARTDMAINT_INT0_MASK (0x1U) +#define SYSCON_SMARTDMAINT_INT0_SHIFT (0U) +/*! INT0 - SmartDMA hijack NVIC IRQ2 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT0_SHIFT)) & SYSCON_SMARTDMAINT_INT0_MASK) + +#define SYSCON_SMARTDMAINT_INT1_MASK (0x2U) +#define SYSCON_SMARTDMAINT_INT1_SHIFT (1U) +/*! INT1 - SmartDMA hijack NVIC IRQ23 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT1_SHIFT)) & SYSCON_SMARTDMAINT_INT1_MASK) + +#define SYSCON_SMARTDMAINT_INT2_MASK (0x4U) +#define SYSCON_SMARTDMAINT_INT2_SHIFT (2U) +/*! INT2 - SmartDMA hijack NVIC IRQ26 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT2_SHIFT)) & SYSCON_SMARTDMAINT_INT2_MASK) + +#define SYSCON_SMARTDMAINT_INT3_MASK (0x8U) +#define SYSCON_SMARTDMAINT_INT3_SHIFT (3U) +/*! INT3 - SmartDMA hijack NVIC IRQ27 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT3_SHIFT)) & SYSCON_SMARTDMAINT_INT3_MASK) + +#define SYSCON_SMARTDMAINT_INT4_MASK (0x10U) +#define SYSCON_SMARTDMAINT_INT4_SHIFT (4U) +/*! INT4 - SmartDMA hijack NVIC IRQ28 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT4_SHIFT)) & SYSCON_SMARTDMAINT_INT4_MASK) + +#define SYSCON_SMARTDMAINT_INT5_MASK (0x20U) +#define SYSCON_SMARTDMAINT_INT5_SHIFT (5U) +/*! INT5 - SmartDMA hijack NVIC IRQ29 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT5_SHIFT)) & SYSCON_SMARTDMAINT_INT5_MASK) + +#define SYSCON_SMARTDMAINT_INT6_MASK (0x40U) +#define SYSCON_SMARTDMAINT_INT6_SHIFT (6U) +/*! INT6 - SmartDMA hijack NVIC IRQ31 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT6_SHIFT)) & SYSCON_SMARTDMAINT_INT6_MASK) + +#define SYSCON_SMARTDMAINT_INT7_MASK (0x80U) +#define SYSCON_SMARTDMAINT_INT7_SHIFT (7U) +/*! INT7 - SmartDMA hijack NVIC IRQ32 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT7_SHIFT)) & SYSCON_SMARTDMAINT_INT7_MASK) + +#define SYSCON_SMARTDMAINT_INT8_MASK (0x100U) +#define SYSCON_SMARTDMAINT_INT8_SHIFT (8U) +/*! INT8 - SmartDMA hijack NVIC IRQ33 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT8_SHIFT)) & SYSCON_SMARTDMAINT_INT8_MASK) + +#define SYSCON_SMARTDMAINT_INT9_MASK (0x200U) +#define SYSCON_SMARTDMAINT_INT9_SHIFT (9U) +/*! INT9 - SmartDMA hijack NVIC IRQ34 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT9_SHIFT)) & SYSCON_SMARTDMAINT_INT9_MASK) + +#define SYSCON_SMARTDMAINT_INT10_MASK (0x400U) +#define SYSCON_SMARTDMAINT_INT10_SHIFT (10U) +/*! INT10 - SmartDMA hijack NVIC IRQ36 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT10_SHIFT)) & SYSCON_SMARTDMAINT_INT10_MASK) + +#define SYSCON_SMARTDMAINT_INT11_MASK (0x800U) +#define SYSCON_SMARTDMAINT_INT11_SHIFT (11U) +/*! INT11 - SmartDMA hijack NVIC IRQ39 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT11(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT11_SHIFT)) & SYSCON_SMARTDMAINT_INT11_MASK) + +#define SYSCON_SMARTDMAINT_INT12_MASK (0x1000U) +#define SYSCON_SMARTDMAINT_INT12_SHIFT (12U) +/*! INT12 - SmartDMA hijack NVIC IRQ40 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT12(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT12_SHIFT)) & SYSCON_SMARTDMAINT_INT12_MASK) + +#define SYSCON_SMARTDMAINT_INT13_MASK (0x2000U) +#define SYSCON_SMARTDMAINT_INT13_SHIFT (13U) +/*! INT13 - SmartDMA hijack NVIC IRQ41 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT13(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT13_SHIFT)) & SYSCON_SMARTDMAINT_INT13_MASK) + +#define SYSCON_SMARTDMAINT_INT14_MASK (0x4000U) +#define SYSCON_SMARTDMAINT_INT14_SHIFT (14U) +/*! INT14 - SmartDMA hijack NVIC IRQ59 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT14(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT14_SHIFT)) & SYSCON_SMARTDMAINT_INT14_MASK) + +#define SYSCON_SMARTDMAINT_INT15_MASK (0x8000U) +#define SYSCON_SMARTDMAINT_INT15_SHIFT (15U) +/*! INT15 - SmartDMA hijack NVIC IRQ62 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT15(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT15_SHIFT)) & SYSCON_SMARTDMAINT_INT15_MASK) + +#define SYSCON_SMARTDMAINT_INT16_MASK (0x10000U) +#define SYSCON_SMARTDMAINT_INT16_SHIFT (16U) +/*! INT16 - SmartDMA hijack NVIC IRQ64 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT16(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT16_SHIFT)) & SYSCON_SMARTDMAINT_INT16_MASK) + +#define SYSCON_SMARTDMAINT_INT17_MASK (0x20000U) +#define SYSCON_SMARTDMAINT_INT17_SHIFT (17U) +/*! INT17 - SmartDMA hijack NVIC IRQ71 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT17(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT17_SHIFT)) & SYSCON_SMARTDMAINT_INT17_MASK) + +#define SYSCON_SMARTDMAINT_INT18_MASK (0x40000U) +#define SYSCON_SMARTDMAINT_INT18_SHIFT (18U) +/*! INT18 - SmartDMA hijack NVIC IRQ72 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT18(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT18_SHIFT)) & SYSCON_SMARTDMAINT_INT18_MASK) + +#define SYSCON_SMARTDMAINT_INT19_MASK (0x80000U) +#define SYSCON_SMARTDMAINT_INT19_SHIFT (19U) +/*! INT19 - SmartDMA hijack NVIC IRQ73 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT19(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT19_SHIFT)) & SYSCON_SMARTDMAINT_INT19_MASK) + +#define SYSCON_SMARTDMAINT_INT20_MASK (0x100000U) +#define SYSCON_SMARTDMAINT_INT20_SHIFT (20U) +/*! INT20 - SmartDMA hijack NVIC IRQ74 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT20(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT20_SHIFT)) & SYSCON_SMARTDMAINT_INT20_MASK) + +#define SYSCON_SMARTDMAINT_INT21_MASK (0x200000U) +#define SYSCON_SMARTDMAINT_INT21_SHIFT (21U) +/*! INT21 - SmartDMA hijack NVIC IRQ75 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT21(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT21_SHIFT)) & SYSCON_SMARTDMAINT_INT21_MASK) +/*! @} */ + +/*! @name RAM_INTERLEAVE - Controls RAM Interleave Integration */ +/*! @{ */ + +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK (0x1U) +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT (0U) +/*! INTERLEAVE - Controls RAM access for RAMA1 and RAMA2 + * 0b0..RAM access is consecutive. + * 0b1..RAM access is interleaved. This setting is need for PKC L0 memory access. + */ +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT)) & SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK) +/*! @} */ + +/*! @name CPUSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - CPU0 sleeping state + * 0b0..CPU is not sleeping + * 0b1..CPU is sleeping + */ +#define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - CPU0 lockup state + * 0b0..CPU is not in lockup + * 0b1..CPU is in lockup + */ +#define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK) +/*! @} */ + +/*! @name LPCAC_CTRL - LPCAC Control */ +/*! @{ */ + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U) +/*! DIS_LPCAC - Disables/enables the cache function. + * 0b0..Enabled + * 0b1..Disabled + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U) +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U) +/*! CLR_LPCAC - Clears the cache function. + * 0b0..Unclears the cache + * 0b1..Clears the cache + */ +#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U) +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U) +/*! FRC_NO_ALLOC - Forces no allocation. + * 0b0..Forces allocation + * 0b1..Forces no allocation + */ +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK) + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK (0x10U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT (4U) +/*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer. + * 0b0..Enables write through buffer + * 0b1..Disables write through buffer + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK (0x20U) +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT (5U) +/*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer. + * 0b0..Write buffer enabled when transaction is bufferable. + * 0b1..Write buffer enabled when transaction is cacheable and bufferable + */ +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK (0x80U) +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT (7U) +/*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SYSCON_LPCAC_CTRL_LPCAC_XOM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK) + +#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK (0x100U) +#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT (8U) +/*! LPCAC_MEM_REQ - Request LPCAC memories. + * 0b0..Configure shared memories RAMX1 as general memories. + * 0b1..Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset. + */ +#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK) +/*! @} */ + +/*! @name PWM0SUBCTL - PWM0 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM0 SUB Clock0 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM0 SUB Clock1 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM0 SUB Clock2 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM0 SUB Clock3 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK) +/*! @} */ + +/*! @name PWM1SUBCTL - PWM1 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM1 SUB Clock0 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM1SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM1 SUB Clock1 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM1SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM1 SUB Clock2 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM1SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM1 SUB Clock3 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_PWM1SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK) +/*! @} */ + +/*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */ +/*! @{ */ + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U) +/*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U) +/*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U) +/*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U) +/*! CTIMER3_CLK_EN - Enables the CTIMER3 function clock + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U) +/*! CTIMER4_CLK_EN - Enables the CTIMER4 function clock + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK) +/*! @} */ + +/*! @name RAM_CTRL - RAM Control */ +/*! @{ */ + +#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK (0x1U) +#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT (0U) +/*! RAMA_ECC_ENABLE - RAMA ECC enable + * 0b0..ECC is disabled + * 0b1..ECC is enabled + */ +#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK) + +#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK (0x10000U) +#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT (16U) +/*! RAMA_CG_OVERRIDE - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0. + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + * 0b1..Auto clock gating feature is disabled + */ +#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK) + +#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK (0x20000U) +#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT (17U) +/*! RAMX_CG_OVERRIDE - RAMX bank clock gating control + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + * 0b1..Auto clock gating feature is disabled + */ +#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK) + +#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_MASK (0x40000U) +#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_SHIFT (18U) +/*! RAMB_CG_OVERRIDE - RAMB bank clock gating control + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + * 0b1..Auto clock gating feature is disabled + */ +#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_MASK) + +#define SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_MASK (0x80000U) +#define SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_SHIFT (19U) +/*! RAMC_CG_OVERRIDE - RAMC bank clock gating control + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + * 0b1..Auto clock gating feature is disabled + */ +#define SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMC_CG_OVERRIDE_MASK) +/*! @} */ + +/*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray Code [31:0] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT (0U) +/*! code_gray_31_0 - Gray code [31:0] */ +#define SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_CODE_GRAY_31_0_MASK) +/*! @} */ + +/*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray Code [41:32] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_MASK (0x3FFU) +#define SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_SHIFT (0U) +/*! code_gray_41_32 - Gray code [41:32] */ +#define SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_CODE_GRAY_41_32_MASK) +/*! @} */ + +/*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT (0U) +/*! code_bin_31_0 - Binary code [31:0] */ +#define SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_CODE_BIN_31_0_MASK) +/*! @} */ + +/*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_MASK (0x3FFU) +#define SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_SHIFT (0U) +/*! code_bin_41_32 - Binary code [41:32] */ +#define SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_CODE_BIN_41_32_MASK) +/*! @} */ + +/*! @name MSFCFG - MSF Configuration */ +/*! @{ */ + +#define SYSCON_MSFCFG_IFR_ERASE_DIS0_MASK (0x1U) +#define SYSCON_MSFCFG_IFR_ERASE_DIS0_SHIFT (0U) +/*! IFR_ERASE_DIS0 - user IFR sector 0 erase control + * 0b0..Enable IFR sector erase. + * 0b1..Disable IFR sector erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_IFR_ERASE_DIS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS0_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS0_MASK) + +#define SYSCON_MSFCFG_IFR_ERASE_DIS1_MASK (0x2U) +#define SYSCON_MSFCFG_IFR_ERASE_DIS1_SHIFT (1U) +/*! IFR_ERASE_DIS1 - user IFR sector 1 erase control + * 0b0..Enable IFR sector erase. + * 0b1..Disable IFR sector erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_IFR_ERASE_DIS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS1_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS1_MASK) + +#define SYSCON_MSFCFG_IFR_ERASE_DIS2_MASK (0x4U) +#define SYSCON_MSFCFG_IFR_ERASE_DIS2_SHIFT (2U) +/*! IFR_ERASE_DIS2 - user IFR sector 2 erase control + * 0b0..Enable IFR sector erase. + * 0b1..Disable IFR sector erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_IFR_ERASE_DIS2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS2_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS2_MASK) + +#define SYSCON_MSFCFG_IFR_ERASE_DIS3_MASK (0x8U) +#define SYSCON_MSFCFG_IFR_ERASE_DIS3_SHIFT (3U) +/*! IFR_ERASE_DIS3 - user IFR sector 3 erase control + * 0b0..Enable IFR sector erase. + * 0b1..Disable IFR sector erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_IFR_ERASE_DIS3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_IFR_ERASE_DIS3_SHIFT)) & SYSCON_MSFCFG_IFR_ERASE_DIS3_MASK) + +#define SYSCON_MSFCFG_MASS_ERASE_DIS_MASK (0x100U) +#define SYSCON_MSFCFG_MASS_ERASE_DIS_SHIFT (8U) +/*! MASS_ERASE_DIS - Mass erase control + * 0b0..Enables mass erase + * 0b1..Disables mass erase, write one lock until a system reset. + */ +#define SYSCON_MSFCFG_MASS_ERASE_DIS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MSFCFG_MASS_ERASE_DIS_SHIFT)) & SYSCON_MSFCFG_MASS_ERASE_DIS_MASK) +/*! @} */ + +/*! @name ROP_STATE - ROP State Register */ +/*! @{ */ + +#define SYSCON_ROP_STATE_ROP_STATE_MASK (0xFFFFFFFFU) +#define SYSCON_ROP_STATE_ROP_STATE_SHIFT (0U) +/*! ROP_STATE - ROP state */ +#define SYSCON_ROP_STATE_ROP_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROP_STATE_ROP_STATE_SHIFT)) & SYSCON_ROP_STATE_ROP_STATE_MASK) +/*! @} */ + +/*! @name SRAM_XEN - RAM XEN Control */ +/*! @{ */ + +#define SYSCON_SRAM_XEN_RAMX0_XEN_MASK (0x1U) +#define SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT (0U) +/*! RAMX0_XEN - RAMX0 Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMX0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX0_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMX1_XEN_MASK (0x2U) +#define SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT (1U) +/*! RAMX1_XEN - RAMX1 Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMX1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX1_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMA0_XEN_MASK (0x4U) +#define SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT (2U) +/*! RAMA0_XEN - RAMA0 Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMA0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA0_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMA1_XEN_MASK (0x8U) +#define SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT (3U) +/*! RAMA1_XEN - RAMAx (excepts RAMA0) Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMA1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA1_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMB_XEN_MASK (0x10U) +#define SYSCON_SRAM_XEN_RAMB_XEN_SHIFT (4U) +/*! RAMB_XEN - RAMBx Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMB_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMB_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMB_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMC_XEN_MASK (0x20U) +#define SYSCON_SRAM_XEN_RAMC_XEN_SHIFT (5U) +/*! RAMC_XEN - RAMCx Execute permission control. + * 0b0..Execute permission is disabled, R/W are enabled. + * 0b1..Execute permission is enabled, R/W/X are enabled. + */ +#define SYSCON_SRAM_XEN_RAMC_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMC_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMC_XEN_MASK) + +#define SYSCON_SRAM_XEN_LOCK_MASK (0x80000000U) +#define SYSCON_SRAM_XEN_LOCK_SHIFT (31U) +/*! LOCK - This 1-bit field provides a mechanism to limit writes to this register (and SRAM_XEN_DP) + * to protect its contents. Once set, this bit remains asserted until a system reset. + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define SYSCON_SRAM_XEN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_LOCK_SHIFT)) & SYSCON_SRAM_XEN_LOCK_MASK) +/*! @} */ + +/*! @name SRAM_XEN_DP - RAM XEN Control (Duplicate) */ +/*! @{ */ + +#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK (0x1U) +#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT (0U) +/*! RAMX0_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMX0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK (0x2U) +#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT (1U) +/*! RAMX1_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMX1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK (0x4U) +#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT (2U) +/*! RAMA0_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMA0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK (0x8U) +#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT (3U) +/*! RAMA1_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMA1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMB_XEN_MASK (0x10U) +#define SYSCON_SRAM_XEN_DP_RAMB_XEN_SHIFT (4U) +/*! RAMB_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMB_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMB_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMB_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMC_XEN_MASK (0x20U) +#define SYSCON_SRAM_XEN_DP_RAMC_XEN_SHIFT (5U) +/*! RAMC_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMC_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMC_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMC_XEN_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE - Life Cycle State Register */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U) +/*! OTP_LC_STATE - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U) +/*! OTP_LC_STATE_DP - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control Write Access to Security */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Controls write access to the security registers + * 0b0000..Any other value than b1010: disables write access to all registers + * 0b1010..Enables write access to all registers + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex Debug Features Control */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) +/*! @} */ + +/*! @name SWD_ACCESS_CPU0 - CPU0 Software Debug Access */ +/*! @{ */ + +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - CPU0 SWD-AP: 0x12345678 + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5. + * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. + */ +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to the application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name JTAG_ID - JTAG Chip ID */ +/*! @{ */ + +#define SYSCON_JTAG_ID_JTAG_ID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAG_ID_JTAG_ID_SHIFT (0U) +/*! JTAG_ID - Indicates the device ID */ +#define SYSCON_JTAG_ID_JTAG_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK) +/*! @} */ + +/*! @name DEVICE_TYPE - Device Type */ +/*! @{ */ + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK (0xFFFFU) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT (0U) +/*! DEVICE_TYPE_NUM - Indicates the device part number */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK) + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK (0x10000U) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT (16U) +/*! DEVICE_TYPE_SEC - Indicates the device type + * 0b0..Non Secure + * 0b1..Secure + */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK) + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK (0xF00000U) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT (20U) +/*! DEVICE_TYPE_PKG - Indicates the device's package type + * 0b0000..HLQFP + * 0b0001..HTQFP + * 0b0010..BGA + * 0b0011..HDQFP + * 0b0100..QFN + * 0b0101..CSP + * 0b0110..LQFP + */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK) + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK (0xFF000000U) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT (24U) +/*! DEVICE_TYPE_PIN - Indicates the device's pin number */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_RAM_SIZE_MASK (0xFU) +#define SYSCON_DEVICE_ID0_RAM_SIZE_SHIFT (0U) +/*! RAM_SIZE - Indicates the device's ram size + * 0b0000..8KB. + * 0b0001..16KB. + * 0b0010..32KB. + * 0b0011..64KB. + * 0b0100..96KB. + * 0b0101..128KB. + * 0b0110..160KB. + * 0b0111..192KB. + * 0b1000..256KB. + * 0b1001..288KB. + * 0b1010..352KB. + * 0b1011..512KB. + */ +#define SYSCON_DEVICE_ID0_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_RAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_RAM_SIZE_MASK) + +#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0xF0U) +#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (4U) +/*! FLASH_SIZE - Indicates the device's flash size + * 0b0000..32KB. + * 0b0001..64KB. + * 0b0010..128KB. + * 0b0011..256KB. + * 0b0100..512KB. + * 0b0101..768KB. + * 0b0110..1MB. + * 0b0111..1.5MB. + * 0b1000..2MB. + */ +#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK) + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - Indicates the device's ROM revision */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) + +#define SYSCON_DEVICE_ID0_SECURITY_MASK (0xF000000U) +#define SYSCON_DEVICE_ID0_SECURITY_SHIFT (24U) +/*! SECURITY + * 0b0101..Secure version. + * 0b1010..Non secure version. + */ +#define SYSCON_DEVICE_ID0_SECURITY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SECURITY_SHIFT)) & SYSCON_DEVICE_ID0_SECURITY_MASK) +/*! @} */ + +/*! @name DIEID - Chip Revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_MINOR_REVISION_MASK (0xFU) +#define SYSCON_DIEID_MINOR_REVISION_SHIFT (0U) +/*! MINOR_REVISION - Chip minor revision */ +#define SYSCON_DIEID_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MINOR_REVISION_SHIFT)) & SYSCON_DIEID_MINOR_REVISION_MASK) + +#define SYSCON_DIEID_MAJOR_REVISION_MASK (0xF0U) +#define SYSCON_DIEID_MAJOR_REVISION_SHIFT (4U) +/*! MAJOR_REVISION - Chip major revision */ +#define SYSCON_DIEID_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MAJOR_REVISION_SHIFT)) & SYSCON_DIEID_MAJOR_REVISION_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF00U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (8U) +/*! MCO_NUM_IN_DIE_ID - Chip number */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_SYSCON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_TRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_TRDC.h new file mode 100644 index 000000000..0a7ab75ff --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_TRDC.h @@ -0,0 +1,937 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for TRDC +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_TRDC.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for TRDC + * + * CMSIS Peripheral Access Layer for TRDC + */ + +#if !defined(PERI_TRDC_H_) +#define PERI_TRDC_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- TRDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer + * @{ + */ + +/** TRDC - Size of Registers Arrays */ +#define MBC_MEM_GLBCFG_COUNT 4u +#define MBC_MEMN_GLBAC_COUNT 8u +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_COUNT 16u +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_COUNT 2u +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_COUNT 1u +#define TRDC_MBC_INDEX_COUNT 1u + +/** TRDC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x1AC */ + __IO uint32_t MBC_MEM_GLBCFG[MBC_MEM_GLBCFG_COUNT]; /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1AC, index2*0x4 */ + uint8_t RESERVED_0[16]; + __IO uint32_t MBC_MEMN_GLBAC[MBC_MEMN_GLBAC_COUNT]; /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1AC, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_COUNT]; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1AC, index2*0x4 */ + uint8_t RESERVED_1[256]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_COUNT]; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1AC, index2*0x4 */ + uint8_t RESERVED_2[32]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_COUNT]; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1AC, index2*0x4 */ + } MBC_INDEX[TRDC_MBC_INDEX_COUNT]; +} TRDC_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Register_Masks TRDC Register Masks + * @{ + */ + +/*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK (0xC0000000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U) +/*! CLRE - Clear Error */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (2U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + + +/*! + * @} + */ /* end of group TRDC_Register_Masks */ + + +/*! + * @} + */ /* end of group TRDC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_TRDC_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_TRNG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_TRNG.h new file mode 100644 index 000000000..832b07160 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_TRNG.h @@ -0,0 +1,1162 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for TRNG +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_TRNG.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for TRNG + * + * CMSIS Peripheral Access Layer for TRNG + */ + +#if !defined(PERI_TRNG_H_) +#define PERI_TRNG_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- TRNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer + * @{ + */ + +/** TRNG - Size of Registers Arrays */ +#define TRNG_ENTA_COUNT 8u + +/** TRNG - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ + __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ + __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ + __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ + }; + __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ + union { /* offset: 0x14 */ + __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ + __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ + }; + union { /* offset: 0x18 */ + __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ + __I uint32_t OSC2_FRQCNT; /**< Oscillator-2 Frequency Count Register, offset: 0x18 */ + }; + union { /* offset: 0x1C */ + __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ + __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ + }; + union { /* offset: 0x20 */ + __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ + __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ + }; + union { /* offset: 0x24 */ + __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ + __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ + }; + union { /* offset: 0x28 */ + __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ + __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ + }; + union { /* offset: 0x2C */ + __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ + __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ + }; + union { /* offset: 0x30 */ + __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ + __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ + }; + union { /* offset: 0x34 */ + __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ + __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ + }; + union { /* offset: 0x38 */ + __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ + __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ + }; + __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ + __I uint32_t ENT[TRNG_ENTA_COUNT]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_0[32]; + __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ + __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ + __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ + __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ + __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ + __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ + __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ + __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ + __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ + __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ + __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ + __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ + __I uint32_t CSER; /**< Common Security Error Register, offset: 0xB0 */ + __O uint32_t CSCLR; /**< Common Security Clear Register, offset: 0xB4 */ + uint8_t RESERVED_1[52]; + __IO uint32_t OSC2_CTL; /**< TRNG Oscillator 2 Control Register, offset: 0xEC */ + __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ + __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ +} TRNG_Type; + +/* ---------------------------------------------------------------------------- + -- TRNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Register_Masks TRNG Register Masks + * @{ + */ + +/*! @name MCTL - Miscellaneous Control Register */ +/*! @{ */ + +#define TRNG_MCTL_OSC_DIV_MASK (0xCU) +#define TRNG_MCTL_OSC_DIV_SHIFT (2U) +/*! OSC_DIV - Oscillator1 Divide + * 0b00..use ring oscillator with no divide + * 0b01..use ring oscillator divided-by-2 + * 0b10..use ring oscillator divided-by-4 + * 0b11..use ring oscillator divided-by-8 + */ +#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) + +#define TRNG_MCTL_DIS_SLF_TST_MASK (0x10U) +#define TRNG_MCTL_DIS_SLF_TST_SHIFT (4U) +/*! DIS_SLF_TST - Disable Self-Tests */ +#define TRNG_MCTL_DIS_SLF_TST(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_DIS_SLF_TST_SHIFT)) & TRNG_MCTL_DIS_SLF_TST_MASK) + +#define TRNG_MCTL_TRNG_ACC_MASK (0x20U) +#define TRNG_MCTL_TRNG_ACC_SHIFT (5U) +/*! TRNG_ACC - TRNG Access Mode */ +#define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK) + +#define TRNG_MCTL_RST_DEF_MASK (0x40U) +#define TRNG_MCTL_RST_DEF_SHIFT (6U) +/*! RST_DEF - Reset Defaults + * 0b0..No impact. + * 0b1..Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state. + */ +#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) + +#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) +#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) +/*! FCT_FAIL - Frequency Count Fail */ +#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) + +#define TRNG_MCTL_FCT_VAL_MASK (0x200U) +#define TRNG_MCTL_FCT_VAL_SHIFT (9U) +/*! FCT_VAL - Frequency Count Valid + * 0b0..Frequency Count is not valid + * 0b1..Frequency Count is valid + */ +#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) + +#define TRNG_MCTL_ENT_VAL_MASK (0x400U) +#define TRNG_MCTL_ENT_VAL_SHIFT (10U) +/*! ENT_VAL - Entropy Valid + * 0b0..Entropy is not valid + * 0b1..Entropy is valid + */ +#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) + +#define TRNG_MCTL_ERR_MASK (0x1000U) +#define TRNG_MCTL_ERR_SHIFT (12U) +/*! ERR - Error Status + * 0b0..No error + * 0b1..Error detected + */ +#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) + +#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) +#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) +/*! TSTOP_OK - TRNG is ok to stop + * 0b0..TRNG is generating entropy and is not ok to stop + * 0b1..TRNG is not generating entropy and is ok to stop + */ +#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) + +#define TRNG_MCTL_OSC2_FAIL_MASK (0x8000U) +#define TRNG_MCTL_OSC2_FAIL_SHIFT (15U) +/*! OSC2_FAIL - Oscillator 2 Failure + * 0b0..Oscillator 2 is running. + * 0b1..Oscillator 2 has failed (see OSC2_CTL[OSC_FAILSAFE_LMT]). + */ +#define TRNG_MCTL_OSC2_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC2_FAIL_SHIFT)) & TRNG_MCTL_OSC2_FAIL_MASK) + +#define TRNG_MCTL_PRGM_MASK (0x10000U) +#define TRNG_MCTL_PRGM_SHIFT (16U) +/*! PRGM - Program Mode + * 0b0..TRNG is in Run Mode + * 0b1..TRNG is in Program Mode + */ +#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) + +#define TRNG_MCTL_INTG_ERR_MASK (0x80000000U) +#define TRNG_MCTL_INTG_ERR_SHIFT (31U) +/*! INTG_ERR - Integrity Error + * 0b0..TRNG detected no internal bit error + * 0b1..TRNG detected internal bit error(s) + */ +#define TRNG_MCTL_INTG_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_INTG_ERR_SHIFT)) & TRNG_MCTL_INTG_ERR_MASK) +/*! @} */ + +/*! @name SCMISC - Statistical Check Miscellaneous Register */ +/*! @{ */ + +#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) +#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) +#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) + +#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) +#define TRNG_SCMISC_RTY_CT_SHIFT (16U) +#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +/*! @} */ + +/*! @name PKRRNG - Poker Range Register */ +/*! @{ */ + +#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) +#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) +#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) +/*! @} */ + +/*! @name PKRMAX - Poker Maximum Limit Register */ +/*! @{ */ + +#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) +#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) +/*! PKR_MAX - Poker Maximum Limit. */ +#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) +/*! @} */ + +/*! @name PKRSQ - Poker Square Calculation Result Register */ +/*! @{ */ + +#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) +#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) +/*! PKR_SQ - Poker Square Calculation Result. */ +#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) +/*! @} */ + +/*! @name SDCTL - Seed Control Register */ +/*! @{ */ + +#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) +#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) +#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) + +#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) +#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) +#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +/*! @} */ + +/*! @name SBLIM - Sparse Bit Limit Register */ +/*! @{ */ + +#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) +#define TRNG_SBLIM_SB_LIM_SHIFT (0U) +#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) +/*! @} */ + +/*! @name TOTSAM - Total Samples Register */ +/*! @{ */ + +#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) +#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) +#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) +/*! @} */ + +/*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/*! @{ */ + +#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) +#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) +#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +/*! @} */ + +/*! @name OSC2_FRQCNT - Oscillator-2 Frequency Count Register */ +/*! @{ */ + +#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK (0x3FFFFFU) +#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT (0U) +#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT)) & TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK) +/*! @} */ + +/*! @name FRQCNT - Frequency Count Register */ +/*! @{ */ + +#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) +#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) +#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +/*! @} */ + +/*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/*! @{ */ + +#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) +#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) +#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +/*! @} */ + +/*! @name SCMC - Statistical Check Monobit Count Register */ +/*! @{ */ + +#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) +#define TRNG_SCMC_MONO_CT_SHIFT (0U) +#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +/*! @} */ + +/*! @name SCML - Statistical Check Monobit Limit Register */ +/*! @{ */ + +#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) +#define TRNG_SCML_MONO_MAX_SHIFT (0U) +#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) + +#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) +#define TRNG_SCML_MONO_RNG_SHIFT (16U) +#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +/*! @} */ + +/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/*! @{ */ + +#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) +#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) +/*! R1_0_CT - Runs of Zero, Length 1 Count */ +#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) + +#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) +#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) +/*! R1_1_CT - Runs of One, Length 1 Count */ +#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +/*! @} */ + +/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/*! @{ */ + +#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) +#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) +/*! RUN1_MAX - Run Length 1 Maximum Limit */ +#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) + +#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) +#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) +/*! RUN1_RNG - Run Length 1 Range */ +#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +/*! @} */ + +/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/*! @{ */ + +#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) +#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) +#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) + +#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) +#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) +#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +/*! @} */ + +/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ +/*! @{ */ + +#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) +#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) +#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) + +#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) +#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) +#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) +/*! @} */ + +/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ +/*! @{ */ + +#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) +#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) +#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) + +#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) +#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) +#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) +/*! @} */ + +/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ +/*! @{ */ + +#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) +#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) +#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) + +#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) +#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) +#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) +/*! @} */ + +/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ +/*! @{ */ + +#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) +#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) +#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) + +#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) +#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) +#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) +/*! @} */ + +/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ +/*! @{ */ + +#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) +#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) +#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) + +#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) +#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) +#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) +/*! @} */ + +/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ +/*! @{ */ + +#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) +#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) +#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) + +#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) +#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) +/*! @} */ + +/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ +/*! @{ */ + +#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) +#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) +#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) + +#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) +#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) +#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) +/*! @} */ + +/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ +/*! @{ */ + +#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) +#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) +#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) + +#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) +#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) +/*! @} */ + +/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ +/*! @{ */ + +#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) +#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) +#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) + +#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) +#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) +#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) +/*! @} */ + +/*! @name STATUS - Status Register */ +/*! @{ */ + +#define TRNG_STATUS_TF1BR0_MASK (0x1U) +#define TRNG_STATUS_TF1BR0_SHIFT (0U) +/*! TF1BR0 + * 0b0..The 1-Bit Run, Sampling 0s Test has passed + * 0b1..The 1-Bit Run, Sampling 0s Test has failed + */ +#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) + +#define TRNG_STATUS_TF1BR1_MASK (0x2U) +#define TRNG_STATUS_TF1BR1_SHIFT (1U) +/*! TF1BR1 + * 0b0..The 1-Bit Run, Sampling 1s Test has passed + * 0b1..The 1-Bit Run, Sampling 1s Test has failed + */ +#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) + +#define TRNG_STATUS_TF2BR0_MASK (0x4U) +#define TRNG_STATUS_TF2BR0_SHIFT (2U) +/*! TF2BR0 + * 0b0..The 2-Bit Run, Sampling 0s Test has passed + * 0b1..The 2-Bit Run, Sampling 0s Test has failed + */ +#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) + +#define TRNG_STATUS_TF2BR1_MASK (0x8U) +#define TRNG_STATUS_TF2BR1_SHIFT (3U) +/*! TF2BR1 + * 0b0..The 2-Bit Run, Sampling 1s Test has passed + * 0b1..The 2-Bit Run, Sampling 1s Test has failed + */ +#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) + +#define TRNG_STATUS_TF3BR0_MASK (0x10U) +#define TRNG_STATUS_TF3BR0_SHIFT (4U) +/*! TF3BR0 + * 0b0..The 3-Bit Run, Sampling 0s Test has passed + * 0b1..The 3-Bit Run, Sampling 0s Test has failed + */ +#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) + +#define TRNG_STATUS_TF3BR1_MASK (0x20U) +#define TRNG_STATUS_TF3BR1_SHIFT (5U) +/*! TF3BR1 - Test Fail + * 0b0..The 3-Bit Run, Sampling 1s Test has passed + * 0b1..The 3-Bit Run, Sampling 1s Test has failed + */ +#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) + +#define TRNG_STATUS_TF4BR0_MASK (0x40U) +#define TRNG_STATUS_TF4BR0_SHIFT (6U) +/*! TF4BR0 + * 0b0..The 4-Bit Run, Sampling 0s Test has passed + * 0b1..The 4-Bit Run, Sampling 0s Test has failed + */ +#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) + +#define TRNG_STATUS_TF4BR1_MASK (0x80U) +#define TRNG_STATUS_TF4BR1_SHIFT (7U) +/*! TF4BR1 + * 0b0..The 4-Bit Run, Sampling 1s Test has passed + * 0b1..The 4-Bit Run, Sampling 1s Test has failed + */ +#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) + +#define TRNG_STATUS_TF5BR0_MASK (0x100U) +#define TRNG_STATUS_TF5BR0_SHIFT (8U) +/*! TF5BR0 + * 0b0..The 5-Bit Run, Sampling 0s Test has passed + * 0b1..The 5-Bit Run, Sampling 0s Test has failed + */ +#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) + +#define TRNG_STATUS_TF5BR1_MASK (0x200U) +#define TRNG_STATUS_TF5BR1_SHIFT (9U) +/*! TF5BR1 + * 0b0..The 5-Bit Run, Sampling 1s Test has passed + * 0b1..The 5-Bit Run, Sampling 1s Test has failed + */ +#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) + +#define TRNG_STATUS_TF6PBR0_MASK (0x400U) +#define TRNG_STATUS_TF6PBR0_SHIFT (10U) +/*! TF6PBR0 + * 0b0..The 6 Plus Bit Run, Sampling 0s Test has passed + * 0b1..the 6 Plus Bit Run, Sampling 0s Test has failed + */ +#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) + +#define TRNG_STATUS_TF6PBR1_MASK (0x800U) +#define TRNG_STATUS_TF6PBR1_SHIFT (11U) +/*! TF6PBR1 - Test Fail, 6 Plus Bit Run, Sampling 1s. + * 0b0..The 6 Plus Bit Run, Sampling 1s Test has passed + * 0b1..The 6 Plus Bit Run, Sampling 1s Test has failed + */ +#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) + +#define TRNG_STATUS_TFSB_MASK (0x1000U) +#define TRNG_STATUS_TFSB_SHIFT (12U) +/*! TFSB - Test Fail, Sparse Bit. + * 0b0..The Sparse Bit Test has passed + * 0b1..The Sparse Bit Test has failed + */ +#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) + +#define TRNG_STATUS_TFLR_MASK (0x2000U) +#define TRNG_STATUS_TFLR_SHIFT (13U) +/*! TFLR - Test Fail, Long Run. + * 0b0..The Long Run Test has passed + * 0b1..The Long Run Test has failed + */ +#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) + +#define TRNG_STATUS_TFP_MASK (0x4000U) +#define TRNG_STATUS_TFP_SHIFT (14U) +/*! TFP + * 0b0..The Poker Test has passed + * 0b1..The Poker Test has failed + */ +#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) + +#define TRNG_STATUS_TFMB_MASK (0x8000U) +#define TRNG_STATUS_TFMB_SHIFT (15U) +/*! TFMB + * 0b0..The Mono Bit Test has passed + * 0b1..The Mono Bit Test has failed + */ +#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) + +#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) +#define TRNG_STATUS_RETRY_CT_SHIFT (16U) +#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) +/*! @} */ + +/*! @name ENTA_ENT - Entropy Read Register */ +/*! @{ */ + +#define TRNG_ENTA_ENT_ENT_MASK (0xFFFFFFFFU) +#define TRNG_ENTA_ENT_ENT_SHIFT (0U) +#define TRNG_ENTA_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENTA_ENT_ENT_SHIFT)) & TRNG_ENTA_ENT_ENT_MASK) +/*! @} */ + +/* The count of TRNG_ENTA_ENT */ +#define TRNG_ENTA_ENT_COUNT (8U) + +/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ +/*! @{ */ + +#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) +#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) + +#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) +#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) +/*! @} */ + +/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ +/*! @{ */ + +#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) +#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) + +#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) +#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) +/*! @} */ + +/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ +/*! @{ */ + +#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) +#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) + +#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) +#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) +/*! @} */ + +/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ +/*! @{ */ + +#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) +#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) + +#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) +#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) +/*! @} */ + +/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ +/*! @{ */ + +#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) +/*! PKR_8_CT - Poker 8h Count */ +#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) + +#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) +/*! PKR_9_CT - Poker 9h Count */ +#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) +/*! @} */ + +/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ +/*! @{ */ + +#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) +/*! PKR_A_CT - Poker Ah Count */ +#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) + +#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) +/*! PKR_B_CT - Poker Bh Count */ +#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) +/*! @} */ + +/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ +/*! @{ */ + +#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) +/*! PKR_C_CT - Poker Ch Count */ +#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) + +#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) +/*! PKR_D_CT - Poker Dh Count */ +#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) +/*! @} */ + +/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ +/*! @{ */ + +#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) +#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) + +#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) +#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) +/*! @} */ + +/*! @name SEC_CFG - Security Configuration Register */ +/*! @{ */ + +#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) +#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) +/*! NO_PRGM + * 0b0..TRNG configuration registers can be modified. + * 0b1..TRNG configuration registers cannot be modified. + */ +#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) +/*! @} */ + +/*! @name INT_CTRL - Interrupt Control Register */ +/*! @{ */ + +#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) +#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Clears the INT_STATUS[HW_ERR] bit. Will automatically set after writing. + * 0b1..Enables the INT_STATUS[HW_ERR] bit to be set, thereby enabling interrupt generation for the HW_ERR condition. + */ +#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) + +#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) +#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Clears the INT_STATUS[ENT_VAL] bit. Will automatically set after writing. + * 0b1..Enables the INT_STATUS[ENT_VAL] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition. + */ +#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) + +#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Clears the INT_STATUS[FRQ_CT_FAIL] bit. Will automatically set after writing. + * 0b1..Enables the INT_STATUS[FRQ_CT_FAIL] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition. + */ +#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) + +#define TRNG_INT_CTRL_INTG_FLT_MASK (0x8U) +#define TRNG_INT_CTRL_INTG_FLT_SHIFT (3U) +/*! INTG_FLT + * 0b0..Clears the INT_STATUS[INTG_FLT] bit. Will automatically set after writing. + * 0b1..Enables the INT_STATUS[INTG_FLT] bit to be set, thereby enabling interrupt generation for the INTG_FLT condition. + */ +#define TRNG_INT_CTRL_INTG_FLT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_INTG_FLT_SHIFT)) & TRNG_INT_CTRL_INTG_FLT_MASK) +/*! @} */ + +/*! @name INT_MASK - Mask Register */ +/*! @{ */ + +#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) +#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..HW_ERR interrupt is disabled. + * 0b1..HW_ERR interrupt is enabled. + */ +#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) + +#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) +#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..ENT_VAL interrupt is disabled. + * 0b1..ENT_VAL interrupt is enabled. + */ +#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) + +#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..FRQ_CT_FAIL interrupt is disabled. + * 0b1..FRQ_CT_FAIL interrupt is enabled. + */ +#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) + +#define TRNG_INT_MASK_INTG_FLT_MASK (0x8U) +#define TRNG_INT_MASK_INTG_FLT_SHIFT (3U) +/*! INTG_FLT + * 0b0..INTG_FLT interrupt is disabled. + * 0b1..INTG_FLT interrupt is enabled. + */ +#define TRNG_INT_MASK_INTG_FLT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_INTG_FLT_SHIFT)) & TRNG_INT_MASK_INTG_FLT_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ + +#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) +#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..No error. + * 0b1..Error detected. + */ +#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) + +#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) +#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Busy generating entropy. Any value read from the Entropy registers is invalid. + * 0b1..Values read from the Entropy registers are valid. + */ +#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) + +#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..No hardware nor self test frequency errors. + * 0b1..The frequency counter has detected a failure. + */ +#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) + +#define TRNG_INT_STATUS_INTG_FLT_MASK (0x8U) +#define TRNG_INT_STATUS_INTG_FLT_SHIFT (3U) +/*! INTG_FLT + * 0b0..No internal fault has been detected. + * 0b1..TRNG has detected internal fault. + */ +#define TRNG_INT_STATUS_INTG_FLT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_INTG_FLT_SHIFT)) & TRNG_INT_STATUS_INTG_FLT_MASK) +/*! @} */ + +/*! @name CSER - Common Security Error Register */ +/*! @{ */ + +#define TRNG_CSER_RED_SIGS_MASK (0x1U) +#define TRNG_CSER_RED_SIGS_SHIFT (0U) +/*! RED_SIGS - Redundant Signals error/fault Detected + * 0b0..No redundant signal error/fault + * 0b1..Redundant signal error/fault detected. + */ +#define TRNG_CSER_RED_SIGS(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSER_RED_SIGS_SHIFT)) & TRNG_CSER_RED_SIGS_MASK) + +#define TRNG_CSER_RED_FSM_MASK (0x2U) +#define TRNG_CSER_RED_FSM_SHIFT (1U) +/*! RED_FSM - Redundant FSM error/fault detected + * 0b0..No redundant FSM error/fault + * 0b1..Redundant FSM error/fault detected. + */ +#define TRNG_CSER_RED_FSM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSER_RED_FSM_SHIFT)) & TRNG_CSER_RED_FSM_MASK) + +#define TRNG_CSER_LOCAL_EDC_MASK (0x4U) +#define TRNG_CSER_LOCAL_EDC_SHIFT (2U) +/*! LOCAL_EDC - Local-EDC error/fault detected + * 0b0..No Local-EDC error/fault detected. + * 0b1..Local-EDC error/fault detected. + */ +#define TRNG_CSER_LOCAL_EDC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSER_LOCAL_EDC_SHIFT)) & TRNG_CSER_LOCAL_EDC_MASK) + +#define TRNG_CSER_BUS_EDC_MASK (0x8U) +#define TRNG_CSER_BUS_EDC_SHIFT (3U) +/*! BUS_EDC - Bus-EDC error/fault detected + * 0b0..No Bus-EDC error/fault detected. + * 0b1..Bus-EDC error/fault detected. + */ +#define TRNG_CSER_BUS_EDC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSER_BUS_EDC_SHIFT)) & TRNG_CSER_BUS_EDC_MASK) +/*! @} */ + +/*! @name CSCLR - Common Security Clear Register */ +/*! @{ */ + +#define TRNG_CSCLR_RED_SIGS_CLR_MASK (0x1U) +#define TRNG_CSCLR_RED_SIGS_CLR_SHIFT (0U) +/*! RED_SIGS_CLR - Redundant Signals error/fault Detected + * 0b0..No effect, ignored + * 0b1..Clears the CSER[RED_SIGS] bit. + */ +#define TRNG_CSCLR_RED_SIGS_CLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSCLR_RED_SIGS_CLR_SHIFT)) & TRNG_CSCLR_RED_SIGS_CLR_MASK) + +#define TRNG_CSCLR_RED_FSM_CLR_MASK (0x2U) +#define TRNG_CSCLR_RED_FSM_CLR_SHIFT (1U) +/*! RED_FSM_CLR + * 0b0..No effect, ignored + * 0b1..Clears the CSER[RED_FSM] bit. + */ +#define TRNG_CSCLR_RED_FSM_CLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSCLR_RED_FSM_CLR_SHIFT)) & TRNG_CSCLR_RED_FSM_CLR_MASK) + +#define TRNG_CSCLR_LOCAL_EDC_CLR_MASK (0x4U) +#define TRNG_CSCLR_LOCAL_EDC_CLR_SHIFT (2U) +/*! LOCAL_EDC_CLR + * 0b0..No effect, ignored + * 0b1..Clears the CSER[LOCAL_EDC] bit. + */ +#define TRNG_CSCLR_LOCAL_EDC_CLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSCLR_LOCAL_EDC_CLR_SHIFT)) & TRNG_CSCLR_LOCAL_EDC_CLR_MASK) + +#define TRNG_CSCLR_BUS_EDC_CLR_MASK (0x8U) +#define TRNG_CSCLR_BUS_EDC_CLR_SHIFT (3U) +/*! BUS_EDC_CLR + * 0b0..No effect, ignored + * 0b1..Clears the CSER[BUS_EDC] bit. + */ +#define TRNG_CSCLR_BUS_EDC_CLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSCLR_BUS_EDC_CLR_SHIFT)) & TRNG_CSCLR_BUS_EDC_CLR_MASK) +/*! @} */ + +/*! @name OSC2_CTL - TRNG Oscillator 2 Control Register */ +/*! @{ */ + +#define TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK (0x3U) +#define TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT (0U) +/*! TRNG_ENT_CTL - TRNG entropy generation control. + * 0b00..Single oscillator mode, using OSC1 (default) + * 0b01..Dual oscillator mode + * 0b10..Single oscillator mode, using OSC2 + * 0b11..Unused, (bit field cannot be written to this value) + */ +#define TRNG_OSC2_CTL_TRNG_ENT_CTL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT)) & TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK) + +#define TRNG_OSC2_CTL_OSC2_DIV_MASK (0xCU) +#define TRNG_OSC2_CTL_OSC2_DIV_SHIFT (2U) +/*! OSC2_DIV - Oscillator 2 Divide. + * 0b00..Use ring oscillator 2 with no divide + * 0b01..Use ring oscillator 2 divided-by-2 + * 0b10..Use ring oscillator 2 divided-by-4 + * 0b11..Use ring oscillator 2 divided-by-8 + */ +#define TRNG_OSC2_CTL_OSC2_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_DIV_SHIFT)) & TRNG_OSC2_CTL_OSC2_DIV_MASK) + +#define TRNG_OSC2_CTL_OSC2_OUT_EN_MASK (0x10U) +#define TRNG_OSC2_CTL_OSC2_OUT_EN_SHIFT (4U) +/*! OSC2_OUT_EN - Oscillator 2 Clock Output Enable + * 0b0..Ring oscillator 2 output is gated to an output pad. + * 0b1..Allows external viewing of divided-by-2 ring oscillator 2 if MCTL[PRGM] = 1 mode is also selected, else + * ring oscillator 2 output is gated to an output pad. + */ +#define TRNG_OSC2_CTL_OSC2_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_OUT_EN_SHIFT)) & TRNG_OSC2_CTL_OSC2_OUT_EN_MASK) + +#define TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK (0x200U) +#define TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT (9U) +/*! OSC2_FCT_VAL - TRNG Oscillator 2 Frequency Count Valid + * 0b0..Frequency count is invalid. + * 0b1..If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT. + */ +#define TRNG_OSC2_CTL_OSC2_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT)) & TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK) + +#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK (0x3000U) +#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT (12U) +/*! OSC_FAILSAFE_LMT - Oscillator fail safe limit. + * 0b00..The limit N is 4096 (2^12) system clocks. + * 0b01..The limit N is 65536 (2^16) system clocks. (default) + * 0b10..N is 2^20 system clocks. + * 0b11..N is 2^22 system clocks (full range of the counter being used). + */ +#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK) + +#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK (0x4000U) +#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT (14U) +/*! OSC_FAILSAFE_TEST - Oscillator fail safe test. + * 0b0..No impact. + * 0b1..Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b). + */ +#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK) +/*! @} */ + +/*! @name VID1 - Version ID Register (MS) */ +/*! @{ */ + +#define TRNG_VID1_MIN_REV_MASK (0xFFU) +#define TRNG_VID1_MIN_REV_SHIFT (0U) +/*! MIN_REV + * 0b00001100..Minor revision number for TRNG. + */ +#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) + +#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) +#define TRNG_VID1_MAJ_REV_SHIFT (8U) +/*! MAJ_REV + * 0b00010100..Major revision number for TRNG. + */ +#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) + +#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) +#define TRNG_VID1_IP_ID_SHIFT (16U) +/*! IP_ID + * 0b0000000000110000..ID for TRNG. + */ +#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) +/*! @} */ + +/*! @name VID2 - Version ID Register (LS) */ +/*! @{ */ + +#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) +#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) +/*! CONFIG_OPT + * 0b00000000..TRNG_CONFIG_OPT for TRNG. + */ +#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) + +#define TRNG_VID2_ECO_REV_MASK (0xFF00U) +#define TRNG_VID2_ECO_REV_SHIFT (8U) +/*! ECO_REV + * 0b00000000..TRNG_ECO_REV for TRNG. + */ +#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) + +#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) +#define TRNG_VID2_INTG_OPT_SHIFT (16U) +/*! INTG_OPT + * 0b00001010..INTG_OPT for TRNG. + */ +#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) + +#define TRNG_VID2_ERA_MASK (0xFF000000U) +#define TRNG_VID2_ERA_SHIFT (24U) +/*! ERA + * 0b00001100..ERA of the TRNG. + */ +#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TRNG_Register_Masks */ + + +/*! + * @} + */ /* end of group TRNG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_TRNG_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_UDF.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_UDF.h new file mode 100644 index 000000000..64ced8012 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_UDF.h @@ -0,0 +1,263 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for UDF +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_UDF.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for UDF + * + * CMSIS Peripheral Access Layer for UDF + */ + +#if !defined(PERI_UDF_H_) +#define PERI_UDF_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- UDF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UDF_Peripheral_Access_Layer UDF Peripheral Access Layer + * @{ + */ + +/** UDF - Register Layout Typedef */ +typedef struct { + __IO uint32_t UDF_CTRL; /**< Control register, offset: 0x0 */ + __I uint32_t UDF_STATUS; /**< Status register, offset: 0x4 */ + __O uint32_t UDF_WR_DATA; /**< Data In Register, offset: 0x8 */ + __I uint32_t UDF_RD_DATA; /**< Data Out Register, offset: 0xC */ +} UDF_Type; + +/* ---------------------------------------------------------------------------- + -- UDF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UDF_Register_Masks UDF Register Masks + * @{ + */ + +/*! @name UDF_CTRL - Control register */ +/*! @{ */ + +#define UDF_UDF_CTRL_salt_MASK (0xFFFFU) +#define UDF_UDF_CTRL_salt_SHIFT (0U) +/*! salt - Bits are internally XORed with i_custom */ +#define UDF_UDF_CTRL_salt(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_CTRL_salt_SHIFT)) & UDF_UDF_CTRL_salt_MASK) + +#define UDF_UDF_CTRL_lock_MASK (0x70000U) +#define UDF_UDF_CTRL_lock_SHIFT (16U) +/*! lock - Lock access to UDF */ +#define UDF_UDF_CTRL_lock(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_CTRL_lock_SHIFT)) & UDF_UDF_CTRL_lock_MASK) + +#define UDF_UDF_CTRL_reserved21_MASK (0x380000U) +#define UDF_UDF_CTRL_reserved21_SHIFT (19U) +/*! reserved21 - RFU */ +#define UDF_UDF_CTRL_reserved21(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_CTRL_reserved21_SHIFT)) & UDF_UDF_CTRL_reserved21_MASK) + +#define UDF_UDF_CTRL_udf_en_MASK (0x1C00000U) +#define UDF_UDF_CTRL_udf_en_SHIFT (22U) +/*! udf_en - Enable the UDF block */ +#define UDF_UDF_CTRL_udf_en(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_CTRL_udf_en_SHIFT)) & UDF_UDF_CTRL_udf_en_MASK) + +#define UDF_UDF_CTRL_reserved25_MASK (0x2000000U) +#define UDF_UDF_CTRL_reserved25_SHIFT (25U) +/*! reserved25 - RFU */ +#define UDF_UDF_CTRL_reserved25(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_CTRL_reserved25_SHIFT)) & UDF_UDF_CTRL_reserved25_MASK) + +#define UDF_UDF_CTRL_reserved27_MASK (0xC000000U) +#define UDF_UDF_CTRL_reserved27_SHIFT (26U) +/*! reserved27 - RFU */ +#define UDF_UDF_CTRL_reserved27(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_CTRL_reserved27_SHIFT)) & UDF_UDF_CTRL_reserved27_MASK) + +#define UDF_UDF_CTRL_flush_MASK (0x70000000U) +#define UDF_UDF_CTRL_flush_SHIFT (28U) +/*! flush - Flush UDF and return to reset state */ +#define UDF_UDF_CTRL_flush(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_CTRL_flush_SHIFT)) & UDF_UDF_CTRL_flush_MASK) + +#define UDF_UDF_CTRL_reserved31_MASK (0x80000000U) +#define UDF_UDF_CTRL_reserved31_SHIFT (31U) +/*! reserved31 - reserved */ +#define UDF_UDF_CTRL_reserved31(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_CTRL_reserved31_SHIFT)) & UDF_UDF_CTRL_reserved31_MASK) +/*! @} */ + +/*! @name UDF_STATUS - Status register */ +/*! @{ */ + +#define UDF_UDF_STATUS_o_status_MASK (0x1FU) +#define UDF_UDF_STATUS_o_status_SHIFT (0U) +/*! o_status - Status bits + * 0b00001..5'b00001 = Reset + * 0b00010..5'b00010 = Init + * 0b00100..5'b00100 = Warmup + * 0b01000..5'b01000 = Ready + * 0b10000..5'b10000 = Error + */ +#define UDF_UDF_STATUS_o_status(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_STATUS_o_status_SHIFT)) & UDF_UDF_STATUS_o_status_MASK) + +#define UDF_UDF_STATUS_rsv_MASK (0x7FFFFFE0U) +#define UDF_UDF_STATUS_rsv_SHIFT (5U) +/*! rsv - RFU */ +#define UDF_UDF_STATUS_rsv(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_STATUS_rsv_SHIFT)) & UDF_UDF_STATUS_rsv_MASK) + +#define UDF_UDF_STATUS_o_wait_MASK (0x80000000U) +#define UDF_UDF_STATUS_o_wait_SHIFT (31U) +/*! o_wait - Indicates UDF is processing data */ +#define UDF_UDF_STATUS_o_wait(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_STATUS_o_wait_SHIFT)) & UDF_UDF_STATUS_o_wait_MASK) +/*! @} */ + +/*! @name UDF_WR_DATA - Data In Register */ +/*! @{ */ + +#define UDF_UDF_WR_DATA_i_dat_MASK (0xFFFFFFFFU) +#define UDF_UDF_WR_DATA_i_dat_SHIFT (0U) +#define UDF_UDF_WR_DATA_i_dat(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_WR_DATA_i_dat_SHIFT)) & UDF_UDF_WR_DATA_i_dat_MASK) +/*! @} */ + +/*! @name UDF_RD_DATA - Data Out Register */ +/*! @{ */ + +#define UDF_UDF_RD_DATA_o_dat_MASK (0xFFFFFFFFU) +#define UDF_UDF_RD_DATA_o_dat_SHIFT (0U) +#define UDF_UDF_RD_DATA_o_dat(x) (((uint32_t)(((uint32_t)(x)) << UDF_UDF_RD_DATA_o_dat_SHIFT)) & UDF_UDF_RD_DATA_o_dat_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group UDF_Register_Masks */ + + +/*! + * @} + */ /* end of group UDF_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_UDF_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_USB.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_USB.h new file mode 100644 index 000000000..6db76755a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_USB.h @@ -0,0 +1,1490 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for USB +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_USB.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for USB + * + * CMSIS Peripheral Access Layer for USB + */ + +#if !defined(PERI_USB_H_) +#define PERI_USB_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Size of Registers Arrays */ +#define USB_ENDPOINT_COUNT 16u + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision, offset: 0x8 */ + uint8_t RESERVED_2[3]; + __I uint8_t ADDINFO; /**< Peripheral Additional Information, offset: 0xC */ + uint8_t RESERVED_3[3]; + __IO uint8_t OTGISTAT; /**< OTG Interrupt Status, offset: 0x10 */ + uint8_t RESERVED_4[3]; + __IO uint8_t OTGICR; /**< OTG Interrupt Control, offset: 0x14 */ + uint8_t RESERVED_5[3]; + __I uint8_t OTGSTAT; /**< OTG Status, offset: 0x18 */ + uint8_t RESERVED_6[3]; + __IO uint8_t OTGCTL; /**< OTG Control, offset: 0x1C */ + uint8_t RESERVED_7[99]; + __IO uint8_t ISTAT; /**< Interrupt Status, offset: 0x80 */ + uint8_t RESERVED_8[3]; + __IO uint8_t INTEN; /**< Interrupt Enable, offset: 0x84 */ + uint8_t RESERVED_9[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status, offset: 0x88 */ + uint8_t RESERVED_10[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable, offset: 0x8C */ + uint8_t RESERVED_11[3]; + __I uint8_t STAT; /**< Status, offset: 0x90 */ + uint8_t RESERVED_12[3]; + __IO uint8_t CTL; /**< Control, offset: 0x94 */ + uint8_t RESERVED_13[3]; + __IO uint8_t ADDR; /**< Address, offset: 0x98 */ + uint8_t RESERVED_14[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page 1, offset: 0x9C */ + uint8_t RESERVED_15[3]; + __I uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ + uint8_t RESERVED_16[3]; + __I uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ + uint8_t RESERVED_17[3]; + __IO uint8_t TOKEN; /**< Token, offset: 0xA8 */ + uint8_t RESERVED_18[3]; + __IO uint8_t SOFTHLD; /**< SOF Threshold, offset: 0xAC */ + uint8_t RESERVED_19[3]; + __IO uint8_t BDTPAGE2; /**< BDT Page 2, offset: 0xB0 */ + uint8_t RESERVED_20[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page 3, offset: 0xB4 */ + uint8_t RESERVED_21[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[USB_ENDPOINT_COUNT]; + __IO uint8_t USBCTRL; /**< USB Control, offset: 0x100 */ + uint8_t RESERVED_22[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe, offset: 0x104 */ + uint8_t RESERVED_23[3]; + __IO uint8_t CONTROL; /**< USB OTG Control, offset: 0x108 */ + uint8_t RESERVED_24[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control 0, offset: 0x10C */ + uint8_t RESERVED_25[7]; + __IO uint8_t USBFRMADJUST; /**< Frame Adjust, offset: 0x114 */ + uint8_t RESERVED_26[23]; + __IO uint8_t MISCCTRL; /**< Miscellaneous Control, offset: 0x12C */ + uint8_t RESERVED_27[3]; + __IO uint8_t STALL_IL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction, offset: 0x130 */ + uint8_t RESERVED_28[3]; + __IO uint8_t STALL_IH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction, offset: 0x134 */ + uint8_t RESERVED_29[3]; + __IO uint8_t STALL_OL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction, offset: 0x138 */ + uint8_t RESERVED_30[3]; + __IO uint8_t STALL_OH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction, offset: 0x13C */ + uint8_t RESERVED_31[3]; + __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock Recovery Control, offset: 0x140 */ + uint8_t RESERVED_32[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; /**< FIRC Oscillator Enable, offset: 0x144 */ + uint8_t RESERVED_33[15]; + __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock Recovery Combined Interrupt Enable, offset: 0x154 */ + uint8_t RESERVED_34[7]; + __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock Recovery Separated Interrupt Status, offset: 0x15C */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name PERID - Peripheral ID */ +/*! @{ */ + +#define USB_PERID_ID_MASK (0x3FU) +#define USB_PERID_ID_SHIFT (0U) +/*! ID - Peripheral Identification */ +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) +/*! @} */ + +/*! @name IDCOMP - Peripheral ID Complement */ +/*! @{ */ + +#define USB_IDCOMP_NID_MASK (0x3FU) +#define USB_IDCOMP_NID_SHIFT (0U) +/*! NID - Negative Peripheral ID */ +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) +/*! @} */ + +/*! @name REV - Peripheral Revision */ +/*! @{ */ + +#define USB_REV_REV_MASK (0xFFU) +#define USB_REV_REV_SHIFT (0U) +/*! REV - Revision */ +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) +/*! @} */ + +/*! @name ADDINFO - Peripheral Additional Information */ +/*! @{ */ + +#define USB_ADDINFO_IEHOST_MASK (0x1U) +#define USB_ADDINFO_IEHOST_SHIFT (0U) +/*! IEHOST - Host Mode Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) +/*! @} */ + +/*! @name OTGISTAT - OTG Interrupt Status */ +/*! @{ */ + +#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) +#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) +/*! LINE_STATE_CHG - Line State Change Interrupt Flag + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt occurred + */ +#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) + +#define USB_OTGISTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGISTAT_ONEMSEC_SHIFT (6U) +/*! ONEMSEC - One Millisecond Timer Timeout Flag + * 0b0..No effect + * 0b0..Not timed out + * 0b1..Clear the flag + * 0b1..Timed out + */ +#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) +/*! @} */ + +/*! @name OTGICR - OTG Interrupt Control */ +/*! @{ */ + +#define USB_OTGICR_LINESTATEEN_MASK (0x20U) +#define USB_OTGICR_LINESTATEEN_SHIFT (5U) +/*! LINESTATEEN - Line State Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) + +#define USB_OTGICR_ONEMSECEN_MASK (0x40U) +#define USB_OTGICR_ONEMSECEN_SHIFT (6U) +/*! ONEMSECEN - 1-Millisecond Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) +/*! @} */ + +/*! @name OTGSTAT - OTG Status */ +/*! @{ */ + +#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) +#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) +/*! LINESTATESTABLE - Line State Stable + * 0b0..Unstable + * 0b1..Stable + */ +#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) + +#define USB_OTGSTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGSTAT_ONEMSEC_SHIFT (6U) +/*! ONEMSEC - Reserved for 1 ms count */ +#define USB_OTGSTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSEC_SHIFT)) & USB_OTGSTAT_ONEMSEC_MASK) +/*! @} */ + +/*! @name OTGCTL - OTG Control */ +/*! @{ */ + +#define USB_OTGCTL_OTGEN_MASK (0x4U) +#define USB_OTGCTL_OTGEN_SHIFT (2U) +/*! OTGEN - On-The-Go Pullup and Pulldown Resistor Enable + * 0b0..If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup + * resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged. + * 0b1..Uses the pullup and pulldown controls in this register. + */ +#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) + +#define USB_OTGCTL_DMLOW_MASK (0x10U) +#define USB_OTGCTL_DMLOW_SHIFT (4U) +/*! DMLOW - D- Data Line Pulldown Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) + +#define USB_OTGCTL_DPLOW_MASK (0x20U) +#define USB_OTGCTL_DPLOW_SHIFT (5U) +/*! DPLOW - D+ Data Line pulldown Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) + +#define USB_OTGCTL_DPHIGH_MASK (0x80U) +#define USB_OTGCTL_DPHIGH_SHIFT (7U) +/*! DPHIGH - D+ Data Line Pullup Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) +/*! @} */ + +/*! @name ISTAT - Interrupt Status */ +/*! @{ */ + +#define USB_ISTAT_USBRST_MASK (0x1U) +#define USB_ISTAT_USBRST_SHIFT (0U) +/*! USBRST - USB Reset Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) + +#define USB_ISTAT_ERROR_MASK (0x2U) +#define USB_ISTAT_ERROR_SHIFT (1U) +/*! ERROR - Error Flag + * 0b0..Error did not occur + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Error occurred + */ +#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) + +#define USB_ISTAT_SOFTOK_MASK (0x4U) +#define USB_ISTAT_SOFTOK_SHIFT (2U) +/*! SOFTOK - Start Of Frame (SOF) Token Flag + * 0b0..Did not receive + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Received + */ +#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) + +#define USB_ISTAT_TOKDNE_MASK (0x8U) +#define USB_ISTAT_TOKDNE_SHIFT (3U) +/*! TOKDNE - Current Token Processing Flag + * 0b0..No effect + * 0b0..Not processed + * 0b1..Clear the flag + * 0b1..Processed + */ +#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) + +#define USB_ISTAT_SLEEP_MASK (0x10U) +#define USB_ISTAT_SLEEP_SHIFT (4U) +/*! SLEEP - Sleep Flag + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt occurred + */ +#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) + +#define USB_ISTAT_RESUME_MASK (0x20U) +#define USB_ISTAT_RESUME_SHIFT (5U) +/*! RESUME - Resume Flag + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt occurred + */ +#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) + +#define USB_ISTAT_ATTACH_MASK (0x40U) +#define USB_ISTAT_ATTACH_SHIFT (6U) +/*! ATTACH - Attach Interrupt Flag + * 0b0..No effect + * 0b0..Not detected + * 0b1..Clear the flag + * 0b1..Detected + */ +#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) + +#define USB_ISTAT_STALL_MASK (0x80U) +#define USB_ISTAT_STALL_SHIFT (7U) +/*! STALL - Stall Interrupt Flag + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt occurred + */ +#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable */ +/*! @{ */ + +#define USB_INTEN_USBRSTEN_MASK (0x1U) +#define USB_INTEN_USBRSTEN_SHIFT (0U) +/*! USBRSTEN - USBRST Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) + +#define USB_INTEN_ERROREN_MASK (0x2U) +#define USB_INTEN_ERROREN_SHIFT (1U) +/*! ERROREN - ERROR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) + +#define USB_INTEN_SOFTOKEN_MASK (0x4U) +#define USB_INTEN_SOFTOKEN_SHIFT (2U) +/*! SOFTOKEN - SOFTOK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) + +#define USB_INTEN_TOKDNEEN_MASK (0x8U) +#define USB_INTEN_TOKDNEEN_SHIFT (3U) +/*! TOKDNEEN - TOKDNE Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) + +#define USB_INTEN_SLEEPEN_MASK (0x10U) +#define USB_INTEN_SLEEPEN_SHIFT (4U) +/*! SLEEPEN - SLEEP Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) + +#define USB_INTEN_RESUMEEN_MASK (0x20U) +#define USB_INTEN_RESUMEEN_SHIFT (5U) +/*! RESUMEEN - RESUME Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) + +#define USB_INTEN_ATTACHEN_MASK (0x40U) +#define USB_INTEN_ATTACHEN_SHIFT (6U) +/*! ATTACHEN - ATTACH Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) + +#define USB_INTEN_STALLEN_MASK (0x80U) +#define USB_INTEN_STALLEN_SHIFT (7U) +/*! STALLEN - STALL Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) +/*! @} */ + +/*! @name ERRSTAT - Error Interrupt Status */ +/*! @{ */ + +#define USB_ERRSTAT_PIDERR_MASK (0x1U) +#define USB_ERRSTAT_PIDERR_SHIFT (0U) +/*! PIDERR - PID Error Flag + * 0b0..Did not fail + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Failed + */ +#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) + +#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) +#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) +/*! CRC5EOF - CRC5 Error or End of Frame Error Flag + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt occurred + */ +#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) + +#define USB_ERRSTAT_CRC16_MASK (0x4U) +#define USB_ERRSTAT_CRC16_SHIFT (2U) +/*! CRC16 - CRC16 Error Flag + * 0b0..No effect + * 0b0..Not rejected + * 0b1..Clear the flag + * 0b1..Rejected + */ +#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) + +#define USB_ERRSTAT_DFN8_MASK (0x8U) +#define USB_ERRSTAT_DFN8_SHIFT (3U) +/*! DFN8 - Data Field Not 8 Bits Flag + * 0b0..Integer number of bytes + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Not an integer number of bytes + */ +#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) + +#define USB_ERRSTAT_BTOERR_MASK (0x10U) +#define USB_ERRSTAT_BTOERR_SHIFT (4U) +/*! BTOERR - Bus Turnaround Timeout Error Flag + * 0b0..No effect + * 0b0..Not timed out + * 0b1..Clear the flag + * 0b1..Timed out + */ +#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) + +#define USB_ERRSTAT_DMAERR_MASK (0x20U) +#define USB_ERRSTAT_DMAERR_SHIFT (5U) +/*! DMAERR - DMA Access Error Flag + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt occurred + */ +#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) + +#define USB_ERRSTAT_OWNERR_MASK (0x40U) +#define USB_ERRSTAT_OWNERR_SHIFT (6U) +/*! OWNERR - BD Unavailable Error Flag + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Interrupt occurred + */ +#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) + +#define USB_ERRSTAT_BTSERR_MASK (0x80U) +#define USB_ERRSTAT_BTSERR_SHIFT (7U) +/*! BTSERR - Bit Stuff Error Flag + * 0b0..No effect + * 0b0..Packet not rejected due to the error + * 0b1..Clear the flag + * 0b1..Packet rejected due to the error + */ +#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) +/*! @} */ + +/*! @name ERREN - Error Interrupt Enable */ +/*! @{ */ + +#define USB_ERREN_PIDERREN_MASK (0x1U) +#define USB_ERREN_PIDERREN_SHIFT (0U) +/*! PIDERREN - PIDERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) + +#define USB_ERREN_CRC5EOFEN_MASK (0x2U) +#define USB_ERREN_CRC5EOFEN_SHIFT (1U) +/*! CRC5EOFEN - CRC5/EOF Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) + +#define USB_ERREN_CRC16EN_MASK (0x4U) +#define USB_ERREN_CRC16EN_SHIFT (2U) +/*! CRC16EN - CRC16 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) + +#define USB_ERREN_DFN8EN_MASK (0x8U) +#define USB_ERREN_DFN8EN_SHIFT (3U) +/*! DFN8EN - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) + +#define USB_ERREN_BTOERREN_MASK (0x10U) +#define USB_ERREN_BTOERREN_SHIFT (4U) +/*! BTOERREN - BTOERR (Bus Timeout Error) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) + +#define USB_ERREN_DMAERREN_MASK (0x20U) +#define USB_ERREN_DMAERREN_SHIFT (5U) +/*! DMAERREN - DMAERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) + +#define USB_ERREN_OWNERREN_MASK (0x40U) +#define USB_ERREN_OWNERREN_SHIFT (6U) +/*! OWNERREN - OWNERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) + +#define USB_ERREN_BTSERREN_MASK (0x80U) +#define USB_ERREN_BTSERREN_SHIFT (7U) +/*! BTSERREN - BTSERR (Bit Stuff Error) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define USB_STAT_ODD_MASK (0x4U) +#define USB_STAT_ODD_SHIFT (2U) +/*! ODD - Odd Bank + * 0b0..Not in the odd bank + * 0b1..In the odd bank + */ +#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) + +#define USB_STAT_TX_MASK (0x8U) +#define USB_STAT_TX_SHIFT (3U) +/*! TX - Transmit Indicator + * 0b0..Receive + * 0b1..Transmit + */ +#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) + +#define USB_STAT_ENDP_MASK (0xF0U) +#define USB_STAT_ENDP_SHIFT (4U) +/*! ENDP - Endpoint address */ +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) +/*! @} */ + +/*! @name CTL - Control */ +/*! @{ */ + +#define USB_CTL_USBENSOFEN_MASK (0x1U) +#define USB_CTL_USBENSOFEN_SHIFT (0U) +/*! USBENSOFEN - USB Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) + +#define USB_CTL_ODDRST_MASK (0x2U) +#define USB_CTL_ODDRST_SHIFT (1U) +/*! ODDRST - Odd Reset */ +#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) + +#define USB_CTL_RESUME_MASK (0x4U) +#define USB_CTL_RESUME_SHIFT (2U) +/*! RESUME - Resume */ +#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) + +#define USB_CTL_HOSTMODEEN_MASK (0x8U) +#define USB_CTL_HOSTMODEEN_SHIFT (3U) +/*! HOSTMODEEN - Host Mode Enable + * 0b0..USBFS operates in Device mode. + * 0b1..USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor. + */ +#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) + +#define USB_CTL_RESET_MASK (0x10U) +#define USB_CTL_RESET_SHIFT (4U) +/*! RESET - Reset Signaling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) + +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) +/*! TXSUSPENDTOKENBUSY - TXD Suspend And Token Busy */ +#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) + +#define USB_CTL_SE0_MASK (0x40U) +#define USB_CTL_SE0_SHIFT (6U) +/*! SE0 - Live USB Single-Ended Zero signal */ +#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) + +#define USB_CTL_JSTATE_MASK (0x80U) +#define USB_CTL_JSTATE_SHIFT (7U) +/*! JSTATE - Live USB Differential Receiver JSTATE Signal */ +#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) +/*! @} */ + +/*! @name ADDR - Address */ +/*! @{ */ + +#define USB_ADDR_ADDR_MASK (0x7FU) +#define USB_ADDR_ADDR_SHIFT (0U) +/*! ADDR - USB Address */ +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) + +#define USB_ADDR_LSEN_MASK (0x80U) +#define USB_ADDR_LSEN_SHIFT (7U) +/*! LSEN - Low Speed Enable */ +#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) +/*! @} */ + +/*! @name BDTPAGE1 - BDT Page 1 */ +/*! @{ */ + +#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) +#define USB_BDTPAGE1_BDTBA_SHIFT (1U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) +/*! @} */ + +/*! @name FRMNUML - Frame Number Register Low */ +/*! @{ */ + +#define USB_FRMNUML_FRM_MASK (0xFFU) +#define USB_FRMNUML_FRM_SHIFT (0U) +/*! FRM - Frame Number, Bits 0-7 */ +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) +/*! @} */ + +/*! @name FRMNUMH - Frame Number Register High */ +/*! @{ */ + +#define USB_FRMNUMH_FRM_MASK (0x7U) +#define USB_FRMNUMH_FRM_SHIFT (0U) +/*! FRM - Frame Number, Bits 8-10 */ +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) +/*! @} */ + +/*! @name TOKEN - Token */ +/*! @{ */ + +#define USB_TOKEN_TOKENENDPT_MASK (0xFU) +#define USB_TOKEN_TOKENENDPT_SHIFT (0U) +/*! TOKENENDPT - Token Endpoint Address */ +#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) + +#define USB_TOKEN_TOKENPID_MASK (0xF0U) +#define USB_TOKEN_TOKENPID_SHIFT (4U) +/*! TOKENPID - Token Type + * 0b0001..OUT token. USBFS performs an OUT (TX) transaction. + * 0b1001..IN token. USBFS performs an IN (RX) transaction. + * 0b1101..SETUP token. USBFS performs a SETUP (TX) transaction + */ +#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) +/*! @} */ + +/*! @name SOFTHLD - SOF Threshold */ +/*! @{ */ + +#define USB_SOFTHLD_CNT_MASK (0xFFU) +#define USB_SOFTHLD_CNT_SHIFT (0U) +/*! CNT - SOF Count Threshold */ +#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) +/*! @} */ + +/*! @name BDTPAGE2 - BDT Page 2 */ +/*! @{ */ + +#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE2_BDTBA_SHIFT (0U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) +/*! @} */ + +/*! @name BDTPAGE3 - BDT Page 3 */ +/*! @{ */ + +#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE3_BDTBA_SHIFT (0U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) +/*! @} */ + +/*! @name ENDPT - Endpoint Control */ +/*! @{ */ + +#define USB_ENDPT_EPHSHK_MASK (0x1U) +#define USB_ENDPT_EPHSHK_SHIFT (0U) +/*! EPHSHK - Endpoint Handshaking Enable */ +#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) + +#define USB_ENDPT_EPSTALL_MASK (0x2U) +#define USB_ENDPT_EPSTALL_SHIFT (1U) +/*! EPSTALL - Endpoint Stalled */ +#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) + +#define USB_ENDPT_EPTXEN_MASK (0x4U) +#define USB_ENDPT_EPTXEN_SHIFT (2U) +/*! EPTXEN - Endpoint for TX transfers enable */ +#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) + +#define USB_ENDPT_EPRXEN_MASK (0x8U) +#define USB_ENDPT_EPRXEN_SHIFT (3U) +/*! EPRXEN - Endpoint for RX transfers enable */ +#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) + +#define USB_ENDPT_EPCTLDIS_MASK (0x10U) +#define USB_ENDPT_EPCTLDIS_SHIFT (4U) +/*! EPCTLDIS - Control Transfer Disable + * 0b0..Enable + * 0b1..Disable + */ +#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) + +#define USB_ENDPT_RETRYDIS_MASK (0x40U) +#define USB_ENDPT_RETRYDIS_SHIFT (6U) +/*! RETRYDIS - Retry Disable + * 0b0..Retried NAK'ed transactions in hardware. + * 0b1..Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK + * PID, and the TOKEN_DNE interrupt becomes 1. + */ +#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) + +#define USB_ENDPT_HOSTWOHUB_MASK (0x80U) +#define USB_ENDPT_HOSTWOHUB_SHIFT (7U) +/*! HOSTWOHUB - Host Without A Hub + * 0b0..Connected using a hub (USBFS generates PRE_PID as required) + * 0b1..Connected directly to host without a hub, or was used to attach + */ +#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) +/*! @} */ + +/* The count of USB_ENDPT */ +#define USB_ENDPT_COUNT (16U) + +/*! @name USBCTRL - USB Control */ +/*! @{ */ + +#define USB_USBCTRL_DPDM_LANE_REVERSE_MASK (0x4U) +#define USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT (2U) +/*! DPDM_LANE_REVERSE - DP and DM Lane Reversal Control + * 0b0..Standard USB DP and DM package pin assignment + * 0b1..Reverse roles of USB DP and DM package pins + */ +#define USB_USBCTRL_DPDM_LANE_REVERSE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT)) & USB_USBCTRL_DPDM_LANE_REVERSE_MASK) + +#define USB_USBCTRL_HOST_LS_EOP_MASK (0x8U) +#define USB_USBCTRL_HOST_LS_EOP_SHIFT (3U) +/*! HOST_LS_EOP - Host-Mode-Only Low-Speed Device EOP Signaling + * 0b0..Full-speed device or a low-speed device through a hub + * 0b1..Directly-connected low-speed device + */ +#define USB_USBCTRL_HOST_LS_EOP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_HOST_LS_EOP_SHIFT)) & USB_USBCTRL_HOST_LS_EOP_MASK) + +#define USB_USBCTRL_UARTSEL_MASK (0x10U) +#define USB_USBCTRL_UARTSEL_SHIFT (4U) +/*! UARTSEL - UART Select + * 0b0..USB DP and DM external package pins are used for USB signaling. + * 0b1..USB DP and DM external package pins are used for UART signaling. + */ +#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) + +#define USB_USBCTRL_UARTCHLS_MASK (0x20U) +#define USB_USBCTRL_UARTCHLS_SHIFT (5U) +/*! UARTCHLS - UART Signal Channel Select + * 0b0..USB DP and DM signals are used as UART TX/RX. + * 0b1..USB DP and DM signals are used as UART RX/TX. + */ +#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) + +#define USB_USBCTRL_PDE_MASK (0x40U) +#define USB_USBCTRL_PDE_SHIFT (6U) +/*! PDE - Pulldown Enable + * 0b0..Disable on D+ and D- + * 0b1..Enable on D+ and D- + */ +#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) + +#define USB_USBCTRL_SUSP_MASK (0x80U) +#define USB_USBCTRL_SUSP_SHIFT (7U) +/*! SUSP - Suspend + * 0b0..Not in Suspend state + * 0b1..In Suspend state + */ +#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) +/*! @} */ + +/*! @name OBSERVE - USB OTG Observe */ +/*! @{ */ + +#define USB_OBSERVE_DMPD_MASK (0x10U) +#define USB_OBSERVE_DMPD_SHIFT (4U) +/*! DMPD - D- Pulldown + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) + +#define USB_OBSERVE_DPPD_MASK (0x40U) +#define USB_OBSERVE_DPPD_SHIFT (6U) +/*! DPPD - D+ Pulldown + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) + +#define USB_OBSERVE_DPPU_MASK (0x80U) +#define USB_OBSERVE_DPPU_SHIFT (7U) +/*! DPPU - D+ Pullup + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) +/*! @} */ + +/*! @name CONTROL - USB OTG Control */ +/*! @{ */ + +#define USB_CONTROL_VBUS_SOURCE_SEL_MASK (0x1U) +#define USB_CONTROL_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS Monitoring Source Select + * 0b0..Reserved + * 0b1..Resistive divider attached to a GPIO pin + */ +#define USB_CONTROL_VBUS_SOURCE_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_VBUS_SOURCE_SEL_SHIFT)) & USB_CONTROL_VBUS_SOURCE_SEL_MASK) + +#define USB_CONTROL_SESS_VLD_MASK (0x2U) +#define USB_CONTROL_SESS_VLD_SHIFT (1U) +/*! SESS_VLD - VBUS Session Valid status + * 0b0..Below + * 0b1..Above + */ +#define USB_CONTROL_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_SESS_VLD_SHIFT)) & USB_CONTROL_SESS_VLD_MASK) + +#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +/*! DPPULLUPNONOTG - DP Pullup in Non-OTG Device Mode + * 0b0..Disable + * 0b1..Enabled + */ +#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) +/*! @} */ + +/*! @name USBTRC0 - USB Transceiver Control 0 */ +/*! @{ */ + +#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) +#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +/*! USB_RESUME_INT - USB Asynchronous Interrupt + * 0b0..Not generated + * 0b1..Generated because of the USB asynchronous interrupt + */ +#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) + +#define USB_USBTRC0_SYNC_DET_MASK (0x2U) +#define USB_USBTRC0_SYNC_DET_SHIFT (1U) +/*! SYNC_DET - Synchronous USB Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) + +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) +/*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status */ +#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) + +#define USB_USBTRC0_VREDG_DET_MASK (0x8U) +#define USB_USBTRC0_VREDG_DET_SHIFT (3U) +/*! VREDG_DET - VREGIN Rising Edge Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) + +#define USB_USBTRC0_VFEDG_DET_MASK (0x10U) +#define USB_USBTRC0_VFEDG_DET_SHIFT (4U) +/*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) + +#define USB_USBTRC0_USBRESMEN_MASK (0x20U) +#define USB_USBTRC0_USBRESMEN_SHIFT (5U) +/*! USBRESMEN - Asynchronous Resume Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) + +#define USB_USBTRC0_VREGIN_STS_MASK (0x40U) +#define USB_USBTRC0_VREGIN_STS_SHIFT (6U) +/*! VREGIN_STS - VREGIN Status */ +#define USB_USBTRC0_VREGIN_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK) + +#define USB_USBTRC0_USBRESET_MASK (0x80U) +#define USB_USBTRC0_USBRESET_SHIFT (7U) +/*! USBRESET - USB Reset + * 0b0..Normal USBFS operation + * 0b1..Returns USBFS to its reset state + */ +#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) +/*! @} */ + +/*! @name USBFRMADJUST - Frame Adjust */ +/*! @{ */ + +#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) +#define USB_USBFRMADJUST_ADJ_SHIFT (0U) +/*! ADJ - Frame Adjustment */ +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) +/*! @} */ + +/*! @name MISCCTRL - Miscellaneous Control */ +/*! @{ */ + +#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) +#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) +/*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode + * 0b0..When the byte-times SOF threshold is reached + * 0b1..When 8 byte-times SOF threshold is reached or overstepped + */ +#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) + +#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) +#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) +/*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select + * 0b0..According to the SOF threshold value + * 0b1..When the SOF counter reaches 0 + */ +#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) + +#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) +#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) +/*! OWNERRISODIS - OWN Error Detect for ISO IN and ISO OUT Disable + * 0b0..Enable + * 0b1..Disable + */ +#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) + +#define USB_MISCCTRL_VREDG_EN_MASK (0x8U) +#define USB_MISCCTRL_VREDG_EN_SHIFT (3U) +/*! VREDG_EN - VREGIN Rising Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) + +#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) +#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) +/*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) + +#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) +#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) +/*! STL_ADJ_EN - USB Peripheral Mode Stall Adjust Enable + * 0b0..If ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint stalls. + * 0b1..If ENDPTn[END_STALL] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls. + */ +#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) +/*! @} */ + +/*! @name STALL_IL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction */ +/*! @{ */ + +#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) +#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) +/*! STALL_I_DIS0 - Disable Endpoint 0 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) +#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) +/*! STALL_I_DIS1 - Disable Endpoint 1 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) +#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) +/*! STALL_I_DIS2 - Disable Endpoint 2 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) +#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) +/*! STALL_I_DIS3 - Disable Endpoint 3 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) +#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) +/*! STALL_I_DIS4 - Disable Endpoint 4 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) +#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) +/*! STALL_I_DIS5 - Disable Endpoint 5 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) +#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) +/*! STALL_I_DIS6 - Disable Endpoint 6 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) +#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) +/*! STALL_I_DIS7 - Disable Endpoint 7 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) +/*! @} */ + +/*! @name STALL_IH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction */ +/*! @{ */ + +#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) +#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) +/*! STALL_I_DIS8 - Disable Endpoint 8 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) +#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) +/*! STALL_I_DIS9 - Disable Endpoint 9 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) +#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) +/*! STALL_I_DIS10 - Disable Endpoint 10 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) +#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) +/*! STALL_I_DIS11 - Disable Endpoint 11 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) +#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) +/*! STALL_I_DIS12 - Disable Endpoint 12 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) +#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) +/*! STALL_I_DIS13 - Disable Endpoint 13 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) +#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) +/*! STALL_I_DIS14 - Disable Endpoint 14 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) +#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) +/*! STALL_I_DIS15 - Disable Endpoint 15 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) +/*! @} */ + +/*! @name STALL_OL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction */ +/*! @{ */ + +#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) +#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) +/*! STALL_O_DIS0 - Disable Endpoint 0 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) +#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) +/*! STALL_O_DIS1 - Disable Endpoint 1 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) +#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) +/*! STALL_O_DIS2 - Disable Endpoint 2 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) +#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) +/*! STALL_O_DIS3 - Disable Endpoint 3 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) +#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) +/*! STALL_O_DIS4 - Disable Endpoint 4 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) +#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) +/*! STALL_O_DIS5 - Disable Endpoint 5 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) +#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) +/*! STALL_O_DIS6 - Disable Endpoint 6 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) +#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) +/*! STALL_O_DIS7 - Disable Endpoint 7 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) +/*! @} */ + +/*! @name STALL_OH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction */ +/*! @{ */ + +#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) +#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) +/*! STALL_O_DIS8 - Disable Endpoint 8 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) +#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) +/*! STALL_O_DIS9 - Disable Endpoint 9 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) +#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) +/*! STALL_O_DIS10 - Disable Endpoint 10 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) +#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) +/*! STALL_O_DIS11 - Disable Endpoint 11 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) +#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) +/*! STALL_O_DIS12 - Disable endpoint 12 OUT direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) +#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) +/*! STALL_O_DIS13 - Disable Endpoint 13 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) +#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) +/*! STALL_O_DIS14 - Disable Endpoint 14 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) +#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) +/*! STALL_O_DIS15 - Disable Endpoint 15 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_CTRL - USB Clock Recovery Control */ +/*! @{ */ + +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK (0x8U) +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT (3U) +/*! TRIM_INIT_VAL_SEL - Selects the source for the initial FIRC trim fine value used after a reset. + * 0b0..Mid-scale + * 0b1..IFR + */ +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT)) & USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK) + +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +/*! RESTART_IFRTRIM_EN - Restart from IFR Trim Value + * 0b0..Trim fine adjustment always works based on the previous updated trim fine value. + * 0b1..Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable. + */ +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) + +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +/*! RESET_RESUME_ROUGH_EN - Reset or Resume to Rough Phase Enable + * 0b0..Always works in tracking phase after the first time rough phase, to track transition. + * 0b1..Go back to rough stage whenever a bus reset or bus resume occurs. + */ +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) + +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +/*! CLOCK_RECOVER_EN - Crystal-Less USB Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_IRC_EN - FIRC Oscillator Enable */ +/*! @{ */ + +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +/*! IRC_EN - Fast IRC enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_INT_EN - Clock Recovery Combined Interrupt Enable */ +/*! @{ */ + +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) +/*! OVF_ERROR_EN - Overflow error interrupt enable + * 0b0..The interrupt is masked + * 0b1..The interrupt is enabled + */ +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_INT_STATUS - Clock Recovery Separated Interrupt Status */ +/*! @{ */ + +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +/*! OVF_ERROR - Overflow Error Interrupt Status Flag + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Clear the flag + * 0b1..Unmasked interrupt occurred + */ +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + +/* Backward compatibility */ +#define USBFS_IRQS USB_IRQS +#define USBFS_IRQHandler USB0_IRQHandler + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_USB_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_UTICK.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_UTICK.h new file mode 100644 index 000000000..9baf9dd43 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_UTICK.h @@ -0,0 +1,343 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for UTICK +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_UTICK.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for UTICK + * + * CMSIS Peripheral Access Layer for UTICK + */ + +#if !defined(PERI_UTICK_H_) +#define PERI_UTICK_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Size of Registers Arrays */ +#define UTICK_CAP_COUNT 4u + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control, offset: 0x0 */ + __IO uint32_t STAT; /**< Status, offset: 0x4 */ + __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */ + __I uint32_t CAP[UTICK_CAP_COUNT]; /**< Capture, array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick Interval + * 0b0000000000000000000000000000000.. + * *..Clock cycles as defined in the description + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat Delay + * 0b0..One-time delay + * 0b1..Delay repeats continuously + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt Flag + * 0b0..Not pending + * 0b1..Pending + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Timer Active Flag + * 0b0..Inactive (stopped) + * 0b1..Active + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture Configuration */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture-Polarity 1 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture Clear */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear Capture 0 + * 0b0..Does nothing + * 0b1..Clears the CAP0 register value + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear Capture 1 + * 0b0..Does nothing + * 0b1..Clears the CAP1 register value + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear Capture 2 + * 0b0..Does nothing + * 0b1..Clears the CAP2 register value + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear Capture 3 + * 0b0..Does nothing + * 0b1..Clears the CAP3 register value + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Captured Value for the Related Capture Event */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Captured Value Valid Flag + * 0b0..Valid value not captured + * 0b1..Valid value captured + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_UTICK_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_VBAT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_VBAT.h new file mode 100644 index 000000000..5ff1e419b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_VBAT.h @@ -0,0 +1,267 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for VBAT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_VBAT.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for VBAT + * + * CMSIS Peripheral Access Layer for VBAT + */ + +#if !defined(PERI_VBAT_H_) +#define PERI_VBAT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- VBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer + * @{ + */ + +/** VBAT - Size of Registers Arrays */ +#define VBAT_WAKEUP_COUNT 2u + +/** VBAT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[508]; + __IO uint32_t FROCTLA; /**< FRO16K Control A, offset: 0x200 */ + uint8_t RESERVED_1[20]; + __IO uint32_t FROLCKA; /**< FRO16K Lock A, offset: 0x218 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FROCLKE; /**< FRO16K Clock Enable, offset: 0x220 */ + uint8_t RESERVED_3[1244]; + struct { /* offset: 0x700, array step: 0x8 */ + __IO uint32_t WAKEUPA; /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } WAKEUP[VBAT_WAKEUP_COUNT]; + uint8_t RESERVED_4[232]; + __IO uint32_t WAKLCKA; /**< Wakeup Lock A, offset: 0x7F8 */ +} VBAT_Type; + +/* ---------------------------------------------------------------------------- + -- VBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Register_Masks VBAT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define VBAT_VERID_FEATURE_MASK (0xFFFFU) +#define VBAT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define VBAT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK) + +#define VBAT_VERID_MINOR_MASK (0xFF0000U) +#define VBAT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define VBAT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK) + +#define VBAT_VERID_MAJOR_MASK (0xFF000000U) +#define VBAT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define VBAT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name FROCTLA - FRO16K Control A */ +/*! @{ */ + +#define VBAT_FROCTLA_FRO_EN_MASK (0x1U) +#define VBAT_FROCTLA_FRO_EN_SHIFT (0U) +/*! FRO_EN - FRO16K Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_FROCTLA_FRO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK) +/*! @} */ + +/*! @name FROLCKA - FRO16K Lock A */ +/*! @{ */ + +#define VBAT_FROLCKA_LOCK_MASK (0x1U) +#define VBAT_FROLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_FROLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK) +/*! @} */ + +/*! @name FROCLKE - FRO16K Clock Enable */ +/*! @{ */ + +#define VBAT_FROCLKE_CLKE_MASK (0x3U) +#define VBAT_FROCLKE_CLKE_SHIFT (0U) +/*! CLKE - Clock Enable */ +#define VBAT_FROCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK) +/*! @} */ + +/*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */ +/*! @{ */ + +#define VBAT_WAKEUP_WAKEUPA_REG_MASK (0xFFFFFFFFU) +#define VBAT_WAKEUP_WAKEUPA_REG_SHIFT (0U) +/*! REG - Register */ +#define VBAT_WAKEUP_WAKEUPA_REG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK) +/*! @} */ + +/* The count of VBAT_WAKEUP_WAKEUPA */ +#define VBAT_WAKEUP_WAKEUPA_COUNT (2U) + +/*! @name WAKLCKA - Wakeup Lock A */ +/*! @{ */ + +#define VBAT_WAKLCKA_LOCK_MASK (0x1U) +#define VBAT_WAKLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_WAKLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VBAT_Register_Masks */ + + +/*! + * @} + */ /* end of group VBAT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_VBAT_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_WAKETIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_WAKETIMER.h new file mode 100644 index 000000000..67c8eba24 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_WAKETIMER.h @@ -0,0 +1,222 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for WAKETIMER +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_WAKETIMER.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for WAKETIMER + * + * CMSIS Peripheral Access Layer for WAKETIMER + */ + +#if !defined(PERI_WAKETIMER_H_) +#define PERI_WAKETIMER_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- WAKETIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WAKETIMER_Peripheral_Access_Layer WAKETIMER Peripheral Access Layer + * @{ + */ + +/** WAKETIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t WAKE_TIMER_CTRL; /**< Wake Timer Control, offset: 0x0 */ + uint8_t RESERVED_0[8]; + __IO uint32_t WAKE_TIMER_CNT; /**< Wake Timer Counter, offset: 0xC */ +} WAKETIMER_Type; + +/* ---------------------------------------------------------------------------- + -- WAKETIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WAKETIMER_Register_Masks WAKETIMER Register Masks + * @{ + */ + +/*! @name WAKE_TIMER_CTRL - Wake Timer Control */ +/*! @{ */ + +#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) +#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) +/*! WAKE_FLAG - Wake Timer Status Flag + * 0b0..Wake timer has not timed out. + * 0b1..Wake timer has timed out. + */ +#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) + +#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) +#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) +/*! CLR_WAKE_TIMER - Clear Wake Timer + * 0b0..No effect. + * 0b1..Clears the wake timer counter and halts operation until a new count value is loaded. + */ +#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) + +#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) +#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) +/*! OSC_DIV_ENA - OSC Divide Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) + +#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) +#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) +/*! INTR_EN - Enable Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CNT - Wake Timer Counter */ +/*! @{ */ + +#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU) +#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U) +/*! WAKE_CNT - Wake Counter */ +#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WAKETIMER_Register_Masks */ + + +/*! + * @} + */ /* end of group WAKETIMER_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_WAKETIMER_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_WUU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_WUU.h new file mode 100644 index 000000000..4f6abb94d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_WUU.h @@ -0,0 +1,1622 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for WUU +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_WUU.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for WUU + * + * CMSIS Peripheral Access Layer for WUU + */ + +#if !defined(PERI_WUU_H_) +#define PERI_WUU_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- WUU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer + * @{ + */ + +/** WUU - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t PE1; /**< Pin Enable 1, offset: 0x8 */ + __IO uint32_t PE2; /**< Pin Enable 2, offset: 0xC */ + uint8_t RESERVED_0[8]; + __IO uint32_t ME; /**< Module Interrupt Enable, offset: 0x18 */ + __IO uint32_t DE; /**< Module DMA/Trigger Enable, offset: 0x1C */ + __IO uint32_t PF; /**< Pin Flag, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FILT; /**< Pin Filter, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */ + __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */ + uint8_t RESERVED_3[8]; + __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */ + uint8_t RESERVED_4[4]; + __IO uint32_t PMC; /**< Pin Mode Configuration, offset: 0x50 */ + uint8_t RESERVED_5[4]; + __IO uint32_t FMC; /**< Pin Filter Mode Configuration, offset: 0x58 */ +} WUU_Type; + +/* ---------------------------------------------------------------------------- + -- WUU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Register_Masks WUU Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define WUU_VERID_FEATURE_MASK (0xFFFFU) +#define WUU_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for + * external pin/filter detection during all power modes enabled. + */ +#define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK) + +#define WUU_VERID_MINOR_MASK (0xFF0000U) +#define WUU_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define WUU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK) + +#define WUU_VERID_MAJOR_MASK (0xFF000000U) +#define WUU_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define WUU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define WUU_PARAM_FILTERS_MASK (0xFFU) +#define WUU_PARAM_FILTERS_SHIFT (0U) +/*! FILTERS - Filter Number */ +#define WUU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK) + +#define WUU_PARAM_DMAS_MASK (0xFF00U) +#define WUU_PARAM_DMAS_SHIFT (8U) +/*! DMAS - DMA Number */ +#define WUU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK) + +#define WUU_PARAM_MODULES_MASK (0xFF0000U) +#define WUU_PARAM_MODULES_SHIFT (16U) +/*! MODULES - Module Number */ +#define WUU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK) + +#define WUU_PARAM_PINS_MASK (0xFF000000U) +#define WUU_PARAM_PINS_SHIFT (24U) +/*! PINS - Pin Number */ +#define WUU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK) +/*! @} */ + +/*! @name PE1 - Pin Enable 1 */ +/*! @{ */ + +#define WUU_PE1_WUPE0_MASK (0x3U) +#define WUU_PE1_WUPE0_SHIFT (0U) +/*! WUPE0 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE0_SHIFT)) & WUU_PE1_WUPE0_MASK) + +#define WUU_PE1_WUPE1_MASK (0xCU) +#define WUU_PE1_WUPE1_SHIFT (2U) +/*! WUPE1 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE1_SHIFT)) & WUU_PE1_WUPE1_MASK) + +#define WUU_PE1_WUPE2_MASK (0x30U) +#define WUU_PE1_WUPE2_SHIFT (4U) +/*! WUPE2 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK) + +#define WUU_PE1_WUPE3_MASK (0xC0U) +#define WUU_PE1_WUPE3_SHIFT (6U) +/*! WUPE3 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK) + +#define WUU_PE1_WUPE4_MASK (0x300U) +#define WUU_PE1_WUPE4_SHIFT (8U) +/*! WUPE4 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK) + +#define WUU_PE1_WUPE5_MASK (0xC00U) +#define WUU_PE1_WUPE5_SHIFT (10U) +/*! WUPE5 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK) + +#define WUU_PE1_WUPE6_MASK (0x3000U) +#define WUU_PE1_WUPE6_SHIFT (12U) +/*! WUPE6 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK) + +#define WUU_PE1_WUPE7_MASK (0xC000U) +#define WUU_PE1_WUPE7_SHIFT (14U) +/*! WUPE7 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK) + +#define WUU_PE1_WUPE8_MASK (0x30000U) +#define WUU_PE1_WUPE8_SHIFT (16U) +/*! WUPE8 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK) + +#define WUU_PE1_WUPE9_MASK (0xC0000U) +#define WUU_PE1_WUPE9_SHIFT (18U) +/*! WUPE9 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK) + +#define WUU_PE1_WUPE10_MASK (0x300000U) +#define WUU_PE1_WUPE10_SHIFT (20U) +/*! WUPE10 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK) + +#define WUU_PE1_WUPE11_MASK (0xC00000U) +#define WUU_PE1_WUPE11_SHIFT (22U) +/*! WUPE11 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK) + +#define WUU_PE1_WUPE12_MASK (0x3000000U) +#define WUU_PE1_WUPE12_SHIFT (24U) +/*! WUPE12 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK) + +#define WUU_PE1_WUPE13_MASK (0xC000000U) +#define WUU_PE1_WUPE13_SHIFT (26U) +/*! WUPE13 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK) + +#define WUU_PE1_WUPE14_MASK (0x30000000U) +#define WUU_PE1_WUPE14_SHIFT (28U) +/*! WUPE14 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE14_SHIFT)) & WUU_PE1_WUPE14_MASK) + +#define WUU_PE1_WUPE15_MASK (0xC0000000U) +#define WUU_PE1_WUPE15_SHIFT (30U) +/*! WUPE15 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE15_SHIFT)) & WUU_PE1_WUPE15_MASK) +/*! @} */ + +/*! @name PE2 - Pin Enable 2 */ +/*! @{ */ + +#define WUU_PE2_WUPE16_MASK (0x3U) +#define WUU_PE2_WUPE16_SHIFT (0U) +/*! WUPE16 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK) + +#define WUU_PE2_WUPE17_MASK (0xCU) +#define WUU_PE2_WUPE17_SHIFT (2U) +/*! WUPE17 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK) + +#define WUU_PE2_WUPE18_MASK (0x30U) +#define WUU_PE2_WUPE18_SHIFT (4U) +/*! WUPE18 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK) + +#define WUU_PE2_WUPE19_MASK (0xC0U) +#define WUU_PE2_WUPE19_SHIFT (6U) +/*! WUPE19 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK) + +#define WUU_PE2_WUPE20_MASK (0x300U) +#define WUU_PE2_WUPE20_SHIFT (8U) +/*! WUPE20 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK) + +#define WUU_PE2_WUPE21_MASK (0xC00U) +#define WUU_PE2_WUPE21_SHIFT (10U) +/*! WUPE21 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE21_SHIFT)) & WUU_PE2_WUPE21_MASK) + +#define WUU_PE2_WUPE22_MASK (0x3000U) +#define WUU_PE2_WUPE22_SHIFT (12U) +/*! WUPE22 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK) + +#define WUU_PE2_WUPE23_MASK (0xC000U) +#define WUU_PE2_WUPE23_SHIFT (14U) +/*! WUPE23 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK) + +#define WUU_PE2_WUPE24_MASK (0x30000U) +#define WUU_PE2_WUPE24_SHIFT (16U) +/*! WUPE24 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK) + +#define WUU_PE2_WUPE25_MASK (0xC0000U) +#define WUU_PE2_WUPE25_SHIFT (18U) +/*! WUPE25 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK) + +#define WUU_PE2_WUPE26_MASK (0x300000U) +#define WUU_PE2_WUPE26_SHIFT (20U) +/*! WUPE26 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK) + +#define WUU_PE2_WUPE27_MASK (0xC00000U) +#define WUU_PE2_WUPE27_SHIFT (22U) +/*! WUPE27 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK) + +#define WUU_PE2_WUPE28_MASK (0x3000000U) +#define WUU_PE2_WUPE28_SHIFT (24U) +/*! WUPE28 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE28_SHIFT)) & WUU_PE2_WUPE28_MASK) + +#define WUU_PE2_WUPE29_MASK (0xC000000U) +#define WUU_PE2_WUPE29_SHIFT (26U) +/*! WUPE29 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE29_SHIFT)) & WUU_PE2_WUPE29_MASK) + +#define WUU_PE2_WUPE30_MASK (0x30000000U) +#define WUU_PE2_WUPE30_SHIFT (28U) +/*! WUPE30 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE30_SHIFT)) & WUU_PE2_WUPE30_MASK) + +#define WUU_PE2_WUPE31_MASK (0xC0000000U) +#define WUU_PE2_WUPE31_SHIFT (30U) +/*! WUPE31 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE31_SHIFT)) & WUU_PE2_WUPE31_MASK) +/*! @} */ + +/*! @name ME - Module Interrupt Enable */ +/*! @{ */ + +#define WUU_ME_WUME0_MASK (0x1U) +#define WUU_ME_WUME0_SHIFT (0U) +/*! WUME0 - Module Interrupt Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK) + +#define WUU_ME_WUME1_MASK (0x2U) +#define WUU_ME_WUME1_SHIFT (1U) +/*! WUME1 - Module Interrupt Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK) + +#define WUU_ME_WUME2_MASK (0x4U) +#define WUU_ME_WUME2_SHIFT (2U) +/*! WUME2 - Module Interrupt Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK) + +#define WUU_ME_WUME3_MASK (0x8U) +#define WUU_ME_WUME3_SHIFT (3U) +/*! WUME3 - Module Interrupt Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK) + +#define WUU_ME_WUME6_MASK (0x40U) +#define WUU_ME_WUME6_SHIFT (6U) +/*! WUME6 - Module Interrupt Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK) + +#define WUU_ME_WUME8_MASK (0x100U) +#define WUU_ME_WUME8_SHIFT (8U) +/*! WUME8 - Module Interrupt Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK) +/*! @} */ + +/*! @name DE - Module DMA/Trigger Enable */ +/*! @{ */ + +#define WUU_DE_WUDE4_MASK (0x10U) +#define WUU_DE_WUDE4_SHIFT (4U) +/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK) + +#define WUU_DE_WUDE6_MASK (0x40U) +#define WUU_DE_WUDE6_SHIFT (6U) +/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK) + +#define WUU_DE_WUDE8_MASK (0x100U) +#define WUU_DE_WUDE8_SHIFT (8U) +/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK) +/*! @} */ + +/*! @name PF - Pin Flag */ +/*! @{ */ + +#define WUU_PF_WUF0_MASK (0x1U) +#define WUU_PF_WUF0_SHIFT (0U) +/*! WUF0 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF0_SHIFT)) & WUU_PF_WUF0_MASK) + +#define WUU_PF_WUF1_MASK (0x2U) +#define WUU_PF_WUF1_SHIFT (1U) +/*! WUF1 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF1_SHIFT)) & WUU_PF_WUF1_MASK) + +#define WUU_PF_WUF2_MASK (0x4U) +#define WUU_PF_WUF2_SHIFT (2U) +/*! WUF2 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK) + +#define WUU_PF_WUF3_MASK (0x8U) +#define WUU_PF_WUF3_SHIFT (3U) +/*! WUF3 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK) + +#define WUU_PF_WUF4_MASK (0x10U) +#define WUU_PF_WUF4_SHIFT (4U) +/*! WUF4 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK) + +#define WUU_PF_WUF5_MASK (0x20U) +#define WUU_PF_WUF5_SHIFT (5U) +/*! WUF5 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK) + +#define WUU_PF_WUF6_MASK (0x40U) +#define WUU_PF_WUF6_SHIFT (6U) +/*! WUF6 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK) + +#define WUU_PF_WUF7_MASK (0x80U) +#define WUU_PF_WUF7_SHIFT (7U) +/*! WUF7 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK) + +#define WUU_PF_WUF8_MASK (0x100U) +#define WUU_PF_WUF8_SHIFT (8U) +/*! WUF8 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK) + +#define WUU_PF_WUF9_MASK (0x200U) +#define WUU_PF_WUF9_SHIFT (9U) +/*! WUF9 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK) + +#define WUU_PF_WUF10_MASK (0x400U) +#define WUU_PF_WUF10_SHIFT (10U) +/*! WUF10 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK) + +#define WUU_PF_WUF11_MASK (0x800U) +#define WUU_PF_WUF11_SHIFT (11U) +/*! WUF11 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK) + +#define WUU_PF_WUF12_MASK (0x1000U) +#define WUU_PF_WUF12_SHIFT (12U) +/*! WUF12 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK) + +#define WUU_PF_WUF13_MASK (0x2000U) +#define WUU_PF_WUF13_SHIFT (13U) +/*! WUF13 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK) + +#define WUU_PF_WUF14_MASK (0x4000U) +#define WUU_PF_WUF14_SHIFT (14U) +/*! WUF14 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF14_SHIFT)) & WUU_PF_WUF14_MASK) + +#define WUU_PF_WUF15_MASK (0x8000U) +#define WUU_PF_WUF15_SHIFT (15U) +/*! WUF15 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF15_SHIFT)) & WUU_PF_WUF15_MASK) + +#define WUU_PF_WUF16_MASK (0x10000U) +#define WUU_PF_WUF16_SHIFT (16U) +/*! WUF16 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK) + +#define WUU_PF_WUF17_MASK (0x20000U) +#define WUU_PF_WUF17_SHIFT (17U) +/*! WUF17 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK) + +#define WUU_PF_WUF18_MASK (0x40000U) +#define WUU_PF_WUF18_SHIFT (18U) +/*! WUF18 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK) + +#define WUU_PF_WUF19_MASK (0x80000U) +#define WUU_PF_WUF19_SHIFT (19U) +/*! WUF19 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK) + +#define WUU_PF_WUF20_MASK (0x100000U) +#define WUU_PF_WUF20_SHIFT (20U) +/*! WUF20 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK) + +#define WUU_PF_WUF21_MASK (0x200000U) +#define WUU_PF_WUF21_SHIFT (21U) +/*! WUF21 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF21_SHIFT)) & WUU_PF_WUF21_MASK) + +#define WUU_PF_WUF22_MASK (0x400000U) +#define WUU_PF_WUF22_SHIFT (22U) +/*! WUF22 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK) + +#define WUU_PF_WUF23_MASK (0x800000U) +#define WUU_PF_WUF23_SHIFT (23U) +/*! WUF23 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK) + +#define WUU_PF_WUF24_MASK (0x1000000U) +#define WUU_PF_WUF24_SHIFT (24U) +/*! WUF24 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK) + +#define WUU_PF_WUF25_MASK (0x2000000U) +#define WUU_PF_WUF25_SHIFT (25U) +/*! WUF25 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK) + +#define WUU_PF_WUF26_MASK (0x4000000U) +#define WUU_PF_WUF26_SHIFT (26U) +/*! WUF26 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK) + +#define WUU_PF_WUF27_MASK (0x8000000U) +#define WUU_PF_WUF27_SHIFT (27U) +/*! WUF27 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK) + +#define WUU_PF_WUF28_MASK (0x10000000U) +#define WUU_PF_WUF28_SHIFT (28U) +/*! WUF28 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF28_SHIFT)) & WUU_PF_WUF28_MASK) + +#define WUU_PF_WUF29_MASK (0x20000000U) +#define WUU_PF_WUF29_SHIFT (29U) +/*! WUF29 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF29_SHIFT)) & WUU_PF_WUF29_MASK) + +#define WUU_PF_WUF30_MASK (0x40000000U) +#define WUU_PF_WUF30_SHIFT (30U) +/*! WUF30 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF30_SHIFT)) & WUU_PF_WUF30_MASK) + +#define WUU_PF_WUF31_MASK (0x80000000U) +#define WUU_PF_WUF31_SHIFT (31U) +/*! WUF31 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF31_SHIFT)) & WUU_PF_WUF31_MASK) +/*! @} */ + +/*! @name FILT - Pin Filter */ +/*! @{ */ + +#define WUU_FILT_FILTSEL1_MASK (0x1FU) +#define WUU_FILT_FILTSEL1_SHIFT (0U) +/*! FILTSEL1 - Filter 1 Pin Select */ +#define WUU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK) + +#define WUU_FILT_FILTE1_MASK (0x60U) +#define WUU_FILT_FILTE1_SHIFT (5U) +/*! FILTE1 - Filter 1 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK) + +#define WUU_FILT_FILTF1_MASK (0x80U) +#define WUU_FILT_FILTF1_SHIFT (7U) +/*! FILTF1 - Filter 1 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK) + +#define WUU_FILT_FILTSEL2_MASK (0x1F00U) +#define WUU_FILT_FILTSEL2_SHIFT (8U) +/*! FILTSEL2 - Filter 2 Pin Select */ +#define WUU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK) + +#define WUU_FILT_FILTE2_MASK (0x6000U) +#define WUU_FILT_FILTE2_SHIFT (13U) +/*! FILTE2 - Filter 2 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK) + +#define WUU_FILT_FILTF2_MASK (0x8000U) +#define WUU_FILT_FILTF2_SHIFT (15U) +/*! FILTF2 - Filter 2 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK) +/*! @} */ + +/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */ +/*! @{ */ + +#define WUU_PDC1_WUPDC0_MASK (0x3U) +#define WUU_PDC1_WUPDC0_SHIFT (0U) +/*! WUPDC0 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC0_SHIFT)) & WUU_PDC1_WUPDC0_MASK) + +#define WUU_PDC1_WUPDC1_MASK (0xCU) +#define WUU_PDC1_WUPDC1_SHIFT (2U) +/*! WUPDC1 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC1_SHIFT)) & WUU_PDC1_WUPDC1_MASK) + +#define WUU_PDC1_WUPDC2_MASK (0x30U) +#define WUU_PDC1_WUPDC2_SHIFT (4U) +/*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK) + +#define WUU_PDC1_WUPDC3_MASK (0xC0U) +#define WUU_PDC1_WUPDC3_SHIFT (6U) +/*! WUPDC3 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK) + +#define WUU_PDC1_WUPDC4_MASK (0x300U) +#define WUU_PDC1_WUPDC4_SHIFT (8U) +/*! WUPDC4 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK) + +#define WUU_PDC1_WUPDC5_MASK (0xC00U) +#define WUU_PDC1_WUPDC5_SHIFT (10U) +/*! WUPDC5 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK) + +#define WUU_PDC1_WUPDC6_MASK (0x3000U) +#define WUU_PDC1_WUPDC6_SHIFT (12U) +/*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK) + +#define WUU_PDC1_WUPDC7_MASK (0xC000U) +#define WUU_PDC1_WUPDC7_SHIFT (14U) +/*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK) + +#define WUU_PDC1_WUPDC8_MASK (0x30000U) +#define WUU_PDC1_WUPDC8_SHIFT (16U) +/*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK) + +#define WUU_PDC1_WUPDC9_MASK (0xC0000U) +#define WUU_PDC1_WUPDC9_SHIFT (18U) +/*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK) + +#define WUU_PDC1_WUPDC10_MASK (0x300000U) +#define WUU_PDC1_WUPDC10_SHIFT (20U) +/*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK) + +#define WUU_PDC1_WUPDC11_MASK (0xC00000U) +#define WUU_PDC1_WUPDC11_SHIFT (22U) +/*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK) + +#define WUU_PDC1_WUPDC12_MASK (0x3000000U) +#define WUU_PDC1_WUPDC12_SHIFT (24U) +/*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK) + +#define WUU_PDC1_WUPDC13_MASK (0xC000000U) +#define WUU_PDC1_WUPDC13_SHIFT (26U) +/*! WUPDC13 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK) + +#define WUU_PDC1_WUPDC14_MASK (0x30000000U) +#define WUU_PDC1_WUPDC14_SHIFT (28U) +/*! WUPDC14 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC14_SHIFT)) & WUU_PDC1_WUPDC14_MASK) + +#define WUU_PDC1_WUPDC15_MASK (0xC0000000U) +#define WUU_PDC1_WUPDC15_SHIFT (30U) +/*! WUPDC15 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC15_SHIFT)) & WUU_PDC1_WUPDC15_MASK) +/*! @} */ + +/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */ +/*! @{ */ + +#define WUU_PDC2_WUPDC16_MASK (0x3U) +#define WUU_PDC2_WUPDC16_SHIFT (0U) +/*! WUPDC16 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK) + +#define WUU_PDC2_WUPDC17_MASK (0xCU) +#define WUU_PDC2_WUPDC17_SHIFT (2U) +/*! WUPDC17 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK) + +#define WUU_PDC2_WUPDC18_MASK (0x30U) +#define WUU_PDC2_WUPDC18_SHIFT (4U) +/*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK) + +#define WUU_PDC2_WUPDC19_MASK (0xC0U) +#define WUU_PDC2_WUPDC19_SHIFT (6U) +/*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK) + +#define WUU_PDC2_WUPDC20_MASK (0x300U) +#define WUU_PDC2_WUPDC20_SHIFT (8U) +/*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK) + +#define WUU_PDC2_WUPDC21_MASK (0xC00U) +#define WUU_PDC2_WUPDC21_SHIFT (10U) +/*! WUPDC21 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC21_SHIFT)) & WUU_PDC2_WUPDC21_MASK) + +#define WUU_PDC2_WUPDC22_MASK (0x3000U) +#define WUU_PDC2_WUPDC22_SHIFT (12U) +/*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK) + +#define WUU_PDC2_WUPDC23_MASK (0xC000U) +#define WUU_PDC2_WUPDC23_SHIFT (14U) +/*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK) + +#define WUU_PDC2_WUPDC24_MASK (0x30000U) +#define WUU_PDC2_WUPDC24_SHIFT (16U) +/*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK) + +#define WUU_PDC2_WUPDC25_MASK (0xC0000U) +#define WUU_PDC2_WUPDC25_SHIFT (18U) +/*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK) + +#define WUU_PDC2_WUPDC26_MASK (0x300000U) +#define WUU_PDC2_WUPDC26_SHIFT (20U) +/*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK) + +#define WUU_PDC2_WUPDC27_MASK (0xC00000U) +#define WUU_PDC2_WUPDC27_SHIFT (22U) +/*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK) + +#define WUU_PDC2_WUPDC28_MASK (0x3000000U) +#define WUU_PDC2_WUPDC28_SHIFT (24U) +/*! WUPDC28 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC28_SHIFT)) & WUU_PDC2_WUPDC28_MASK) + +#define WUU_PDC2_WUPDC29_MASK (0xC000000U) +#define WUU_PDC2_WUPDC29_SHIFT (26U) +/*! WUPDC29 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC29_SHIFT)) & WUU_PDC2_WUPDC29_MASK) + +#define WUU_PDC2_WUPDC30_MASK (0x30000000U) +#define WUU_PDC2_WUPDC30_SHIFT (28U) +/*! WUPDC30 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC30_SHIFT)) & WUU_PDC2_WUPDC30_MASK) + +#define WUU_PDC2_WUPDC31_MASK (0xC0000000U) +#define WUU_PDC2_WUPDC31_SHIFT (30U) +/*! WUPDC31 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC31_SHIFT)) & WUU_PDC2_WUPDC31_MASK) +/*! @} */ + +/*! @name FDC - Pin Filter DMA/Trigger Configuration */ +/*! @{ */ + +#define WUU_FDC_FILTC1_MASK (0x3U) +#define WUU_FDC_FILTC1_SHIFT (0U) +/*! FILTC1 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK) + +#define WUU_FDC_FILTC2_MASK (0xCU) +#define WUU_FDC_FILTC2_SHIFT (2U) +/*! FILTC2 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK) +/*! @} */ + +/*! @name PMC - Pin Mode Configuration */ +/*! @{ */ + +#define WUU_PMC_WUPMC0_MASK (0x1U) +#define WUU_PMC_WUPMC0_SHIFT (0U) +/*! WUPMC0 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC0_SHIFT)) & WUU_PMC_WUPMC0_MASK) + +#define WUU_PMC_WUPMC1_MASK (0x2U) +#define WUU_PMC_WUPMC1_SHIFT (1U) +/*! WUPMC1 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC1_SHIFT)) & WUU_PMC_WUPMC1_MASK) + +#define WUU_PMC_WUPMC2_MASK (0x4U) +#define WUU_PMC_WUPMC2_SHIFT (2U) +/*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK) + +#define WUU_PMC_WUPMC3_MASK (0x8U) +#define WUU_PMC_WUPMC3_SHIFT (3U) +/*! WUPMC3 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK) + +#define WUU_PMC_WUPMC4_MASK (0x10U) +#define WUU_PMC_WUPMC4_SHIFT (4U) +/*! WUPMC4 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK) + +#define WUU_PMC_WUPMC5_MASK (0x20U) +#define WUU_PMC_WUPMC5_SHIFT (5U) +/*! WUPMC5 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK) + +#define WUU_PMC_WUPMC6_MASK (0x40U) +#define WUU_PMC_WUPMC6_SHIFT (6U) +/*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK) + +#define WUU_PMC_WUPMC7_MASK (0x80U) +#define WUU_PMC_WUPMC7_SHIFT (7U) +/*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK) + +#define WUU_PMC_WUPMC8_MASK (0x100U) +#define WUU_PMC_WUPMC8_SHIFT (8U) +/*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK) + +#define WUU_PMC_WUPMC9_MASK (0x200U) +#define WUU_PMC_WUPMC9_SHIFT (9U) +/*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK) + +#define WUU_PMC_WUPMC10_MASK (0x400U) +#define WUU_PMC_WUPMC10_SHIFT (10U) +/*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK) + +#define WUU_PMC_WUPMC11_MASK (0x800U) +#define WUU_PMC_WUPMC11_SHIFT (11U) +/*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK) + +#define WUU_PMC_WUPMC12_MASK (0x1000U) +#define WUU_PMC_WUPMC12_SHIFT (12U) +/*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK) + +#define WUU_PMC_WUPMC13_MASK (0x2000U) +#define WUU_PMC_WUPMC13_SHIFT (13U) +/*! WUPMC13 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK) + +#define WUU_PMC_WUPMC14_MASK (0x4000U) +#define WUU_PMC_WUPMC14_SHIFT (14U) +/*! WUPMC14 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC14_SHIFT)) & WUU_PMC_WUPMC14_MASK) + +#define WUU_PMC_WUPMC15_MASK (0x8000U) +#define WUU_PMC_WUPMC15_SHIFT (15U) +/*! WUPMC15 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC15_SHIFT)) & WUU_PMC_WUPMC15_MASK) + +#define WUU_PMC_WUPMC16_MASK (0x10000U) +#define WUU_PMC_WUPMC16_SHIFT (16U) +/*! WUPMC16 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK) + +#define WUU_PMC_WUPMC17_MASK (0x20000U) +#define WUU_PMC_WUPMC17_SHIFT (17U) +/*! WUPMC17 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK) + +#define WUU_PMC_WUPMC18_MASK (0x40000U) +#define WUU_PMC_WUPMC18_SHIFT (18U) +/*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK) + +#define WUU_PMC_WUPMC19_MASK (0x80000U) +#define WUU_PMC_WUPMC19_SHIFT (19U) +/*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK) + +#define WUU_PMC_WUPMC20_MASK (0x100000U) +#define WUU_PMC_WUPMC20_SHIFT (20U) +/*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK) + +#define WUU_PMC_WUPMC21_MASK (0x200000U) +#define WUU_PMC_WUPMC21_SHIFT (21U) +/*! WUPMC21 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC21_SHIFT)) & WUU_PMC_WUPMC21_MASK) + +#define WUU_PMC_WUPMC22_MASK (0x400000U) +#define WUU_PMC_WUPMC22_SHIFT (22U) +/*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK) + +#define WUU_PMC_WUPMC23_MASK (0x800000U) +#define WUU_PMC_WUPMC23_SHIFT (23U) +/*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK) + +#define WUU_PMC_WUPMC24_MASK (0x1000000U) +#define WUU_PMC_WUPMC24_SHIFT (24U) +/*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK) + +#define WUU_PMC_WUPMC25_MASK (0x2000000U) +#define WUU_PMC_WUPMC25_SHIFT (25U) +/*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK) + +#define WUU_PMC_WUPMC26_MASK (0x4000000U) +#define WUU_PMC_WUPMC26_SHIFT (26U) +/*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK) + +#define WUU_PMC_WUPMC27_MASK (0x8000000U) +#define WUU_PMC_WUPMC27_SHIFT (27U) +/*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK) + +#define WUU_PMC_WUPMC28_MASK (0x10000000U) +#define WUU_PMC_WUPMC28_SHIFT (28U) +/*! WUPMC28 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC28_SHIFT)) & WUU_PMC_WUPMC28_MASK) + +#define WUU_PMC_WUPMC29_MASK (0x20000000U) +#define WUU_PMC_WUPMC29_SHIFT (29U) +/*! WUPMC29 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC29_SHIFT)) & WUU_PMC_WUPMC29_MASK) + +#define WUU_PMC_WUPMC30_MASK (0x40000000U) +#define WUU_PMC_WUPMC30_SHIFT (30U) +/*! WUPMC30 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC30_SHIFT)) & WUU_PMC_WUPMC30_MASK) + +#define WUU_PMC_WUPMC31_MASK (0x80000000U) +#define WUU_PMC_WUPMC31_SHIFT (31U) +/*! WUPMC31 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC31_SHIFT)) & WUU_PMC_WUPMC31_MASK) +/*! @} */ + +/*! @name FMC - Pin Filter Mode Configuration */ +/*! @{ */ + +#define WUU_FMC_FILTM1_MASK (0x1U) +#define WUU_FMC_FILTM1_SHIFT (0U) +/*! FILTM1 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK) + +#define WUU_FMC_FILTM2_MASK (0x2U) +#define WUU_FMC_FILTM2_SHIFT (1U) +/*! FILTM2 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WUU_Register_Masks */ + + +/*! + * @} + */ /* end of group WUU_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_WUU_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_WWDT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_WWDT.h new file mode 100644 index 000000000..f0edb8a6f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph5/PERI_WWDT.h @@ -0,0 +1,278 @@ +/* +** ################################################################### +** Processors: MCXA175VLH +** MCXA175VLL +** MCXA175VLQ +** MCXA175VPN +** MCXA176VLH +** MCXA176VLL +** MCXA176VLQ +** MCXA176VPN +** MCXA185VLH +** MCXA185VLL +** MCXA185VLQ +** MCXA185VPN +** MCXA186VLH +** MCXA186VLL +** MCXA186VLQ +** MCXA186VPN +** MCXA255VLH +** MCXA255VLL +** MCXA255VLQ +** MCXA255VPN +** MCXA256VLH +** MCXA256VLL +** MCXA256VLQ +** MCXA256VPN +** MCXA265VLH +** MCXA265VLL +** MCXA265VLQ +** MCXA265VPN +** MCXA266VLH +** MCXA266VLL +** MCXA266VLQ +** MCXA266VPN +** +** Version: rev. 1.0, 2024-11-21 +** Build: b250804 +** +** Abstract: +** CMSIS Peripheral Access Layer for WWDT +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-21) +** Initial version based on Rev1 RM +** +** ################################################################### +*/ + +/*! + * @file PERI_WWDT.h + * @version 1.0 + * @date 2024-11-21 + * @brief CMSIS Peripheral Access Layer for WWDT + * + * CMSIS Peripheral Access Layer for WWDT + */ + +#if !defined(PERI_WWDT_H_) +#define PERI_WWDT_H_ /**< Symbol preventing repeated inclusion */ + +#if (defined(CPU_MCXA175VLH) || defined(CPU_MCXA175VLL) || defined(CPU_MCXA175VLQ) || defined(CPU_MCXA175VPN)) +#include "MCXA175_COMMON.h" +#elif (defined(CPU_MCXA176VLH) || defined(CPU_MCXA176VLL) || defined(CPU_MCXA176VLQ) || defined(CPU_MCXA176VPN)) +#include "MCXA176_COMMON.h" +#elif (defined(CPU_MCXA185VLH) || defined(CPU_MCXA185VLL) || defined(CPU_MCXA185VLQ) || defined(CPU_MCXA185VPN)) +#include "MCXA185_COMMON.h" +#elif (defined(CPU_MCXA186VLH) || defined(CPU_MCXA186VLL) || defined(CPU_MCXA186VLQ) || defined(CPU_MCXA186VPN)) +#include "MCXA186_COMMON.h" +#elif (defined(CPU_MCXA255VLH) || defined(CPU_MCXA255VLL) || defined(CPU_MCXA255VLQ) || defined(CPU_MCXA255VPN)) +#include "MCXA255_COMMON.h" +#elif (defined(CPU_MCXA256VLH) || defined(CPU_MCXA256VLL) || defined(CPU_MCXA256VLQ) || defined(CPU_MCXA256VPN)) +#include "MCXA256_COMMON.h" +#elif (defined(CPU_MCXA265VLH) || defined(CPU_MCXA265VLL) || defined(CPU_MCXA265VLQ) || defined(CPU_MCXA265VPN)) +#include "MCXA265_COMMON.h" +#elif (defined(CPU_MCXA266VLH) || defined(CPU_MCXA266VLL) || defined(CPU_MCXA266VLQ) || defined(CPU_MCXA266VPN)) +#include "MCXA266_COMMON.h" +#else + #error "No valid CPU defined!" +#endif + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Mode, offset: 0x0 */ + __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */ + __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */ + __I uint32_t TV; /**< Timer Value, offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */ + __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Mode */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog Enable + * 0b0..Timer stopped + * 0b1..Timer running + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog Reset Enable + * 0b0..Interrupt + * 0b1..Reset + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog Timeout Flag + * 0b0..Watchdog event has not occurred. + * 0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1). + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning Interrupt Flag + * 0b0..No flag + * 0b1..Flag + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog Update Mode + * 0b0..Flexible + * 0b1..Threshold + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) + +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +/*! LOCK - Lock + * 0b0..No Lock + * 0b1..Lock + */ +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) +/*! @} */ + +/*! @name TC - Timer Constant */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog Timeout Value */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Feed Sequence */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed Value */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Timer Value */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter Timer Value */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Warning Interrupt Compare Value */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog Warning Interrupt Compare Value */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Window Compare Value */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog Window Value */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* PERI_WWDT_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph_mapping.md b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph_mapping.md index cd3e33a68..9b47fb5db 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph_mapping.md +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXA/periph_mapping.md @@ -1,4 +1,7 @@ #### Peripheral folder for devices + * periph:MCXA132,MCXA133,MCXA142,MCXA143,MCXA152,MCXA153 * periph1:MCXA144,MCXA145,MCXA146,MCXA154,MCXA155,MCXA156 -* periph2:MCXA266,MCXA345,MCXA346,MCXA366 +* periph2:MCXA345,MCXA346,MCXA355,MCXA356,MCXA365,MCXA366 +* periph3:MCXA343,MCXA344 +* periph5:MCXA175,MCXA176,MCXA185,MCXA186,MCXA255,MCXA256,MCXA265,MCXA266 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC041/MCXC041_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC041/MCXC041_features.h index 2951fb32f..7c867037f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC041/MCXC041_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC041/MCXC041_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-19 -** Build: b250428 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -614,8 +614,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -638,8 +636,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -682,6 +678,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -865,6 +867,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1046,13 +1056,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC141/MCXC141_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC141/MCXC141_features.h index 14bb3c669..e74d3be9e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC141/MCXC141_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC141/MCXC141_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.9, 2016-06-08 -** Build: b250428 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -712,8 +712,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -736,8 +734,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -780,6 +776,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -978,6 +980,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1159,13 +1169,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC142/MCXC142_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC142/MCXC142_features.h index 4ae5826e0..05bccf40e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC142/MCXC142_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC142/MCXC142_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.9, 2016-06-08 -** Build: b250428 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -712,8 +712,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -736,8 +734,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -780,6 +776,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -978,6 +980,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1159,13 +1169,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143.h index 03ed91102..f9d1b38c6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC143 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143_COMMON.h index 1a82bb8c0..ccfd3edaf 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC143 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143_features.h index c7d590bf7..52f42d361 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/MCXC143_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-11 -** Build: b250506 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -444,8 +444,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (0) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (0) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -464,18 +462,28 @@ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) -/* @brief Ihe interrupt source number */ +/* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (0) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (0) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -729,8 +737,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -753,8 +759,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -797,6 +801,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -995,6 +1005,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1176,13 +1194,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/system_MCXC143.c b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/system_MCXC143.c index 31a963376..4175d4453 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/system_MCXC143.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/system_MCXC143.c @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -110,3 +110,4 @@ void SystemCoreClockUpdate (void) { __attribute__ ((weak)) void SystemInitHook (void) { /* Void implementation of the weak function. */ } + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/system_MCXC143.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/system_MCXC143.h index 18b051b8c..029135c2c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/system_MCXC143.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC143/system_MCXC143.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -75,7 +75,6 @@ extern "C" { #define CPU_INT_SLOW_CLK_HZ 8000000U /* Value of the slow internal oscillator clock frequency in Hz */ - /** * @brief System clock frequency (core clock) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144.h index d8ee1416b..1804737e6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC144 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144_COMMON.h index ad719fc3e..9afb34fbb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC144 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144_features.h index 6496eca54..24d60583f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/MCXC144_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-11 -** Build: b250506 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -444,8 +444,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (0) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (0) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -464,18 +462,28 @@ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) -/* @brief Ihe interrupt source number */ +/* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (0) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (0) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -729,8 +737,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -753,8 +759,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -797,6 +801,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -995,6 +1005,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1176,13 +1194,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/system_MCXC144.c b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/system_MCXC144.c index 62f94ff3b..34d51b3d3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/system_MCXC144.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/system_MCXC144.c @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -110,3 +110,4 @@ void SystemCoreClockUpdate (void) { __attribute__ ((weak)) void SystemInitHook (void) { /* Void implementation of the weak function. */ } + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/system_MCXC144.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/system_MCXC144.h index 99238c447..3c5793c81 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/system_MCXC144.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC144/system_MCXC144.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -75,7 +75,6 @@ extern "C" { #define CPU_INT_SLOW_CLK_HZ 8000000U /* Value of the slow internal oscillator clock frequency in Hz */ - /** * @brief System clock frequency (core clock) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC242/MCXC242_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC242/MCXC242_features.h index 4a06a2f63..49973e225 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC242/MCXC242_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC242/MCXC242_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.9, 2016-06-08 -** Build: b250428 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -714,8 +714,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -738,8 +736,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -782,6 +778,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -980,6 +982,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1161,13 +1171,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243.h index 101d25263..f490c1433 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243.h @@ -9,7 +9,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC243 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243_COMMON.h index c847160e1..3dec8943e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243_COMMON.h @@ -9,7 +9,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC243 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243_features.h index 7b4336dbc..1647fe36b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/MCXC243_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-11 -** Build: b250506 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -446,8 +446,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (0) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (0) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -466,18 +464,28 @@ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) -/* @brief Ihe interrupt source number */ +/* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (0) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (0) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -731,8 +739,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -755,8 +761,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -799,6 +803,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -997,6 +1007,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1178,13 +1196,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/system_MCXC243.c b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/system_MCXC243.c index 2e78aaf71..f9b1e9160 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/system_MCXC243.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/system_MCXC243.c @@ -9,7 +9,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -108,3 +108,4 @@ void SystemCoreClockUpdate (void) { __attribute__ ((weak)) void SystemInitHook (void) { /* Void implementation of the weak function. */ } + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/system_MCXC243.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/system_MCXC243.h index 92b2561e3..406140920 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/system_MCXC243.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC243/system_MCXC243.h @@ -9,7 +9,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -73,7 +73,6 @@ extern "C" { #define CPU_INT_SLOW_CLK_HZ 8000000U /* Value of the slow internal oscillator clock frequency in Hz */ - /** * @brief System clock frequency (core clock) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244.h index df916ca1c..e98684a94 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC244 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244_COMMON.h index fc62e5aef..19e589a1b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC244 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244_features.h index df9358e10..93f1d030b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/MCXC244_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-11 -** Build: b250506 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -446,8 +446,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (0) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (0) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -466,18 +464,28 @@ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) -/* @brief Ihe interrupt source number */ +/* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (0) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (0) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LLWU module features */ @@ -731,8 +739,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -755,8 +761,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -799,6 +803,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -997,6 +1007,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1178,13 +1196,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/system_MCXC244.c b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/system_MCXC244.c index 8f69708a9..4bc836c43 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/system_MCXC244.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/system_MCXC244.c @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -110,3 +110,4 @@ void SystemCoreClockUpdate (void) { __attribute__ ((weak)) void SystemInitHook (void) { /* Void implementation of the weak function. */ } + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/system_MCXC244.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/system_MCXC244.h index 9e438485f..d3d4ce4cf 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/system_MCXC244.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC244/system_MCXC244.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -75,7 +75,6 @@ extern "C" { #define CPU_INT_SLOW_CLK_HZ 8000000U /* Value of the slow internal oscillator clock frequency in Hz */ - /** * @brief System clock frequency (core clock) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443.h index 6b8c3a533..a998f34ae 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC443 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443_COMMON.h index 12913548d..04ff6a969 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC443 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443_features.h index d41058510..83acb60a2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/MCXC443_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-11 -** Build: b250506 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -448,8 +448,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (0) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (0) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -468,18 +466,28 @@ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) -/* @brief Ihe interrupt source number */ +/* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (0) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (0) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SLCD module features */ @@ -754,8 +762,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -778,8 +784,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -822,6 +826,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -1020,6 +1030,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1201,13 +1219,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/system_MCXC443.c b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/system_MCXC443.c index 57ec7083d..e235d5e84 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/system_MCXC443.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/system_MCXC443.c @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -110,3 +110,4 @@ void SystemCoreClockUpdate (void) { __attribute__ ((weak)) void SystemInitHook (void) { /* Void implementation of the weak function. */ } + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/system_MCXC443.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/system_MCXC443.h index 69fc05f11..ee40f5169 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/system_MCXC443.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC443/system_MCXC443.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -75,7 +75,6 @@ extern "C" { #define CPU_INT_SLOW_CLK_HZ 8000000U /* Value of the slow internal oscillator clock frequency in Hz */ - /** * @brief System clock frequency (core clock) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444.h index 19394adbd..f020cbea8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC444 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444_COMMON.h index bb18bfb6d..01436e9c8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXC444 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444_features.h index 899fc38ea..d6e02cec0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/MCXC444_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-11 -** Build: b250506 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -448,8 +448,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (0) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (0) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -468,18 +466,28 @@ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) -/* @brief Ihe interrupt source number */ +/* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (0) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (0) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SLCD module features */ @@ -754,8 +762,6 @@ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (0) /* @brief Hardware flow control (RTS, CTS) is supported. */ @@ -778,8 +784,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -822,6 +826,12 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (0) /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) @@ -1020,6 +1030,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SIM module features */ @@ -1201,13 +1219,13 @@ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +/* @brief Has Kinetis/MCX family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +/* @brief Has Kinetis/MCX sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +/* @brief Has Kinetis/MCX series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/system_MCXC444.c b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/system_MCXC444.c index f874b2630..e3404edc8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/system_MCXC444.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/system_MCXC444.c @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -110,3 +110,4 @@ void SystemCoreClockUpdate (void) { __attribute__ ((weak)) void SystemInitHook (void) { /* Void implementation of the weak function. */ } + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/system_MCXC444.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/system_MCXC444.h index 699f4dc4a..b0b18db90 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/system_MCXC444.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/MCXC444/system_MCXC444.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXC444RM, Rev.1, Mar 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -75,7 +75,6 @@ extern "C" { #define CPU_INT_SLOW_CLK_HZ 8000000U /* Value of the slow internal oscillator clock frequency in Hz */ - /** * @brief System clock frequency (core clock) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_ADC.h index 5f19100ed..8b985b36d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_ADC.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_CMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_CMP.h index 03ab73200..3bd51b7af 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_CMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_CMP.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DAC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DAC.h index ff6bb8597..7ce346f47 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DAC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DAC.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for DAC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DMA.h index 3596b6e30..2b7420ca3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DMA.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DMAMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DMAMUX.h index 386d62980..19597bd1f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DMAMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_DMAMUX.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMAMUX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FGPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FGPIO.h index e788bc769..6cfad33cb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FGPIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FGPIO.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for FGPIO diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FLEXIO.h index 41aa5cea5..4ada48ff0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FLEXIO.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FTFA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FTFA.h index 0e462b37e..9df73943d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FTFA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_FTFA.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for FTFA diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_GPIO.h index ca1fcacea..87353eb73 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_GPIO.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_I2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_I2C.h index 15e9f3d39..adaa94ba8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_I2C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_I2C.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2C diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_I2S.h index 44cc4fdad..1041b20d2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_I2S.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LCD.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LCD.h index d54358d9b..06f195890 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LCD.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LCD.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for LCD diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LLWU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LLWU.h index 8f76bcf36..2e2731318 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LLWU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LLWU.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for LLWU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LPTMR.h index 64727393a..499f969cc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LPTMR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LPTMR.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPTMR diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LPUART.h index 42993b864..44837ad2c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_LPUART.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MCG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MCG.h index 2120d37f3..4ac43cf9e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MCG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MCG.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCG diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MCM.h index 2cad2831f..d3b31d616 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MCM.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MTB.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MTB.h index 2276a5822..654d661ad 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MTB.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MTB.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MTB diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MTBDWT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MTBDWT.h index 4b20f3439..34202f74f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MTBDWT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_MTBDWT.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for MTBDWT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_NV.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_NV.h index 607be8cda..ad8d0c138 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_NV.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_NV.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for NV diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_OSC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_OSC.h index 9d5ad564b..8a070a223 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_OSC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_OSC.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PIT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PIT.h index e189f49f7..edb323a7f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PIT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PIT.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for PIT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PMC.h index fdd493978..d75704695 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PMC.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for PMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PORT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PORT.h index 955bd5aef..82dfa1222 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PORT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_PORT.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for PORT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RCM.h index dbee42447..2cbd5fbd9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RCM.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for RCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RFSYS.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RFSYS.h index 6b34a36c3..31f029943 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RFSYS.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RFSYS.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for RFSYS diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_ROM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_ROM.h index 73830f6f7..2bf80b28f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_ROM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_ROM.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for ROM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RTC.h index 290c08632..d65317e91 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_RTC.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SIM.h index 05aa73be3..4413efbcd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SIM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SIM.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for SIM @@ -482,15 +482,17 @@ typedef struct { #define SIM_SDID_SERIESID_MASK (0xF00000U) #define SIM_SDID_SERIESID_SHIFT (20U) -/*! SERIESID - Kinetis Series ID - * 0b0001..KL family +/*! SERIESID - Series ID + * 0b0001..MCXC family */ #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) #define SIM_SDID_SUBFAMID_MASK (0xF000000U) #define SIM_SDID_SUBFAMID_SHIFT (24U) -/*! SUBFAMID - TBD Sub-Family ID - * 0b0011..TBD Subfamily +/*! SUBFAMID - Sub-Family ID + * 0b0001..MCX C14x/24x Subfamily + * 0b0010..MCX C44x Subfamily + * 0b0011..MCX C041 Subfamily */ #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SMC.h index 26d97cc5b..cda9f1855 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SMC.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for SMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SPI.h index 1facbf29d..98cbf0c3d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_SPI.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPI diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_TPM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_TPM.h index 11a3e369d..1e57a633e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_TPM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_TPM.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for TPM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_UART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_UART.h index 43912fbaa..80fd8c99e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_UART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_UART.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for UART diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_USB.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_USB.h index 7c0c2c822..ff31dd611 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_USB.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_VREF.h b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_VREF.h index c7363d44d..ad9bbda0c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_VREF.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXC/periph2/PERI_VREF.h @@ -13,7 +13,7 @@ ** MCXC444VMP ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250630 ** ** Abstract: ** CMSIS Peripheral Access Layer for VREF diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/MCXE245_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/MCXE245_COMMON.h index 66e2e1c4f..5ee6dedef 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/MCXE245_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/MCXE245_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXE24x RM Rev.1 ** Version: rev. 1.0, 2025-02-21 -** Build: b250429 +** Build: b250813 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE245 @@ -336,6 +336,8 @@ typedef enum IRQn { #define EWM_BASE_ADDRS { EWM_BASE } /** Array initializer of EWM peripheral base pointers */ #define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { WDOG_EWM_IRQn } /* FLEXIO - Peripheral instance base addresses */ /** Peripheral FLEXIO base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/MCXE245_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/MCXE245_features.h index 29ea77c99..fedd4a538 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/MCXE245_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/MCXE245_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2025-02-21 -** Build: b250610 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -181,6 +181,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (1) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (1) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (1) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* ACMP module features */ @@ -217,10 +221,8 @@ /* CRC module features */ -/* @brief If CRC has CRC register */ -#define FSL_FEATURE_CRC_HAS_CRC_REGISTER (0) -/* @brief CRC16 type of the peripheral. */ -#define FSL_FEATURE_CRC_CRC16_TYPE (0) +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) /* EDMA module features */ @@ -306,8 +308,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -336,6 +336,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLASH module features */ @@ -707,8 +709,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -751,6 +751,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MSCM module features */ @@ -915,8 +919,12 @@ #define FSL_FEATURE_RTC_HAS_PCR (0) /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) /* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ #define FSL_FEATURE_RTC_HAS_ERRATA_010716 (1) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/drivers/fsl_flexcan_soc.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/drivers/fsl_flexcan_soc.c index aeaa63a8e..0a0358b7d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/drivers/fsl_flexcan_soc.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/drivers/fsl_flexcan_soc.c @@ -32,7 +32,7 @@ void CAN2_Error_DriverIRQHandler(void); void CAN2_ORed_0_15_MB_DriverIRQHandler(void); void CAN2_ORed_16_31_MB_DriverIRQHandler(void); extern void FLEXCAN_DriverEventIRQHandler(uint32_t instance); -extern void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t startMbIdx, uint32_t endMbIdx, uint32_t type); +extern void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t startMbIdx, uint32_t endMbIdx); /******************************************************************************* * Code @@ -75,7 +75,7 @@ void CAN0_Wake_Up_DriverIRQHandler(void) void CAN0_ORed_0_15_MB_DriverIRQHandler(void) { /* Instance 0, MB 0-15 */ - FLEXCAN_DriverDataIRQHandler(0U, 0U, 15U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 15U); } /*! @@ -85,7 +85,7 @@ void CAN0_ORed_0_15_MB_DriverIRQHandler(void) void CAN0_ORed_16_31_MB_DriverIRQHandler(void) { /* Instance 0, MB 16-31 */ - FLEXCAN_DriverDataIRQHandler(0U, 16U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 16U, 31U); } /*! @@ -115,7 +115,7 @@ void CAN1_Error_DriverIRQHandler(void) void CAN1_ORed_0_15_MB_DriverIRQHandler(void) { /* Instance 1, MB 0-15 */ - FLEXCAN_DriverDataIRQHandler(1U, 0U, 15U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 15U); } /*! @@ -125,7 +125,7 @@ void CAN1_ORed_0_15_MB_DriverIRQHandler(void) void CAN1_ORed_16_31_MB_DriverIRQHandler(void) { /* Instance 1, MB 16-31 */ - FLEXCAN_DriverDataIRQHandler(1U, 16U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 16U, 31U); } /*! @@ -155,7 +155,7 @@ void CAN2_Error_DriverIRQHandler(void) void CAN2_ORed_0_15_MB_DriverIRQHandler(void) { /* Instance 2, MB 0-15 */ - FLEXCAN_DriverDataIRQHandler(2U, 0U, 15U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 15U); } /*! @@ -165,5 +165,5 @@ void CAN2_ORed_0_15_MB_DriverIRQHandler(void) void CAN2_ORed_16_31_MB_DriverIRQHandler(void) { /* Instance 2*, MB 16-31 */ - FLEXCAN_DriverDataIRQHandler(2U, 16U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 16U, 31U); } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/system_MCXE245.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/system_MCXE245.c index 27041e57b..b046784b2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/system_MCXE245.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/system_MCXE245.c @@ -11,7 +11,7 @@ ** ** Reference manual: MCXE24x RM Rev.1 ** Version: rev. 1.0, 2025-02-21 -** Build: b250429 +** Build: b250530 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -145,9 +145,9 @@ __attribute__ ((weak)) void SystemInitHook (void) { ---------------------------------------------------------------------------- */ int __low_level_init(void) -{ +{ /* Errata ERR050877 workaround. Enable FZ mode in the FPSCR. */ __set_FPSCR(__get_FPSCR() | FPSCR_FZ_MASK); - + return 1; } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/system_MCXE245.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/system_MCXE245.h index 2565e0120..52ed4083a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/system_MCXE245.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/system_MCXE245.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXE24x RM Rev.1 ** Version: rev. 1.0, 2025-02-21 -** Build: b250429 +** Build: b250530 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/MCXE246_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/MCXE246_COMMON.h index da1e2cd3a..33f876600 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/MCXE246_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/MCXE246_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXE24x RM Rev.1 ** Version: rev. 1.0, 2025-02-21 -** Build: b250424 +** Build: b250813 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE246 @@ -350,6 +350,8 @@ typedef enum IRQn { #define EWM_BASE_ADDRS { EWM_BASE } /** Array initializer of EWM peripheral base pointers */ #define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { WDOG_EWM_IRQn } /* FLEXIO - Peripheral instance base addresses */ /** Peripheral FLEXIO base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/MCXE246_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/MCXE246_features.h index fc59d2b09..cbf0e2c12 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/MCXE246_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/MCXE246_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2025-02-21 -** Build: b250610 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -181,6 +181,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (1) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (1) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* ACMP module features */ @@ -217,10 +221,8 @@ /* CRC module features */ -/* @brief If CRC has CRC register */ -#define FSL_FEATURE_CRC_HAS_CRC_REGISTER (0) -/* @brief CRC16 type of the peripheral. */ -#define FSL_FEATURE_CRC_CRC16_TYPE (0) +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) /* EDMA module features */ @@ -306,8 +308,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -336,6 +336,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLASH module features */ @@ -721,8 +723,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -765,6 +765,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MSCM module features */ @@ -929,8 +933,12 @@ #define FSL_FEATURE_RTC_HAS_PCR (0) /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) /* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ #define FSL_FEATURE_RTC_HAS_ERRATA_010716 (1) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/drivers/fsl_flexcan_soc.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/drivers/fsl_flexcan_soc.c index aeaa63a8e..0a0358b7d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/drivers/fsl_flexcan_soc.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/drivers/fsl_flexcan_soc.c @@ -32,7 +32,7 @@ void CAN2_Error_DriverIRQHandler(void); void CAN2_ORed_0_15_MB_DriverIRQHandler(void); void CAN2_ORed_16_31_MB_DriverIRQHandler(void); extern void FLEXCAN_DriverEventIRQHandler(uint32_t instance); -extern void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t startMbIdx, uint32_t endMbIdx, uint32_t type); +extern void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t startMbIdx, uint32_t endMbIdx); /******************************************************************************* * Code @@ -75,7 +75,7 @@ void CAN0_Wake_Up_DriverIRQHandler(void) void CAN0_ORed_0_15_MB_DriverIRQHandler(void) { /* Instance 0, MB 0-15 */ - FLEXCAN_DriverDataIRQHandler(0U, 0U, 15U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 15U); } /*! @@ -85,7 +85,7 @@ void CAN0_ORed_0_15_MB_DriverIRQHandler(void) void CAN0_ORed_16_31_MB_DriverIRQHandler(void) { /* Instance 0, MB 16-31 */ - FLEXCAN_DriverDataIRQHandler(0U, 16U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 16U, 31U); } /*! @@ -115,7 +115,7 @@ void CAN1_Error_DriverIRQHandler(void) void CAN1_ORed_0_15_MB_DriverIRQHandler(void) { /* Instance 1, MB 0-15 */ - FLEXCAN_DriverDataIRQHandler(1U, 0U, 15U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 15U); } /*! @@ -125,7 +125,7 @@ void CAN1_ORed_0_15_MB_DriverIRQHandler(void) void CAN1_ORed_16_31_MB_DriverIRQHandler(void) { /* Instance 1, MB 16-31 */ - FLEXCAN_DriverDataIRQHandler(1U, 16U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 16U, 31U); } /*! @@ -155,7 +155,7 @@ void CAN2_Error_DriverIRQHandler(void) void CAN2_ORed_0_15_MB_DriverIRQHandler(void) { /* Instance 2, MB 0-15 */ - FLEXCAN_DriverDataIRQHandler(2U, 0U, 15U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 15U); } /*! @@ -165,5 +165,5 @@ void CAN2_ORed_0_15_MB_DriverIRQHandler(void) void CAN2_ORed_16_31_MB_DriverIRQHandler(void) { /* Instance 2*, MB 16-31 */ - FLEXCAN_DriverDataIRQHandler(2U, 16U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 16U, 31U); } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/system_MCXE246.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/system_MCXE246.c index 2f16eff4c..5585de2cf 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/system_MCXE246.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/system_MCXE246.c @@ -11,7 +11,7 @@ ** ** Reference manual: MCXE24x RM Rev.1 ** Version: rev. 1.0, 2025-02-21 -** Build: b250424 +** Build: b250530 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -145,9 +145,9 @@ __attribute__ ((weak)) void SystemInitHook (void) { ---------------------------------------------------------------------------- */ int __low_level_init(void) -{ +{ /* Errata ERR050877 workaround. Enable FZ mode in the FPSCR. */ __set_FPSCR(__get_FPSCR() | FPSCR_FZ_MASK); - + return 1; } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/system_MCXE246.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/system_MCXE246.h index cf37e6b99..cbe93f20b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/system_MCXE246.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/system_MCXE246.h @@ -11,7 +11,7 @@ ** ** Reference manual: MCXE24x RM Rev.1 ** Version: rev. 1.0, 2025-02-21 -** Build: b250424 +** Build: b250530 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/MCXE247_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/MCXE247_COMMON.h index f63a95f6a..7c5baf211 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/MCXE247_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/MCXE247_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: MCXE24x RM Rev.1 ** Version: rev. 1.0, 2025-02-21 -** Build: b250417 +** Build: b250813 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE247 @@ -390,6 +390,8 @@ typedef enum IRQn { #define EWM_BASE_ADDRS { EWM_BASE } /** Array initializer of EWM peripheral base pointers */ #define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { WDOG_EWM_IRQn } /* FLEXIO - Peripheral instance base addresses */ /** Peripheral FLEXIO base address */ @@ -840,3 +842,4 @@ typedef enum IRQn { #endif /* MCXE247_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/MCXE247_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/MCXE247_features.h index 3e022a197..f38eb4a6b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/MCXE247_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/MCXE247_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2025-02-21 -** Build: b250526 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -181,6 +181,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (1) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (1) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (1) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* ACMP module features */ @@ -217,10 +221,8 @@ /* CRC module features */ -/* @brief If CRC has CRC register */ -#define FSL_FEATURE_CRC_HAS_CRC_REGISTER (0) -/* @brief CRC16 type of the peripheral. */ -#define FSL_FEATURE_CRC_CRC16_TYPE (0) +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) /* EDMA module features */ @@ -325,12 +327,14 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) +/* @brief ENET Has Extra Clock Gate (RW610). */ +#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -341,8 +345,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -371,6 +373,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLASH module features */ @@ -667,8 +671,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -699,14 +701,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (0) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* LMEM module features */ @@ -805,8 +811,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -849,6 +853,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MSCM module features */ @@ -1072,8 +1080,12 @@ #define FSL_FEATURE_RTC_HAS_PCR (0) /* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ #define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (0) /* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ #define FSL_FEATURE_RTC_HAS_ERRATA_010716 (1) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SCG module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/drivers/fsl_flexcan_soc.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/drivers/fsl_flexcan_soc.c index aeaa63a8e..0a0358b7d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/drivers/fsl_flexcan_soc.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/drivers/fsl_flexcan_soc.c @@ -32,7 +32,7 @@ void CAN2_Error_DriverIRQHandler(void); void CAN2_ORed_0_15_MB_DriverIRQHandler(void); void CAN2_ORed_16_31_MB_DriverIRQHandler(void); extern void FLEXCAN_DriverEventIRQHandler(uint32_t instance); -extern void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t startMbIdx, uint32_t endMbIdx, uint32_t type); +extern void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t startMbIdx, uint32_t endMbIdx); /******************************************************************************* * Code @@ -75,7 +75,7 @@ void CAN0_Wake_Up_DriverIRQHandler(void) void CAN0_ORed_0_15_MB_DriverIRQHandler(void) { /* Instance 0, MB 0-15 */ - FLEXCAN_DriverDataIRQHandler(0U, 0U, 15U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 15U); } /*! @@ -85,7 +85,7 @@ void CAN0_ORed_0_15_MB_DriverIRQHandler(void) void CAN0_ORed_16_31_MB_DriverIRQHandler(void) { /* Instance 0, MB 16-31 */ - FLEXCAN_DriverDataIRQHandler(0U, 16U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 16U, 31U); } /*! @@ -115,7 +115,7 @@ void CAN1_Error_DriverIRQHandler(void) void CAN1_ORed_0_15_MB_DriverIRQHandler(void) { /* Instance 1, MB 0-15 */ - FLEXCAN_DriverDataIRQHandler(1U, 0U, 15U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 15U); } /*! @@ -125,7 +125,7 @@ void CAN1_ORed_0_15_MB_DriverIRQHandler(void) void CAN1_ORed_16_31_MB_DriverIRQHandler(void) { /* Instance 1, MB 16-31 */ - FLEXCAN_DriverDataIRQHandler(1U, 16U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 16U, 31U); } /*! @@ -155,7 +155,7 @@ void CAN2_Error_DriverIRQHandler(void) void CAN2_ORed_0_15_MB_DriverIRQHandler(void) { /* Instance 2, MB 0-15 */ - FLEXCAN_DriverDataIRQHandler(2U, 0U, 15U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 15U); } /*! @@ -165,5 +165,5 @@ void CAN2_ORed_0_15_MB_DriverIRQHandler(void) void CAN2_ORed_16_31_MB_DriverIRQHandler(void) { /* Instance 2*, MB 16-31 */ - FLEXCAN_DriverDataIRQHandler(2U, 16U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 16U, 31U); } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/system_MCXE247.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/system_MCXE247.c index f6597c8b6..cefff7d5f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/system_MCXE247.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/system_MCXE247.c @@ -10,7 +10,7 @@ ** ** Reference manual: MCXE24x RM Rev.1 ** Version: rev. 1.0, 2025-02-21 -** Build: b250325 +** Build: b250530 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -45,6 +45,8 @@ #include #include "fsl_device_registers.h" + + /* ---------------------------------------------------------------------------- -- Core clock ---------------------------------------------------------------------------- */ @@ -142,9 +144,9 @@ __attribute__ ((weak)) void SystemInitHook (void) { ---------------------------------------------------------------------------- */ int __low_level_init(void) -{ +{ /* Errata ERR050877 workaround. Enable FZ mode in the FPSCR. */ __set_FPSCR(__get_FPSCR() | FPSCR_FZ_MASK); - + return 1; } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/system_MCXE247.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/system_MCXE247.h index 512c5fda7..8524591ce 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/system_MCXE247.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/system_MCXE247.h @@ -10,7 +10,7 @@ ** ** Reference manual: MCXE24x RM Rev.1 ** Version: rev. 1.0, 2025-02-21 -** Build: b250325 +** Build: b250530 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315.h index 6f90545e2..e2551d1d6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315.h @@ -3,14 +3,15 @@ ** Processors: MCXE315MLF ** MCXE315MPA ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE315 @@ -25,14 +26,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file MCXE315.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCXE315 * * CMSIS Peripheral Access Layer for MCXE315 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315_COMMON.h index c13d91439..1f084a0b0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315_COMMON.h @@ -3,14 +3,15 @@ ** Processors: MCXE315MLF ** MCXE315MPA ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250527 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250728 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE315 @@ -25,14 +26,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file MCXE315_COMMON.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCXE315 * * CMSIS Peripheral Access Layer for MCXE315 @@ -43,9 +46,9 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- @@ -121,8 +124,8 @@ typedef enum IRQn { SWT0_IRQn = 42, /**< Platform watchdog initial time-out */ Reserved59_IRQn = 43, /**< Reserved interrupt */ Reserved60_IRQn = 44, /**< Reserved interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - Reserved62_IRQn = 46, /**< Reserved interrupt */ + CTI_INT0_IRQn = 45, /**< CTI interrupt0 */ + CTI_INT1_IRQn = 46, /**< CTI interrupt1 */ Reserved63_IRQn = 47, /**< Reserved interrupt */ FLASH_0_IRQn = 48, /**< Program or erase operation is completed */ FLASH_1_IRQn = 49, /**< Main watchdog timeout interrupt */ @@ -245,7 +248,7 @@ typedef enum IRQn { Reserved201_IRQn = 185, /**< Reserved interrupt */ FCCU_0_IRQn = 189, /**< Interrupt request (ALARM state) */ FCCU_1_IRQn = 190, /**< Interrupt request (miscellaneous conditions) */ - Reserved207_IRQn = 191, /**< Reserved interrupt */ + STCU_IRQn = 191, /**< LBIST and MBIST IRQ */ MU0_B_TX_IRQn = 192, /**< ORed TX interrupt to MU-0 */ MU0_B_RX_IRQn = 193, /**< ORed RX interrupt to MU-0 */ MU0_B_IRQn = 194, /**< ORed general purpose interrupt request to MU-0 */ @@ -268,12 +271,12 @@ typedef enum IRQn { Reserved227_IRQn = 211, /**< Reserved interrupt */ PLL_LOL_IRQn = 212, /**< PLL LOL interrupt */ CORE_CLK_FAIL_IRQn = 213, /**< CORE_CLK_FAIL CMU reset reaction interrupt */ - Reserved230_IRQn = 214, /**< PLL2 LOL interrupt */ + Reserved230_IRQn = 214, /**< Reserved interrupt */ AIPS_PLAT_CLK_FAIL_IRQn = 215, /**< AIPS_PLAT_CLK_FAIL CMU reset reaction interrupt */ - Reserved232_IRQn = 216, /**< XRDC Error Interrupt */ + Reserved232_IRQn = 216, /**< Reserved interrupt */ HSE_B_CLK_FAIL_IRQn = 217, /**< HSE_B_CLK_FAIL CMU reset reaction interrupt */ Reserved234_IRQn = 218, /**< Reserved interrupt */ - Reserved235_IRQn = 219, /**< CM7_CORE_CLK_FAIL CMU reset reaction interrupt */ + Reserved235_IRQn = 219, /**< Reserved interrupt */ Reserved236_IRQn = 220, /**< Reserved interrupt */ Reserved237_IRQn = 221, /**< Reserved interrupt */ Reserved238_IRQn = 222, /**< Reserved interrupt */ @@ -929,6 +932,8 @@ typedef enum _xbic_slave_port #define DMA_BASE_ADDRS { EDMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { EDMA } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { DMATCD0_IRQn, DMATCD1_IRQn, DMATCD2_IRQn, DMATCD3_IRQn, DMATCD4_IRQn, DMATCD5_IRQn, DMATCD6_IRQn, DMATCD7_IRQn, DMATCD8_IRQn, DMATCD9_IRQn, DMATCD10_IRQn, DMATCD11_IRQn, DMATCD12_IRQn, DMATCD13_IRQn, DMATCD14_IRQn, DMATCD15_IRQn, DMATCD16_IRQn, DMATCD17_IRQn, DMATCD18_IRQn, DMATCD19_IRQn, DMATCD20_IRQn, DMATCD21_IRQn, DMATCD22_IRQn, DMATCD23_IRQn, DMATCD24_IRQn, DMATCD25_IRQn, DMATCD26_IRQn, DMATCD27_IRQn, DMATCD28_IRQn, DMATCD29_IRQn, DMATCD30_IRQn, DMATCD31_IRQn } } /* DMAMUX - Peripheral instance base addresses */ /** Peripheral DMAMUX_0 base address */ @@ -1313,6 +1318,16 @@ typedef enum _xbic_slave_port #define SIUL2_BASE_ADDRS { SIUL2_BASE } /** Array initializer of SIUL2 peripheral base pointers */ #define SIUL2_BASE_PTRS { SIUL2 } +/** Interrupt vectors for the SIUL2 peripheral type */ +#define SIUL2_IRQS { { SIUL2_0_IRQn, SIUL2_1_IRQn, SIUL2_2_IRQn, SIUL2_3_IRQn } } +/*! Maximum pins which share the same EIRQ request */ +#define SIUL2_MAX_PINS_PER_EIRQ (3U) +/*! Pins and EIRQ mapping array */ +#define SIUL2_EIRQ_PINS_MAP {{0, 64, 128}, {1, 65, 129}, {2, 66, 130}, {3, 67, 131}, {4, 16, 68}, {5, 69, -1}, {6, 70, 134}, {7, 71, 136}, \ + {32, 96, 137}, {33, 97, 138}, {34, 98, 139}, {35, 99, 140}, {36, 100, 141}, {37, 101, -1}, {40, 102, 143}, {41, 103, 144}, \ + {8, 72, -1}, {9, 73, -1}, {10, 74, -1}, {11, 75, -1}, {12, 76, -1}, {13, 77, -1}, {14, 78, -1}, {15, 79, -1}, \ + {42, 104, 113}, {43, 105, -1}, {44, 106, -1}, {45, 107, -1}, {46, 108, -1}, {47, 109, -1}, {48, 110, -1}, {49, 111, -1}} + /* STCU - Peripheral instance base addresses */ /** Peripheral STCU base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315_features.h index 5489352cf..f95fabb86 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/MCXE315_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2024-11-18 -** Build: b250520 +** Version: rev. 1.0, 2025-07-18 +** Build: b250829 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,10 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2024-11-18) +** - rev. 0.1 (2024-11-18) ** +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -63,6 +65,8 @@ #define FSL_FEATURE_SOC_PMC_COUNT (1) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SIUL2 availability on the SoC. */ +#define FSL_FEATURE_SOC_SIUL2_COUNT (1) /* @brief STM availability on the SoC. */ #define FSL_FEATURE_SOC_STM_COUNT (1) /* @brief TRGMUX availability on the SoC. */ @@ -205,7 +209,7 @@ /* @brief If channel clock controlled independently */ #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) /* @brief If 128 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) /* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (12) /* @brief Has register CH_CSR. */ @@ -266,6 +270,8 @@ #define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) /* @brief Number of DMA channels with asynchronous request capability. */ #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (12) +/* @brief TCD has clock control. */ +#define FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE (1) /* FLASH_C40 module features */ @@ -336,7 +342,7 @@ /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ @@ -359,11 +365,15 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 052403. */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_052403 (1) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (0) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -392,6 +402,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (0) /* INTM module features */ @@ -460,6 +472,8 @@ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) /* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) +/* @brief Has ERRATA050456. */ +#define FSL_FEATURE_LPSPI_HAS_ERRATA_050456 (1) /* LPUART module features */ @@ -493,12 +507,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ - (((x) == LPUART_0) ? (16) : \ - (((x) == LPUART_1) ? (16) : \ - (((x) == LPUART_2) ? (4) : \ - (((x) == LPUART_3) ? (4) : (-1))))) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -541,6 +549,14 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART_0) ? (16) : \ + (((x) == LPUART_1) ? (16) : \ + (((x) == LPUART_2) ? (4) : \ + (((x) == LPUART_3) ? (4) : (-1))))) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MCM module features */ @@ -655,12 +671,10 @@ /* @brief Lowest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) /* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (207) +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (223) /* PIT module features */ -/* @brief Has Real Time Interrupt. */ -#define FSL_FEATURE_PIT_HAS_RTI (1) /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ #define FSL_FEATURE_PIT_TIMER_COUNT (4) /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ @@ -671,6 +685,10 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has Real Time Interrupt. */ +#define FSL_FEATURE_PIT_HAS_RTI (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/drivers/CMakeLists.txt index adad73e40..9e3669e9c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/drivers/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/drivers/CMakeLists.txt @@ -4,6 +4,7 @@ include(../../MCXE31B/drivers/CMakeLists_clock.txt) include(../../MCXE31B/drivers/CMakeLists_dcm_gpr.txt) +include(../../MCXE31B/drivers/CMakeLists_dcm.txt) include(../../MCXE31B/drivers/CMakeLists_edma_soc.txt) include(../../MCXE31B/drivers/CMakeLists_memory.txt) include(../../MCXE31B/drivers/CMakeLists_siul2.txt) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/startup_MCXE315.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/startup_MCXE315.c index 4f291b6ab..292ac37ff 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/startup_MCXE315.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/startup_MCXE315.c @@ -2,7 +2,7 @@ //***************************************************************************** // MCXE315 startup code // -// Version : 120525 +// Version : 110825 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -130,8 +130,8 @@ WEAK void Reserved57_IRQHandler(void); WEAK void SWT0_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); -WEAK void Reserved61_IRQHandler(void); -WEAK void Reserved62_IRQHandler(void); +WEAK void CTI_INT0_IRQHandler(void); +WEAK void CTI_INT1_IRQHandler(void); WEAK void Reserved63_IRQHandler(void); WEAK void FLASH_0_IRQHandler(void); WEAK void FLASH_1_IRQHandler(void); @@ -276,7 +276,7 @@ WEAK void Reserved203_IRQHandler(void); WEAK void Reserved204_IRQHandler(void); WEAK void FCCU_0_IRQHandler(void); WEAK void FCCU_1_IRQHandler(void); -WEAK void Reserved207_IRQHandler(void); +WEAK void STCU_IRQHandler(void); WEAK void MU0_B_TX_IRQHandler(void); WEAK void MU0_B_RX_IRQHandler(void); WEAK void MU0_B_IRQHandler(void); @@ -355,8 +355,8 @@ void Reserved57_DriverIRQHandler(void) ALIAS(DefaultISR); void SWT0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved61_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved62_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved63_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_1_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -418,7 +418,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved123_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved124_DriverIRQHandler(void) ALIAS(DefaultISR); -void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) ALIAS(DefaultISR4); +void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end) ALIAS(DefaultISR3); void FLEXCAN_DriverEventIRQHandler(uint32_t instance) ALIAS(DefaultISR1); void Reserved135_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved136_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -485,7 +485,7 @@ void Reserved203_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved204_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_1_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved207_DriverIRQHandler(void) ALIAS(DefaultISR); +void STCU_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_TX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_RX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -601,6 +601,8 @@ void (* const g_pfnVectors[])(void) = { ResetISR, // The reset handler #elif defined (__ICCARM__) extern void (* const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); __attribute__ ((used, section(".intvec"))) void (* const __vector_table[])(void) = { (void(*)())(uint32_t)__StackTop, // The initial stack pointer @@ -675,8 +677,8 @@ void (* const __isr_vector[])(void) = { SWT0_IRQHandler, // 58 : Platform watchdog initial time-out Reserved59_IRQHandler, // 59 : Reserved interrupt Reserved60_IRQHandler, // 60 : Reserved interrupt - Reserved61_IRQHandler, // 61 : Reserved interrupt - Reserved62_IRQHandler, // 62 : Reserved interrupt + CTI_INT0_IRQHandler, // 61 : CTI interrupt0 + CTI_INT1_IRQHandler, // 62 : CTI interrupt1 Reserved63_IRQHandler, // 63 : Reserved interrupt FLASH_0_IRQHandler, // 64 : Program or erase operation is completed FLASH_1_IRQHandler, // 65 : Main watchdog timeout interrupt @@ -821,7 +823,7 @@ void (* const __isr_vector[])(void) = { Reserved204_IRQHandler, // 204: Reserved interrupt FCCU_0_IRQHandler, // 205: Interrupt request(ALARM state) FCCU_1_IRQHandler, // 206: Interrupt request(miscellaneous conditions) - Reserved207_IRQHandler, // 207: Reserved interrupt + STCU_IRQHandler, // 207: MBIST IRQ MU0_B_TX_IRQHandler, // 208: ORed TX interrupt to MU-0 MU0_B_RX_IRQHandler, // 209: ORed RX interrupt to MU-0 MU0_B_IRQHandler, // 210: ORed general purpose interrupt request to MU-0 @@ -1282,7 +1284,7 @@ WEAK_AV void DefaultISR1(uint32_t instance) } } -WEAK_AV void DefaultISR4(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) +WEAK_AV void DefaultISR3(uint32_t instance, uint32_t start, uint32_t end) { while(1) { @@ -1520,14 +1522,14 @@ WEAK void Reserved60_IRQHandler(void) Reserved60_DriverIRQHandler(); } -WEAK void Reserved61_IRQHandler(void) +WEAK void CTI_INT0_IRQHandler(void) { - Reserved61_DriverIRQHandler(); + CTI_INT0_DriverIRQHandler(); } -WEAK void Reserved62_IRQHandler(void) +WEAK void CTI_INT1_IRQHandler(void) { - Reserved62_DriverIRQHandler(); + CTI_INT1_DriverIRQHandler(); } WEAK void Reserved63_IRQHandler(void) @@ -1847,17 +1849,17 @@ WEAK void FlexCAN0_0_IRQHandler(void) WEAK void FlexCAN0_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U, 1U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U); } WEAK void FlexCAN0_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U); } WEAK void FlexCAN0_3_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U); } WEAK void FlexCAN1_0_IRQHandler(void) @@ -1867,12 +1869,12 @@ WEAK void FlexCAN1_0_IRQHandler(void) WEAK void FlexCAN1_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U); } WEAK void FlexCAN1_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U); } WEAK void FlexCAN2_0_IRQHandler(void) @@ -1882,12 +1884,12 @@ WEAK void FlexCAN2_0_IRQHandler(void) WEAK void FlexCAN2_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U); } WEAK void FlexCAN2_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U); } WEAK void Reserved135_IRQHandler(void) @@ -2251,9 +2253,9 @@ WEAK void FCCU_1_IRQHandler(void) FCCU_1_DriverIRQHandler(); } -WEAK void Reserved207_IRQHandler(void) +WEAK void STCU_IRQHandler(void) { - Reserved207_DriverIRQHandler(); + STCU_DriverIRQHandler(); } WEAK void MU0_B_TX_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/startup_MCXE315.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/startup_MCXE315.cpp index 4f291b6ab..292ac37ff 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/startup_MCXE315.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/startup_MCXE315.cpp @@ -2,7 +2,7 @@ //***************************************************************************** // MCXE315 startup code // -// Version : 120525 +// Version : 110825 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -130,8 +130,8 @@ WEAK void Reserved57_IRQHandler(void); WEAK void SWT0_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); -WEAK void Reserved61_IRQHandler(void); -WEAK void Reserved62_IRQHandler(void); +WEAK void CTI_INT0_IRQHandler(void); +WEAK void CTI_INT1_IRQHandler(void); WEAK void Reserved63_IRQHandler(void); WEAK void FLASH_0_IRQHandler(void); WEAK void FLASH_1_IRQHandler(void); @@ -276,7 +276,7 @@ WEAK void Reserved203_IRQHandler(void); WEAK void Reserved204_IRQHandler(void); WEAK void FCCU_0_IRQHandler(void); WEAK void FCCU_1_IRQHandler(void); -WEAK void Reserved207_IRQHandler(void); +WEAK void STCU_IRQHandler(void); WEAK void MU0_B_TX_IRQHandler(void); WEAK void MU0_B_RX_IRQHandler(void); WEAK void MU0_B_IRQHandler(void); @@ -355,8 +355,8 @@ void Reserved57_DriverIRQHandler(void) ALIAS(DefaultISR); void SWT0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved61_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved62_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved63_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_1_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -418,7 +418,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved123_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved124_DriverIRQHandler(void) ALIAS(DefaultISR); -void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) ALIAS(DefaultISR4); +void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end) ALIAS(DefaultISR3); void FLEXCAN_DriverEventIRQHandler(uint32_t instance) ALIAS(DefaultISR1); void Reserved135_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved136_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -485,7 +485,7 @@ void Reserved203_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved204_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_1_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved207_DriverIRQHandler(void) ALIAS(DefaultISR); +void STCU_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_TX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_RX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -601,6 +601,8 @@ void (* const g_pfnVectors[])(void) = { ResetISR, // The reset handler #elif defined (__ICCARM__) extern void (* const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); __attribute__ ((used, section(".intvec"))) void (* const __vector_table[])(void) = { (void(*)())(uint32_t)__StackTop, // The initial stack pointer @@ -675,8 +677,8 @@ void (* const __isr_vector[])(void) = { SWT0_IRQHandler, // 58 : Platform watchdog initial time-out Reserved59_IRQHandler, // 59 : Reserved interrupt Reserved60_IRQHandler, // 60 : Reserved interrupt - Reserved61_IRQHandler, // 61 : Reserved interrupt - Reserved62_IRQHandler, // 62 : Reserved interrupt + CTI_INT0_IRQHandler, // 61 : CTI interrupt0 + CTI_INT1_IRQHandler, // 62 : CTI interrupt1 Reserved63_IRQHandler, // 63 : Reserved interrupt FLASH_0_IRQHandler, // 64 : Program or erase operation is completed FLASH_1_IRQHandler, // 65 : Main watchdog timeout interrupt @@ -821,7 +823,7 @@ void (* const __isr_vector[])(void) = { Reserved204_IRQHandler, // 204: Reserved interrupt FCCU_0_IRQHandler, // 205: Interrupt request(ALARM state) FCCU_1_IRQHandler, // 206: Interrupt request(miscellaneous conditions) - Reserved207_IRQHandler, // 207: Reserved interrupt + STCU_IRQHandler, // 207: MBIST IRQ MU0_B_TX_IRQHandler, // 208: ORed TX interrupt to MU-0 MU0_B_RX_IRQHandler, // 209: ORed RX interrupt to MU-0 MU0_B_IRQHandler, // 210: ORed general purpose interrupt request to MU-0 @@ -1282,7 +1284,7 @@ WEAK_AV void DefaultISR1(uint32_t instance) } } -WEAK_AV void DefaultISR4(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) +WEAK_AV void DefaultISR3(uint32_t instance, uint32_t start, uint32_t end) { while(1) { @@ -1520,14 +1522,14 @@ WEAK void Reserved60_IRQHandler(void) Reserved60_DriverIRQHandler(); } -WEAK void Reserved61_IRQHandler(void) +WEAK void CTI_INT0_IRQHandler(void) { - Reserved61_DriverIRQHandler(); + CTI_INT0_DriverIRQHandler(); } -WEAK void Reserved62_IRQHandler(void) +WEAK void CTI_INT1_IRQHandler(void) { - Reserved62_DriverIRQHandler(); + CTI_INT1_DriverIRQHandler(); } WEAK void Reserved63_IRQHandler(void) @@ -1847,17 +1849,17 @@ WEAK void FlexCAN0_0_IRQHandler(void) WEAK void FlexCAN0_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U, 1U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U); } WEAK void FlexCAN0_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U); } WEAK void FlexCAN0_3_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U); } WEAK void FlexCAN1_0_IRQHandler(void) @@ -1867,12 +1869,12 @@ WEAK void FlexCAN1_0_IRQHandler(void) WEAK void FlexCAN1_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U); } WEAK void FlexCAN1_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U); } WEAK void FlexCAN2_0_IRQHandler(void) @@ -1882,12 +1884,12 @@ WEAK void FlexCAN2_0_IRQHandler(void) WEAK void FlexCAN2_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U); } WEAK void FlexCAN2_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U); } WEAK void Reserved135_IRQHandler(void) @@ -2251,9 +2253,9 @@ WEAK void FCCU_1_IRQHandler(void) FCCU_1_DriverIRQHandler(); } -WEAK void Reserved207_IRQHandler(void) +WEAK void STCU_IRQHandler(void) { - Reserved207_DriverIRQHandler(); + STCU_DriverIRQHandler(); } WEAK void MU0_B_TX_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/system_MCXE315.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/system_MCXE315.c index db944f75b..33e15746d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/system_MCXE315.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/system_MCXE315.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250811 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MCXE315 * @version 1.0 - * @date 2025-05-12 + * @date 2025-08-11 * @brief Device specific configuration file for MCXE315 (implementation file) * * Provides a system configuration function and a global variable that contains @@ -58,6 +60,15 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { +#if (DISABLE_WDOG) + if ((SWT_0->CR & SWT_CR_WEN_MASK) != 0U) + { + SWT_0->SR = 0xC520; + SWT_0->SR = 0xD928; + SWT_0->CR &= ~SWT_CR_WEN_MASK; + } +#endif /* (DISABLE_WDOG) */ + #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/system_MCXE315.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/system_MCXE315.h index 614c8b266..a07e0df57 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/system_MCXE315.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE315/system_MCXE315.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250811 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MCXE315 * @version 1.0 - * @date 2025-05-12 + * @date 2025-08-11 * @brief Device specific configuration file for MCXE315 (header file) * * Provides a system configuration function and a global variable that contains @@ -51,6 +53,10 @@ #define DEFAULT_SYSTEM_CLOCK 48000000U #define CLK_FIRC_CLOCK_FREQ 48000000U /**< FIRC clock frequency */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316.h index 05fe38118..3d67dac8c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316.h @@ -3,14 +3,15 @@ ** Processors: MCXE316MLF ** MCXE316MPA ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE316 @@ -25,14 +26,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file MCXE316.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCXE316 * * CMSIS Peripheral Access Layer for MCXE316 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316_COMMON.h index 5a610933c..3845eacb2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316_COMMON.h @@ -3,14 +3,15 @@ ** Processors: MCXE316MLF ** MCXE316MPA ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250527 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250728 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE316 @@ -25,14 +26,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file MCXE316_COMMON.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCXE316 * * CMSIS Peripheral Access Layer for MCXE316 @@ -43,9 +46,9 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- @@ -121,8 +124,8 @@ typedef enum IRQn { SWT0_IRQn = 42, /**< Platform watchdog initial time-out */ Reserved59_IRQn = 43, /**< Reserved interrupt */ Reserved60_IRQn = 44, /**< Reserved interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - Reserved62_IRQn = 46, /**< Reserved interrupt */ + CTI_INT0_IRQn = 45, /**< CTI interrupt0 */ + CTI_INT1_IRQn = 46, /**< CTI interrupt1 */ Reserved63_IRQn = 47, /**< Reserved interrupt */ FLASH_0_IRQn = 48, /**< Program or erase operation is completed */ FLASH_1_IRQn = 49, /**< Main watchdog timeout interrupt */ @@ -245,7 +248,7 @@ typedef enum IRQn { Reserved201_IRQn = 185, /**< Reserved interrupt */ FCCU_0_IRQn = 189, /**< Interrupt request (ALARM state) */ FCCU_1_IRQn = 190, /**< Interrupt request (miscellaneous conditions) */ - Reserved207_IRQn = 191, /**< Reserved interrupt */ + STCU_IRQn = 191, /**< LBIST and MBIST IRQ */ MU0_B_TX_IRQn = 192, /**< ORed TX interrupt to MU-0 */ MU0_B_RX_IRQn = 193, /**< ORed RX interrupt to MU-0 */ MU0_B_IRQn = 194, /**< ORed general purpose interrupt request to MU-0 */ @@ -268,12 +271,12 @@ typedef enum IRQn { Reserved227_IRQn = 211, /**< Reserved interrupt */ PLL_LOL_IRQn = 212, /**< PLL LOL interrupt */ CORE_CLK_FAIL_IRQn = 213, /**< CORE_CLK_FAIL CMU reset reaction interrupt */ - Reserved230_IRQn = 214, /**< PLL2 LOL interrupt */ + Reserved230_IRQn = 214, /**< Reserved interrupt */ AIPS_PLAT_CLK_FAIL_IRQn = 215, /**< AIPS_PLAT_CLK_FAIL CMU reset reaction interrupt */ - Reserved232_IRQn = 216, /**< XRDC Error Interrupt */ + Reserved232_IRQn = 216, /**< Reserved interrupt */ HSE_B_CLK_FAIL_IRQn = 217, /**< HSE_B_CLK_FAIL CMU reset reaction interrupt */ Reserved234_IRQn = 218, /**< Reserved interrupt */ - Reserved235_IRQn = 219, /**< CM7_CORE_CLK_FAIL CMU reset reaction interrupt */ + Reserved235_IRQn = 219, /**< Reserved interrupt */ Reserved236_IRQn = 220, /**< Reserved interrupt */ Reserved237_IRQn = 221, /**< Reserved interrupt */ Reserved238_IRQn = 222, /**< Reserved interrupt */ @@ -929,6 +932,8 @@ typedef enum _xbic_slave_port #define DMA_BASE_ADDRS { EDMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { EDMA } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { DMATCD0_IRQn, DMATCD1_IRQn, DMATCD2_IRQn, DMATCD3_IRQn, DMATCD4_IRQn, DMATCD5_IRQn, DMATCD6_IRQn, DMATCD7_IRQn, DMATCD8_IRQn, DMATCD9_IRQn, DMATCD10_IRQn, DMATCD11_IRQn, DMATCD12_IRQn, DMATCD13_IRQn, DMATCD14_IRQn, DMATCD15_IRQn, DMATCD16_IRQn, DMATCD17_IRQn, DMATCD18_IRQn, DMATCD19_IRQn, DMATCD20_IRQn, DMATCD21_IRQn, DMATCD22_IRQn, DMATCD23_IRQn, DMATCD24_IRQn, DMATCD25_IRQn, DMATCD26_IRQn, DMATCD27_IRQn, DMATCD28_IRQn, DMATCD29_IRQn, DMATCD30_IRQn, DMATCD31_IRQn } } /* DMAMUX - Peripheral instance base addresses */ /** Peripheral DMAMUX_0 base address */ @@ -1313,6 +1318,16 @@ typedef enum _xbic_slave_port #define SIUL2_BASE_ADDRS { SIUL2_BASE } /** Array initializer of SIUL2 peripheral base pointers */ #define SIUL2_BASE_PTRS { SIUL2 } +/** Interrupt vectors for the SIUL2 peripheral type */ +#define SIUL2_IRQS { { SIUL2_0_IRQn, SIUL2_1_IRQn, SIUL2_2_IRQn, SIUL2_3_IRQn } } +/*! Maximum pins which share the same EIRQ request */ +#define SIUL2_MAX_PINS_PER_EIRQ (3U) +/*! Pins and EIRQ mapping array */ +#define SIUL2_EIRQ_PINS_MAP {{0, 64, 128}, {1, 65, 129}, {2, 66, 130}, {3, 67, 131}, {4, 16, 68}, {5, 69, -1}, {6, 70, 134}, {7, 71, 136}, \ + {32, 96, 137}, {33, 97, 138}, {34, 98, 139}, {35, 99, 140}, {36, 100, 141}, {37, 101, -1}, {40, 102, 143}, {41, 103, 144}, \ + {8, 72, -1}, {9, 73, -1}, {10, 74, -1}, {11, 75, -1}, {12, 76, -1}, {13, 77, -1}, {14, 78, -1}, {15, 79, -1}, \ + {42, 104, 113}, {43, 105, -1}, {44, 106, -1}, {45, 107, -1}, {46, 108, -1}, {47, 109, -1}, {48, 110, -1}, {49, 111, -1}} + /* STCU - Peripheral instance base addresses */ /** Peripheral STCU base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316_features.h index 86dde061f..8a160d4b1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/MCXE316_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2024-11-18 -** Build: b250520 +** Version: rev. 1.0, 2025-07-18 +** Build: b250829 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,10 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2024-11-18) +** - rev. 0.1 (2024-11-18) ** +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -63,6 +65,8 @@ #define FSL_FEATURE_SOC_PMC_COUNT (1) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SIUL2 availability on the SoC. */ +#define FSL_FEATURE_SOC_SIUL2_COUNT (1) /* @brief STM availability on the SoC. */ #define FSL_FEATURE_SOC_STM_COUNT (1) /* @brief TRGMUX availability on the SoC. */ @@ -205,7 +209,7 @@ /* @brief If channel clock controlled independently */ #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) /* @brief If 128 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) /* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (12) /* @brief Has register CH_CSR. */ @@ -266,6 +270,8 @@ #define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) /* @brief Number of DMA channels with asynchronous request capability. */ #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (12) +/* @brief TCD has clock control. */ +#define FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE (1) /* FLASH_C40 module features */ @@ -336,7 +342,7 @@ /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ @@ -359,11 +365,15 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 052403. */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_052403 (1) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (0) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -392,6 +402,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (0) /* INTM module features */ @@ -460,6 +472,8 @@ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) /* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) +/* @brief Has ERRATA050456. */ +#define FSL_FEATURE_LPSPI_HAS_ERRATA_050456 (1) /* LPUART module features */ @@ -493,12 +507,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ - (((x) == LPUART_0) ? (16) : \ - (((x) == LPUART_1) ? (16) : \ - (((x) == LPUART_2) ? (4) : \ - (((x) == LPUART_3) ? (4) : (-1))))) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -541,6 +549,14 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART_0) ? (16) : \ + (((x) == LPUART_1) ? (16) : \ + (((x) == LPUART_2) ? (4) : \ + (((x) == LPUART_3) ? (4) : (-1))))) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MCM module features */ @@ -655,12 +671,10 @@ /* @brief Lowest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) /* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (207) +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (223) /* PIT module features */ -/* @brief Has Real Time Interrupt. */ -#define FSL_FEATURE_PIT_HAS_RTI (1) /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ #define FSL_FEATURE_PIT_TIMER_COUNT (4) /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ @@ -671,6 +685,10 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has Real Time Interrupt. */ +#define FSL_FEATURE_PIT_HAS_RTI (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/drivers/CMakeLists.txt index adad73e40..9e3669e9c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/drivers/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/drivers/CMakeLists.txt @@ -4,6 +4,7 @@ include(../../MCXE31B/drivers/CMakeLists_clock.txt) include(../../MCXE31B/drivers/CMakeLists_dcm_gpr.txt) +include(../../MCXE31B/drivers/CMakeLists_dcm.txt) include(../../MCXE31B/drivers/CMakeLists_edma_soc.txt) include(../../MCXE31B/drivers/CMakeLists_memory.txt) include(../../MCXE31B/drivers/CMakeLists_siul2.txt) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/startup_MCXE316.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/startup_MCXE316.c index 7ce1d87f3..7c607e0f4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/startup_MCXE316.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/startup_MCXE316.c @@ -2,7 +2,7 @@ //***************************************************************************** // MCXE316 startup code // -// Version : 120525 +// Version : 110825 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -130,8 +130,8 @@ WEAK void Reserved57_IRQHandler(void); WEAK void SWT0_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); -WEAK void Reserved61_IRQHandler(void); -WEAK void Reserved62_IRQHandler(void); +WEAK void CTI_INT0_IRQHandler(void); +WEAK void CTI_INT1_IRQHandler(void); WEAK void Reserved63_IRQHandler(void); WEAK void FLASH_0_IRQHandler(void); WEAK void FLASH_1_IRQHandler(void); @@ -276,7 +276,7 @@ WEAK void Reserved203_IRQHandler(void); WEAK void Reserved204_IRQHandler(void); WEAK void FCCU_0_IRQHandler(void); WEAK void FCCU_1_IRQHandler(void); -WEAK void Reserved207_IRQHandler(void); +WEAK void STCU_IRQHandler(void); WEAK void MU0_B_TX_IRQHandler(void); WEAK void MU0_B_RX_IRQHandler(void); WEAK void MU0_B_IRQHandler(void); @@ -355,8 +355,8 @@ void Reserved57_DriverIRQHandler(void) ALIAS(DefaultISR); void SWT0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved61_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved62_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved63_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_1_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -418,7 +418,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved123_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved124_DriverIRQHandler(void) ALIAS(DefaultISR); -void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) ALIAS(DefaultISR4); +void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end) ALIAS(DefaultISR3); void FLEXCAN_DriverEventIRQHandler(uint32_t instance) ALIAS(DefaultISR1); void Reserved135_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved136_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -485,7 +485,7 @@ void Reserved203_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved204_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_1_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved207_DriverIRQHandler(void) ALIAS(DefaultISR); +void STCU_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_TX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_RX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -601,6 +601,8 @@ void (* const g_pfnVectors[])(void) = { ResetISR, // The reset handler #elif defined (__ICCARM__) extern void (* const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); __attribute__ ((used, section(".intvec"))) void (* const __vector_table[])(void) = { (void(*)())(uint32_t)__StackTop, // The initial stack pointer @@ -675,8 +677,8 @@ void (* const __isr_vector[])(void) = { SWT0_IRQHandler, // 58 : Platform watchdog initial time-out Reserved59_IRQHandler, // 59 : Reserved interrupt Reserved60_IRQHandler, // 60 : Reserved interrupt - Reserved61_IRQHandler, // 61 : Reserved interrupt - Reserved62_IRQHandler, // 62 : Reserved interrupt + CTI_INT0_IRQHandler, // 61 : CTI interrupt0 + CTI_INT1_IRQHandler, // 62 : CTI interrupt1 Reserved63_IRQHandler, // 63 : Reserved interrupt FLASH_0_IRQHandler, // 64 : Program or erase operation is completed FLASH_1_IRQHandler, // 65 : Main watchdog timeout interrupt @@ -821,7 +823,7 @@ void (* const __isr_vector[])(void) = { Reserved204_IRQHandler, // 204: Reserved interrupt FCCU_0_IRQHandler, // 205: Interrupt request(ALARM state) FCCU_1_IRQHandler, // 206: Interrupt request(miscellaneous conditions) - Reserved207_IRQHandler, // 207: Reserved interrupt + STCU_IRQHandler, // 207: MBIST IRQ MU0_B_TX_IRQHandler, // 208: ORed TX interrupt to MU-0 MU0_B_RX_IRQHandler, // 209: ORed RX interrupt to MU-0 MU0_B_IRQHandler, // 210: ORed general purpose interrupt request to MU-0 @@ -1282,7 +1284,7 @@ WEAK_AV void DefaultISR1(uint32_t instance) } } -WEAK_AV void DefaultISR4(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) +WEAK_AV void DefaultISR3(uint32_t instance, uint32_t start, uint32_t end) { while(1) { @@ -1520,14 +1522,14 @@ WEAK void Reserved60_IRQHandler(void) Reserved60_DriverIRQHandler(); } -WEAK void Reserved61_IRQHandler(void) +WEAK void CTI_INT0_IRQHandler(void) { - Reserved61_DriverIRQHandler(); + CTI_INT0_DriverIRQHandler(); } -WEAK void Reserved62_IRQHandler(void) +WEAK void CTI_INT1_IRQHandler(void) { - Reserved62_DriverIRQHandler(); + CTI_INT1_DriverIRQHandler(); } WEAK void Reserved63_IRQHandler(void) @@ -1847,17 +1849,17 @@ WEAK void FlexCAN0_0_IRQHandler(void) WEAK void FlexCAN0_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U, 1U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U); } WEAK void FlexCAN0_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U); } WEAK void FlexCAN0_3_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U); } WEAK void FlexCAN1_0_IRQHandler(void) @@ -1867,12 +1869,12 @@ WEAK void FlexCAN1_0_IRQHandler(void) WEAK void FlexCAN1_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U); } WEAK void FlexCAN1_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U); } WEAK void FlexCAN2_0_IRQHandler(void) @@ -1882,12 +1884,12 @@ WEAK void FlexCAN2_0_IRQHandler(void) WEAK void FlexCAN2_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U); } WEAK void FlexCAN2_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U); } WEAK void Reserved135_IRQHandler(void) @@ -2251,9 +2253,9 @@ WEAK void FCCU_1_IRQHandler(void) FCCU_1_DriverIRQHandler(); } -WEAK void Reserved207_IRQHandler(void) +WEAK void STCU_IRQHandler(void) { - Reserved207_DriverIRQHandler(); + STCU_DriverIRQHandler(); } WEAK void MU0_B_TX_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/startup_MCXE316.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/startup_MCXE316.cpp index 7ce1d87f3..7c607e0f4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/startup_MCXE316.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/startup_MCXE316.cpp @@ -2,7 +2,7 @@ //***************************************************************************** // MCXE316 startup code // -// Version : 120525 +// Version : 110825 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -130,8 +130,8 @@ WEAK void Reserved57_IRQHandler(void); WEAK void SWT0_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); -WEAK void Reserved61_IRQHandler(void); -WEAK void Reserved62_IRQHandler(void); +WEAK void CTI_INT0_IRQHandler(void); +WEAK void CTI_INT1_IRQHandler(void); WEAK void Reserved63_IRQHandler(void); WEAK void FLASH_0_IRQHandler(void); WEAK void FLASH_1_IRQHandler(void); @@ -276,7 +276,7 @@ WEAK void Reserved203_IRQHandler(void); WEAK void Reserved204_IRQHandler(void); WEAK void FCCU_0_IRQHandler(void); WEAK void FCCU_1_IRQHandler(void); -WEAK void Reserved207_IRQHandler(void); +WEAK void STCU_IRQHandler(void); WEAK void MU0_B_TX_IRQHandler(void); WEAK void MU0_B_RX_IRQHandler(void); WEAK void MU0_B_IRQHandler(void); @@ -355,8 +355,8 @@ void Reserved57_DriverIRQHandler(void) ALIAS(DefaultISR); void SWT0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved61_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved62_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved63_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_1_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -418,7 +418,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved123_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved124_DriverIRQHandler(void) ALIAS(DefaultISR); -void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) ALIAS(DefaultISR4); +void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end) ALIAS(DefaultISR3); void FLEXCAN_DriverEventIRQHandler(uint32_t instance) ALIAS(DefaultISR1); void Reserved135_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved136_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -485,7 +485,7 @@ void Reserved203_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved204_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_1_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved207_DriverIRQHandler(void) ALIAS(DefaultISR); +void STCU_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_TX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_RX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -601,6 +601,8 @@ void (* const g_pfnVectors[])(void) = { ResetISR, // The reset handler #elif defined (__ICCARM__) extern void (* const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); __attribute__ ((used, section(".intvec"))) void (* const __vector_table[])(void) = { (void(*)())(uint32_t)__StackTop, // The initial stack pointer @@ -675,8 +677,8 @@ void (* const __isr_vector[])(void) = { SWT0_IRQHandler, // 58 : Platform watchdog initial time-out Reserved59_IRQHandler, // 59 : Reserved interrupt Reserved60_IRQHandler, // 60 : Reserved interrupt - Reserved61_IRQHandler, // 61 : Reserved interrupt - Reserved62_IRQHandler, // 62 : Reserved interrupt + CTI_INT0_IRQHandler, // 61 : CTI interrupt0 + CTI_INT1_IRQHandler, // 62 : CTI interrupt1 Reserved63_IRQHandler, // 63 : Reserved interrupt FLASH_0_IRQHandler, // 64 : Program or erase operation is completed FLASH_1_IRQHandler, // 65 : Main watchdog timeout interrupt @@ -821,7 +823,7 @@ void (* const __isr_vector[])(void) = { Reserved204_IRQHandler, // 204: Reserved interrupt FCCU_0_IRQHandler, // 205: Interrupt request(ALARM state) FCCU_1_IRQHandler, // 206: Interrupt request(miscellaneous conditions) - Reserved207_IRQHandler, // 207: Reserved interrupt + STCU_IRQHandler, // 207: MBIST IRQ MU0_B_TX_IRQHandler, // 208: ORed TX interrupt to MU-0 MU0_B_RX_IRQHandler, // 209: ORed RX interrupt to MU-0 MU0_B_IRQHandler, // 210: ORed general purpose interrupt request to MU-0 @@ -1282,7 +1284,7 @@ WEAK_AV void DefaultISR1(uint32_t instance) } } -WEAK_AV void DefaultISR4(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) +WEAK_AV void DefaultISR3(uint32_t instance, uint32_t start, uint32_t end) { while(1) { @@ -1520,14 +1522,14 @@ WEAK void Reserved60_IRQHandler(void) Reserved60_DriverIRQHandler(); } -WEAK void Reserved61_IRQHandler(void) +WEAK void CTI_INT0_IRQHandler(void) { - Reserved61_DriverIRQHandler(); + CTI_INT0_DriverIRQHandler(); } -WEAK void Reserved62_IRQHandler(void) +WEAK void CTI_INT1_IRQHandler(void) { - Reserved62_DriverIRQHandler(); + CTI_INT1_DriverIRQHandler(); } WEAK void Reserved63_IRQHandler(void) @@ -1847,17 +1849,17 @@ WEAK void FlexCAN0_0_IRQHandler(void) WEAK void FlexCAN0_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U, 1U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U); } WEAK void FlexCAN0_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U); } WEAK void FlexCAN0_3_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U); } WEAK void FlexCAN1_0_IRQHandler(void) @@ -1867,12 +1869,12 @@ WEAK void FlexCAN1_0_IRQHandler(void) WEAK void FlexCAN1_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U); } WEAK void FlexCAN1_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U); } WEAK void FlexCAN2_0_IRQHandler(void) @@ -1882,12 +1884,12 @@ WEAK void FlexCAN2_0_IRQHandler(void) WEAK void FlexCAN2_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U); } WEAK void FlexCAN2_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U); } WEAK void Reserved135_IRQHandler(void) @@ -2251,9 +2253,9 @@ WEAK void FCCU_1_IRQHandler(void) FCCU_1_DriverIRQHandler(); } -WEAK void Reserved207_IRQHandler(void) +WEAK void STCU_IRQHandler(void) { - Reserved207_DriverIRQHandler(); + STCU_DriverIRQHandler(); } WEAK void MU0_B_TX_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/system_MCXE316.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/system_MCXE316.c index 2e2eb7a21..dbebafc0e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/system_MCXE316.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/system_MCXE316.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250811 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MCXE316 * @version 1.0 - * @date 2025-05-12 + * @date 2025-08-11 * @brief Device specific configuration file for MCXE316 (implementation file) * * Provides a system configuration function and a global variable that contains @@ -58,6 +60,15 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { +#if (DISABLE_WDOG) + if ((SWT_0->CR & SWT_CR_WEN_MASK) != 0U) + { + SWT_0->SR = 0xC520; + SWT_0->SR = 0xD928; + SWT_0->CR &= ~SWT_CR_WEN_MASK; + } +#endif /* (DISABLE_WDOG) */ + #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/system_MCXE316.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/system_MCXE316.h index df72248b9..033b22038 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/system_MCXE316.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE316/system_MCXE316.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250811 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MCXE316 * @version 1.0 - * @date 2025-05-12 + * @date 2025-08-11 * @brief Device specific configuration file for MCXE316 (header file) * * Provides a system configuration function and a global variable that contains @@ -51,6 +53,10 @@ #define DEFAULT_SYSTEM_CLOCK 48000000U #define CLK_FIRC_CLOCK_FREQ 48000000U /**< FIRC clock frequency */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317.h index 59153ef41..ee95f566f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317.h @@ -3,14 +3,15 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE317 @@ -25,14 +26,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file MCXE317.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCXE317 * * CMSIS Peripheral Access Layer for MCXE317 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317_COMMON.h index 76ab71d28..67fb9f9e2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317_COMMON.h @@ -3,14 +3,15 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250527 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250728 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE317 @@ -25,14 +26,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file MCXE317_COMMON.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCXE317 * * CMSIS Peripheral Access Layer for MCXE317 @@ -43,9 +46,9 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- @@ -121,8 +124,8 @@ typedef enum IRQn { SWT0_IRQn = 42, /**< Platform watchdog initial time-out */ Reserved59_IRQn = 43, /**< Reserved interrupt */ Reserved60_IRQn = 44, /**< Reserved interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - Reserved62_IRQn = 46, /**< Reserved interrupt */ + CTI_INT0_IRQn = 45, /**< CTI interrupt0 */ + CTI_INT1_IRQn = 46, /**< CTI interrupt1 */ Reserved63_IRQn = 47, /**< Reserved interrupt */ FLASH_0_IRQn = 48, /**< Program or erase operation is completed */ FLASH_1_IRQn = 49, /**< Main watchdog timeout interrupt */ @@ -245,7 +248,7 @@ typedef enum IRQn { Reserved201_IRQn = 185, /**< Reserved interrupt */ FCCU_0_IRQn = 189, /**< Interrupt request (ALARM state) */ FCCU_1_IRQn = 190, /**< Interrupt request (miscellaneous conditions) */ - Reserved207_IRQn = 191, /**< Reserved interrupt */ + STCU_IRQn = 191, /**< LBIST and MBIST IRQ */ MU0_B_TX_IRQn = 192, /**< ORed TX interrupt to MU-0 */ MU0_B_RX_IRQn = 193, /**< ORed RX interrupt to MU-0 */ MU0_B_IRQn = 194, /**< ORed general purpose interrupt request to MU-0 */ @@ -268,12 +271,12 @@ typedef enum IRQn { Reserved227_IRQn = 211, /**< Reserved interrupt */ PLL_LOL_IRQn = 212, /**< PLL LOL interrupt */ CORE_CLK_FAIL_IRQn = 213, /**< CORE_CLK_FAIL CMU reset reaction interrupt */ - Reserved230_IRQn = 214, /**< PLL2 LOL interrupt */ + Reserved230_IRQn = 214, /**< Reserved interrupt */ AIPS_PLAT_CLK_FAIL_IRQn = 215, /**< AIPS_PLAT_CLK_FAIL CMU reset reaction interrupt */ - Reserved232_IRQn = 216, /**< XRDC Error Interrupt */ + Reserved232_IRQn = 216, /**< Reserved interrupt */ HSE_B_CLK_FAIL_IRQn = 217, /**< HSE_B_CLK_FAIL CMU reset reaction interrupt */ Reserved234_IRQn = 218, /**< Reserved interrupt */ - Reserved235_IRQn = 219, /**< CM7_CORE_CLK_FAIL CMU reset reaction interrupt */ + Reserved235_IRQn = 219, /**< Reserved interrupt */ Reserved236_IRQn = 220, /**< Reserved interrupt */ Reserved237_IRQn = 221, /**< Reserved interrupt */ Reserved238_IRQn = 222, /**< Reserved interrupt */ @@ -954,6 +957,8 @@ typedef enum _xbic_slave_port #define DMA_BASE_ADDRS { EDMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { EDMA } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { DMATCD0_IRQn, DMATCD1_IRQn, DMATCD2_IRQn, DMATCD3_IRQn, DMATCD4_IRQn, DMATCD5_IRQn, DMATCD6_IRQn, DMATCD7_IRQn, DMATCD8_IRQn, DMATCD9_IRQn, DMATCD10_IRQn, DMATCD11_IRQn, DMATCD12_IRQn, DMATCD13_IRQn, DMATCD14_IRQn, DMATCD15_IRQn, DMATCD16_IRQn, DMATCD17_IRQn, DMATCD18_IRQn, DMATCD19_IRQn, DMATCD20_IRQn, DMATCD21_IRQn, DMATCD22_IRQn, DMATCD23_IRQn, DMATCD24_IRQn, DMATCD25_IRQn, DMATCD26_IRQn, DMATCD27_IRQn, DMATCD28_IRQn, DMATCD29_IRQn, DMATCD30_IRQn, DMATCD31_IRQn } } /* DMAMUX - Peripheral instance base addresses */ /** Peripheral DMAMUX_0 base address */ @@ -1358,6 +1363,16 @@ typedef enum _xbic_slave_port #define SIUL2_BASE_ADDRS { SIUL2_BASE } /** Array initializer of SIUL2 peripheral base pointers */ #define SIUL2_BASE_PTRS { SIUL2 } +/** Interrupt vectors for the SIUL2 peripheral type */ +#define SIUL2_IRQS { { SIUL2_0_IRQn, SIUL2_1_IRQn, SIUL2_2_IRQn, SIUL2_3_IRQn } } +/*! Maximum pins which share the same EIRQ request */ +#define SIUL2_MAX_PINS_PER_EIRQ (4U) +/*! Pins and EIRQ mapping array */ +#define SIUL2_EIRQ_PINS_MAP {{0, 18, 64, 128}, {1, 19, 65, 129}, {2, 20, 66, 130}, {3, 21, 67, 131}, {4, 16, 68, 132}, {5, 25, 69, 133}, {6, 28, 70, 134}, {7, 30, 71, 136}, \ + {32, 53, 96, 137}, {33, 54, 97, 138}, {34, 55, 98, 139}, {35, 56, 99, 140}, {36, 57, 100, 141}, {37, 58, 101, 142}, {40, 60, 102, 143}, {41, 103, 144, -1}, \ + {8, 72, 84, -1}, {9, 73, 85, -1}, {10, 74, 87, -1}, {11, 75, 88, -1}, {12, 76, 89, -1}, {13, 77, 90, -1}, {14, 78, 91, -1}, {15, 79, 93, -1}, \ + {42, 104, 113, -1}, {43, 105, 116, -1}, {44, 106, 117, -1}, {45, 107, 118, -1}, {46, 108, 119, -1}, {47, 109, 120, -1}, {48, 110, 123, -1}, {49, 111, 124, -1}} + /* STCU - Peripheral instance base addresses */ /** Peripheral STCU base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317_features.h index 5c070520e..0e651753e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/MCXE317_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2024-11-18 -** Build: b250520 +** Version: rev. 1.0, 2025-07-18 +** Build: b250829 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,10 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2024-11-18) +** - rev. 0.1 (2024-11-18) ** +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -63,6 +65,8 @@ #define FSL_FEATURE_SOC_PMC_COUNT (1) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SIUL2 availability on the SoC. */ +#define FSL_FEATURE_SOC_SIUL2_COUNT (1) /* @brief STM availability on the SoC. */ #define FSL_FEATURE_SOC_STM_COUNT (1) /* @brief TRGMUX availability on the SoC. */ @@ -205,7 +209,7 @@ /* @brief If channel clock controlled independently */ #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) /* @brief If 128 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) /* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (12) /* @brief Has register CH_CSR. */ @@ -266,6 +270,8 @@ #define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) /* @brief Number of DMA channels with asynchronous request capability. */ #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (12) +/* @brief TCD has clock control. */ +#define FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE (1) /* FLASH_C40 module features */ @@ -345,7 +351,7 @@ /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) /* @brief Has more than 64 MBs. */ -#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) /* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ @@ -368,11 +374,15 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 052403. */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_052403 (1) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (0) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -401,6 +411,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (0) /* INTM module features */ @@ -469,6 +481,8 @@ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) /* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) +/* @brief Has ERRATA050456. */ +#define FSL_FEATURE_LPSPI_HAS_ERRATA_050456 (1) /* LPUART module features */ @@ -502,8 +516,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -546,6 +558,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MCM module features */ @@ -660,12 +676,10 @@ /* @brief Lowest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) /* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (207) +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (223) /* PIT module features */ -/* @brief Has Real Time Interrupt. */ -#define FSL_FEATURE_PIT_HAS_RTI (1) /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ #define FSL_FEATURE_PIT_TIMER_COUNT (4) /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ @@ -676,6 +690,10 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has Real Time Interrupt. */ +#define FSL_FEATURE_PIT_HAS_RTI (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/drivers/CMakeLists.txt index adad73e40..9e3669e9c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/drivers/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/drivers/CMakeLists.txt @@ -4,6 +4,7 @@ include(../../MCXE31B/drivers/CMakeLists_clock.txt) include(../../MCXE31B/drivers/CMakeLists_dcm_gpr.txt) +include(../../MCXE31B/drivers/CMakeLists_dcm.txt) include(../../MCXE31B/drivers/CMakeLists_edma_soc.txt) include(../../MCXE31B/drivers/CMakeLists_memory.txt) include(../../MCXE31B/drivers/CMakeLists_siul2.txt) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/startup_MCXE317.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/startup_MCXE317.c index 1f20f1403..b669eb8c2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/startup_MCXE317.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/startup_MCXE317.c @@ -2,7 +2,7 @@ //***************************************************************************** // MCXE317 startup code // -// Version : 120525 +// Version : 110825 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -130,8 +130,8 @@ WEAK void Reserved57_IRQHandler(void); WEAK void SWT0_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); -WEAK void Reserved61_IRQHandler(void); -WEAK void Reserved62_IRQHandler(void); +WEAK void CTI_INT0_IRQHandler(void); +WEAK void CTI_INT1_IRQHandler(void); WEAK void Reserved63_IRQHandler(void); WEAK void FLASH_0_IRQHandler(void); WEAK void FLASH_1_IRQHandler(void); @@ -276,7 +276,7 @@ WEAK void Reserved203_IRQHandler(void); WEAK void Reserved204_IRQHandler(void); WEAK void FCCU_0_IRQHandler(void); WEAK void FCCU_1_IRQHandler(void); -WEAK void Reserved207_IRQHandler(void); +WEAK void STCU_IRQHandler(void); WEAK void MU0_B_TX_IRQHandler(void); WEAK void MU0_B_RX_IRQHandler(void); WEAK void MU0_B_IRQHandler(void); @@ -355,8 +355,8 @@ void Reserved57_DriverIRQHandler(void) ALIAS(DefaultISR); void SWT0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved61_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved62_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved63_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_1_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -418,7 +418,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved123_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved124_DriverIRQHandler(void) ALIAS(DefaultISR); -void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) ALIAS(DefaultISR4); +void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end) ALIAS(DefaultISR3); void FLEXCAN_DriverEventIRQHandler(uint32_t instance) ALIAS(DefaultISR1); void Reserved141_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved142_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -475,7 +475,7 @@ void Reserved203_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved204_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_1_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved207_DriverIRQHandler(void) ALIAS(DefaultISR); +void STCU_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_TX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_RX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -591,6 +591,8 @@ void (* const g_pfnVectors[])(void) = { ResetISR, // The reset handler #elif defined (__ICCARM__) extern void (* const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); __attribute__ ((used, section(".intvec"))) void (* const __vector_table[])(void) = { (void(*)())(uint32_t)__StackTop, // The initial stack pointer @@ -665,8 +667,8 @@ void (* const __isr_vector[])(void) = { SWT0_IRQHandler, // 58 : Platform watchdog initial time-out Reserved59_IRQHandler, // 59 : Reserved interrupt Reserved60_IRQHandler, // 60 : Reserved interrupt - Reserved61_IRQHandler, // 61 : Reserved interrupt - Reserved62_IRQHandler, // 62 : Reserved interrupt + CTI_INT0_IRQHandler, // 61 : CTI interrupt0 + CTI_INT1_IRQHandler, // 62 : CTI interrupt1 Reserved63_IRQHandler, // 63 : Reserved interrupt FLASH_0_IRQHandler, // 64 : Program or erase operation is completed FLASH_1_IRQHandler, // 65 : Main watchdog timeout interrupt @@ -811,7 +813,7 @@ void (* const __isr_vector[])(void) = { Reserved204_IRQHandler, // 204: Reserved interrupt FCCU_0_IRQHandler, // 205: Interrupt request(ALARM state) FCCU_1_IRQHandler, // 206: Interrupt request(miscellaneous conditions) - Reserved207_IRQHandler, // 207: Reserved interrupt + STCU_IRQHandler, // 207: MBIST IRQ MU0_B_TX_IRQHandler, // 208: ORed TX interrupt to MU-0 MU0_B_RX_IRQHandler, // 209: ORed RX interrupt to MU-0 MU0_B_IRQHandler, // 210: ORed general purpose interrupt request to MU-0 @@ -1278,7 +1280,7 @@ WEAK_AV void DefaultISR1(uint32_t instance) } } -WEAK_AV void DefaultISR4(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) +WEAK_AV void DefaultISR3(uint32_t instance, uint32_t start, uint32_t end) { while(1) { @@ -1516,14 +1518,14 @@ WEAK void Reserved60_IRQHandler(void) Reserved60_DriverIRQHandler(); } -WEAK void Reserved61_IRQHandler(void) +WEAK void CTI_INT0_IRQHandler(void) { - Reserved61_DriverIRQHandler(); + CTI_INT0_DriverIRQHandler(); } -WEAK void Reserved62_IRQHandler(void) +WEAK void CTI_INT1_IRQHandler(void) { - Reserved62_DriverIRQHandler(); + CTI_INT1_DriverIRQHandler(); } WEAK void Reserved63_IRQHandler(void) @@ -1843,17 +1845,17 @@ WEAK void FlexCAN0_0_IRQHandler(void) WEAK void FlexCAN0_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U, 1U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U); } WEAK void FlexCAN0_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U); } WEAK void FlexCAN0_3_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U); } WEAK void FlexCAN1_0_IRQHandler(void) @@ -1863,12 +1865,12 @@ WEAK void FlexCAN1_0_IRQHandler(void) WEAK void FlexCAN1_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U); } WEAK void FlexCAN1_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U); } WEAK void FlexCAN2_0_IRQHandler(void) @@ -1878,12 +1880,12 @@ WEAK void FlexCAN2_0_IRQHandler(void) WEAK void FlexCAN2_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U); } WEAK void FlexCAN2_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U); } WEAK void FlexCAN3_0_IRQHandler(void) @@ -1893,7 +1895,7 @@ WEAK void FlexCAN3_0_IRQHandler(void) WEAK void FlexCAN3_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(3U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(3U, 0U, 31U); } WEAK void FlexCAN4_0_IRQHandler(void) @@ -1903,7 +1905,7 @@ WEAK void FlexCAN4_0_IRQHandler(void) WEAK void FlexCAN4_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(4U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(4U, 0U, 31U); } WEAK void FlexCAN5_0_IRQHandler(void) @@ -1913,7 +1915,7 @@ WEAK void FlexCAN5_0_IRQHandler(void) WEAK void FlexCAN5_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(5U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(5U, 0U, 31U); } WEAK void Reserved141_IRQHandler(void) @@ -2247,9 +2249,9 @@ WEAK void FCCU_1_IRQHandler(void) FCCU_1_DriverIRQHandler(); } -WEAK void Reserved207_IRQHandler(void) +WEAK void STCU_IRQHandler(void) { - Reserved207_DriverIRQHandler(); + STCU_DriverIRQHandler(); } WEAK void MU0_B_TX_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/startup_mcxe317.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/startup_mcxe317.cpp index 1f20f1403..b669eb8c2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/startup_mcxe317.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/startup_mcxe317.cpp @@ -2,7 +2,7 @@ //***************************************************************************** // MCXE317 startup code // -// Version : 120525 +// Version : 110825 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -130,8 +130,8 @@ WEAK void Reserved57_IRQHandler(void); WEAK void SWT0_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); -WEAK void Reserved61_IRQHandler(void); -WEAK void Reserved62_IRQHandler(void); +WEAK void CTI_INT0_IRQHandler(void); +WEAK void CTI_INT1_IRQHandler(void); WEAK void Reserved63_IRQHandler(void); WEAK void FLASH_0_IRQHandler(void); WEAK void FLASH_1_IRQHandler(void); @@ -276,7 +276,7 @@ WEAK void Reserved203_IRQHandler(void); WEAK void Reserved204_IRQHandler(void); WEAK void FCCU_0_IRQHandler(void); WEAK void FCCU_1_IRQHandler(void); -WEAK void Reserved207_IRQHandler(void); +WEAK void STCU_IRQHandler(void); WEAK void MU0_B_TX_IRQHandler(void); WEAK void MU0_B_RX_IRQHandler(void); WEAK void MU0_B_IRQHandler(void); @@ -355,8 +355,8 @@ void Reserved57_DriverIRQHandler(void) ALIAS(DefaultISR); void SWT0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved61_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved62_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved63_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_1_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -418,7 +418,7 @@ void Reserved121_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved122_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved123_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved124_DriverIRQHandler(void) ALIAS(DefaultISR); -void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) ALIAS(DefaultISR4); +void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end) ALIAS(DefaultISR3); void FLEXCAN_DriverEventIRQHandler(uint32_t instance) ALIAS(DefaultISR1); void Reserved141_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved142_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -475,7 +475,7 @@ void Reserved203_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved204_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_1_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved207_DriverIRQHandler(void) ALIAS(DefaultISR); +void STCU_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_TX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_RX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -591,6 +591,8 @@ void (* const g_pfnVectors[])(void) = { ResetISR, // The reset handler #elif defined (__ICCARM__) extern void (* const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); __attribute__ ((used, section(".intvec"))) void (* const __vector_table[])(void) = { (void(*)())(uint32_t)__StackTop, // The initial stack pointer @@ -665,8 +667,8 @@ void (* const __isr_vector[])(void) = { SWT0_IRQHandler, // 58 : Platform watchdog initial time-out Reserved59_IRQHandler, // 59 : Reserved interrupt Reserved60_IRQHandler, // 60 : Reserved interrupt - Reserved61_IRQHandler, // 61 : Reserved interrupt - Reserved62_IRQHandler, // 62 : Reserved interrupt + CTI_INT0_IRQHandler, // 61 : CTI interrupt0 + CTI_INT1_IRQHandler, // 62 : CTI interrupt1 Reserved63_IRQHandler, // 63 : Reserved interrupt FLASH_0_IRQHandler, // 64 : Program or erase operation is completed FLASH_1_IRQHandler, // 65 : Main watchdog timeout interrupt @@ -811,7 +813,7 @@ void (* const __isr_vector[])(void) = { Reserved204_IRQHandler, // 204: Reserved interrupt FCCU_0_IRQHandler, // 205: Interrupt request(ALARM state) FCCU_1_IRQHandler, // 206: Interrupt request(miscellaneous conditions) - Reserved207_IRQHandler, // 207: Reserved interrupt + STCU_IRQHandler, // 207: MBIST IRQ MU0_B_TX_IRQHandler, // 208: ORed TX interrupt to MU-0 MU0_B_RX_IRQHandler, // 209: ORed RX interrupt to MU-0 MU0_B_IRQHandler, // 210: ORed general purpose interrupt request to MU-0 @@ -1278,7 +1280,7 @@ WEAK_AV void DefaultISR1(uint32_t instance) } } -WEAK_AV void DefaultISR4(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) +WEAK_AV void DefaultISR3(uint32_t instance, uint32_t start, uint32_t end) { while(1) { @@ -1516,14 +1518,14 @@ WEAK void Reserved60_IRQHandler(void) Reserved60_DriverIRQHandler(); } -WEAK void Reserved61_IRQHandler(void) +WEAK void CTI_INT0_IRQHandler(void) { - Reserved61_DriverIRQHandler(); + CTI_INT0_DriverIRQHandler(); } -WEAK void Reserved62_IRQHandler(void) +WEAK void CTI_INT1_IRQHandler(void) { - Reserved62_DriverIRQHandler(); + CTI_INT1_DriverIRQHandler(); } WEAK void Reserved63_IRQHandler(void) @@ -1843,17 +1845,17 @@ WEAK void FlexCAN0_0_IRQHandler(void) WEAK void FlexCAN0_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U, 1U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U); } WEAK void FlexCAN0_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U); } WEAK void FlexCAN0_3_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U); } WEAK void FlexCAN1_0_IRQHandler(void) @@ -1863,12 +1865,12 @@ WEAK void FlexCAN1_0_IRQHandler(void) WEAK void FlexCAN1_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U); } WEAK void FlexCAN1_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U); } WEAK void FlexCAN2_0_IRQHandler(void) @@ -1878,12 +1880,12 @@ WEAK void FlexCAN2_0_IRQHandler(void) WEAK void FlexCAN2_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U); } WEAK void FlexCAN2_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U); } WEAK void FlexCAN3_0_IRQHandler(void) @@ -1893,7 +1895,7 @@ WEAK void FlexCAN3_0_IRQHandler(void) WEAK void FlexCAN3_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(3U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(3U, 0U, 31U); } WEAK void FlexCAN4_0_IRQHandler(void) @@ -1903,7 +1905,7 @@ WEAK void FlexCAN4_0_IRQHandler(void) WEAK void FlexCAN4_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(4U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(4U, 0U, 31U); } WEAK void FlexCAN5_0_IRQHandler(void) @@ -1913,7 +1915,7 @@ WEAK void FlexCAN5_0_IRQHandler(void) WEAK void FlexCAN5_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(5U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(5U, 0U, 31U); } WEAK void Reserved141_IRQHandler(void) @@ -2247,9 +2249,9 @@ WEAK void FCCU_1_IRQHandler(void) FCCU_1_DriverIRQHandler(); } -WEAK void Reserved207_IRQHandler(void) +WEAK void STCU_IRQHandler(void) { - Reserved207_DriverIRQHandler(); + STCU_DriverIRQHandler(); } WEAK void MU0_B_TX_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/system_MCXE317.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/system_MCXE317.c index 4b2dc5b89..969d11af1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/system_MCXE317.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/system_MCXE317.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250811 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MCXE317 * @version 1.0 - * @date 2025-05-12 + * @date 2025-08-11 * @brief Device specific configuration file for MCXE317 (implementation file) * * Provides a system configuration function and a global variable that contains @@ -58,6 +60,15 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { +#if (DISABLE_WDOG) + if ((SWT_0->CR & SWT_CR_WEN_MASK) != 0U) + { + SWT_0->SR = 0xC520; + SWT_0->SR = 0xD928; + SWT_0->CR &= ~SWT_CR_WEN_MASK; + } +#endif /* (DISABLE_WDOG) */ + #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/system_MCXE317.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/system_MCXE317.h index 8b5a860b0..5fac88e32 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/system_MCXE317.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE317/system_MCXE317.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250811 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MCXE317 * @version 1.0 - * @date 2025-05-12 + * @date 2025-08-11 * @brief Device specific configuration file for MCXE317 (header file) * * Provides a system configuration function and a global variable that contains @@ -51,6 +53,10 @@ #define DEFAULT_SYSTEM_CLOCK 48000000U #define CLK_FIRC_CLOCK_FREQ 48000000U /**< FIRC clock frequency */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B.h index 1b2f445fd..0d28d2270 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B.h @@ -1,14 +1,15 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250319 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE31B @@ -23,14 +24,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file MCXE31B.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCXE31B * * CMSIS Peripheral Access Layer for MCXE31B diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B_COMMON.h index 3b4bca588..962a9b53d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B_COMMON.h @@ -1,14 +1,15 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250527 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250728 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXE31B @@ -23,14 +24,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file MCXE31B_COMMON.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCXE31B * * CMSIS Peripheral Access Layer for MCXE31B @@ -41,9 +44,9 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- @@ -119,8 +122,8 @@ typedef enum IRQn { SWT0_IRQn = 42, /**< Platform watchdog initial time-out */ Reserved59_IRQn = 43, /**< Reserved interrupt */ Reserved60_IRQn = 44, /**< Reserved interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - Reserved62_IRQn = 46, /**< Reserved interrupt */ + CTI_INT0_IRQn = 45, /**< CTI interrupt0 */ + CTI_INT1_IRQn = 46, /**< CTI interrupt1 */ Reserved63_IRQn = 47, /**< Reserved interrupt */ FLASH_0_IRQn = 48, /**< Program or erase operation is completed */ FLASH_1_IRQn = 49, /**< Main watchdog timeout interrupt */ @@ -243,7 +246,7 @@ typedef enum IRQn { CMP2_IRQn = 185, /**< Async interrupt */ FCCU_0_IRQn = 189, /**< Interrupt request (ALARM state) */ FCCU_1_IRQn = 190, /**< Interrupt request (miscellaneous conditions) */ - Reserved207_IRQn = 191, /**< Reserved interrupt */ + STCU_IRQn = 191, /**< LBIST and MBIST IRQ */ MU0_B_TX_IRQn = 192, /**< ORed TX interrupt to MU-0 */ MU0_B_RX_IRQn = 193, /**< ORed RX interrupt to MU-0 */ MU0_B_IRQn = 194, /**< ORed general purpose interrupt request to MU-0 */ @@ -266,12 +269,12 @@ typedef enum IRQn { Reserved227_IRQn = 211, /**< Reserved interrupt */ PLL_LOL_IRQn = 212, /**< PLL LOL interrupt */ CORE_CLK_FAIL_IRQn = 213, /**< CORE_CLK_FAIL CMU reset reaction interrupt */ - Reserved230_IRQn = 214, /**< PLL2 LOL interrupt */ + Reserved230_IRQn = 214, /**< Reserved interrupt */ AIPS_PLAT_CLK_FAIL_IRQn = 215, /**< AIPS_PLAT_CLK_FAIL CMU reset reaction interrupt */ - Reserved232_IRQn = 216, /**< XRDC Error Interrupt */ + Reserved232_IRQn = 216, /**< Reserved interrupt */ HSE_B_CLK_FAIL_IRQn = 217, /**< HSE_B_CLK_FAIL CMU reset reaction interrupt */ Reserved234_IRQn = 218, /**< Reserved interrupt */ - Reserved235_IRQn = 219, /**< CM7_CORE_CLK_FAIL CMU reset reaction interrupt */ + Reserved235_IRQn = 219, /**< Reserved interrupt */ Reserved236_IRQn = 220, /**< Reserved interrupt */ Reserved237_IRQn = 221, /**< Reserved interrupt */ Reserved238_IRQn = 222, /**< Reserved interrupt */ @@ -989,6 +992,8 @@ typedef enum _xbic_slave_port #define DMA_BASE_ADDRS { EDMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { EDMA } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { DMATCD0_IRQn, DMATCD1_IRQn, DMATCD2_IRQn, DMATCD3_IRQn, DMATCD4_IRQn, DMATCD5_IRQn, DMATCD6_IRQn, DMATCD7_IRQn, DMATCD8_IRQn, DMATCD9_IRQn, DMATCD10_IRQn, DMATCD11_IRQn, DMATCD12_IRQn, DMATCD13_IRQn, DMATCD14_IRQn, DMATCD15_IRQn, DMATCD16_IRQn, DMATCD17_IRQn, DMATCD18_IRQn, DMATCD19_IRQn, DMATCD20_IRQn, DMATCD21_IRQn, DMATCD22_IRQn, DMATCD23_IRQn, DMATCD24_IRQn, DMATCD25_IRQn, DMATCD26_IRQn, DMATCD27_IRQn, DMATCD28_IRQn, DMATCD29_IRQn, DMATCD30_IRQn, DMATCD31_IRQn } } /* DMAMUX - Peripheral instance base addresses */ /** Peripheral DMAMUX_0 base address */ @@ -1023,6 +1028,8 @@ typedef enum _xbic_slave_port #define EMAC_BASE_ADDRS { EMAC_BASE } /** Array initializer of EMAC peripheral base pointers */ #define EMAC_BASE_PTRS { EMAC } +/** Interrupt vectors for the EMAC peripheral type */ +#define EMAC_IRQS { EMAC_0_IRQn } /* EMIOS - Peripheral instance base addresses */ /** Peripheral EMIOS_0 base address */ @@ -1518,6 +1525,16 @@ typedef enum _xbic_slave_port #define SIUL2_BASE_ADDRS { SIUL2_BASE } /** Array initializer of SIUL2 peripheral base pointers */ #define SIUL2_BASE_PTRS { SIUL2 } +/** Interrupt vectors for the SIUL2 peripheral type */ +#define SIUL2_IRQS { { SIUL2_0_IRQn, SIUL2_1_IRQn, SIUL2_2_IRQn, SIUL2_3_IRQn } } +/*! Maximum pins which share the same EIRQ request */ +#define SIUL2_MAX_PINS_PER_EIRQ (4U) +/*! Pins and EIRQ mapping array */ +#define SIUL2_EIRQ_PINS_MAP {{0, 18, 64, 128}, {1, 19, 65, 129}, {2, 20, 66, 130}, {3, 21, 67, 131}, {4, 16, 68, 132}, {5, 25, 69, 133}, {6, 28, 70, 134}, {7, 30, 71, 136}, \ + {32, 53, 96, 137}, {33, 54, 97, 138}, {34, 55, 98, 139}, {35, 56, 99, 140}, {36, 57, 100, 141}, {37, 58, 101, 142}, {40, 60, 102, 143}, {41, 103, 144, -1}, \ + {8, 72, 84, -1}, {9, 73, 85, -1}, {10, 74, 87, -1}, {11, 75, 88, -1}, {12, 76, 89, -1}, {13, 77, 90, -1}, {14, 78, 91, -1}, {15, 79, 93, -1}, \ + {42, 104, 113, -1}, {43, 105, 116, -1}, {44, 106, 117, -1}, {45, 107, 118, -1}, {46, 108, 119, -1}, {47, 109, 120, -1}, {48, 110, 123, -1}, {49, 111, 124, -1}} + /* STCU - Peripheral instance base addresses */ /** Peripheral STCU base address */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B_features.h index 2e5e0a128..74903cc08 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/MCXE31B_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2024-11-18 -** Build: b250520 +** Version: rev. 1.0, 2025-07-18 +** Build: b250829 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,10 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2024-11-18) +** - rev. 0.1 (2024-11-18) ** +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -39,6 +41,8 @@ #define FSL_FEATURE_SOC_EDMA_COUNT (1) /* @brief EIM availability on the SoC. */ #define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EMAC availability on the SoC. */ +#define FSL_FEATURE_SOC_EMAC_COUNT (1) /* @brief EMIOS availability on the SoC. */ #define FSL_FEATURE_SOC_EMIOS_COUNT (3) /* @brief FLEXCAN availability on the SoC. */ @@ -71,6 +75,8 @@ #define FSL_FEATURE_SOC_RTC_COUNT (1) /* @brief SEMA42 availability on the SoC. */ #define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SIUL2 availability on the SoC. */ +#define FSL_FEATURE_SOC_SIUL2_COUNT (1) /* @brief STM availability on the SoC. */ #define FSL_FEATURE_SOC_STM_COUNT (2) /* @brief TRGMUX availability on the SoC. */ @@ -216,7 +222,7 @@ /* @brief If channel clock controlled independently */ #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) /* @brief If 128 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) /* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (32) /* @brief Has register CH_CSR. */ @@ -277,6 +283,8 @@ #define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) /* @brief Number of DMA channels with asynchronous request capability. */ #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) +/* @brief TCD has clock control. */ +#define FSL_FEATURE_EDMA_HAS_EDMA_TCD_CLOCK_ENABLE (1) /* FLASH_C40 module features */ @@ -379,11 +387,15 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 052403. */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_052403 (1) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (1) /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (0) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -412,6 +424,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (0) /* INTM module features */ @@ -480,6 +494,8 @@ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) /* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) +/* @brief Has ERRATA050456. */ +#define FSL_FEATURE_LPSPI_HAS_ERRATA_050456 (1) /* LPUART module features */ @@ -513,8 +529,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -557,6 +571,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MCM module features */ @@ -671,12 +689,10 @@ /* @brief Lowest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) /* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (207) +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (223) /* PIT module features */ -/* @brief Has Real Time Interrupt. */ -#define FSL_FEATURE_PIT_HAS_RTI (1) /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ #define FSL_FEATURE_PIT_TIMER_COUNT (4) /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ @@ -687,6 +703,10 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has Real Time Interrupt. */ +#define FSL_FEATURE_PIT_HAS_RTI (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMC module features */ @@ -802,6 +822,10 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (0) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) +/* @brief Is affected by errata with ID 051421 (SAI: Synchronous mode with bypass is not supported). */ +#define FSL_FEATURE_SAI_HAS_ERRATA_051421 (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists.txt index ecafe1ae7..318b4ed8c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists.txt @@ -4,6 +4,7 @@ include(./CMakeLists_clock.txt) include(./CMakeLists_dcm_gpr.txt) +include(./CMakeLists_dcm.txt) include(./CMakeLists_edma_soc.txt) include(./CMakeLists_memory.txt) include(./CMakeLists_siul2.txt) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_clock.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_clock.txt index 3f5754256..ae6053a40 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_clock.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_clock.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.1.0) + mcux_component_version(2.1.2) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) mcux_add_include( INCLUDES . ) endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_dcm.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_dcm.txt new file mode 100644 index 000000000..c52d6c861 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_dcm.txt @@ -0,0 +1,12 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +if(CONFIG_MCUX_COMPONENT_driver.dcm) + mcux_component_version(2.0.1) + + mcux_add_source(SOURCES fsl_dcm.h fsl_dcm.c) + + mcux_add_include(INCLUDES .) + +endif() diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_siul2.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_siul2.txt index 148918de7..830662d0b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_siul2.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/CMakeLists_siul2.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.siul2) - mcux_component_version(2.0.3) + mcux_component_version(2.1.0) mcux_add_source( SOURCES fsl_siul2.c fsl_siul2.h ) mcux_add_include( INCLUDES . ) endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_clock.c index c9ca8eabf..4f192a4ab 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_clock.c @@ -234,6 +234,7 @@ void CLOCK_ProgressiveClockFrequencySwitch(clock_attach_id_t connection, clock_p MC_CGM->PCFS_SDUR = MC_CGM_PCFS_SDUR_SDUR(sdur); MC_CGM->PCFS_DIVC8 = MC_CGM_PCFS_DIVC8_RATE(divcRate) | MC_CGM_PCFS_DIVC8_INIT(divcInit); MC_CGM->PCFS_DIVE8 = MC_CGM_PCFS_DIVE8_DIVE(divEndValue); + assert(divStartValue <= MC_CGM_PCFS_DIVS8_DIVS_MASK); MC_CGM->PCFS_DIVS8 = MC_CGM_PCFS_DIVS8_DIVS((uint32_t)divStartValue); while ((CLOCK_TUPLE_MUX_CSS_REG(connection) & MC_CGM_MUX_0_CSS_SWIP_MASK) != 0) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_clock.h index e82ff9c16..cd9b80313 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_clock.h @@ -19,8 +19,8 @@ *****************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.1.0 */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @brief CLOCK driver version 2.1.2 */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*@}*/ /* Definition for delay API in clock driver, users can redefine it to the real @@ -121,6 +121,30 @@ extern volatile uint32_t g_xtal0Freq; kCLOCK_Edma \ } +/*! @brief Clock ip name array for EMAC. */ +#define EMAC_CLOCKS \ + { \ + kCLOCK_Emac \ + } + +/*! @brief Clock ip name array for EDMA TCD. */ +#if defined(FSL_FEATURE_MC_ME_HAS_PRTN2) && (FSL_FEATURE_MC_ME_HAS_PRTN2 != 0U) +#define EDMA_TCD_CLOCKS \ + { \ + kCLOCK_Tcd0, kCLOCK_Tcd1, kCLOCK_Tcd2, kCLOCK_Tcd3, kCLOCK_Tcd4, kCLOCK_Tcd5, kCLOCK_Tcd6, kCLOCK_Tcd7, \ + kCLOCK_Tcd8, kCLOCK_Tcd9, kCLOCK_Tcd10, kCLOCK_Tcd11, kCLOCK_Tcd12, kCLOCK_Tcd13, kCLOCK_Tcd14, \ + kCLOCK_Tcd15, kCLOCK_Tcd16, kCLOCK_Tcd17, kCLOCK_Tcd18, kCLOCK_Tcd19, kCLOCK_Tcd20, kCLOCK_Tcd21, \ + kCLOCK_Tcd22, kCLOCK_Tcd23, kCLOCK_Tcd24, kCLOCK_Tcd25, kCLOCK_Tcd26, kCLOCK_Tcd27, kCLOCK_Tcd28, \ + kCLOCK_Tcd29, kCLOCK_Tcd30, kCLOCK_Tcd31 \ + } +#else +#define EDMA_TCD_CLOCKS \ + { \ + kCLOCK_Tcd0, kCLOCK_Tcd1, kCLOCK_Tcd2, kCLOCK_Tcd3, kCLOCK_Tcd4, kCLOCK_Tcd5, kCLOCK_Tcd6, kCLOCK_Tcd7, \ + kCLOCK_Tcd8, kCLOCK_Tcd9, kCLOCK_Tcd10, kCLOCK_Tcd11, \ + } +#endif /* FSL_FEATURE_MC_ME_HAS_PRTN2 */ + /*! @brief Clock ip name array for EIM. */ #define EIM_CLOCKS \ { \ @@ -431,7 +455,7 @@ typedef enum _clock_ip_name kCLOCK_Sema42 = MC_ME_COFB_TUPLE(0x530U, 24), /*!< Semaphores2 (PRTN2_COFB0) */ kCLOCK_Stm1 = MC_ME_COFB_TUPLE(0x530U, 29), /*!< System Timer Module 1 (PRTN2_COFB0) */ /* PRTN2_COFB1_CLKEN Bit Fields */ - kCLOCK_Enet = MC_ME_COFB_TUPLE(0x534U, 0), /*!< ENET (PRTN2_COFB1) */ + kCLOCK_Emac = MC_ME_COFB_TUPLE(0x534U, 0), /*!< EMAC (PRTN2_COFB1) */ kCLOCK_Lpuart8 = MC_ME_COFB_TUPLE(0x534U, 3U), /*!< Low Power UART 8 (PRTN2_COFB1). */ kCLOCK_Lpuart9 = MC_ME_COFB_TUPLE(0x534U, 4U), /*!< Low Power UART 9 (PRTN2_COFB1). */ kCLOCK_Lpuart10 = MC_ME_COFB_TUPLE(0x534U, 5U), /*!< Low Power UART 10 (PRTN2_COFB1). */ @@ -584,6 +608,9 @@ typedef enum _clock_attach_id CLOCK_DIV_TUPLE(8U, CLOCK_EMAC_RMII_TX_CLK), /*!< Select EMAC_RMII_TX_CLK(pin) as EMAC_TX_CLK clock source. */ kFIRC_CLK_to_EMAC_TS = CLOCK_DIV_TUPLE(9U, CLOCK_FIRC_CLK), /*!< Select FIRC as EMAC_TS_CLK clock source. */ + kFXOSC_CLK_to_EMAC_TS = CLOCK_DIV_TUPLE(9U, CLOCK_FXOSC_CLK), /*!< Select FXOSC as EMAC_TS_CLK clock source. */ + kPLL_PHI0_CLK_to_EMAC_TS = + CLOCK_DIV_TUPLE(9U, CLOCK_PLL_PHI0_CLK), /*!< Select PLL_PHI0_CLK as EMAC_TS_CLK clock source. */ kEMAC_RMII_TX_CLK_to_EMAC_TS = CLOCK_DIV_TUPLE(9U, CLOCK_EMAC_RMII_TX_CLK), /*!< Select EMAC_RMII_TX_CLK(pin) as EMAC_TS_CLK clock source. */ kEMAC_RX_CLK_to_EMAC_TS = @@ -593,14 +620,8 @@ typedef enum _clock_attach_id #if defined(FSL_FEATURE_CLOCK_HAS_QSPI) && (FSL_FEATURE_CLOCK_HAS_QSPI != 0U) kFIRC_CLK_to_QSPI_SFCK = CLOCK_DIV_TUPLE(10U, CLOCK_FIRC_CLK), /*!< Select FIRC as QSPI_SFCK clock source. */ kFXOSC_CLK_to_QSPI_SFCK = CLOCK_DIV_TUPLE(10U, CLOCK_FXOSC_CLK), /*!< Select FXOSC as QSPI_SFCK clock source. */ - kPLL_PHI0_CLK_to_QSPI_SFCK = - CLOCK_DIV_TUPLE(10U, CLOCK_PLL_PHI0_CLK), /*!< Select PLL_PHI0_CLK as QSPI_SFCK clock source. */ kPLL_PHI1_CLK_to_QSPI_SFCK = CLOCK_DIV_TUPLE(10U, CLOCK_PLL_PHI1_CLK), /*!< Select PLL_PHI1_CLK as QSPI_SFCK clock source. */ - kEMAC_RMII_TX_CLK_to_QSPI_SFCK = - CLOCK_DIV_TUPLE(10U, CLOCK_EMAC_RMII_TX_CLK), /*!< Select EMAC_RMII_TX_CLK(pin) as QSPI_SFCKe clock source. */ - kEMAC_RX_CLK_to_QSPI_SFCK = - CLOCK_DIV_TUPLE(10U, CLOCK_EMAC_RX_CLK), /*!< Select EMAC_RX_CLK(pin) as QSPI_SFCK clock source. */ #endif /* FSL_FEATURE_CLOCK_HAS_QSPI */ kFIRC_CLK_to_TRACE = CLOCK_DIV_TUPLE(11U, CLOCK_FIRC_CLK), /*!< Select FIRC as TRACE clock source. */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_dcm.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_dcm.c new file mode 100644 index 000000000..cb8cabba5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_dcm.c @@ -0,0 +1,104 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dcm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define DCM_DCMLCS_DCMLCSS_SHIFT 0x00U +#define DCM_DCMLCS_DCMLCSS_MASK (0x01U << DCM_DCMLCS_DCMLCSS_SHIFT) + +#define DCM_DCMLCS_DCMLCC_SHIFT 0x01U +#define DCM_DCMLCS_DCMLCC_MASK (0x03U << DCM_DCMLCS_DCMLCC_SHIFT) + +#define DCM_DCMLCS_DCMLCE_SHIFT 0x04U +#define DCM_DCMLCS_DCMLCE_MASK (0x01U << DCM_DCMLCS_DCMLCE_SHIFT) + +#define DCM_DCMLCS_DCMLCFE_SHIFT 0x05U +#define DCM_DCMLCS_DCMLCFE_MASK (0x01U << DCM_DCMLCS_DCMLCFE_SHIFT) + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dcm" +#endif + +/* + * @brief Get DCF scan report. + * + * @param slot Slot number, should be less than DCM_DCMSRR_COUNT. + * @param report The DCF scan report. + */ +void DCM_GetDcfScanReport(uint32_t slot, dcm_dcf_scan_report_t *report) +{ + assert(slot < DCM_DCMSRR_COUNT); + assert(report != NULL); + + union + { + uint32_t reg; + dcm_dcf_scan_report_t dcfScanReport; + } localReport; + + localReport.reg = DCM->DCMSRR[slot]; + *report = localReport.dcfScanReport; +} + +/* + * @brief Get life cycle slost scan status. + * + * @param status The life cycle scan status. + */ +static void DCM_GetLifeCycleSlotScanStatus(dcm_life_cycle_slot_scan_status_t *status, uint32_t regVal) +{ + status->hasError = (regVal & DCM_DCMLCS_DCMLCSS_MASK) >> DCM_DCMLCS_DCMLCSS_SHIFT; + status->marking = (regVal & DCM_DCMLCS_DCMLCC_MASK) >> DCM_DCMLCS_DCMLCC_SHIFT; + status->hasEccError = (regVal & DCM_DCMLCS_DCMLCE_MASK) >> DCM_DCMLCS_DCMLCE_SHIFT; + status->hasFlashError = (regVal & DCM_DCMLCS_DCMLCFE_MASK) >> DCM_DCMLCS_DCMLCFE_SHIFT; +} + +/* + * @brief Get life cycle scan status. + * + * @param status The life cycle scan status. + */ +void DCM_GetLifeCycleScanStatus(dcm_life_cycle_scan_status_t *status) +{ + assert(status != NULL); + + uint32_t dcmlcs = DCM->DCMLCS; + uint32_t dcmlcs2 = DCM->DCMLCS_2; + + DCM_GetLifeCycleSlotScanStatus(&status->status[0], dcmlcs & 0x3FUL); + + dcmlcs >>= 6; + DCM_GetLifeCycleSlotScanStatus(&status->status[1], dcmlcs & 0x3FUL); + + dcmlcs >>= 6; + DCM_GetLifeCycleSlotScanStatus(&status->status[2], dcmlcs & 0x3FUL); + + dcmlcs >>= 6; + DCM_GetLifeCycleSlotScanStatus(&status->status[3], dcmlcs & 0x3FUL); + + dcmlcs >>= 6; + DCM_GetLifeCycleSlotScanStatus(&status->status[4], dcmlcs & 0x3FUL); + + DCM_GetLifeCycleSlotScanStatus(&status->status[5], dcmlcs2 & 0x3FUL); +} + +/* + * @brief Clear life cycle scan status. + */ +void DCM_ClearLifeCycleScanStatus(void) +{ + DCM->DCMLCS = 0x3FFFFFFFUL; + DCM->DCMLCS_2 = 0x0000003FUL; +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_dcm.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_dcm.h new file mode 100644 index 000000000..df52d926b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_dcm.h @@ -0,0 +1,169 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_DCM_H_ +#define FSL_DCM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dcm + * @{ + */ + + /******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ + +/*! @brief DCM driver version. */ +#define FSL_DCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @} */ + +/*! @brief DCM life cycle slot count */ +#define DCM_LC_SLOT_COUNT 6u + +/*! + * @brief DCF scan report + */ +typedef struct _dcm_dcf_scan_report +{ + uint32_t address : 21; /*!< Address */ + uint32_t : 3; + uint32_t location : 3; /*!< Load location */ + uint32_t flashError : 1; /*!< Flash memory error, 1 if there is error */ + uint32_t chipSideError : 1; /*!< Chip side error, 1 if there is error */ + uint32_t scanTimeout : 1; /*!< 1 if scan timeout. */ + uint32_t : 2; +} dcm_dcf_scan_report_t; + +/*! + * @brief Life cycle + */ +typedef enum _dcm_life_cycle +{ + kDCM_LifeCycleFailureAnalysis = 0U, /*!< Failure analysis (FA) */ + kDCM_LifeCyclePreFailureAnalysis = 1U, /*!< Pre-Failure analysis (Pre-FA) */ + kDCM_LifeCycleOemProduction = 2U, /*!< OEM production */ + kDCM_LifeCycleCustomerDelivery = 3U, /*!< Customer delivery */ + kDCM_LifeCycleMcuProduction = 6U, /*!< MCU production */ + kDCM_LifeCycleInField = 7U, /*!< In field */ +} dcm_life_cycle_t; + +/*! + * @brief Life cycle scan marking + */ +enum _dcm_life_cycle_scan_marking +{ + kDCM_LifeCycleScanNotScanned = 0U, /*!< Not scanned yet */ + kDCM_LifeCycleScanActive = 1U, /*!< Marked as active */ + kDCM_LifeCycleScanInactive = 2U, /*!< Marked as inactive */ + kDCM_LifeCycleScanRegionErased = 3U, /*!< Region is erased/virgin */ + kDCM_LifeCycleScanUnknown = 4U, /*!< Marked as inactive by an unknown pattern */ + kDCM_LifeCycleScanTimeout = 5U, /*!< Scanning timed out */ +}; + +/*! + * @brief Life cycle slot scan status structure + */ +typedef struct _dcm_life_cycle_slost_scan_status +{ + uint8_t hasError : 1; /*!< 1 means error, 0 means no error. */ + uint8_t marking : 3; /*!< See _dcm_life_cycle_scan_marking */ + uint8_t hasEccError : 1; /*!< 1 means error, 0 means no error. */ + uint8_t hasFlashError : 1; /*!< 1 means error, 0 means no error. */ +} dcm_life_cycle_slot_scan_status_t; + +/*! + * @brief Life cycle scan status structure + */ +typedef struct _dcm_life_cycle_scan_status +{ + dcm_life_cycle_slot_scan_status_t status[DCM_LC_SLOT_COUNT]; +} dcm_life_cycle_scan_status_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DCF scan result + * @{ + */ + +/*! + * @brief Get DCF scan report. + * + * @param slot Slot number, should be less than DCM_DCMSRR_COUNT. + * @param report The DCF scan report. + */ +void DCM_GetDcfScanReport(uint32_t slot, dcm_dcf_scan_report_t *report); + +/*! + * @brief Clear DCF scan report. + * + * @param slot Slot number, should be less than DCM_DCMSRR_COUNT. + */ +static inline void DCM_ClearDcfScanReport(uint32_t slot) +{ + assert(slot < DCM_DCMSRR_COUNT); + + DCM->DCMSRR[slot] = (DCM_DCMSRR_DCMDCFE1_MASK | DCM_DCMSRR_DCMDCFF1_MASK | DCM_DCMSRR_DCMESF1_MASK | DCM_DCMSRR_DCMESD1_MASK | DCM_DCMSRR_DCMDCFT1_MASK); +} +/*! @}*/ + +/*! + * @name Life cycle + * @{ + */ + +/*! + * @brief Get real life cycle. + * + * @return The real life cycle. + */ +static inline dcm_life_cycle_t DCM_GetRealLifeCycle(void) +{ + return (dcm_life_cycle_t)((DCM->DCMLCC & DCM_DCMLCC_DCMRLC_MASK) >> DCM_DCMLCC_DCMRLC_SHIFT); +} + +/*! + * @brief Get current life cycle. + * + * @return The current life cycle. + */ +static inline dcm_life_cycle_t DCM_GetCurrentLifeCycle(void) +{ + return (dcm_life_cycle_t)((DCM->DCMLCC & DCM_DCMLCC_DCMCLC_MASK) >> DCM_DCMLCC_DCMCLC_SHIFT); +} + +/*! + * @brief Get life cycle scan status. + * + * @param status The life cycle scan status. + */ +void DCM_GetLifeCycleScanStatus(dcm_life_cycle_scan_status_t *status); + +/*! + * @brief Clear life cycle scan status. + */ +void DCM_ClearLifeCycleScanStatus(void); + +/*! @}*/ + +/*! + * @} + */ +#if defined(__cplusplus) +} +#endif +#endif /* FSL_DCM_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_memory.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_memory.h index bd9bf2de9..8777b3466 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_memory.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_memory.h @@ -80,12 +80,12 @@ static inline uint32_t MEMORY_ConvertMemoryMapAddress(uint32_t addr, mem_directi if ((addr >= (FSL_MEM_M7_ITCM_BEGIN + FSL_MEM_M7_ITCM_BACKDOOR_OFFSET)) && (addr <= (FSL_MEM_M7_ITCM_END + FSL_MEM_M7_ITCM_BACKDOOR_OFFSET))) { - dest = addr + FSL_MEM_M7_ITCM_BACKDOOR_OFFSET; + dest = addr - FSL_MEM_M7_ITCM_BACKDOOR_OFFSET; } else if ((addr >= (FSL_MEM_M7_DTCM_BEGIN + FSL_MEM_M7_DTCM_BACKDOOR_OFFSET)) && (addr <= (FSL_MEM_M7_DTCM_END + FSL_MEM_M7_DTCM_BACKDOOR_OFFSET))) { - dest = addr + FSL_MEM_M7_DTCM_BACKDOOR_OFFSET; + dest = addr - FSL_MEM_M7_DTCM_BACKDOOR_OFFSET; } else { diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_siul2.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_siul2.c index 56f0589b2..c4927ea12 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_siul2.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_siul2.c @@ -15,10 +15,20 @@ #endif #define PORT_PIN_LEVEL_NOTCHANGED_U8 ((uint8_t)2) /**< @brief Not changed port pin logic. */ + +#define SIUL2_NUMBER_OF_EIRQ 32U +#define SIUL2_NUMBER_OF_IRQN 4U + /******************************************************************************* * Variables ******************************************************************************/ - +/* Array of SIUL2 IRQ number. */ +const IRQn_Type s_siul2IRQ[][SIUL2_NUMBER_OF_IRQN] = SIUL2_IRQS; +static siul2_cb_t s_siul2Callback[SIUL2_NUMBER_OF_EIRQ] = {0U}; /*!< Array of SIUL2 ISR. */ +static uint8_t s_irqEnabledCount[SIUL2_NUMBER_OF_IRQN] = {0U}; +/* Array of SIUL2 IRQ number. */ +const int16_t s_siul2EIRQ[SIUL2_NUMBER_OF_EIRQ][SIUL2_MAX_PINS_PER_EIRQ] = SIUL2_EIRQ_PINS_MAP; +static SIUL2_Type *s_siul2EirqBase = NULL; /* SIUL2 base for IRQ related registers access. */ /******************************************************************************* * Prototypes ******************************************************************************/ @@ -178,13 +188,14 @@ static uint16_t SIUL2_Reverse_Bit_16(uint16_t value) for (i = 0U; i < 8U; i++) { temp = (((value >> i) & 1U) << (15U - i)) | (((value << i) & 0x8000U) >> (15U - i)); - ret |= (uint16_t)(temp & 0xFFFFU); + ret |= (uint16_t)(temp & 0xFFFFU); } return ret; } -void SIUL2_SetPinInputBuffer(SIUL2_Type *base, uint32_t pin, bool enable, uint32_t inputMuxReg, siul2_port_inputmux_t inputMux) +void SIUL2_SetPinInputBuffer( + SIUL2_Type *base, uint32_t pin, bool enable, uint32_t inputMuxReg, siul2_port_inputmux_t inputMux) { uint32_t imcrRegIdx = inputMuxReg; uint32_t imcrVal; @@ -192,7 +203,7 @@ void SIUL2_SetPinInputBuffer(SIUL2_Type *base, uint32_t pin, bool enable, uint32 base->MSCR[pin] &= ~SIUL2_MSCR_IBE_MASK; base->MSCR[pin] |= SIUL2_MSCR_IBE(enable ? 1UL : 0UL); - imcrVal = base->IMCR[imcrRegIdx % SIUL2_IMCR_COUNT]; + imcrVal = base->IMCR[imcrRegIdx % SIUL2_IMCR_COUNT]; imcrVal &= ~SIUL2_IMCR_SSS_MASK; /* Check input mux to configure input signal */ @@ -305,8 +316,8 @@ void SIUL2_PortMaskWrite(SIUL2_Type *base, siul2_port_num_t port, uint32_t pins, maskRevH = SIUL2_Reverse_Bit_16((uint16_t)((mask & 0xFFFF0000U) >> 16U)); pinsRevH = SIUL2_Reverse_Bit_16((uint16_t)((pins & 0xFFFF0000U) >> 16U)); - base->MPGPDO[(uint8_t)port * 2U] = (maskRevL << (uint32_t)16U) | pinsRevL; - base->MPGPDO[(uint8_t)port * 2U + 1U] = (maskRevH << (uint32_t)16U) | pinsRevH; + base->MPGPDO[(uint8_t)port * 2U] = (maskRevL << (uint32_t)16U) | pinsRevL; + base->MPGPDO[(uint8_t)port * 2U + 1U] = (maskRevH << (uint32_t)16U) | pinsRevH; } void SIUL2_PortSet(SIUL2_Type *base, siul2_port_num_t port, uint32_t pins) @@ -329,6 +340,7 @@ void SIUL2_PortToggle(SIUL2_Type *base, siul2_port_num_t port, uint32_t pins) void SIUL2_SetDmaInterruptConfig(SIUL2_Type *base, uint32_t req, siul2_interrupt_config_t config) { + assert(req < SIUL2_NUMBER_OF_EIRQ); /*Configure edge*/ switch (config) { @@ -355,6 +367,8 @@ void SIUL2_SetDmaInterruptConfig(SIUL2_Type *base, uint32_t req, siul2_interrupt void SIUL2_EnableExtInterrupt(SIUL2_Type *base, uint32_t req, siul2_interrupt_config_t config, int8_t filterCount) { + assert(req < SIUL2_NUMBER_OF_EIRQ); + base->DISR0 = 1 << req; /* Clear interrupt flag. */ base->DIRER0 |= (1U << req); /* Enable Int/DMA request. */ base->DIRSR0 &= ~(1U << req); /* Select interrupt. */ @@ -365,6 +379,8 @@ void SIUL2_EnableExtInterrupt(SIUL2_Type *base, uint32_t req, siul2_interrupt_co void SIUL2_EnableExtDma(SIUL2_Type *base, uint32_t req, siul2_interrupt_config_t config, int8_t filterCount) { + assert(req < SIUL2_NUMBER_OF_EIRQ); + base->DISR0 = 1 << req; /* Clear flag. */ base->DIRER0 |= (1U << req); /* Enable Int/DMA request. */ base->DIRSR0 |= (1U << req); /* Select DMA. */ @@ -375,7 +391,8 @@ void SIUL2_EnableExtDma(SIUL2_Type *base, uint32_t req, siul2_interrupt_config_t void SIUL2_EnableExtInterrupts(SIUL2_Type *base, uint32_t mask, siul2_interrupt_config_t config, int8_t filterCount) { - uint32_t i = 0U; + uint32_t i = 0U; + base->DISR0 = mask; /* Clear Int/DMA flag. */ base->DIRER0 |= mask; /* Enable Int/DMA request. */ base->DIRSR0 &= ~mask; /* Select interrupt. */ @@ -391,7 +408,8 @@ void SIUL2_EnableExtInterrupts(SIUL2_Type *base, uint32_t mask, siul2_interrupt_ void SIUL2_EnableExtDmaRequests(SIUL2_Type *base, uint32_t mask, siul2_interrupt_config_t config, int8_t filterCount) { - uint32_t i = 0U; + uint32_t i = 0U; + base->DISR0 = mask; /* Clear Int/DMA flag. */ base->DIRER0 |= mask; /* Enable Int/DMA request. */ base->DIRSR0 |= mask; /* Select interrupt. */ @@ -404,3 +422,115 @@ void SIUL2_EnableExtDmaRequests(SIUL2_Type *base, uint32_t mask, siul2_interrupt } } } + +uint32_t SIUL2_GetPinEirqNumber(uint32_t pin) +{ + assert(pin < SIUL2_MSCR_COUNT); + + for (uint32_t eirq = 0; eirq < SIUL2_NUMBER_OF_EIRQ; eirq++) + { + for (uint32_t i = 0; i < SIUL2_MAX_PINS_PER_EIRQ; i++) + { + if (s_siul2EIRQ[eirq][i] == (int16_t)pin) + { + return eirq; + } + + if (s_siul2EIRQ[eirq][i] < 0) + { + break; + } + } + } + + /* Return an invalid value if not found. */ + return UINT32_MAX; +} + +void SIUL2_EnableExtInteruptWithCallback( + SIUL2_Type *base, uint32_t req, siul2_interrupt_config_t config, int8_t filterCount, siul2_cb_t cb) +{ + assert(req < SIUL2_NUMBER_OF_EIRQ); + + uint32_t eirq = req / (SIUL2_NUMBER_OF_EIRQ / SIUL2_NUMBER_OF_IRQN); + + s_siul2Callback[req] = cb; + s_siul2EirqBase = base; + + SIUL2_EnableExtInterrupt(base, req, config, filterCount); + + if (s_irqEnabledCount[eirq] == 0U) /* Enable interrupt if not enabled yet. */ + { + NVIC_ClearPendingIRQ(s_siul2IRQ[0U][eirq]); + EnableIRQ(s_siul2IRQ[0U][eirq]); + } + s_irqEnabledCount[eirq]++; +} + +void SIUL2_DisableExtInterruptCallback(SIUL2_Type *base, uint32_t req) +{ + assert(req < SIUL2_NUMBER_OF_EIRQ); + + uint32_t eirq = req / (SIUL2_NUMBER_OF_EIRQ / SIUL2_NUMBER_OF_IRQN); + + s_siul2Callback[req] = NULL; + + SIUL2_DisableExtDmaAndInterrupt(base, req); + if (s_irqEnabledCount[eirq] > 0U) + { + s_irqEnabledCount[eirq]--; + } + if (s_irqEnabledCount[eirq] == 0U) + { + DisableIRQ(s_siul2IRQ[0U][eirq]); + } +} + +void SIUL2_CommonDriverIRQHandler(SIUL2_Type *base, uint8_t irqn) +{ + uint32_t bitMask = 0xFFUL; + uint32_t status = SIUL2_GetExtDmaInterruptStatusFlags(base); + uint32_t eirqsPerInt = SIUL2_NUMBER_OF_EIRQ / SIUL2_NUMBER_OF_IRQN; + + assert(irqn < SIUL2_NUMBER_OF_IRQN); + + SIUL2_ClearExtDmaInterruptStatusFlags(base, bitMask << (eirqsPerInt * irqn)); + + for (uint32_t i = 0U; i < eirqsPerInt; i++) + { + uint32_t eirq = i + eirqsPerInt * irqn; + /* Call callback when IRQ fired and callback enabled. */ + if ((s_siul2Callback[eirq] != NULL) && ((status & (1U << eirq)) != 0U)) + { + s_siul2Callback[eirq](base, status); + } + } +} + +void SIUL2_0_DriverIRQHandler(void); +void SIUL2_0_DriverIRQHandler(void) +{ + SIUL2_CommonDriverIRQHandler(s_siul2EirqBase, 0U); + SDK_ISR_EXIT_BARRIER; +} + +void SIUL2_1_DriverIRQHandler(void); +void SIUL2_1_DriverIRQHandler(void) +{ + SIUL2_CommonDriverIRQHandler(s_siul2EirqBase, 1U); + SDK_ISR_EXIT_BARRIER; +} + +void SIUL2_2_DriverIRQHandler(void); +void SIUL2_2_DriverIRQHandler(void) +{ + SIUL2_CommonDriverIRQHandler(s_siul2EirqBase, 2U); + SDK_ISR_EXIT_BARRIER; +} + +void SIUL2_3_DriverIRQHandler(void); +void SIUL2_3_DriverIRQHandler(void) +{ + SIUL2_CommonDriverIRQHandler(s_siul2EirqBase, 3U); + SDK_ISR_EXIT_BARRIER; +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_siul2.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_siul2.h index a3dbb4666..f944791da 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_siul2.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/drivers/fsl_siul2.h @@ -21,7 +21,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief SIUL2 driver version. */ -#define FSL_SIUL2_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +#define FSL_SIUL2_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*! @brief SIUL2 module maximum number of input signal on a pin */ #define FEATURE_SIUL2_MAX_NUMBER_OF_INPUT (16U) @@ -30,7 +30,8 @@ #define FEATURE_ADC_INTERLEAVE_MAX_MUX_MODE \ (2U) /*!< Some pins have two ADC interleave config, such as GPIO45 can be muxed as ADC0_S8 & ADC2_S8. */ #endif -#define DCM_DCMRWF4_ADC_INTERLEAVE_MASK (uint32_t)0x00001FFFUL /*!< Mask all adc interleave bits, some bit may not exist on some parts. */ +#define DCM_DCMRWF4_ADC_INTERLEAVE_MASK \ + (uint32_t)0x00001FFFUL /*!< Mask all adc interleave bits, some bit may not exist on some parts. */ #define SIUL2_PORT_WRITE8(address, value) ((*(volatile uint8_t *)(address)) = (value)) #define SIUL2_PORT_WRITE32(address, value) ((*(volatile uint32_t *)(address)) = (value)) @@ -202,7 +203,7 @@ typedef enum siul2_port_direction /*! * @brief Configures adc interleave mux mode. - * Note! Not all are supported for a given part, please refer to IOMUX table for supported interleaves. + * Note! Not all are supported for a given part, please refer to IOMUX table for supported interleaves. */ typedef enum siul2_adc_interleaves { @@ -238,7 +239,7 @@ typedef enum siul2_adc_interleaves kMUX_MODE_EN_ADC0_S12_0 = (uint32_t)0x0000FF7FUL, /*!< With bits 15-0, only clear ADC0_S12 bit, the other bits set to 1 */ kMUX_MODE_EN_ADC0_S13_0 = - (uint32_t)0x0000FEFFUL, /*!< With bits 15-0, only clear ADC0_S13 bit, the other bits set to 1 */ + (uint32_t)0x0000FEFFUL, /*!< With bits 15-0, only clear ADC0_S13 bit, the other bits set to 1 */ kMUX_MODE_EN_ADC2_S8_0 = (uint32_t)0x0000FDFFUL, /*!< With bits 15-0, only clear ADC2_S8 bit, the other bits set to 1 */ kMUX_MODE_EN_ADC2_S9_0 = @@ -290,20 +291,32 @@ typedef enum _siul2_port_num kSIUL2_PTG = 6U, /*!< PTG. */ } siul2_port_num_t; +/*! + * @brief SIUL2 Interrupt Filter Configuration + * + * This structure is used to configure the filter for interrupt. + */ typedef struct siul2_filter_config { uint8_t preScaler : 4; /*!< Interrupt Filter clock prescaler setting, 0-15. */ uint8_t maxCount : 4; /*!< Interrupt Filter Maximum Counter, 0-15. */ } siul2_filter_config_t; +/*! + * @brief SIUL2 Interrupt Configuration + * + * This structure is used to configure the interrupt. + */ typedef enum siul2_interrupt_config { - kSIUL2_InterruptStatusFlagDisabled = 0U, /*!< Interrupt status flag is disabled. */ - kSIUL2_InterruptRisingEdge = 0x1U, - kSIUL2_InterruptFallingEdge = 0x2U, - kSIUL2_InterruptBothEdge = 0x3U, + kSIUL2_InterruptStatusFlagDisabled = 0U, /*!< Interrupt status flag is disabled. */ + kSIUL2_InterruptRisingEdge = 0x1U, /*!< Interrupt on rising edge. */ + kSIUL2_InterruptFallingEdge = 0x2U, /*!< Interrupt on falling edge. */ + kSIUL2_InterruptBothEdge = 0x3U, /*!< Interrupt on both edges. */ } siul2_interrupt_config_t; +/* Typedef for interrupt callback. */ +typedef void (*siul2_cb_t)(SIUL2_Type *base, uint32_t status); /******************************************************************************* * API ******************************************************************************/ @@ -324,11 +337,12 @@ void SIUL2_PinInit(const siul2_pin_settings_t *config); * * @param base SIUL2 peripheral base pointer * @param pin pin number, 0, 1...511, see RM for available pins - * @param enable Enable output buffer + * @param enable Enable input buffer * @param inputMuxReg Pin muxing register slot selection * @param inputMux Pin muxing slot selection */ -void SIUL2_SetPinInputBuffer(SIUL2_Type *base, uint32_t pin, bool enable, uint32_t inputMuxReg, siul2_port_inputmux_t inputMux); +void SIUL2_SetPinInputBuffer( + SIUL2_Type *base, uint32_t pin, bool enable, uint32_t inputMuxReg, siul2_port_inputmux_t inputMux); /*! * @brief Set the pin Output Buffer. @@ -429,7 +443,6 @@ inline static uint32_t SIUL2_PortPinRead(SIUL2_Type *base, siul2_port_num_t port return SIUL2_PORT_READ8(SIUL2_GPDI_ADDR(base, pinIndex)); } - /*! * @brief Set the pin output. * @@ -497,7 +510,7 @@ void SIUL2_SetDmaInterruptConfig(SIUL2_Type *base, uint32_t req, siul2_interrupt * @brief Enable external interrupt. * * @param base SIUL2 peripheral base pointer - * @param req which interrupt/DMA request to set, 0...31 + * @param req which interrupt request to set, 0...31 * @param config interrupt configuration, @ref siul2_interrupt_config_t * @param filterCount Maximum filter count 0...15, < 0 disable filterCount. */ @@ -507,7 +520,7 @@ void SIUL2_EnableExtInterrupt(SIUL2_Type *base, uint32_t req, siul2_interrupt_co * @brief Enable external DMA request. * * @param base SIUL2 peripheral base pointer - * @param req which interrupt/DMA request to set, 0...31 + * @param req which DMA request to set, refer to RM for supported external DMA request number. * @param config interrupt configuration, @ref siul2_interrupt_config_t * @param filterCount Maximum filter count 0...15, < 0 disable filterCount. */ @@ -539,7 +552,7 @@ inline static void SIUL2_DisableExtDmaAndInterrupts(SIUL2_Type *base, uint32_t m * @brief Enable mutliple external interrupts. * * @param base SIUL2 peripheral base pointer - * @param mask bit mask ofinterrupt requests + * @param mask bit mask of interrupt requests * @param config interrupt configuration, @ref siul2_interrupt_config_t * @param filterCount Maximum filter count 0...15, < 0 disable filterCount. */ @@ -576,6 +589,38 @@ inline static void SIUL2_ClearExtDmaInterruptStatusFlags(SIUL2_Type *base, uint3 { base->DISR0 |= mask; } + +/*! + * @brief Get the external interrupt request number for the pin. + * + * @param pin GPIO pin number, 0...511, refer to RM for avaiable Pins. + * @return 0...31 the EIRQ number, > 32 means the pin is not capable for EIRQ. + */ +uint32_t SIUL2_GetPinEirqNumber(uint32_t pin); + +/*! + * @brief Enable EIRQ with callback. + * This function enables the interrupt for the selected EIRQ. It enables interrupt both in SIUL2 and NIVC. + * So, the callback function will be called when interrupt comes. + * + * @param base SIUL2 peripheral base pointer + * @param req which interrupt request to set, 0...31 + * @param config interrupt configuration, @ref siul2_interrupt_config_t + * @param filterCount Maximum filter count 0...15, < 0 disable filterCount. + */ +void SIUL2_EnableExtInteruptWithCallback( + SIUL2_Type *base, uint32_t req, siul2_interrupt_config_t config, int8_t filterCount, siul2_cb_t cb); + +/*! + * @brief Disable EIRQ callback. + + * This function disables the interrupt for the selected EIRQ. It disables interrupt in SIUL2 and NIVC. + * + * @param base SIUL2 peripheral base pointer + * @param req which interrupt request to set, 0...31 + */ +void SIUL2_DisableExtInterruptCallback(SIUL2_Type *base, uint32_t req); + #if defined(__cplusplus) } #endif diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/startup_MCXE31B.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/startup_MCXE31B.c index 55dfff580..50dd81de6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/startup_MCXE31B.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/startup_MCXE31B.c @@ -2,7 +2,7 @@ //***************************************************************************** // MCXE31B startup code // -// Version : 120525 +// Version : 110825 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -130,8 +130,8 @@ WEAK void Reserved57_IRQHandler(void); WEAK void SWT0_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); -WEAK void Reserved61_IRQHandler(void); -WEAK void Reserved62_IRQHandler(void); +WEAK void CTI_INT0_IRQHandler(void); +WEAK void CTI_INT1_IRQHandler(void); WEAK void Reserved63_IRQHandler(void); WEAK void FLASH_0_IRQHandler(void); WEAK void FLASH_1_IRQHandler(void); @@ -276,7 +276,7 @@ WEAK void Reserved203_IRQHandler(void); WEAK void Reserved204_IRQHandler(void); WEAK void FCCU_0_IRQHandler(void); WEAK void FCCU_1_IRQHandler(void); -WEAK void Reserved207_IRQHandler(void); +WEAK void STCU_IRQHandler(void); WEAK void MU0_B_TX_IRQHandler(void); WEAK void MU0_B_RX_IRQHandler(void); WEAK void MU0_B_IRQHandler(void); @@ -354,8 +354,8 @@ void Reserved57_DriverIRQHandler(void) ALIAS(DefaultISR); void SWT0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved61_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved62_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved63_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_1_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -417,7 +417,7 @@ void EMAC_0_DriverIRQHandler(void) ALIAS(DefaultISR); void EMAC_1_DriverIRQHandler(void) ALIAS(DefaultISR); void EMAC_2_DriverIRQHandler(void) ALIAS(DefaultISR); void EMAC_3_DriverIRQHandler(void) ALIAS(DefaultISR); -void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) ALIAS(DefaultISR4); +void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end) ALIAS(DefaultISR3); void FLEXCAN_DriverEventIRQHandler(uint32_t instance) ALIAS(DefaultISR1); void Reserved141_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved142_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -463,7 +463,7 @@ void Reserved203_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved204_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_1_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved207_DriverIRQHandler(void) ALIAS(DefaultISR); +void STCU_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_TX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_RX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -579,6 +579,8 @@ void (* const g_pfnVectors[])(void) = { ResetISR, // The reset handler #elif defined (__ICCARM__) extern void (* const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); __attribute__ ((used, section(".intvec"))) void (* const __vector_table[])(void) = { (void(*)())(uint32_t)__StackTop, // The initial stack pointer @@ -653,8 +655,8 @@ void (* const __isr_vector[])(void) = { SWT0_IRQHandler, // 58 : Platform watchdog initial time-out Reserved59_IRQHandler, // 59 : Reserved interrupt Reserved60_IRQHandler, // 60 : Reserved interrupt - Reserved61_IRQHandler, // 61 : Reserved interrupt - Reserved62_IRQHandler, // 62 : Reserved interrupt + CTI_INT0_IRQHandler, // 61 : CTI interrupt0 + CTI_INT1_IRQHandler, // 62 : CTI interrupt1 Reserved63_IRQHandler, // 63 : Reserved interrupt FLASH_0_IRQHandler, // 64 : Program or erase operation is completed FLASH_1_IRQHandler, // 65 : Main watchdog timeout interrupt @@ -799,7 +801,7 @@ void (* const __isr_vector[])(void) = { Reserved204_IRQHandler, // 204: Reserved interrupt FCCU_0_IRQHandler, // 205: Interrupt request(ALARM state) FCCU_1_IRQHandler, // 206: Interrupt request(miscellaneous conditions) - Reserved207_IRQHandler, // 207: Reserved interrupt + STCU_IRQHandler, // 207: LBIST and MBIST IRQ MU0_B_TX_IRQHandler, // 208: ORed TX interrupt to MU-0 MU0_B_RX_IRQHandler, // 209: ORed RX interrupt to MU-0 MU0_B_IRQHandler, // 210: ORed general purpose interrupt request to MU-0 @@ -888,6 +890,14 @@ extern unsigned int __bss_section_table_end; #define SRAM_BASE_ADDR 0x20400000UL #define SRAM_END_ADDR 0x20407fffUL +// ITCM1 backdoor base and end addresses +#define ITCM1_BASE_ADDR 0x11400000UL +#define ITCM1_END_ADDR 0x11407fffUL + +// DTCM1 backdoor base and end addresses +#define DTCM1_BASE_ADDR 0x21400000UL +#define DTCM1_END_ADDR 0x2140ffffUL + // patterns for initial ecc, heap and stack sections initialization #ifndef STARTUP_ECC_INITVALUE #define STARTUP_ECC_INITVALUE 0xFEEDFACECAFEBEEFULL @@ -960,6 +970,34 @@ void Reset_Handler(void) { ); #endif +#if !defined(BYPASS_ECC_ITCM1_INIT) + __asm volatile ("LDR R0, =0x11400000 \n" + "LDR R1, =0x11407FFF \n" + "LDR R2, =0 \n" + "LDR R3, =0 \n" + "LDR R4, =0 \n" + "LDR R5, =0 \n" + ".loop04: \n" + "STMIA R0!, {R2 - R5} \n" + "CMP R0, R1 \n" + "BCC.N .loop04 \n" + ); +#endif + +#if !defined(BYPASS_ECC_DTCM1_INIT) + __asm volatile ("LDR R0, =0x21400000 \n" + "LDR R1, =0x2140FFFF \n" + "LDR R2, =0 \n" + "LDR R3, =0 \n" + "LDR R4, =0 \n" + "LDR R5, =0 \n" + ".loop05: \n" + "STMIA R0!, {R2 - R5} \n" + "CMP R0, R1 \n" + "BCC.N .loop05 \n" + ); +#endif + #elif defined(__MCUXPRESSO) __attribute__ ((naked, section(".after_vectors.reset"))) void ResetISR(void) { @@ -1037,6 +1075,25 @@ void Reset_Handler(void) { } #endif +#if !defined(BYPASS_ECC_ITCM1_INIT) + __asm volatile ("LDR R0, =0x11400000 \n" + "LDR R1, =0x11407FFF \n" + "LDR R2, =0 \n" + "LDR R3, =0 \n" + "LDR R4, =0 \n" + "LDR R5, =0 \n" + "loopITCM1: \n" + "STMIA R0!, {R2 - R5} \n" + "CMP R0, R1 \n" + "BCC.N loopITCM1 \n" + ); +#endif + +#if !defined(BYPASS_ECC_DTCM1_INIT) + pDest = (uint64_t*)DTCM1_BASE_ADDR; + while (pDest < (uint64_t*)DTCM1_END_ADDR) { *pDest++ = STARTUP_ECC_INITVALUE; } +#endif + SystemInit(); #endif @@ -1266,7 +1323,7 @@ WEAK_AV void DefaultISR1(uint32_t instance) } } -WEAK_AV void DefaultISR4(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) +WEAK_AV void DefaultISR3(uint32_t instance, uint32_t start, uint32_t end) { while(1) { @@ -1504,14 +1561,14 @@ WEAK void Reserved60_IRQHandler(void) Reserved60_DriverIRQHandler(); } -WEAK void Reserved61_IRQHandler(void) +WEAK void CTI_INT0_IRQHandler(void) { - Reserved61_DriverIRQHandler(); + CTI_INT0_DriverIRQHandler(); } -WEAK void Reserved62_IRQHandler(void) +WEAK void CTI_INT1_IRQHandler(void) { - Reserved62_DriverIRQHandler(); + CTI_INT1_DriverIRQHandler(); } WEAK void Reserved63_IRQHandler(void) @@ -1831,17 +1888,17 @@ WEAK void FlexCAN0_0_IRQHandler(void) WEAK void FlexCAN0_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U, 1U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U); } WEAK void FlexCAN0_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U); } WEAK void FlexCAN0_3_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U); } WEAK void FlexCAN1_0_IRQHandler(void) @@ -1851,12 +1908,12 @@ WEAK void FlexCAN1_0_IRQHandler(void) WEAK void FlexCAN1_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U); } WEAK void FlexCAN1_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U); } WEAK void FlexCAN2_0_IRQHandler(void) @@ -1866,12 +1923,12 @@ WEAK void FlexCAN2_0_IRQHandler(void) WEAK void FlexCAN2_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U); } WEAK void FlexCAN2_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U); } WEAK void FlexCAN3_0_IRQHandler(void) @@ -1881,7 +1938,7 @@ WEAK void FlexCAN3_0_IRQHandler(void) WEAK void FlexCAN3_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(3U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(3U, 0U, 31U); } WEAK void FlexCAN4_0_IRQHandler(void) @@ -1891,7 +1948,7 @@ WEAK void FlexCAN4_0_IRQHandler(void) WEAK void FlexCAN4_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(4U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(4U, 0U, 31U); } WEAK void FlexCAN5_0_IRQHandler(void) @@ -1901,7 +1958,7 @@ WEAK void FlexCAN5_0_IRQHandler(void) WEAK void FlexCAN5_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(5U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(5U, 0U, 31U); } WEAK void Reserved141_IRQHandler(void) @@ -2234,9 +2291,9 @@ WEAK void FCCU_1_IRQHandler(void) FCCU_1_DriverIRQHandler(); } -WEAK void Reserved207_IRQHandler(void) +WEAK void STCU_IRQHandler(void) { - Reserved207_DriverIRQHandler(); + STCU_DriverIRQHandler(); } WEAK void MU0_B_TX_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/startup_MCXE31B.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/startup_MCXE31B.cpp index 55dfff580..50dd81de6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/startup_MCXE31B.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/startup_MCXE31B.cpp @@ -2,7 +2,7 @@ //***************************************************************************** // MCXE31B startup code // -// Version : 120525 +// Version : 110825 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -130,8 +130,8 @@ WEAK void Reserved57_IRQHandler(void); WEAK void SWT0_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); -WEAK void Reserved61_IRQHandler(void); -WEAK void Reserved62_IRQHandler(void); +WEAK void CTI_INT0_IRQHandler(void); +WEAK void CTI_INT1_IRQHandler(void); WEAK void Reserved63_IRQHandler(void); WEAK void FLASH_0_IRQHandler(void); WEAK void FLASH_1_IRQHandler(void); @@ -276,7 +276,7 @@ WEAK void Reserved203_IRQHandler(void); WEAK void Reserved204_IRQHandler(void); WEAK void FCCU_0_IRQHandler(void); WEAK void FCCU_1_IRQHandler(void); -WEAK void Reserved207_IRQHandler(void); +WEAK void STCU_IRQHandler(void); WEAK void MU0_B_TX_IRQHandler(void); WEAK void MU0_B_RX_IRQHandler(void); WEAK void MU0_B_IRQHandler(void); @@ -354,8 +354,8 @@ void Reserved57_DriverIRQHandler(void) ALIAS(DefaultISR); void SWT0_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved61_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved62_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT0_DriverIRQHandler(void) ALIAS(DefaultISR); +void CTI_INT1_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved63_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FLASH_1_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -417,7 +417,7 @@ void EMAC_0_DriverIRQHandler(void) ALIAS(DefaultISR); void EMAC_1_DriverIRQHandler(void) ALIAS(DefaultISR); void EMAC_2_DriverIRQHandler(void) ALIAS(DefaultISR); void EMAC_3_DriverIRQHandler(void) ALIAS(DefaultISR); -void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) ALIAS(DefaultISR4); +void FLEXCAN_DriverDataIRQHandler(uint32_t instance, uint32_t start, uint32_t end) ALIAS(DefaultISR3); void FLEXCAN_DriverEventIRQHandler(uint32_t instance) ALIAS(DefaultISR1); void Reserved141_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved142_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -463,7 +463,7 @@ void Reserved203_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved204_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_0_DriverIRQHandler(void) ALIAS(DefaultISR); void FCCU_1_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved207_DriverIRQHandler(void) ALIAS(DefaultISR); +void STCU_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_TX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_RX_DriverIRQHandler(void) ALIAS(DefaultISR); void MU0_B_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -579,6 +579,8 @@ void (* const g_pfnVectors[])(void) = { ResetISR, // The reset handler #elif defined (__ICCARM__) extern void (* const __vector_table[])(void); +/* The vector table is not needed for initialization. */ +extern void (*const __iar_init$$done[])(void) __attribute__((alias("__vector_table"))); __attribute__ ((used, section(".intvec"))) void (* const __vector_table[])(void) = { (void(*)())(uint32_t)__StackTop, // The initial stack pointer @@ -653,8 +655,8 @@ void (* const __isr_vector[])(void) = { SWT0_IRQHandler, // 58 : Platform watchdog initial time-out Reserved59_IRQHandler, // 59 : Reserved interrupt Reserved60_IRQHandler, // 60 : Reserved interrupt - Reserved61_IRQHandler, // 61 : Reserved interrupt - Reserved62_IRQHandler, // 62 : Reserved interrupt + CTI_INT0_IRQHandler, // 61 : CTI interrupt0 + CTI_INT1_IRQHandler, // 62 : CTI interrupt1 Reserved63_IRQHandler, // 63 : Reserved interrupt FLASH_0_IRQHandler, // 64 : Program or erase operation is completed FLASH_1_IRQHandler, // 65 : Main watchdog timeout interrupt @@ -799,7 +801,7 @@ void (* const __isr_vector[])(void) = { Reserved204_IRQHandler, // 204: Reserved interrupt FCCU_0_IRQHandler, // 205: Interrupt request(ALARM state) FCCU_1_IRQHandler, // 206: Interrupt request(miscellaneous conditions) - Reserved207_IRQHandler, // 207: Reserved interrupt + STCU_IRQHandler, // 207: LBIST and MBIST IRQ MU0_B_TX_IRQHandler, // 208: ORed TX interrupt to MU-0 MU0_B_RX_IRQHandler, // 209: ORed RX interrupt to MU-0 MU0_B_IRQHandler, // 210: ORed general purpose interrupt request to MU-0 @@ -888,6 +890,14 @@ extern unsigned int __bss_section_table_end; #define SRAM_BASE_ADDR 0x20400000UL #define SRAM_END_ADDR 0x20407fffUL +// ITCM1 backdoor base and end addresses +#define ITCM1_BASE_ADDR 0x11400000UL +#define ITCM1_END_ADDR 0x11407fffUL + +// DTCM1 backdoor base and end addresses +#define DTCM1_BASE_ADDR 0x21400000UL +#define DTCM1_END_ADDR 0x2140ffffUL + // patterns for initial ecc, heap and stack sections initialization #ifndef STARTUP_ECC_INITVALUE #define STARTUP_ECC_INITVALUE 0xFEEDFACECAFEBEEFULL @@ -960,6 +970,34 @@ void Reset_Handler(void) { ); #endif +#if !defined(BYPASS_ECC_ITCM1_INIT) + __asm volatile ("LDR R0, =0x11400000 \n" + "LDR R1, =0x11407FFF \n" + "LDR R2, =0 \n" + "LDR R3, =0 \n" + "LDR R4, =0 \n" + "LDR R5, =0 \n" + ".loop04: \n" + "STMIA R0!, {R2 - R5} \n" + "CMP R0, R1 \n" + "BCC.N .loop04 \n" + ); +#endif + +#if !defined(BYPASS_ECC_DTCM1_INIT) + __asm volatile ("LDR R0, =0x21400000 \n" + "LDR R1, =0x2140FFFF \n" + "LDR R2, =0 \n" + "LDR R3, =0 \n" + "LDR R4, =0 \n" + "LDR R5, =0 \n" + ".loop05: \n" + "STMIA R0!, {R2 - R5} \n" + "CMP R0, R1 \n" + "BCC.N .loop05 \n" + ); +#endif + #elif defined(__MCUXPRESSO) __attribute__ ((naked, section(".after_vectors.reset"))) void ResetISR(void) { @@ -1037,6 +1075,25 @@ void Reset_Handler(void) { } #endif +#if !defined(BYPASS_ECC_ITCM1_INIT) + __asm volatile ("LDR R0, =0x11400000 \n" + "LDR R1, =0x11407FFF \n" + "LDR R2, =0 \n" + "LDR R3, =0 \n" + "LDR R4, =0 \n" + "LDR R5, =0 \n" + "loopITCM1: \n" + "STMIA R0!, {R2 - R5} \n" + "CMP R0, R1 \n" + "BCC.N loopITCM1 \n" + ); +#endif + +#if !defined(BYPASS_ECC_DTCM1_INIT) + pDest = (uint64_t*)DTCM1_BASE_ADDR; + while (pDest < (uint64_t*)DTCM1_END_ADDR) { *pDest++ = STARTUP_ECC_INITVALUE; } +#endif + SystemInit(); #endif @@ -1266,7 +1323,7 @@ WEAK_AV void DefaultISR1(uint32_t instance) } } -WEAK_AV void DefaultISR4(uint32_t instance, uint32_t start, uint32_t end, uint32_t type) +WEAK_AV void DefaultISR3(uint32_t instance, uint32_t start, uint32_t end) { while(1) { @@ -1504,14 +1561,14 @@ WEAK void Reserved60_IRQHandler(void) Reserved60_DriverIRQHandler(); } -WEAK void Reserved61_IRQHandler(void) +WEAK void CTI_INT0_IRQHandler(void) { - Reserved61_DriverIRQHandler(); + CTI_INT0_DriverIRQHandler(); } -WEAK void Reserved62_IRQHandler(void) +WEAK void CTI_INT1_IRQHandler(void) { - Reserved62_DriverIRQHandler(); + CTI_INT1_DriverIRQHandler(); } WEAK void Reserved63_IRQHandler(void) @@ -1831,17 +1888,17 @@ WEAK void FlexCAN0_0_IRQHandler(void) WEAK void FlexCAN0_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U, 1U); + FLEXCAN_DriverDataIRQHandler(0U, 0U, 31U); } WEAK void FlexCAN0_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 32U, 63U); } WEAK void FlexCAN0_3_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U, 0U); + FLEXCAN_DriverDataIRQHandler(0U, 64U, 95U); } WEAK void FlexCAN1_0_IRQHandler(void) @@ -1851,12 +1908,12 @@ WEAK void FlexCAN1_0_IRQHandler(void) WEAK void FlexCAN1_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 0U, 31U); } WEAK void FlexCAN1_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(1U, 32U, 63U); } WEAK void FlexCAN2_0_IRQHandler(void) @@ -1866,12 +1923,12 @@ WEAK void FlexCAN2_0_IRQHandler(void) WEAK void FlexCAN2_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 0U, 31U); } WEAK void FlexCAN2_2_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U, 0U); + FLEXCAN_DriverDataIRQHandler(2U, 32U, 63U); } WEAK void FlexCAN3_0_IRQHandler(void) @@ -1881,7 +1938,7 @@ WEAK void FlexCAN3_0_IRQHandler(void) WEAK void FlexCAN3_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(3U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(3U, 0U, 31U); } WEAK void FlexCAN4_0_IRQHandler(void) @@ -1891,7 +1948,7 @@ WEAK void FlexCAN4_0_IRQHandler(void) WEAK void FlexCAN4_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(4U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(4U, 0U, 31U); } WEAK void FlexCAN5_0_IRQHandler(void) @@ -1901,7 +1958,7 @@ WEAK void FlexCAN5_0_IRQHandler(void) WEAK void FlexCAN5_1_IRQHandler(void) { - FLEXCAN_DriverDataIRQHandler(5U, 0U, 31U, 0U); + FLEXCAN_DriverDataIRQHandler(5U, 0U, 31U); } WEAK void Reserved141_IRQHandler(void) @@ -2234,9 +2291,9 @@ WEAK void FCCU_1_IRQHandler(void) FCCU_1_DriverIRQHandler(); } -WEAK void Reserved207_IRQHandler(void) +WEAK void STCU_IRQHandler(void) { - Reserved207_DriverIRQHandler(); + STCU_DriverIRQHandler(); } WEAK void MU0_B_TX_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/system_MCXE31B.c b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/system_MCXE31B.c index 03a7e85e5..7eb4bcb5d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/system_MCXE31B.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/system_MCXE31B.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250310 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250811 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,6 +25,8 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -32,7 +34,7 @@ /*! * @file MCXE31B * @version 1.0 - * @date 2025-03-10 + * @date 2025-08-11 * @brief Device specific configuration file for MCXE31B (implementation file) * * Provides a system configuration function and a global variable that contains @@ -56,9 +58,18 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit(void) { +#if (DISABLE_WDOG) + if ((SWT_0->CR & SWT_CR_WEN_MASK) != 0U) + { + SWT_0->SR = 0xC520; + SWT_0->SR = 0xD928; + SWT_0->CR &= ~SWT_CR_WEN_MASK; + } +#endif /* (DISABLE_WDOG) */ + #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ /* Enable flash controller code and data line read and prefetch buffers */ PFLASH->PFCR[0] = @@ -80,9 +91,9 @@ void SystemInit(void) ---------------------------------------------------------------------------- */ void SystemCoreClockUpdate(void) { - uint32_t div = 0U; - uint32_t freq = 0U; - uint32_t temp = 0U; + uint32_t div = 0U; + uint32_t freq = 0U; + uint32_t temp = 0U; uint64_t temp64 = 0U; switch (MC_CGM->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) @@ -98,8 +109,8 @@ void SystemCoreClockUpdate(void) if ((PLL->PLLFD & PLL_PLLFD_SDMEN_MASK) != 0U) /* Fractional mode. */ { - freq = CLK_XTAL_OSC_CLK / 1000U / div; - temp = (PLL->PLLDV & PLL_PLLDV_MFI_MASK) >> PLL_PLLDV_MFI_SHIFT; + freq = CLK_XTAL_OSC_CLK / 1000U / div; + temp = (PLL->PLLDV & PLL_PLLDV_MFI_MASK) >> PLL_PLLDV_MFI_SHIFT; temp64 = (uint64_t)temp * 18432U + (uint64_t)(PLL->PLLFD & PLL_PLLFD_MFN_MASK); temp64 = temp64 * 1000U / 18432U; freq = (uint32_t)((uint64_t)freq * temp64); diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/system_MCXE31B.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/system_MCXE31B.h index a84844dfd..ef3b25a33 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/system_MCXE31B.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE31B/system_MCXE31B.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXE31 RM Rev1 -** Version: rev. 0.1, 2024-11-19 -** Build: b250310 +** Reference manual: MCXE31 RM Rev2 +** Version: rev. 1.0, 2025-07-18 +** Build: b250811 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,6 +25,8 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ @@ -32,7 +34,7 @@ /*! * @file MCXE31B * @version 1.0 - * @date 2025-03-10 + * @date 2025-08-11 * @brief Device specific configuration file for MCXE31B (header file) * * Provides a system configuration function and a global variable that contains @@ -49,6 +51,10 @@ #define DEFAULT_SYSTEM_CLOCK 48000000U #define CLK_FIRC_CLOCK_FREQ 48000000U /**< FIRC clock frequency */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_ADC.h index 5ac85911f..6605cde24 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_ADC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_ADC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for ADC * * CMSIS Peripheral Access Layer for ADC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_AXBS_LITE.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_AXBS_LITE.h index 33d6abd93..615e2a50e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_AXBS_LITE.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_AXBS_LITE.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for AXBS_LITE @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_AXBS_LITE.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for AXBS_LITE * * CMSIS Peripheral Access Layer for AXBS_LITE diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_BCTU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_BCTU.h index 3b3a4429d..bc4e41bfe 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_BCTU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_BCTU.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for BCTU @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_BCTU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for BCTU * * CMSIS Peripheral Access Layer for BCTU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CAN.h index 9fbe6e4fb..4219357a6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CAN.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CAN.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CAN * * CMSIS Peripheral Access Layer for CAN diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CMU_FC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CMU_FC.h index c4fe4acad..7fe505f17 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CMU_FC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CMU_FC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMU_FC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CMU_FC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CMU_FC * * CMSIS Peripheral Access Layer for CMU_FC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CMU_FM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CMU_FM.h index 2eaa7d6f0..ee78bbdc6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CMU_FM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CMU_FM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMU_FM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CMU_FM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CMU_FM * * CMSIS Peripheral Access Layer for CMU_FM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CONFIGURATION.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CONFIGURATION.h index 0a5d4f5f1..b0b39b8da 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CONFIGURATION.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CONFIGURATION.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CONFIGURATION @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CONFIGURATION.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CONFIGURATION * * CMSIS Peripheral Access Layer for CONFIGURATION diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CRC.h index 562ffeca0..837aa3e41 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_CRC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CRC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CRC * * CMSIS Peripheral Access Layer for CRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DCM.h index 7576a07a9..e7145d7be 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DCM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DCM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DCM * * CMSIS Peripheral Access Layer for DCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DCM_GPR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DCM_GPR.h index a9190105d..fa665e7c1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DCM_GPR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DCM_GPR.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCM_GPR @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DCM_GPR.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DCM_GPR * * CMSIS Peripheral Access Layer for DCM_GPR diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DMA.h index 94c00fa23..d3f757f45 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DMA.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DMA.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DMA * * CMSIS Peripheral Access Layer for DMA diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DMAMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DMAMUX.h index 2c23e57bb..8f61d82c9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DMAMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_DMAMUX.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMAMUX @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DMAMUX.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DMAMUX * * CMSIS Peripheral Access Layer for DMAMUX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EIM.h index 652dc8cdd..61a1cd72d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EIM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EIM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for EIM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_EIM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for EIM * * CMSIS Peripheral Access Layer for EIM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EMAC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EMAC.h index 0674cd9a8..e38c5d642 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EMAC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EMAC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for EMAC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_EMAC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for EMAC * * CMSIS Peripheral Access Layer for EMAC @@ -77,6 +79,14 @@ * @{ */ +/** EMAC - Size of Registers Arrays */ +#define EMAC_MAC_TX_FLOW_CTRL_Q_COUNT 1u +#define EMAC_MAC_RXQ_CTRL_COUNT 3u +#define EMAC_MAC_HW_FEAT_COUNT 4u +#define EMAC_MAC_ADDRESS_COUNT 3u +#define EMAC_MTL_QUEUE_COUNT 2u +#define EMAC_DMA_CH_COUNT 2u + /** EMAC - Register Layout Typedef */ typedef struct { __IO uint32_t MAC_CONFIGURATION; /**< MAC Configuration, offset: 0x0 */ @@ -112,14 +122,12 @@ typedef struct { }; __IO uint32_t MAC_INNER_VLAN_INCL; /**< Inner VLAN Tag Inclusion Or Replacement, offset: 0x64 */ uint8_t RESERVED_2[8]; - __IO uint32_t MAC_Q0_TX_FLOW_CTRL; /**< MAC Q0 Tx Flow Control, offset: 0x70 */ + __IO uint32_t MAC_TX_FLOW_CTRL_Q[EMAC_MAC_TX_FLOW_CTRL_Q_COUNT]; /**< MAC Q0 Tx Flow Control, array offset: 0x70, array step: 0x4 */ uint8_t RESERVED_3[28]; __IO uint32_t MAC_RX_FLOW_CTRL; /**< MAC Receive Flow Control, offset: 0x90 */ __IO uint32_t MAC_RXQ_CTRL4; /**< MAC RxQ Control 4, offset: 0x94 */ uint8_t RESERVED_4[8]; - __IO uint32_t MAC_RXQ_CTRL0; /**< MAC RxQ Control 0, offset: 0xA0 */ - __IO uint32_t MAC_RXQ_CTRL1; /**< Receive Queue Control 1, offset: 0xA4 */ - __IO uint32_t MAC_RXQ_CTRL2; /**< MAC RxQ Control 2, offset: 0xA8 */ + __IO uint32_t MAC_RXQ_CTRL[EMAC_MAC_RXQ_CTRL_COUNT]; /**< MAC RxQ Control 0..MAC RxQ Control 2, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_5[4]; __I uint32_t MAC_INTERRUPT_STATUS; /**< MAC Interrupt Status, offset: 0xB0 */ __IO uint32_t MAC_INTERRUPT_ENABLE; /**< MAC Interrupt Enable, offset: 0xB4 */ @@ -128,10 +136,7 @@ typedef struct { __I uint32_t MAC_VERSION; /**< MAC Version, offset: 0x110 */ __I uint32_t MAC_DEBUG; /**< MAC Debug, offset: 0x114 */ uint8_t RESERVED_7[4]; - __I uint32_t MAC_HW_FEATURE0; /**< MAC Hardware Feature 0, offset: 0x11C */ - __I uint32_t MAC_HW_FEATURE1; /**< MAC Hardware Feature 1, offset: 0x120 */ - __I uint32_t MAC_HW_FEATURE2; /**< MAC Hardware Feature 2, offset: 0x124 */ - __I uint32_t MAC_HW_FEATURE3; /**< MAC Hardware Feature 3, offset: 0x128 */ + __I uint32_t MAC_HW_FEAT[EMAC_MAC_HW_FEAT_COUNT]; /**< MAC Hardware Feature 0..MAC Hardware Feature 3, array offset: 0x11C, array step: 0x4 */ uint8_t RESERVED_8[20]; __I uint32_t MAC_DPP_FSM_INTERRUPT_STATUS; /**< MAC DPP FSM Interrupt Status, offset: 0x140 */ uint8_t RESERVED_9[4]; @@ -148,12 +153,10 @@ typedef struct { __I uint32_t MAC_PRESN_TIME_NS; /**< MAC Presentation Time, offset: 0x240 */ __IO uint32_t MAC_PRESN_TIME_UPDT; /**< MAC Presentation Time Update, offset: 0x244 */ uint8_t RESERVED_13[184]; - __IO uint32_t MAC_ADDRESS0_HIGH; /**< MAC Address 0 High, offset: 0x300 */ - __IO uint32_t MAC_ADDRESS0_LOW; /**< MAC Address 0 Low, offset: 0x304 */ - __IO uint32_t MAC_ADDRESS1_HIGH; /**< MAC Address 1 High, offset: 0x308 */ - __IO uint32_t MAC_ADDRESS1_LOW; /**< MAC Address 1 Low, offset: 0x30C */ - __IO uint32_t MAC_ADDRESS2_HIGH; /**< MAC Address 2 High, offset: 0x310 */ - __IO uint32_t MAC_ADDRESS2_LOW; /**< MAC Address 2 Low, offset: 0x314 */ + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t HIGH; /**< MAC Address 0 High..MAC Address 2 High, array offset: 0x300, array step: 0x8 */ + __IO uint32_t LOW; /**< MAC Address 0 Low..MAC Address 2 Low, array offset: 0x304, array step: 0x8 */ + } MAC_ADDRESS[EMAC_MAC_ADDRESS_COUNT]; uint8_t RESERVED_14[1000]; __IO uint32_t MMC_CONTROL; /**< MMC Control, offset: 0x700 */ __I uint32_t MMC_RX_INTERRUPT; /**< MMC Receive Interrupt, offset: 0x704 */ @@ -343,99 +346,64 @@ typedef struct { uint8_t RESERVED_43[4]; __IO uint32_t MTL_DPP_CONTROL; /**< MTL DPP Control, offset: 0xCE0 */ uint8_t RESERVED_44[28]; - __IO uint32_t MTL_TXQ0_OPERATION_MODE; /**< MTL Tx Queue 0 Operation Mode, offset: 0xD00 */ - __I uint32_t MTL_TXQ0_UNDERFLOW; /**< MTL Tx Queue 0 Underflow, offset: 0xD04 */ - __I uint32_t MTL_TXQ0_DEBUG; /**< MTL Tx Queue 0 Debug, offset: 0xD08 */ - uint8_t RESERVED_45[8]; - __I uint32_t MTL_TXQ0_ETS_STATUS; /**< MTL Tx Queue 0 ETS Status, offset: 0xD14 */ - __IO uint32_t MTL_TXQ0_QUANTUM_WEIGHT; /**< MTL Tx Queue Quantum Weight, offset: 0xD18 */ - uint8_t RESERVED_46[16]; - __IO uint32_t MTL_Q0_INTERRUPT_CONTROL_STATUS; /**< MTL Queue 0 Interrupt Control Status, offset: 0xD2C */ - __IO uint32_t MTL_RXQ0_OPERATION_MODE; /**< MTL Rx Queue 0 Operation Mode, offset: 0xD30 */ - __I uint32_t MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT; /**< MTL Rx Queue Missed Packet Overflow Count, offset: 0xD34 */ - __I uint32_t MTL_RXQ0_DEBUG; /**< MTL Rx Queue 0 Debug, offset: 0xD38 */ - __IO uint32_t MTL_RXQ0_CONTROL; /**< MTL Rx Queue 0 Control 0, offset: 0xD3C */ - __IO uint32_t MTL_TXQ1_OPERATION_MODE; /**< MTL Tx Queue 1 Operation Mode, offset: 0xD40 */ - __I uint32_t MTL_TXQ1_UNDERFLOW; /**< MTL Tx Queue 1 Underflow, offset: 0xD44 */ - __I uint32_t MTL_TXQ1_DEBUG; /**< MTL Tx Queue 1 Debug, offset: 0xD48 */ - uint8_t RESERVED_47[4]; - __IO uint32_t MTL_TXQ1_ETS_CONTROL; /**< MTL Tx Queue 1 ETS Control, offset: 0xD50 */ - __I uint32_t MTL_TXQ1_ETS_STATUS; /**< MTL Tx Queue 1 ETS Status, offset: 0xD54 */ - __IO uint32_t MTL_TXQ1_QUANTUM_WEIGHT; /**< MTL Tx Queue 1 Quantum Weight, offset: 0xD58 */ - __IO uint32_t MTL_TXQ1_SENDSLOPECREDIT; /**< MTL Tx Queue 1 Sendslope Credit, offset: 0xD5C */ - __IO uint32_t MTL_TXQ1_HICREDIT; /**< MTL Tx Queue 1 HiCredit, offset: 0xD60 */ - __IO uint32_t MTL_TXQ1_LOCREDIT; /**< MTL Tx Queue 1 LoCredit, offset: 0xD64 */ - uint8_t RESERVED_48[4]; - __IO uint32_t MTL_Q1_INTERRUPT_CONTROL_STATUS; /**< MTL Queue 1 Interrupt Control Status, offset: 0xD6C */ - __IO uint32_t MTL_RXQ1_OPERATION_MODE; /**< MTL Rx Queue 1 Operation Mode, offset: 0xD70 */ - __I uint32_t MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT; /**< MTL Rx Queue 1 Missed Packet Overflow Counter, offset: 0xD74 */ - __I uint32_t MTL_RXQ1_DEBUG; /**< MTL Rx Queue 1 Debug, offset: 0xD78 */ - __IO uint32_t MTL_RXQ1_CONTROL; /**< MTL Rx Queue 1 Control, offset: 0xD7C */ - uint8_t RESERVED_49[640]; + struct { /* offset: 0xD00, array step: 0x40 */ + __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL Tx Queue 0 Operation Mode..MTL Tx Queue 1 Operation Mode, array offset: 0xD00, array step: 0x40 */ + __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL Tx Queue 0 Underflow..MTL Tx Queue 1 Underflow, array offset: 0xD04, array step: 0x40 */ + __I uint32_t MTL_TXQX_DBG; /**< MTL Tx Queue 0 Debug..MTL Tx Queue 1 Debug, array offset: 0xD08, array step: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL Tx Queue 1 ETS Control, array offset: 0xD10, array step: 0x40, valid indices: [1] */ + __I uint32_t MTL_TXQX_ETS_STAT; /**< MTL Tx Queue 0 ETS Status..MTL Tx Queue 1 ETS Status, array offset: 0xD14, array step: 0x40 */ + __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< MTL Tx Queue Quantum Weight..MTL Tx Queue 1 Quantum Weight, array offset: 0xD18, array step: 0x40 */ + __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL Tx Queue 1 Sendslope Credit, array offset: 0xD1C, array step: 0x40, valid indices: [1] */ + __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL Tx Queue 1 HiCredit, array offset: 0xD20, array step: 0x40, valid indices: [1] */ + __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL Tx Queue 1 LoCredit, array offset: 0xD24, array step: 0x40, valid indices: [1] */ + uint8_t RESERVED_1[4]; + __IO uint32_t MTL_QX_INTCTRL_STAT; /**< MTL Queue 0 Interrupt Control Status..MTL Queue 1 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */ + __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL Rx Queue 0 Operation Mode..MTL Rx Queue 1 Operation Mode, array offset: 0xD30, array step: 0x40 */ + __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL Rx Queue Missed Packet Overflow Count..MTL Rx Queue 1 Missed Packet Overflow Counter, array offset: 0xD34, array step: 0x40 */ + __I uint32_t MTL_RXQX_DBG; /**< MTL Rx Queue 0 Debug..MTL Rx Queue 1 Debug, array offset: 0xD38, array step: 0x40 */ + __IO uint32_t MTL_RXQX_CTRL; /**< MTL Rx Queue 0 Control 0..MTL Rx Queue 1 Control, array offset: 0xD3C, array step: 0x40 */ + } MTL_QUEUE[EMAC_MTL_QUEUE_COUNT]; + uint8_t RESERVED_45[640]; __IO uint32_t DMA_MODE; /**< DMA Mode, offset: 0x1000 */ __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus Mode, offset: 0x1004 */ __I uint32_t DMA_INTERRUPT_STATUS; /**< DMA Interrupt Status, offset: 0x1008 */ __I uint32_t DMA_DEBUG_STATUS0; /**< DMA Debug Status 0, offset: 0x100C */ - uint8_t RESERVED_50[64]; + uint8_t RESERVED_46[64]; __IO uint32_t DMA_TBS_CTRL; /**< DMA TBS Control, offset: 0x1050 */ - uint8_t RESERVED_51[44]; + uint8_t RESERVED_47[44]; __I uint32_t DMA_SAFETY_INTERRUPT_STATUS; /**< DMA Safety Interrupt Status, offset: 0x1080 */ - uint8_t RESERVED_52[124]; - __IO uint32_t DMA_CH0_CONTROL; /**< DMA Channel 0 Control, offset: 0x1100 */ - __IO uint32_t DMA_CH0_TX_CONTROL; /**< DMA Channel Tx Control, offset: 0x1104 */ - __IO uint32_t DMA_CH0_RX_CONTROL; /**< DMA Channel Rx Control, offset: 0x1108 */ - uint8_t RESERVED_53[8]; - __IO uint32_t DMA_CH0_TXDESC_LIST_ADDRESS; /**< DMA Channel 0 Tx Descriptor List Address, offset: 0x1114 */ - uint8_t RESERVED_54[4]; - __IO uint32_t DMA_CH0_RXDESC_LIST_ADDRESS; /**< DMA Channel 0 Rx Descriptor List Address, offset: 0x111C */ - __IO uint32_t DMA_CH0_TXDESC_TAIL_POINTER; /**< DMA Channel 0 Tx Descriptor Tail Pointer, offset: 0x1120 */ - uint8_t RESERVED_55[4]; - __IO uint32_t DMA_CH0_RXDESC_TAIL_POINTER; /**< DMA Channeli 0 Rx Descriptor List Pointer, offset: 0x1128 */ - __IO uint32_t DMA_CH0_TXDESC_RING_LENGTH; /**< DMA Channel 0 Tx Descriptor Ring Length, offset: 0x112C */ - __IO uint32_t DMA_CH0_RXDESC_RING_LENGTH; /**< DMA Channel 0 Rx Descriptor Ring Length, offset: 0x1130 */ - __IO uint32_t DMA_CH0_INTERRUPT_ENABLE; /**< DMA Channel 0 Interrupt Enable, offset: 0x1134 */ - __IO uint32_t DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER; /**< DMA Channel 0 Rx Interrupt Watchdog Timer, offset: 0x1138 */ - __IO uint32_t DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS; /**< DMA Channel 0 Slot Function Control Status, offset: 0x113C */ - uint8_t RESERVED_56[4]; - __I uint32_t DMA_CH0_CURRENT_APP_TXDESC; /**< DMA Channel 0 Current Application Transmit Descriptor, offset: 0x1144 */ - uint8_t RESERVED_57[4]; - __I uint32_t DMA_CH0_CURRENT_APP_RXDESC; /**< DMA Channel 0 Current Application Receive Descriptor, offset: 0x114C */ - uint8_t RESERVED_58[4]; - __I uint32_t DMA_CH0_CURRENT_APP_TXBUFFER; /**< DMA Channel 0 Current Application Transmit Descriptor, offset: 0x1154 */ - uint8_t RESERVED_59[4]; - __I uint32_t DMA_CH0_CURRENT_APP_RXBUFFER; /**< DMA Channel 0 Current Application Receive Buffer, offset: 0x115C */ - __IO uint32_t DMA_CH0_STATUS; /**< DMA Channel 0 Status, offset: 0x1160 */ - __I uint32_t DMA_CH0_MISS_FRAME_CNT; /**< DMA Channel 0 Miss Frame Counter, offset: 0x1164 */ - __I uint32_t DMA_CH0_RXP_ACCEPT_CNT; /**< DMA Channel 0 Rx Parser Accept Count, offset: 0x1168 */ - __I uint32_t DMA_CH0_RX_ERI_CNT; /**< DMA Channel 0 Rx ERI Count, offset: 0x116C */ - uint8_t RESERVED_60[16]; - __IO uint32_t DMA_CH1_CONTROL; /**< DMA Channel 1 Control, offset: 0x1180 */ - __IO uint32_t DMA_CH1_TX_CONTROL; /**< DMA Channel 1 Tx Control, offset: 0x1184 */ - __IO uint32_t DMA_CH1_RX_CONTROL; /**< DMA Channel 1 Rx Control, offset: 0x1188 */ - uint8_t RESERVED_61[8]; - __IO uint32_t DMA_CH1_TXDESC_LIST_ADDRESS; /**< DMA Channel 1 Tx Descriptor List Address, offset: 0x1194 */ - uint8_t RESERVED_62[4]; - __IO uint32_t DMA_CH1_RXDESC_LIST_ADDRESS; /**< DMA Channel 1 Rx Descriptor List Address, offset: 0x119C */ - __IO uint32_t DMA_CH1_TXDESC_TAIL_POINTER; /**< DMA Channel 1 Tx Descriptor Tail Pointer, offset: 0x11A0 */ - uint8_t RESERVED_63[4]; - __IO uint32_t DMA_CH1_RXDESC_TAIL_POINTER; /**< DMA Channel 1 Rx Descriptor Tail Pointer, offset: 0x11A8 */ - __IO uint32_t DMA_CH1_TXDESC_RING_LENGTH; /**< DMA Channel 1 Tx Descriptor Ring Length, offset: 0x11AC */ - __IO uint32_t DMA_CH1_RXDESC_RING_LENGTH; /**< DMA Channel 1 Rx Descriptor Ring Length, offset: 0x11B0 */ - __IO uint32_t DMA_CH1_INTERRUPT_ENABLE; /**< DMA Channel 1 Interrupt Enable, offset: 0x11B4 */ - __IO uint32_t DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER; /**< DMA Channel 1 Rx Interrupt Watchdog Timer, offset: 0x11B8 */ - __IO uint32_t DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS; /**< DMA Channel 1 Slot Function Control Status, offset: 0x11BC */ - uint8_t RESERVED_64[4]; - __I uint32_t DMA_CH1_CURRENT_APP_TXDESC; /**< DMA Channel 1 Current Application Transmit Descriptor, offset: 0x11C4 */ - uint8_t RESERVED_65[4]; - __I uint32_t DMA_CH1_CURRENT_APP_RXDESC; /**< DMA Channel 1 Current Application Receive Descriptor, offset: 0x11CC */ - uint8_t RESERVED_66[4]; - __I uint32_t DMA_CH1_CURRENT_APP_TXBUFFER; /**< DMA Channel 1 Current Application Transmit Buffer, offset: 0x11D4 */ - uint8_t RESERVED_67[4]; - __I uint32_t DMA_CH1_CURRENT_APP_RXBUFFER; /**< DMA Channel 1 Current Application Receive Buffer, offset: 0x11DC */ - __IO uint32_t DMA_CH1_STATUS; /**< DMA Channel 1 Status, offset: 0x11E0 */ - __I uint32_t DMA_CH1_MISS_FRAME_CNT; /**< DMA Channel 1 Miss Frame Counter, offset: 0x11E4 */ - __I uint32_t DMA_CH1_RXP_ACCEPT_CNT; /**< DMA Channel 1 Rx Parser Accept Count, offset: 0x11E8 */ - __I uint32_t DMA_CH1_RX_ERI_CNT; /**< DMA Channel 1 Rx ERI Count, offset: 0x11EC */ + uint8_t RESERVED_48[124]; + struct { /* offset: 0x1100, array step: 0x80 */ + __IO uint32_t DMA_CHX_CTRL; /**< DMA Channel 0 Control..DMA Channel 1 Control, array offset: 0x1100, array step: 0x80 */ + __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channel Tx Control..DMA Channel 1 Tx Control, array offset: 0x1104, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channel Rx Control..DMA Channel 1 Rx Control, array offset: 0x1108, array step: 0x80 */ + uint8_t RESERVED_0[8]; + __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< DMA Channel 0 Tx Descriptor List Address..DMA Channel 1 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< DMA Channel 0 Rx Descriptor List Address..DMA Channel 1 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */ + __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< DMA Channel 0 Tx Descriptor Tail Pointer..DMA Channel 1 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */ + uint8_t RESERVED_2[4]; + __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< DMA Channeli 0 Rx Descriptor List Pointer..DMA Channel 1 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */ + __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< DMA Channel 0 Tx Descriptor Ring Length..DMA Channel 1 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */ + __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< DMA Channel 0 Rx Descriptor Ring Length..DMA Channel 1 Rx Descriptor Ring Length, array offset: 0x1130, array step: 0x80 */ + __IO uint32_t DMA_CHX_INT_EN; /**< DMA Channel 0 Interrupt Enable..DMA Channel 1 Interrupt Enable, array offset: 0x1134, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< DMA Channel 0 Rx Interrupt Watchdog Timer..DMA Channel 1 Rx Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ + __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< DMA Channel 0 Slot Function Control Status..DMA Channel 1 Slot Function Control Status, array offset: 0x113C, array step: 0x80 */ + uint8_t RESERVED_3[4]; + __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< DMA Channel 0 Current Application Transmit Descriptor..DMA Channel 1 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */ + uint8_t RESERVED_4[4]; + __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< DMA Channel 0 Current Application Receive Descriptor..DMA Channel 1 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */ + uint8_t RESERVED_5[4]; + __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< DMA Channel 0 Current Application Transmit Descriptor..DMA Channel 1 Current Application Transmit Buffer, array offset: 0x1154, array step: 0x80 */ + uint8_t RESERVED_6[4]; + __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< DMA Channel 0 Current Application Receive Buffer..DMA Channel 1 Current Application Receive Buffer, array offset: 0x115C, array step: 0x80 */ + __IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, array offset: 0x1160, array step: 0x80 */ + __I uint32_t DMA_CHX_MISS_FRAME_CNT; /**< DMA Channel 0 Miss Frame Counter..DMA Channel 1 Miss Frame Counter, array offset: 0x1164, array step: 0x80 */ + __I uint32_t DMA_CHX_RXP_ACCEPT_CNT; /**< DMA Channel 0 Rx Parser Accept Count..DMA Channel 1 Rx Parser Accept Count, array offset: 0x1168, array step: 0x80 */ + __I uint32_t DMA_CHX_RX_ERI_CNT; /**< DMA Channel 0 Rx ERI Count..DMA Channel 1 Rx ERI Count, array offset: 0x116C, array step: 0x80 */ + uint8_t RESERVED_7[16]; + } DMA_CH[EMAC_DMA_CH_COUNT]; } EMAC_Type; /* ---------------------------------------------------------------------------- @@ -1676,27 +1644,27 @@ typedef struct { #define EMAC_MAC_INNER_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & EMAC_MAC_INNER_VLAN_INCL_VLTI_MASK) /*! @} */ -/*! @name MAC_Q0_TX_FLOW_CTRL - MAC Q0 Tx Flow Control */ +/*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control */ /*! @{ */ -#define EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK (0x1U) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT (0U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U) /*! FCB_BPA - Flow Control Busy Or Backpressure Activate * 0b0..Flow control busy or backpressure activate is disabled * 0b1..Flow control busy or backpressure activate is enabled */ -#define EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK) +#define EMAC_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & EMAC_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK (0x2U) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT (1U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U) /*! TFE - Transmit Flow Control Enable * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK) +#define EMAC_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & EMAC_MAC_TX_FLOW_CTRL_Q_TFE_MASK) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK (0x70U) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT (4U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) /*! PLT - Pause Low Threshold * 0b000..Pause time minus 4 slot times (PT is 4 slot times) * 0b001..Pause time minus 28 slot times (PT is 28 slot times) @@ -1706,20 +1674,20 @@ typedef struct { * 0b101..Pause time minus 512 slot times (PT is 512 slot times) * 0b110..Reserved */ -#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK) +#define EMAC_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & EMAC_MAC_TX_FLOW_CTRL_Q_PLT_MASK) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK (0x80U) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT (7U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) /*! DZPQ - Disable Zero-Quanta Pause * 0b0..Enabled * 0b1..Disabled */ -#define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK) +#define EMAC_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & EMAC_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFF0000U) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT (16U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U) +#define EMAC_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U) /*! PT - Pause Time */ -#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK) +#define EMAC_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & EMAC_MAC_TX_FLOW_CTRL_Q_PT_MASK) /*! @} */ /*! @name MAC_RX_FLOW_CTRL - MAC Receive Flow Control */ @@ -1785,35 +1753,31 @@ typedef struct { #define EMAC_MAC_RXQ_CTRL4_VFFQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & EMAC_MAC_RXQ_CTRL4_VFFQ_MASK) /*! @} */ -/*! @name MAC_RXQ_CTRL0 - MAC RxQ Control 0 */ +/*! @name MAC_RXQ_CTRL - MAC RxQ Control 0..MAC RxQ Control 2 */ /*! @{ */ -#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK (0x3U) -#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT (0U) +#define EMAC_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U) +#define EMAC_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U) /*! RXQ0EN - Receive Queue 0 Enable * 0b00..Queue not enabled * 0b01..Queue enabled for AV * 0b10..Queue enabled for DCB/generic * 0b11..Reserved */ -#define EMAC_MAC_RXQ_CTRL0_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT)) & EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK) +#define EMAC_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & EMAC_MAC_RXQ_CTRL_RXQ0EN_MASK) -#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK (0xCU) -#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT (2U) +#define EMAC_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU) +#define EMAC_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U) /*! RXQ1EN - Receive Queue 1 Enable * 0b00..Queue not enabled * 0b01..Queue enabled for AV * 0b10..Queue enabled for DCB/generic * 0b11..Reserved */ -#define EMAC_MAC_RXQ_CTRL0_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT)) & EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK) -/*! @} */ - -/*! @name MAC_RXQ_CTRL1 - Receive Queue Control 1 */ -/*! @{ */ +#define EMAC_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & EMAC_MAC_RXQ_CTRL_RXQ1EN_MASK) -#define EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK (0x7U) -#define EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT (0U) +#define EMAC_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U) +#define EMAC_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U) /*! AVCPQ - AV Untagged Control Packets Queue * 0b000..Receive queue 0 * 0b001..Receive queue 1 @@ -1824,10 +1788,10 @@ typedef struct { * 0b110..Receive queue 6 * 0b111..Receive queue 7 */ -#define EMAC_MAC_RXQ_CTRL1_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK) +#define EMAC_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & EMAC_MAC_RXQ_CTRL_AVCPQ_MASK) -#define EMAC_MAC_RXQ_CTRL1_PTPQ_MASK (0x70U) -#define EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT (4U) +#define EMAC_MAC_RXQ_CTRL_PTPQ_MASK (0x70U) +#define EMAC_MAC_RXQ_CTRL_PTPQ_SHIFT (4U) /*! PTPQ - PTP Packets Queue * 0b000..Receive queue 0 * 0b001..Receive queue 1 @@ -1838,10 +1802,10 @@ typedef struct { * 0b110..Receive queue 6 * 0b111..Receive queue 7 */ -#define EMAC_MAC_RXQ_CTRL1_PTPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_PTPQ_MASK) +#define EMAC_MAC_RXQ_CTRL_PTPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_PTPQ_SHIFT)) & EMAC_MAC_RXQ_CTRL_PTPQ_MASK) -#define EMAC_MAC_RXQ_CTRL1_UPQ_MASK (0x7000U) -#define EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT (12U) +#define EMAC_MAC_RXQ_CTRL_UPQ_MASK (0x7000U) +#define EMAC_MAC_RXQ_CTRL_UPQ_SHIFT (12U) /*! UPQ - Untagged Packet Queue * 0b000..Receive queue 0 * 0b001..Receive queue 1 @@ -1852,10 +1816,10 @@ typedef struct { * 0b110..Receive queue 6 * 0b111..Receive queue 7 */ -#define EMAC_MAC_RXQ_CTRL1_UPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_UPQ_MASK) +#define EMAC_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_UPQ_SHIFT)) & EMAC_MAC_RXQ_CTRL_UPQ_MASK) -#define EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK (0x70000U) -#define EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT (16U) +#define EMAC_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U) +#define EMAC_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U) /*! MCBCQ - Multicast And Broadcast Queue * 0b000..Receive queue 0 * 0b001..Receive queue 1 @@ -1866,47 +1830,43 @@ typedef struct { * 0b110..Receive queue 6 * 0b111..Receive queue 7 */ -#define EMAC_MAC_RXQ_CTRL1_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK) +#define EMAC_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & EMAC_MAC_RXQ_CTRL_MCBCQ_MASK) -#define EMAC_MAC_RXQ_CTRL1_MCBCQEN_MASK (0x100000U) -#define EMAC_MAC_RXQ_CTRL1_MCBCQEN_SHIFT (20U) +#define EMAC_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U) +#define EMAC_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U) /*! MCBCQEN - Multicast And Broadcast Queue Enable * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MAC_RXQ_CTRL1_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_MCBCQEN_SHIFT)) & EMAC_MAC_RXQ_CTRL1_MCBCQEN_MASK) +#define EMAC_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & EMAC_MAC_RXQ_CTRL_MCBCQEN_MASK) -#define EMAC_MAC_RXQ_CTRL1_TACPQE_MASK (0x200000U) -#define EMAC_MAC_RXQ_CTRL1_TACPQE_SHIFT (21U) +#define EMAC_MAC_RXQ_CTRL_TACPQE_MASK (0x200000U) +#define EMAC_MAC_RXQ_CTRL_TACPQE_SHIFT (21U) /*! TACPQE - Tagged AV Control Packets Queuing Enable * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MAC_RXQ_CTRL1_TACPQE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_TACPQE_SHIFT)) & EMAC_MAC_RXQ_CTRL1_TACPQE_MASK) +#define EMAC_MAC_RXQ_CTRL_TACPQE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_TACPQE_SHIFT)) & EMAC_MAC_RXQ_CTRL_TACPQE_MASK) -#define EMAC_MAC_RXQ_CTRL1_TPQC_MASK (0xC00000U) -#define EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT (22U) +#define EMAC_MAC_RXQ_CTRL_TPQC_MASK (0xC00000U) +#define EMAC_MAC_RXQ_CTRL_TPQC_SHIFT (22U) /*! TPQC - Tagged PTP Over Ethernet Packets Queuing Control */ -#define EMAC_MAC_RXQ_CTRL1_TPQC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT)) & EMAC_MAC_RXQ_CTRL1_TPQC_MASK) +#define EMAC_MAC_RXQ_CTRL_TPQC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_TPQC_SHIFT)) & EMAC_MAC_RXQ_CTRL_TPQC_MASK) -#define EMAC_MAC_RXQ_CTRL1_FPRQ_MASK (0x7000000U) -#define EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT (24U) +#define EMAC_MAC_RXQ_CTRL_FPRQ_MASK (0x7000000U) +#define EMAC_MAC_RXQ_CTRL_FPRQ_SHIFT (24U) /*! FPRQ - Frame Preemption Residue Queue */ -#define EMAC_MAC_RXQ_CTRL1_FPRQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_FPRQ_MASK) -/*! @} */ - -/*! @name MAC_RXQ_CTRL2 - MAC RxQ Control 2 */ -/*! @{ */ +#define EMAC_MAC_RXQ_CTRL_FPRQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_FPRQ_SHIFT)) & EMAC_MAC_RXQ_CTRL_FPRQ_MASK) -#define EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK (0xFFU) -#define EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT (0U) +#define EMAC_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU) +#define EMAC_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U) /*! PSRQ0 - Priorities Selected In Receive Queue 0 */ -#define EMAC_MAC_RXQ_CTRL2_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT)) & EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK) +#define EMAC_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & EMAC_MAC_RXQ_CTRL_PSRQ0_MASK) -#define EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK (0xFF00U) -#define EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT (8U) +#define EMAC_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U) +#define EMAC_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U) /*! PSRQ1 - Priorities Selected In Receive Queue 1 */ -#define EMAC_MAC_RXQ_CTRL2_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT)) & EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK) +#define EMAC_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & EMAC_MAC_RXQ_CTRL_PSRQ1_MASK) /*! @} */ /*! @name MAC_INTERRUPT_STATUS - MAC Interrupt Status */ @@ -2165,165 +2125,165 @@ typedef struct { #define EMAC_MAC_DEBUG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DEBUG_TFCSTS_SHIFT)) & EMAC_MAC_DEBUG_TFCSTS_MASK) /*! @} */ -/*! @name MAC_HW_FEATURE0 - MAC Hardware Feature 0 */ +/*! @name MAC_HW_FEAT - MAC Hardware Feature 0..MAC Hardware Feature 3 */ /*! @{ */ -#define EMAC_MAC_HW_FEATURE0_MIISEL_MASK (0x1U) -#define EMAC_MAC_HW_FEATURE0_MIISEL_SHIFT (0U) +#define EMAC_MAC_HW_FEAT_MIISEL_MASK (0x1U) +#define EMAC_MAC_HW_FEAT_MIISEL_SHIFT (0U) /*! MIISEL - 10 or 100 Mbit/s Support Feature * 0b0..Unavailable * 0b1..Available */ -#define EMAC_MAC_HW_FEATURE0_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MIISEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MIISEL_MASK) +#define EMAC_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_MIISEL_SHIFT)) & EMAC_MAC_HW_FEAT_MIISEL_MASK) -#define EMAC_MAC_HW_FEATURE0_GMIISEL_MASK (0x2U) -#define EMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT (1U) +#define EMAC_MAC_HW_FEAT_GMIISEL_MASK (0x2U) +#define EMAC_MAC_HW_FEAT_GMIISEL_SHIFT (1U) /*! GMIISEL - 1000 Mbit/s Support Feature * 0b0..Unavailable * 0b1..Available */ -#define EMAC_MAC_HW_FEATURE0_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_GMIISEL_MASK) +#define EMAC_MAC_HW_FEAT_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_GMIISEL_SHIFT)) & EMAC_MAC_HW_FEAT_GMIISEL_MASK) -#define EMAC_MAC_HW_FEATURE0_HDSEL_MASK (0x4U) -#define EMAC_MAC_HW_FEATURE0_HDSEL_SHIFT (2U) +#define EMAC_MAC_HW_FEAT_HDSEL_MASK (0x4U) +#define EMAC_MAC_HW_FEAT_HDSEL_SHIFT (2U) /*! HDSEL - Half-Duplex Support Feature * 0b0..Unavailable * 0b1..Available */ -#define EMAC_MAC_HW_FEATURE0_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_HDSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_HDSEL_MASK) +#define EMAC_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_HDSEL_SHIFT)) & EMAC_MAC_HW_FEAT_HDSEL_MASK) -#define EMAC_MAC_HW_FEATURE0_PCSSEL_MASK (0x8U) -#define EMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT (3U) +#define EMAC_MAC_HW_FEAT_PCSSEL_MASK (0x8U) +#define EMAC_MAC_HW_FEAT_PCSSEL_SHIFT (3U) /*! PCSSEL - PCS Select * 0b0..No * 0b1..Yes */ -#define EMAC_MAC_HW_FEATURE0_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_PCSSEL_MASK) +#define EMAC_MAC_HW_FEAT_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_PCSSEL_SHIFT)) & EMAC_MAC_HW_FEAT_PCSSEL_MASK) -#define EMAC_MAC_HW_FEATURE0_VLHASH_MASK (0x10U) -#define EMAC_MAC_HW_FEATURE0_VLHASH_SHIFT (4U) +#define EMAC_MAC_HW_FEAT_VLHASH_MASK (0x10U) +#define EMAC_MAC_HW_FEAT_VLHASH_SHIFT (4U) /*! VLHASH - VLAN Hash Filter Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_VLHASH_SHIFT)) & EMAC_MAC_HW_FEATURE0_VLHASH_MASK) +#define EMAC_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_VLHASH_SHIFT)) & EMAC_MAC_HW_FEAT_VLHASH_MASK) -#define EMAC_MAC_HW_FEATURE0_SMASEL_MASK (0x20U) -#define EMAC_MAC_HW_FEATURE0_SMASEL_SHIFT (5U) +#define EMAC_MAC_HW_FEAT_SMASEL_MASK (0x20U) +#define EMAC_MAC_HW_FEAT_SMASEL_SHIFT (5U) /*! SMASEL - SMA (MDIO) Interface Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_SMASEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_SMASEL_MASK) +#define EMAC_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_SMASEL_SHIFT)) & EMAC_MAC_HW_FEAT_SMASEL_MASK) -#define EMAC_MAC_HW_FEATURE0_RWKSEL_MASK (0x40U) -#define EMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT (6U) +#define EMAC_MAC_HW_FEAT_RWKSEL_MASK (0x40U) +#define EMAC_MAC_HW_FEAT_RWKSEL_SHIFT (6U) /*! RWKSEL - PMT Remote Wake-Up Packet Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_RWKSEL_MASK) +#define EMAC_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_RWKSEL_SHIFT)) & EMAC_MAC_HW_FEAT_RWKSEL_MASK) -#define EMAC_MAC_HW_FEATURE0_MGKSEL_MASK (0x80U) -#define EMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT (7U) +#define EMAC_MAC_HW_FEAT_MGKSEL_MASK (0x80U) +#define EMAC_MAC_HW_FEAT_MGKSEL_SHIFT (7U) /*! MGKSEL - PMT Magic Packet Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MGKSEL_MASK) +#define EMAC_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_MGKSEL_SHIFT)) & EMAC_MAC_HW_FEAT_MGKSEL_MASK) -#define EMAC_MAC_HW_FEATURE0_MMCSEL_MASK (0x100U) -#define EMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT (8U) +#define EMAC_MAC_HW_FEAT_MMCSEL_MASK (0x100U) +#define EMAC_MAC_HW_FEAT_MMCSEL_SHIFT (8U) /*! MMCSEL - MAC Management Counters (MMC) Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MMCSEL_MASK) +#define EMAC_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_MMCSEL_SHIFT)) & EMAC_MAC_HW_FEAT_MMCSEL_MASK) -#define EMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK (0x200U) -#define EMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT (9U) +#define EMAC_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) +#define EMAC_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) /*! ARPOFFSEL - ARP Offload Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK) +#define EMAC_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & EMAC_MAC_HW_FEAT_ARPOFFSEL_MASK) -#define EMAC_MAC_HW_FEATURE0_TSSEL_MASK (0x1000U) -#define EMAC_MAC_HW_FEATURE0_TSSEL_SHIFT (12U) +#define EMAC_MAC_HW_FEAT_TSSEL_MASK (0x1000U) +#define EMAC_MAC_HW_FEAT_TSSEL_SHIFT (12U) /*! TSSEL - IEEE 1588-2008 Timestamp Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_TSSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_TSSEL_MASK) +#define EMAC_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_TSSEL_SHIFT)) & EMAC_MAC_HW_FEAT_TSSEL_MASK) -#define EMAC_MAC_HW_FEATURE0_EEESEL_MASK (0x2000U) -#define EMAC_MAC_HW_FEATURE0_EEESEL_SHIFT (13U) +#define EMAC_MAC_HW_FEAT_EEESEL_MASK (0x2000U) +#define EMAC_MAC_HW_FEAT_EEESEL_SHIFT (13U) /*! EEESEL - Energy Efficient Ethernet (EEE) Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_EEESEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_EEESEL_MASK) +#define EMAC_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_EEESEL_SHIFT)) & EMAC_MAC_HW_FEAT_EEESEL_MASK) -#define EMAC_MAC_HW_FEATURE0_TXCOESEL_MASK (0x4000U) -#define EMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT (14U) +#define EMAC_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U) +#define EMAC_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) /*! TXCOESEL - Transmit Checksum Offload Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_TXCOESEL_MASK) +#define EMAC_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_TXCOESEL_SHIFT)) & EMAC_MAC_HW_FEAT_TXCOESEL_MASK) -#define EMAC_MAC_HW_FEATURE0_RXCOESEL_MASK (0x10000U) -#define EMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT (16U) +#define EMAC_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) +#define EMAC_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) /*! RXCOESEL - Receive Checksum Offload Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_RXCOESEL_MASK) +#define EMAC_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_RXCOESEL_SHIFT)) & EMAC_MAC_HW_FEAT_RXCOESEL_MASK) -#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x7C0000U) -#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT (18U) +#define EMAC_MAC_HW_FEAT_ADDMACADRSEL_MASK (0x7C0000U) +#define EMAC_MAC_HW_FEAT_ADDMACADRSEL_SHIFT (18U) /*! ADDMACADRSEL - MAC Addresses 1-31 * 0b00000..Not selected * 0b00001..Selected */ -#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK) +#define EMAC_MAC_HW_FEAT_ADDMACADRSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & EMAC_MAC_HW_FEAT_ADDMACADRSEL_MASK) -#define EMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK (0x800000U) -#define EMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT (23U) +#define EMAC_MAC_HW_FEAT_MACADR32SEL_MASK (0x800000U) +#define EMAC_MAC_HW_FEAT_MACADR32SEL_SHIFT (23U) /*! MACADR32SEL - MAC Addresses 32-63 * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK) +#define EMAC_MAC_HW_FEAT_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & EMAC_MAC_HW_FEAT_MACADR32SEL_MASK) -#define EMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK (0x1000000U) -#define EMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT (24U) +#define EMAC_MAC_HW_FEAT_MACADR64SEL_MASK (0x1000000U) +#define EMAC_MAC_HW_FEAT_MACADR64SEL_SHIFT (24U) /*! MACADR64SEL - MAC Addresses 64-127 * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK) +#define EMAC_MAC_HW_FEAT_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & EMAC_MAC_HW_FEAT_MACADR64SEL_MASK) -#define EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK (0x6000000U) -#define EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT (25U) +#define EMAC_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U) +#define EMAC_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) /*! TSSTSSEL - Timestamp System Time Source Feature * 0b00..Internal * 0b01..External * 0b10..Both internal and external * 0b11..Reserved */ -#define EMAC_MAC_HW_FEATURE0_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK) +#define EMAC_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & EMAC_MAC_HW_FEAT_TSSTSSEL_MASK) -#define EMAC_MAC_HW_FEATURE0_SAVLANINS_MASK (0x8000000U) -#define EMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT (27U) +#define EMAC_MAC_HW_FEAT_SAVLANINS_MASK (0x8000000U) +#define EMAC_MAC_HW_FEAT_SAVLANINS_SHIFT (27U) /*! SAVLANINS - SA or VLAN Insertion Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE0_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT)) & EMAC_MAC_HW_FEATURE0_SAVLANINS_MASK) +#define EMAC_MAC_HW_FEAT_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_SAVLANINS_SHIFT)) & EMAC_MAC_HW_FEAT_SAVLANINS_MASK) -#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK (0x70000000U) -#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT (28U) +#define EMAC_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U) +#define EMAC_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U) /*! ACTPHYSEL - Active PHY Feature * 0b000..GMII or MII * 0b001..RGMII @@ -2334,14 +2294,10 @@ typedef struct { * 0b110..SMII * 0b111..RevMII */ -#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK) -/*! @} */ +#define EMAC_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & EMAC_MAC_HW_FEAT_ACTPHYSEL_MASK) -/*! @name MAC_HW_FEATURE1 - MAC Hardware Feature 1 */ -/*! @{ */ - -#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1FU) -#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT (0U) +#define EMAC_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU) +#define EMAC_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - MTL Receive FIFO Size Feature * 0b00000..128 bytes * 0b00001..256 bytes @@ -2357,18 +2313,18 @@ typedef struct { * 0b01011..256 KB * 0b01100..Reserved */ -#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT)) & EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK) +#define EMAC_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & EMAC_MAC_HW_FEAT_RXFIFOSIZE_MASK) -#define EMAC_MAC_HW_FEATURE1_SPRAM_MASK (0x20U) -#define EMAC_MAC_HW_FEATURE1_SPRAM_SHIFT (5U) +#define EMAC_MAC_HW_FEAT_SPRAM_MASK (0x20U) +#define EMAC_MAC_HW_FEAT_SPRAM_SHIFT (5U) /*! SPRAM - Single Port RAM Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_SPRAM_SHIFT)) & EMAC_MAC_HW_FEATURE1_SPRAM_MASK) +#define EMAC_MAC_HW_FEAT_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_SPRAM_SHIFT)) & EMAC_MAC_HW_FEAT_SPRAM_MASK) -#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x7C0U) -#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT (6U) +#define EMAC_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U) +#define EMAC_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) /*! TXFIFOSIZE - MTL Transmit FIFO Size Feature * 0b00000..128 bytes * 0b00001..256 bytes @@ -2383,110 +2339,110 @@ typedef struct { * 0b01010..128 KB * 0b01011..Reserved */ -#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT)) & EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK) +#define EMAC_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & EMAC_MAC_HW_FEAT_TXFIFOSIZE_MASK) -#define EMAC_MAC_HW_FEATURE1_OSTEN_MASK (0x800U) -#define EMAC_MAC_HW_FEATURE1_OSTEN_SHIFT (11U) +#define EMAC_MAC_HW_FEAT_OSTEN_MASK (0x800U) +#define EMAC_MAC_HW_FEAT_OSTEN_SHIFT (11U) /*! OSTEN - One-Step Timestamping Enable Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_OSTEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_OSTEN_MASK) +#define EMAC_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_OSTEN_SHIFT)) & EMAC_MAC_HW_FEAT_OSTEN_MASK) -#define EMAC_MAC_HW_FEATURE1_PTOEN_MASK (0x1000U) -#define EMAC_MAC_HW_FEATURE1_PTOEN_SHIFT (12U) +#define EMAC_MAC_HW_FEAT_PTOEN_MASK (0x1000U) +#define EMAC_MAC_HW_FEAT_PTOEN_SHIFT (12U) /*! PTOEN - PTP Offload Enable Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_PTOEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_PTOEN_MASK) +#define EMAC_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_PTOEN_SHIFT)) & EMAC_MAC_HW_FEAT_PTOEN_MASK) -#define EMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK (0x2000U) -#define EMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT (13U) +#define EMAC_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) +#define EMAC_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) /*! ADVTHWORD - IEEE 1588 High-Word Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT)) & EMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK) +#define EMAC_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & EMAC_MAC_HW_FEAT_ADVTHWORD_MASK) -#define EMAC_MAC_HW_FEATURE1_ADDR64_MASK (0xC000U) -#define EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT (14U) +#define EMAC_MAC_HW_FEAT_ADDR64_MASK (0xC000U) +#define EMAC_MAC_HW_FEAT_ADDR64_SHIFT (14U) /*! ADDR64 - Address Width Feature * 0b00..32 * 0b01..40 * 0b10..48 * 0b11..Reserved */ -#define EMAC_MAC_HW_FEATURE1_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)) & EMAC_MAC_HW_FEATURE1_ADDR64_MASK) +#define EMAC_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_ADDR64_SHIFT)) & EMAC_MAC_HW_FEAT_ADDR64_MASK) -#define EMAC_MAC_HW_FEATURE1_DCBEN_MASK (0x10000U) -#define EMAC_MAC_HW_FEATURE1_DCBEN_SHIFT (16U) +#define EMAC_MAC_HW_FEAT_DCBEN_MASK (0x10000U) +#define EMAC_MAC_HW_FEAT_DCBEN_SHIFT (16U) /*! DCBEN - DCB Enable Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_DCBEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_DCBEN_MASK) +#define EMAC_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_DCBEN_SHIFT)) & EMAC_MAC_HW_FEAT_DCBEN_MASK) -#define EMAC_MAC_HW_FEATURE1_SPHEN_MASK (0x20000U) -#define EMAC_MAC_HW_FEATURE1_SPHEN_SHIFT (17U) +#define EMAC_MAC_HW_FEAT_SPHEN_MASK (0x20000U) +#define EMAC_MAC_HW_FEAT_SPHEN_SHIFT (17U) /*! SPHEN - Split Header Enable Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_SPHEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_SPHEN_MASK) +#define EMAC_MAC_HW_FEAT_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_SPHEN_SHIFT)) & EMAC_MAC_HW_FEAT_SPHEN_MASK) -#define EMAC_MAC_HW_FEATURE1_TSOEN_MASK (0x40000U) -#define EMAC_MAC_HW_FEATURE1_TSOEN_SHIFT (18U) +#define EMAC_MAC_HW_FEAT_TSOEN_MASK (0x40000U) +#define EMAC_MAC_HW_FEAT_TSOEN_SHIFT (18U) /*! TSOEN - TCP Segmentation Offload Enable Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_TSOEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_TSOEN_MASK) +#define EMAC_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_TSOEN_SHIFT)) & EMAC_MAC_HW_FEAT_TSOEN_MASK) -#define EMAC_MAC_HW_FEATURE1_DBGMEMA_MASK (0x80000U) -#define EMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT (19U) +#define EMAC_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) +#define EMAC_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) /*! DBGMEMA - DMA Debug Registers Enable Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT)) & EMAC_MAC_HW_FEATURE1_DBGMEMA_MASK) +#define EMAC_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_DBGMEMA_SHIFT)) & EMAC_MAC_HW_FEAT_DBGMEMA_MASK) -#define EMAC_MAC_HW_FEATURE1_AVSEL_MASK (0x100000U) -#define EMAC_MAC_HW_FEATURE1_AVSEL_SHIFT (20U) +#define EMAC_MAC_HW_FEAT_AVSEL_MASK (0x100000U) +#define EMAC_MAC_HW_FEAT_AVSEL_SHIFT (20U) /*! AVSEL - AV Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_AVSEL_SHIFT)) & EMAC_MAC_HW_FEATURE1_AVSEL_MASK) +#define EMAC_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_AVSEL_SHIFT)) & EMAC_MAC_HW_FEAT_AVSEL_MASK) -#define EMAC_MAC_HW_FEATURE1_RAVSEL_MASK (0x200000U) -#define EMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT (21U) +#define EMAC_MAC_HW_FEAT_RAVSEL_MASK (0x200000U) +#define EMAC_MAC_HW_FEAT_RAVSEL_SHIFT (21U) /*! RAVSEL - Receive Side-Only AV Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT)) & EMAC_MAC_HW_FEATURE1_RAVSEL_MASK) +#define EMAC_MAC_HW_FEAT_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_RAVSEL_SHIFT)) & EMAC_MAC_HW_FEAT_RAVSEL_MASK) -#define EMAC_MAC_HW_FEATURE1_POUOST_MASK (0x800000U) -#define EMAC_MAC_HW_FEATURE1_POUOST_SHIFT (23U) +#define EMAC_MAC_HW_FEAT_POUOST_MASK (0x800000U) +#define EMAC_MAC_HW_FEAT_POUOST_SHIFT (23U) /*! POUOST - One Step For PTP Over UDP/IP Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE1_POUOST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_POUOST_SHIFT)) & EMAC_MAC_HW_FEATURE1_POUOST_MASK) +#define EMAC_MAC_HW_FEAT_POUOST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_POUOST_SHIFT)) & EMAC_MAC_HW_FEAT_POUOST_MASK) -#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (0x3000000U) -#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT (24U) +#define EMAC_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) +#define EMAC_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) /*! HASHTBLSZ - Hash Table Size * 0b00..No hash table * 0b01..64 * 0b10..128 * 0b11..256 */ -#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT)) & EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK) +#define EMAC_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & EMAC_MAC_HW_FEAT_HASHTBLSZ_MASK) -#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0x78000000U) -#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT (27U) +#define EMAC_MAC_HW_FEAT_L3L4FNUM_MASK (0x78000000U) +#define EMAC_MAC_HW_FEAT_L3L4FNUM_SHIFT (27U) /*! L3L4FNUM - L3 Or L4 Filter Number * 0b0000..No filters (0) * 0b0001..1 @@ -2498,14 +2454,10 @@ typedef struct { * 0b0111..7 * 0b1000..8 */ -#define EMAC_MAC_HW_FEATURE1_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT)) & EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK) -/*! @} */ - -/*! @name MAC_HW_FEATURE2 - MAC Hardware Feature 2 */ -/*! @{ */ +#define EMAC_MAC_HW_FEAT_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & EMAC_MAC_HW_FEAT_L3L4FNUM_MASK) -#define EMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xFU) -#define EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT (0U) +#define EMAC_MAC_HW_FEAT_RXQCNT_MASK (0xFU) +#define EMAC_MAC_HW_FEAT_RXQCNT_SHIFT (0U) /*! RXQCNT - Number Of MTL Receive Queues * 0b0000..1 * 0b0001..2 @@ -2516,10 +2468,10 @@ typedef struct { * 0b0110..7 * 0b0111..8 */ -#define EMAC_MAC_HW_FEATURE2_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT)) & EMAC_MAC_HW_FEATURE2_RXQCNT_MASK) +#define EMAC_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_RXQCNT_SHIFT)) & EMAC_MAC_HW_FEAT_RXQCNT_MASK) -#define EMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0x3C0U) -#define EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT (6U) +#define EMAC_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U) +#define EMAC_MAC_HW_FEAT_TXQCNT_SHIFT (6U) /*! TXQCNT - Number Of MTL Transmit Queues * 0b0000..1 * 0b0001..2 @@ -2530,10 +2482,10 @@ typedef struct { * 0b0110..7 * 0b0111..8 */ -#define EMAC_MAC_HW_FEATURE2_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT)) & EMAC_MAC_HW_FEATURE2_TXQCNT_MASK) +#define EMAC_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_TXQCNT_SHIFT)) & EMAC_MAC_HW_FEAT_TXQCNT_MASK) -#define EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xF000U) -#define EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT (12U) +#define EMAC_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U) +#define EMAC_MAC_HW_FEAT_RXCHCNT_SHIFT (12U) /*! RXCHCNT - Number Of DMA Receive Channels * 0b0000..1 * 0b0001..2 @@ -2544,10 +2496,10 @@ typedef struct { * 0b0110..7 * 0b0111..8 */ -#define EMAC_MAC_HW_FEATURE2_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT)) & EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK) +#define EMAC_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_RXCHCNT_SHIFT)) & EMAC_MAC_HW_FEAT_RXCHCNT_MASK) -#define EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0x3C0000U) -#define EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT (18U) +#define EMAC_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U) +#define EMAC_MAC_HW_FEAT_TXCHCNT_SHIFT (18U) /*! TXCHCNT - Number Of DMA Transmit Channels * 0b0000..1 * 0b0001..2 @@ -2558,10 +2510,10 @@ typedef struct { * 0b0110..7 * 0b0111..8 */ -#define EMAC_MAC_HW_FEATURE2_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT)) & EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK) +#define EMAC_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_TXCHCNT_SHIFT)) & EMAC_MAC_HW_FEAT_TXCHCNT_MASK) -#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (0x7000000U) -#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT (24U) +#define EMAC_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) +#define EMAC_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) /*! PPSOUTNUM - Number Of PPS Outputs * 0b000..No PPS output (0) * 0b001..1 @@ -2570,10 +2522,10 @@ typedef struct { * 0b100..4 * 0b101..Reserved */ -#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT)) & EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK) +#define EMAC_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & EMAC_MAC_HW_FEAT_PPSOUTNUM_MASK) -#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK (0x70000000U) -#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT (28U) +#define EMAC_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) +#define EMAC_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) /*! AUXSNAPNUM - Number Of Auxiliary Snapshot Inputs * 0b000..No auxiliary input (0) * 0b001..1 @@ -2582,14 +2534,10 @@ typedef struct { * 0b100..4 * 0b101..Reserved */ -#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT)) & EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK) -/*! @} */ - -/*! @name MAC_HW_FEATURE3 - MAC Hardware Feature 3 */ -/*! @{ */ +#define EMAC_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & EMAC_MAC_HW_FEAT_AUXSNAPNUM_MASK) -#define EMAC_MAC_HW_FEATURE3_NRVF_MASK (0x7U) -#define EMAC_MAC_HW_FEATURE3_NRVF_SHIFT (0U) +#define EMAC_MAC_HW_FEAT_NRVF_MASK (0x7U) +#define EMAC_MAC_HW_FEAT_NRVF_SHIFT (0U) /*! NRVF * 0b000..No filters (0) * 0b001..4 @@ -2599,70 +2547,70 @@ typedef struct { * 0b101..32 * 0b110..Reserved */ -#define EMAC_MAC_HW_FEATURE3_NRVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT)) & EMAC_MAC_HW_FEATURE3_NRVF_MASK) +#define EMAC_MAC_HW_FEAT_NRVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_NRVF_SHIFT)) & EMAC_MAC_HW_FEAT_NRVF_MASK) -#define EMAC_MAC_HW_FEATURE3_CBTISEL_MASK (0x10U) -#define EMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT (4U) +#define EMAC_MAC_HW_FEAT_CBTISEL_MASK (0x10U) +#define EMAC_MAC_HW_FEAT_CBTISEL_SHIFT (4U) /*! CBTISEL - Queue/Channel Based VLAN Tag Insertion On Transmit Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE3_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_CBTISEL_MASK) +#define EMAC_MAC_HW_FEAT_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_CBTISEL_SHIFT)) & EMAC_MAC_HW_FEAT_CBTISEL_MASK) -#define EMAC_MAC_HW_FEATURE3_DVLAN_MASK (0x20U) -#define EMAC_MAC_HW_FEATURE3_DVLAN_SHIFT (5U) +#define EMAC_MAC_HW_FEAT_DVLAN_MASK (0x20U) +#define EMAC_MAC_HW_FEAT_DVLAN_SHIFT (5U) /*! DVLAN - Double VLAN Tag Processing Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE3_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_DVLAN_SHIFT)) & EMAC_MAC_HW_FEATURE3_DVLAN_MASK) +#define EMAC_MAC_HW_FEAT_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_DVLAN_SHIFT)) & EMAC_MAC_HW_FEAT_DVLAN_MASK) -#define EMAC_MAC_HW_FEATURE3_PDUPSEL_MASK (0x200U) -#define EMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT (9U) +#define EMAC_MAC_HW_FEAT_PDUPSEL_MASK (0x200U) +#define EMAC_MAC_HW_FEAT_PDUPSEL_SHIFT (9U) /*! PDUPSEL - Broadcast/Multicast Packet Duplication Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE3_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_PDUPSEL_MASK) +#define EMAC_MAC_HW_FEAT_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_PDUPSEL_SHIFT)) & EMAC_MAC_HW_FEAT_PDUPSEL_MASK) -#define EMAC_MAC_HW_FEATURE3_FRPSEL_MASK (0x400U) -#define EMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT (10U) +#define EMAC_MAC_HW_FEAT_FRPSEL_MASK (0x400U) +#define EMAC_MAC_HW_FEAT_FRPSEL_SHIFT (10U) /*! FRPSEL - Flexible Receive Parser Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE3_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_FRPSEL_MASK) +#define EMAC_MAC_HW_FEAT_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_FRPSEL_SHIFT)) & EMAC_MAC_HW_FEAT_FRPSEL_MASK) -#define EMAC_MAC_HW_FEATURE3_FRPBS_MASK (0x1800U) -#define EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT (11U) +#define EMAC_MAC_HW_FEAT_FRPBS_MASK (0x1800U) +#define EMAC_MAC_HW_FEAT_FRPBS_SHIFT (11U) /*! FRPBS - Flexible Receive Parser Buffer Size * 0b00..64 * 0b01..128 * 0b10..256 * 0b11..Reserved */ -#define EMAC_MAC_HW_FEATURE3_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT)) & EMAC_MAC_HW_FEATURE3_FRPBS_MASK) +#define EMAC_MAC_HW_FEAT_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_FRPBS_SHIFT)) & EMAC_MAC_HW_FEAT_FRPBS_MASK) -#define EMAC_MAC_HW_FEATURE3_FRPES_MASK (0x6000U) -#define EMAC_MAC_HW_FEATURE3_FRPES_SHIFT (13U) +#define EMAC_MAC_HW_FEAT_FRPES_MASK (0x6000U) +#define EMAC_MAC_HW_FEAT_FRPES_SHIFT (13U) /*! FRPES - Flexible Receive Parser Table Entry Size * 0b00..64 * 0b01..128 * 0b10..256 * 0b11..Reserved */ -#define EMAC_MAC_HW_FEATURE3_FRPES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT)) & EMAC_MAC_HW_FEATURE3_FRPES_MASK) +#define EMAC_MAC_HW_FEAT_FRPES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_FRPES_SHIFT)) & EMAC_MAC_HW_FEAT_FRPES_MASK) -#define EMAC_MAC_HW_FEATURE3_ESTSEL_MASK (0x10000U) -#define EMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT (16U) +#define EMAC_MAC_HW_FEAT_ESTSEL_MASK (0x10000U) +#define EMAC_MAC_HW_FEAT_ESTSEL_SHIFT (16U) /*! ESTSEL - Enhancements To Scheduling Traffic Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE3_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_ESTSEL_MASK) +#define EMAC_MAC_HW_FEAT_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_ESTSEL_SHIFT)) & EMAC_MAC_HW_FEAT_ESTSEL_MASK) -#define EMAC_MAC_HW_FEATURE3_ESTDEP_MASK (0xE0000U) -#define EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT (17U) +#define EMAC_MAC_HW_FEAT_ESTDEP_MASK (0xE0000U) +#define EMAC_MAC_HW_FEAT_ESTDEP_SHIFT (17U) /*! ESTDEP - Depth Of Gate Control List * 0b000..No depth configured * 0b001..64 bytes @@ -2672,43 +2620,43 @@ typedef struct { * 0b101..1024 bytes * 0b110..Reserved */ -#define EMAC_MAC_HW_FEATURE3_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT)) & EMAC_MAC_HW_FEATURE3_ESTDEP_MASK) +#define EMAC_MAC_HW_FEAT_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_ESTDEP_SHIFT)) & EMAC_MAC_HW_FEAT_ESTDEP_MASK) -#define EMAC_MAC_HW_FEATURE3_ESTWID_MASK (0x300000U) -#define EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT (20U) +#define EMAC_MAC_HW_FEAT_ESTWID_MASK (0x300000U) +#define EMAC_MAC_HW_FEAT_ESTWID_SHIFT (20U) /*! ESTWID - Estimated Time Interval Width * 0b00..Width not configured * 0b01..16 bits * 0b10..20 bits * 0b11..24 bits */ -#define EMAC_MAC_HW_FEATURE3_ESTWID(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT)) & EMAC_MAC_HW_FEATURE3_ESTWID_MASK) +#define EMAC_MAC_HW_FEAT_ESTWID(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_ESTWID_SHIFT)) & EMAC_MAC_HW_FEAT_ESTWID_MASK) -#define EMAC_MAC_HW_FEATURE3_FPESEL_MASK (0x4000000U) -#define EMAC_MAC_HW_FEATURE3_FPESEL_SHIFT (26U) +#define EMAC_MAC_HW_FEAT_FPESEL_MASK (0x4000000U) +#define EMAC_MAC_HW_FEAT_FPESEL_SHIFT (26U) /*! FPESEL - Frame Preemption Feature * 0b0..Not selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE3_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_FPESEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_FPESEL_MASK) +#define EMAC_MAC_HW_FEAT_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_FPESEL_SHIFT)) & EMAC_MAC_HW_FEAT_FPESEL_MASK) -#define EMAC_MAC_HW_FEATURE3_TBSSEL_MASK (0x8000000U) -#define EMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT (27U) +#define EMAC_MAC_HW_FEAT_TBSSEL_MASK (0x8000000U) +#define EMAC_MAC_HW_FEAT_TBSSEL_SHIFT (27U) /*! TBSSEL - Time-Based Scheduling Feature * 0b0..Selected * 0b1..Selected */ -#define EMAC_MAC_HW_FEATURE3_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_TBSSEL_MASK) +#define EMAC_MAC_HW_FEAT_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_TBSSEL_SHIFT)) & EMAC_MAC_HW_FEAT_TBSSEL_MASK) -#define EMAC_MAC_HW_FEATURE3_ASP_MASK (0x30000000U) -#define EMAC_MAC_HW_FEATURE3_ASP_SHIFT (28U) +#define EMAC_MAC_HW_FEAT_ASP_MASK (0x30000000U) +#define EMAC_MAC_HW_FEAT_ASP_SHIFT (28U) /*! ASP - Automotive Safety Package * 0b00..No safety features selected * 0b01..Only "ECC protection for external memory" feature is selected * 0b10..All the safety features are selected without the "parity port enable for external interface" feature * 0b11..All the safety features are selected with the "parity port enable for external interface" feature */ -#define EMAC_MAC_HW_FEATURE3_ASP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_ASP_SHIFT)) & EMAC_MAC_HW_FEATURE3_ASP_MASK) +#define EMAC_MAC_HW_FEAT_ASP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEAT_ASP_SHIFT)) & EMAC_MAC_HW_FEAT_ASP_MASK) /*! @} */ /*! @name MAC_DPP_FSM_INTERRUPT_STATUS - MAC DPP FSM Interrupt Status */ @@ -3162,125 +3110,56 @@ typedef struct { #define EMAC_MAC_PRESN_TIME_UPDT_MPTU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK) /*! @} */ -/*! @name MAC_ADDRESS0_HIGH - MAC Address 0 High */ +/*! @name HIGH - MAC Address 0 High..MAC Address 2 High */ /*! @{ */ -#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFFU) -#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0U) -/*! ADDRHI - MAC Address 0 [47:32] */ -#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT)) & EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK) - -#define EMAC_MAC_ADDRESS0_HIGH_DCS_MASK (0x30000U) -#define EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT (16U) -/*! DCS - DMA Channel Select */ -#define EMAC_MAC_ADDRESS0_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT)) & EMAC_MAC_ADDRESS0_HIGH_DCS_MASK) - -#define EMAC_MAC_ADDRESS0_HIGH_AE_MASK (0x80000000U) -#define EMAC_MAC_ADDRESS0_HIGH_AE_SHIFT (31U) -/*! AE - Address Enable - * 0b0..Disabled and invalid (the field's value must always be 1) - * 0b1..Enabled - */ -#define EMAC_MAC_ADDRESS0_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS0_HIGH_AE_SHIFT)) & EMAC_MAC_ADDRESS0_HIGH_AE_MASK) -/*! @} */ - -/*! @name MAC_ADDRESS0_LOW - MAC Address 0 Low */ -/*! @{ */ - -#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFFU) -#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0U) -/*! ADDRLO - MAC Address 0 [31:0] */ -#define EMAC_MAC_ADDRESS0_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT)) & EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK) -/*! @} */ - -/*! @name MAC_ADDRESS1_HIGH - MAC Address 1 High */ -/*! @{ */ - -#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK (0xFFFFU) -#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT (0U) +#define EMAC_HIGH_ADDRHI_MASK (0xFFFFU) +#define EMAC_HIGH_ADDRHI_SHIFT (0U) /*! ADDRHI - MAC Address 1 [47:32] */ -#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK) +#define EMAC_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_HIGH_ADDRHI_SHIFT)) & EMAC_HIGH_ADDRHI_MASK) -#define EMAC_MAC_ADDRESS1_HIGH_DCS_MASK (0x30000U) -#define EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT (16U) +#define EMAC_HIGH_DCS_MASK (0x30000U) +#define EMAC_HIGH_DCS_SHIFT (16U) /*! DCS - DMA Channel Select */ -#define EMAC_MAC_ADDRESS1_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_DCS_MASK) +#define EMAC_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_HIGH_DCS_SHIFT)) & EMAC_HIGH_DCS_MASK) -#define EMAC_MAC_ADDRESS1_HIGH_MBC_MASK (0x3F000000U) -#define EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT (24U) +#define EMAC_HIGH_MBC_MASK (0x3F000000U) +#define EMAC_HIGH_MBC_SHIFT (24U) /*! MBC - Mask Byte Control */ -#define EMAC_MAC_ADDRESS1_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_MBC_MASK) +#define EMAC_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_HIGH_MBC_SHIFT)) & EMAC_HIGH_MBC_MASK) -#define EMAC_MAC_ADDRESS1_HIGH_SA_MASK (0x40000000U) -#define EMAC_MAC_ADDRESS1_HIGH_SA_SHIFT (30U) +#define EMAC_HIGH_SA_MASK (0x40000000U) +#define EMAC_HIGH_SA_SHIFT (30U) /*! SA - Source Address * 0b0..Destination address * 0b1..Source address */ -#define EMAC_MAC_ADDRESS1_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_SA_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_SA_MASK) +#define EMAC_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_HIGH_SA_SHIFT)) & EMAC_HIGH_SA_MASK) -#define EMAC_MAC_ADDRESS1_HIGH_AE_MASK (0x80000000U) -#define EMAC_MAC_ADDRESS1_HIGH_AE_SHIFT (31U) +#define EMAC_HIGH_AE_MASK (0x80000000U) +#define EMAC_HIGH_AE_SHIFT (31U) /*! AE - Address Enable - * 0b0..Ignored + * 0b0..Disabled and invalid (the field's value must always be 1) * 0b1..Enabled */ -#define EMAC_MAC_ADDRESS1_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_AE_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_AE_MASK) +#define EMAC_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_HIGH_AE_SHIFT)) & EMAC_HIGH_AE_MASK) /*! @} */ -/*! @name MAC_ADDRESS1_LOW - MAC Address 1 Low */ -/*! @{ */ - -#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK (0xFFFFFFFFU) -#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT (0U) -/*! ADDRLO - MAC Address 1 [31:0] */ -#define EMAC_MAC_ADDRESS1_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT)) & EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK) -/*! @} */ - -/*! @name MAC_ADDRESS2_HIGH - MAC Address 2 High */ -/*! @{ */ - -#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK (0xFFFFU) -#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT (0U) -/*! ADDRHI - MAC Address 1 [47:32] */ -#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK) - -#define EMAC_MAC_ADDRESS2_HIGH_DCS_MASK (0x30000U) -#define EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT (16U) -/*! DCS - DMA Channel Select */ -#define EMAC_MAC_ADDRESS2_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_DCS_MASK) - -#define EMAC_MAC_ADDRESS2_HIGH_MBC_MASK (0x3F000000U) -#define EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT (24U) -/*! MBC - Mask Byte Control */ -#define EMAC_MAC_ADDRESS2_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_MBC_MASK) - -#define EMAC_MAC_ADDRESS2_HIGH_SA_MASK (0x40000000U) -#define EMAC_MAC_ADDRESS2_HIGH_SA_SHIFT (30U) -/*! SA - Source Address - * 0b0..Destination address - * 0b1..Source address - */ -#define EMAC_MAC_ADDRESS2_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_SA_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_SA_MASK) - -#define EMAC_MAC_ADDRESS2_HIGH_AE_MASK (0x80000000U) -#define EMAC_MAC_ADDRESS2_HIGH_AE_SHIFT (31U) -/*! AE - Address Enable - * 0b0..Ignored - * 0b1..Enabled - */ -#define EMAC_MAC_ADDRESS2_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_AE_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_AE_MASK) -/*! @} */ +/* The count of EMAC_HIGH */ +#define EMAC_HIGH_COUNT (3U) -/*! @name MAC_ADDRESS2_LOW - MAC Address 2 Low */ +/*! @name LOW - MAC Address 0 Low..MAC Address 2 Low */ /*! @{ */ -#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK (0xFFFFFFFFU) -#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT (0U) +#define EMAC_LOW_ADDRLO_MASK (0xFFFFFFFFU) +#define EMAC_LOW_ADDRLO_SHIFT (0U) /*! ADDRLO - MAC Address 1 [31:0] */ -#define EMAC_MAC_ADDRESS2_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT)) & EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK) +#define EMAC_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_LOW_ADDRLO_SHIFT)) & EMAC_LOW_ADDRLO_MASK) /*! @} */ +/* The count of EMAC_LOW */ +#define EMAC_LOW_COUNT (3U) + /*! @name MMC_CONTROL - MMC Control */ /*! @{ */ @@ -7331,37 +7210,37 @@ typedef struct { #define EMAC_MTL_DPP_CONTROL_IPERD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_IPERD_SHIFT)) & EMAC_MTL_DPP_CONTROL_IPERD_MASK) /*! @} */ -/*! @name MTL_TXQ0_OPERATION_MODE - MTL Tx Queue 0 Operation Mode */ +/*! @name MTL_TXQX_OP_MODE - MTL Tx Queue 0 Operation Mode..MTL Tx Queue 1 Operation Mode */ /*! @{ */ -#define EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK (0x1U) -#define EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT (0U) +#define EMAC_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U) +#define EMAC_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U) /*! FTQ - Flush Transmit Queue * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MTL_TXQ0_OPERATION_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK) +#define EMAC_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & EMAC_MTL_TXQX_OP_MODE_FTQ_MASK) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK (0x2U) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT (1U) +#define EMAC_MTL_TXQX_OP_MODE_TSF_MASK (0x2U) +#define EMAC_MTL_TXQX_OP_MODE_TSF_SHIFT (1U) /*! TSF - Transmit Store and Forward - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Transmit Store and Forward is disabled + * 0b1..Transmit Store and Forward is enabled */ -#define EMAC_MTL_TXQ0_OPERATION_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK) +#define EMAC_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_OP_MODE_TSF_SHIFT)) & EMAC_MTL_TXQX_OP_MODE_TSF_MASK) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0xCU) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT (2U) +#define EMAC_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU) +#define EMAC_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) /*! TXQEN - Transmit Queue Enable * 0b00..Not enabled * 0b01..Enable in AV mode (Reserved in non-AV) * 0b10..Enabled * 0b11..Reserved */ -#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK) +#define EMAC_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & EMAC_MTL_TXQX_OP_MODE_TXQEN_MASK) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (0x70U) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT (4U) +#define EMAC_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) +#define EMAC_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) /*! TTC - Transmit Threshold Control * 0b000..32 * 0b001..64 @@ -7372,2007 +7251,1256 @@ typedef struct { * 0b110..384 * 0b111..512 */ -#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK) +#define EMAC_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_OP_MODE_TTC_SHIFT)) & EMAC_MTL_TXQX_OP_MODE_TTC_MASK) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK (0x1F0000U) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT (16U) +#define EMAC_MTL_TXQX_OP_MODE_TQS_MASK (0x1F0000U) +#define EMAC_MTL_TXQX_OP_MODE_TQS_SHIFT (16U) /*! TQS - Transmit Queue Size */ -#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK) +#define EMAC_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_OP_MODE_TQS_SHIFT)) & EMAC_MTL_TXQX_OP_MODE_TQS_MASK) /*! @} */ -/*! @name MTL_TXQ0_UNDERFLOW - MTL Tx Queue 0 Underflow */ +/* The count of EMAC_MTL_TXQX_OP_MODE */ +#define EMAC_MTL_TXQX_OP_MODE_COUNT (2U) + +/*! @name MTL_TXQX_UNDRFLW - MTL Tx Queue 0 Underflow..MTL Tx Queue 1 Underflow */ /*! @{ */ -#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7FFU) -#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT (0U) +#define EMAC_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU) +#define EMAC_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U) /*! UFFRMCNT - Underflow Packet Counter */ -#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT)) & EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK) +#define EMAC_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & EMAC_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK) -#define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK (0x800U) -#define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT (11U) +#define EMAC_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U) +#define EMAC_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT)) & EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK) +#define EMAC_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & EMAC_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK) /*! @} */ -/*! @name MTL_TXQ0_DEBUG - MTL Tx Queue 0 Debug */ +/* The count of EMAC_MTL_TXQX_UNDRFLW */ +#define EMAC_MTL_TXQX_UNDRFLW_COUNT (2U) + +/*! @name MTL_TXQX_DBG - MTL Tx Queue 0 Debug..MTL Tx Queue 1 Debug */ /*! @{ */ -#define EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK (0x1U) -#define EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT (0U) +#define EMAC_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U) +#define EMAC_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U) /*! TXQPAUSED - Transmit Queue in Pause * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_TXQ0_DEBUG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK) +#define EMAC_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & EMAC_MTL_TXQX_DBG_TXQPAUSED_MASK) -#define EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK (0x6U) -#define EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT (1U) +#define EMAC_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) +#define EMAC_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) /*! TRCSTS - MTL Tx Queue Read Controller Status * 0b00..Idle state * 0b01..Read state (transferring data to the MAC transmitter) * 0b10..Waiting for pending transit status from the MAC transmitter * 0b11..Flushing the transit queue because of the packet abort request from the MAC */ -#define EMAC_MTL_TXQ0_DEBUG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK) +#define EMAC_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_DBG_TRCSTS_SHIFT)) & EMAC_MTL_TXQX_DBG_TRCSTS_MASK) -#define EMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK (0x8U) -#define EMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT (3U) +#define EMAC_MTL_TXQX_DBG_TWCSTS_MASK (0x8U) +#define EMAC_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) /*! TWCSTS - MTL Tx Queue Write Controller Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_TXQ0_DEBUG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK) +#define EMAC_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_DBG_TWCSTS_SHIFT)) & EMAC_MTL_TXQX_DBG_TWCSTS_MASK) -#define EMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK (0x10U) -#define EMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT (4U) +#define EMAC_MTL_TXQX_DBG_TXQSTS_MASK (0x10U) +#define EMAC_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) /*! TXQSTS - MTL Tx Queue Not Empty Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_TXQ0_DEBUG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK) +#define EMAC_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_DBG_TXQSTS_SHIFT)) & EMAC_MTL_TXQX_DBG_TXQSTS_MASK) -#define EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK (0x20U) -#define EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT (5U) +#define EMAC_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) +#define EMAC_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) /*! TXSTSFSTS - MTL Tx Status FIFO Full Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK) +#define EMAC_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & EMAC_MTL_TXQX_DBG_TXSTSFSTS_MASK) -#define EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK (0x70000U) -#define EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT (16U) +#define EMAC_MTL_TXQX_DBG_PTXQ_MASK (0x70000U) +#define EMAC_MTL_TXQX_DBG_PTXQ_SHIFT (16U) /*! PTXQ - Number of Packets in the Transmit Queue */ -#define EMAC_MTL_TXQ0_DEBUG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK) +#define EMAC_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_DBG_PTXQ_SHIFT)) & EMAC_MTL_TXQX_DBG_PTXQ_MASK) -#define EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK (0x700000U) -#define EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT (20U) +#define EMAC_MTL_TXQX_DBG_STXSTSF_MASK (0x700000U) +#define EMAC_MTL_TXQX_DBG_STXSTSF_SHIFT (20U) /*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue */ -#define EMAC_MTL_TXQ0_DEBUG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK) +#define EMAC_MTL_TXQX_DBG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_DBG_STXSTSF_SHIFT)) & EMAC_MTL_TXQX_DBG_STXSTSF_MASK) +/*! @} */ + +/* The count of EMAC_MTL_TXQX_DBG */ +#define EMAC_MTL_TXQX_DBG_COUNT (2U) + +/*! @name MTL_TXQX_ETS_CTRL - MTL Tx Queue 1 ETS Control */ +/*! @{ */ + +#define EMAC_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U) +#define EMAC_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U) +/*! AVALG - AV Algorithm + * 0b0..Disabled + * 0b1..Enabled + */ +#define EMAC_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & EMAC_MTL_TXQX_ETS_CTRL_AVALG_MASK) + +#define EMAC_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U) +#define EMAC_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U) +/*! CC - Credit Control + * 0b0..Disabled + * 0b1..Enabled + */ +#define EMAC_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & EMAC_MTL_TXQX_ETS_CTRL_CC_MASK) + +#define EMAC_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) +#define EMAC_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) +/*! SLC - Slot Count + * 0b000..1 slot + * 0b001..2 slots + * 0b010..4 slots + * 0b011..8 slots + * 0b100..16 slots + * 0b101..Reserved + */ +#define EMAC_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & EMAC_MTL_TXQX_ETS_CTRL_SLC_MASK) /*! @} */ -/*! @name MTL_TXQ0_ETS_STATUS - MTL Tx Queue 0 ETS Status */ +/* The count of EMAC_MTL_TXQX_ETS_CTRL */ +#define EMAC_MTL_TXQX_ETS_CTRL_COUNT (2U) + +/*! @name MTL_TXQX_ETS_STAT - MTL Tx Queue 0 ETS Status..MTL Tx Queue 1 ETS Status */ /*! @{ */ -#define EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK (0xFFFFFFU) -#define EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT (0U) +#define EMAC_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU) +#define EMAC_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U) /*! ABS - Average Bits per Slot */ -#define EMAC_MTL_TXQ0_ETS_STATUS_ABS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT)) & EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK) +#define EMAC_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & EMAC_MTL_TXQX_ETS_STAT_ABS_MASK) +/*! @} */ + +/* The count of EMAC_MTL_TXQX_ETS_STAT */ +#define EMAC_MTL_TXQX_ETS_STAT_COUNT (2U) + +/*! @name MTL_TXQX_QNTM_WGHT - MTL Tx Queue Quantum Weight..MTL Tx Queue 1 Quantum Weight */ +/*! @{ */ + +#define EMAC_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU) +#define EMAC_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U) +/*! ISCQW - idleSlopeCredit, Quantum or Weights */ +#define EMAC_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & EMAC_MTL_TXQX_QNTM_WGHT_ISCQW_MASK) +/*! @} */ + +/* The count of EMAC_MTL_TXQX_QNTM_WGHT */ +#define EMAC_MTL_TXQX_QNTM_WGHT_COUNT (2U) + +/*! @name MTL_TXQX_SNDSLP_CRDT - MTL Tx Queue 1 Sendslope Credit */ +/*! @{ */ + +#define EMAC_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU) +#define EMAC_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U) +/*! SSC - sendSlopeCredit Value */ +#define EMAC_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & EMAC_MTL_TXQX_SNDSLP_CRDT_SSC_MASK) +/*! @} */ + +/* The count of EMAC_MTL_TXQX_SNDSLP_CRDT */ +#define EMAC_MTL_TXQX_SNDSLP_CRDT_COUNT (2U) + +/*! @name MTL_TXQX_HI_CRDT - MTL Tx Queue 1 HiCredit */ +/*! @{ */ + +#define EMAC_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU) +#define EMAC_MTL_TXQX_HI_CRDT_HC_SHIFT (0U) +/*! HC - hiCredit Value */ +#define EMAC_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_HI_CRDT_HC_SHIFT)) & EMAC_MTL_TXQX_HI_CRDT_HC_MASK) /*! @} */ -/*! @name MTL_TXQ0_QUANTUM_WEIGHT - MTL Tx Queue Quantum Weight */ +/* The count of EMAC_MTL_TXQX_HI_CRDT */ +#define EMAC_MTL_TXQX_HI_CRDT_COUNT (2U) + +/*! @name MTL_TXQX_LO_CRDT - MTL Tx Queue 1 LoCredit */ /*! @{ */ -#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFFU) -#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT (0U) -/*! ISCQW - Quantum or Weights */ -#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT)) & EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK) +#define EMAC_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU) +#define EMAC_MTL_TXQX_LO_CRDT_LC_SHIFT (0U) +/*! LC - loCredit Value */ +#define EMAC_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQX_LO_CRDT_LC_SHIFT)) & EMAC_MTL_TXQX_LO_CRDT_LC_MASK) /*! @} */ -/*! @name MTL_Q0_INTERRUPT_CONTROL_STATUS - MTL Queue 0 Interrupt Control Status */ +/* The count of EMAC_MTL_TXQX_LO_CRDT */ +#define EMAC_MTL_TXQX_LO_CRDT_COUNT (2U) + +/*! @name MTL_QX_INTCTRL_STAT - MTL Queue 0 Interrupt Control Status..MTL Queue 1 Interrupt Control Status */ /*! @{ */ -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK (0x1U) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT (0U) +#define EMAC_MTL_QX_INTCTRL_STAT_TXUNFIS_MASK (0x1U) +#define EMAC_MTL_QX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) /*! TXUNFIS - Transmit Queue Underflow Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK) +#define EMAC_MTL_QX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_QX_INTCTRL_STAT_TXUNFIS_SHIFT)) & EMAC_MTL_QX_INTCTRL_STAT_TXUNFIS_MASK) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK (0x2U) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT (1U) +#define EMAC_MTL_QX_INTCTRL_STAT_ABPSIS_MASK (0x2U) +#define EMAC_MTL_QX_INTCTRL_STAT_ABPSIS_SHIFT (1U) /*! ABPSIS - Average Bits Per Slot Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK) +#define EMAC_MTL_QX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_QX_INTCTRL_STAT_ABPSIS_SHIFT)) & EMAC_MTL_QX_INTCTRL_STAT_ABPSIS_MASK) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_MASK (0x100U) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT (8U) +#define EMAC_MTL_QX_INTCTRL_STAT_TXUIE_MASK (0x100U) +#define EMAC_MTL_QX_INTCTRL_STAT_TXUIE_SHIFT (8U) /*! TXUIE - Transmit Queue Underflow Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_MASK) +#define EMAC_MTL_QX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_QX_INTCTRL_STAT_TXUIE_SHIFT)) & EMAC_MTL_QX_INTCTRL_STAT_TXUIE_MASK) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK (0x200U) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT (9U) +#define EMAC_MTL_QX_INTCTRL_STAT_ABPSIE_MASK (0x200U) +#define EMAC_MTL_QX_INTCTRL_STAT_ABPSIE_SHIFT (9U) /*! ABPSIE - Average Bits Per Slot Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK) +#define EMAC_MTL_QX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_QX_INTCTRL_STAT_ABPSIE_SHIFT)) & EMAC_MTL_QX_INTCTRL_STAT_ABPSIE_MASK) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK (0x10000U) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT (16U) +#define EMAC_MTL_QX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U) +#define EMAC_MTL_QX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) /*! RXOVFIS - Receive Queue Overflow Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK) +#define EMAC_MTL_QX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_QX_INTCTRL_STAT_RXOVFIS_SHIFT)) & EMAC_MTL_QX_INTCTRL_STAT_RXOVFIS_MASK) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_MASK (0x1000000U) -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT (24U) +#define EMAC_MTL_QX_INTCTRL_STAT_RXOIE_MASK (0x1000000U) +#define EMAC_MTL_QX_INTCTRL_STAT_RXOIE_SHIFT (24U) /*! RXOIE - Receive Queue Overflow Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_MASK) +#define EMAC_MTL_QX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_QX_INTCTRL_STAT_RXOIE_SHIFT)) & EMAC_MTL_QX_INTCTRL_STAT_RXOIE_MASK) /*! @} */ -/*! @name MTL_RXQ0_OPERATION_MODE - MTL Rx Queue 0 Operation Mode */ +/* The count of EMAC_MTL_QX_INTCTRL_STAT */ +#define EMAC_MTL_QX_INTCTRL_STAT_COUNT (2U) + +/*! @name MTL_RXQX_OP_MODE - MTL Rx Queue 0 Operation Mode..MTL Rx Queue 1 Operation Mode */ /*! @{ */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK (0x3U) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT (0U) +#define EMAC_MTL_RXQX_OP_MODE_RTC_MASK (0x3U) +#define EMAC_MTL_RXQX_OP_MODE_RTC_SHIFT (0U) /*! RTC - Receive Queue Threshold Control * 0b00..64 * 0b01..32 * 0b10..96 * 0b11..128 */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK) +#define EMAC_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_OP_MODE_RTC_SHIFT)) & EMAC_MTL_RXQX_OP_MODE_RTC_MASK) -#define EMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK (0x8U) -#define EMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT (3U) +#define EMAC_MTL_RXQX_OP_MODE_FUP_MASK (0x8U) +#define EMAC_MTL_RXQX_OP_MODE_FUP_SHIFT (3U) /*! FUP - Forward Undersized Good Packets * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK) +#define EMAC_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_OP_MODE_FUP_SHIFT)) & EMAC_MTL_RXQX_OP_MODE_FUP_MASK) -#define EMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK (0x10U) -#define EMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT (4U) +#define EMAC_MTL_RXQX_OP_MODE_FEP_MASK (0x10U) +#define EMAC_MTL_RXQX_OP_MODE_FEP_SHIFT (4U) /*! FEP - Forward Error Packets * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK) +#define EMAC_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_OP_MODE_FEP_SHIFT)) & EMAC_MTL_RXQX_OP_MODE_FEP_MASK) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK (0x20U) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT (5U) +#define EMAC_MTL_RXQX_OP_MODE_RSF_MASK (0x20U) +#define EMAC_MTL_RXQX_OP_MODE_RSF_SHIFT (5U) /*! RSF - Receive Queue Store and Forward * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK) +#define EMAC_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_OP_MODE_RSF_SHIFT)) & EMAC_MTL_RXQX_OP_MODE_RSF_MASK) -#define EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK (0x40U) -#define EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT (6U) -/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets - * 0b0..Enable - * 0b1..Disable +#define EMAC_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U) +#define EMAC_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U) +/*! DIS_TCP_EF - Disable Dropping of TCP or IP Checksum Error Packets + * 0b0..Enabled + * 0b1..Disabled */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK) +#define EMAC_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & EMAC_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) -#define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK (0x80U) -#define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT (7U) +#define EMAC_MTL_RXQX_OP_MODE_EHFC_MASK (0x80U) +#define EMAC_MTL_RXQX_OP_MODE_EHFC_SHIFT (7U) /*! EHFC - Enable Hardware Flow Control * 0b0..Disable * 0b1..Enable */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK) +#define EMAC_MTL_RXQX_OP_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & EMAC_MTL_RXQX_OP_MODE_EHFC_MASK) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0xF00U) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT (8U) +#define EMAC_MTL_RXQX_OP_MODE_RFA_MASK (0xF00U) +#define EMAC_MTL_RXQX_OP_MODE_RFA_SHIFT (8U) /*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex) */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK) +#define EMAC_MTL_RXQX_OP_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_OP_MODE_RFA_SHIFT)) & EMAC_MTL_RXQX_OP_MODE_RFA_MASK) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0x3C000U) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT (14U) +#define EMAC_MTL_RXQX_OP_MODE_RFD_MASK (0x3C000U) +#define EMAC_MTL_RXQX_OP_MODE_RFD_SHIFT (14U) /*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK) +#define EMAC_MTL_RXQX_OP_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_OP_MODE_RFD_SHIFT)) & EMAC_MTL_RXQX_OP_MODE_RFD_MASK) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK (0x1F00000U) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT (20U) +#define EMAC_MTL_RXQX_OP_MODE_RQS_MASK (0x1F00000U) +#define EMAC_MTL_RXQX_OP_MODE_RQS_SHIFT (20U) /*! RQS - Receive Queue Size */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK) +#define EMAC_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_OP_MODE_RQS_SHIFT)) & EMAC_MTL_RXQX_OP_MODE_RQS_MASK) /*! @} */ -/*! @name MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT - MTL Rx Queue Missed Packet Overflow Count */ +/* The count of EMAC_MTL_RXQX_OP_MODE */ +#define EMAC_MTL_RXQX_OP_MODE_COUNT (2U) + +/*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL Rx Queue Missed Packet Overflow Count..MTL Rx Queue 1 Missed Packet Overflow Counter */ /*! @{ */ -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FFU) -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0U) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U) /*! OVFPKTCNT - Overflow Packet Counter */ -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK) -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK (0x800U) -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT (11U) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) /*! OVFCNTOVF - Overflow Counter Overflow Bit * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT)) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF0000U) -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16U) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U) /*! MISPKTCNT - Missed Packet Counter */ -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK) -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK (0x8000000U) -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT (27U) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U) /*! MISCNTOVF - Missed Packet Counter Overflow Bit * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT)) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK) +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK) /*! @} */ -/*! @name MTL_RXQ0_DEBUG - MTL Rx Queue 0 Debug */ +/* The count of EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT */ +#define EMAC_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U) + +/*! @name MTL_RXQX_DBG - MTL Rx Queue 0 Debug..MTL Rx Queue 1 Debug */ /*! @{ */ -#define EMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK (0x1U) -#define EMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT (0U) +#define EMAC_MTL_RXQX_DBG_RWCSTS_MASK (0x1U) +#define EMAC_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) /*! RWCSTS - MTL Rx Queue Write Controller Active Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_RXQ0_DEBUG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT)) & EMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK) +#define EMAC_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_DBG_RWCSTS_SHIFT)) & EMAC_MTL_RXQX_DBG_RWCSTS_MASK) -#define EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK (0x6U) -#define EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT (1U) +#define EMAC_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) +#define EMAC_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) /*! RRCSTS - MTL Rx Queue Read Controller State * 0b00..Idle state * 0b01..Reading packet data * 0b10..Reading packet status (or timestamp) * 0b11..Flushing the packet data and status */ -#define EMAC_MTL_RXQ0_DEBUG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT)) & EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK) +#define EMAC_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_DBG_RRCSTS_SHIFT)) & EMAC_MTL_RXQX_DBG_RRCSTS_MASK) -#define EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK (0x30U) -#define EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT (4U) +#define EMAC_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) +#define EMAC_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) /*! RXQSTS - MTL Rx Queue Fill-Level Status * 0b00..Rx Queue empty * 0b01..Rx Queue fill-level below flow-control deactivate threshold * 0b10..Rx Queue fill-level above flow-control activate threshold * 0b11..Rx Queue full */ -#define EMAC_MTL_RXQ0_DEBUG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT)) & EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK) +#define EMAC_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_DBG_RXQSTS_SHIFT)) & EMAC_MTL_RXQX_DBG_RXQSTS_MASK) -#define EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0x3FFF0000U) -#define EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT (16U) +#define EMAC_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U) +#define EMAC_MTL_RXQX_DBG_PRXQ_SHIFT (16U) /*! PRXQ - Number of Packets in Receive Queue */ -#define EMAC_MTL_RXQ0_DEBUG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT)) & EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK) +#define EMAC_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_DBG_PRXQ_SHIFT)) & EMAC_MTL_RXQX_DBG_PRXQ_MASK) /*! @} */ -/*! @name MTL_RXQ0_CONTROL - MTL Rx Queue 0 Control 0 */ +/* The count of EMAC_MTL_RXQX_DBG */ +#define EMAC_MTL_RXQX_DBG_COUNT (2U) + +/*! @name MTL_RXQX_CTRL - MTL Rx Queue 0 Control 0..MTL Rx Queue 1 Control */ /*! @{ */ -#define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK (0x7U) -#define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT (0U) +#define EMAC_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U) +#define EMAC_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U) /*! RXQ_WEGT - Receive Queue Weight */ -#define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT)) & EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK) +#define EMAC_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & EMAC_MTL_RXQX_CTRL_RXQ_WEGT_MASK) -#define EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_MASK (0x8U) -#define EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_SHIFT (3U) +#define EMAC_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U) +#define EMAC_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U) /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_SHIFT)) & EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_MASK) +#define EMAC_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & EMAC_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK) /*! @} */ -/*! @name MTL_TXQ1_OPERATION_MODE - MTL Tx Queue 1 Operation Mode */ +/* The count of EMAC_MTL_RXQX_CTRL */ +#define EMAC_MTL_RXQX_CTRL_COUNT (2U) + +/*! @name DMA_MODE - DMA Mode */ /*! @{ */ -#define EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_MASK (0x1U) -#define EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_SHIFT (0U) -/*! FTQ - Flush Transmit Queue +#define EMAC_DMA_MODE_SWR_MASK (0x1U) +#define EMAC_DMA_MODE_SWR_SHIFT (0U) +/*! SWR - Software Reset * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_MTL_TXQ1_OPERATION_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_MASK) +#define EMAC_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_SWR_SHIFT)) & EMAC_DMA_MODE_SWR_MASK) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TSF_MASK (0x2U) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TSF_SHIFT (1U) -/*! TSF - Transmit Store and Forward - * 0b0..Transmit Store and Forward is disabled - * 0b1..Transmit Store and Forward is enabled +#define EMAC_DMA_MODE_DA_MASK (0x2U) +#define EMAC_DMA_MODE_DA_SHIFT (1U) +/*! DA - DMA Tx or Rx Arbitration Scheme + * 0b0..Weighted Round-Robin with Rx:Tx or Tx:Rx + * 0b1..Fixed Priority */ -#define EMAC_MTL_TXQ1_OPERATION_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_TSF_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_TSF_MASK) +#define EMAC_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_DA_SHIFT)) & EMAC_DMA_MODE_DA_MASK) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK (0xCU) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT (2U) -/*! TXQEN - Transmit Queue Enable - * 0b00..Not enabled - * 0b01..Enable in AV mode (Reserved in non-AV) - * 0b10..Enabled - * 0b11..Reserved +#define EMAC_DMA_MODE_TAA_MASK (0x1CU) +#define EMAC_DMA_MODE_TAA_SHIFT (2U) +/*! TAA - Transmit Arbitration Algorithm + * 0b000..Fixed priority (Channel 0 has the lowest priority and the last channel has the highest priority) + * 0b001..Weighted Strict Priority (WSP) + * 0b010..Weighted Round-Robin (WRR) + * 0b011..Reserved (for 3'b011 to 3'b111) */ -#define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK) +#define EMAC_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_TAA_SHIFT)) & EMAC_DMA_MODE_TAA_MASK) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK (0x70U) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT (4U) -/*! TTC - Transmit Threshold Control - * 0b000..32 - * 0b001..64 - * 0b010..96 - * 0b011..128 - * 0b100..192 - * 0b101..256 - * 0b110..384 - * 0b111..512 +#define EMAC_DMA_MODE_ARBC_MASK (0x200U) +#define EMAC_DMA_MODE_ARBC_SHIFT (9U) +/*! ARBC + * 0b0..NXP reserved field disabled + * 0b1..NXP reserved field enabled up on NXP request */ -#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK) +#define EMAC_DMA_MODE_ARBC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_ARBC_SHIFT)) & EMAC_DMA_MODE_ARBC_MASK) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK (0x1F0000U) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT (16U) -/*! TQS - Transmit Queue Size */ -#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK) +#define EMAC_DMA_MODE_TXPR_MASK (0x800U) +#define EMAC_DMA_MODE_TXPR_SHIFT (11U) +/*! TXPR - Transmit Priority + * 0b0..Disabled + * 0b1..Enabled + */ +#define EMAC_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_TXPR_SHIFT)) & EMAC_DMA_MODE_TXPR_MASK) + +#define EMAC_DMA_MODE_PR_MASK (0x7000U) +#define EMAC_DMA_MODE_PR_SHIFT (12U) +/*! PR - Priority Ratio + * 0b000..The priority ratio is 1:1 + * 0b001..The priority ratio is 2:1 + * 0b010..The priority ratio is 3:1 + * 0b011..The priority ratio is 4:1 + * 0b100..The priority ratio is 5:1 + * 0b101..The priority ratio is 6:1 + * 0b110..The priority ratio is 7:1 + * 0b111..The priority ratio is 8:1 + */ +#define EMAC_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_PR_SHIFT)) & EMAC_DMA_MODE_PR_MASK) + +#define EMAC_DMA_MODE_INTM_MASK (0x30000U) +#define EMAC_DMA_MODE_INTM_SHIFT (16U) +/*! INTM - Interrupt Mode + * 0b00..See above description + * 0b01..See above description + * 0b10..See above description + * 0b11..Reserved + */ +#define EMAC_DMA_MODE_INTM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_INTM_SHIFT)) & EMAC_DMA_MODE_INTM_MASK) /*! @} */ -/*! @name MTL_TXQ1_UNDERFLOW - MTL Tx Queue 1 Underflow */ +/*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */ /*! @{ */ -#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK (0x7FFU) -#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT (0U) -/*! UFFRMCNT - Underflow Packet Counter */ -#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT)) & EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK) +#define EMAC_DMA_SYSBUS_MODE_FB_MASK (0x1U) +#define EMAC_DMA_SYSBUS_MODE_FB_SHIFT (0U) +/*! FB - Fixed Burst Length + * 0b0..Disabled + * 0b1..Enabled + */ +#define EMAC_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_FB_SHIFT)) & EMAC_DMA_SYSBUS_MODE_FB_MASK) -#define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_MASK (0x800U) -#define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_SHIFT (11U) -/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter - * 0b0..Not detected - * 0b1..Detected +#define EMAC_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) +#define EMAC_DMA_SYSBUS_MODE_AAL_SHIFT (12U) +/*! AAL - Address-Aligned Beats + * 0b0..Disabled + * 0b1..Enabled + */ +#define EMAC_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_AAL_SHIFT)) & EMAC_DMA_SYSBUS_MODE_AAL_MASK) + +#define EMAC_DMA_SYSBUS_MODE_MB_MASK (0x4000U) +#define EMAC_DMA_SYSBUS_MODE_MB_SHIFT (14U) +/*! MB - Mixed Burst + * 0b0..Disabled + * 0b1..Enabled + */ +#define EMAC_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_MB_SHIFT)) & EMAC_DMA_SYSBUS_MODE_MB_MASK) + +#define EMAC_DMA_SYSBUS_MODE_RB_MASK (0x8000U) +#define EMAC_DMA_SYSBUS_MODE_RB_SHIFT (15U) +/*! RB - Rebuild INCRx Burst + * 0b0..Disabled + * 0b1..Enabled */ -#define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_SHIFT)) & EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_MASK) +#define EMAC_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_RB_SHIFT)) & EMAC_DMA_SYSBUS_MODE_RB_MASK) /*! @} */ -/*! @name MTL_TXQ1_DEBUG - MTL Tx Queue 1 Debug */ +/*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */ /*! @{ */ -#define EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_MASK (0x1U) -#define EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_SHIFT (0U) -/*! TXQPAUSED - Transmit Queue in Pause +#define EMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U) +#define EMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U) +/*! DC0IS - DMA Channel 0 Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_TXQ1_DEBUG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_MASK) - -#define EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK (0x6U) -#define EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT (1U) -/*! TRCSTS - MTL Tx Queue Read Controller Status - * 0b00..Idle state - * 0b01..Read state (transferring data to the MAC transmitter) - * 0b10..Waiting for pending transit status from the MAC transmitter - * 0b11..Flushing the transit queue because of the packet abort request from the MAC - */ -#define EMAC_MTL_TXQ1_DEBUG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK) +#define EMAC_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK) -#define EMAC_MTL_TXQ1_DEBUG_TWCSTS_MASK (0x8U) -#define EMAC_MTL_TXQ1_DEBUG_TWCSTS_SHIFT (3U) -/*! TWCSTS - MTL Tx Queue Write Controller Status +#define EMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U) +#define EMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U) +/*! DC1IS - DMA Channel 1 Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_TXQ1_DEBUG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TWCSTS_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TWCSTS_MASK) +#define EMAC_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK) -#define EMAC_MTL_TXQ1_DEBUG_TXQSTS_MASK (0x10U) -#define EMAC_MTL_TXQ1_DEBUG_TXQSTS_SHIFT (4U) -/*! TXQSTS - MTL Tx Queue Not Empty Status +#define EMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U) +#define EMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U) +/*! MTLIS - MTL Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_TXQ1_DEBUG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TXQSTS_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TXQSTS_MASK) +#define EMAC_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK) -#define EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_MASK (0x20U) -#define EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_SHIFT (5U) -/*! TXSTSFSTS - MTL Tx Status FIFO Full Status +#define EMAC_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U) +#define EMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U) +/*! MACIS - MAC Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_MASK) - -#define EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK (0x70000U) -#define EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT (16U) -/*! PTXQ - Number of Packets in the Transmit Queue */ -#define EMAC_MTL_TXQ1_DEBUG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK) - -#define EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK (0x700000U) -#define EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT (20U) -/*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue */ -#define EMAC_MTL_TXQ1_DEBUG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK) +#define EMAC_DMA_INTERRUPT_STATUS_MACIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_MACIS_MASK) /*! @} */ -/*! @name MTL_TXQ1_ETS_CONTROL - MTL Tx Queue 1 ETS Control */ +/*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */ /*! @{ */ -#define EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_MASK (0x4U) -#define EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_SHIFT (2U) -/*! AVALG - AV Algorithm - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_MTL_TXQ1_ETS_CONTROL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_SHIFT)) & EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_MASK) - -#define EMAC_MTL_TXQ1_ETS_CONTROL_CC_MASK (0x8U) -#define EMAC_MTL_TXQ1_ETS_CONTROL_CC_SHIFT (3U) -/*! CC - Credit Control - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_MTL_TXQ1_ETS_CONTROL_CC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_ETS_CONTROL_CC_SHIFT)) & EMAC_MTL_TXQ1_ETS_CONTROL_CC_MASK) - -#define EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK (0x70U) -#define EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT (4U) -/*! SLC - Slot Count - * 0b000..1 slot - * 0b001..2 slots - * 0b010..4 slots - * 0b011..8 slots - * 0b100..16 slots - * 0b101..Reserved - */ -#define EMAC_MTL_TXQ1_ETS_CONTROL_SLC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT)) & EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK) -/*! @} */ - -/*! @name MTL_TXQ1_ETS_STATUS - MTL Tx Queue 1 ETS Status */ -/*! @{ */ - -#define EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK (0xFFFFFFU) -#define EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT (0U) -/*! ABS - Average Bits per Slot */ -#define EMAC_MTL_TXQ1_ETS_STATUS_ABS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT)) & EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK) -/*! @} */ - -/*! @name MTL_TXQ1_QUANTUM_WEIGHT - MTL Tx Queue 1 Quantum Weight */ -/*! @{ */ - -#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFFU) -#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT (0U) -/*! ISCQW - idleSlopeCredit, Quantum or Weights */ -#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT)) & EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK) -/*! @} */ - -/*! @name MTL_TXQ1_SENDSLOPECREDIT - MTL Tx Queue 1 Sendslope Credit */ -/*! @{ */ - -#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK (0x3FFFU) -#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT (0U) -/*! SSC - sendSlopeCredit Value */ -#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT)) & EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK) -/*! @} */ - -/*! @name MTL_TXQ1_HICREDIT - MTL Tx Queue 1 HiCredit */ -/*! @{ */ - -#define EMAC_MTL_TXQ1_HICREDIT_HC_MASK (0x1FFFFFFFU) -#define EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT (0U) -/*! HC - hiCredit Value */ -#define EMAC_MTL_TXQ1_HICREDIT_HC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT)) & EMAC_MTL_TXQ1_HICREDIT_HC_MASK) -/*! @} */ - -/*! @name MTL_TXQ1_LOCREDIT - MTL Tx Queue 1 LoCredit */ -/*! @{ */ - -#define EMAC_MTL_TXQ1_LOCREDIT_LC_MASK (0x1FFFFFFFU) -#define EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT (0U) -/*! LC - loCredit Value */ -#define EMAC_MTL_TXQ1_LOCREDIT_LC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT)) & EMAC_MTL_TXQ1_LOCREDIT_LC_MASK) -/*! @} */ - -/*! @name MTL_Q1_INTERRUPT_CONTROL_STATUS - MTL Queue 1 Interrupt Control Status */ -/*! @{ */ - -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK (0x1U) -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT (0U) -/*! TXUNFIS - Transmit Queue Underflow Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK) - -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK (0x2U) -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT (1U) -/*! ABPSIS - Average Bits Per Slot Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK) - -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_MASK (0x100U) -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT (8U) -/*! TXUIE - Transmit Queue Underflow Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_MASK) - -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK (0x200U) -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT (9U) -/*! ABPSIE - Average Bits Per Slot Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK) - -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK (0x10000U) -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT (16U) -/*! RXOVFIS - Receive Queue Overflow Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK) - -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_MASK (0x1000000U) -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT (24U) -/*! RXOIE - Receive Queue Overflow Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_MASK) -/*! @} */ - -/*! @name MTL_RXQ1_OPERATION_MODE - MTL Rx Queue 1 Operation Mode */ -/*! @{ */ - -#define EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK (0x3U) -#define EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT (0U) -/*! RTC - Receive Queue Threshold Control - * 0b00..64 - * 0b01..32 - * 0b10..96 - * 0b11..128 - */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK) - -#define EMAC_MTL_RXQ1_OPERATION_MODE_FUP_MASK (0x8U) -#define EMAC_MTL_RXQ1_OPERATION_MODE_FUP_SHIFT (3U) -/*! FUP - Forward Undersized Good Packets - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_FUP_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_FUP_MASK) - -#define EMAC_MTL_RXQ1_OPERATION_MODE_FEP_MASK (0x10U) -#define EMAC_MTL_RXQ1_OPERATION_MODE_FEP_SHIFT (4U) -/*! FEP - Forward Error Packets - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_FEP_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_FEP_MASK) - -#define EMAC_MTL_RXQ1_OPERATION_MODE_RSF_MASK (0x20U) -#define EMAC_MTL_RXQ1_OPERATION_MODE_RSF_SHIFT (5U) -/*! RSF - Receive Queue Store and Forward - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RSF_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RSF_MASK) - -#define EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_MASK (0x40U) -#define EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_SHIFT (6U) -/*! DIS_TCP_EF - Disable Dropping of TCP or IP Checksum Error Packets - * 0b0..Enabled - * 0b1..Disabled - */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_MASK) - -#define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_MASK (0x80U) -#define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_SHIFT (7U) -/*! EHFC - Enable Hardware Flow Control - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_MASK) - -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK (0xF00U) -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT (8U) -/*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK) - -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK (0x3C000U) -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT (14U) -/*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK) - -#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK (0x1F00000U) -#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT (20U) -/*! RQS - Receive Queue Size */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK) -/*! @} */ - -/*! @name MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT - MTL Rx Queue 1 Missed Packet Overflow Counter */ -/*! @{ */ - -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FFU) -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0U) -/*! OVFPKTCNT - Overflow Packet Counter */ -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) - -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK (0x800U) -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT (11U) -/*! OVFCNTOVF - Overflow Counter Overflow Bit - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT)) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK) - -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF0000U) -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16U) -/*! MISPKTCNT - Missed Packet Counter */ -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) - -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK (0x8000000U) -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT (27U) -/*! MISCNTOVF - Missed Packet Counter Overflow Bit - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT)) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK) -/*! @} */ - -/*! @name MTL_RXQ1_DEBUG - MTL Rx Queue 1 Debug */ -/*! @{ */ - -#define EMAC_MTL_RXQ1_DEBUG_RWCSTS_MASK (0x1U) -#define EMAC_MTL_RXQ1_DEBUG_RWCSTS_SHIFT (0U) -/*! RWCSTS - MTL Rx Queue Write Controller Active Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_MTL_RXQ1_DEBUG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_DEBUG_RWCSTS_SHIFT)) & EMAC_MTL_RXQ1_DEBUG_RWCSTS_MASK) - -#define EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK (0x6U) -#define EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT (1U) -/*! RRCSTS - MTL Rx Queue Read Controller State - * 0b00..Idle state - * 0b01..Reading packet data - * 0b10..Reading packet status (or timestamp) - * 0b11..Flushing the packet data and status - */ -#define EMAC_MTL_RXQ1_DEBUG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT)) & EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK) - -#define EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK (0x30U) -#define EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT (4U) -/*! RXQSTS - MTL Rx Queue Fill-Level Status - * 0b00..Rx Queue empty - * 0b01..Rx Queue fill-level below flow-control deactivate threshold - * 0b10..Rx Queue fill-level above flow-control activate threshold - * 0b11..Rx Queue full - */ -#define EMAC_MTL_RXQ1_DEBUG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT)) & EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK) - -#define EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK (0x3FFF0000U) -#define EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT (16U) -/*! PRXQ - Number of Packets in Receive Queue */ -#define EMAC_MTL_RXQ1_DEBUG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT)) & EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK) -/*! @} */ - -/*! @name MTL_RXQ1_CONTROL - MTL Rx Queue 1 Control */ -/*! @{ */ - -#define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK (0x7U) -#define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT (0U) -/*! RXQ_WEGT - Receive Queue Weight */ -#define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT)) & EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK) - -#define EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_MASK (0x8U) -#define EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_SHIFT (3U) -/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_SHIFT)) & EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_MASK) -/*! @} */ - -/*! @name DMA_MODE - DMA Mode */ -/*! @{ */ - -#define EMAC_DMA_MODE_SWR_MASK (0x1U) -#define EMAC_DMA_MODE_SWR_SHIFT (0U) -/*! SWR - Software Reset - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_SWR_SHIFT)) & EMAC_DMA_MODE_SWR_MASK) - -#define EMAC_DMA_MODE_DA_MASK (0x2U) -#define EMAC_DMA_MODE_DA_SHIFT (1U) -/*! DA - DMA Tx or Rx Arbitration Scheme - * 0b0..Weighted Round-Robin with Rx:Tx or Tx:Rx - * 0b1..Fixed Priority - */ -#define EMAC_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_DA_SHIFT)) & EMAC_DMA_MODE_DA_MASK) - -#define EMAC_DMA_MODE_TAA_MASK (0x1CU) -#define EMAC_DMA_MODE_TAA_SHIFT (2U) -/*! TAA - Transmit Arbitration Algorithm - * 0b000..Fixed priority (Channel 0 has the lowest priority and the last channel has the highest priority) - * 0b001..Weighted Strict Priority (WSP) - * 0b010..Weighted Round-Robin (WRR) - * 0b011..Reserved (for 3'b011 to 3'b111) - */ -#define EMAC_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_TAA_SHIFT)) & EMAC_DMA_MODE_TAA_MASK) - -#define EMAC_DMA_MODE_ARBC_MASK (0x200U) -#define EMAC_DMA_MODE_ARBC_SHIFT (9U) -/*! ARBC - * 0b0..NXP reserved field disabled - * 0b1..NXP reserved field enabled up on NXP request - */ -#define EMAC_DMA_MODE_ARBC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_ARBC_SHIFT)) & EMAC_DMA_MODE_ARBC_MASK) - -#define EMAC_DMA_MODE_TXPR_MASK (0x800U) -#define EMAC_DMA_MODE_TXPR_SHIFT (11U) -/*! TXPR - Transmit Priority - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_TXPR_SHIFT)) & EMAC_DMA_MODE_TXPR_MASK) - -#define EMAC_DMA_MODE_PR_MASK (0x7000U) -#define EMAC_DMA_MODE_PR_SHIFT (12U) -/*! PR - Priority Ratio - * 0b000..The priority ratio is 1:1 - * 0b001..The priority ratio is 2:1 - * 0b010..The priority ratio is 3:1 - * 0b011..The priority ratio is 4:1 - * 0b100..The priority ratio is 5:1 - * 0b101..The priority ratio is 6:1 - * 0b110..The priority ratio is 7:1 - * 0b111..The priority ratio is 8:1 - */ -#define EMAC_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_PR_SHIFT)) & EMAC_DMA_MODE_PR_MASK) - -#define EMAC_DMA_MODE_INTM_MASK (0x30000U) -#define EMAC_DMA_MODE_INTM_SHIFT (16U) -/*! INTM - Interrupt Mode - * 0b00..See above description - * 0b01..See above description - * 0b10..See above description - * 0b11..Reserved - */ -#define EMAC_DMA_MODE_INTM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_INTM_SHIFT)) & EMAC_DMA_MODE_INTM_MASK) -/*! @} */ - -/*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */ -/*! @{ */ - -#define EMAC_DMA_SYSBUS_MODE_FB_MASK (0x1U) -#define EMAC_DMA_SYSBUS_MODE_FB_SHIFT (0U) -/*! FB - Fixed Burst Length - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_FB_SHIFT)) & EMAC_DMA_SYSBUS_MODE_FB_MASK) - -#define EMAC_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) -#define EMAC_DMA_SYSBUS_MODE_AAL_SHIFT (12U) -/*! AAL - Address-Aligned Beats - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_AAL_SHIFT)) & EMAC_DMA_SYSBUS_MODE_AAL_MASK) - -#define EMAC_DMA_SYSBUS_MODE_MB_MASK (0x4000U) -#define EMAC_DMA_SYSBUS_MODE_MB_SHIFT (14U) -/*! MB - Mixed Burst - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_MB_SHIFT)) & EMAC_DMA_SYSBUS_MODE_MB_MASK) - -#define EMAC_DMA_SYSBUS_MODE_RB_MASK (0x8000U) -#define EMAC_DMA_SYSBUS_MODE_RB_SHIFT (15U) -/*! RB - Rebuild INCRx Burst - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_RB_SHIFT)) & EMAC_DMA_SYSBUS_MODE_RB_MASK) -/*! @} */ - -/*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */ -/*! @{ */ - -#define EMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U) -#define EMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U) -/*! DC0IS - DMA Channel 0 Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK) - -#define EMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U) -#define EMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U) -/*! DC1IS - DMA Channel 1 Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK) - -#define EMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U) -#define EMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U) -/*! MTLIS - MTL Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK) - -#define EMAC_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U) -#define EMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U) -/*! MACIS - MAC Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_INTERRUPT_STATUS_MACIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_MACIS_MASK) -/*! @} */ - -/*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */ -/*! @{ */ - -#define EMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U) -#define EMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U) -/*! AXWHSTS - AHB Master Status - * 0b0..Not detected - * 0b1..detected - */ -#define EMAC_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK) - -#define EMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U) -#define EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U) -/*! RPS0 - DMA Channel 0 Receive Process State - * 0b0000..Stopped (Reset or stop receive command issued) - * 0b0001..Running (Fetching receive transfer descriptor) - * 0b0010..Reserved for future use - * 0b0011..Running (Waiting for receive packet) - * 0b0100..Suspended (Receive descriptor unavailable) - * 0b0101..Running (Closing the receive descriptor) - * 0b0110..Timestamp write state - * 0b0111..Running (Transferring the received packet data from the receive buffer to the system memory) - */ -#define EMAC_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_RPS0_MASK) - -#define EMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U) -#define EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U) -/*! TPS0 - DMA Channel 0 Transmit Process State - * 0b0000..Stopped (Reset or stop transmit command issued) - * 0b0001..Running (Fetching transmit transfer descriptor) - * 0b0010..Running (Waiting for status) - * 0b0011..Running (Reading data from system memory buffer and queuing it to the transmit buffer (Tx FIFO)) - * 0b0100..Timestamp write state - * 0b0101..Reserved for future use - * 0b0110..Suspended (Transmit descriptor unavailable or transmit buffer underflow) - * 0b0111..Running (Closing transmit descriptor) - */ -#define EMAC_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_TPS0_MASK) - -#define EMAC_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U) -#define EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U) -/*! RPS1 - DMA Channel 1 Receive Process State - * 0b0000..Stopped (Reset or Stop receive command issued) - * 0b0001..Running (Fetching receive transfer descriptor) - * 0b0010..Reserved for future use - * 0b0011..Running (Waiting for receive packet) - * 0b0100..Suspended (Receive descriptor unavailable) - * 0b0101..Running (Closing the receive descriptor) - * 0b0110..Timestamp write state - * 0b0111..Running (Transferring the received packet data from the receive buffer to the system memory) - */ -#define EMAC_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_RPS1_MASK) - -#define EMAC_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U) -#define EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U) -/*! TPS1 - DMA Channel 1 Transmit Process State - * 0b0000..Stopped (Reset or stop transmit command issued) - * 0b0001..Running (Fetching transmit transfer descriptor) - * 0b0010..Running (Waiting for status) - * 0b0011..Running (Reading data from system memory buffer and queuing it to the transmit buffer (Tx FIFO)) - * 0b0100..Timestamp write state - * 0b0101..Reserved for future use - * 0b0110..Suspended (Transmit descriptor unavailable or transmit buffer underflow) - * 0b0111..Running (Closing transmit descriptor) - */ -#define EMAC_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_TPS1_MASK) -/*! @} */ - -/*! @name DMA_TBS_CTRL - DMA TBS Control */ -/*! @{ */ - -#define EMAC_DMA_TBS_CTRL_FTOV_MASK (0x1U) -#define EMAC_DMA_TBS_CTRL_FTOV_SHIFT (0U) -/*! FTOV - Fetch Time Offset Valid - * 0b0..Invalid - * 0b1..Valid - */ -#define EMAC_DMA_TBS_CTRL_FTOV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_TBS_CTRL_FTOV_SHIFT)) & EMAC_DMA_TBS_CTRL_FTOV_MASK) - -#define EMAC_DMA_TBS_CTRL_FGOS_MASK (0x70U) -#define EMAC_DMA_TBS_CTRL_FGOS_SHIFT (4U) -/*! FGOS - Fetch GSN Offset */ -#define EMAC_DMA_TBS_CTRL_FGOS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_TBS_CTRL_FGOS_SHIFT)) & EMAC_DMA_TBS_CTRL_FGOS_MASK) - -#define EMAC_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF00U) -#define EMAC_DMA_TBS_CTRL_FTOS_SHIFT (8U) -/*! FTOS - Fetch Time Offset */ -#define EMAC_DMA_TBS_CTRL_FTOS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_TBS_CTRL_FTOS_SHIFT)) & EMAC_DMA_TBS_CTRL_FTOS_MASK) -/*! @} */ - -/*! @name DMA_SAFETY_INTERRUPT_STATUS - DMA Safety Interrupt Status */ -/*! @{ */ - -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK (0x1U) -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT (0U) -/*! DECIS - DMA ECC Correctable Error Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK) - -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK (0x2U) -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT (1U) -/*! DEUIS - DMA ECC Uncorrectable Error Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK) - -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK (0x10000000U) -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT (28U) -/*! MSCIS - MTL Safety Correctable Error Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK) - -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK (0x20000000U) -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT (29U) -/*! MSUIS - MTL Safety Uncorrectable Error Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK) - -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK (0x80000000U) -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT (31U) -/*! MCSIS - MAC Safety Uncorrectable Interrupt Status - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK) -/*! @} */ - -/*! @name DMA_CH0_CONTROL - DMA Channel 0 Control */ -/*! @{ */ - -#define EMAC_DMA_CH0_CONTROL_PBLx8_MASK (0x10000U) -#define EMAC_DMA_CH0_CONTROL_PBLx8_SHIFT (16U) -/*! PBLx8 - 8xPBL mode - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_CH0_CONTROL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CONTROL_PBLx8_SHIFT)) & EMAC_DMA_CH0_CONTROL_PBLx8_MASK) - -#define EMAC_DMA_CH0_CONTROL_DSL_MASK (0x1C0000U) -#define EMAC_DMA_CH0_CONTROL_DSL_SHIFT (18U) -/*! DSL - Descriptor Skip Length */ -#define EMAC_DMA_CH0_CONTROL_DSL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CONTROL_DSL_SHIFT)) & EMAC_DMA_CH0_CONTROL_DSL_MASK) -/*! @} */ - -/*! @name DMA_CH0_TX_CONTROL - DMA Channel Tx Control */ -/*! @{ */ - -#define EMAC_DMA_CH0_TX_CONTROL_ST_MASK (0x1U) -#define EMAC_DMA_CH0_TX_CONTROL_ST_SHIFT (0U) -/*! ST - Start or Stop Transmission Command - * 0b0..Stop - * 0b1..Start - */ -#define EMAC_DMA_CH0_TX_CONTROL_ST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_ST_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_ST_MASK) - -#define EMAC_DMA_CH0_TX_CONTROL_TCW_MASK (0xEU) -#define EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT (1U) -/*! TCW - Transmit Channel Weight */ -#define EMAC_DMA_CH0_TX_CONTROL_TCW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_TCW_MASK) - -#define EMAC_DMA_CH0_TX_CONTROL_OSF_MASK (0x10U) -#define EMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT (4U) -/*! OSF - Operate on Second Packet - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_CH0_TX_CONTROL_OSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_OSF_MASK) - -#define EMAC_DMA_CH0_TX_CONTROL_TxPBL_MASK (0x3F0000U) -#define EMAC_DMA_CH0_TX_CONTROL_TxPBL_SHIFT (16U) -/*! TxPBL - Transmit Programmable Burst Length */ -#define EMAC_DMA_CH0_TX_CONTROL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_TxPBL_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_TxPBL_MASK) - -#define EMAC_DMA_CH0_TX_CONTROL_ETIC_MASK (0x400000U) -#define EMAC_DMA_CH0_TX_CONTROL_ETIC_SHIFT (22U) -/*! ETIC - Early Transmit Interrupt Control - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_CH0_TX_CONTROL_ETIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_ETIC_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_ETIC_MASK) - -#define EMAC_DMA_CH0_TX_CONTROL_EDSE_MASK (0x10000000U) -#define EMAC_DMA_CH0_TX_CONTROL_EDSE_SHIFT (28U) -/*! EDSE - Enhanced Descriptor Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_CH0_TX_CONTROL_EDSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_EDSE_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_EDSE_MASK) -/*! @} */ - -/*! @name DMA_CH0_RX_CONTROL - DMA Channel Rx Control */ -/*! @{ */ - -#define EMAC_DMA_CH0_RX_CONTROL_SR_MASK (0x1U) -#define EMAC_DMA_CH0_RX_CONTROL_SR_SHIFT (0U) -/*! SR - Start or Stop Receive - * 0b0..Stop - * 0b1..Start - */ -#define EMAC_DMA_CH0_RX_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_SR_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_SR_MASK) - -#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_MASK (0x6U) -#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_SHIFT (1U) -/*! RBSZ_x_0 - Receive Buffer size Low */ -#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_MASK) - -#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_MASK (0x7FF8U) -#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_SHIFT (3U) -/*! RBSZ_13_y - Receive Buffer size High */ -#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_MASK) - -#define EMAC_DMA_CH0_RX_CONTROL_RxPBL_MASK (0x3F0000U) -#define EMAC_DMA_CH0_RX_CONTROL_RxPBL_SHIFT (16U) -/*! RxPBL - Receive Programmable Burst Length */ -#define EMAC_DMA_CH0_RX_CONTROL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_RxPBL_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_RxPBL_MASK) - -#define EMAC_DMA_CH0_RX_CONTROL_ERIC_MASK (0x400000U) -#define EMAC_DMA_CH0_RX_CONTROL_ERIC_SHIFT (22U) -/*! ERIC - Early Receive Interrupt Control - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_CH0_RX_CONTROL_ERIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_ERIC_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_ERIC_MASK) - -#define EMAC_DMA_CH0_RX_CONTROL_RPF_MASK (0x80000000U) -#define EMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT (31U) -/*! RPF - Rx Packet Flush - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_CH0_RX_CONTROL_RPF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_RPF_MASK) -/*! @} */ - -/*! @name DMA_CH0_TXDESC_LIST_ADDRESS - DMA Channel 0 Tx Descriptor List Address */ -/*! @{ */ - -#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0xFFFFFFFCU) -#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2U) -/*! TDESLA - Start of Transmit List */ -#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)) & EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK) -/*! @} */ - -/*! @name DMA_CH0_RXDESC_LIST_ADDRESS - DMA Channel 0 Rx Descriptor List Address */ -/*! @{ */ - -#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0xFFFFFFFCU) -#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2U) -/*! RDESLA - Start of Receive List */ -#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)) & EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK) -/*! @} */ - -/*! @name DMA_CH0_TXDESC_TAIL_POINTER - DMA Channel 0 Tx Descriptor Tail Pointer */ -/*! @{ */ - -#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0xFFFFFFFCU) -#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT (2U) -/*! TDTP - Transmit Descriptor Tail Pointer */ -#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT)) & EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK) -/*! @} */ - -/*! @name DMA_CH0_RXDESC_TAIL_POINTER - DMA Channeli 0 Rx Descriptor List Pointer */ -/*! @{ */ - -#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK (0xFFFFFFFCU) -#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT (2U) -/*! RDTP - Receive Descriptor Tail Pointer */ -#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT)) & EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK) -/*! @} */ - -/*! @name DMA_CH0_TXDESC_RING_LENGTH - DMA Channel 0 Tx Descriptor Ring Length */ -/*! @{ */ - -#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) -#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) -/*! TDRL - Transmit Descriptor Ring Length */ -#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT)) & EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK) -/*! @} */ - -/*! @name DMA_CH0_RXDESC_RING_LENGTH - DMA Channel 0 Rx Descriptor Ring Length */ -/*! @{ */ - -#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) -#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) -/*! RDRL - Receive Descriptor Ring Length */ -#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT)) & EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK) -/*! @} */ - -/*! @name DMA_CH0_INTERRUPT_ENABLE - DMA Channel 0 Interrupt Enable */ -/*! @{ */ - -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK (0x1U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT (0U) -/*! TIE - Transmit Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK) - -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK (0x2U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT (1U) -/*! TXSE - Transmit Stopped Enable - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK) - -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK (0x4U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT (2U) -/*! TBUE - Transmit Buffer Unavailable Enable - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK) - -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK (0x40U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT (6U) -/*! RIE - Receive Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK) - -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK (0x80U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT (7U) -/*! RBUE - Receive Buffer Unavailable Enable - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK) - -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK (0x100U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT (8U) -/*! RSE - Receive Stopped Enable - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK) - -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK (0x200U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT (9U) -/*! RWTE - Receive Watchdog Timeout Enable - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK) - -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK (0x400U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT (10U) -/*! ETIE - Early Transmit Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK) - -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK (0x800U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT (11U) -/*! ERIE - Early Receive Interrupt Enable - * 0b0..Disable - * 0b1..Enable +#define EMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U) +#define EMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U) +/*! AXWHSTS - AHB Master Status + * 0b0..Not detected + * 0b1..detected */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK) +#define EMAC_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK (0x1000U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT (12U) -/*! FBEE - Fatal Bus Error Enable - * 0b0..Disable - * 0b1..Enable +#define EMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U) +#define EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U) +/*! RPS0 - DMA Channel 0 Receive Process State + * 0b0000..Stopped (Reset or stop receive command issued) + * 0b0001..Running (Fetching receive transfer descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for receive packet) + * 0b0100..Suspended (Receive descriptor unavailable) + * 0b0101..Running (Closing the receive descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the receive buffer to the system memory) */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK) +#define EMAC_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_RPS0_MASK) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK (0x2000U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT (13U) -/*! CDEE - Context Descriptor Error Enable - * 0b0..Disable - * 0b1..Enable +#define EMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U) +#define EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U) +/*! TPS0 - DMA Channel 0 Transmit Process State + * 0b0000..Stopped (Reset or stop transmit command issued) + * 0b0001..Running (Fetching transmit transfer descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading data from system memory buffer and queuing it to the transmit buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Transmit descriptor unavailable or transmit buffer underflow) + * 0b0111..Running (Closing transmit descriptor) */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK) +#define EMAC_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_TPS0_MASK) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK (0x4000U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT (14U) -/*! AIE - Abnormal Interrupt Summary Enable - * 0b0..Disable - * 0b1..Enable +#define EMAC_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U) +#define EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U) +/*! RPS1 - DMA Channel 1 Receive Process State + * 0b0000..Stopped (Reset or Stop receive command issued) + * 0b0001..Running (Fetching receive transfer descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for receive packet) + * 0b0100..Suspended (Receive descriptor unavailable) + * 0b0101..Running (Closing the receive descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the receive buffer to the system memory) */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK) +#define EMAC_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_RPS1_MASK) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK (0x8000U) -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT (15U) -/*! NIE - Normal Interrupt Summary Enable - * 0b0..Disable - * 0b1..Enable +#define EMAC_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U) +#define EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U) +/*! TPS1 - DMA Channel 1 Transmit Process State + * 0b0000..Stopped (Reset or stop transmit command issued) + * 0b0001..Running (Fetching transmit transfer descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading data from system memory buffer and queuing it to the transmit buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Transmit descriptor unavailable or transmit buffer underflow) + * 0b0111..Running (Closing transmit descriptor) */ -#define EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK) -/*! @} */ - -/*! @name DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER - DMA Channel 0 Rx Interrupt Watchdog Timer */ -/*! @{ */ - -#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFFU) -#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0U) -/*! RWT - Receive Interrupt Watchdog Timer Count */ -#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) - -#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x30000U) -#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16U) -/*! RWTU - Receive Interrupt Watchdog Timer Count Units */ -#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT)) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK) +#define EMAC_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_TPS1_MASK) /*! @} */ -/*! @name DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS - DMA Channel 0 Slot Function Control Status */ +/*! @name DMA_TBS_CTRL - DMA TBS Control */ /*! @{ */ -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK (0x1U) -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT (0U) -/*! ESC - Enable Slot Comparison - * 0b0..Disabled - * 0b1..Enabled - */ -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT)) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK) - -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK (0x2U) -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT (1U) -/*! ASC - Advance Slot Check - * 0b0..Disabled - * 0b1..Enabled +#define EMAC_DMA_TBS_CTRL_FTOV_MASK (0x1U) +#define EMAC_DMA_TBS_CTRL_FTOV_SHIFT (0U) +/*! FTOV - Fetch Time Offset Valid + * 0b0..Invalid + * 0b1..Valid */ -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT)) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK) - -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF0U) -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4U) -/*! SIV - Slot Interval Value */ -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) - -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF0000U) -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16U) -/*! RSN - Reference Slot Number */ -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) -/*! @} */ - -/*! @name DMA_CH0_CURRENT_APP_TXDESC - DMA Channel 0 Current Application Transmit Descriptor */ -/*! @{ */ - -#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU) -#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0U) -/*! CURTDESAPTR - Application Transmit Descriptor Address Pointer */ -#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)) & EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) -/*! @} */ - -/*! @name DMA_CH0_CURRENT_APP_RXDESC - DMA Channel 0 Current Application Receive Descriptor */ -/*! @{ */ - -#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU) -#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0U) -/*! CURRDESAPTR - Application Receive Descriptor Address Pointer */ -#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)) & EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) -/*! @} */ - -/*! @name DMA_CH0_CURRENT_APP_TXBUFFER - DMA Channel 0 Current Application Transmit Descriptor */ -/*! @{ */ - -#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFFU) -#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0U) -/*! CURTBUFAPTR - Application Transmit Buffer Address Pointer */ -#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)) & EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) -/*! @} */ +#define EMAC_DMA_TBS_CTRL_FTOV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_TBS_CTRL_FTOV_SHIFT)) & EMAC_DMA_TBS_CTRL_FTOV_MASK) -/*! @name DMA_CH0_CURRENT_APP_RXBUFFER - DMA Channel 0 Current Application Receive Buffer */ -/*! @{ */ +#define EMAC_DMA_TBS_CTRL_FGOS_MASK (0x70U) +#define EMAC_DMA_TBS_CTRL_FGOS_SHIFT (4U) +/*! FGOS - Fetch GSN Offset */ +#define EMAC_DMA_TBS_CTRL_FGOS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_TBS_CTRL_FGOS_SHIFT)) & EMAC_DMA_TBS_CTRL_FGOS_MASK) -#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFFU) -#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0U) -/*! CURRBUFAPTR - Application Receive Buffer Address Pointer */ -#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)) & EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) +#define EMAC_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF00U) +#define EMAC_DMA_TBS_CTRL_FTOS_SHIFT (8U) +/*! FTOS - Fetch Time Offset */ +#define EMAC_DMA_TBS_CTRL_FTOS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_TBS_CTRL_FTOS_SHIFT)) & EMAC_DMA_TBS_CTRL_FTOS_MASK) /*! @} */ -/*! @name DMA_CH0_STATUS - DMA Channel 0 Status */ +/*! @name DMA_SAFETY_INTERRUPT_STATUS - DMA Safety Interrupt Status */ /*! @{ */ -#define EMAC_DMA_CH0_STATUS_TI_MASK (0x1U) -#define EMAC_DMA_CH0_STATUS_TI_SHIFT (0U) -/*! TI - Transmit Interrupt - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_CH0_STATUS_TI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_TI_SHIFT)) & EMAC_DMA_CH0_STATUS_TI_MASK) - -#define EMAC_DMA_CH0_STATUS_TPS_MASK (0x2U) -#define EMAC_DMA_CH0_STATUS_TPS_SHIFT (1U) -/*! TPS - Transmit Process Stopped - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_CH0_STATUS_TPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_TPS_SHIFT)) & EMAC_DMA_CH0_STATUS_TPS_MASK) - -#define EMAC_DMA_CH0_STATUS_TBU_MASK (0x4U) -#define EMAC_DMA_CH0_STATUS_TBU_SHIFT (2U) -/*! TBU - Transmit Buffer Unavailable - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_CH0_STATUS_TBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_TBU_SHIFT)) & EMAC_DMA_CH0_STATUS_TBU_MASK) - -#define EMAC_DMA_CH0_STATUS_RI_MASK (0x40U) -#define EMAC_DMA_CH0_STATUS_RI_SHIFT (6U) -/*! RI - Receive Interrupt - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_CH0_STATUS_RI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_RI_SHIFT)) & EMAC_DMA_CH0_STATUS_RI_MASK) - -#define EMAC_DMA_CH0_STATUS_RBU_MASK (0x80U) -#define EMAC_DMA_CH0_STATUS_RBU_SHIFT (7U) -/*! RBU - Receive Buffer Unavailable - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_CH0_STATUS_RBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_RBU_SHIFT)) & EMAC_DMA_CH0_STATUS_RBU_MASK) - -#define EMAC_DMA_CH0_STATUS_RPS_MASK (0x100U) -#define EMAC_DMA_CH0_STATUS_RPS_SHIFT (8U) -/*! RPS - Receive Process Stopped - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_CH0_STATUS_RPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_RPS_SHIFT)) & EMAC_DMA_CH0_STATUS_RPS_MASK) - -#define EMAC_DMA_CH0_STATUS_RWT_MASK (0x200U) -#define EMAC_DMA_CH0_STATUS_RWT_SHIFT (9U) -/*! RWT - Receive Watchdog Timeout - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_CH0_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_RWT_SHIFT)) & EMAC_DMA_CH0_STATUS_RWT_MASK) - -#define EMAC_DMA_CH0_STATUS_ETI_MASK (0x400U) -#define EMAC_DMA_CH0_STATUS_ETI_SHIFT (10U) -/*! ETI - Early Transmit Interrupt - * 0b0..Not detected - * 0b1..Detected - */ -#define EMAC_DMA_CH0_STATUS_ETI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_ETI_SHIFT)) & EMAC_DMA_CH0_STATUS_ETI_MASK) - -#define EMAC_DMA_CH0_STATUS_ERI_MASK (0x800U) -#define EMAC_DMA_CH0_STATUS_ERI_SHIFT (11U) -/*! ERI - Early Receive Interrupt +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK (0x1U) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT (0U) +/*! DECIS - DMA ECC Correctable Error Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH0_STATUS_ERI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_ERI_SHIFT)) & EMAC_DMA_CH0_STATUS_ERI_MASK) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK) -#define EMAC_DMA_CH0_STATUS_FBE_MASK (0x1000U) -#define EMAC_DMA_CH0_STATUS_FBE_SHIFT (12U) -/*! FBE - Fatal Bus Error +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK (0x2U) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT (1U) +/*! DEUIS - DMA ECC Uncorrectable Error Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH0_STATUS_FBE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_FBE_SHIFT)) & EMAC_DMA_CH0_STATUS_FBE_MASK) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK) -#define EMAC_DMA_CH0_STATUS_CDE_MASK (0x2000U) -#define EMAC_DMA_CH0_STATUS_CDE_SHIFT (13U) -/*! CDE - Context Descriptor Error +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK (0x10000000U) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT (28U) +/*! MSCIS - MTL Safety Correctable Error Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH0_STATUS_CDE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_CDE_SHIFT)) & EMAC_DMA_CH0_STATUS_CDE_MASK) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK) -#define EMAC_DMA_CH0_STATUS_AIS_MASK (0x4000U) -#define EMAC_DMA_CH0_STATUS_AIS_SHIFT (14U) -/*! AIS - Abnormal Interrupt Summary +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK (0x20000000U) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT (29U) +/*! MSUIS - MTL Safety Uncorrectable Error Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH0_STATUS_AIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_AIS_SHIFT)) & EMAC_DMA_CH0_STATUS_AIS_MASK) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK) -#define EMAC_DMA_CH0_STATUS_NIS_MASK (0x8000U) -#define EMAC_DMA_CH0_STATUS_NIS_SHIFT (15U) -/*! NIS - Normal Interrupt Summary +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK (0x80000000U) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT (31U) +/*! MCSIS - MAC Safety Uncorrectable Interrupt Status * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH0_STATUS_NIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_NIS_SHIFT)) & EMAC_DMA_CH0_STATUS_NIS_MASK) - -#define EMAC_DMA_CH0_STATUS_TEB_MASK (0x70000U) -#define EMAC_DMA_CH0_STATUS_TEB_SHIFT (16U) -/*! TEB - Tx DMA Error Bits */ -#define EMAC_DMA_CH0_STATUS_TEB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_TEB_SHIFT)) & EMAC_DMA_CH0_STATUS_TEB_MASK) - -#define EMAC_DMA_CH0_STATUS_REB_MASK (0x380000U) -#define EMAC_DMA_CH0_STATUS_REB_SHIFT (19U) -/*! REB - Rx DMA Error Bits */ -#define EMAC_DMA_CH0_STATUS_REB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_REB_SHIFT)) & EMAC_DMA_CH0_STATUS_REB_MASK) -/*! @} */ - -/*! @name DMA_CH0_MISS_FRAME_CNT - DMA Channel 0 Miss Frame Counter */ -/*! @{ */ - -#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7FFU) -#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0U) -#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT)) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK) - -#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_MASK (0x8000U) -#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_SHIFT (15U) -/*! MFCO - Overflow status of the MFC Counter - * 0b0..Not occurred - * 0b1..Occurred - */ -#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_SHIFT)) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_MASK) -/*! @} */ - -/*! @name DMA_CH0_RXP_ACCEPT_CNT - DMA Channel 0 Rx Parser Accept Count */ -/*! @{ */ - -#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU) -#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U) -/*! RXPAC - Rx Parser Accept Counter */ -#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK) - -#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U) -#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U) -/*! RXPACOF - Rx Parser Accept Counter Overflow Bit - * 0b0..Not occurred - * 0b1..Occurred - */ -#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_MASK) -/*! @} */ - -/*! @name DMA_CH0_RX_ERI_CNT - DMA Channel 0 Rx ERI Count */ -/*! @{ */ - -#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0xFFFU) -#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT (0U) -/*! ECNT - ERI Counter */ -#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT)) & EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK) +#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK) /*! @} */ -/*! @name DMA_CH1_CONTROL - DMA Channel 1 Control */ +/*! @name DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 1 Control */ /*! @{ */ -#define EMAC_DMA_CH1_CONTROL_PBLx8_MASK (0x10000U) -#define EMAC_DMA_CH1_CONTROL_PBLx8_SHIFT (16U) +#define EMAC_DMA_CHX_CTRL_PBLx8_MASK (0x10000U) +#define EMAC_DMA_CHX_CTRL_PBLx8_SHIFT (16U) /*! PBLx8 - 8xPBL mode * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_DMA_CH1_CONTROL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CONTROL_PBLx8_SHIFT)) & EMAC_DMA_CH1_CONTROL_PBLx8_MASK) +#define EMAC_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_CTRL_PBLx8_SHIFT)) & EMAC_DMA_CHX_CTRL_PBLx8_MASK) -#define EMAC_DMA_CH1_CONTROL_DSL_MASK (0x1C0000U) -#define EMAC_DMA_CH1_CONTROL_DSL_SHIFT (18U) +#define EMAC_DMA_CHX_CTRL_DSL_MASK (0x1C0000U) +#define EMAC_DMA_CHX_CTRL_DSL_SHIFT (18U) /*! DSL - Descriptor Skip Length */ -#define EMAC_DMA_CH1_CONTROL_DSL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CONTROL_DSL_SHIFT)) & EMAC_DMA_CH1_CONTROL_DSL_MASK) +#define EMAC_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_CTRL_DSL_SHIFT)) & EMAC_DMA_CHX_CTRL_DSL_MASK) /*! @} */ -/*! @name DMA_CH1_TX_CONTROL - DMA Channel 1 Tx Control */ +/* The count of EMAC_DMA_CHX_CTRL */ +#define EMAC_DMA_CHX_CTRL_COUNT (2U) + +/*! @name DMA_CHX_TX_CTRL - DMA Channel Tx Control..DMA Channel 1 Tx Control */ /*! @{ */ -#define EMAC_DMA_CH1_TX_CONTROL_ST_MASK (0x1U) -#define EMAC_DMA_CH1_TX_CONTROL_ST_SHIFT (0U) +#define EMAC_DMA_CHX_TX_CTRL_ST_MASK (0x1U) +#define EMAC_DMA_CHX_TX_CTRL_ST_SHIFT (0U) /*! ST - Start or Stop Transmission Command * 0b0..Stop * 0b1..Start */ -#define EMAC_DMA_CH1_TX_CONTROL_ST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_ST_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_ST_MASK) +#define EMAC_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_TX_CTRL_ST_SHIFT)) & EMAC_DMA_CHX_TX_CTRL_ST_MASK) -#define EMAC_DMA_CH1_TX_CONTROL_TCW_MASK (0xEU) -#define EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT (1U) +#define EMAC_DMA_CHX_TX_CTRL_TCW_MASK (0xEU) +#define EMAC_DMA_CHX_TX_CTRL_TCW_SHIFT (1U) /*! TCW - Transmit Channel Weight */ -#define EMAC_DMA_CH1_TX_CONTROL_TCW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_TCW_MASK) +#define EMAC_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_TX_CTRL_TCW_SHIFT)) & EMAC_DMA_CHX_TX_CTRL_TCW_MASK) -#define EMAC_DMA_CH1_TX_CONTROL_OSF_MASK (0x10U) -#define EMAC_DMA_CH1_TX_CONTROL_OSF_SHIFT (4U) +#define EMAC_DMA_CHX_TX_CTRL_OSF_MASK (0x10U) +#define EMAC_DMA_CHX_TX_CTRL_OSF_SHIFT (4U) /*! OSF - Operate on Second Packet * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_DMA_CH1_TX_CONTROL_OSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_OSF_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_OSF_MASK) +#define EMAC_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_TX_CTRL_OSF_SHIFT)) & EMAC_DMA_CHX_TX_CTRL_OSF_MASK) -#define EMAC_DMA_CH1_TX_CONTROL_TxPBL_MASK (0x3F0000U) -#define EMAC_DMA_CH1_TX_CONTROL_TxPBL_SHIFT (16U) +#define EMAC_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U) +#define EMAC_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U) /*! TxPBL - Transmit Programmable Burst Length */ -#define EMAC_DMA_CH1_TX_CONTROL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_TxPBL_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_TxPBL_MASK) +#define EMAC_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & EMAC_DMA_CHX_TX_CTRL_TxPBL_MASK) -#define EMAC_DMA_CH1_TX_CONTROL_ETIC_MASK (0x400000U) -#define EMAC_DMA_CH1_TX_CONTROL_ETIC_SHIFT (22U) +#define EMAC_DMA_CHX_TX_CTRL_ETIC_MASK (0x400000U) +#define EMAC_DMA_CHX_TX_CTRL_ETIC_SHIFT (22U) /*! ETIC - Early Transmit Interrupt Control * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_DMA_CH1_TX_CONTROL_ETIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_ETIC_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_ETIC_MASK) +#define EMAC_DMA_CHX_TX_CTRL_ETIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_TX_CTRL_ETIC_SHIFT)) & EMAC_DMA_CHX_TX_CTRL_ETIC_MASK) -#define EMAC_DMA_CH1_TX_CONTROL_EDSE_MASK (0x10000000U) -#define EMAC_DMA_CH1_TX_CONTROL_EDSE_SHIFT (28U) +#define EMAC_DMA_CHX_TX_CTRL_EDSE_MASK (0x10000000U) +#define EMAC_DMA_CHX_TX_CTRL_EDSE_SHIFT (28U) /*! EDSE - Enhanced Descriptor Enable * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_DMA_CH1_TX_CONTROL_EDSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_EDSE_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_EDSE_MASK) +#define EMAC_DMA_CHX_TX_CTRL_EDSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_TX_CTRL_EDSE_SHIFT)) & EMAC_DMA_CHX_TX_CTRL_EDSE_MASK) /*! @} */ -/*! @name DMA_CH1_RX_CONTROL - DMA Channel 1 Rx Control */ +/* The count of EMAC_DMA_CHX_TX_CTRL */ +#define EMAC_DMA_CHX_TX_CTRL_COUNT (2U) + +/*! @name DMA_CHX_RX_CTRL - DMA Channel Rx Control..DMA Channel 1 Rx Control */ /*! @{ */ -#define EMAC_DMA_CH1_RX_CONTROL_SR_MASK (0x1U) -#define EMAC_DMA_CH1_RX_CONTROL_SR_SHIFT (0U) +#define EMAC_DMA_CHX_RX_CTRL_SR_MASK (0x1U) +#define EMAC_DMA_CHX_RX_CTRL_SR_SHIFT (0U) /*! SR - Start or Stop Receive * 0b0..Stop * 0b1..Start */ -#define EMAC_DMA_CH1_RX_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_SR_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_SR_MASK) +#define EMAC_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RX_CTRL_SR_SHIFT)) & EMAC_DMA_CHX_RX_CTRL_SR_MASK) -#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_MASK (0x6U) -#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_SHIFT (1U) +#define EMAC_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK (0x6U) +#define EMAC_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT (1U) /*! RBSZ_x_0 - Receive Buffer size Low */ -#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_MASK) +#define EMAC_DMA_CHX_RX_CTRL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & EMAC_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK) -#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_MASK (0x7FF8U) -#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_SHIFT (3U) +#define EMAC_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK (0x7FF8U) +#define EMAC_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (3U) /*! RBSZ_13_y - Receive Buffer size High */ -#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_MASK) +#define EMAC_DMA_CHX_RX_CTRL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & EMAC_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK) -#define EMAC_DMA_CH1_RX_CONTROL_RxPBL_MASK (0x3F0000U) -#define EMAC_DMA_CH1_RX_CONTROL_RxPBL_SHIFT (16U) +#define EMAC_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U) +#define EMAC_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U) /*! RxPBL - Receive Programmable Burst Length */ -#define EMAC_DMA_CH1_RX_CONTROL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_RxPBL_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_RxPBL_MASK) +#define EMAC_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & EMAC_DMA_CHX_RX_CTRL_RxPBL_MASK) -#define EMAC_DMA_CH1_RX_CONTROL_ERIC_MASK (0x400000U) -#define EMAC_DMA_CH1_RX_CONTROL_ERIC_SHIFT (22U) +#define EMAC_DMA_CHX_RX_CTRL_ERIC_MASK (0x400000U) +#define EMAC_DMA_CHX_RX_CTRL_ERIC_SHIFT (22U) /*! ERIC - Early Receive Interrupt Control * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_DMA_CH1_RX_CONTROL_ERIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_ERIC_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_ERIC_MASK) +#define EMAC_DMA_CHX_RX_CTRL_ERIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RX_CTRL_ERIC_SHIFT)) & EMAC_DMA_CHX_RX_CTRL_ERIC_MASK) -#define EMAC_DMA_CH1_RX_CONTROL_RPF_MASK (0x80000000U) -#define EMAC_DMA_CH1_RX_CONTROL_RPF_SHIFT (31U) +#define EMAC_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U) +#define EMAC_DMA_CHX_RX_CTRL_RPF_SHIFT (31U) /*! RPF - Rx Packet Flush * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_DMA_CH1_RX_CONTROL_RPF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_RPF_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_RPF_MASK) +#define EMAC_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RX_CTRL_RPF_SHIFT)) & EMAC_DMA_CHX_RX_CTRL_RPF_MASK) /*! @} */ -/*! @name DMA_CH1_TXDESC_LIST_ADDRESS - DMA Channel 1 Tx Descriptor List Address */ +/* The count of EMAC_DMA_CHX_RX_CTRL */ +#define EMAC_DMA_CHX_RX_CTRL_COUNT (2U) + +/*! @name DMA_CHX_TXDESC_LIST_ADDR - DMA Channel 0 Tx Descriptor List Address..DMA Channel 1 Tx Descriptor List Address */ /*! @{ */ -#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK (0xFFFFFFFCU) -#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2U) +#define EMAC_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFFCU) +#define EMAC_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (2U) /*! TDESLA - Start of Transmit List */ -#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)) & EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK) +#define EMAC_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & EMAC_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK) /*! @} */ -/*! @name DMA_CH1_RXDESC_LIST_ADDRESS - DMA Channel 1 Rx Descriptor List Address */ +/* The count of EMAC_DMA_CHX_TXDESC_LIST_ADDR */ +#define EMAC_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U) + +/*! @name DMA_CHX_RXDESC_LIST_ADDR - DMA Channel 0 Rx Descriptor List Address..DMA Channel 1 Rx Descriptor List Address */ /*! @{ */ -#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK (0xFFFFFFFCU) -#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2U) +#define EMAC_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFFCU) +#define EMAC_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (2U) /*! RDESLA - Start of Receive List */ -#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)) & EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK) +#define EMAC_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & EMAC_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK) /*! @} */ -/*! @name DMA_CH1_TXDESC_TAIL_POINTER - DMA Channel 1 Tx Descriptor Tail Pointer */ +/* The count of EMAC_DMA_CHX_RXDESC_LIST_ADDR */ +#define EMAC_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U) + +/*! @name DMA_CHX_TXDESC_TAIL_PTR - DMA Channel 0 Tx Descriptor Tail Pointer..DMA Channel 1 Tx Descriptor Tail Pointer */ /*! @{ */ -#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK (0xFFFFFFFCU) -#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT (2U) +#define EMAC_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU) +#define EMAC_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U) /*! TDTP - Transmit Descriptor Tail Pointer */ -#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT)) & EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK) +#define EMAC_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & EMAC_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK) /*! @} */ -/*! @name DMA_CH1_RXDESC_TAIL_POINTER - DMA Channel 1 Rx Descriptor Tail Pointer */ +/* The count of EMAC_DMA_CHX_TXDESC_TAIL_PTR */ +#define EMAC_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U) + +/*! @name DMA_CHX_RXDESC_TAIL_PTR - DMA Channeli 0 Rx Descriptor List Pointer..DMA Channel 1 Rx Descriptor Tail Pointer */ /*! @{ */ -#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK (0xFFFFFFFCU) -#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT (2U) +#define EMAC_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU) +#define EMAC_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U) /*! RDTP - Receive Descriptor Tail Pointer */ -#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT)) & EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK) +#define EMAC_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & EMAC_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK) /*! @} */ -/*! @name DMA_CH1_TXDESC_RING_LENGTH - DMA Channel 1 Tx Descriptor Ring Length */ +/* The count of EMAC_DMA_CHX_RXDESC_TAIL_PTR */ +#define EMAC_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U) + +/*! @name DMA_CHX_TXDESC_RING_LENGTH - DMA Channel 0 Tx Descriptor Ring Length..DMA Channel 1 Tx Descriptor Ring Length */ /*! @{ */ -#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) -#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) +#define EMAC_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) +#define EMAC_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) /*! TDRL - Transmit Descriptor Ring Length */ -#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT)) & EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK) +#define EMAC_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & EMAC_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK) /*! @} */ -/*! @name DMA_CH1_RXDESC_RING_LENGTH - DMA Channel 1 Rx Descriptor Ring Length */ +/* The count of EMAC_DMA_CHX_TXDESC_RING_LENGTH */ +#define EMAC_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U) + +/*! @name DMA_CHX_RXDESC_RING_LENGTH - DMA Channel 0 Rx Descriptor Ring Length..DMA Channel 1 Rx Descriptor Ring Length */ /*! @{ */ -#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) -#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) +#define EMAC_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) +#define EMAC_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) /*! RDRL - Receive Descriptor Ring Length */ -#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT)) & EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK) +#define EMAC_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & EMAC_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK) /*! @} */ -/*! @name DMA_CH1_INTERRUPT_ENABLE - DMA Channel 1 Interrupt Enable */ +/* The count of EMAC_DMA_CHX_RXDESC_RING_LENGTH */ +#define EMAC_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U) + +/*! @name DMA_CHX_INT_EN - DMA Channel 0 Interrupt Enable..DMA Channel 1 Interrupt Enable */ /*! @{ */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_MASK (0x1U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_SHIFT (0U) +#define EMAC_DMA_CHX_INT_EN_TIE_MASK (0x1U) +#define EMAC_DMA_CHX_INT_EN_TIE_SHIFT (0U) /*! TIE - Transmit Interrupt Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_MASK) +#define EMAC_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_TIE_SHIFT)) & EMAC_DMA_CHX_INT_EN_TIE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_MASK (0x2U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_SHIFT (1U) +#define EMAC_DMA_CHX_INT_EN_TXSE_MASK (0x2U) +#define EMAC_DMA_CHX_INT_EN_TXSE_SHIFT (1U) /*! TXSE - Transmit Stopped Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_MASK) +#define EMAC_DMA_CHX_INT_EN_TXSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_TXSE_SHIFT)) & EMAC_DMA_CHX_INT_EN_TXSE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_MASK (0x4U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_SHIFT (2U) +#define EMAC_DMA_CHX_INT_EN_TBUE_MASK (0x4U) +#define EMAC_DMA_CHX_INT_EN_TBUE_SHIFT (2U) /*! TBUE - Transmit Buffer Unavailable Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_MASK) +#define EMAC_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_TBUE_SHIFT)) & EMAC_DMA_CHX_INT_EN_TBUE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_MASK (0x40U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_SHIFT (6U) +#define EMAC_DMA_CHX_INT_EN_RIE_MASK (0x40U) +#define EMAC_DMA_CHX_INT_EN_RIE_SHIFT (6U) /*! RIE - Receive Interrupt Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_MASK) +#define EMAC_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_RIE_SHIFT)) & EMAC_DMA_CHX_INT_EN_RIE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_MASK (0x80U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_SHIFT (7U) +#define EMAC_DMA_CHX_INT_EN_RBUE_MASK (0x80U) +#define EMAC_DMA_CHX_INT_EN_RBUE_SHIFT (7U) /*! RBUE - Receive Buffer Unavailable Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_MASK) +#define EMAC_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_RBUE_SHIFT)) & EMAC_DMA_CHX_INT_EN_RBUE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_MASK (0x100U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_SHIFT (8U) +#define EMAC_DMA_CHX_INT_EN_RSE_MASK (0x100U) +#define EMAC_DMA_CHX_INT_EN_RSE_SHIFT (8U) /*! RSE - Receive Stopped Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_MASK) +#define EMAC_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_RSE_SHIFT)) & EMAC_DMA_CHX_INT_EN_RSE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_MASK (0x200U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_SHIFT (9U) +#define EMAC_DMA_CHX_INT_EN_RWTE_MASK (0x200U) +#define EMAC_DMA_CHX_INT_EN_RWTE_SHIFT (9U) /*! RWTE - Receive Watchdog Timeout Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_MASK) +#define EMAC_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_RWTE_SHIFT)) & EMAC_DMA_CHX_INT_EN_RWTE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_MASK (0x400U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_SHIFT (10U) +#define EMAC_DMA_CHX_INT_EN_ETIE_MASK (0x400U) +#define EMAC_DMA_CHX_INT_EN_ETIE_SHIFT (10U) /*! ETIE - Early Transmit Interrupt Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_MASK) +#define EMAC_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_ETIE_SHIFT)) & EMAC_DMA_CHX_INT_EN_ETIE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_MASK (0x800U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_SHIFT (11U) +#define EMAC_DMA_CHX_INT_EN_ERIE_MASK (0x800U) +#define EMAC_DMA_CHX_INT_EN_ERIE_SHIFT (11U) /*! ERIE - Early Receive Interrupt Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_MASK) +#define EMAC_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_ERIE_SHIFT)) & EMAC_DMA_CHX_INT_EN_ERIE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_MASK (0x1000U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_SHIFT (12U) +#define EMAC_DMA_CHX_INT_EN_FBEE_MASK (0x1000U) +#define EMAC_DMA_CHX_INT_EN_FBEE_SHIFT (12U) /*! FBEE - Fatal Bus Error Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_MASK) +#define EMAC_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_FBEE_SHIFT)) & EMAC_DMA_CHX_INT_EN_FBEE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_MASK (0x2000U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_SHIFT (13U) +#define EMAC_DMA_CHX_INT_EN_CDEE_MASK (0x2000U) +#define EMAC_DMA_CHX_INT_EN_CDEE_SHIFT (13U) /*! CDEE - Context Descriptor Error Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_MASK) +#define EMAC_DMA_CHX_INT_EN_CDEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_CDEE_SHIFT)) & EMAC_DMA_CHX_INT_EN_CDEE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_MASK (0x4000U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_SHIFT (14U) +#define EMAC_DMA_CHX_INT_EN_AIE_MASK (0x4000U) +#define EMAC_DMA_CHX_INT_EN_AIE_SHIFT (14U) /*! AIE - Abnormal Interrupt Summary Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_MASK) +#define EMAC_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_AIE_SHIFT)) & EMAC_DMA_CHX_INT_EN_AIE_MASK) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_MASK (0x8000U) -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_SHIFT (15U) +#define EMAC_DMA_CHX_INT_EN_NIE_MASK (0x8000U) +#define EMAC_DMA_CHX_INT_EN_NIE_SHIFT (15U) /*! NIE - Normal Interrupt Summary Enable * 0b0..Disable * 0b1..Enable */ -#define EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_MASK) +#define EMAC_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_INT_EN_NIE_SHIFT)) & EMAC_DMA_CHX_INT_EN_NIE_MASK) /*! @} */ -/*! @name DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER - DMA Channel 1 Rx Interrupt Watchdog Timer */ +/* The count of EMAC_DMA_CHX_INT_EN */ +#define EMAC_DMA_CHX_INT_EN_COUNT (2U) + +/*! @name DMA_CHX_RX_INT_WDTIMER - DMA Channel 0 Rx Interrupt Watchdog Timer..DMA Channel 1 Rx Interrupt Watchdog Timer */ /*! @{ */ -#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFFU) -#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0U) +#define EMAC_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU) +#define EMAC_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U) /*! RWT - Receive Interrupt Watchdog Timer Count */ -#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) +#define EMAC_DMA_CHX_RX_INT_WDTIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & EMAC_DMA_CHX_RX_INT_WDTIMER_RWT_MASK) -#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x30000U) -#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16U) +#define EMAC_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U) +#define EMAC_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U) /*! RWTU - Receive Interrupt Watchdog Timer Count Units */ -#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT)) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK) +#define EMAC_DMA_CHX_RX_INT_WDTIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & EMAC_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK) /*! @} */ -/*! @name DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS - DMA Channel 1 Slot Function Control Status */ +/* The count of EMAC_DMA_CHX_RX_INT_WDTIMER */ +#define EMAC_DMA_CHX_RX_INT_WDTIMER_COUNT (2U) + +/*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - DMA Channel 0 Slot Function Control Status..DMA Channel 1 Slot Function Control Status */ /*! @{ */ -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK (0x1U) -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT (0U) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U) /*! ESC - Enable Slot Comparison - * 0b0..Disable - * 0b1..Enable + * 0b0..Disabled + * 0b1..Enabled */ -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT)) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK) -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK (0x2U) -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT (1U) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U) /*! ASC - Advance Slot Check * 0b0..Disabled * 0b1..Enabled */ -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT)) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK) -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF0U) -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4U) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U) /*! SIV - Slot Interval Value */ -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK) -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF0000U) -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16U) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U) /*! RSN - Reference Slot Number */ -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK) /*! @} */ -/*! @name DMA_CH1_CURRENT_APP_TXDESC - DMA Channel 1 Current Application Transmit Descriptor */ +/* The count of EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT */ +#define EMAC_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U) + +/*! @name DMA_CHX_CUR_HST_TXDESC - DMA Channel 0 Current Application Transmit Descriptor..DMA Channel 1 Current Application Transmit Descriptor */ /*! @{ */ -#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU) -#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0U) +#define EMAC_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU) +#define EMAC_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U) /*! CURTDESAPTR - Application Transmit Descriptor Address Pointer */ -#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)) & EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) +#define EMAC_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & EMAC_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK) /*! @} */ -/*! @name DMA_CH1_CURRENT_APP_RXDESC - DMA Channel 1 Current Application Receive Descriptor */ +/* The count of EMAC_DMA_CHX_CUR_HST_TXDESC */ +#define EMAC_DMA_CHX_CUR_HST_TXDESC_COUNT (2U) + +/*! @name DMA_CHX_CUR_HST_RXDESC - DMA Channel 0 Current Application Receive Descriptor..DMA Channel 1 Current Application Receive Descriptor */ /*! @{ */ -#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU) -#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0U) +#define EMAC_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU) +#define EMAC_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U) /*! CURRDESAPTR - Application Receive Descriptor Address Pointer */ -#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)) & EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) +#define EMAC_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & EMAC_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK) /*! @} */ -/*! @name DMA_CH1_CURRENT_APP_TXBUFFER - DMA Channel 1 Current Application Transmit Buffer */ +/* The count of EMAC_DMA_CHX_CUR_HST_RXDESC */ +#define EMAC_DMA_CHX_CUR_HST_RXDESC_COUNT (2U) + +/*! @name DMA_CHX_CUR_HST_TXBUF - DMA Channel 0 Current Application Transmit Descriptor..DMA Channel 1 Current Application Transmit Buffer */ /*! @{ */ -#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFFU) -#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0U) +#define EMAC_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU) +#define EMAC_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U) /*! CURTBUFAPTR - Application Transmit Buffer Address Pointer */ -#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)) & EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) +#define EMAC_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & EMAC_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK) /*! @} */ -/*! @name DMA_CH1_CURRENT_APP_RXBUFFER - DMA Channel 1 Current Application Receive Buffer */ +/* The count of EMAC_DMA_CHX_CUR_HST_TXBUF */ +#define EMAC_DMA_CHX_CUR_HST_TXBUF_COUNT (2U) + +/*! @name DMA_CHX_CUR_HST_RXBUF - DMA Channel 0 Current Application Receive Buffer..DMA Channel 1 Current Application Receive Buffer */ /*! @{ */ -#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFFU) -#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0U) +#define EMAC_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU) +#define EMAC_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U) /*! CURRBUFAPTR - Application Receive Buffer Address Pointer */ -#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)) & EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) +#define EMAC_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & EMAC_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK) /*! @} */ -/*! @name DMA_CH1_STATUS - DMA Channel 1 Status */ +/* The count of EMAC_DMA_CHX_CUR_HST_RXBUF */ +#define EMAC_DMA_CHX_CUR_HST_RXBUF_COUNT (2U) + +/*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 1 Status */ /*! @{ */ -#define EMAC_DMA_CH1_STATUS_TI_MASK (0x1U) -#define EMAC_DMA_CH1_STATUS_TI_SHIFT (0U) +#define EMAC_DMA_CHX_STAT_TI_MASK (0x1U) +#define EMAC_DMA_CHX_STAT_TI_SHIFT (0U) /*! TI - Transmit Interrupt * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_TI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_TI_SHIFT)) & EMAC_DMA_CH1_STATUS_TI_MASK) +#define EMAC_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_TI_SHIFT)) & EMAC_DMA_CHX_STAT_TI_MASK) -#define EMAC_DMA_CH1_STATUS_TPS_MASK (0x2U) -#define EMAC_DMA_CH1_STATUS_TPS_SHIFT (1U) +#define EMAC_DMA_CHX_STAT_TPS_MASK (0x2U) +#define EMAC_DMA_CHX_STAT_TPS_SHIFT (1U) /*! TPS - Transmit Process Stopped * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_TPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_TPS_SHIFT)) & EMAC_DMA_CH1_STATUS_TPS_MASK) +#define EMAC_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_TPS_SHIFT)) & EMAC_DMA_CHX_STAT_TPS_MASK) -#define EMAC_DMA_CH1_STATUS_TBU_MASK (0x4U) -#define EMAC_DMA_CH1_STATUS_TBU_SHIFT (2U) +#define EMAC_DMA_CHX_STAT_TBU_MASK (0x4U) +#define EMAC_DMA_CHX_STAT_TBU_SHIFT (2U) /*! TBU - Transmit Buffer Unavailable * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_TBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_TBU_SHIFT)) & EMAC_DMA_CH1_STATUS_TBU_MASK) +#define EMAC_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_TBU_SHIFT)) & EMAC_DMA_CHX_STAT_TBU_MASK) -#define EMAC_DMA_CH1_STATUS_RI_MASK (0x40U) -#define EMAC_DMA_CH1_STATUS_RI_SHIFT (6U) +#define EMAC_DMA_CHX_STAT_RI_MASK (0x40U) +#define EMAC_DMA_CHX_STAT_RI_SHIFT (6U) /*! RI - Receive Interrupt * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_RI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_RI_SHIFT)) & EMAC_DMA_CH1_STATUS_RI_MASK) +#define EMAC_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_RI_SHIFT)) & EMAC_DMA_CHX_STAT_RI_MASK) -#define EMAC_DMA_CH1_STATUS_RBU_MASK (0x80U) -#define EMAC_DMA_CH1_STATUS_RBU_SHIFT (7U) +#define EMAC_DMA_CHX_STAT_RBU_MASK (0x80U) +#define EMAC_DMA_CHX_STAT_RBU_SHIFT (7U) /*! RBU - Receive Buffer Unavailable * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_RBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_RBU_SHIFT)) & EMAC_DMA_CH1_STATUS_RBU_MASK) +#define EMAC_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_RBU_SHIFT)) & EMAC_DMA_CHX_STAT_RBU_MASK) -#define EMAC_DMA_CH1_STATUS_RPS_MASK (0x100U) -#define EMAC_DMA_CH1_STATUS_RPS_SHIFT (8U) +#define EMAC_DMA_CHX_STAT_RPS_MASK (0x100U) +#define EMAC_DMA_CHX_STAT_RPS_SHIFT (8U) /*! RPS - Receive Process Stopped * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_RPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_RPS_SHIFT)) & EMAC_DMA_CH1_STATUS_RPS_MASK) +#define EMAC_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_RPS_SHIFT)) & EMAC_DMA_CHX_STAT_RPS_MASK) -#define EMAC_DMA_CH1_STATUS_RWT_MASK (0x200U) -#define EMAC_DMA_CH1_STATUS_RWT_SHIFT (9U) +#define EMAC_DMA_CHX_STAT_RWT_MASK (0x200U) +#define EMAC_DMA_CHX_STAT_RWT_SHIFT (9U) /*! RWT - Receive Watchdog Timeout * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_RWT_SHIFT)) & EMAC_DMA_CH1_STATUS_RWT_MASK) +#define EMAC_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_RWT_SHIFT)) & EMAC_DMA_CHX_STAT_RWT_MASK) -#define EMAC_DMA_CH1_STATUS_ETI_MASK (0x400U) -#define EMAC_DMA_CH1_STATUS_ETI_SHIFT (10U) +#define EMAC_DMA_CHX_STAT_ETI_MASK (0x400U) +#define EMAC_DMA_CHX_STAT_ETI_SHIFT (10U) /*! ETI - Early Transmit Interrupt * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_ETI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_ETI_SHIFT)) & EMAC_DMA_CH1_STATUS_ETI_MASK) +#define EMAC_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_ETI_SHIFT)) & EMAC_DMA_CHX_STAT_ETI_MASK) -#define EMAC_DMA_CH1_STATUS_ERI_MASK (0x800U) -#define EMAC_DMA_CH1_STATUS_ERI_SHIFT (11U) +#define EMAC_DMA_CHX_STAT_ERI_MASK (0x800U) +#define EMAC_DMA_CHX_STAT_ERI_SHIFT (11U) /*! ERI - Early Receive Interrupt * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_ERI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_ERI_SHIFT)) & EMAC_DMA_CH1_STATUS_ERI_MASK) +#define EMAC_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_ERI_SHIFT)) & EMAC_DMA_CHX_STAT_ERI_MASK) -#define EMAC_DMA_CH1_STATUS_FBE_MASK (0x1000U) -#define EMAC_DMA_CH1_STATUS_FBE_SHIFT (12U) +#define EMAC_DMA_CHX_STAT_FBE_MASK (0x1000U) +#define EMAC_DMA_CHX_STAT_FBE_SHIFT (12U) /*! FBE - Fatal Bus Error * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_FBE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_FBE_SHIFT)) & EMAC_DMA_CH1_STATUS_FBE_MASK) +#define EMAC_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_FBE_SHIFT)) & EMAC_DMA_CHX_STAT_FBE_MASK) -#define EMAC_DMA_CH1_STATUS_CDE_MASK (0x2000U) -#define EMAC_DMA_CH1_STATUS_CDE_SHIFT (13U) +#define EMAC_DMA_CHX_STAT_CDE_MASK (0x2000U) +#define EMAC_DMA_CHX_STAT_CDE_SHIFT (13U) /*! CDE - Context Descriptor Error * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_CDE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_CDE_SHIFT)) & EMAC_DMA_CH1_STATUS_CDE_MASK) +#define EMAC_DMA_CHX_STAT_CDE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_CDE_SHIFT)) & EMAC_DMA_CHX_STAT_CDE_MASK) -#define EMAC_DMA_CH1_STATUS_AIS_MASK (0x4000U) -#define EMAC_DMA_CH1_STATUS_AIS_SHIFT (14U) +#define EMAC_DMA_CHX_STAT_AIS_MASK (0x4000U) +#define EMAC_DMA_CHX_STAT_AIS_SHIFT (14U) /*! AIS - Abnormal Interrupt Summary * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_AIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_AIS_SHIFT)) & EMAC_DMA_CH1_STATUS_AIS_MASK) +#define EMAC_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_AIS_SHIFT)) & EMAC_DMA_CHX_STAT_AIS_MASK) -#define EMAC_DMA_CH1_STATUS_NIS_MASK (0x8000U) -#define EMAC_DMA_CH1_STATUS_NIS_SHIFT (15U) +#define EMAC_DMA_CHX_STAT_NIS_MASK (0x8000U) +#define EMAC_DMA_CHX_STAT_NIS_SHIFT (15U) /*! NIS - Normal Interrupt Summary * 0b0..Not detected * 0b1..Detected */ -#define EMAC_DMA_CH1_STATUS_NIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_NIS_SHIFT)) & EMAC_DMA_CH1_STATUS_NIS_MASK) +#define EMAC_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_NIS_SHIFT)) & EMAC_DMA_CHX_STAT_NIS_MASK) -#define EMAC_DMA_CH1_STATUS_TEB_MASK (0x70000U) -#define EMAC_DMA_CH1_STATUS_TEB_SHIFT (16U) +#define EMAC_DMA_CHX_STAT_TEB_MASK (0x70000U) +#define EMAC_DMA_CHX_STAT_TEB_SHIFT (16U) /*! TEB - Tx DMA Error Bits */ -#define EMAC_DMA_CH1_STATUS_TEB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_TEB_SHIFT)) & EMAC_DMA_CH1_STATUS_TEB_MASK) +#define EMAC_DMA_CHX_STAT_TEB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_TEB_SHIFT)) & EMAC_DMA_CHX_STAT_TEB_MASK) -#define EMAC_DMA_CH1_STATUS_REB_MASK (0x380000U) -#define EMAC_DMA_CH1_STATUS_REB_SHIFT (19U) +#define EMAC_DMA_CHX_STAT_REB_MASK (0x380000U) +#define EMAC_DMA_CHX_STAT_REB_SHIFT (19U) /*! REB - Rx DMA Error Bits */ -#define EMAC_DMA_CH1_STATUS_REB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_REB_SHIFT)) & EMAC_DMA_CH1_STATUS_REB_MASK) +#define EMAC_DMA_CHX_STAT_REB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_STAT_REB_SHIFT)) & EMAC_DMA_CHX_STAT_REB_MASK) /*! @} */ -/*! @name DMA_CH1_MISS_FRAME_CNT - DMA Channel 1 Miss Frame Counter */ +/* The count of EMAC_DMA_CHX_STAT */ +#define EMAC_DMA_CHX_STAT_COUNT (2U) + +/*! @name DMA_CHX_MISS_FRAME_CNT - DMA Channel 0 Miss Frame Counter..DMA Channel 1 Miss Frame Counter */ /*! @{ */ -#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK (0x7FFU) -#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT (0U) +#define EMAC_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU) +#define EMAC_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U) /*! MFC - Dropped Packet Counters */ -#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT)) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK) +#define EMAC_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & EMAC_DMA_CHX_MISS_FRAME_CNT_MFC_MASK) -#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_MASK (0x8000U) -#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_SHIFT (15U) +#define EMAC_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U) +#define EMAC_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U) /*! MFCO - Overflow status of the MFC Counter * 0b0..Not occurred * 0b1..Occurred */ -#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_SHIFT)) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_MASK) +#define EMAC_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & EMAC_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK) /*! @} */ -/*! @name DMA_CH1_RXP_ACCEPT_CNT - DMA Channel 1 Rx Parser Accept Count */ +/* The count of EMAC_DMA_CHX_MISS_FRAME_CNT */ +#define EMAC_DMA_CHX_MISS_FRAME_CNT_COUNT (2U) + +/*! @name DMA_CHX_RXP_ACCEPT_CNT - DMA Channel 0 Rx Parser Accept Count..DMA Channel 1 Rx Parser Accept Count */ /*! @{ */ -#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU) -#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U) +#define EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU) +#define EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U) /*! RXPAC - Rx Parser Accept Counter */ -#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK) +#define EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK) -#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U) -#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U) +#define EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U) +#define EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U) /*! RXPACOF - Rx Parser Accept Counter Overflow Bit * 0b0..Not occurred * 0b1..Occurred */ -#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_MASK) +#define EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & EMAC_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK) /*! @} */ -/*! @name DMA_CH1_RX_ERI_CNT - DMA Channel 1 Rx ERI Count */ +/* The count of EMAC_DMA_CHX_RXP_ACCEPT_CNT */ +#define EMAC_DMA_CHX_RXP_ACCEPT_CNT_COUNT (2U) + +/*! @name DMA_CHX_RX_ERI_CNT - DMA Channel 0 Rx ERI Count..DMA Channel 1 Rx ERI Count */ /*! @{ */ -#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK (0xFFFU) -#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT (0U) +#define EMAC_DMA_CHX_RX_ERI_CNT_ECNT_MASK (0xFFFU) +#define EMAC_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT (0U) /*! ECNT - ERI Counter */ -#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT)) & EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK) +#define EMAC_DMA_CHX_RX_ERI_CNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT)) & EMAC_DMA_CHX_RX_ERI_CNT_ECNT_MASK) /*! @} */ +/* The count of EMAC_DMA_CHX_RX_ERI_CNT */ +#define EMAC_DMA_CHX_RX_ERI_CNT_COUNT (2U) + /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EMIOS.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EMIOS.h index af3bea1ac..775966857 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EMIOS.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_EMIOS.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for EMIOS @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_EMIOS.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for EMIOS * * CMSIS Peripheral Access Layer for EMIOS diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_ERM.h index 6fbb256d2..ddeef0e74 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_ERM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_ERM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for ERM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_ERM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for ERM * * CMSIS Peripheral Access Layer for ERM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FCCU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FCCU.h index dde123635..e52c86533 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FCCU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FCCU.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FCCU @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FCCU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FCCU * * CMSIS Peripheral Access Layer for FCCU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FIRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FIRC.h index 738cd319d..7c818ee3c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FIRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FIRC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FIRC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FIRC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FIRC * * CMSIS Peripheral Access Layer for FIRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FLASH.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FLASH.h index f080e9f52..3899e19c7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FLASH.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FLASH.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FLASH.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FLASH * * CMSIS Peripheral Access Layer for FLASH diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FLEXIO.h index 7a6b8dc5c..e52baa73f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FLEXIO.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FLEXIO.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FLEXIO * * CMSIS Peripheral Access Layer for FLEXIO diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FXOSC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FXOSC.h index 13a5cd854..94d74f7cb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FXOSC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_FXOSC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FXOSC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FXOSC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FXOSC * * CMSIS Peripheral Access Layer for FXOSC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_I2S.h index c066382f3..c517f8055 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_I2S.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_I2S.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for I2S * * CMSIS Peripheral Access Layer for I2S diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_INTM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_INTM.h index dca6ed49d..c6a28a654 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_INTM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_INTM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for INTM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_INTM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for INTM * * CMSIS Peripheral Access Layer for INTM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_JDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_JDC.h index 388b2f567..0ca45d65d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_JDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_JDC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for JDC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_JDC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for JDC * * CMSIS Peripheral Access Layer for JDC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LCU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LCU.h index c01fab651..e7dff4fdb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LCU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LCU.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LCU @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LCU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LCU * * CMSIS Peripheral Access Layer for LCU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPCMP.h index 9b3668616..454ebd983 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPCMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPCMP.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPCMP @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPCMP.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPCMP * * CMSIS Peripheral Access Layer for LPCMP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPI2C.h index 9a2b709c4..00f31b80f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPI2C.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPI2C.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPI2C * * CMSIS Peripheral Access Layer for LPI2C diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPSPI.h index f6a9c5a61..0a30c3869 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPSPI.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPSPI.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPSPI * * CMSIS Peripheral Access Layer for LPSPI diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPUART.h index bd7f5fb9d..b5e1d0b87 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_LPUART.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPUART.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPUART * * CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MCM.h index 328cc45e9..487f395f6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MCM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MCM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCM * * CMSIS Peripheral Access Layer for MCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_CGM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_CGM.h index 00f726aa6..9dde67bf7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_CGM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_CGM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MC_CGM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MC_CGM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MC_CGM * * CMSIS Peripheral Access Layer for MC_CGM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_ME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_ME.h index 12bc0499c..87a416f88 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_ME.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_ME.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MC_ME @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MC_ME.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MC_ME * * CMSIS Peripheral Access Layer for MC_ME diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_RGM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_RGM.h index be5ffa92a..fc80f13f3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_RGM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MC_RGM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MC_RGM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MC_RGM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MC_RGM * * CMSIS Peripheral Access Layer for MC_RGM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MDM_AP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MDM_AP.h index 4ec019d35..99871d310 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MDM_AP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MDM_AP.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MDM_AP @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MDM_AP.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MDM_AP * * CMSIS Peripheral Access Layer for MDM_AP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MSCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MSCM.h index aec12775a..21a574945 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MSCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MSCM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MSCM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MSCM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MSCM * * CMSIS Peripheral Access Layer for MSCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MU.h index 5060bba19..b73a0bbfc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_MU.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MU * * CMSIS Peripheral Access Layer for MU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PFLASH.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PFLASH.h index 6400f513a..ded3d6d50 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PFLASH.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PFLASH.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PFLASH @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PFLASH.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PFLASH * * CMSIS Peripheral Access Layer for PFLASH diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PIT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PIT.h index c1059847c..470c86236 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PIT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PIT.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PIT @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PIT.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PIT * * CMSIS Peripheral Access Layer for PIT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PLL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PLL.h index 087059834..1dd27d2db 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PLL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PLL.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PLL @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PLL.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PLL * * CMSIS Peripheral Access Layer for PLL diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PMC.h index 8d5975d5c..56a1554c0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PMC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PMC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PMC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PMC * * CMSIS Peripheral Access Layer for PMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PRAMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PRAMC.h index 20da09411..1a45498ea 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PRAMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_PRAMC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PRAMC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PRAMC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PRAMC * * CMSIS Peripheral Access Layer for PRAMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_QUADSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_QUADSPI.h index b42827fd6..7c54d24b7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_QUADSPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_QUADSPI.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250515 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for QuadSPI @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_QuadSPI.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for QuadSPI * * CMSIS Peripheral Access Layer for QuadSPI diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_QUADSPI_ARDB.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_QUADSPI_ARDB.h index b1f59bd3f..6fd30b11f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_QUADSPI_ARDB.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_QUADSPI_ARDB.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for QuadSPI_ARDB @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_QuadSPI_ARDB.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for QuadSPI_ARDB * * CMSIS Peripheral Access Layer for QuadSPI_ARDB diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_RTC.h index 324010d4d..ad7015bd6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_RTC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_RTC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for RTC * * CMSIS Peripheral Access Layer for RTC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SDA_AP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SDA_AP.h index f8016ea57..e21e5ad40 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SDA_AP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SDA_AP.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SDA_AP @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SDA_AP.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SDA_AP * * CMSIS Peripheral Access Layer for SDA_AP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SELFTEST.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SELFTEST.h index 69dce06e5..d1756621e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SELFTEST.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SELFTEST.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SELFTEST @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SELFTEST.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SELFTEST * * CMSIS Peripheral Access Layer for SELFTEST diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SEMA42.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SEMA42.h index d34f00fb6..aefeed4fd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SEMA42.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SEMA42.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMA42 @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SEMA42.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SEMA42 * * CMSIS Peripheral Access Layer for SEMA42 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SIRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SIRC.h index f7e4003ea..4d424d992 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SIRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SIRC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SIRC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SIRC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SIRC * * CMSIS Peripheral Access Layer for SIRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SIUL2.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SIUL2.h index 36d815e89..7f85a32f7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SIUL2.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SIUL2.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SIUL2 @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SIUL2.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SIUL2 * * CMSIS Peripheral Access Layer for SIUL2 @@ -1869,7 +1871,7 @@ typedef struct { #define SIUL2_MIDR4_SEC_FET_MASK (0x60U) #define SIUL2_MIDR4_SEC_FET_SHIFT (5U) /*! SEC_FET - Security Feature - * 0b01..HSE-B + * 0b01..ELE_HSEB */ #define SIUL2_MIDR4_SEC_FET(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_SEC_FET_SHIFT)) & SIUL2_MIDR4_SEC_FET_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_STCU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_STCU.h index 2cde83948..31d93f069 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_STCU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_STCU.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for STCU @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_STCU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for STCU * * CMSIS Peripheral Access Layer for STCU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_STM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_STM.h index b98f1d750..4fc0afdbd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_STM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_STM.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for STM @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_STM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for STM * * CMSIS Peripheral Access Layer for STM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SWT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SWT.h index b773eb0de..235679a70 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SWT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SWT.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SWT @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SWT.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SWT * * CMSIS Peripheral Access Layer for SWT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SXOSC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SXOSC.h index 3b44fea0c..e677c2f03 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SXOSC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_SXOSC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SXOSC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SXOSC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SXOSC * * CMSIS Peripheral Access Layer for SXOSC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TEMPSENSE.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TEMPSENSE.h index d18166974..52cef7326 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TEMPSENSE.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TEMPSENSE.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for TEMPSENSE @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_TEMPSENSE.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for TEMPSENSE * * CMSIS Peripheral Access Layer for TEMPSENSE diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TRGMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TRGMUX.h index 6b41aa30b..a9334e27a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TRGMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TRGMUX.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRGMUX @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_TRGMUX.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for TRGMUX * * CMSIS Peripheral Access Layer for TRGMUX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TSPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TSPC.h index 8a0c32064..60914bb0e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TSPC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_TSPC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for TSPC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_TSPC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for TSPC * * CMSIS Peripheral Access Layer for TSPC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_VIRT_WRAPPER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_VIRT_WRAPPER.h index 517341a65..29151c268 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_VIRT_WRAPPER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_VIRT_WRAPPER.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for VIRT_WRAPPER @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_VIRT_WRAPPER.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for VIRT_WRAPPER * * CMSIS Peripheral Access Layer for VIRT_WRAPPER diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_WKPU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_WKPU.h index 4533ca134..5852439bc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_WKPU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_WKPU.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for WKPU @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_WKPU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for WKPU * * CMSIS Peripheral Access Layer for WKPU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_XBIC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_XBIC.h index c41525a3c..403e1f2dd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_XBIC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_XBIC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBIC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_XBIC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for XBIC * * CMSIS Peripheral Access Layer for XBIC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_XRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_XRDC.h index 062ddcd55..53d80ea06 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_XRDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph1/PERI_XRDC.h @@ -1,8 +1,8 @@ /* ** ################################################################### ** Processor: MCXE31BMPB -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for XRDC @@ -17,14 +17,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_XRDC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for XRDC * * CMSIS Peripheral Access Layer for XRDC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_ADC.h index 4c17eb1ae..4e04a9fb5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_ADC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_ADC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for ADC * * CMSIS Peripheral Access Layer for ADC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_BCTU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_BCTU.h index ed07d2ec8..b7bec19ad 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_BCTU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_BCTU.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for BCTU @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_BCTU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for BCTU * * CMSIS Peripheral Access Layer for BCTU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CAN.h index c3f34c58c..64daec486 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CAN.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CAN.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CAN * * CMSIS Peripheral Access Layer for CAN diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CMU_FC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CMU_FC.h index 2a205be13..8c49d6b04 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CMU_FC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CMU_FC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMU_FC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CMU_FC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CMU_FC * * CMSIS Peripheral Access Layer for CMU_FC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CMU_FM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CMU_FM.h index b4b54f759..383ab79c4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CMU_FM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CMU_FM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMU_FM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CMU_FM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CMU_FM * * CMSIS Peripheral Access Layer for CMU_FM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CONFIGURATION.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CONFIGURATION.h index ac536859b..71f712517 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CONFIGURATION.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CONFIGURATION.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CONFIGURATION @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CONFIGURATION.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CONFIGURATION * * CMSIS Peripheral Access Layer for CONFIGURATION diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CRC.h index 5bb9e9287..621975f96 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_CRC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CRC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CRC * * CMSIS Peripheral Access Layer for CRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DCM.h index 6dcb5ea00..900edfffa 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DCM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DCM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DCM * * CMSIS Peripheral Access Layer for DCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DCM_GPR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DCM_GPR.h index a03a592a5..19ec0ebda 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DCM_GPR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DCM_GPR.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCM_GPR @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DCM_GPR.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DCM_GPR * * CMSIS Peripheral Access Layer for DCM_GPR diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DMA.h index d40578ec0..2182024cd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DMA.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DMA.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DMA * * CMSIS Peripheral Access Layer for DMA diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DMAMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DMAMUX.h index 7c65d599a..df328ff97 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DMAMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_DMAMUX.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMAMUX @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DMAMUX.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DMAMUX * * CMSIS Peripheral Access Layer for DMAMUX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_EIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_EIM.h index 521809764..0dfb74572 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_EIM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_EIM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for EIM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_EIM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for EIM * * CMSIS Peripheral Access Layer for EIM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_EMIOS.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_EMIOS.h index 256be0487..bb57a3606 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_EMIOS.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_EMIOS.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for EMIOS @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_EMIOS.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for EMIOS * * CMSIS Peripheral Access Layer for EMIOS diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_ERM.h index 1fba6528b..69bd7b181 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_ERM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_ERM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for ERM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_ERM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for ERM * * CMSIS Peripheral Access Layer for ERM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FCCU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FCCU.h index 0f21927be..6be369e7a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FCCU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FCCU.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FCCU @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FCCU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FCCU * * CMSIS Peripheral Access Layer for FCCU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FIRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FIRC.h index 1d6975362..724b73545 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FIRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FIRC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FIRC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FIRC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FIRC * * CMSIS Peripheral Access Layer for FIRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FLASH.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FLASH.h index 8af224592..4466dbdb7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FLASH.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FLASH.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FLASH.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FLASH * * CMSIS Peripheral Access Layer for FLASH diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FLEXIO.h index c33fac7c7..f60c027b6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FLEXIO.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FLEXIO.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FLEXIO * * CMSIS Peripheral Access Layer for FLEXIO diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FXOSC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FXOSC.h index bc9f33a03..b9ca06185 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FXOSC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_FXOSC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FXOSC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FXOSC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FXOSC * * CMSIS Peripheral Access Layer for FXOSC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_INTM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_INTM.h index 5bc084f40..01a0bc947 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_INTM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_INTM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for INTM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_INTM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for INTM * * CMSIS Peripheral Access Layer for INTM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_JDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_JDC.h index 9cb588e8f..f61f2ff92 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_JDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_JDC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for JDC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_JDC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for JDC * * CMSIS Peripheral Access Layer for JDC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LCU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LCU.h index ab41fa2a2..da7246b57 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LCU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LCU.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LCU @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LCU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LCU * * CMSIS Peripheral Access Layer for LCU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPCMP.h index 263bd64be..18311d9d0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPCMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPCMP.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPCMP @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPCMP.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPCMP * * CMSIS Peripheral Access Layer for LPCMP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPI2C.h index 6a8272273..fe9bd4511 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPI2C.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPI2C.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPI2C * * CMSIS Peripheral Access Layer for LPI2C diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPSPI.h index e40197be2..a25a68361 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPSPI.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPSPI.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPSPI * * CMSIS Peripheral Access Layer for LPSPI diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPUART.h index 9a28a78bf..a4fd10685 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_LPUART.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPUART.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPUART * * CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MCM.h index 7af6e6854..8208d498b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MCM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MCM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCM * * CMSIS Peripheral Access Layer for MCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_CGM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_CGM.h index b19145acd..0627864d9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_CGM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_CGM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MC_CGM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MC_CGM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MC_CGM * * CMSIS Peripheral Access Layer for MC_CGM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_ME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_ME.h index 29a830651..172706c00 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_ME.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_ME.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MC_ME @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MC_ME.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MC_ME * * CMSIS Peripheral Access Layer for MC_ME diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_RGM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_RGM.h index 7aec2e190..347e05db0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_RGM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MC_RGM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MC_RGM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MC_RGM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MC_RGM * * CMSIS Peripheral Access Layer for MC_RGM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MDM_AP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MDM_AP.h index c33e42844..0b7ea9ed8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MDM_AP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MDM_AP.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MDM_AP @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MDM_AP.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MDM_AP * * CMSIS Peripheral Access Layer for MDM_AP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MSCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MSCM.h index bc0402347..0e3abadff 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MSCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MSCM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MSCM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MSCM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MSCM * * CMSIS Peripheral Access Layer for MSCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MU.h index 59224868c..f831ed2b6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_MU.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MU * * CMSIS Peripheral Access Layer for MU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PFLASH.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PFLASH.h index 16496b4aa..cbca843c7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PFLASH.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PFLASH.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PFLASH @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PFLASH.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PFLASH * * CMSIS Peripheral Access Layer for PFLASH diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PIT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PIT.h index 849f3c186..88d432aa0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PIT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PIT.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PIT @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PIT.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PIT * * CMSIS Peripheral Access Layer for PIT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PLL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PLL.h index 42d914bc2..92ac1212e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PLL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PLL.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PLL @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PLL.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PLL * * CMSIS Peripheral Access Layer for PLL diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PMC.h index e40c0b289..2686f7b10 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PMC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PMC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PMC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PMC * * CMSIS Peripheral Access Layer for PMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PRAMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PRAMC.h index 0c2a3d6a8..6de0a2af1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PRAMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_PRAMC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PRAMC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PRAMC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PRAMC * * CMSIS Peripheral Access Layer for PRAMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_RTC.h index 09e666bba..6e464d9f7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_RTC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_RTC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for RTC * * CMSIS Peripheral Access Layer for RTC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SDA_AP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SDA_AP.h index 0e3c1af3d..a320de07f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SDA_AP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SDA_AP.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SDA_AP @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SDA_AP.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SDA_AP * * CMSIS Peripheral Access Layer for SDA_AP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SIRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SIRC.h index 3f43d0e44..5d4d9f006 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SIRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SIRC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SIRC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SIRC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SIRC * * CMSIS Peripheral Access Layer for SIRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SIUL2.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SIUL2.h index a73559534..f1658d42e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SIUL2.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SIUL2.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SIUL2 @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SIUL2.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SIUL2 * * CMSIS Peripheral Access Layer for SIUL2 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_STCU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_STCU.h index 026f8f475..f39df8c8d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_STCU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_STCU.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for STCU @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_STCU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for STCU * * CMSIS Peripheral Access Layer for STCU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_STM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_STM.h index 2f5663415..18e1bde5e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_STM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_STM.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for STM @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_STM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for STM * * CMSIS Peripheral Access Layer for STM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SWT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SWT.h index baaa3b51d..c5e0ced13 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SWT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SWT.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SWT @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SWT.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SWT * * CMSIS Peripheral Access Layer for SWT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SXOSC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SXOSC.h index 6c54418a1..2fa89d6af 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SXOSC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_SXOSC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SXOSC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SXOSC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SXOSC * * CMSIS Peripheral Access Layer for SXOSC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TEMPSENSE.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TEMPSENSE.h index fbcab8502..d18bfa76c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TEMPSENSE.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TEMPSENSE.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for TEMPSENSE @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_TEMPSENSE.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for TEMPSENSE * * CMSIS Peripheral Access Layer for TEMPSENSE diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TRGMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TRGMUX.h index 0ea8662df..33ffc27a0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TRGMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TRGMUX.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRGMUX @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_TRGMUX.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for TRGMUX * * CMSIS Peripheral Access Layer for TRGMUX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TSPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TSPC.h index 77eeaae53..459b51bc7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TSPC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_TSPC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for TSPC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_TSPC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for TSPC * * CMSIS Peripheral Access Layer for TSPC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_VIRT_WRAPPER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_VIRT_WRAPPER.h index 3dfbbabb2..c72f4f6a3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_VIRT_WRAPPER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_VIRT_WRAPPER.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for VIRT_WRAPPER @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_VIRT_WRAPPER.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for VIRT_WRAPPER * * CMSIS Peripheral Access Layer for VIRT_WRAPPER diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_WKPU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_WKPU.h index 3195aa212..f614d34f9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_WKPU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_WKPU.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for WKPU @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_WKPU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for WKPU * * CMSIS Peripheral Access Layer for WKPU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_XBIC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_XBIC.h index 34c291495..ff47aa535 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_XBIC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_XBIC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBIC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_XBIC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for XBIC * * CMSIS Peripheral Access Layer for XBIC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_XRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_XRDC.h index 78be1fa65..abdf435ad 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_XRDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph4/PERI_XRDC.h @@ -3,8 +3,8 @@ ** Processors: MCXE317MPA ** MCXE317MPB ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for XRDC @@ -19,14 +19,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_XRDC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for XRDC * * CMSIS Peripheral Access Layer for XRDC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_ADC.h index 2158962b0..1fb31ae02 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_ADC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_ADC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for ADC * * CMSIS Peripheral Access Layer for ADC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_BCTU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_BCTU.h index 110b5c016..1ca61a967 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_BCTU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_BCTU.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for BCTU @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_BCTU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for BCTU * * CMSIS Peripheral Access Layer for BCTU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CAN.h index 6b012afa1..ea91d8bd5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CAN.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CAN.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CAN * * CMSIS Peripheral Access Layer for CAN diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CMU_FC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CMU_FC.h index bf5804dd0..822ff1a0b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CMU_FC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CMU_FC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMU_FC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CMU_FC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CMU_FC * * CMSIS Peripheral Access Layer for CMU_FC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CMU_FM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CMU_FM.h index b5c9e339f..10118919c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CMU_FM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CMU_FM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMU_FM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CMU_FM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CMU_FM * * CMSIS Peripheral Access Layer for CMU_FM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CONFIGURATION.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CONFIGURATION.h index 8ef63276e..e65e5ccb6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CONFIGURATION.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CONFIGURATION.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CONFIGURATION @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CONFIGURATION.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CONFIGURATION * * CMSIS Peripheral Access Layer for CONFIGURATION diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CRC.h index 066521bd9..3b32458c3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_CRC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_CRC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for CRC * * CMSIS Peripheral Access Layer for CRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DCM.h index c328121e9..6e6a70fa9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DCM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DCM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DCM * * CMSIS Peripheral Access Layer for DCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DCM_GPR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DCM_GPR.h index c1ce71172..f9e42b52f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DCM_GPR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DCM_GPR.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCM_GPR @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DCM_GPR.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DCM_GPR * * CMSIS Peripheral Access Layer for DCM_GPR diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DMA.h index 8eb008f20..ca579e5c7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DMA.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DMA.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DMA * * CMSIS Peripheral Access Layer for DMA diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DMAMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DMAMUX.h index e474eee99..29caa57db 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DMAMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_DMAMUX.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMAMUX @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_DMAMUX.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for DMAMUX * * CMSIS Peripheral Access Layer for DMAMUX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_EIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_EIM.h index fee95d226..5350ee3ee 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_EIM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_EIM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for EIM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_EIM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for EIM * * CMSIS Peripheral Access Layer for EIM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_EMIOS.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_EMIOS.h index b0ff4c005..bfc2c0a4a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_EMIOS.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_EMIOS.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for EMIOS @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_EMIOS.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for EMIOS * * CMSIS Peripheral Access Layer for EMIOS diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_ERM.h index b765fd76d..1fae8565b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_ERM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_ERM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for ERM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_ERM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for ERM * * CMSIS Peripheral Access Layer for ERM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FCCU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FCCU.h index 19edd2649..72795f11f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FCCU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FCCU.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FCCU @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FCCU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FCCU * * CMSIS Peripheral Access Layer for FCCU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FIRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FIRC.h index d198020cb..d9c4e7474 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FIRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FIRC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FIRC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FIRC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FIRC * * CMSIS Peripheral Access Layer for FIRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FLASH.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FLASH.h index 886717645..bc33a9ed8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FLASH.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FLASH.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FLASH.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FLASH * * CMSIS Peripheral Access Layer for FLASH diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FLEXIO.h index e82ea9345..0e91fd650 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FLEXIO.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FLEXIO.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FLEXIO * * CMSIS Peripheral Access Layer for FLEXIO diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FXOSC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FXOSC.h index 097d9b56e..d8060fb0b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FXOSC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_FXOSC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for FXOSC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_FXOSC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for FXOSC * * CMSIS Peripheral Access Layer for FXOSC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_INTM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_INTM.h index 62de0ad88..1a1bb8ac7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_INTM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_INTM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for INTM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_INTM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for INTM * * CMSIS Peripheral Access Layer for INTM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_JDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_JDC.h index c8b2ad5d4..9e7e06870 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_JDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_JDC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for JDC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_JDC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for JDC * * CMSIS Peripheral Access Layer for JDC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LCU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LCU.h index cb590f1b8..1747389e5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LCU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LCU.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LCU @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LCU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LCU * * CMSIS Peripheral Access Layer for LCU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPCMP.h index f5a296983..aeac74409 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPCMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPCMP.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPCMP @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPCMP.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPCMP * * CMSIS Peripheral Access Layer for LPCMP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPI2C.h index 57519aabd..6996a18a7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPI2C.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPI2C.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPI2C * * CMSIS Peripheral Access Layer for LPI2C diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPSPI.h index 6c15be8ba..0aff53ac6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPSPI.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPSPI.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPSPI * * CMSIS Peripheral Access Layer for LPSPI diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPUART.h index 371e727ec..70abb9622 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_LPUART.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_LPUART.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for LPUART * * CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MCM.h index 97b061d07..b03690c51 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MCM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MCM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MCM * * CMSIS Peripheral Access Layer for MCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_CGM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_CGM.h index c746ab519..8054df922 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_CGM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_CGM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MC_CGM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MC_CGM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MC_CGM * * CMSIS Peripheral Access Layer for MC_CGM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_ME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_ME.h index 07489271e..f72378754 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_ME.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_ME.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MC_ME @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MC_ME.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MC_ME * * CMSIS Peripheral Access Layer for MC_ME diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_RGM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_RGM.h index a357fdc57..c9996281e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_RGM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MC_RGM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MC_RGM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MC_RGM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MC_RGM * * CMSIS Peripheral Access Layer for MC_RGM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MDM_AP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MDM_AP.h index be9db2b40..0152ef396 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MDM_AP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MDM_AP.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MDM_AP @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MDM_AP.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MDM_AP * * CMSIS Peripheral Access Layer for MDM_AP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MSCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MSCM.h index fb345987a..4f1f32fe5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MSCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MSCM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250513 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MSCM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MSCM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MSCM * * CMSIS Peripheral Access Layer for MSCM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MU.h index b327af590..67fbbde68 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_MU.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_MU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for MU * * CMSIS Peripheral Access Layer for MU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PFLASH.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PFLASH.h index 955a3370a..9e7d62b4b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PFLASH.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PFLASH.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PFLASH @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PFLASH.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PFLASH * * CMSIS Peripheral Access Layer for PFLASH diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PIT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PIT.h index e70d1a65f..0597922f5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PIT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PIT.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PIT @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PIT.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PIT * * CMSIS Peripheral Access Layer for PIT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PLL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PLL.h index 69af3177f..612598e1f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PLL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PLL.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PLL @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PLL.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PLL * * CMSIS Peripheral Access Layer for PLL diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PMC.h index c013d57f2..5f4780ae1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PMC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PMC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PMC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PMC * * CMSIS Peripheral Access Layer for PMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PRAMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PRAMC.h index a2cabbd1d..082d15444 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PRAMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_PRAMC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for PRAMC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_PRAMC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for PRAMC * * CMSIS Peripheral Access Layer for PRAMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_RTC.h index 3f1f35a1d..6d0e7e2d4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_RTC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_RTC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for RTC * * CMSIS Peripheral Access Layer for RTC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SDA_AP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SDA_AP.h index 07d0f1068..581224fca 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SDA_AP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SDA_AP.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SDA_AP @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SDA_AP.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SDA_AP * * CMSIS Peripheral Access Layer for SDA_AP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SIRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SIRC.h index 8e5fc9568..f3225b119 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SIRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SIRC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SIRC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SIRC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SIRC * * CMSIS Peripheral Access Layer for SIRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SIUL2.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SIUL2.h index c17283955..7ed4ec9b6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SIUL2.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SIUL2.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SIUL2 @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SIUL2.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SIUL2 * * CMSIS Peripheral Access Layer for SIUL2 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_STCU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_STCU.h index d429d1576..0ef701021 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_STCU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_STCU.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for STCU @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_STCU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for STCU * * CMSIS Peripheral Access Layer for STCU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_STM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_STM.h index 2f2bb06fe..9be5dcb73 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_STM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_STM.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for STM @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_STM.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for STM * * CMSIS Peripheral Access Layer for STM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SWT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SWT.h index 5a523ad57..a3570cc9d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SWT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_SWT.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for SWT @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_SWT.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for SWT * * CMSIS Peripheral Access Layer for SWT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TEMPSENSE.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TEMPSENSE.h index ccf3574fd..163c4e432 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TEMPSENSE.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TEMPSENSE.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for TEMPSENSE @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_TEMPSENSE.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for TEMPSENSE * * CMSIS Peripheral Access Layer for TEMPSENSE diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TRGMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TRGMUX.h index e0a5b0ef7..6d245ae80 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TRGMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TRGMUX.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRGMUX @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_TRGMUX.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for TRGMUX * * CMSIS Peripheral Access Layer for TRGMUX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TSPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TSPC.h index 3de6938b1..2e1932ffe 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TSPC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_TSPC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for TSPC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_TSPC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for TSPC * * CMSIS Peripheral Access Layer for TSPC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_VIRT_WRAPPER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_VIRT_WRAPPER.h index f2f25f78d..e5ba7791a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_VIRT_WRAPPER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_VIRT_WRAPPER.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for VIRT_WRAPPER @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_VIRT_WRAPPER.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for VIRT_WRAPPER * * CMSIS Peripheral Access Layer for VIRT_WRAPPER diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_WKPU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_WKPU.h index 00ff415ad..c813e2247 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_WKPU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_WKPU.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for WKPU @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_WKPU.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for WKPU * * CMSIS Peripheral Access Layer for WKPU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_XBIC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_XBIC.h index 3ae7a7ee1..6f365767b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_XBIC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_XBIC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBIC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_XBIC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for XBIC * * CMSIS Peripheral Access Layer for XBIC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_XRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_XRDC.h index 1ff39ea7b..fba21dc5c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_XRDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXE/periph5/PERI_XRDC.h @@ -5,8 +5,8 @@ ** MCXE316MLF ** MCXE316MPA ** -** Version: rev. 0.1, 2024-11-19 -** Build: b250512 +** Version: rev. 1.0, 2025-07-18 +** Build: b250718 ** ** Abstract: ** CMSIS Peripheral Access Layer for XRDC @@ -21,14 +21,16 @@ ** Revisions: ** - rev. 0.1 (2024-11-19) ** Initial version. +** - rev. 1.0 (2025-07-18) +** Rev2 RM. ** ** ################################################################### */ /*! * @file PERI_XRDC.h - * @version 0.1 - * @date 2024-11-19 + * @version 1.0 + * @date 2025-07-18 * @brief CMSIS Peripheral Access Layer for XRDC * * CMSIS Peripheral Access Layer for XRDC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/CMakeLists.txt new file mode 100644 index 000000000..de4de5e6a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright 2024-2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) + +#### core related +include(${CMAKE_CURRENT_LIST_DIR}/${core_id}/setting.cmake) + +#### device specific drivers +mcux_add_cmakelists(${CMAKE_CURRENT_LIST_DIR}/../MCXL255/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus.h index 21e757c61..6ba47a160 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL253_cm0plus @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL253_cm0plus.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL253_cm0plus * * CMSIS Peripheral Access Layer for MCXL253_cm0plus diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus_COMMON.h index 95d4efeeb..cfb218aae 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus_COMMON.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250812 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL253_cm0plus @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL253_cm0plus_COMMON.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL253_cm0plus * * CMSIS Peripheral Access Layer for MCXL253_cm0plus @@ -66,10 +66,10 @@ typedef enum IRQn { /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0P SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0P SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0P Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0P System Tick Interrupt */ /* Device specific interrupts */ LPI2C0_AON_IRQn = 1, /**< Low-Power Inter Integrated Circuit interrupt */ @@ -91,12 +91,12 @@ typedef enum IRQn { PMU_IRQn = 20, /**< PMU IRQ */ KPP_IRQn = 21, /**< Keypad Interrupt */ LPADC_AON_IRQn = 22, /**< Analog-to-Digital Converter interrupt */ - SGLCD_AON_IRQn = 23, /**< SLCD frame start interrupt */ + SLCD_FRAME_AON_IRQn = 23, /**< SLCD frame start interrupt */ TMR0_AON_IRQn = 24, /**< ORed QTMR Interrupts */ TMR1_AON_IRQn = 25, /**< ORed QTMR Interrupts */ LCSENSE_IRQn = 27, /**< LCSense Fault/Tamper Interrupt */ LPTMR_AON_IRQn = 28, /**< Low Power Timer 0 interrupt */ - CMP0_AON_IRQn = 30, /**< Comparator interrupt */ + ACMP0_AON_IRQn = 30, /**< Comparator interrupt */ ADVC_IRQn = 31 /**< ADVC_2.0 Controller Interrupt */ } IRQn_Type; @@ -314,32 +314,34 @@ typedef enum IRQn { /* LPCMP - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xB0086000u) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE_NS (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0_NS ((LPCMP_Type *)AON__CMP0_BASE_NS) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xB0086000u) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE_NS (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0_NS ((LPCMP_Type *)AON__ACMP0_BASE_NS) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE } + #define LPCMP_BASE_ADDRS { AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0 } + #define LPCMP_BASE_PTRS { AON__ACMP0 } /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS_NS { AON__CMP0_BASE_NS } + #define LPCMP_BASE_ADDRS_NS { AON__ACMP0_BASE_NS } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS_NS { AON__CMP0_NS } + #define LPCMP_BASE_PTRS_NS { AON__ACMP0_NS } #else - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE } + #define LPCMP_BASE_ADDRS { AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0 } + #define LPCMP_BASE_PTRS { AON__ACMP0 } #endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { ACMP0_AON_IRQn } /* LPI2C - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) @@ -576,6 +578,9 @@ typedef enum IRQn { /** Array initializer of SGLCD_CONTROL peripheral base pointers */ #define SGLCD_CONTROL_BASE_PTRS { AON__SGLCD0_AON } #endif +/** Interrupt vectors for the SGLCD */ +#define SGLCD_CONTROL_IRQS { SLCD_FRAME_AON_IRQn } + /* SMM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) @@ -730,3 +735,4 @@ typedef enum IRQn { #endif /* MCXL253_CM0PLUS_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus_features.h index 5c874c98f..83dbae99f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm0plus_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Version: rev. 1.0, 2025-06-13 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -31,8 +31,6 @@ #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) /* @brief KPP availability on the SoC. */ #define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (1) /* @brief LPADC availability on the SoC. */ #define FSL_FEATURE_SOC_LPADC_COUNT (1) /* @brief LPCMP availability on the SoC. */ @@ -45,8 +43,6 @@ #define FSL_FEATURE_SOC_LPUART_COUNT (1) /* @brief MU availability on the SoC. */ #define FSL_FEATURE_SOC_MU_COUNT (1) -/* @brief PMU availability on the SoC. */ -#define FSL_FEATURE_SOC_PMU_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (1) /* @brief RTC availability on the SoC. */ @@ -68,10 +64,30 @@ #define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) /* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ #define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (0) +/* @brief Has RRCR0 RR_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_CLK_SEL (1) +/* @brief Has RRCR0 RR_TRG_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_TRG_SEL (1) +/* @brief Has RRCR0 RR_SAMPLE_CNT bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_CNT (1) +/* @brief Has RRCR0 RR_SAMPLE_THRESHOLD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_THRESHOLD (1) +/* @brief Has CCR2 INPSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INPSEL (0) +/* @brief Has CCR2 INMSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INMSEL (0) +/* @brief Has CCR2 CMP_NPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_CMP_NPMD (1) +/* @brief Has DCR DAC_HPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_DCR_DAC_HPMD (1) +/* @brief Has CCR0 LINKEN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_LINKEN (0) +/* @brief Has RRCR2 register. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR2 (1) /* @brief Has CCR0 CMP_STOP_EN bitfield. */ #define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) -/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ -#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) /* GPIO module features */ @@ -92,6 +108,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (16) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPTMR module features */ @@ -102,11 +120,11 @@ /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) /* @brief Do not has prescaler clock source 0. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) /* @brief Do not has prescaler clock source 1. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) /* @brief Do not has prescaler clock source 2. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) /* @brief Do not has prescaler clock source 3. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) @@ -142,8 +160,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -176,12 +192,25 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (0) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* ADVC module features */ + +/* @brief ADVC calibration data address. */ +#define FSL_FEATURE_ADVC_CFG_TABLE_ADDR (0x01100000UL) /* PORT module features */ @@ -213,6 +242,8 @@ #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ #define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Alt function 0 means GPIO (not analog). */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Defines width of PCR[MUX] field. */ @@ -232,10 +263,24 @@ /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) -/* LCD module features */ +/* SLCD module features */ -/* @brief LCD registers are split into control and fault detect parts. */ -#define FSL_FEATURE_SGLCD_HAS_FAULT_DETECT (1) +/* @brief (S)LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (1) +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) /* SYSCON_AON module features */ @@ -244,6 +289,11 @@ /* @brief Starter register discontinuous. */ #define FSL_FEATURE_SYSCON_AON_STARTER_DISCONTINUOUS (1) +/* TMR module features */ + +/* @brief Has 32-bit width register. */ +#define FSL_FEATURE_TMR_HAS_32BIT_REGISTER (1) + /* MU module features */ /* @brief MU side for current core */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33.h index 5140128f7..6ec01f235 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL253_cm33 @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL253_cm33.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL253_cm33 * * CMSIS Peripheral Access Layer for MCXL253_cm33 @@ -70,7 +70,6 @@ #include "PERI_LPSPI.h" #include "PERI_LPTMR.h" #include "PERI_LPUART.h" -#include "PERI_MBC.h" #include "PERI_MRCC.h" #include "PERI_MU.h" #include "PERI_OSTIMER.h" @@ -86,6 +85,7 @@ #include "PERI_SYSCON.h" #include "PERI_SYSCON_AON.h" #include "PERI_TMR.h" +#include "PERI_TRDC.h" #include "PERI_TRNG.h" #include "PERI_UDF.h" #include "PERI_UTICK.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33_COMMON.h index 7bd71a44c..5755fdc0f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33_COMMON.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250812 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL253_cm33 @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL253_cm33_COMMON.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL253_cm33 * * CMSIS Peripheral Access Layer for MCXL253_cm33 @@ -104,7 +104,7 @@ typedef enum IRQn { UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ ADC0_IRQn = 62, /**< Analog-to-Digital Converter interrupt */ - CMP0_IRQn = 64, /**< Comparator interrupt */ + ACMP0_IRQn = 64, /**< Comparator interrupt */ GPIO10_IRQn = 71, /**< General Purpose Input/Output 1 interrupt 0 */ GPIO11_IRQn = 72, /**< General Purpose Input/Output 1 interrupt 1 */ GPIO20_IRQn = 73, /**< General Purpose Input/Output 2 interrupt 0 */ @@ -140,10 +140,10 @@ typedef enum IRQn { TMR1_AON_IRQn = 152, /**< ORed QTMR Interrupts */ LCSENSE_IRQn = 154, /**< LCSense Fault/Tamper Interrupt */ LPTMR_AON_IRQn = 155, /**< Low Power Timer 0 interrupt */ - CMP0_AON_IRQn = 157, /**< Comparator interrupt */ + ACMP0_AON_IRQn = 157, /**< Comparator interrupt */ ADVC_IRQn = 158, /**< ADVC_2.0 Controller Interrupt */ - SGLCD_FRAME_AON_IRQn = 160, /**< Frame Update Interrupt */ - SGLCD_FFAULT_AON_IRQn = 161 /**< Fault Detect Interrupt */ + SLCD_FRAME_AON_IRQn = 160, /**< Frame Update Interrupt */ + SLCD_FFAULT_AON_IRQn = 161 /**< Fault Detect Interrupt */ } IRQn_Type; /*! @@ -700,6 +700,8 @@ typedef enum IRQn { /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } #endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -948,46 +950,46 @@ typedef enum IRQn { /* LPCMP - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xB0086000u) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE_NS (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0_NS ((LPCMP_Type *)AON__CMP0_BASE_NS) - /** Peripheral CMP0 base address */ - #define CMP0_BASE (0x500B1000u) - /** Peripheral CMP0 base address */ - #define CMP0_BASE_NS (0x400B1000u) - /** Peripheral CMP0 base pointer */ - #define CMP0 ((LPCMP_Type *)CMP0_BASE) - /** Peripheral CMP0 base pointer */ - #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral ACMP0 base address */ + #define ACMP0_BASE (0x500B1000u) + /** Peripheral ACMP0 base address */ + #define ACMP0_BASE_NS (0x400B1000u) + /** Peripheral ACMP0 base pointer */ + #define ACMP0 ((LPCMP_Type *)ACMP0_BASE) + /** Peripheral ACMP0 base pointer */ + #define ACMP0_NS ((LPCMP_Type *)ACMP0_BASE_NS) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xB0086000u) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE_NS (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0_NS ((LPCMP_Type *)AON__ACMP0_BASE_NS) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE, CMP0_BASE } + #define LPCMP_BASE_ADDRS { ACMP0_BASE, AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0, CMP0 } + #define LPCMP_BASE_PTRS { ACMP0, AON__ACMP0 } /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS_NS { AON__CMP0_BASE_NS, CMP0_BASE_NS } + #define LPCMP_BASE_ADDRS_NS { ACMP0_BASE_NS, AON__ACMP0_BASE_NS } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS_NS { AON__CMP0_NS, CMP0_NS } + #define LPCMP_BASE_PTRS_NS { ACMP0_NS, AON__ACMP0_NS } #else - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) - /** Peripheral CMP0 base address */ - #define CMP0_BASE (0x400B1000u) - /** Peripheral CMP0 base pointer */ - #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral ACMP0 base address */ + #define ACMP0_BASE (0x400B1000u) + /** Peripheral ACMP0 base pointer */ + #define ACMP0 ((LPCMP_Type *)ACMP0_BASE) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE, CMP0_BASE } + #define LPCMP_BASE_ADDRS { ACMP0_BASE, AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0, CMP0 } + #define LPCMP_BASE_PTRS { ACMP0, AON__ACMP0 } #endif /** Interrupt vectors for the LPCMP peripheral type */ -#define LPCMP_IRQS { NotAvail_IRQn, CMP0_IRQn } +#define LPCMP_IRQS { ACMP0_IRQn, ACMP0_AON_IRQn } /* LPI2C - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1171,35 +1173,6 @@ typedef enum IRQn { /** Interrupt vectors for the LPUART peripheral type */ #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART0_AON_IRQn } -/* MBC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MBC0 base address */ - #define MBC0_BASE (0x5008E000u) - /** Peripheral MBC0 base address */ - #define MBC0_BASE_NS (0x4008E000u) - /** Peripheral MBC0 base pointer */ - #define MBC0 ((MBC_Type *)MBC0_BASE) - /** Peripheral MBC0 base pointer */ - #define MBC0_NS ((MBC_Type *)MBC0_BASE_NS) - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS { MBC0_BASE } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS { MBC0 } - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS_NS { MBC0_BASE_NS } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS_NS { MBC0_NS } -#else - /** Peripheral MBC0 base address */ - #define MBC0_BASE (0x4008E000u) - /** Peripheral MBC0 base pointer */ - #define MBC0 ((MBC_Type *)MBC0_BASE) - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS { MBC0_BASE } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS { MBC0 } -#endif - /* MRCC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral MRCC base address */ @@ -1291,31 +1264,31 @@ typedef enum IRQn { /* PKC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PKC0__PKC base address */ - #define PKC0__PKC_BASE (0x500D0000u) - /** Peripheral PKC0__PKC base address */ - #define PKC0__PKC_BASE_NS (0x400D0000u) - /** Peripheral PKC0__PKC base pointer */ - #define PKC0__PKC ((PKC_Type *)PKC0__PKC_BASE) - /** Peripheral PKC0__PKC base pointer */ - #define PKC0__PKC_NS ((PKC_Type *)PKC0__PKC_BASE_NS) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x500D0000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x400D0000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS { PKC0__PKC_BASE } + #define PKC_BASE_ADDRS { PKC0_BASE } /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS { PKC0__PKC } + #define PKC_BASE_PTRS { PKC0 } /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS_NS { PKC0__PKC_BASE_NS } + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS_NS { PKC0__PKC_NS } + #define PKC_BASE_PTRS_NS { PKC0_NS } #else - /** Peripheral PKC0__PKC base address */ - #define PKC0__PKC_BASE (0x400D0000u) - /** Peripheral PKC0__PKC base pointer */ - #define PKC0__PKC ((PKC_Type *)PKC0__PKC_BASE) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x400D0000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS { PKC0__PKC_BASE } + #define PKC_BASE_ADDRS { PKC0_BASE } /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS { PKC0__PKC } + #define PKC_BASE_PTRS { PKC0 } #endif /* PMU - Peripheral instance base addresses */ @@ -1527,35 +1500,41 @@ typedef enum IRQn { /** Array initializer of SGLCD_CONTROL peripheral base pointers */ #define SGLCD_CONTROL_BASE_PTRS { AON__SGLCD0_AON } #endif +/** Interrupt vectors for the SGLCD */ +#define SGLCD_CONTROL_IRQS { SLCD_FRAME_AON_IRQn } + /* SGLCD_FAULT_DETECT - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SGLCD0_MAIN base address */ - #define SGLCD0_MAIN_BASE (0x500C7000u) - /** Peripheral SGLCD0_MAIN base address */ - #define SGLCD0_MAIN_BASE_NS (0x400C7000u) - /** Peripheral SGLCD0_MAIN base pointer */ - #define SGLCD0_MAIN ((SGLCD_FAULT_DETECT_Type *)SGLCD0_MAIN_BASE) - /** Peripheral SGLCD0_MAIN base pointer */ - #define SGLCD0_MAIN_NS ((SGLCD_FAULT_DETECT_Type *)SGLCD0_MAIN_BASE_NS) + /** Peripheral SGLCD_FAULT_DETECT base address */ + #define SGLCD_FAULT_DETECT_BASE (0x500C7000u) + /** Peripheral SGLCD_FAULT_DETECT base address */ + #define SGLCD_FAULT_DETECT_BASE_NS (0x400C7000u) + /** Peripheral SGLCD_FAULT_DETECT base pointer */ + #define SGLCD_FAULT_DETECT ((SGLCD_FAULT_DETECT_Type *)SGLCD_FAULT_DETECT_BASE) + /** Peripheral SGLCD_FAULT_DETECT base pointer */ + #define SGLCD_FAULT_DETECT_NS ((SGLCD_FAULT_DETECT_Type *)SGLCD_FAULT_DETECT_BASE_NS) /** Array initializer of SGLCD_FAULT_DETECT peripheral base addresses */ - #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD0_MAIN_BASE } + #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD_FAULT_DETECT_BASE } /** Array initializer of SGLCD_FAULT_DETECT peripheral base pointers */ - #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD0_MAIN } + #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD_FAULT_DETECT } /** Array initializer of SGLCD_FAULT_DETECT peripheral base addresses */ - #define SGLCD_FAULT_DETECT_BASE_ADDRS_NS { SGLCD0_MAIN_BASE_NS } + #define SGLCD_FAULT_DETECT_BASE_ADDRS_NS { SGLCD_FAULT_DETECT_BASE_NS } /** Array initializer of SGLCD_FAULT_DETECT peripheral base pointers */ - #define SGLCD_FAULT_DETECT_BASE_PTRS_NS { SGLCD0_MAIN_NS } + #define SGLCD_FAULT_DETECT_BASE_PTRS_NS { SGLCD_FAULT_DETECT_NS } #else - /** Peripheral SGLCD0_MAIN base address */ - #define SGLCD0_MAIN_BASE (0x400C7000u) - /** Peripheral SGLCD0_MAIN base pointer */ - #define SGLCD0_MAIN ((SGLCD_FAULT_DETECT_Type *)SGLCD0_MAIN_BASE) + /** Peripheral SGLCD_FAULT_DETECT base address */ + #define SGLCD_FAULT_DETECT_BASE (0x400C7000u) + /** Peripheral SGLCD_FAULT_DETECT base pointer */ + #define SGLCD_FAULT_DETECT ((SGLCD_FAULT_DETECT_Type *)SGLCD_FAULT_DETECT_BASE) /** Array initializer of SGLCD_FAULT_DETECT peripheral base addresses */ - #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD0_MAIN_BASE } + #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD_FAULT_DETECT_BASE } /** Array initializer of SGLCD_FAULT_DETECT peripheral base pointers */ - #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD0_MAIN } + #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD_FAULT_DETECT } #endif +/** Interrupt vectors for the SGLCD */ +#define SGLCD_FAULT_DETECT_IRQS { SLCD_FFAULT_AON_IRQn } + /* SMM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1685,6 +1664,46 @@ typedef enum IRQn { #define TMR_BASE_PTRS { AON__TMR0, AON__TMR1 } #endif +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MBC0 base address */ + #define MBC0_BASE (0x5008E000u) + /** Peripheral MBC0 base address */ + #define MBC0_BASE_NS (0x4008E000u) + /** Peripheral MBC0 base pointer */ + #define MBC0 ((TRDC_Type *)MBC0_BASE) + /** Peripheral MBC0 base pointer */ + #define MBC0_NS ((TRDC_Type *)MBC0_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { MBC0_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { MBC0 } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { MBC0_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { MBC0_NS } +#else + /** Peripheral MBC0 base address */ + #define MBC0_BASE (0x4008E000u) + /** Peripheral MBC0 base pointer */ + #define MBC0 ((TRDC_Type *)MBC0_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { MBC0_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { MBC0 } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + /* TRNG - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral TRNG0 base address */ @@ -1888,3 +1907,4 @@ typedef enum IRQn { #endif /* MCXL253_CM33_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33_features.h index 6e3b9f174..8beb10668 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/MCXL253_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Version: rev. 1.0, 2025-06-13 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -49,8 +49,6 @@ #define FSL_FEATURE_SOC_INPUTMUX_COUNT (2) /* @brief KPP availability on the SoC. */ #define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (2) /* @brief LPADC availability on the SoC. */ #define FSL_FEATURE_SOC_LPADC_COUNT (2) /* @brief LPCMP availability on the SoC. */ @@ -69,8 +67,6 @@ #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) /* @brief PKC availability on the SoC. */ #define FSL_FEATURE_SOC_PKC_COUNT (1) -/* @brief PMU availability on the SoC. */ -#define FSL_FEATURE_SOC_PMU_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (4) /* @brief RTC availability on the SoC. */ @@ -81,6 +77,8 @@ #define FSL_FEATURE_SOC_SYSCON_COUNT (2) /* @brief TMR availability on the SoC. */ #define FSL_FEATURE_SOC_TMR_COUNT (2) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) /* @brief UTICK availability on the SoC. */ #define FSL_FEATURE_SOC_UTICK_COUNT (1) /* @brief WWDT availability on the SoC. */ @@ -88,10 +86,49 @@ /* @brief WUU availability on the SoC. */ #define FSL_FEATURE_SOC_WUU_COUNT (1) +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (0) +/* @brief Has RRCR0 RR_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_CLK_SEL (1) +/* @brief Has RRCR0 RR_TRG_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_TRG_SEL (1) +/* @brief Has RRCR0 RR_SAMPLE_CNT bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_CNT (1) +/* @brief Has RRCR0 RR_SAMPLE_THRESHOLD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_THRESHOLD (1) +/* @brief Has CCR2 INPSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INPSEL (0) +/* @brief Has CCR2 INMSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INMSEL (0) +/* @brief Has CCR2 CMP_NPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_CMP_NPMD (1) +/* @brief Has DCR DAC_HPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_DCR_DAC_HPMD (1) +/* @brief Has CCR0 LINKEN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_LINKEN (0) +/* @brief Has RRCR2 register. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR2 (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) + /* LPADC module features */ /* @brief FIFO availability on the SoC. */ #define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ @@ -102,8 +139,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -112,8 +147,6 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ @@ -122,10 +155,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -138,6 +167,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -160,6 +195,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) /* AOI module features */ @@ -168,23 +207,6 @@ /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ #define FSL_FEATURE_AOI_EVENT_COUNT (4) -/* LPCMP module features */ - -/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) -/* @brief Has IER RRF_IE bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) -/* @brief Has CSR RRF bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) -/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ -#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) -/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ -#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) -/* @brief Has CCR0 CMP_STOP_EN bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) -/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ -#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) - /* GPIO module features */ /* @brief Has GPIO attribute checker register (GACR). */ @@ -207,6 +229,8 @@ (((x) == LPI2C0) ? (4) : \ (((x) == LPI2C1) ? (4) : \ (((x) == AON__LPI2C0) ? (16) : (-1)))) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPTMR module features */ @@ -217,11 +241,11 @@ /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) /* @brief Do not has prescaler clock source 0. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) /* @brief Do not has prescaler clock source 1. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) /* @brief Do not has prescaler clock source 2. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) /* @brief Do not has prescaler clock source 3. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) @@ -257,11 +281,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ - (((x) == LPUART0) ? (4) : \ - (((x) == LPUART1) ? (4) : \ - (((x) == AON__LPUART0) ? (16) : (-1)))) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -294,12 +313,28 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (0) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART0) ? (4) : \ + (((x) == LPUART1) ? (4) : \ + (((x) == AON__LPUART0) ? (16) : (-1)))) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* ADVC module features */ + +/* @brief ADVC calibration data address. */ +#define FSL_FEATURE_ADVC_CFG_TABLE_ADDR (0x01100000UL) /* PORT module features */ @@ -331,6 +366,8 @@ #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ #define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Alt function 0 means GPIO (not analog). */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Defines width of PCR[MUX] field. */ @@ -350,10 +387,26 @@ /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) -/* LCD module features */ +/* SLCD module features */ /* @brief LCD registers are split into control and fault detect parts. */ -#define FSL_FEATURE_SGLCD_HAS_FAULT_DETECT (1) +#define FSL_FEATURE_LCD_HAS_FAULT_DETECT (1) +/* @brief (S)LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (1) +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) /* SYSCON_AON module features */ @@ -362,10 +415,19 @@ /* @brief Starter register discontinuous. */ #define FSL_FEATURE_SYSCON_AON_STARTER_DISCONTINUOUS (1) +/* TMR module features */ + +/* @brief Has 32-bit width register. */ +#define FSL_FEATURE_TMR_HAS_32BIT_REGISTER (1) + /* CDOG module features */ -/* @brief CDOG Has No Reset */ +/* @brief SOC has no reset driver. */ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (1) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -500,17 +562,36 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + /* MU module features */ /* @brief MU side for current core */ @@ -558,6 +639,11 @@ /* @brief The number of general purpose interrupts supported by MU. */ #define FSL_FEATURE_MU_GPI_COUNT (20) +/* OSTIMER module features */ + +/* @brief Has binary encoded value in counter register. */ +#define FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER (1) + /* SYSCON module features */ /* @brief Powerlib API is different with other series devices */ @@ -565,6 +651,29 @@ /* @brief Starter register discontinuous. */ #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* TRNG module features */ + +/* @brief TRNG does not support SCR4L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (1) +/* @brief TRNG does not support SCR5L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (1) +/* @brief TRNG does not support SCR6L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) +/* @brief TRNG does not support PKRMAX. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (1) +/* @brief TRNG does not support SAMP mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) +/* @brief TRNG does not support ACC. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) +/* @brief TRNG does not support SBLIM. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (1) +/* @brief TRNG supports reset control. */ +#define FSL_FEATURE_TRNG_HAS_RSTCTL (1) +/* @brief TRNG does not support FOR_CLK mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1) +/* @brief TRNG has two oscillators. */ +#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) + /* UTICK module features */ /* @brief UTICK does not support power down configure. */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm0plus/setting.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm0plus/setting.cmake new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm0plus/setting.cmake @@ -0,0 +1 @@ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm0plus/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm0plus/variable.cmake new file mode 100644 index 000000000..cdd3e6d76 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm0plus/variable.cmake @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm0plus) +mcux_set_variable(multicore_foldername cm0plus) + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm33/setting.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm33/setting.cmake new file mode 100644 index 000000000..4dad0e6e2 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm33/setting.cmake @@ -0,0 +1 @@ +#mcux_add_cmakelists(${CMAKE_CURRENT_LIST_DIR}/../xip) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm33/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm33/variable.cmake new file mode 100644 index 000000000..12cbceaf9 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/cm33/variable.cmake @@ -0,0 +1,9 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33) +mcux_set_variable(multicore_foldername cm33) +mcux_set_variable(multicore_sec_core_foldername cm0plus) \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm0plus.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm0plus.c index 7234c88e4..cd7a25f55 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm0plus.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm0plus.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL253_cm0plus * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL253_cm0plus (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm0plus.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm0plus.h index 36c84b012..abdb48802 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm0plus.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm0plus.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL253_cm0plus * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL253_cm0plus (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm33.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm33.c index 42178c4dc..f231cc7b7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm33.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm33.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL253_cm33 * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL253_cm33 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm33.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm33.h index c9341d578..634d7be6c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm33.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/system_MCXL253_cm33.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL253_cm33 * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL253_cm33 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/variable.cmake new file mode 100644 index 000000000..9a3d47ae7 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL253/variable.cmake @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +mcux_set_variable(device_root devices) + +include(${SdkRootDirPath}/${device_root}/MCX/MCXL/variable.cmake) +mcux_set_variable(device MCXL253) + +if (NOT DEFINED core_id) + message(FATAL_ERROR "Please specify core_id for multicore device like -Dcore_id=cm33 or -Dcore_id=cm0plus") +endif() + +include(${CMAKE_CURRENT_LIST_DIR}/${core_id}/variable.cmake) + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/CMakeLists.txt new file mode 100644 index 000000000..de4de5e6a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright 2024-2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) + +#### core related +include(${CMAKE_CURRENT_LIST_DIR}/${core_id}/setting.cmake) + +#### device specific drivers +mcux_add_cmakelists(${CMAKE_CURRENT_LIST_DIR}/../MCXL255/drivers) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus.h index 9a25f199e..c06439e69 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL254_cm0plus @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL254_cm0plus.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL254_cm0plus * * CMSIS Peripheral Access Layer for MCXL254_cm0plus diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus_COMMON.h index 321ed01b5..700c0ce19 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus_COMMON.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250812 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL254_cm0plus @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL254_cm0plus_COMMON.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL254_cm0plus * * CMSIS Peripheral Access Layer for MCXL254_cm0plus @@ -66,10 +66,10 @@ typedef enum IRQn { /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0P SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0P SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0P Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0P System Tick Interrupt */ /* Device specific interrupts */ LPI2C0_AON_IRQn = 1, /**< Low-Power Inter Integrated Circuit interrupt */ @@ -91,12 +91,12 @@ typedef enum IRQn { PMU_IRQn = 20, /**< PMU IRQ */ KPP_IRQn = 21, /**< Keypad Interrupt */ LPADC_AON_IRQn = 22, /**< Analog-to-Digital Converter interrupt */ - SGLCD_AON_IRQn = 23, /**< SLCD frame start interrupt */ + SLCD_FRAME_AON_IRQn = 23, /**< SLCD frame start interrupt */ TMR0_AON_IRQn = 24, /**< ORed QTMR Interrupts */ TMR1_AON_IRQn = 25, /**< ORed QTMR Interrupts */ LCSENSE_IRQn = 27, /**< LCSense Fault/Tamper Interrupt */ LPTMR_AON_IRQn = 28, /**< Low Power Timer 0 interrupt */ - CMP0_AON_IRQn = 30, /**< Comparator interrupt */ + ACMP0_AON_IRQn = 30, /**< Comparator interrupt */ ADVC_IRQn = 31 /**< ADVC_2.0 Controller Interrupt */ } IRQn_Type; @@ -314,32 +314,34 @@ typedef enum IRQn { /* LPCMP - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xB0086000u) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE_NS (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0_NS ((LPCMP_Type *)AON__CMP0_BASE_NS) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xB0086000u) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE_NS (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0_NS ((LPCMP_Type *)AON__ACMP0_BASE_NS) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE } + #define LPCMP_BASE_ADDRS { AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0 } + #define LPCMP_BASE_PTRS { AON__ACMP0 } /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS_NS { AON__CMP0_BASE_NS } + #define LPCMP_BASE_ADDRS_NS { AON__ACMP0_BASE_NS } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS_NS { AON__CMP0_NS } + #define LPCMP_BASE_PTRS_NS { AON__ACMP0_NS } #else - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE } + #define LPCMP_BASE_ADDRS { AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0 } + #define LPCMP_BASE_PTRS { AON__ACMP0 } #endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { ACMP0_AON_IRQn } /* LPI2C - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) @@ -576,6 +578,9 @@ typedef enum IRQn { /** Array initializer of SGLCD_CONTROL peripheral base pointers */ #define SGLCD_CONTROL_BASE_PTRS { AON__SGLCD0_AON } #endif +/** Interrupt vectors for the SGLCD */ +#define SGLCD_CONTROL_IRQS { SLCD_FRAME_AON_IRQn } + /* SMM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) @@ -730,3 +735,4 @@ typedef enum IRQn { #endif /* MCXL254_CM0PLUS_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus_features.h index 2755f6e0c..b36a94843 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm0plus_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Version: rev. 1.0, 2025-06-13 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -31,8 +31,6 @@ #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) /* @brief KPP availability on the SoC. */ #define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (1) /* @brief LPADC availability on the SoC. */ #define FSL_FEATURE_SOC_LPADC_COUNT (1) /* @brief LPCMP availability on the SoC. */ @@ -45,8 +43,6 @@ #define FSL_FEATURE_SOC_LPUART_COUNT (1) /* @brief MU availability on the SoC. */ #define FSL_FEATURE_SOC_MU_COUNT (1) -/* @brief PMU availability on the SoC. */ -#define FSL_FEATURE_SOC_PMU_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (1) /* @brief RTC availability on the SoC. */ @@ -68,10 +64,30 @@ #define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) /* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ #define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (0) +/* @brief Has RRCR0 RR_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_CLK_SEL (1) +/* @brief Has RRCR0 RR_TRG_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_TRG_SEL (1) +/* @brief Has RRCR0 RR_SAMPLE_CNT bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_CNT (1) +/* @brief Has RRCR0 RR_SAMPLE_THRESHOLD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_THRESHOLD (1) +/* @brief Has CCR2 INPSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INPSEL (0) +/* @brief Has CCR2 INMSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INMSEL (0) +/* @brief Has CCR2 CMP_NPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_CMP_NPMD (1) +/* @brief Has DCR DAC_HPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_DCR_DAC_HPMD (1) +/* @brief Has CCR0 LINKEN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_LINKEN (0) +/* @brief Has RRCR2 register. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR2 (1) /* @brief Has CCR0 CMP_STOP_EN bitfield. */ #define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) -/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ -#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) /* GPIO module features */ @@ -92,6 +108,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (16) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPTMR module features */ @@ -102,11 +120,11 @@ /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) /* @brief Do not has prescaler clock source 0. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) /* @brief Do not has prescaler clock source 1. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) /* @brief Do not has prescaler clock source 2. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) /* @brief Do not has prescaler clock source 3. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) @@ -142,8 +160,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -176,12 +192,25 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (0) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* ADVC module features */ + +/* @brief ADVC calibration data address. */ +#define FSL_FEATURE_ADVC_CFG_TABLE_ADDR (0x01100000UL) /* PORT module features */ @@ -213,6 +242,8 @@ #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ #define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Alt function 0 means GPIO (not analog). */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Defines width of PCR[MUX] field. */ @@ -232,10 +263,24 @@ /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) -/* LCD module features */ +/* SLCD module features */ -/* @brief LCD registers are split into control and fault detect parts. */ -#define FSL_FEATURE_SGLCD_HAS_FAULT_DETECT (1) +/* @brief (S)LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (1) +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) /* SYSCON_AON module features */ @@ -244,6 +289,11 @@ /* @brief Starter register discontinuous. */ #define FSL_FEATURE_SYSCON_AON_STARTER_DISCONTINUOUS (1) +/* TMR module features */ + +/* @brief Has 32-bit width register. */ +#define FSL_FEATURE_TMR_HAS_32BIT_REGISTER (1) + /* MU module features */ /* @brief MU side for current core */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33.h index 58f88aa8d..a831c3bef 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL254_cm33 @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL254_cm33.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL254_cm33 * * CMSIS Peripheral Access Layer for MCXL254_cm33 @@ -70,7 +70,6 @@ #include "PERI_LPSPI.h" #include "PERI_LPTMR.h" #include "PERI_LPUART.h" -#include "PERI_MBC.h" #include "PERI_MRCC.h" #include "PERI_MU.h" #include "PERI_OSTIMER.h" @@ -86,6 +85,7 @@ #include "PERI_SYSCON.h" #include "PERI_SYSCON_AON.h" #include "PERI_TMR.h" +#include "PERI_TRDC.h" #include "PERI_TRNG.h" #include "PERI_UDF.h" #include "PERI_UTICK.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33_COMMON.h index 715b1aa07..41857829d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33_COMMON.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250812 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL254_cm33 @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL254_cm33_COMMON.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL254_cm33 * * CMSIS Peripheral Access Layer for MCXL254_cm33 @@ -104,7 +104,7 @@ typedef enum IRQn { UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ ADC0_IRQn = 62, /**< Analog-to-Digital Converter interrupt */ - CMP0_IRQn = 64, /**< Comparator interrupt */ + ACMP0_IRQn = 64, /**< Comparator interrupt */ GPIO10_IRQn = 71, /**< General Purpose Input/Output 1 interrupt 0 */ GPIO11_IRQn = 72, /**< General Purpose Input/Output 1 interrupt 1 */ GPIO20_IRQn = 73, /**< General Purpose Input/Output 2 interrupt 0 */ @@ -140,10 +140,10 @@ typedef enum IRQn { TMR1_AON_IRQn = 152, /**< ORed QTMR Interrupts */ LCSENSE_IRQn = 154, /**< LCSense Fault/Tamper Interrupt */ LPTMR_AON_IRQn = 155, /**< Low Power Timer 0 interrupt */ - CMP0_AON_IRQn = 157, /**< Comparator interrupt */ + ACMP0_AON_IRQn = 157, /**< Comparator interrupt */ ADVC_IRQn = 158, /**< ADVC_2.0 Controller Interrupt */ - SGLCD_FRAME_AON_IRQn = 160, /**< Frame Update Interrupt */ - SGLCD_FFAULT_AON_IRQn = 161 /**< Fault Detect Interrupt */ + SLCD_FRAME_AON_IRQn = 160, /**< Frame Update Interrupt */ + SLCD_FFAULT_AON_IRQn = 161 /**< Fault Detect Interrupt */ } IRQn_Type; /*! @@ -700,6 +700,8 @@ typedef enum IRQn { /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } #endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -948,46 +950,46 @@ typedef enum IRQn { /* LPCMP - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xB0086000u) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE_NS (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0_NS ((LPCMP_Type *)AON__CMP0_BASE_NS) - /** Peripheral CMP0 base address */ - #define CMP0_BASE (0x500B1000u) - /** Peripheral CMP0 base address */ - #define CMP0_BASE_NS (0x400B1000u) - /** Peripheral CMP0 base pointer */ - #define CMP0 ((LPCMP_Type *)CMP0_BASE) - /** Peripheral CMP0 base pointer */ - #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral ACMP0 base address */ + #define ACMP0_BASE (0x500B1000u) + /** Peripheral ACMP0 base address */ + #define ACMP0_BASE_NS (0x400B1000u) + /** Peripheral ACMP0 base pointer */ + #define ACMP0 ((LPCMP_Type *)ACMP0_BASE) + /** Peripheral ACMP0 base pointer */ + #define ACMP0_NS ((LPCMP_Type *)ACMP0_BASE_NS) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xB0086000u) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE_NS (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0_NS ((LPCMP_Type *)AON__ACMP0_BASE_NS) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE, CMP0_BASE } + #define LPCMP_BASE_ADDRS { ACMP0_BASE, AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0, CMP0 } + #define LPCMP_BASE_PTRS { ACMP0, AON__ACMP0 } /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS_NS { AON__CMP0_BASE_NS, CMP0_BASE_NS } + #define LPCMP_BASE_ADDRS_NS { ACMP0_BASE_NS, AON__ACMP0_BASE_NS } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS_NS { AON__CMP0_NS, CMP0_NS } + #define LPCMP_BASE_PTRS_NS { ACMP0_NS, AON__ACMP0_NS } #else - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) - /** Peripheral CMP0 base address */ - #define CMP0_BASE (0x400B1000u) - /** Peripheral CMP0 base pointer */ - #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral ACMP0 base address */ + #define ACMP0_BASE (0x400B1000u) + /** Peripheral ACMP0 base pointer */ + #define ACMP0 ((LPCMP_Type *)ACMP0_BASE) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE, CMP0_BASE } + #define LPCMP_BASE_ADDRS { ACMP0_BASE, AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0, CMP0 } + #define LPCMP_BASE_PTRS { ACMP0, AON__ACMP0 } #endif /** Interrupt vectors for the LPCMP peripheral type */ -#define LPCMP_IRQS { NotAvail_IRQn, CMP0_IRQn } +#define LPCMP_IRQS { ACMP0_IRQn, ACMP0_AON_IRQn } /* LPI2C - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1171,35 +1173,6 @@ typedef enum IRQn { /** Interrupt vectors for the LPUART peripheral type */ #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART0_AON_IRQn } -/* MBC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral MBC0 base address */ - #define MBC0_BASE (0x5008E000u) - /** Peripheral MBC0 base address */ - #define MBC0_BASE_NS (0x4008E000u) - /** Peripheral MBC0 base pointer */ - #define MBC0 ((MBC_Type *)MBC0_BASE) - /** Peripheral MBC0 base pointer */ - #define MBC0_NS ((MBC_Type *)MBC0_BASE_NS) - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS { MBC0_BASE } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS { MBC0 } - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS_NS { MBC0_BASE_NS } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS_NS { MBC0_NS } -#else - /** Peripheral MBC0 base address */ - #define MBC0_BASE (0x4008E000u) - /** Peripheral MBC0 base pointer */ - #define MBC0 ((MBC_Type *)MBC0_BASE) - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS { MBC0_BASE } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS { MBC0 } -#endif - /* MRCC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral MRCC base address */ @@ -1291,31 +1264,31 @@ typedef enum IRQn { /* PKC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PKC0__PKC base address */ - #define PKC0__PKC_BASE (0x500D0000u) - /** Peripheral PKC0__PKC base address */ - #define PKC0__PKC_BASE_NS (0x400D0000u) - /** Peripheral PKC0__PKC base pointer */ - #define PKC0__PKC ((PKC_Type *)PKC0__PKC_BASE) - /** Peripheral PKC0__PKC base pointer */ - #define PKC0__PKC_NS ((PKC_Type *)PKC0__PKC_BASE_NS) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x500D0000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x400D0000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS { PKC0__PKC_BASE } + #define PKC_BASE_ADDRS { PKC0_BASE } /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS { PKC0__PKC } + #define PKC_BASE_PTRS { PKC0 } /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS_NS { PKC0__PKC_BASE_NS } + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS_NS { PKC0__PKC_NS } + #define PKC_BASE_PTRS_NS { PKC0_NS } #else - /** Peripheral PKC0__PKC base address */ - #define PKC0__PKC_BASE (0x400D0000u) - /** Peripheral PKC0__PKC base pointer */ - #define PKC0__PKC ((PKC_Type *)PKC0__PKC_BASE) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x400D0000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS { PKC0__PKC_BASE } + #define PKC_BASE_ADDRS { PKC0_BASE } /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS { PKC0__PKC } + #define PKC_BASE_PTRS { PKC0 } #endif /* PMU - Peripheral instance base addresses */ @@ -1527,35 +1500,41 @@ typedef enum IRQn { /** Array initializer of SGLCD_CONTROL peripheral base pointers */ #define SGLCD_CONTROL_BASE_PTRS { AON__SGLCD0_AON } #endif +/** Interrupt vectors for the SGLCD */ +#define SGLCD_CONTROL_IRQS { SLCD_FRAME_AON_IRQn } + /* SGLCD_FAULT_DETECT - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SGLCD0_MAIN base address */ - #define SGLCD0_MAIN_BASE (0x500C7000u) - /** Peripheral SGLCD0_MAIN base address */ - #define SGLCD0_MAIN_BASE_NS (0x400C7000u) - /** Peripheral SGLCD0_MAIN base pointer */ - #define SGLCD0_MAIN ((SGLCD_FAULT_DETECT_Type *)SGLCD0_MAIN_BASE) - /** Peripheral SGLCD0_MAIN base pointer */ - #define SGLCD0_MAIN_NS ((SGLCD_FAULT_DETECT_Type *)SGLCD0_MAIN_BASE_NS) + /** Peripheral SGLCD_FAULT_DETECT base address */ + #define SGLCD_FAULT_DETECT_BASE (0x500C7000u) + /** Peripheral SGLCD_FAULT_DETECT base address */ + #define SGLCD_FAULT_DETECT_BASE_NS (0x400C7000u) + /** Peripheral SGLCD_FAULT_DETECT base pointer */ + #define SGLCD_FAULT_DETECT ((SGLCD_FAULT_DETECT_Type *)SGLCD_FAULT_DETECT_BASE) + /** Peripheral SGLCD_FAULT_DETECT base pointer */ + #define SGLCD_FAULT_DETECT_NS ((SGLCD_FAULT_DETECT_Type *)SGLCD_FAULT_DETECT_BASE_NS) /** Array initializer of SGLCD_FAULT_DETECT peripheral base addresses */ - #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD0_MAIN_BASE } + #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD_FAULT_DETECT_BASE } /** Array initializer of SGLCD_FAULT_DETECT peripheral base pointers */ - #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD0_MAIN } + #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD_FAULT_DETECT } /** Array initializer of SGLCD_FAULT_DETECT peripheral base addresses */ - #define SGLCD_FAULT_DETECT_BASE_ADDRS_NS { SGLCD0_MAIN_BASE_NS } + #define SGLCD_FAULT_DETECT_BASE_ADDRS_NS { SGLCD_FAULT_DETECT_BASE_NS } /** Array initializer of SGLCD_FAULT_DETECT peripheral base pointers */ - #define SGLCD_FAULT_DETECT_BASE_PTRS_NS { SGLCD0_MAIN_NS } + #define SGLCD_FAULT_DETECT_BASE_PTRS_NS { SGLCD_FAULT_DETECT_NS } #else - /** Peripheral SGLCD0_MAIN base address */ - #define SGLCD0_MAIN_BASE (0x400C7000u) - /** Peripheral SGLCD0_MAIN base pointer */ - #define SGLCD0_MAIN ((SGLCD_FAULT_DETECT_Type *)SGLCD0_MAIN_BASE) + /** Peripheral SGLCD_FAULT_DETECT base address */ + #define SGLCD_FAULT_DETECT_BASE (0x400C7000u) + /** Peripheral SGLCD_FAULT_DETECT base pointer */ + #define SGLCD_FAULT_DETECT ((SGLCD_FAULT_DETECT_Type *)SGLCD_FAULT_DETECT_BASE) /** Array initializer of SGLCD_FAULT_DETECT peripheral base addresses */ - #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD0_MAIN_BASE } + #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD_FAULT_DETECT_BASE } /** Array initializer of SGLCD_FAULT_DETECT peripheral base pointers */ - #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD0_MAIN } + #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD_FAULT_DETECT } #endif +/** Interrupt vectors for the SGLCD */ +#define SGLCD_FAULT_DETECT_IRQS { SLCD_FFAULT_AON_IRQn } + /* SMM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1685,6 +1664,46 @@ typedef enum IRQn { #define TMR_BASE_PTRS { AON__TMR0, AON__TMR1 } #endif +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MBC0 base address */ + #define MBC0_BASE (0x5008E000u) + /** Peripheral MBC0 base address */ + #define MBC0_BASE_NS (0x4008E000u) + /** Peripheral MBC0 base pointer */ + #define MBC0 ((TRDC_Type *)MBC0_BASE) + /** Peripheral MBC0 base pointer */ + #define MBC0_NS ((TRDC_Type *)MBC0_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { MBC0_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { MBC0 } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { MBC0_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { MBC0_NS } +#else + /** Peripheral MBC0 base address */ + #define MBC0_BASE (0x4008E000u) + /** Peripheral MBC0 base pointer */ + #define MBC0 ((TRDC_Type *)MBC0_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { MBC0_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { MBC0 } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + /* TRNG - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral TRNG0 base address */ @@ -1888,3 +1907,4 @@ typedef enum IRQn { #endif /* MCXL254_CM33_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33_features.h index c552f7364..f760c37c0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/MCXL254_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Version: rev. 1.0, 2025-06-13 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -49,8 +49,6 @@ #define FSL_FEATURE_SOC_INPUTMUX_COUNT (2) /* @brief KPP availability on the SoC. */ #define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (2) /* @brief LPADC availability on the SoC. */ #define FSL_FEATURE_SOC_LPADC_COUNT (2) /* @brief LPCMP availability on the SoC. */ @@ -69,8 +67,6 @@ #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) /* @brief PKC availability on the SoC. */ #define FSL_FEATURE_SOC_PKC_COUNT (1) -/* @brief PMU availability on the SoC. */ -#define FSL_FEATURE_SOC_PMU_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (4) /* @brief RTC availability on the SoC. */ @@ -81,6 +77,8 @@ #define FSL_FEATURE_SOC_SYSCON_COUNT (2) /* @brief TMR availability on the SoC. */ #define FSL_FEATURE_SOC_TMR_COUNT (2) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) /* @brief UTICK availability on the SoC. */ #define FSL_FEATURE_SOC_UTICK_COUNT (1) /* @brief WWDT availability on the SoC. */ @@ -88,10 +86,49 @@ /* @brief WUU availability on the SoC. */ #define FSL_FEATURE_SOC_WUU_COUNT (1) +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (0) +/* @brief Has RRCR0 RR_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_CLK_SEL (1) +/* @brief Has RRCR0 RR_TRG_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_TRG_SEL (1) +/* @brief Has RRCR0 RR_SAMPLE_CNT bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_CNT (1) +/* @brief Has RRCR0 RR_SAMPLE_THRESHOLD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_THRESHOLD (1) +/* @brief Has CCR2 INPSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INPSEL (0) +/* @brief Has CCR2 INMSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INMSEL (0) +/* @brief Has CCR2 CMP_NPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_CMP_NPMD (1) +/* @brief Has DCR DAC_HPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_DCR_DAC_HPMD (1) +/* @brief Has CCR0 LINKEN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_LINKEN (0) +/* @brief Has RRCR2 register. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR2 (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) + /* LPADC module features */ /* @brief FIFO availability on the SoC. */ #define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ @@ -102,8 +139,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -112,8 +147,6 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ @@ -122,10 +155,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -138,6 +167,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -160,6 +195,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) /* AOI module features */ @@ -168,23 +207,6 @@ /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ #define FSL_FEATURE_AOI_EVENT_COUNT (4) -/* LPCMP module features */ - -/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) -/* @brief Has IER RRF_IE bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) -/* @brief Has CSR RRF bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) -/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ -#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) -/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ -#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) -/* @brief Has CCR0 CMP_STOP_EN bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) -/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ -#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) - /* GPIO module features */ /* @brief Has GPIO attribute checker register (GACR). */ @@ -207,6 +229,8 @@ (((x) == LPI2C0) ? (4) : \ (((x) == LPI2C1) ? (4) : \ (((x) == AON__LPI2C0) ? (16) : (-1)))) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPTMR module features */ @@ -217,11 +241,11 @@ /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) /* @brief Do not has prescaler clock source 0. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) /* @brief Do not has prescaler clock source 1. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) /* @brief Do not has prescaler clock source 2. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) /* @brief Do not has prescaler clock source 3. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) @@ -257,11 +281,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ - (((x) == LPUART0) ? (4) : \ - (((x) == LPUART1) ? (4) : \ - (((x) == AON__LPUART0) ? (16) : (-1)))) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -294,12 +313,28 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (0) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART0) ? (4) : \ + (((x) == LPUART1) ? (4) : \ + (((x) == AON__LPUART0) ? (16) : (-1)))) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* ADVC module features */ + +/* @brief ADVC calibration data address. */ +#define FSL_FEATURE_ADVC_CFG_TABLE_ADDR (0x01100000UL) /* PORT module features */ @@ -331,6 +366,8 @@ #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ #define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Alt function 0 means GPIO (not analog). */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Defines width of PCR[MUX] field. */ @@ -350,10 +387,26 @@ /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) -/* LCD module features */ +/* SLCD module features */ /* @brief LCD registers are split into control and fault detect parts. */ -#define FSL_FEATURE_SGLCD_HAS_FAULT_DETECT (1) +#define FSL_FEATURE_LCD_HAS_FAULT_DETECT (1) +/* @brief (S)LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (1) +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) /* SYSCON_AON module features */ @@ -362,10 +415,19 @@ /* @brief Starter register discontinuous. */ #define FSL_FEATURE_SYSCON_AON_STARTER_DISCONTINUOUS (1) +/* TMR module features */ + +/* @brief Has 32-bit width register. */ +#define FSL_FEATURE_TMR_HAS_32BIT_REGISTER (1) + /* CDOG module features */ -/* @brief CDOG Has No Reset */ +/* @brief SOC has no reset driver. */ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (1) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -500,17 +562,36 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + /* MU module features */ /* @brief MU side for current core */ @@ -558,6 +639,11 @@ /* @brief The number of general purpose interrupts supported by MU. */ #define FSL_FEATURE_MU_GPI_COUNT (20) +/* OSTIMER module features */ + +/* @brief Has binary encoded value in counter register. */ +#define FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER (1) + /* SYSCON module features */ /* @brief Powerlib API is different with other series devices */ @@ -565,6 +651,29 @@ /* @brief Starter register discontinuous. */ #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* TRNG module features */ + +/* @brief TRNG does not support SCR4L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (1) +/* @brief TRNG does not support SCR5L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (1) +/* @brief TRNG does not support SCR6L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) +/* @brief TRNG does not support PKRMAX. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (1) +/* @brief TRNG does not support SAMP mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) +/* @brief TRNG does not support ACC. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) +/* @brief TRNG does not support SBLIM. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (1) +/* @brief TRNG supports reset control. */ +#define FSL_FEATURE_TRNG_HAS_RSTCTL (1) +/* @brief TRNG does not support FOR_CLK mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1) +/* @brief TRNG has two oscillators. */ +#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) + /* UTICK module features */ /* @brief UTICK does not support power down configure. */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm0plus/setting.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm0plus/setting.cmake new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm0plus/setting.cmake @@ -0,0 +1 @@ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm0plus/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm0plus/variable.cmake new file mode 100644 index 000000000..cdd3e6d76 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm0plus/variable.cmake @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm0plus) +mcux_set_variable(multicore_foldername cm0plus) + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm33/setting.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm33/setting.cmake new file mode 100644 index 000000000..4dad0e6e2 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm33/setting.cmake @@ -0,0 +1 @@ +#mcux_add_cmakelists(${CMAKE_CURRENT_LIST_DIR}/../xip) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm33/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm33/variable.cmake new file mode 100644 index 000000000..12cbceaf9 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/cm33/variable.cmake @@ -0,0 +1,9 @@ +# Copyright 2025 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33) +mcux_set_variable(multicore_foldername cm33) +mcux_set_variable(multicore_sec_core_foldername cm0plus) \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm0plus.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm0plus.c index e3a00781e..9f59279eb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm0plus.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm0plus.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL254_cm0plus * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL254_cm0plus (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm0plus.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm0plus.h index bd321948f..d50b2f605 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm0plus.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm0plus.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL254_cm0plus * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL254_cm0plus (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm33.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm33.c index 34ad88add..79b04b950 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm33.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm33.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL254_cm33 * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL254_cm33 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm33.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm33.h index 8ea3321e6..1cdf2db86 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm33.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/system_MCXL254_cm33.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL254_cm33 * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL254_cm33 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/variable.cmake new file mode 100644 index 000000000..b7edb3207 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL254/variable.cmake @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +mcux_set_variable(device_root devices) + +include(${SdkRootDirPath}/${device_root}/MCX/MCXL/variable.cmake) +mcux_set_variable(device MCXL254) + +if (NOT DEFINED core_id) + message(FATAL_ERROR "Please specify core_id for multicore device like -Dcore_id=cm33 or -Dcore_id=cm0plus") +endif() + +include(${CMAKE_CURRENT_LIST_DIR}/${core_id}/variable.cmake) + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus.h index a32474b4c..aaf04979a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL255_cm0plus @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL255_cm0plus.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL255_cm0plus * * CMSIS Peripheral Access Layer for MCXL255_cm0plus diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus_COMMON.h index 297acafb4..c4de1aa58 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus_COMMON.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250812 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL255_cm0plus @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL255_cm0plus_COMMON.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL255_cm0plus * * CMSIS Peripheral Access Layer for MCXL255_cm0plus @@ -66,10 +66,10 @@ typedef enum IRQn { /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0P SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0P SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0P Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0P System Tick Interrupt */ /* Device specific interrupts */ LPI2C0_AON_IRQn = 1, /**< Low-Power Inter Integrated Circuit interrupt */ @@ -91,12 +91,12 @@ typedef enum IRQn { PMU_IRQn = 20, /**< PMU IRQ */ KPP_IRQn = 21, /**< Keypad Interrupt */ LPADC_AON_IRQn = 22, /**< Analog-to-Digital Converter interrupt */ - SGLCD_AON_IRQn = 23, /**< SLCD frame start interrupt */ + SLCD_FRAME_AON_IRQn = 23, /**< SLCD frame start interrupt */ TMR0_AON_IRQn = 24, /**< ORed QTMR Interrupts */ TMR1_AON_IRQn = 25, /**< ORed QTMR Interrupts */ LCSENSE_IRQn = 27, /**< LCSense Fault/Tamper Interrupt */ LPTMR_AON_IRQn = 28, /**< Low Power Timer 0 interrupt */ - CMP0_AON_IRQn = 30, /**< Comparator interrupt */ + ACMP0_AON_IRQn = 30, /**< Comparator interrupt */ ADVC_IRQn = 31 /**< ADVC_2.0 Controller Interrupt */ } IRQn_Type; @@ -128,7 +128,9 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +#ifndef MCXL255_cm0plus_SERIES #define MCXL255_cm0plus_SERIES +#endif /* CPU specific feature definitions */ #include "MCXL255_cm0plus_features.h" @@ -312,32 +314,34 @@ typedef enum IRQn { /* LPCMP - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xB0086000u) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE_NS (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0_NS ((LPCMP_Type *)AON__CMP0_BASE_NS) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xB0086000u) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE_NS (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0_NS ((LPCMP_Type *)AON__ACMP0_BASE_NS) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE } + #define LPCMP_BASE_ADDRS { AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0 } + #define LPCMP_BASE_PTRS { AON__ACMP0 } /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS_NS { AON__CMP0_BASE_NS } + #define LPCMP_BASE_ADDRS_NS { AON__ACMP0_BASE_NS } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS_NS { AON__CMP0_NS } + #define LPCMP_BASE_PTRS_NS { AON__ACMP0_NS } #else - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE } + #define LPCMP_BASE_ADDRS { AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0 } + #define LPCMP_BASE_PTRS { AON__ACMP0 } #endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { ACMP0_AON_IRQn } /* LPI2C - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) @@ -574,9 +578,9 @@ typedef enum IRQn { /** Array initializer of SGLCD_CONTROL peripheral base pointers */ #define SGLCD_CONTROL_BASE_PTRS { AON__SGLCD0_AON } #endif +/** Interrupt vectors for the SGLCD */ +#define SGLCD_CONTROL_IRQS { SLCD_FRAME_AON_IRQn } -/** Interrupt vectors for the LCD_CONTROL peripheral type */ -#define SGLCD_CONTROL_IRQS { SGLCD_AON_IRQn } /* SMM - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus_features.h index d743a39b1..44dd6fe91 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm0plus_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Version: rev. 1.0, 2025-06-13 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -31,8 +31,6 @@ #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) /* @brief KPP availability on the SoC. */ #define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (1) /* @brief LPADC availability on the SoC. */ #define FSL_FEATURE_SOC_LPADC_COUNT (1) /* @brief LPCMP availability on the SoC. */ @@ -45,8 +43,6 @@ #define FSL_FEATURE_SOC_LPUART_COUNT (1) /* @brief MU availability on the SoC. */ #define FSL_FEATURE_SOC_MU_COUNT (1) -/* @brief PMU availability on the SoC. */ -#define FSL_FEATURE_SOC_PMU_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (1) /* @brief RTC availability on the SoC. */ @@ -68,10 +64,30 @@ #define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) /* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ #define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (0) +/* @brief Has RRCR0 RR_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_CLK_SEL (1) +/* @brief Has RRCR0 RR_TRG_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_TRG_SEL (1) +/* @brief Has RRCR0 RR_SAMPLE_CNT bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_CNT (1) +/* @brief Has RRCR0 RR_SAMPLE_THRESHOLD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_THRESHOLD (1) +/* @brief Has CCR2 INPSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INPSEL (0) +/* @brief Has CCR2 INMSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INMSEL (0) +/* @brief Has CCR2 CMP_NPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_CMP_NPMD (1) +/* @brief Has DCR DAC_HPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_DCR_DAC_HPMD (1) +/* @brief Has CCR0 LINKEN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_LINKEN (0) +/* @brief Has RRCR2 register. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR2 (1) /* @brief Has CCR0 CMP_STOP_EN bitfield. */ #define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) -/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ -#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) /* GPIO module features */ @@ -92,6 +108,8 @@ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (16) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPTMR module features */ @@ -102,11 +120,11 @@ /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) /* @brief Do not has prescaler clock source 0. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) /* @brief Do not has prescaler clock source 1. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) /* @brief Do not has prescaler clock source 2. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) /* @brief Do not has prescaler clock source 3. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) @@ -142,8 +160,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -176,12 +192,25 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (0) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* ADVC module features */ + +/* @brief ADVC calibration data address. */ +#define FSL_FEATURE_ADVC_CFG_TABLE_ADDR (0x01100000UL) /* PORT module features */ @@ -213,6 +242,8 @@ #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ #define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Alt function 0 means GPIO (not analog). */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Defines width of PCR[MUX] field. */ @@ -232,10 +263,24 @@ /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) -/* LCD module features */ +/* SLCD module features */ -/* @brief LCD registers are split into control and fault detect parts. */ -#define FSL_FEATURE_SGLCD_HAS_FAULT_DETECT (1) +/* @brief (S)LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (1) +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) /* SYSCON_AON module features */ @@ -244,6 +289,11 @@ /* @brief Starter register discontinuous. */ #define FSL_FEATURE_SYSCON_AON_STARTER_DISCONTINUOUS (1) +/* TMR module features */ + +/* @brief Has 32-bit width register. */ +#define FSL_FEATURE_TMR_HAS_32BIT_REGISTER (1) + /* MU module features */ /* @brief MU side for current core */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33.h index 88bbbd190..18fbed477 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL255_cm33 @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL255_cm33.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL255_cm33 * * CMSIS Peripheral Access Layer for MCXL255_cm33 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33_COMMON.h index 75d78a7e8..359396780 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33_COMMON.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250812 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXL255_cm33 @@ -23,8 +23,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -32,7 +32,7 @@ /*! * @file MCXL255_cm33_COMMON.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MCXL255_cm33 * * CMSIS Peripheral Access Layer for MCXL255_cm33 @@ -104,7 +104,7 @@ typedef enum IRQn { UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ ADC0_IRQn = 62, /**< Analog-to-Digital Converter interrupt */ - CMP0_IRQn = 64, /**< Comparator interrupt */ + ACMP0_IRQn = 64, /**< Comparator interrupt */ GPIO10_IRQn = 71, /**< General Purpose Input/Output 1 interrupt 0 */ GPIO11_IRQn = 72, /**< General Purpose Input/Output 1 interrupt 1 */ GPIO20_IRQn = 73, /**< General Purpose Input/Output 2 interrupt 0 */ @@ -140,10 +140,10 @@ typedef enum IRQn { TMR1_AON_IRQn = 152, /**< ORed QTMR Interrupts */ LCSENSE_IRQn = 154, /**< LCSense Fault/Tamper Interrupt */ LPTMR_AON_IRQn = 155, /**< Low Power Timer 0 interrupt */ - CMP0_AON_IRQn = 157, /**< Comparator interrupt */ + ACMP0_AON_IRQn = 157, /**< Comparator interrupt */ ADVC_IRQn = 158, /**< ADVC_2.0 Controller Interrupt */ - SGLCD_FRAME_AON_IRQn = 160, /**< Frame Update Interrupt */ - SGLCD_FFAULT_AON_IRQn = 161 /**< Fault Detect Interrupt */ + SLCD_FRAME_AON_IRQn = 160, /**< Frame Update Interrupt */ + SLCD_FFAULT_AON_IRQn = 161 /**< Fault Detect Interrupt */ } IRQn_Type; /*! @@ -174,9 +174,10 @@ typedef enum IRQn { * @} */ /* end of group Cortex_Core_Configuration */ + #ifndef MCXL255_cm33_SERIES #define MCXL255_cm33_SERIES -#endif +#endif /* CPU specific feature definitions */ #include "MCXL255_cm33_features.h" @@ -699,6 +700,8 @@ typedef enum IRQn { /** Array initializer of FREQME peripheral base pointers */ #define FREQME_BASE_PTRS { FREQME0 } #endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { FREQME0_IRQn } /* GLIKEY - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -947,46 +950,46 @@ typedef enum IRQn { /* LPCMP - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xB0086000u) - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE_NS (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0_NS ((LPCMP_Type *)AON__CMP0_BASE_NS) - /** Peripheral CMP0 base address */ - #define CMP0_BASE (0x500B1000u) - /** Peripheral CMP0 base address */ - #define CMP0_BASE_NS (0x400B1000u) - /** Peripheral CMP0 base pointer */ - #define CMP0 ((LPCMP_Type *)CMP0_BASE) - /** Peripheral CMP0 base pointer */ - #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral ACMP0 base address */ + #define ACMP0_BASE (0x500B1000u) + /** Peripheral ACMP0 base address */ + #define ACMP0_BASE_NS (0x400B1000u) + /** Peripheral ACMP0 base pointer */ + #define ACMP0 ((LPCMP_Type *)ACMP0_BASE) + /** Peripheral ACMP0 base pointer */ + #define ACMP0_NS ((LPCMP_Type *)ACMP0_BASE_NS) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xB0086000u) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE_NS (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0_NS ((LPCMP_Type *)AON__ACMP0_BASE_NS) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE, CMP0_BASE } + #define LPCMP_BASE_ADDRS { ACMP0_BASE, AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0, CMP0 } + #define LPCMP_BASE_PTRS { ACMP0, AON__ACMP0 } /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS_NS { AON__CMP0_BASE_NS, CMP0_BASE_NS } + #define LPCMP_BASE_ADDRS_NS { ACMP0_BASE_NS, AON__ACMP0_BASE_NS } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS_NS { AON__CMP0_NS, CMP0_NS } + #define LPCMP_BASE_PTRS_NS { ACMP0_NS, AON__ACMP0_NS } #else - /** Peripheral AON__CMP0 base address */ - #define AON__CMP0_BASE (0xA0086000u) - /** Peripheral AON__CMP0 base pointer */ - #define AON__CMP0 ((LPCMP_Type *)AON__CMP0_BASE) - /** Peripheral CMP0 base address */ - #define CMP0_BASE (0x400B1000u) - /** Peripheral CMP0 base pointer */ - #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral ACMP0 base address */ + #define ACMP0_BASE (0x400B1000u) + /** Peripheral ACMP0 base pointer */ + #define ACMP0 ((LPCMP_Type *)ACMP0_BASE) + /** Peripheral AON__ACMP0 base address */ + #define AON__ACMP0_BASE (0xA0086000u) + /** Peripheral AON__ACMP0 base pointer */ + #define AON__ACMP0 ((LPCMP_Type *)AON__ACMP0_BASE) /** Array initializer of LPCMP peripheral base addresses */ - #define LPCMP_BASE_ADDRS { AON__CMP0_BASE, CMP0_BASE } + #define LPCMP_BASE_ADDRS { ACMP0_BASE, AON__ACMP0_BASE } /** Array initializer of LPCMP peripheral base pointers */ - #define LPCMP_BASE_PTRS { AON__CMP0, CMP0 } + #define LPCMP_BASE_PTRS { ACMP0, AON__ACMP0 } #endif /** Interrupt vectors for the LPCMP peripheral type */ -#define LPCMP_IRQS { NotAvail_IRQn, CMP0_IRQn } +#define LPCMP_IRQS { ACMP0_IRQn, ACMP0_AON_IRQn } /* LPI2C - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1041,7 +1044,7 @@ typedef enum IRQn { #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, AON__LPI2C0 } #endif /** Interrupt vectors for the LPI2C peripheral type */ -#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, NotAvail_IRQn } +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C0_AON_IRQn } /* LPSPI - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) @@ -1261,31 +1264,31 @@ typedef enum IRQn { /* PKC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PKC0__PKC base address */ - #define PKC0__PKC_BASE (0x500D0000u) - /** Peripheral PKC0__PKC base address */ - #define PKC0__PKC_BASE_NS (0x400D0000u) - /** Peripheral PKC0__PKC base pointer */ - #define PKC0__PKC ((PKC_Type *)PKC0__PKC_BASE) - /** Peripheral PKC0__PKC base pointer */ - #define PKC0__PKC_NS ((PKC_Type *)PKC0__PKC_BASE_NS) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x500D0000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x400D0000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS { PKC0__PKC_BASE } + #define PKC_BASE_ADDRS { PKC0_BASE } /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS { PKC0__PKC } + #define PKC_BASE_PTRS { PKC0 } /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS_NS { PKC0__PKC_BASE_NS } + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS_NS { PKC0__PKC_NS } + #define PKC_BASE_PTRS_NS { PKC0_NS } #else - /** Peripheral PKC0__PKC base address */ - #define PKC0__PKC_BASE (0x400D0000u) - /** Peripheral PKC0__PKC base pointer */ - #define PKC0__PKC ((PKC_Type *)PKC0__PKC_BASE) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x400D0000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) /** Array initializer of PKC peripheral base addresses */ - #define PKC_BASE_ADDRS { PKC0__PKC_BASE } + #define PKC_BASE_ADDRS { PKC0_BASE } /** Array initializer of PKC peripheral base pointers */ - #define PKC_BASE_PTRS { PKC0__PKC } + #define PKC_BASE_PTRS { PKC0 } #endif /* PMU - Peripheral instance base addresses */ @@ -1497,41 +1500,41 @@ typedef enum IRQn { /** Array initializer of SGLCD_CONTROL peripheral base pointers */ #define SGLCD_CONTROL_BASE_PTRS { AON__SGLCD0_AON } #endif +/** Interrupt vectors for the SGLCD */ +#define SGLCD_CONTROL_IRQS { SLCD_FRAME_AON_IRQn } -/** Interrupt vectors for the SGLCD_CONTROL peripheral type */ -#define SGLCD_CONTROL_IRQS { SGLCD_FRAME_AON_IRQn } /* SGLCD_FAULT_DETECT - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SGLCD0_MAIN base address */ - #define SGLCD0_MAIN_BASE (0x500C7000u) - /** Peripheral SGLCD0_MAIN base address */ - #define SGLCD0_MAIN_BASE_NS (0x400C7000u) - /** Peripheral SGLCD0_MAIN base pointer */ - #define SGLCD0_MAIN ((SGLCD_FAULT_DETECT_Type *)SGLCD0_MAIN_BASE) - /** Peripheral SGLCD0_MAIN base pointer */ - #define SGLCD0_MAIN_NS ((SGLCD_FAULT_DETECT_Type *)SGLCD0_MAIN_BASE_NS) + /** Peripheral SGLCD_FAULT_DETECT base address */ + #define SGLCD_FAULT_DETECT_BASE (0x500C7000u) + /** Peripheral SGLCD_FAULT_DETECT base address */ + #define SGLCD_FAULT_DETECT_BASE_NS (0x400C7000u) + /** Peripheral SGLCD_FAULT_DETECT base pointer */ + #define SGLCD_FAULT_DETECT ((SGLCD_FAULT_DETECT_Type *)SGLCD_FAULT_DETECT_BASE) + /** Peripheral SGLCD_FAULT_DETECT base pointer */ + #define SGLCD_FAULT_DETECT_NS ((SGLCD_FAULT_DETECT_Type *)SGLCD_FAULT_DETECT_BASE_NS) /** Array initializer of SGLCD_FAULT_DETECT peripheral base addresses */ - #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD0_MAIN_BASE } + #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD_FAULT_DETECT_BASE } /** Array initializer of SGLCD_FAULT_DETECT peripheral base pointers */ - #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD0_MAIN } + #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD_FAULT_DETECT } /** Array initializer of SGLCD_FAULT_DETECT peripheral base addresses */ - #define SGLCD_FAULT_DETECT_BASE_ADDRS_NS { SGLCD0_MAIN_BASE_NS } + #define SGLCD_FAULT_DETECT_BASE_ADDRS_NS { SGLCD_FAULT_DETECT_BASE_NS } /** Array initializer of SGLCD_FAULT_DETECT peripheral base pointers */ - #define SGLCD_FAULT_DETECT_BASE_PTRS_NS { SGLCD0_MAIN_NS } + #define SGLCD_FAULT_DETECT_BASE_PTRS_NS { SGLCD_FAULT_DETECT_NS } #else - /** Peripheral SGLCD0_MAIN base address */ - #define SGLCD0_MAIN_BASE (0x400C7000u) - /** Peripheral SGLCD0_MAIN base pointer */ - #define SGLCD0_MAIN ((SGLCD_FAULT_DETECT_Type *)SGLCD0_MAIN_BASE) + /** Peripheral SGLCD_FAULT_DETECT base address */ + #define SGLCD_FAULT_DETECT_BASE (0x400C7000u) + /** Peripheral SGLCD_FAULT_DETECT base pointer */ + #define SGLCD_FAULT_DETECT ((SGLCD_FAULT_DETECT_Type *)SGLCD_FAULT_DETECT_BASE) /** Array initializer of SGLCD_FAULT_DETECT peripheral base addresses */ - #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD0_MAIN_BASE } + #define SGLCD_FAULT_DETECT_BASE_ADDRS { SGLCD_FAULT_DETECT_BASE } /** Array initializer of SGLCD_FAULT_DETECT peripheral base pointers */ - #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD0_MAIN } + #define SGLCD_FAULT_DETECT_BASE_PTRS { SGLCD_FAULT_DETECT } #endif +/** Interrupt vectors for the SGLCD */ +#define SGLCD_FAULT_DETECT_IRQS { SLCD_FFAULT_AON_IRQn } -/** Interrupt vectors for the SGLCD_FAULT_DETECT peripheral type */ -#define SGLCD_FAULT_DETECT_IRQS { SGLCD_FFAULT_AON_IRQn } /* SMM - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33_features.h index d436d21d3..9e3f12ffc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/MCXL255_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 1.0, 2023-01-09 -** Build: b250422 +** Version: rev. 1.0, 2025-06-13 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -14,8 +14,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -49,9 +49,6 @@ #define FSL_FEATURE_SOC_INPUTMUX_COUNT (2) /* @brief KPP availability on the SoC. */ #define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (1) -#define FSL_FEATURE_LCD_HAS_FAULT_DETECT (1) /* @brief LPADC availability on the SoC. */ #define FSL_FEATURE_SOC_LPADC_COUNT (2) /* @brief LPCMP availability on the SoC. */ @@ -70,8 +67,6 @@ #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) /* @brief PKC availability on the SoC. */ #define FSL_FEATURE_SOC_PKC_COUNT (1) -/* @brief PMU availability on the SoC. */ -#define FSL_FEATURE_SOC_PMU_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (4) /* @brief RTC availability on the SoC. */ @@ -82,6 +77,8 @@ #define FSL_FEATURE_SOC_SYSCON_COUNT (2) /* @brief TMR availability on the SoC. */ #define FSL_FEATURE_SOC_TMR_COUNT (2) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) /* @brief UTICK availability on the SoC. */ #define FSL_FEATURE_SOC_UTICK_COUNT (1) /* @brief WWDT availability on the SoC. */ @@ -89,10 +86,49 @@ /* @brief WUU availability on the SoC. */ #define FSL_FEATURE_SOC_WUU_COUNT (1) +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (0) +/* @brief Has RRCR0 RR_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_CLK_SEL (1) +/* @brief Has RRCR0 RR_TRG_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_TRG_SEL (1) +/* @brief Has RRCR0 RR_SAMPLE_CNT bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_CNT (1) +/* @brief Has RRCR0 RR_SAMPLE_THRESHOLD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR0_RR_SAMPLE_THRESHOLD (1) +/* @brief Has CCR2 INPSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INPSEL (0) +/* @brief Has CCR2 INMSEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_INMSEL (0) +/* @brief Has CCR2 CMP_NPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR2_CMP_NPMD (1) +/* @brief Has DCR DAC_HPMD bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_DCR_DAC_HPMD (1) +/* @brief Has CCR0 LINKEN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_LINKEN (0) +/* @brief Has RRCR2 register. */ +#define FSL_FEATURE_LPCMP_HAS_RRCR2 (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) + /* LPADC module features */ /* @brief FIFO availability on the SoC. */ #define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1) /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ @@ -103,8 +139,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -113,8 +147,6 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ @@ -123,10 +155,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -139,6 +167,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -161,6 +195,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (1) /* AOI module features */ @@ -169,23 +207,6 @@ /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ #define FSL_FEATURE_AOI_EVENT_COUNT (4) -/* LPCMP module features */ - -/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) -/* @brief Has IER RRF_IE bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) -/* @brief Has CSR RRF bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) -/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ -#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) -/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ -#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) -/* @brief Has CCR0 CMP_STOP_EN bitfield. */ -#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) -/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ -#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (1) - /* GPIO module features */ /* @brief Has GPIO attribute checker register (GACR). */ @@ -208,6 +229,8 @@ (((x) == LPI2C0) ? (4) : \ (((x) == LPI2C1) ? (4) : \ (((x) == AON__LPI2C0) ? (16) : (-1)))) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPTMR module features */ @@ -218,11 +241,11 @@ /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) /* @brief Do not has prescaler clock source 0. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) /* @brief Do not has prescaler clock source 1. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) /* @brief Do not has prescaler clock source 2. */ -#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) /* @brief Do not has prescaler clock source 3. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) @@ -258,11 +281,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ - (((x) == LPUART0) ? (4) : \ - (((x) == LPUART1) ? (4) : \ - (((x) == AON__LPUART0) ? (16) : (-1)))) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -295,12 +313,28 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ #define FSL_FEATURE_LPUART_HAS_HDCR (0) /* @brief Has register Timeout. */ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART0) ? (4) : \ + (((x) == LPUART1) ? (4) : \ + (((x) == AON__LPUART0) ? (16) : (-1)))) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* ADVC module features */ + +/* @brief ADVC calibration data address. */ +#define FSL_FEATURE_ADVC_CFG_TABLE_ADDR (0x01100000UL) /* PORT module features */ @@ -332,6 +366,8 @@ #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ #define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Alt function 0 means GPIO (not analog). */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Defines width of PCR[MUX] field. */ @@ -351,10 +387,26 @@ /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) -/* LCD module features */ +/* SLCD module features */ /* @brief LCD registers are split into control and fault detect parts. */ -#define FSL_FEATURE_SGLCD_HAS_FAULT_DETECT (1) +#define FSL_FEATURE_LCD_HAS_FAULT_DETECT (1) +/* @brief (S)LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (1) +/* @brief The SLCD module is designed for low-voltage and low-power operation */ +#define FSL_FEATURE_SLCD_LP_CONTROL (1) +/* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ +#define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) +/* @brief Has fast frame rate (register bit GCR[FFR]). */ +#define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) +/* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ +#define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (1) +/* @brief Has pad safe (register bit GCR[PADSAFE]). */ +#define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) +/* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) +/* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ +#define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) /* SYSCON_AON module features */ @@ -363,14 +415,19 @@ /* @brief Starter register discontinuous. */ #define FSL_FEATURE_SYSCON_AON_STARTER_DISCONTINUOUS (1) +/* TMR module features */ + +/* @brief Has 32-bit width register. */ +#define FSL_FEATURE_TMR_HAS_32BIT_REGISTER (1) + /* CDOG module features */ -/* @brief CDOG Has No Reset */ +/* @brief SOC has no reset driver. */ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) -/* @brief CDOG Use Restart register */ -#define FLS_FEATURE_CDOG_USE_RESTART (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (1) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -505,15 +562,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* TRDC module features */ @@ -582,6 +639,11 @@ /* @brief The number of general purpose interrupts supported by MU. */ #define FSL_FEATURE_MU_GPI_COUNT (20) +/* OSTIMER module features */ + +/* @brief Has binary encoded value in counter register. */ +#define FSL_FEATURE_OSTIMER_HAS_BINARY_ENCODED_COUNTER (1) + /* SYSCON module features */ /* @brief Powerlib API is different with other series devices */ @@ -589,6 +651,29 @@ /* @brief Starter register discontinuous. */ #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* TRNG module features */ + +/* @brief TRNG does not support SCR4L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (1) +/* @brief TRNG does not support SCR5L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (1) +/* @brief TRNG does not support SCR6L. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) +/* @brief TRNG does not support PKRMAX. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (1) +/* @brief TRNG does not support SAMP mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) +/* @brief TRNG does not support ACC. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) +/* @brief TRNG does not support SBLIM. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (1) +/* @brief TRNG supports reset control. */ +#define FSL_FEATURE_TRNG_HAS_RSTCTL (1) +/* @brief TRNG does not support FOR_CLK mode. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1) +/* @brief TRNG has two oscillators. */ +#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) + /* UTICK module features */ /* @brief UTICK does not support power down configure. */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/CMakeLists.txt index a6e52e072..85503eea2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/CMakeLists.txt @@ -19,14 +19,28 @@ if (CONFIG_MCUX_COMPONENT_driver.inputmux_connections) mcux_add_include( INCLUDES . ) endif() -# if (CONFIG_MCUX_COMPONENT_driver.ipmq) -# mcux_add_source( SOURCES fsl_ipmq.c fsl_ipmq.h ) -# mcux_add_include( INCLUDES . ) -# endif() +if (CONFIG_MCUX_COMPONENT_driver.advc) + mcux_component_version(2.0.1) + mcux_add_source( SOURCES fsl_advc.c fsl_advc.h ) + mcux_add_include( INCLUDES . ) + mcux_add_library( + BASE_PATH ${SdkRootDirPath}/${device_root} + CORES cm33 + LIBS "MCX/MCXL/MCXL255/drivers/advc_cm33.lib" + TOOLCHAINS iar armgcc + ) + mcux_add_library( + BASE_PATH ${SdkRootDirPath}/${device_root} + CORES cm0p + LIBS "MCX/MCXL/MCXL255/drivers/advc_cm0p.lib" + TOOLCHAINS iar armgcc + ) +endif() if (CONFIG_MCUX_COMPONENT_driver.power) mcux_add_source( SOURCES fsl_power.c fsl_power.h ) mcux_add_include( INCLUDES . ) + mcux_component_version(2.1.0) endif() if (CONFIG_MCUX_COMPONENT_driver.reset) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_advc.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_advc.c new file mode 100644 index 000000000..f1b5eb8b8 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_advc.c @@ -0,0 +1,303 @@ +/* + * Copyright 2025 NXP + * + * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_advc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.advc" +#endif + +#define ADVC_OPTIMAL_CFG_CLOCK_MASK (0xFFF9UL) + +typedef enum _advc_state +{ + kADVC_NotInitalized = 0U, + kADVC_Initalized = 1U, +} advc_state_t; + +typedef enum +{ + ADVC_STATUS_OK, /*< ADVC returns OK */ + ADVC_STATUS_INIT, /*< ADVC init status */ + ADVC_STATUS_SAFE_DONE_FAILED, /*< ADVC safe was not done */ + ADVC_STATUS_TIMEOUT, /*< ADVC status done condition was not set before timeout */ + ADVC_STATUS_RINGO_MEASURE_FAILED, /*< RINGO measurement failed */ + ADVC_STATUS_FF_MEASURE_FAILED, /*< First fail measurement failed */ + ADVC_STATUS_OPTIMAL_FAILED, /*< ADVC set optimal ended with error */ + ADVC_STATUS_BAD_SIGNATURE, /*< ADVC table value */ + ADVC_STATUS_IS_NOT_ENABLED, /*< when trying to manipulate advc frequencies before it's enabled */ + ADVC_STATUS_PRE_VOLTAGE_REQUEST_FAILED, /*< when pre-voltage request change is reaching timeout */ + ADVC_STATUS_ILLEGAL_OPERATION, /*< When using illegal operation mode in ADVC_ENABLE */ +} ADVC_STATUS_t; + +typedef enum ADVC_MODE +{ + ADVC_MODE_SAFE = 0, + ADVC_MODE_PRODUCTION_TEST = 1, + ADVC_MODE_OPTIMAL = 2, + ADVC_MODE_SW = 3, +} ADVC_MODE_t; + +typedef enum ADVC_FREQUENCY_CODE +{ + ADVC_FREQUENCY_CODE_10MHZ = 0, /**< 10 MHz, from FRO 10MHZ */ + ADVC_FREQUENCY_CODE_5MHZ = 1, /*< 5 MHz, from FRO 10MHZ */ + ADVC_FREQUENCY_CODE_3P3MHZ = 2, /*< 3.3P3MHZ MHz, from FRO 10MHZ */ + ADVC_FREQUENCY_CODE_2P5MHZ = 3, /*< 2.5P3MHZ MHz, from FRO 10MHZ */ + ADVC_FREQUENCY_CODE_2MHZ = 4, /*< 2MHZ MHz, from FRO 2MHZ */ + ADVC_FREQUENCY_CODE_1MHZ = 5, /*< 1MHZ MHz, from FRO 2MHZ */ +} ADVC_FREQUENCY_CODE_t; + +/** + * @brief defines safe_mode_parameters + */ +typedef struct ADVC_SAFE_CONFIG_s +{ + bool should_write_to_dc2dc; /*< should write to dc2dc or not */ + ADVC_FREQUENCY_CODE_t frequency_code; /*< frequency code , @see ADVC_FREQUENCY_CODE_t for details */ +} ADVC_SAFE_CONFIG_t; + +/** + * @brief defines optimal_mode_parameters + */ +typedef struct ADVC_OPTIMAL_CONFIG_s +{ + bool is_sw_mode; // + bool should_write_to_dc2dc; + bool should_use_spare_function; + bool is_external_temperature; + uint32_t clocks_mask; +} ADVC_OPTIMAL_CONFIG_t; + +/** + * @brief defines advc enable mode paratemers to safe/optimal + */ +typedef union +{ + ADVC_SAFE_CONFIG_t advc_safe_config; /*< advc_safe_config @see ADVC_SAFE_CONFIG_t for details */ + ADVC_OPTIMAL_CONFIG_t advc_optimal_config; /*< advc_optimal_config @see ADVC_OPTIMAL_CONFIG_t for details */ +} ADVC_ENABLE_CONFIG_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +extern void ADVC_DRIVER_init(uint32_t table_address); +extern ADVC_STATUS_t ADVC_DRIVER_Enable(ADVC_MODE_t advc_mode, ADVC_ENABLE_CONFIG_t *advc_enable_config, uint8_t *code); +extern void ADVC_DRIVER_Disable(); +extern ADVC_STATUS_t ADVC_DRIVER_convert_frequency_to_code(uint32_t frequency_in_Hz, + ADVC_FREQUENCY_CODE_t *frequency_code); +extern ADVC_STATUS_t ADVC_DRIVER_pre_voltage_change_request(ADVC_FREQUENCY_CODE_t frequency); +extern ADVC_STATUS_t ADVC_DRIVER_post_voltage_change_request(); +extern bool ADVC_DRIVER_is_ADVC_enabled(); +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile advc_state_t g_advcState = kADVC_NotInitalized; + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool ADVC_CheckAONApbClockEnabled(void) +{ + if ((AON__CGU->PER_CLK_EN & CGU_PER_CLK_EN_APB_CLK_MASK) != 0UL) + { + return true; + } + else + { + return false; + } +} + +/*! + * brief Load advc configuration table and initialize ADVC. + */ +#if __CORTEX_M == 33U +void ADVC_Init(void) +{ + bool isAhbClockEnabled = ADVC_CheckAONApbClockEnabled(); + ADVC_DRIVER_init(FSL_FEATURE_ADVC_CFG_TABLE_ADDR); + + if (isAhbClockEnabled) + { + AON__CGU->PER_CLK_EN |= CGU_PER_CLK_EN_APB_CLK_MASK; + } + g_advcState = kADVC_Initalized; +} +#endif /* __CORTEX_M == 33U */ + +/*! + * brief Check if ADVC is initialized. + * + * retval false ADVC is not initialized. + * retval true ADVC is initialized. + */ +bool ADVC_IsInitalized(void) +{ + return (bool)(g_advcState == kADVC_Initalized); +} + +/*! + * brief Enable ADVC + * + * param[in] mode Specify the mode of advc, please refer to advc_mode_t. + * param[out] vddCode The value of VDD. + * + * return The result outcome with enabling ADVC. + */ +advc_result_t ADVC_Enable(advc_mode_t mode, uint8_t *vddCode) +{ + ADVC_ENABLE_CONFIG_t advcEnableConfig; + ADVC_STATUS_t status; + + bool isAhbClockEnabled = ADVC_CheckAONApbClockEnabled(); + + if (mode == kADVC_ModeSafe) + { + advcEnableConfig.advc_safe_config.frequency_code = ADVC_FREQUENCY_CODE_10MHZ; + advcEnableConfig.advc_safe_config.should_write_to_dc2dc = true; + } + else if (mode == kADVC_ModeOptimal) + { + advcEnableConfig.advc_optimal_config.clocks_mask = ADVC_OPTIMAL_CFG_CLOCK_MASK; + advcEnableConfig.advc_optimal_config.is_external_temperature = false; + advcEnableConfig.advc_optimal_config.is_sw_mode = false; + advcEnableConfig.advc_optimal_config.should_use_spare_function = true; + advcEnableConfig.advc_optimal_config.should_write_to_dc2dc = true; + } + else + { + /* To avoid violation of MISRA rule. */ + } + + if (vddCode == NULL) + { + uint8_t tmp8 = 0U; + status = ADVC_DRIVER_Enable((ADVC_MODE_t)mode, &advcEnableConfig, &tmp8); + (void)tmp8; + } + else + { + status = ADVC_DRIVER_Enable((ADVC_MODE_t)mode, &advcEnableConfig, vddCode); + } + + if (isAhbClockEnabled) + { + AON__CGU->PER_CLK_EN |= CGU_PER_CLK_EN_APB_CLK_MASK; + } + + return (advc_result_t)status; +} + +/*! + * brief Check if ADVC is enabled. + * + * retval false ADVC is not enabled. + * retval true ADVC is enabled. + */ +bool ADVC_IsEnabled(void) +{ + bool isAhbClockEnabled = ADVC_CheckAONApbClockEnabled(); + bool ret = false; + + ret = ADVC_DRIVER_is_ADVC_enabled(); + + if (isAhbClockEnabled) + { + AON__CGU->PER_CLK_EN |= CGU_PER_CLK_EN_APB_CLK_MASK; + } + return ret; +} + +/*! + * brief Disable ADVC. + */ +void ADVC_Disable(void) +{ + bool isAhbClockEnabled = ADVC_CheckAONApbClockEnabled(); + + ADVC_DRIVER_Disable(); + + if (isAhbClockEnabled) + { + AON__CGU->PER_CLK_EN |= CGU_PER_CLK_EN_APB_CLK_MASK; + } +} + +/*! + * brief Check if ADVC is disabled. + * + * retval true ADVC is not disabled. + * retval false ADVC is enabled. + */ +bool ADVC_IsDisabled(void) +{ + bool isAhbClockEnabled = ADVC_CheckAONApbClockEnabled(); + bool ret = false; + + ret = !(ADVC_DRIVER_is_ADVC_enabled()); + + if (isAhbClockEnabled) + { + AON__CGU->PER_CLK_EN |= CGU_PER_CLK_EN_APB_CLK_MASK; + } + return ret; +} + +/*! + * brief Request to change frequency. + * + * note This should be done every time we want to change frequency of any ADVC related clock. + * + * param aonCpuFreq The frequency of AON CPU, only 10MHz, 5MHz, 3.3MHz, 2.5MHz, 2MHz, 1MHz are allowed. + * + * return The result outcome with requesting to change frequency. + */ +advc_result_t ADVC_PreVoltageChangeRequest(uint32_t aonCpuFreq) +{ + ADVC_FREQUENCY_CODE_t advcFreqCode; + ADVC_STATUS_t status; + + bool isAhbClockEnabled = ADVC_CheckAONApbClockEnabled(); + status = ADVC_DRIVER_convert_frequency_to_code(aonCpuFreq, &advcFreqCode); + + if (status == ADVC_STATUS_OK) + { + status = ADVC_DRIVER_pre_voltage_change_request(advcFreqCode); + } + + if (isAhbClockEnabled) + { + AON__CGU->PER_CLK_EN |= CGU_PER_CLK_EN_APB_CLK_MASK; + } + return (advc_result_t)status; +} + +/*! + * brief Move back to optimal after changing any ADVC related clock frequency. + * + * return The observed result following the post-frequency change. + */ +advc_result_t ADVC_PostVoltageChangeRequest(void) +{ + ADVC_STATUS_t status; + bool isAhbClockEnabled = ADVC_CheckAONApbClockEnabled(); + + status = ADVC_DRIVER_post_voltage_change_request(); + + if (isAhbClockEnabled) + { + AON__CGU->PER_CLK_EN |= CGU_PER_CLK_EN_APB_CLK_MASK; + } + + return (advc_result_t)status; +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_advc.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_advc.h new file mode 100644 index 000000000..8e6c951cb --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_advc.h @@ -0,0 +1,137 @@ +/* + * Copyright 2025 NXP + * + * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ADVC_H +#define _FSL_ADVC_H + +#include "fsl_common.h" + +/*! + * @addtogroup ADVC + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief advc driver version 2.0.1. */ +#define FSL_ADVC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief The enumeration of ADVC operation result. + * + */ +typedef enum _advc_result +{ + kADVC_Stat_Ok = 0U, /*!< ADVC Run Well. */ + kADVC_Stat_Init = 1U, /*!< ADVC is initialized. */ + kADVC_Stat_SafeDoneFailed = 2U, /*!< Fail to set ADVC as safe mode. */ + kADVC_Stat_Timeout = 3U, /*!< ADVC status done condition was not set before timeout */ + kADVC_Stat_RingoMeasureFailed = 4U, /*!< Fail to measure ringo. */ + kADVC_Stat_FFMeasureFailed = 5U, /*!< First fail measurement failed. */ + kADVC_Stat_OptimalFailed = 6U, /*!< ADVC set optimal ended with error. */ + kADVC_Stat_BadSignature = 7U, /*!< Wrong ADVC table. */ + kADVC_Stat_NotEnabled = 8U, /*!< when trying to manipulate advc frequencies before it's enabled. */ + kADVC_Stat_PreVoltageReqestFailed = 9U, /*!< when pre-voltage request change is reaching timeout. */ + kADVC_Stat_IllegalOperation = 10U, /*!< When using illegal operation mode in ADVC_ENABLE. */ +} advc_result_t; + +/*! + * @brief The enumeration of ADVC mode. + * + */ +typedef enum _advc_mode +{ + kADVC_ModeSafe = 0U, /*!< Set ADVC work as safe mode. */ + kADVC_ModeOptimal = 2U, /*!< Set ADVC work as optimal mode. */ +} advc_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif +#if __CORTEX_M == 33U +/*! + * @brief Load advc configuration table and initialize ADVC. + */ +void ADVC_Init(void); +#endif /* __CORTEX_M == 33U */ + +/*! + * @brief Check if ADVC is initialized. + * + * @retval false ADVC is not initialized. + * @retval true ADVC is initialized. + */ +bool ADVC_IsInitialized(void); + +/*! + * @brief Enable ADVC + * + * @param[in] mode Specify the mode of advc, please refer to @ref advc_mode_t. + * @param[out] vddCode The value of VDD_AON, NULL means do not care voltage of VDD_AON. + * + * @return The result outcome with enabling ADVC. + */ +advc_result_t ADVC_Enable(advc_mode_t mode, uint8_t *vddCode); + +/*! + * @brief Check if ADVC is enabled. + * + * @retval false ADVC is not enabled. + * @retval true ADVC is enabled. + */ +bool ADVC_IsEnabled(void); + +/*! + * @brief Disable ADVC. + */ +void ADVC_Disable(void); + +/*! + * @brief Check if ADVC is disabled. + * + * @retval true ADVC is not disabled. + * @retval false ADVC is enabled. + */ +bool ADVC_IsDisabled(void); + +/*! + * @brief Request to change frequency. + * + * @note This should be done every time we want to change frequency of any ADVC related clock. + * @note Pre Voltage request should be called before any clock change which is derived from CGU. + * The paramter we pass is the the future cpu frequency, since we move to safe voltage according to that. + * + * @param aonCpuFreq The frequency of AON CPU, only 10MHz, 5MHz, 3.3MHz, 2.5MHz, 2MHz, 1MHz are allowed. + * + * @return The result outcome with requesting to change frequency. + */ +advc_result_t ADVC_PreVoltageChangeRequest(uint32_t aonCpuFreq); + +/*! + * @brief Move back to optimal after changing any ADVC related clock frequency. + * + * @return The observed result following the post-frequency change. + */ +advc_result_t ADVC_PostVoltageChangeRequest(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* __FSL_ADVC_H */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_clock.c index e2ed1cbaa..594683e81 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_clock.c @@ -23,6 +23,15 @@ #define FSL_COMPONENT_ID "platform.drivers.clock" #endif +typedef enum _clock_aon_chg +{ + kClockAonChg_auxClk, /* RTC/AUX clk was changed or disabled, pass frequency or 0 for disable */ + kClockAonChg_Fro, /* FRO10M_2M changed, pass 10M/2M/0 */ + kClockAonChg_clkSel, /* ROOT_CLK_SEL_MUX changed, pass mux value */ + kClockAonChg_cpuClkDiv, /* AON_CPU_CLK_DIV changed, pass divisor(>1) or 0 when AON_CPU_CLK is disabled */ + +}clock_aon_chg_t; + /******************************************************************************* * Variables ******************************************************************************/ @@ -37,6 +46,10 @@ volatile uint32_t g_xtal32Freq; static uint32_t CLOCK_GetFroAonFreq(void); /* Get RTC OSC Clk */ static uint32_t CLOCK_GetRtcOscFreq(void); +/* Get AON_AUX_CLK freq*/ +static uint32_t CLOCK_GetAonAuxFreq(void); +/* Get AON ROOT AUX freq */ +static uint32_t CLOCK_GetAonRootAuxFreq(void); #if __CORTEX_M == (33U) /* Building on the main core */ /* Get Main_Clk */ @@ -70,6 +83,101 @@ static inline bool CLOCK_IsDivHalt(uint32_t div_value) * Code ******************************************************************************/ +static void ADVC_PreChg(const clock_aon_chg_t change, uint32_t newValue) +{ +#if defined(ADVC_DRIVER_USED) & ADVC_DRIVER_USED + if(ADVC_IsEnabled()) + { + uint32_t freq = 0U; + uint32_t root_clk_sel; + + if(change == kClockAonChg_clkSel) + { + root_clk_sel = newValue; + } + else + { + root_clk_sel = (AON__CGU->CLK_CONFIG & + CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) >> + CGU_CLK_CONFIG_ROOT_CLK_SEL_SHIFT; + } + + if(root_clk_sel == 3U) + { /* Using ROOT_AUX_CLK */ + + if(change == kClockAonChg_auxClk) + { + freq = newValue; + } + else + { + freq = CLOCK_GetAonRootAuxFreq(); + } + } + else + { /* Using FRO */ + + const uint32_t div = 1U << root_clk_sel; + + if(change == kClockAonChg_Fro) + { + freq = newValue; + } + else + { + freq = CLOCK_GetFroAonFreq(); + } + + freq /= div; + } + + if(change == kClockAonChg_cpuClkDiv) + { + if(0U == newValue) + { + freq = 0U; /* disable */ + } + else + { + freq /= newValue; + } + } + else + { + if(AON__CGU->CLOCK_DIV & CGU_CLOCK_DIV_CLK_DIV_EN_MASK) + { + const uint32_t aon_cpu_clk_div = (AON__CGU->CLOCK_DIV & + CGU_CLOCK_DIV_AON_CPU_CLK_DIV_MASK) >> + CGU_CLOCK_DIV_AON_CPU_CLK_DIV_SHIFT; + + freq /= aon_cpu_clk_div + 1U; + } + else + { + freq = 0U; /* AON_CPU_CLK is Disabled*/ + } + } + + ADVC_PreVoltageChangeRequest(freq); + /* ADVC functions always diables APB clk, so enable it again. */ + CLOCK_EnableClock(kCLOCK_GateAonAPB); + + } /* ADVC is enabled */ +#endif +} + +static void ADVC_PostChg(void) +{ +#if defined(ADVC_DRIVER_USED) & ADVC_DRIVER_USED + if(ADVC_IsEnabled()) + { + ADVC_PostVoltageChangeRequest(); + /* ADVC functions always diables APB clk, so enable it again. */ + CLOCK_EnableClock(kCLOCK_GateAonAPB); + } +#endif +} + /* Clock Selection for IP */ /** * brief Configure the clock selection muxes. @@ -83,7 +191,39 @@ void CLOCK_AttachClk(clock_attach_id_t connection) if (kNONE_to_NONE != connection) { + uint8_t run_advc_postchg = 1U; + + switch(connection) + { + case kFROdiv1_to_AON_CPU: + ADVC_PreChg(kClockAonChg_clkSel, 0U); + break; + case kFROdiv2_to_AON_CPU: + ADVC_PreChg(kClockAonChg_clkSel, 1U); + break; + case kFROdiv4_to_AON_CPU: + ADVC_PreChg(kClockAonChg_clkSel, 2U); + break; + case kROOT_AUX_to_AON_CPU: + ADVC_PreChg(kClockAonChg_clkSel, 3U); + break; + case kXTAL32K_to_AON_ROOT_AUX: + ADVC_PreChg(kClockAonChg_auxClk, CLOCK_GetRtcOscFreq()); + break; + case kAUX_to_AON_ROOT_AUX: + ADVC_PreChg(kClockAonChg_auxClk, CLOCK_GetAonAuxFreq()); + break; + default: + run_advc_postchg = 0U; + break; + } + CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); + + if(run_advc_postchg) + { + ADVC_PostChg(); + } } } @@ -213,32 +353,32 @@ void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value) { /* AON ACMP CLK 0*/ if(value==0) { - AON__CGU->ACMP_CLK_DIV &= ~(CGU_ACMP_CLK_DIV_ACMP0_CLK_EN_MASK); - AON__CGU->ACMP_CLK_DIV &= ~(CGU_ACMP_CLK_DIV_ACMP_CLK0_DIV_EN_MASK); + AON__CGU->ACMP_CLK &= ~(CGU_ACMP_CLK_ACMP0_CLK_EN_MASK); + AON__CGU->ACMP_CLK &= ~(CGU_ACMP_CLK_ACMP_CLK0_DIV_EN_MASK); } else { - AON__CGU->ACMP_CLK_DIV &= ~(CGU_ACMP_CLK_DIV_AON_ACMP_CLK0_DIV_MASK); - AON__CGU->ACMP_CLK_DIV |= (value-1U) << CGU_ACMP_CLK_DIV_AON_ACMP_CLK0_DIV_SHIFT; + AON__CGU->ACMP_CLK &= ~(CGU_ACMP_CLK_AON_ACMP_CLK0_DIV_MASK); + AON__CGU->ACMP_CLK |= (value-1U) << CGU_ACMP_CLK_AON_ACMP_CLK0_DIV_SHIFT; - AON__CGU->ACMP_CLK_DIV |= CGU_ACMP_CLK_DIV_ACMP_CLK0_DIV_EN_MASK; - AON__CGU->ACMP_CLK_DIV |= CGU_ACMP_CLK_DIV_ACMP0_CLK_EN_MASK; + AON__CGU->ACMP_CLK |= CGU_ACMP_CLK_ACMP_CLK0_DIV_EN_MASK; + AON__CGU->ACMP_CLK |= CGU_ACMP_CLK_ACMP0_CLK_EN_MASK; } } else if(div_name == 0x411U) { /* AON ACMP CLK 1*/ if(value==0) { - AON__CGU->ACMP_CLK_DIV &= ~(CGU_ACMP_CLK_DIV_ACMP1_CLK_EN_MASK); - AON__CGU->ACMP_CLK_DIV &= ~(CGU_ACMP_CLK_DIV_ACMP_CLK1_DIV_EN_MASK); + AON__CGU->ACMP_CLK &= ~(CGU_ACMP_CLK_ACMP1_CLK_EN_MASK); + AON__CGU->ACMP_CLK &= ~(CGU_ACMP_CLK_ACMP_CLK1_DIV_EN_MASK); } else { - AON__CGU->ACMP_CLK_DIV &= ~(CGU_ACMP_CLK_DIV_AON_ACMP_CLK1_DIV_MASK); - AON__CGU->ACMP_CLK_DIV |= (value-1U) << CGU_ACMP_CLK_DIV_AON_ACMP_CLK1_DIV_SHIFT; + AON__CGU->ACMP_CLK &= ~(CGU_ACMP_CLK_AON_ACMP_CLK1_DIV_MASK); + AON__CGU->ACMP_CLK |= (value-1U) << CGU_ACMP_CLK_AON_ACMP_CLK1_DIV_SHIFT; - AON__CGU->ACMP_CLK_DIV |= CGU_ACMP_CLK_DIV_ACMP_CLK1_DIV_EN_MASK; - AON__CGU->ACMP_CLK_DIV |= CGU_ACMP_CLK_DIV_ACMP1_CLK_EN_MASK; + AON__CGU->ACMP_CLK |= CGU_ACMP_CLK_ACMP_CLK1_DIV_EN_MASK; + AON__CGU->ACMP_CLK |= CGU_ACMP_CLK_ACMP1_CLK_EN_MASK; } } @@ -248,17 +388,29 @@ void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value) const uint32_t div_shift = 3U*(en_shift+1U); uint32_t reg_val = AON__CGU->CLOCK_DIV; - assert((value <= 8U) && (value > 0U)); + assert(value <= 8U); reg_val &= ~((7U << div_shift) | (1U << en_shift)); - reg_val |= (value - 1U) << div_shift; + if(value >= 1U ) { + reg_val |= (value - 1U) << div_shift; + /* enable divider */ reg_val |= 1U << en_shift; } - - AON__CGU->CLOCK_DIV = reg_val; + + if(div_name == kCLOCK_DIVAonCPU) + { /* Changing AON CPU clock - inform ADVC: */ + + ADVC_PreChg(kClockAonChg_cpuClkDiv, value); + AON__CGU->CLOCK_DIV = reg_val; + ADVC_PostChg(); + } + else + { + AON__CGU->CLOCK_DIV = reg_val; + } } } #if __CORTEX_M == (33U) /* Building on the main core */ @@ -306,31 +458,31 @@ uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name) { /* AON clk*/ if(div_name == 0x410U) { /* AON ACMP CLK 0*/ - uint32_t reg_val = AON__CGU->ACMP_CLK_DIV; - if((!(reg_val & CGU_ACMP_CLK_DIV_ACMP0_CLK_EN_MASK)) || - (!(reg_val & CGU_ACMP_CLK_DIV_ACMP_CLK0_DIV_EN_MASK))) + uint32_t reg_val = AON__CGU->ACMP_CLK; + if((!(reg_val & CGU_ACMP_CLK_ACMP0_CLK_EN_MASK)) || + (!(reg_val & CGU_ACMP_CLK_ACMP_CLK0_DIV_EN_MASK))) { return 0; /* Not enabled clk or div*/ } else { - reg_val &= CGU_ACMP_CLK_DIV_AON_ACMP_CLK0_DIV_MASK; - reg_val >>= CGU_ACMP_CLK_DIV_AON_ACMP_CLK0_DIV_SHIFT; + reg_val &= CGU_ACMP_CLK_AON_ACMP_CLK0_DIV_MASK; + reg_val >>= CGU_ACMP_CLK_AON_ACMP_CLK0_DIV_SHIFT; return reg_val + 1U; } } else if(div_name == 0x411U) { /* AON ACMP CLK 1*/ - uint32_t reg_val = AON__CGU->ACMP_CLK_DIV; - if((!(reg_val & CGU_ACMP_CLK_DIV_ACMP1_CLK_EN_MASK)) || - (!(reg_val & CGU_ACMP_CLK_DIV_ACMP_CLK1_DIV_EN_MASK))) + uint32_t reg_val = AON__CGU->ACMP_CLK; + if((!(reg_val & CGU_ACMP_CLK_ACMP1_CLK_EN_MASK)) || + (!(reg_val & CGU_ACMP_CLK_ACMP_CLK1_DIV_EN_MASK))) { return 0; /* Not enabled clk or div*/ } else { - reg_val &= CGU_ACMP_CLK_DIV_AON_ACMP_CLK1_DIV_MASK; - reg_val >>= CGU_ACMP_CLK_DIV_AON_ACMP_CLK1_DIV_SHIFT; + reg_val &= CGU_ACMP_CLK_AON_ACMP_CLK1_DIV_MASK; + reg_val >>= CGU_ACMP_CLK_AON_ACMP_CLK1_DIV_SHIFT; return reg_val + 1U; } } @@ -381,11 +533,11 @@ void CLOCK_HaltClockDiv(clock_div_name_t div_name) { /* AON clk*/ if(div_name == 0x410U) { /* AON ACMP CLK 0*/ - AON__CGU->ACMP_CLK_DIV &= ~(CGU_ACMP_CLK_DIV_ACMP_CLK0_DIV_EN_MASK); + AON__CGU->ACMP_CLK &= ~(CGU_ACMP_CLK_ACMP_CLK0_DIV_EN_MASK); } else if(div_name == 0x411U) { /* AON ACMP CLK 1*/ - AON__CGU->ACMP_CLK_DIV &= ~(CGU_ACMP_CLK_DIV_ACMP_CLK1_DIV_EN_MASK); + AON__CGU->ACMP_CLK &= ~(CGU_ACMP_CLK_ACMP_CLK1_DIV_EN_MASK); } else { /* The rest of AON */ @@ -412,6 +564,8 @@ void CLOCK_HaltClockDiv(clock_div_name_t div_name) /* Initialize the FROHF to given frequency (10M, 2M) */ status_t CLOCK_SetupFROAonClocking(uint32_t iFreq) { + ADVC_PreChg(kClockAonChg_Fro, iFreq); + switch(iFreq) { case 10000000U: @@ -428,9 +582,11 @@ status_t CLOCK_SetupFROAonClocking(uint32_t iFreq) AON__CGU->CLK_CONFIG &= ~(1U << CGU_CLK_CONFIG_FRO10M_EN_SHIFT); break; default: + ADVC_PostChg(); return kStatus_Fail; } - + + ADVC_PostChg(); return (status_t)kStatus_Success; } @@ -503,6 +659,9 @@ status_t CLOCK_SetupFRO12MClocking(void) SCG0->SIRCCSR |= SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK; /* Enable FRO12M clock for Flash use */ SCG0->SIRCCSR |= SCG_SIRCCSR_SIRC_CLK_FLASH_EN_MASK; + + /* Enable FROM12M in deep sleep */ + SCG0->SIRCCSR |= SCG_SIRCCSR_SIRCSTEN_MASK; /* Lock SIRCCSR */ SCG0->SIRCCSR |= SCG_SIRCCSR_LK_MASK; @@ -636,7 +795,7 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) break; #endif /* Building on the main core */ case kCLOCK_Fro16k: /* AON PAC and SMM clock. */ - freq = 16000U; + freq = 16384U; break; case kCLOKC_FroAON: /* AON functional clock. this is wrong add kCLOKC_FroAON */ freq = CLOCK_GetFroAonFreq(); @@ -656,7 +815,7 @@ static uint32_t CLOCK_GetAonRootAuxFreq(void) { if(AON__CGU->CLK_CONFIG & CGU_CLK_CONFIG_ROOT_AUX_CLK_SEL_MASK) { - freq = 1U; /* FIXME how to get aon_aux_clk freq?*/ + freq = 32768U; /* FIXME how to get aon_aux_clk freq?*/ } else { @@ -783,7 +942,7 @@ static uint32_t CLOCK_GetFroHfFreq(void) #endif /* Building on the main core */ /*! - * @brief Gets the SCG RTC OSC clock frequency. + * @brief Gets the RTC OSC clock frequency. * * @return Clock frequency; If the clock is invalid, returns 0. */ @@ -803,6 +962,54 @@ uint32_t CLOCK_GetRtcOscFreq(void) } } +/*! + * @brief Gets the AON_AUX_CLK frequency. + * + * @return Clock frequency; + */ +uint32_t CLOCK_GetAonAuxFreq(void) +{ + return 32768U; /* FIXME */ +} + + +/*! brief Return Frequency of the AON core + * return Frequency of the core + */ +uint32_t CLOCK_GetAonCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + if(AON__CGU->CLOCK_DIV & CGU_CLOCK_DIV_CLK_DIV_EN_MASK) + { + const uint32_t sel = (AON__CGU->CLK_CONFIG & + CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) >> + CGU_CLK_CONFIG_ROOT_CLK_SEL_SHIFT; + const uint32_t div = (AON__CGU->CLOCK_DIV & + CGU_CLOCK_DIV_AON_CPU_CLK_DIV_MASK) >> + CGU_CLOCK_DIV_AON_CPU_CLK_DIV_SHIFT; + + switch(sel) + { + case 0U: + freq = CLOCK_GetAonFroFreq(); + break; + case 1U: + freq = CLOCK_GetAonFroFreq() / 2U; + break; + case 2U: + freq = CLOCK_GetAonFroFreq() / 4U; + break; + case 3U: + freq = CLOCK_GetAonRootAuxFreq(); + break; + } + + freq /= div + 1U; + } + return freq; +} + #if __CORTEX_M == (33U) /* Building on the main core */ /*! @@ -910,7 +1117,7 @@ uint32_t CLOCK_GetMainClk(void) return freq; } -/*! brief Return Frequency of core +/*! brief Return Frequency of the main core * return Frequency of the core */ uint32_t CLOCK_GetCoreSysClkFreq(void) @@ -1350,11 +1557,11 @@ uint32_t CLOCK_GetSystickClkFreq(void) */ uint32_t CLOCK_GetFroAonFreq(void) { - if(CGU_CLK_CONFIG_FRO10M_EN(AON__CGU->CLK_CONFIG) == 0U) + if((AON__CGU->CLK_CONFIG & CGU_CLK_CONFIG_FRO10M_EN_MASK) == 0U) { return 0U; } - else if(CGU_CLK_CONFIG_SEL_MODE(AON__CGU->CLK_CONFIG)) + else if(!(AON__CGU->CLK_CONFIG & CGU_CLK_CONFIG_SEL_MODE_MASK)) { return 10000000U; } @@ -1417,72 +1624,6 @@ status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config) } #endif /* Building on the main core */ -/** - * @brief Sets AON FRO 10M or 2M trim. - * @param is_fro2m : 0 for FRO10M, 1 for FRO2M - * @param config : trim value - */ -void CLOCK_AON_FRO_Trim_Set(uint8_t is_fro2m, aon_fro_trim_config_t config) -{ - volatile uint32_t *reg_config = (is_fro2m) ? - &AON__CGU->FRO2M_CONFIG : - &AON__CGU->FRO10M_CONFIG; - - volatile uint32_t *reg_trim = (is_fro2m) ? - &AON__CGU->FRO2M_TRIM : - &AON__CGU->FRO10M_TRIM; - uint32_t val; - assert(config.fs_bp <= 7U); - assert(config.fs_vcco <= 3U); - assert(config.tf <= 7U); - - assert(config.cltrim <= 63U); - assert(config.ccotrim <= 63U); - - - val = *reg_trim; - val &= ~( CGU_FRO10M_TRIM_TRIM_FVCH_LV_MASK | CGU_FRO10M_TRIM_TRIM_TC_LV_MASK ); - val |= CGU_FRO10M_TRIM_TRIM_FVCH_LV((config.fs_vcco << 2U)|config.fs_bp); - val |= CGU_FRO10M_CONFIG_TRIM_CCO_LV(config.tf); - *reg_trim = val; - - val = *reg_config; - val &= ~( CGU_FRO10M_CONFIG_TRIM_CLK_LV_MASK | CGU_FRO10M_CONFIG_TRIM_CCO_LV_MASK ); - val |= CGU_FRO10M_CONFIG_TRIM_CLK_LV(config.cltrim); /* fine */ - val |= CGU_FRO10M_CONFIG_TRIM_CCO_LV(config.ccotrim); /* coarse */ - *reg_config = val; - -} - -/** - * @brief Reads AON FRO 10M or 2M trim values. - * @param is_fro2m : 0 for FRO10M, 1 for FRO2M - * @param config : ptr to aon_fro_trim_config_t struct. - */ -void CLOCK_AON_FRO_Trim_Get(uint8_t is_fro2m, aon_fro_trim_config_t * config) -{ - volatile uint32_t *reg_config = (is_fro2m) ? - &AON__CGU->FRO2M_CONFIG : - &AON__CGU->FRO10M_CONFIG; - - volatile uint32_t *reg_trim = (is_fro2m) ? - &AON__CGU->FRO2M_TRIM : - &AON__CGU->FRO10M_TRIM; - uint32_t val; - assert(config); - - val = *reg_trim; - config->fs_vcco = (val >> (CGU_FRO10M_TRIM_TRIM_FVCH_LV_SHIFT + 2U)) & 3U; - config->fs_bp = (val >> CGU_FRO10M_TRIM_TRIM_FVCH_LV_SHIFT) & 7U; - config->tf = (val >> CGU_FRO10M_TRIM_TRIM_TC_LV_SHIFT) & 7U; - - val = *reg_config; - - /* fine */ - config->cltrim = (val & CGU_FRO10M_CONFIG_TRIM_CLK_LV_MASK) >> CGU_FRO10M_CONFIG_TRIM_CLK_LV_SHIFT; - /* coarse */ - config->ccotrim = (val & CGU_FRO10M_CONFIG_TRIM_CCO_LV_MASK) >> CGU_FRO10M_CONFIG_TRIM_CCO_LV_SHIFT; -} #if __CORTEX_M == (33U) /* Building on the main core */ @@ -1517,3 +1658,48 @@ void CLOCK_EnableOstimer32kClock(void) return; } #endif /* Building on the main core */ + +#if __CORTEX_M == (33U) /* Building on the main core */ +/*! + * @brief Set flash wait state. + * + * This function sets the flash wait state. Valid states are only 0-15. + * + * @param state Flash wait state (0-15) + */ +void CLOCK_SetFlashWaitState(uint8_t state) +{ + assert(state <= 15); + FMU0->FCTRL = (FMU0->FCTRL & ~FMU_FCTRL_RWSC_MASK) | (state << FMU_FCTRL_RWSC_SHIFT); +} + +/*! + * @brief Set flash wait state based on frequency. + * + * This function sets the flash wait state based on frequency. + * + * @param freq Core frequency. + */ +void CLOCK_SetFlashWaitStateBasedOnFreq(uint32_t freq) +{ + if (freq <= 48000000U) { + CLOCK_SetFlashWaitState(0x1U); + } + else if (freq <= 96000000U) + { + CLOCK_SetFlashWaitState(0x2U); + } +} + +/*! + * @brief Get flash wait state. + * + * This function returns flash wait state.ň + * + * @return Returns flash wait state. + */ +uint8_t CLOCK_GetFlashWaitState() +{ + return (FMU0->FCTRL & FMU_FCTRL_RWSC_MASK) >> FMU_FCTRL_RWSC_SHIFT; +} +#endif /* Building on the main core */ \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_clock.h index 2fa3ab8bd..bf9768401 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_clock.h @@ -10,6 +10,10 @@ #include "fsl_common.h" +#if defined(ADVC_DRIVER_USED) & ADVC_DRIVER_USED +#include "fsl_advc.h" +#endif + /*! @addtogroup clock */ /*! @{ */ @@ -80,7 +84,6 @@ typedef enum _clock_ip_name #if __CORTEX_M == (33U) /* Building on the main core */ /* Check syscon mrcc reg, in RM */ - kCLOCK_InputMux = (0xFFFFFFF0U), /*!< Clock gate name: INPUTMUX0 + AON_INPUTMUX1 */ kCLOCK_GateINPUTMUX0 = (0x00U | (0U)), /*!< Clock gate name: INPUTMUX0 */ kCLOCK_GateCTIMER0 = (0x00U | (1U)), /*!< Clock gate name: CTIMER0 */ kCLOCK_GateCTIMER1 = (0x00U | (2U)), /*!< Clock gate name: CTIMER1 */ @@ -100,7 +103,7 @@ typedef enum _clock_ip_name kCLOCK_GateLPUART0 = (0x00U | (18U)), /*!< Clock gate name: LPUART0 */ kCLOCK_GateADC0 = (0x00U | (19U)), /*!< Clock gate name: ADC0 */ kCLOCK_GateATX0 = (0x00U | (20U)), /*!< Clock gate name: ATX0 */ - kCLOCK_GateCMP0 = (0x00U | (21U)), /*!< Clock gate name: CMP0 */ + kCLOCK_GateACMP0 = (0x00U | (21U)), /*!< Clock gate name: ACMP0 */ kCLOCK_GateDMA1 = (0x00U | (22U)), /*!< Clock gate name: DMA1 */ kCLOCK_GateSRAMA0A1 = (0x00U | (23U)), /*!< Clock gate name: SRAMA0A1 */ kCLOCK_GateGPIO1 = (0x00U | (24U)), /*!< Clock gate name: GPIO1 */ @@ -117,13 +120,11 @@ typedef enum _clock_ip_name kCLOCK_GatePORT2 = ((0x4U << 16U) | (0x10U << 8U) | (2U)), /*!< Clock gate name: PORT2 */ kCLOCK_GatePORT3 = ((0x4U << 16U) | (0x10U << 8U) | (3U)), /*!< Clock gate name: PORT3 */ kCLOCK_GateROMCP = ((0x4U << 16U) | (0x10U << 8U) | (4U)), /*!< Clock gate name: ROMCP */ - kCLOCK_GateSGIO0 = ((0x4U << 16U) | (0x10U << 8U) | (5U)), /*!< Clock gate name: SGIO0 */ + kCLOCK_GateSGI0 = ((0x4U << 16U) | (0x10U << 8U) | (5U)), /*!< Clock gate name: SGI0 */ kCLOCK_GateSGLCD = ((0x4U << 16U) | (0x10U << 8U) | (6U)), /*!< Clock gate name: SGLCD */ kCLOCK_GateTCU = ((0x4U << 16U) | (0x10U << 8U) | (7U)), /*!< Clock gate name: TCU */ kCLOCK_GateTRNG0 = ((0x4U << 16U) | (0x10U << 8U) | (8U)), /*!< Clock gate name: TRNG0 */ kCLOCK_GateUDF0 = ((0x4U << 16U) | (0x10U << 8U) | (9U)), /*!< Clock gate name: UDF0 */ -#else - kCLOCK_InputMux = ((1U<<24U) | (16U)), /*!< Clock gate name: AON INPUTMUX (only)*/ #endif /* Building on the main core */ /* Check AON CGU PER_CLK_EN in RM */ @@ -138,10 +139,10 @@ typedef enum _clock_ip_name kCLOCK_GateAonKPP = ((1U<<24U) | (10U)), /*!< Clock gate name: AON KPP */ kCLOCK_GateAonLPADC = ((1U<<24U) | (11U)), /*!< Clock gate name: AON LPADC */ kCLOCK_GateAonSYS = ((1U<<24U) | (12U)), /*!< Clock gate name: AON SYS (tick) */ - kCLOCK_GateAonCMP0 = ((1U<<24U) | (13U)), /*!< Clock gate name: AON comparator */ + kCLOCK_GateAonACMP0 = ((1U<<24U) | (13U)), /*!< Clock gate name: AON comparator */ kCLOCK_GateAonLCD = ((1U<<24U) | (14U)), /*!< Clock gate name: AON LCD */ kCLOCK_GateAonAVDC2P0 = ((1U<<24U) | (15U)), /*!< Clock gate name: AON AVDC2P0 */ - kCLOCK_GateAonINPUTMUX1 = ((1U<<24U) | (16U)), /*!< Clock gate name: AON INPUTMUX */ + kCLOCK_GateAonINPUTMUX1 = ((1U<<24U) | (16U)), /*!< Clock gate name: AON INPUTMUX */ kCLOCK_GateNotAvail = (0xFFFFFFFFU), /**< Clock gate name: None */ } clock_ip_name_t; @@ -163,6 +164,12 @@ typedef enum _clock_ip_name kCLOCK_GateAonLCD \ } +/*! @brief Clock ip name array for LPACMP. */ +#define LPACMP_CLOCKS \ + { \ + kCLOCK_GateAonACMP0 \ + } + /*! @brief Clock ip name array for AOI. */ #define AOI_CLOCKS \ { \ @@ -234,14 +241,14 @@ typedef enum _clock_ip_name /*! @brief Clock ip name array for LPCMP. */ #if __CORTEX_M == (33U) /* Building on the main core */ -#define LPCMP_CLOCKS \ - { \ - kCLOCK_GateAonCMP0, kCLOCK_GateCMP0 \ +#define LPCMP_CLOCKS \ + { \ + kCLOCK_GateACMP0, kCLOCK_GateAonACMP0 \ } #else #define LPCMP_CLOCKS \ { \ - kCLOCK_GateAonCMP0 \ + kCLOCK_GateAonACMP0 \ } #endif @@ -328,6 +335,11 @@ typedef enum _clock_ip_name { \ kCLOCK_GateTCU \ } +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_GateTRNG0 \ + } /*! @brief Clock ip name array for UTICK. */ #define UTICK_CLOCKS \ { \ @@ -431,7 +443,7 @@ typedef enum _clock_select_name typedef enum _clock_attach_id { - kXTAL32K_to_AON_ROOT_AUX = CLK_ATTACH_MUX(kCLOKC_SelAonROOT_AUX, 0U), /*!< Attach XTAL32K to AON AUX. */ + kXTAL32K_to_AON_ROOT_AUX = CLK_ATTACH_MUX(kCLOKC_SelAonROOT_AUX, 0U), /*!< Attach XTAL32K to AON AUX. */ kAUX_to_AON_ROOT_AUX = CLK_ATTACH_MUX(kCLOKC_SelAonROOT_AUX, 1U), /*!< Attach AUX to AON AUX. */ kFROdiv1_to_AON_CPU = CLK_ATTACH_MUX(kCLOKC_SelAonROOT, 0U), /*!< Attach FRO div 1 to AON_CPU. */ @@ -451,8 +463,8 @@ typedef enum _clock_attach_id kFROdiv2_to_AON_LPADC = CLK_ATTACH_MUX(kCLOKC_SelAonLPADC, 1U), /*!< Attach FRO div 2 to AON LPADC. */ kFROdiv4_to_AON_LPADC = CLK_ATTACH_MUX(kCLOKC_SelAonLPADC, 2U), /*!< Attach FRO div 4 to AON LPADC. */ kROOT_AUX_to_AON_LPADC = CLK_ATTACH_MUX(kCLOKC_SelAonLPADC, 3U), /*!< Attach ROOT AUX to AON LPADC. */ - kXTAL32K_to_AON_LPADC = CLK_ATTACH_MUX(kCLOKC_SelAonLCD, 4U), /*!< Attach FRO RTC to AON LPADC. */ - kFRO16K_to_AON_LPADC = CLK_ATTACH_MUX(kCLOKC_SelAonLCD, 5U), /*!< Attach FRO fro16k to AON LPADC. */ + kXTAL32K_to_AON_LPADC = CLK_ATTACH_MUX(kCLOKC_SelAonLPADC, 4U), /*!< Attach FRO RTC to AON LPADC. */ + kFRO16K_to_AON_LPADC = CLK_ATTACH_MUX(kCLOKC_SelAonLPADC, 5U), /*!< Attach FRO fro16k to AON LPADC. */ kFROdiv1_to_AON_SYSTICK = CLK_ATTACH_MUX(kCLOKC_SelAonSYSTICK, 0U), /*!< Attach FRO div 1 to AON SYSTICK. */ kFROdiv2_to_AON_SYSTICK = CLK_ATTACH_MUX(kCLOKC_SelAonSYSTICK, 1U), /*!< Attach FRO div 2 to AON SYSTICK. */ @@ -505,7 +517,7 @@ typedef enum _clock_attach_id kCLK_16K_to_OSTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 0U), /*!< Attach CLK_16K to OSTIMER0. */ kFRO_16k_to_OSTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 1U), /*!< Attach FRO_16K to OSTIMER0. */ - kCLK_1M_to_OSTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 2U), /*!< Attach CLK_1M to OSTIMER0. */ + kCLK_1M_to_OSTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 3U), /*!< Attach CLK_1M to OSTIMER0. */ kFRO12M_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 0U), /*!< Attach FRO12M to ADC0. */ kXTAL32K_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 1U), /*!< Attach XTAL32K to ADC0. */ @@ -599,8 +611,8 @@ typedef enum _clock_div_name kCLOCK_DIVAonCPU = (0x400U), /*!< Aon CPU clock divider */ kCLOCK_DIVAonCMP = (0x401U), /*!< Aon Comp grp clock divider */ kCLOCK_DIVAonSYS = (0x402U), /*!< Aon SYSTICK clock divider */ - kCLOCK_DIVAonCMP0CLK0 = (0x410U), /*!< Aon CMP0 CLK0 clock divider */ - kCLOCK_DIVAonCMP0CLK1 = (0x411U), /*!< Aon CMP0 CLK1 clock divider */ + kCLOCK_DIVAonACMP0CLK0 = (0x410U), /*!< Aon CMP0 CLK0 clock divider */ + kCLOCK_DIVAonACMP0CLK1 = (0x411U), /*!< Aon CMP0 CLK1 clock divider */ kCLOCK_DivMax = (0x411U), /*!< MAX clock divider */ } clock_div_name_t; @@ -733,21 +745,12 @@ static inline void CLOCK_EnableClock(clock_ip_name_t clk) { return; } - -#if __CORTEX_M == (33U) /* Building on the main core */ - if (clk == kCLOCK_InputMux) /* Workaround for inputmux driver */ - { - CLOCK_EnableClock(kCLOCK_GateAonINPUTMUX1); - CLOCK_EnableClock(kCLOCK_GateINPUTMUX0); - return; - } -#endif if (CLK_OF_AON(clk)) { if(clk == kCLOCK_GateAonINPUTMUX1) { - AON__SYSCON_AON->PINMUXCLKCTRL = SYSCON_AON_PINMUXCLKCTRL_PINMUX_CLK_CTRL(0); + AON__SYSCON_AON->INPUTMUXCLKCTRL = SYSCON_AON_INPUTMUXCLKCTRL_INPUTMUX_CLK_CTRL(0); } else { @@ -766,7 +769,7 @@ static inline void CLOCK_EnableClock(clock_ip_name_t clk) /* Unlock clock configuration */ SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_CLKGEN_LOCKOUT_MASK; - if (clk != kCLOCK_InputMux && clk != kCLOCK_GateWWDT0 && clk != kCLOCK_GateSRAMA0A1 && clk != kCLOCK_GateROMCP ) + if (clk != kCLOCK_GateWWDT0 && clk != kCLOCK_GateSRAMA0A1 && clk != kCLOCK_GateROMCP) { *pPeripheralEnCtrl |= (1UL << bit_shift); } @@ -834,7 +837,7 @@ static inline void CLOCK_DisableClock(clock_ip_name_t clk) *pClkCtrl = (1UL << bit_shift); } - if (clk != kCLOCK_InputMux && clk != kCLOCK_GateWWDT0 && clk != kCLOCK_GateSRAMA0A1 && clk != kCLOCK_GateROMCP) + if (clk != kCLOCK_GateWWDT0 && clk != kCLOCK_GateSRAMA0A1 && clk != kCLOCK_GateROMCP) { *pPeripheralEnCtrl &= ~(1UL << bit_shift); } @@ -905,6 +908,11 @@ void CLOCK_HaltClockDiv(clock_div_name_t div_name); */ status_t CLOCK_SetupFROAonClocking(uint32_t iFreq); +/*! @brief Return Frequency of the AON core + * @return Frequency of the core + */ +uint32_t CLOCK_GetAonCoreSysClkFreq(void); + #if __CORTEX_M == (33U) /* Building on the main core */ /** * @brief Initialize the FROHF to given frequency. @@ -962,7 +970,7 @@ status_t CLOCK_DeinitRosc(void); uint32_t CLOCK_GetFreq(clock_name_t clockName); #if __CORTEX_M == (33U) /* Building on the main core */ -/*! @brief Return Frequency of core +/*! @brief Return Frequency of the main core * @return Frequency of the core */ uint32_t CLOCK_GetCoreSysClkFreq(void); @@ -1066,23 +1074,6 @@ status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config); */ status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config); -#endif /* Building on the main core */ - -/** - * @brief Sets AON FRO 10M or 2M trim. - * @param is_fro2m : 0 for FRO10M, 1 for FRO2M - * @param config : trim value - */ -void CLOCK_AON_FRO_Trim_Set(uint8_t is_fro2m, aon_fro_trim_config_t config); - -/** - * @brief Reads AON FRO 10M or 2M trim values. - * @param is_fro2m : 0 for FRO10M, 1 for FRO2M - * @param config : ptr to aon_fro_trim_config_t struct. - */ -void CLOCK_AON_FRO_Trim_Get(uint8_t is_fro2m, aon_fro_trim_config_t * config); - -#if __CORTEX_M == (33U) /* Building on the main core */ /*! * @brief Sets the ROSC monitor mode. @@ -1136,6 +1127,26 @@ static inline void CLOCK_SetXtal32Freq(uint32_t freq) g_xtal32Freq = freq; } +#if __CORTEX_M == (33U) /* Building on the main core */ +/*! + * @brief Set flash wait state. + * @param state Flash wait state (0-15) + */ +void CLOCK_SetFlashWaitState(uint8_t state); + +/*! + * @brief Set flash wait state based on frequency. + * @param freq Core frequency. + */ +void CLOCK_SetFlashWaitStateBasedOnFreq(uint32_t freq); + +/*! + * @brief Get flash wait state. + * @return Returns flash wait state. + */ +uint8_t CLOCK_GetFlashWaitState(void); +#endif /* Building on the main core */ + #if defined(__cplusplus) } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_power.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_power.c index f84ce392d..305ac7359 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_power.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_power.c @@ -11,7 +11,9 @@ #endif /* __CORTEX_M */ #include "fsl_mu.h" #include "fsl_smm.h" -#include "fsl_pmu.h" + +#include "fsl_advc.h" + /******************************************************************************* * Definitions ******************************************************************************/ @@ -24,29 +26,47 @@ /******************************************************************************* * Prototypes ******************************************************************************/ + +/*! + * @brief The union of lower half word of message. + */ +typedef union _power_mu_msg_2half_content +{ + uint16_t halfWordValueMask; + uint16_t sharedHandleAddrOff; /* Used when message type is sync. */ + uint16_t NAckReason; /* Used when message type is NACK. */ +} power_mu_msg_2half_content_t; + +/*! + * brief Union representing a power MU message. + */ +typedef union _power_mu_message +{ + struct + { + uint32_t syncCode : 8U; /*!< Synchronization code for the message */ + power_mu_message_type_t type : 2U; /*!< Type of the message, refer to ref power_mu_message_type_t */ + power_mu_message_direction_t + direction : 1U; /*!< Direction of the message, refer to ref power_mu_message_direction_t */ + power_low_power_mode_t reqestLowPowerMode : 4U; /*!< Requested low power mode */ + bool reserved : 1U; /*!< Reserved */ + power_mu_msg_2half_content_t lowHalfContent; /*!< Contents of lower half word, different message type + indicate different meaning. */ + } strcutFormat; + uint32_t wordFormat; /*!< Message in word format */ +} power_mu_message_t; + typedef enum _power_mu_transfer_state { - kPower_MuTransferIdle = 0U, - kPower_MuTransferStart = 1U, + kPower_MuTransferIdle = 0U, + kPower_MuTransferStart = 1U, kPower_MuTransferEndWithNACK = 2U, - kPower_MuTransferEndWithACK = 3U, - kPower_MuTransferWrong = 4U, + kPower_MuTransferEndWithACK = 3U, + kPower_MuTransferWrong = 4U, } power_mu_transfer_state_t; -volatile power_wakeup_source_info_t g_powerWakeupSourceInfo = { - .aonWakeupSourceMask = 0UL, - .wuuPinIntEnable[0] = 0UL, - .wuuPinIntEnable[1] = 0UL, - .wuuModuleIntEnable = 0UL, - .wuuModuleDmaTrigEnable = 0UL, - .wuuPinDmaTrigConfig[0] = 0UL, - .wuuPinDmaTrigConfig[1] = 0UL, -}; - volatile power_mu_transfer_state_t g_powerMuTransferState = kPower_MuTransferIdle; -static void Power_RecordWUURegisterValue(void); - /******************************************************************************* * Variables ******************************************************************************/ @@ -55,28 +75,16 @@ volatile power_mu_message_t g_powerRequestMuMsg; uint32_t g_Handle_Offset = 0xFFFFFFFFUL; #if __CORTEX_M == 33U -#define POWER_USED_MU (MUA) +#define POWER_USED_MU (MUA) #elif __CORTEX_M == 0U -#define POWER_USED_MU (MUB) +#define POWER_USED_MU (MUB) #endif /* __CORTEX_M */ /******************************************************************************* * Code ******************************************************************************/ -static void Power_RecordWUURegisterValue(void) -{ -#if __CORTEX_M == 33U - g_powerWakeupSourceInfo.wuuPinIntEnable[0] = WUU0->PE1; - g_powerWakeupSourceInfo.wuuPinIntEnable[1] = WUU0->PE2; - g_powerWakeupSourceInfo.wuuModuleIntEnable = WUU0->ME; - g_powerWakeupSourceInfo.wuuModuleDmaTrigEnable = WUU0->DE; - g_powerWakeupSourceInfo.wuuPinDmaTrigConfig[0] = WUU0->PDC1; - g_powerWakeupSourceInfo.wuuPinDmaTrigConfig[1] = WUU0->PDC2; -#endif -} - -static status_t Power_VerifyMuMessage(uint32_t message, bool msgIsRequest) +static status_t Power_VerifyMuMessage(uint32_t message) { power_mu_message_t msg; msg.wordFormat = message; @@ -87,47 +95,47 @@ static status_t Power_VerifyMuMessage(uint32_t message, bool msgIsRequest) } else { -#if 0 - if (msgIsRequest == false) - { - if ((msg.strcutFormat.direction == g_powerRequestMuMsg.strcutFormat.direction) || - (msg.strcutFormat.reqestLowPowerMode != g_powerRequestMuMsg.strcutFormat.reqestLowPowerMode) || - (msg.strcutFormat.sharedHandleAddrOff != g_powerRequestMuMsg.strcutFormat.sharedHandleAddrOff)) - { - return kStatus_POWER_MuTransferError; - } - } -#endif return kStatus_Success; } } -static uint32_t Power_PopulateMuMessage(power_mu_message_type_t msgType, power_mu_message_direction_t msgDirection, - power_low_power_mode_t lowPowerMode, bool init, uint32_t sharedHandleAddrOff) +static uint32_t Power_PopulateMuMessage(power_mu_message_type_t msgType, + power_mu_message_direction_t msgDirection, + power_low_power_mode_t lowPowerMode, + uint16_t lowHalfWordValue) { power_mu_message_t msg; - msg.strcutFormat.syncCode = 0x5A; - msg.strcutFormat.type = msgType; - msg.strcutFormat.direction = msgDirection; - msg.strcutFormat.reqestLowPowerMode = lowPowerMode; - msg.strcutFormat.init = init; - msg.strcutFormat.sharedHandleAddrOff = sharedHandleAddrOff; + msg.strcutFormat.syncCode = 0x5A; + msg.strcutFormat.type = msgType; + msg.strcutFormat.direction = msgDirection; + msg.strcutFormat.reqestLowPowerMode = lowPowerMode; + msg.strcutFormat.lowHalfContent.halfWordValueMask = lowHalfWordValue; return msg.wordFormat; } +static power_mu_nack_reason_t Power_GetMuNackReason(uint32_t message) +{ + power_mu_message_t msg; + + msg.wordFormat = message; + + return (power_mu_nack_reason_t)(msg.strcutFormat.lowHalfContent.NAckReason); +} + #if __CORTEX_M == 0U static status_t Power_ReqestCM33StartLpSeq(power_low_power_mode_t targetMode) { - uint32_t tmp32 = 0UL; + uint32_t tmp32 = 0UL; power_handle_t *curHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); - tmp32 = Power_PopulateMuMessage(kPower_MsgTypeRequest, kPower_MsgDirAonToMain, targetMode, false, g_Handle_Offset); + tmp32 = + Power_PopulateMuMessage(kPower_MsgTypeRequest, kPower_MsgDirAonToMain, targetMode, (uint16_t)g_Handle_Offset); MU_SendMsg(POWER_USED_MU, curHandle->muChannelId, tmp32); /* Waiting for response from CM0P. */ - while(g_powerMuTransferState != kPower_MuTransferStart) + while (g_powerMuTransferState != kPower_MuTransferStart) { } if (g_powerMuTransferState == kPower_MuTransferWrong) @@ -146,7 +154,7 @@ static status_t Power_ReqestCM33StartLpSeq(power_low_power_mode_t targetMode) /*! * brief Create shared power handle. - * + * * param[in] handle Pointer to a handle in type of power_handle_t, must be in shared RAM. * param[in] muChannelId MU channel ID used by power driver. * @@ -154,8 +162,7 @@ static status_t Power_ReqestCM33StartLpSeq(power_low_power_mode_t targetMode) * retval kStatus_Power_HandleDuplicated Shared power handle already be created. * retval kStatus_Success Created handle successfully. */ -status_t Power_CreateHandle(power_handle_t *handle, - uint32_t muChannelId) +status_t Power_CreateHandle(power_handle_t *handle, uint32_t muChannelId) { #if __CORTEX_M == 33U assert((uint32_t)handle >= POWER_SHARED_RAM_BASE_ADDR); @@ -163,22 +170,24 @@ status_t Power_CreateHandle(power_handle_t *handle, (void)memset(handle, 0UL, sizeof(power_handle_t)); - handle->muChannelId = muChannelId; - handle->targetPowerMode = kPower_Active; + handle->muChannelId = muChannelId; + handle->targetPowerMode = kPower_Active; + handle->previousPowerMode = kPower_Active; - handle->dualCoreSynced = false; + handle->dualCoreSynced = false; handle->requestCM33Start = false; /* Record offset of handle. */ g_Handle_Offset = (uint32_t)handle - POWER_SHARED_RAM_BASE_ADDR; /* Inform another that attemp to create handle. */ - uint32_t tmp32 = Power_PopulateMuMessage(kPower_MsgTypeRequest, kPower_MsgDirMainToAon, kPower_Active, true, g_Handle_Offset); + uint32_t tmp32 = + Power_PopulateMuMessage(kPower_MsgTypeSync, kPower_MsgDirMainToAon, kPower_Active, (uint16_t)g_Handle_Offset); g_powerMuTransferState = kPower_MuTransferStart; MU_SendMsg(POWER_USED_MU, muChannelId, tmp32); /* Waiting for response from CM0P. */ - while(g_powerMuTransferState == kPower_MuTransferStart) + while (g_powerMuTransferState == kPower_MuTransferStart) { } if (g_powerMuTransferState == kPower_MuTransferWrong) @@ -192,172 +201,206 @@ status_t Power_CreateHandle(power_handle_t *handle, g_powerMuTransferState = kPower_MuTransferIdle; handle->dualCoreSynced = true; + return kStatus_Success; } +/*! + * brief Dump contents of handle. + * + * param[out] ptrDumpBuffer The pointer to a buffer in type of ref power_handle_t to store dumped handle value. + */ void Power_DumpHandleValue(power_handle_t *ptrDumpBuffer) { - power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); - - memcpy(ptrDumpBuffer, sharedHandle, sizeof(power_handle_t)); + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + + memcpy(ptrDumpBuffer, sharedHandle, sizeof(power_handle_t)); } +/*! + * brief Get the offset of shared handle in shared RAM. + * + * return Offset of shared handle in shared RAM, in bytes. + */ uint32_t Power_GetHandleOffset(void) { return g_Handle_Offset; } +/*! + * brief Restore the shared handle from offset in shared RAM. + * + * param[in] offset Offset of shared handle in shared RAM, in bytes. + */ void Power_RestoreHandleOffset(uint32_t offset) { g_Handle_Offset = offset; } /*! - * brief Enable input wakeup source, once enabled it will be effective until disabled + * brief Get configurations of latest requested low power mode. * - * param[in] ws Specify the coded wakeup source, please refer to power_wakeup_source_t for details. + * param[out] config The pointer to a buffer to store configurations of latest requested low power mode */ -void Power_EnableWakeupSource(power_wakeup_source_t ws) +void Power_GetPowerModeConfig(void *config) { - uint32_t aonIndex; - uint32_t wuuIndex; - uint32_t wuuEvent; - uint32_t pinEdge; - uint32_t wakeupDomain; - bool isWuuExtPin; - bool isCm33Ws; -#if __CORTEX_M == 33U - wuu_external_wakeup_pin_config_t tmpPinConfig; -#endif + power_handle_t handleBuf; - POWER_DECODE_WS((uint32_t)ws); + Power_DumpHandleValue(&handleBuf); - if (isCm33Ws == true) + switch (handleBuf.previousPowerMode) { -#if __CORTEX_M == 33U - if (isWuuExtPin == true) + case kPower_DeepSleep: { - tmpPinConfig.edge = (wuu_external_pin_edge_detection_t)pinEdge; - tmpPinConfig.event = (wuu_external_wakeup_pin_event_t)wuuEvent; - tmpPinConfig.mode = kWUU_ExternalPinActiveAlways; - WUU_SetExternalWakeUpPinsConfig(WUU0, wuuIndex, &tmpPinConfig); + (void)memcpy(config, handleBuf.lpConfig, sizeof(power_ds_config_t)); + break; } - else + case kPower_PowerDown1: { - WUU_SetInternalWakeUpModulesConfig(WUU0, wuuIndex, (wuu_internal_wakeup_module_event_t)wuuEvent); + (void)memcpy(config, handleBuf.lpConfig, sizeof(power_pd1_config_t)); + break; } -#elif __CORTEX_M == 0U - (void)wuuIndex; - (void)wuuEvent; - (void)isWuuExtPin; -#endif - } - else - { - g_powerWakeupSourceInfo.aonWakeupSourceMask |= 1UL << aonIndex; - if (wakeupDomain == 0) + case kPower_PowerDown2: { - SMM_EnableWakeupSourceToMainCpu(AON__SMM, aonIndex); + (void)memcpy(config, handleBuf.lpConfig, sizeof(power_pd2_config_t)); + break; } - else if (wakeupDomain == 1) + case kPower_DeepPowerDown1: { - SMM_EnableWakeupSourceToAonCpu(AON__SMM, aonIndex); + (void)memcpy(config, handleBuf.lpConfig, sizeof(power_dpd1_config_t)); + break; } - else + case kPower_DeepPowerDown2: { - SMM_EnableWakeupSourceToAonCpu(AON__SMM, aonIndex); - SMM_EnableWakeupSourceToMainCpu(AON__SMM, aonIndex); + (void)memcpy(config, handleBuf.lpConfig, sizeof(power_dpd2_config_t)); + break; } - - if (aonIndex == 5U) + case kPower_DeepPowerDown3: { - /* In case of external interrupt. */ - smm_ext_int_config_t extIntConfig = { - .maskExtIntPin = false, - }; - if (pinEdge == 2UL) - { - extIntConfig.extIntPolarity = kSMM_ExtIntFallingEdge; - } - else if (pinEdge == 1UL) - { - extIntConfig.extIntPolarity = kSMM_ExtIntRisingEdge; - } - SMM_SetExtInterruptConfig(AON__SMM, &extIntConfig); - SMM_ClearExternalIntFlag(AON__SMM); + (void)memcpy(config, handleBuf.lpConfig, sizeof(power_dpd3_config_t)); + break; + } + case kPower_ShutDown: + { + (void)memcpy(config, handleBuf.lpConfig, sizeof(power_sd_config_t)); + break; + } + default: + { + /* Avoid violation of MISRA C-2012 rule. */ + break; } } +} - Power_RecordWUURegisterValue(); +/*! + * brief Get the target low power mode of latest request. + * + * return The target low power mode ref power_low_power_mode_t of latest request. + */ +power_low_power_mode_t Power_GetTargetLowPowerMode(void) +{ + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); -#if __CORTEX_M == 33U - if ((g_powerWakeupSourceInfo.wuuPinIntEnable[0] != 0UL) || (g_powerWakeupSourceInfo.wuuPinIntEnable[1] != 0UL)) - { - EnableIRQ(WUU0_IRQn); - } -#endif + return sharedHandle->targetPowerMode; } /*! - * brief Disable input wakeup source. + * brief Enable input wakeup source, once enabled it will be effective until disabled * * param[in] ws Specify the coded wakeup source, please refer to power_wakeup_source_t for details. */ -void Power_DisableWakeupSource(power_wakeup_source_t ws) +void Power_EnableWakeupSource(power_wakeup_source_t ws) { uint32_t aonIndex; - uint32_t wuuIndex; - uint32_t wuuEvent; uint32_t pinEdge; uint32_t wakeupDomain; - bool isWuuExtPin; - bool isCm33Ws; + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); POWER_DECODE_WS((uint32_t)ws); - (void)pinEdge; - if (isCm33Ws == true) + if (ws == kPower_WS_NONE) { -#if __CORTEX_M == 33U - if (isWuuExtPin == true) - { - WUU_ClearExternalWakeupPinsConfig(WUU0, wuuIndex); - } - else - { - WUU_ClearInternalWakeUpModulesConfig(WUU0, wuuIndex, (wuu_internal_wakeup_module_event_t)wuuEvent); - } -#elif __CORTEX_M == 0U - (void)wuuIndex; - (void)wuuEvent; - (void)isWuuExtPin; -#endif + return; + } + + if (wakeupDomain == 0U) + { + sharedHandle->enabledWsInfo.mainWakeupSourceMask |= 1UL << aonIndex; + } + else if (wakeupDomain == 1) + { + sharedHandle->enabledWsInfo.aonWakeupSourceMask |= 1UL << aonIndex; } else { - if (wakeupDomain == 0) - { - SMM_DisableWakeupSourceToMainCpu(AON__SMM, aonIndex); - } - else if (wakeupDomain == 1) + sharedHandle->enabledWsInfo.mainWakeupSourceMask |= 1UL << aonIndex; + sharedHandle->enabledWsInfo.aonWakeupSourceMask |= 1UL << aonIndex; + } + + if (aonIndex == 5U) + { + /* In case of external interrupt. */ + smm_ext_int_config_t extIntConfig = { + .maskExtIntPin = false, + }; + if (pinEdge == 2UL) { - SMM_DisableWakeupSourceToAonCpu(AON__SMM, aonIndex); + extIntConfig.extIntPolarity = kSMM_ExtIntFallingEdge; } - else + else if (pinEdge == 1UL) { - SMM_DisableWakeupSourceToAonCpu(AON__SMM, aonIndex); - SMM_DisableWakeupSourceToMainCpu(AON__SMM, aonIndex); + extIntConfig.extIntPolarity = kSMM_ExtIntRisingEdge; } + SMM_SetExtInterruptConfig(AON__SMM, &extIntConfig); + SMM_ClearExternalIntFlag(AON__SMM); } +} + +/*! + * brief Disable input wakeup source. + * + * param[in] ws Specify the coded wakeup source, please refer to power_wakeup_source_t for details. + */ +void Power_DisableWakeupSource(power_wakeup_source_t ws) +{ + uint32_t aonIndex; + uint32_t pinEdge; + uint32_t wakeupDomain; + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); - Power_RecordWUURegisterValue(); + POWER_DECODE_WS((uint32_t)ws); -#if __CORTEX_M == 33U - if ((g_powerWakeupSourceInfo.wuuPinIntEnable[0] == 0UL) && (g_powerWakeupSourceInfo.wuuPinIntEnable[1] == 0UL)) + (void)pinEdge; + + if (ws == kPower_WS_NONE) + { + return; + } + + if (wakeupDomain == 0) + { + sharedHandle->enabledWsInfo.mainWakeupSourceMask &= ~(1UL << aonIndex); + SMM_DisableWakeupSourceToMainCpu(AON__SMM, (1UL << aonIndex)); + } + else if (wakeupDomain == 1) + { + sharedHandle->enabledWsInfo.aonWakeupSourceMask &= ~(1UL << aonIndex); + SMM_DisableWakeupSourceToAonCpu(AON__SMM, (1UL << aonIndex)); + } + else { - DisableIRQ(WUU0_IRQn); + sharedHandle->enabledWsInfo.mainWakeupSourceMask &= ~(1UL << aonIndex); + sharedHandle->enabledWsInfo.aonWakeupSourceMask &= ~(1UL << aonIndex); + SMM_DisableWakeupSourceToAonCpu(AON__SMM, (1UL << aonIndex)); + SMM_DisableWakeupSourceToMainCpu(AON__SMM, (1UL << aonIndex)); } -#endif +} + +void Power_DisableAllWakeupSources(void) +{ + SMM_DisableWakeupSourceToMainCpu(AON__SMM, SMM_WKUP_MAIN_WKUP_SRC_MAIN_CPU_MASK); + SMM_DisableWakeupSourceToAonCpu(AON__SMM, SMM_AON_CPU_WKUP_SRC_AON_CPU_MASK); } /*! @@ -369,7 +412,9 @@ void Power_DumpEnabledWakeSource(power_wakeup_source_info_t *ptrWsInfo) { assert(ptrWsInfo); - (void)memcpy((void *)ptrWsInfo, (void *)(&g_powerWakeupSourceInfo), sizeof(g_powerWakeupSourceInfo)); + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + + (void)memcpy((void *)ptrWsInfo, (void *)(&(sharedHandle->enabledWsInfo)), sizeof(power_wakeup_source_info_t)); } /*! @@ -382,9 +427,98 @@ void Power_GetWakeupSource(uint32_t *ptrWakeupSourceMask) *ptrWakeupSourceMask = SMM_GetWakeupSourceStatus(AON__SMM); } +/*! + * brief Check selected wakeup source already enabled, if is enabled then disable it. + * + * param ws Specify the wakeup source in type of power_wakeup_source_t. + */ +void Power_CheckThenDisableWakeupSource(power_wakeup_source_t ws) +{ + uint32_t aonIndex; + uint32_t pinEdge; + uint32_t wakeupDomain; + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + + POWER_DECODE_WS((uint32_t)ws); + + (void)pinEdge; + + if (ws == kPower_WS_NONE) + { + return; + } + + if (wakeupDomain == 0UL) + { + if ((sharedHandle->enabledWsInfo.mainWakeupSourceMask & (1UL << aonIndex)) != 0UL) + { + Power_DisableWakeupSource(ws); + } + } + else if (wakeupDomain == 1UL) + { + if ((sharedHandle->enabledWsInfo.aonWakeupSourceMask & (1UL << aonIndex)) != 0UL) + { + Power_DisableWakeupSource(ws); + } + } + else + { + if (((sharedHandle->enabledWsInfo.mainWakeupSourceMask & (1UL << aonIndex)) != 0UL) && + ((sharedHandle->enabledWsInfo.aonWakeupSourceMask & (1UL << aonIndex)) != 0UL)) + { + Power_DisableWakeupSource(ws); + } + } +} + +/*! + * brief Check selected wakeup source is disabled, if is disabled then enable it. + * + * param ws Specify the wakeup source in type of power_wakeup_source_t. + */ +void Power_CheckThenEnableWakeupSource(power_wakeup_source_t ws) +{ + uint32_t aonIndex; + uint32_t pinEdge; + uint32_t wakeupDomain; + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + + POWER_DECODE_WS((uint32_t)ws); + (void)pinEdge; + + if (ws == kPower_WS_NONE) + { + return; + } + + if (wakeupDomain == 0U) + { + if ((sharedHandle->enabledWsInfo.mainWakeupSourceMask & (1UL << aonIndex)) == 0UL) + { + Power_EnableWakeupSource(ws); + } + } + else if (wakeupDomain == 1) + { + if ((sharedHandle->enabledWsInfo.aonWakeupSourceMask & (1UL << aonIndex)) == 0UL) + { + Power_EnableWakeupSource(ws); + } + } + else + { + if (((sharedHandle->enabledWsInfo.mainWakeupSourceMask & (1UL << aonIndex)) == 0UL) && + ((sharedHandle->enabledWsInfo.aonWakeupSourceMask & (1UL << aonIndex)) == 0UL)) + { + Power_EnableWakeupSource(ws); + } + } +} + /*! * brief Register user callback. - * + * * param[in] callback Pointer to callback in type of power_user_callback_t. * param[in] userData Pointer to user data. */ @@ -415,15 +549,45 @@ void Power_UnRegisterUserCallback(void) #endif } -status_t Power_GetCurrentPowerMode(power_low_power_mode_t *ptrCurLpMode) +/*! + * brief Get previous power mode. + * + * return The previous power mode. + */ +power_low_power_mode_t Power_GetPreviousPowerMode(void) +{ + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + + return sharedHandle->previousPowerMode; +} + +/*! + * brief Reset previous power mode as active mode. + */ +void Power_ResetPreviousPowerMode(void) { - status_t status = kStatus_Success; - uint8_t tmp8 = SMM_GetPowerState(AON__SMM); power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + + sharedHandle->previousPowerMode = kPower_Active; +} + +/*! + * brief Get current power mode. + * + * param[out] ptrCurLpMode Pointer to store current low power mode + * + * retval kStatus_Success Successfully retrieved current low power mode. + */ +status_t Power_GetCurrentPowerMode(power_low_power_mode_t *ptrCurLpMode) +{ + assert(g_Handle_Offset != 0xFFFFFFFFUL); + status_t status = kStatus_Success; + uint8_t tmp8 = SMM_GetPowerState(AON__SMM); + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); power_low_power_mode_t targetLpMode = sharedHandle->targetPowerMode; - power_low_power_mode_t curLpMode = kPower_Active; + power_low_power_mode_t curLpMode = kPower_Active; - switch(tmp8) + switch (tmp8) { case 0U: { @@ -448,83 +612,85 @@ status_t Power_GetCurrentPowerMode(power_low_power_mode_t *ptrCurLpMode) curLpMode = kPower_PowerDown1; break; } - case 4U: - { - curLpMode = kPower_DeepPowerDown2; - break; - } - case 5U: - { - curLpMode = kPower_DeepPowerDown3; - break; - } - case 6U: - { - curLpMode = kPower_ShutDown; - break; - } - default: + default: { - /* Avoid violation of MISRA rule. */ + status = kStatus_Fail; break; } } *ptrCurLpMode = curLpMode; -// if (curLpMode != targetLpMode) -// { -// status = kStatus_Power_NotInTargetMode; -// } return status; } +/*! + * brief Get the target low power mode. + * + * return Requested low power mode, in type of ref power_low_power_mode_t. + */ power_low_power_mode_t Power_GetTargetPowerMode(void) { - power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); power_low_power_mode_t targetPowerMode = sharedHandle->targetPowerMode; return targetPowerMode; } -void Power_ClearTargatePowerMode(void) +/*! + * brief Clear the target low power mode. + */ +void Power_ClearTargetPowerMode(void) { - power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); sharedHandle->targetPowerMode = kPower_Active; } +/*! + * brief Clear all low power settings. + */ void Power_ClearLpPowerSettings(void) { #if __CORTEX_M == 33U SMM_DisableMainCpuIso(AON__SMM); SMM_ClearAllLowPowerSequence(AON__SMM); SMM_ClearMainCpuWakeupSources(AON__SMM); + CMC_SetClockMode(CMC, kCMC_GateNoneClock); + CMC_SetGlobalPowerMode(CMC, kCMC_ActiveOrSleepMode); + AON__SMM->STAT = SMM_STAT_DPD_SEQ_END_MASK | SMM_STAT_DPD_END_MASK; + AON__SMM->LSB_BCKP1 = 0UL; + AON__SMM->LSB_BCKP2 = 0UL; + AON__SMM->MSB_BCKP2 = 0UL; #elif __CORTEX_M == 0U SMM_DisableAonCpuIso(AON__SMM); SMM_ClearAllLowPowerSequence(AON__SMM); SMM_ClearAonCpuWakeupSources(AON__SMM); -#endif /* __CORTEX_M */ +#if 0 + AON__SMM->STAT = SMM_STAT_DPD_SEQ_END_MASK | SMM_STAT_DPD_END_MASK; +#endif + AON__SMM->MSB_BCKP1 = 0UL; +#endif /* __CORTEX_M */ } /*! -* brief Enter selected low power mode. -* -* param[in] lowpowerMode Indicate specific low power mode. -* param config Point to low power configurations. -* -* retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. -* retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. -*/ + * brief Enter selected low power mode. + * + * param[in] lowpowerMode Indicate specific low power mode. + * param config Point to low power configurations. + * + * retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. + * retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. + */ status_t Power_EnterLowPowerMode(power_low_power_mode_t lowpowerMode, void *config) { - status_t status = kStatus_Success; - switch(lowpowerMode) + status_t status = kStatus_Success; + switch (lowpowerMode) { case kPower_Sleep: { (void)config; status = Power_EnterSleep(); break; - } + } case kPower_DeepSleep: { status = Power_EnterDeepSleep((power_ds_config_t *)config); @@ -572,9 +738,9 @@ status_t Power_EnterLowPowerMode(power_low_power_mode_t lowpowerMode, void *conf /*! * brief Enter the sleep mode. - * + * * This function is used to put the system into sleep mode. - * + * * retval kStatus_Success Successfully entered sleep mode. * retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -582,11 +748,12 @@ status_t Power_EnterLowPowerMode(power_low_power_mode_t lowpowerMode, void *conf status_t Power_EnterSleep(void) { #if __CORTEX_M == 33U - power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); sharedHandle->targetPowerMode = kPower_Sleep; __DSB(); __ISB(); __WFI(); + sharedHandle->previousPowerMode = kPower_Sleep; return kStatus_Success; #elif __CORTEX_M == 0U @@ -594,14 +761,13 @@ status_t Power_EnterSleep(void) #endif /* __CORTEX_M == 33U */ } - /*! * brief Enter Deep Sleep mode. - * + * * This function attempts to put the system into Deep Sleep mode with the provided configuration. - * + * * param[in] config Pointer to the Deep Sleep mode configuration. - * + * * retval kStatus_Success Successfully entered Deep Sleep mode. * retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -609,7 +775,7 @@ status_t Power_EnterSleep(void) status_t Power_EnterDeepSleep(power_ds_config_t *config) { power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); - memcpy(sharedHandle->lpConfig, config, sizeof(power_ds_config_t)); + (void)config; #if __CORTEX_M == 33U /* Invoke CMC API to set Main domain as Deep power down mode and then execute WFI instruction. */ @@ -617,12 +783,13 @@ status_t Power_EnterDeepSleep(power_ds_config_t *config) CMC_SetClockMode(CMC, kCMC_GateAllSystemClocksEnterLowPowerMode); CMC_SetGlobalPowerMode(CMC, kCMC_DeepSleepMode); sharedHandle->requestCM33Start = false; - sharedHandle->targetPowerMode = kPower_DeepSleep; + sharedHandle->targetPowerMode = kPower_DeepSleep; SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; __DSB(); __WFI(); __ISB(); + sharedHandle->previousPowerMode = kPower_DeepSleep; return kStatus_Success; #elif __CORTEX_M == 0U sharedHandle->requestCM33Start = true; @@ -632,11 +799,11 @@ status_t Power_EnterDeepSleep(power_ds_config_t *config) /*! * brief Enter Power Down 1 mode. - * + * * This function attempts to put the system into Power Down 1 mode with the provided configuration. - * + * * param[in] config Pointer to the Power Down 1 mode configuration. - * + * * retval kStatus_Success Successfully entered Power Down 1 mode. * retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -646,25 +813,29 @@ status_t Power_EnterPowerDown1(power_pd1_config_t *config) power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); memcpy(sharedHandle->lpConfig, config, sizeof(power_pd1_config_t)); #if __CORTEX_M == 33U + /*1. Enable wakeup sources. */ + Power_CheckThenEnableWakeupSource(config->mainWakeupSource); + /*2. Configuration for SMM and PMU. */ + SMM_EnableWakeupSourceToMainCpu(AON__SMM, sharedHandle->enabledWsInfo.mainWakeupSourceMask); SMM_EnableMainDomainSramRetention(AON__SMM, config->mainRamArraysToRetain); - SMM_ShutDownBandgapInLowPowerModes(AON__SMM, config->disableBandgap); + SMM_ShutDownBandgapInLowPowerModes(AON__SMM, false); SMM_EnableIvsModeForSramRetention(AON__SMM, config->enableIVSMode); SMM_StartPowerDownSequence(AON__SMM); - /* TODO: WUU settings? */ - + /* 3. Configuration for CMC. */ CMC_SetPowerModeProtection(CMC, kCMC_AllowAllLowPowerModes); CMC_SetClockMode(CMC, kCMC_GateAllSystemClocksEnterLowPowerMode); CMC->GPMCTRL = CMC_GPMCTRL_LPMODE((uint8_t)0x7); sharedHandle->requestCM33Start = false; - sharedHandle->targetPowerMode = kPower_PowerDown1; + sharedHandle->targetPowerMode = kPower_PowerDown1; SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; __DSB(); __ISB(); __WFI(); + sharedHandle->previousPowerMode = kPower_PowerDown1; return kStatus_Success; #elif __CORTEX_M == 0U sharedHandle->requestCM33Start = true; @@ -674,11 +845,11 @@ status_t Power_EnterPowerDown1(power_pd1_config_t *config) /*! * brief Enter Power Down 2 mode. - * + * * This function attempts to put the system into Power Down 2 mode with the provided configuration. - * + * * param[in] config Pointer to the Power Down 2 mode configuration. - * + * * retval kStatus_Success Successfully entered Power Down 2 mode. * retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -688,36 +859,22 @@ status_t Power_EnterPowerDown2(power_pd2_config_t *config) power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); memcpy(sharedHandle->lpConfig, config, sizeof(power_pd2_config_t)); #if __CORTEX_M == 33U - /* 1. Configuration for SMM. */ - SMM_PowerOffAonSramAutomatically(AON__SMM, (uint8_t)(~(config->aonRamArraysToRetain))); - SMM_EnableMainDomainSramRetention(AON__SMM, config->mainRamArraysToRetain); - SMM_ShutDownBandgapInLowPowerModes(AON__SMM, config->disableBandgap); - SMM_EnableIvsModeForSramRetention(AON__SMM, config->enableIVSMode); - SMM_SwitchToXTAL32(AON__SMM, config->switchToX32K); - if (config->switchToX32K) - { - AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; - } - SMM_StartAonDPD2Sequence(AON__SMM); - - /* 2. Software configuration for CM0P. */ + /* 1. Inform CM0P that CM33 request to set whole system into PD2 mode, require CM0P execute WFI. */ if (sharedHandle->requestCM33Start != true) { /* Inform CM0P to execute WFI. */ - power_mu_message_t msg = { - .strcutFormat = { - .syncCode = 0x5A, - .type = kPower_MsgTypeRequest, - .direction = kPower_MsgDirMainToAon, - .reqestLowPowerMode = kPower_PowerDown2, - .sharedHandleAddrOff = 0UL, - } - }; + power_mu_message_t msg = {.strcutFormat = { + .syncCode = 0x5A, + .type = kPower_MsgTypeRequest, + .direction = kPower_MsgDirMainToAon, + .reqestLowPowerMode = kPower_PowerDown2, + .lowHalfContent.halfWordValueMask = 0UL, + }}; g_powerMuTransferState = kPower_MuTransferStart; - g_powerRequestMuMsg = msg; - MU_SendMsg(MUA, sharedHandle->muChannelId, (uint32_t)msg.wordFormat); + g_powerRequestMuMsg = msg; + MU_SendMsg(POWER_USED_MU, sharedHandle->muChannelId, (uint32_t)msg.wordFormat); /* Waiting for response from CM0P. */ - while(g_powerMuTransferState == kPower_MuTransferStart) + while (g_powerMuTransferState == kPower_MuTransferStart) { } if (g_powerMuTransferState == kPower_MuTransferWrong) @@ -731,40 +888,103 @@ status_t Power_EnterPowerDown2(power_pd2_config_t *config) g_powerMuTransferState = kPower_MuTransferIdle; } - /* 3. TODO: Configuration for WUU? */ + /* 2. Enable wakeup sources for different domain. */ + Power_CheckThenEnableWakeupSource(config->mainWakeupSource); + Power_CheckThenEnableWakeupSource(config->aonWakeupSource); + + SMM_EnableWakeupSourceToMainCpu(AON__SMM, sharedHandle->enabledWsInfo.mainWakeupSourceMask); + SMM_EnableWakeupSourceToAonCpu(AON__SMM, sharedHandle->enabledWsInfo.aonWakeupSourceMask); + + /* 3. Configuration for SMM and PMU. */ + if (config->vddCoreAonVoltage != kPower_VddCoreAon_AdvcControl) + { + PMU_UpdateVDDCoreInActiveMode(AON__PMU, config->vddCoreAonVoltage); + } + SMM_PowerOffAonSramAutomatically(AON__SMM, (uint8_t)(~(config->aonRamArraysToRetain))); + SMM_EnableMainDomainSramRetention(AON__SMM, config->mainRamArraysToRetain); + SMM_ShutDownBandgapInLowPowerModes(AON__SMM, false); + SMM_EnableIvsModeForSramRetention(AON__SMM, config->enableIVSMode); + SMM_StartPowerDownSequence(AON__SMM); /* 4. Configuration for CMC. */ CMC_SetPowerModeProtection(CMC, kCMC_AllowAllLowPowerModes); CMC_SetClockMode(CMC, kCMC_GateAllSystemClocksEnterLowPowerMode); CMC->GPMCTRL = CMC_GPMCTRL_LPMODE((uint8_t)0x7); - sharedHandle->requestCM33Start = false; - sharedHandle->targetPowerMode = kPower_PowerDown2; - if (config->disableFRO10M) + /* Disable FRO10M is required. */ + if (sharedHandle->cm0pWFI == false) { - AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; - AON__CGU->CLK_CONFIG = (AON__CGU->CLK_CONFIG & ~CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) | CGU_CLK_CONFIG_ROOT_CLK_SEL(3U); - AON__CGU->CLK_CONFIG &= ~(CGU_CLK_CONFIG_FRO10M_EN_MASK | CGU_CLK_CONFIG_FRO2M_EN_MASK); - } - /* 5. Software configuration for CM33. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __ISB(); - __WFI(); - - return kStatus_Success; -#elif __CORTEX_M == 0U - status_t status = kStatus_Success; - sharedHandle->requestCM33Start = true; + return kStatus_Power_CM0PNotWFI; + } + else + { + if (config->disableFRO10M) + { + AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; + AON__CGU->CLK_CONFIG = + (AON__CGU->CLK_CONFIG & ~CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) | CGU_CLK_CONFIG_ROOT_CLK_SEL(3U); + AON__CGU->CLK_CONFIG &= ~(CGU_CLK_CONFIG_FRO10M_EN_MASK | CGU_CLK_CONFIG_FRO2M_EN_MASK); + } - status = Power_ReqestCM33StartLpSeq(kPower_PowerDown2); + sharedHandle->requestCM33Start = false; + sharedHandle->targetPowerMode = kPower_PowerDown2; + sharedHandle->previousPowerMode = kPower_PowerDown2; + sharedHandle->cm0pWFI = false; - if (status == kStatus_Success) - { + /* 5. Execute WFI. */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; __DSB(); __ISB(); __WFI(); + return kStatus_Success; + } + +#elif __CORTEX_M == 0U + status_t status = kStatus_POWER_RequestNotAllowed; + sharedHandle->requestCM33Start = true; + sharedHandle->targetPowerMode = kPower_PowerDown2; + power_low_power_mode_t curLpMode; + status = Power_GetCurrentPowerMode(&curLpMode); + + if (status == kStatus_Success) + { + if (curLpMode != kPower_PowerDown1) + { + /* If system is not in Power Down1 Mode, request CM33 to start sequence to enter PD2. */ + status = Power_ReqestCM33StartLpSeq(kPower_PowerDown2); + } + else + { /* System is in PD1 mode, */ + + /*1. Enable wakeup sources.*/ + Power_CheckThenEnableWakeupSource(config->mainWakeupSource); + Power_CheckThenEnableWakeupSource(config->aonWakeupSource); + + SMM_EnableWakeupSourceToMainCpu(AON__SMM, sharedHandle->enabledWsInfo.mainWakeupSourceMask); + SMM_EnableWakeupSourceToAonCpu(AON__SMM, sharedHandle->enabledWsInfo.aonWakeupSourceMask); + + /*2. Update SMM settings. */ + SMM_PowerOffAonSramAutomatically(AON__SMM, (uint8_t)(~(config->aonRamArraysToRetain))); + SMM_EnableMainDomainSramRetention(AON__SMM, config->mainRamArraysToRetain); + SMM_ShutDownBandgapInLowPowerModes(AON__SMM, false); + SMM_EnableIvsModeForSramRetention(AON__SMM, config->enableIVSMode); + + if (config->disableFRO10M) + { + AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; + AON__CGU->CLK_CONFIG = + (AON__CGU->CLK_CONFIG & ~CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) | CGU_CLK_CONFIG_ROOT_CLK_SEL(3U); + AON__CGU->CLK_CONFIG &= ~(CGU_CLK_CONFIG_FRO10M_EN_MASK | CGU_CLK_CONFIG_FRO2M_EN_MASK); + } + + sharedHandle->previousPowerMode = kPower_PowerDown2; + /*3. Execute WFI to enter PD2. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + sharedHandle->cm0pWFI = true; + __DSB(); + __ISB(); + __WFI(); + } } return status; @@ -773,11 +993,11 @@ status_t Power_EnterPowerDown2(power_pd2_config_t *config) /*! * brief Enter Deep Power Down 1 mode. - * + * * This function attempts to put the system into Deep Power Down 1 mode with the provided configuration. - * + * * param[in] config Pointer to the Deep Power Down 1 mode configuration. - * + * * retval kStatus_Success Successfully entered Deep Power Down 1 mode. * retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -788,51 +1008,78 @@ status_t Power_EnterDeepPowerDown1(power_dpd1_config_t *config) memcpy(sharedHandle->lpConfig, config, sizeof(power_dpd1_config_t)); #if __CORTEX_M == 33U - /* 1. Configuration for PMU. */ -// PMU_UpdateVDDCoreInLpMode(AON__PMU, (uint8_t)config->VDDCoreOutputVoltage); + Power_CheckThenEnableWakeupSource(config->mainWakeupSource); + SMM_EnableWakeupSourceToMainCpu(AON__SMM, sharedHandle->enabledWsInfo.mainWakeupSourceMask); - /* 2. Configuration for SMM. */ + /* 1. Configuration for SMM and PMU. */ + if (config->vddCoreAonVoltage != kPower_VddCoreAon_AdvcControl) + { + PMU_UpdateVDDCoreInActiveMode(AON__PMU, config->vddCoreAonVoltage); + } SMM_EnableMainDomainSramRetention(AON__SMM, config->mainRamArraysToRetain); SMM_ShutDownBandgapInLowPowerModes(AON__SMM, config->disableBandgap); SMM_EnableIvsModeForSramRetention(AON__SMM, config->enableIVSMode); SMM_StartPowerDownSequence(AON__SMM); - /* 3. Configuration for CMC. */ + /* 2. Configuration for CMC. */ CMC_SetPowerModeProtection(CMC, kCMC_AllowAllLowPowerModes); CMC_SetClockMode(CMC, kCMC_GateAllSystemClocksEnterLowPowerMode); CMC_SetGlobalPowerMode(CMC, kCMC_DeepPowerDown); - sharedHandle->requestCM33Start = false; - sharedHandle->targetPowerMode = kPower_DeepPowerDown1; + sharedHandle->requestCM33Start = false; + sharedHandle->targetPowerMode = kPower_DeepPowerDown1; + sharedHandle->previousPowerMode = kPower_DeepPowerDown1; - /* 4. Software configuration for CM33. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __ISB(); - __WFI(); + if (config->mainRamArraysToRetain != kPower_MainDomainNoneRams) + { + AON__SMM->LSB_BCKP1 = 0UL; + if (Power_PushContext((uint32_t)sharedHandle) == 0UL) + { + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __ISB(); + __WFI(); + } + g_Handle_Offset = (uint32_t)((uint32_t)sharedHandle - POWER_SHARED_RAM_BASE_ADDR); + sharedHandle->previousPowerMode = kPower_DeepPowerDown1; + return kStatus_Power_WakeupFromDPD1; + } + else + { + /* 3. Software configuration for CM33. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __ISB(); + __WFI(); - return kStatus_Success; + return kStatus_Success; + } #elif __CORTEX_M == 0U sharedHandle->requestCM33Start = true; return Power_ReqestCM33StartLpSeq(kPower_DeepPowerDown1); #endif /* __CORTEX_M == 33U */ } +/*! + * brief Get the next transition after Deep Power Down 1 mode. + * + * return Next transition after Deep Power Down 1 mode, in type of power_dpd1_transition_t. + */ power_dpd1_transition_t Power_GetDeepPowerDown1NextTransition(void) { power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); power_dpd1_config_t config; memcpy(&config, sharedHandle->lpConfig, sizeof(power_dpd1_config_t)); - + return config.nextTrans; } /*! * brief Enter Deep Power Down 2 mode. - * + * * This function attempts to put the system into Deep Power Down 2 mode with the provided configuration. - * + * * param[in] config Pointer to the Deep Power Down 2 mode configuration. - * + * * retval kStatus_Success Successfully entered Deep Power Down 2 mode. * retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -842,42 +1089,24 @@ status_t Power_EnterDeepPowerDown2(power_dpd2_config_t *config) power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); memcpy(sharedHandle->lpConfig, config, sizeof(power_dpd2_config_t)); -#if __CORTEX_M == 33U - //patch - uint32_t *ptr = (uint32_t *)0xA0098038; - *ptr |= (1 << 11); // Set the 8th bit (bit 7, as bits are 0-indexed) - - /*1. Configuration for SMM. */ - SMM_PowerOffAonSramAutomatically(AON__SMM, (uint8_t)(~(config->aonRamArraysToRetain))); - SMM_EnableMainDomainSramRetention(AON__SMM, config->mainRamArraysToRetain); - SMM_ShutDownBandgapInLowPowerModes(AON__SMM, config->disableBandgap); - SMM_EnableIvsModeForSramRetention(AON__SMM, config->enableIVSMode); - SMM_SwitchToXTAL32(AON__SMM, config->switchToX32K); - if (config->switchToX32K) - { - AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; - } - SMM_StartAonDPD2Sequence(AON__SMM); - - /*2. Software configuration for CM0P. */ +#if __CORTEX_M == 33U + /*1. Inform CM0P that CM33 request to set whole system into DPD2 mode, require CM0P execute WFI. */ if (sharedHandle->requestCM33Start != true) { /* Inform CM0P to execute WFI. */ - power_mu_message_t msg = { - .strcutFormat = { - .syncCode = 0x5A, - .type = kPower_MsgTypeRequest, - .direction = kPower_MsgDirMainToAon, - .reqestLowPowerMode = kPower_DeepPowerDown2, - .sharedHandleAddrOff = 0UL, - } - }; + power_mu_message_t msg = {.strcutFormat = { + .syncCode = 0x5A, + .type = kPower_MsgTypeRequest, + .direction = kPower_MsgDirMainToAon, + .reqestLowPowerMode = kPower_DeepPowerDown2, + .lowHalfContent.halfWordValueMask = 0UL, + }}; g_powerMuTransferState = kPower_MuTransferStart; - g_powerRequestMuMsg = msg; - MU_SendMsg(MUA, sharedHandle->muChannelId, (uint32_t)msg.wordFormat); + g_powerRequestMuMsg = msg; + MU_SendMsg(POWER_USED_MU, sharedHandle->muChannelId, (uint32_t)msg.wordFormat); /* Waiting for response from CM0P. */ - while(g_powerMuTransferState == kPower_MuTransferStart) + while (g_powerMuTransferState == kPower_MuTransferStart) { } if (g_powerMuTransferState == kPower_MuTransferWrong) @@ -890,31 +1119,70 @@ status_t Power_EnterDeepPowerDown2(power_dpd2_config_t *config) } g_powerMuTransferState = kPower_MuTransferIdle; } - /* 3. Configuration for CMC */ + + /*2. Enable wakeup sources for main and aon domain. */ + Power_CheckThenEnableWakeupSource(config->mainWakeupSource); + Power_CheckThenEnableWakeupSource(config->aonWakeupSource); + + SMM_EnableWakeupSourceToMainCpu(AON__SMM, sharedHandle->enabledWsInfo.mainWakeupSourceMask); + SMM_EnableWakeupSourceToAonCpu(AON__SMM, sharedHandle->enabledWsInfo.aonWakeupSourceMask); + + /*3. Configuration for SMM and PMU. */ + PMU_UpdateVDDCoreInLpMode(AON__PMU, (uint8_t)config->dpd2VddCoreAonVoltage); + SMM_PowerOffAonSramAutomatically(AON__SMM, (uint8_t)(~(config->aonRamArraysToRetain))); + SMM_EnableMainDomainSramRetention(AON__SMM, config->mainRamArraysToRetain); + SMM_ShutDownBandgapInLowPowerModes(AON__SMM, config->disableBandgap); + SMM_EnableIvsModeForSramRetention(AON__SMM, config->enableIVSMode); + SMM_SwitchToXTAL32(AON__SMM, config->switchToX32K); + if (config->switchToX32K) + { + AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; + } + SMM_StartAonDPD2Sequence(AON__SMM); + + /* 4. Configuration for CMC */ CMC_SetPowerModeProtection(CMC, kCMC_AllowAllLowPowerModes); CMC_SetClockMode(CMC, kCMC_GateAllSystemClocksEnterLowPowerMode); CMC_SetGlobalPowerMode(CMC, kCMC_DeepPowerDown); - sharedHandle->requestCM33Start = false; - sharedHandle->targetPowerMode = kPower_DeepPowerDown2; - - if (config->disableFRO10M) + + if (sharedHandle->cm0pWFI == false) { - AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; - AON__CGU->CLK_CONFIG = (AON__CGU->CLK_CONFIG & ~CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) | CGU_CLK_CONFIG_ROOT_CLK_SEL(3U); - AON__CGU->CLK_CONFIG &= ~(CGU_CLK_CONFIG_FRO10M_EN_MASK | CGU_CLK_CONFIG_FRO2M_EN_MASK); - } - /* 4. Software configuration for CM33. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __ISB(); - __WFI(); + return kStatus_Power_CM0PNotWFI; + } + else + { + if (config->disableFRO10M) + { + AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; + AON__CGU->CLK_CONFIG = + (AON__CGU->CLK_CONFIG & ~CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) | CGU_CLK_CONFIG_ROOT_CLK_SEL(3U); + AON__CGU->CLK_CONFIG &= ~(CGU_CLK_CONFIG_FRO10M_EN_MASK | CGU_CLK_CONFIG_FRO2M_EN_MASK); + } - return kStatus_Success; + sharedHandle->requestCM33Start = false; + sharedHandle->targetPowerMode = kPower_DeepPowerDown2; + sharedHandle->previousPowerMode = kPower_DeepPowerDown2; + sharedHandle->cm0pWFI = false; + + /* Disable ADVC in DPD2 mode. */ + if (ADVC_IsEnabled() == true) + { + ADVC_Disable(); + } + + /* 5. Software configuration for CM33. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __ISB(); + __WFI(); + + return kStatus_Success; + } #else status_t status = kStatus_Success; power_low_power_mode_t curLpMode; status = Power_GetCurrentPowerMode(&curLpMode); - + if (status == kStatus_Success) { if (curLpMode != kPower_DeepPowerDown1) @@ -928,10 +1196,21 @@ status_t Power_EnterDeepPowerDown2(power_dpd2_config_t *config) { /* If current system is in DPD1 mode, enter DPD2 from DPD1. */ sharedHandle->targetPowerMode = kPower_DeepPowerDown2; - //patch - uint32_t *ptr = (uint32_t *)0xA0098038; - *ptr |= (1 << 11); // Set the 8th bit (bit 7, as bits are 0-indexed) - /*1. Configuration for SMM. */ + + /*1. Enable wakeup sources for main and aon domain. */ + Power_CheckThenEnableWakeupSource(config->mainWakeupSource); + Power_CheckThenEnableWakeupSource(config->aonWakeupSource); + + SMM_EnableWakeupSourceToMainCpu(AON__SMM, sharedHandle->enabledWsInfo.mainWakeupSourceMask); + SMM_EnableWakeupSourceToAonCpu(AON__SMM, sharedHandle->enabledWsInfo.aonWakeupSourceMask); + + /*2. Configuration for SMM and PMU. */ + /* Disable ADVC in DPD2 mode. */ + if (ADVC_IsEnabled() == true) + { + ADVC_Disable(); + } + PMU_UpdateVDDCoreInLpMode(AON__PMU, (uint8_t)config->dpd2VddCoreAonVoltage); SMM_PowerOffAonSramAutomatically(AON__SMM, (uint8_t)(~(config->aonRamArraysToRetain))); SMM_EnableMainDomainSramRetention(AON__SMM, config->mainRamArraysToRetain); SMM_ShutDownBandgapInLowPowerModes(AON__SMM, config->disableBandgap); @@ -940,19 +1219,48 @@ status_t Power_EnterDeepPowerDown2(power_dpd2_config_t *config) if (config->switchToX32K) { AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; - } - SMM_StartAonDPD2Sequence(AON__SMM); - (void)AON__SMM->PWDN_CONFIG; + } + if (config->disableFRO10M) { AON__CGU->CLK_CONFIG |= CGU_CLK_CONFIG_ROOT_AUX_CLK_EN_MASK; - AON__CGU->CLK_CONFIG = (AON__CGU->CLK_CONFIG & ~CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) | CGU_CLK_CONFIG_ROOT_CLK_SEL(3U); + AON__CGU->CLK_CONFIG = + (AON__CGU->CLK_CONFIG & ~CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) | CGU_CLK_CONFIG_ROOT_CLK_SEL(3U); AON__CGU->CLK_CONFIG &= ~(CGU_CLK_CONFIG_FRO10M_EN_MASK | CGU_CLK_CONFIG_FRO2M_EN_MASK); - } + } + + sharedHandle->previousPowerMode = kPower_DeepPowerDown2; + + /*3. CM0P. Execute WFI */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __ISB(); - __WFI(); + sharedHandle->cm0pWFI = true; + + if ((config->wakeToDpd1 == true) && (config->aonRamArraysToRetain != kPower_AonDomainNoneRams)) + { + if (Power_PushContext((uint32_t)sharedHandle) == 0UL) + { + AON__SMM->PWDN_CONFIG |= SMM_PWDN_CONFIG_DPD2_AON_MASK; + (void)AON__SMM->PWDN_CONFIG; + __DSB(); + __ISB(); + __WFI(); + } + AON__SMM->MSB_BCKP1 = SMM_MSB_BCKP1_MSB1(0UL); + g_Handle_Offset = (uint32_t)((uint32_t)sharedHandle - POWER_SHARED_RAM_BASE_ADDR); + + return kStatus_Power_WakeupFromDPD2; + } + else + { + AON__SMM->MSB_BCKP1 = SMM_MSB_BCKP1_MSB1(0UL); + AON__SMM->PWDN_CONFIG |= SMM_PWDN_CONFIG_DPD2_AON_MASK; + (void)AON__SMM->PWDN_CONFIG; + __DSB(); + __ISB(); + __WFI(); + + return kStatus_Fail; + } } } @@ -962,11 +1270,11 @@ status_t Power_EnterDeepPowerDown2(power_dpd2_config_t *config) /*! * brief Enter Deep Power Down 3 mode. - * + * * This function attempts to put the system into Deep Power Down 3 mode with the provided configuration. - * + * * param[in] config Pointer to the Deep Power Down 3 mode configuration. - * + * * retval kStatus_Success Successfully entered Deep Power Down 3 mode. * retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -976,29 +1284,23 @@ status_t Power_EnterDeepPowerDown3(power_dpd3_config_t *config) power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); memcpy(sharedHandle->lpConfig, config, sizeof(power_dpd3_config_t)); #if __CORTEX_M == 33U - - /* 1. Configuration of SMM. */ - SMM_StartAonShutDownSequence(AON__SMM); - - /*2. Software configuration for CM0P. */ + /*1. Inform CM0P that CM33 request to set whole system into DPD3 mode, require CM0P execute WFI. */ if (sharedHandle->requestCM33Start != true) { /* Inform CM0P to execute WFI. */ - power_mu_message_t msg = { - .strcutFormat = { - .syncCode = 0x5A, - .type = kPower_MsgTypeRequest, - .direction = kPower_MsgDirMainToAon, - .reqestLowPowerMode = kPower_DeepPowerDown3, - .sharedHandleAddrOff = 0UL, - } - }; + power_mu_message_t msg = {.strcutFormat = { + .syncCode = 0x5A, + .type = kPower_MsgTypeRequest, + .direction = kPower_MsgDirMainToAon, + .reqestLowPowerMode = kPower_DeepPowerDown3, + .lowHalfContent.halfWordValueMask = 0UL, + }}; g_powerMuTransferState = kPower_MuTransferStart; - g_powerRequestMuMsg = msg; - MU_SendMsg(MUA, sharedHandle->muChannelId, (uint32_t)msg.wordFormat); + g_powerRequestMuMsg = msg; + MU_SendMsg(POWER_USED_MU, sharedHandle->muChannelId, (uint32_t)msg.wordFormat); /* Waiting for response from CM0P. */ - while(g_powerMuTransferState == kPower_MuTransferStart) + while (g_powerMuTransferState == kPower_MuTransferStart) { } if (g_powerMuTransferState == kPower_MuTransferWrong) @@ -1012,21 +1314,39 @@ status_t Power_EnterDeepPowerDown3(power_dpd3_config_t *config) g_powerMuTransferState = kPower_MuTransferIdle; } - /*3. Configuration of CMC */ + /*2. Enable wakeup source to wakeup the whole system. */ + Power_CheckThenEnableWakeupSource(config->wakeupSource); + SMM_EnableWakeupSourceToMainCpu(AON__SMM, sharedHandle->enabledWsInfo.mainWakeupSourceMask); + SMM_EnableWakeupSourceToAonCpu(AON__SMM, sharedHandle->enabledWsInfo.aonWakeupSourceMask); + + /*3. Configuration of SMM. */ + SMM_StartAonShutDownSequence(AON__SMM); + + /*4. Configuration of CMC */ CMC_SetPowerModeProtection(CMC, kCMC_AllowAllLowPowerModes); CMC_SetClockMode(CMC, kCMC_GateAllSystemClocksEnterLowPowerMode); CMC_SetGlobalPowerMode(CMC, kCMC_DeepPowerDown); - sharedHandle->requestCM33Start = false; - sharedHandle->targetPowerMode = kPower_DeepPowerDown3; - /* 4. Software configuration for CM33. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __ISB(); - __WFI(); + + if (sharedHandle->cm0pWFI == false) + { + return kStatus_Power_CM0PNotWFI; + } + else + { + sharedHandle->cm0pWFI = false; + sharedHandle->requestCM33Start = false; + sharedHandle->targetPowerMode = kPower_DeepPowerDown3; + sharedHandle->previousPowerMode = kPower_DeepPowerDown3; + /* 5. Software configuration for CM33. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __ISB(); + __WFI(); + } return kStatus_Success; #else - status_t status = kStatus_Success; + status_t status = kStatus_Success; sharedHandle->requestCM33Start = true; status = Power_ReqestCM33StartLpSeq(kPower_DeepPowerDown3); @@ -1034,6 +1354,7 @@ status_t Power_EnterDeepPowerDown3(power_dpd3_config_t *config) if (status == kStatus_Success) { SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + sharedHandle->cm0pWFI = true; __DSB(); __ISB(); __WFI(); @@ -1045,11 +1366,11 @@ status_t Power_EnterDeepPowerDown3(power_dpd3_config_t *config) /*! * brief Enter Shutdown mode. - * + * * This function attempts to put the system into Shutdown mode with the provided configuration. - * + * * param[in] config Pointer to the Shutdown mode configuration. - * + * * retval kStatus_Success Successfully entered Shutdown mode. * retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -1060,28 +1381,23 @@ status_t Power_EnterShutDown(power_sd_config_t *config) memcpy(sharedHandle->lpConfig, config, sizeof(power_sd_config_t)); #if __CORTEX_M == 33U - /* 1. Configuration of SMM. */ - SMM_StartAonShutDownSequence(AON__SMM); - - /*2. Software configuration for CM0P. */ + /*1. Inform CM0P that CM33 request to set whole system into SD mode, require CM0P execute WFI. */ if (sharedHandle->requestCM33Start != true) { /* Inform CM0P to execute WFI. */ - power_mu_message_t msg = { - .strcutFormat = { - .syncCode = 0x5A, - .type = kPower_MsgTypeRequest, - .direction = kPower_MsgDirMainToAon, - .reqestLowPowerMode = kPower_ShutDown, - .sharedHandleAddrOff = 0UL, - } - }; + power_mu_message_t msg = {.strcutFormat = { + .syncCode = 0x5A, + .type = kPower_MsgTypeRequest, + .direction = kPower_MsgDirMainToAon, + .reqestLowPowerMode = kPower_ShutDown, + .lowHalfContent.halfWordValueMask = 0UL, + }}; g_powerMuTransferState = kPower_MuTransferStart; - g_powerRequestMuMsg = msg; - MU_SendMsg(MUA, sharedHandle->muChannelId, (uint32_t)msg.wordFormat); + g_powerRequestMuMsg = msg; + MU_SendMsg(POWER_USED_MU, sharedHandle->muChannelId, (uint32_t)msg.wordFormat); /* Waiting for response from CM0P. */ - while(g_powerMuTransferState == kPower_MuTransferStart) + while (g_powerMuTransferState == kPower_MuTransferStart) { } if (g_powerMuTransferState == kPower_MuTransferWrong) @@ -1095,25 +1411,45 @@ status_t Power_EnterShutDown(power_sd_config_t *config) g_powerMuTransferState = kPower_MuTransferIdle; } - AON__SMM->RTC_DCDC_CNTRL &= ~(SMM_RTC_DCDC_CNTRL_LDO_EN_MASK); - AON__SMM->RTC_XTAL_CONFG1 &= ~SMM_RTC_XTAL_CONFG1_XTAL_EN_MASK; - AON__SMM->RTC_XTAL_CONFG2 &= ~(SMM_RTC_XTAL_CONFG2_CAP_BNK_EN_MASK | SMM_RTC_XTAL_CONFG2_SOX_EN_MASK); - AON__SMM->RTC_DCDC_CNTRL |= SMM_RTC_DCDC_CNTRL_LDO_PULDWN_EN_MASK; - /*3. Configuration of CMC */ + /*2. Enable wakeup source to wakeup the whole system. */ + Power_CheckThenEnableWakeupSource(config->wakeupSource); + SMM_EnableWakeupSourceToMainCpu(AON__SMM, sharedHandle->enabledWsInfo.mainWakeupSourceMask); + SMM_EnableWakeupSourceToAonCpu(AON__SMM, sharedHandle->enabledWsInfo.aonWakeupSourceMask); + + /*3. Configuration of SMM and PMU. */ + + PMU_UpdateFRO16KFreq(AON__PMU, config->fro16KOutputFreq); + PMU_UpdateWakeupTime(AON__PMU, 0x7F8); + /* Clean all settings of RTC. */ + AON__SMM->RTC_DCDC_CNTRL = 0xe00; + AON__SMM->RTC_XTAL_CONFG1 = 0x0UL; + AON__SMM->RTC_XTAL_CONFG2 = 0x0UL; + SMM_StartAonShutDownSequence(AON__SMM); + + /*4. Configuration of CMC */ CMC_SetPowerModeProtection(CMC, kCMC_AllowAllLowPowerModes); CMC_SetClockMode(CMC, kCMC_GateAllSystemClocksEnterLowPowerMode); CMC_SetGlobalPowerMode(CMC, kCMC_DeepPowerDown); - sharedHandle->requestCM33Start = false; - sharedHandle->targetPowerMode = kPower_ShutDown; - /* 4. Software configuration for CM33. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __ISB(); - __WFI(); - return kStatus_Success; + if (sharedHandle->cm0pWFI == false) + { + return kStatus_Power_CM0PNotWFI; + } + else + { + sharedHandle->requestCM33Start = false; + sharedHandle->targetPowerMode = kPower_ShutDown; + sharedHandle->previousPowerMode = kPower_ShutDown; + /* 5. Software configuration for CM33. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __ISB(); + __WFI(); + return kStatus_Success; + } + #elif __CORTEX_M == 0U - status_t status = kStatus_Success; + status_t status = kStatus_Success; sharedHandle->requestCM33Start = true; status = Power_ReqestCM33StartLpSeq(kPower_ShutDown); @@ -1121,6 +1457,7 @@ status_t Power_EnterShutDown(power_sd_config_t *config) if (status == kStatus_Success) { SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + sharedHandle->cm0pWFI = true; __DSB(); __ISB(); __WFI(); @@ -1130,96 +1467,607 @@ status_t Power_EnterShutDown(power_sd_config_t *config) #endif /* __CORTEX_M == 0U */ } +/*! + * brief Save current context into stack. + * --------- <-----High address + | D15 | ----- + --------- | + | D14 | | + --------- | + | D13 | | + --------- | + | D12 | | + --------- |---- Only CM33 + | D11 | | + --------- | + | D10 | | + --------- | + | D9 | | + --------- | + | D8 | ----- + --------- + | LR | + --------- + | R12 | + --------- + | R11 | + --------- + | R10 | + --------- + | R9 | + --------- + | R8 | + --------- + | R7 | + --------- + | R6 | + --------- + | R5 | + --------- + | R4 | + --------- + | handle| + | value | + --------- + | handle| + | addr | + --------- + | ASPR | + --------- + | PSR | + --------- + |PRIMASK| + --------- + |CONTROL| + --------- <------ SP Address saved in backup register + * param handleAddr The address of handle. + * + * retval 0 Return 0 before entering low power modes. + * retval 1 Return 1 after waking up from low power modes. + */ +uint32_t Power_PushContext(uint32_t handleAddr) +{ + /* Stack layout: + --------- <-----High address + | D15 | ----- + --------- | + | D14 | | + --------- | + | D13 | | + --------- | + | D12 | | + --------- |---- Only CM33 + | D11 | | + --------- | + | D10 | | + --------- | + | D9 | | + --------- | + | D8 | ----- + --------- + | LR | + --------- + | R12 | + --------- + | R11 | + --------- + | R10 | + --------- + | R9 | + --------- + | R8 | + --------- + | R7 | + --------- + | R6 | + --------- + | R5 | + --------- + | R4 | + --------- + | handle| + | value | + --------- + | handle| + | addr | + --------- + | ASPR | + --------- + | PSR | + --------- + |PRIMASK| + --------- + |CONTROL| + --------- <------ SP Address saved in backup register + */ +#ifdef __ARMVFP__ + /* push FPU registers. */ + asm volatile("VSTMDB sp!, {D15}"); + asm volatile("VSTMDB sp!, {D14}"); + asm volatile("VSTMDB sp!, {D13}"); + asm volatile("VSTMDB sp!, {D12}"); + asm volatile("VSTMDB sp!, {D11}"); + asm volatile("VSTMDB sp!, {D10}"); + asm volatile("VSTMDB sp!, {D9}"); + asm volatile("VSTMDB sp!, {D8}"); +#endif + /* push LR */ + asm volatile("PUSH {lr}"); + + /* push r12 */ + asm volatile("PUSH {r0}"); + asm volatile("MOV r0, r12"); + asm volatile("POP {r1}"); + asm volatile("PUSH {r0}"); + asm volatile("MOV r12, r1"); + + /* push r11, r10, r9, r8. */ + asm volatile("MOV r0, r8"); + asm volatile("MOV r1, r9"); + asm volatile("MOV r2, r10"); + asm volatile("MOV r3, r11"); + asm volatile("PUSH {r0-r3}"); + + /* push r7, r6, r5, r4. */ + asm volatile("PUSH {r4-r7}"); + + /* push value of current handle.*/ + asm volatile("MOV r0, r12"); + asm volatile("LDR r1, [r0, #40]"); /* Latest word */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #36]"); /* handle->enabledWsInfo.mainWakeupSourceMask. */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #32]"); /* handle->enabledWsInfo.aonWakeupSourceMask. */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #28]"); /* handle->cm0pUserData. */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #24]"); /* handle->cm0pCallback. */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #20]"); /* handle->cm33UserData. */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #16]"); /* handle->cm33Callback. */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #12]"); /* handle->lpConfig[3]. */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #8]"); /* handle->lpConfig[2]. */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #4]"); /* handle->lpConfig[1]. */ + asm volatile("PUSH {r1}"); + asm volatile("LDR r1, [r0, #0]"); /* handle->lpConfig[0]. */ + asm volatile("PUSH {r1}"); + asm volatile("PUSH {r0}"); + + /* push aspr, psr, PRIMASK, CONTROL */ + asm volatile("MRS r0, CONTROL"); + asm volatile("MRS r1, PRIMASK"); + asm volatile("MRS r2, psr"); + asm volatile("MRS r3, apsr"); + asm volatile("PUSH {r0-r3}"); + + /* save current sp to backup register */ +#if __CORTEX_M == 33U + asm volatile("MOV R0, SP"); + asm volatile("UXTH R1, R0"); + asm volatile("LDR R2, =0xA009A034"); + asm volatile("STR R1, [R2]"); + asm volatile("LSRS R1, R0, #16"); + asm volatile("LDR R2, =0xA009A038"); + asm volatile("STR R1, [R2]"); +#else + asm volatile("MOV R0, SP"); + asm volatile("LDR R2, =0xA009A030"); + asm volatile("STR R0, [R2]"); +#endif + + asm volatile("MOVS R0, #0"); + asm volatile("BX LR"); + + return 0; +} + +#define POWER_BCKP1_MSB_VALUE (uint32_t)(AON__SMM->MSB_BCKP1 & SMM_MSB_BCKP1_MSB1_MASK) + +#define POWER_BCKP2_VALUE \ + (uint32_t)((AON__SMM->LSB_BCKP2 & SMM_LSB_BCKP2_LSB2_MASK) | \ + ((AON__SMM->MSB_BCKP2 & SMM_MSB_BCKP2_MSB2_MASK) << 16UL)) + +/*! + * brief Restore saved context from stack. + */ +void Power_LowPowerBoot(void) +{ +#if __CORTEX_M == 33U + if (POWER_BCKP2_VALUE != 0UL) + { + AON__SMM->LSB_BCKP1 = 0x5A5A; + asm volatile("MOV sp, %[input]" + : // no C variable outputs + : [input] "r"(POWER_BCKP2_VALUE) + : // No need to tell nothing to the compiler + ); +#else + if (POWER_BCKP1_MSB_VALUE != 0UL) + { + asm volatile("MOV sp, %[input]" + : // no C variable outputs + : [input] "r"(POWER_BCKP1_MSB_VALUE) + : // No need to tell nothing to the compiler + ); +#endif + + asm volatile("POP {r0-r3}"); + asm volatile("MSR CONTROL, r0"); + asm volatile("MSR PRIMASK, r1"); +#ifdef __IAR_SYSTEMS_ICC__ + __asm volatile("MSR psr, r2"); + __asm volatile("MSR APSR, r3"); +#else + __asm volatile("MSR psr_nzcvq, r2"); + __asm volatile("MSR APSR_nzcvq, r3"); +#endif + + /* Restore handle value. */ + asm volatile("POP {r0}"); /* handle address. */ + asm volatile("POP {r1-r7}"); /* first 7 words of handle. */ + asm volatile("STR r1, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("STR r2, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("STR r3, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("STR r4, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("STR r5, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("STR r6, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("STR r7, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("POP {r1-r4}"); /*left 4 words of handle. */ + asm volatile("STR r1, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("STR r2, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("STR r3, [r0]"); +#if __IAR_SYSTEMS_ICC__ + asm volatile("ADDS r0, r0, #4"); +#else + asm volatile("ADD r0, r0, #4"); +#endif + asm volatile("STR r4, [r0]"); + + /* Restore r4-r7. */ + asm volatile("POP {r4-r7}"); + + /* Restore r8-r12. */ + asm volatile("POP {r0-r4}"); + asm volatile("MOV r8, r0"); + asm volatile("MOV r9, r1"); + asm volatile("MOV r10, r2"); + asm volatile("MOV r11, r3"); + asm volatile("MOV r12, r4"); + + /* Restore LR */ + asm volatile("POP {r0}"); /* saved PC */ + asm volatile("MOV lr, r0"); +#ifdef __ARMVFP__ + asm volatile("VLDMIA sp!, {D8}"); + asm volatile("VLDMIA sp!, {D9}"); + asm volatile("VLDMIA sp!, {D10}"); + asm volatile("VLDMIA sp!, {D11}"); + asm volatile("VLDMIA sp!, {D12}"); + asm volatile("VLDMIA sp!, {D13}"); + asm volatile("VLDMIA sp!, {D14}"); + asm volatile("VLDMIA sp!, {D15}"); +#endif + asm volatile("MOVS r0, #1"); + asm volatile("BX lr"); + } +} + /*! * brief Callback function for handling power MU messages. - * + * * This function is called when a power MU message is received. It processes the message * based on the given message content and the channel ID. - * + * * param[in] message The received power MU message. * param[in] channelId The ID of the channel on which the message was received. - * + * * retval None This function does not return a value. */ -void Power_MuMessageCallback(uint32_t message, uint32_t channelId) +status_t Power_MuMessageCallback(uint32_t message, uint32_t channelId) +{ + status_t status = kStatus_Success; + power_mu_message_type_t msgType = Power_GetMuMessageType(message); + if (msgType == kPower_MsgTypeSync) + { + status = Power_MuSyncCallback(message, channelId); + } + else if (msgType == kPower_MsgTypeRequest) + { + status = Power_InterpretRequest(message); + } + else + { + status = Power_InterpretResponse(message); + } + + return status; +} + +/*! + * brief Get type of received MU message. + * + * param message The received message. + * + * return The type of MU message. + */ +power_mu_message_type_t Power_GetMuMessageType(uint32_t message) { power_mu_message_t msg; - uint32_t tmp32; - power_mu_message_type_t resType; - bool userAllowed = false; msg.wordFormat = message; + + return msg.strcutFormat.type; +} + +/*! + * brief Get direction of received MU message. + * + * param message The received message. + * + * return The direction of MU message. + */ +power_mu_message_direction_t Power_GetMuMessageDir(uint32_t message) +{ + power_mu_message_t msg; + msg.wordFormat = message; + + return msg.strcutFormat.direction; +} + +/*! + * brief The callback when one core want to sync with another, that is when the message type is #kPower_MsgTypeSync. + * + * param message Received message value. + * param channelId The channel which transfer the message. + * + * retval kStatus_Power_SyncFailed Failed to sync between dual cores. + * retval kStatus_Success Sync dual cores successfully. + */ +status_t Power_MuSyncCallback(uint32_t message, uint32_t channelId) +{ + power_mu_message_type_t resType = kPower_MsgTypeACK; + power_mu_message_t msg; + msg.wordFormat = message; power_low_power_mode_t targetLowPowerMode = msg.strcutFormat.reqestLowPowerMode; - uint32_t lpConfigAddr = POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset + offsetof(power_handle_t, lpConfig[0]); - power_user_callback_t curCallback = NULL; - void *curCallbackData = NULL; - - if (msg.strcutFormat.type == kPower_MsgTypeRequest) + power_mu_message_direction_t responseDir = kPower_MsgDirAonToMain; + uint16_t lowerHalfWordValue = 0U; + + if (Power_VerifyMuMessage(message) != kStatus_Success) { - if (Power_VerifyMuMessage(message, true) != kStatus_Success) + lowerHalfWordValue |= kPower_MsgNACK_WrongMsgReceived; + } + else + { + g_Handle_Offset = msg.strcutFormat.lowHalfContent.sharedHandleAddrOff; + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + if (sharedHandle->muChannelId != channelId) { - resType = kPower_MsgTypeNACK; + lowerHalfWordValue |= kPower_MsgNACK_ChannelMisMatch; } - else + if (targetLowPowerMode != kPower_Active) { - if (msg.strcutFormat.init == true) - { - g_Handle_Offset = msg.strcutFormat.sharedHandleAddrOff; - resType = kPower_MsgTypeACK; - } - else - { - power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + lowerHalfWordValue |= kPower_MsgNACK_TargetModeNotAllowed; + } + } + + if (Power_GetMuMessageDir(message) == kPower_MsgDirAonToMain) + { + responseDir = kPower_MsgDirMainToAon; + } + if (lowerHalfWordValue != 0U) + { + resType = kPower_MsgTypeNACK; + } + + uint32_t tmp32 = Power_PopulateMuMessage(resType, responseDir, targetLowPowerMode, lowerHalfWordValue); + MU_SendMsg(POWER_USED_MU, channelId, tmp32); + + if (lowerHalfWordValue != 0U) + { + return kStatus_Power_SyncFailed; + } + else + { + return kStatus_Success; + } +} + +/*! + * brief Interpret request message from requester. + * + * param message The message which request from requester. + * + * retval kStatus_POWER_MuTransferError Something wrong during transfer. + * retval kStatus_POWER_RequestNotAllowed Request is not allowed. + * retval kStatus_Success Interpret request message successfully. + */ +status_t Power_InterpretRequest(uint32_t message) +{ + power_mu_message_type_t resType = kPower_MsgTypeACK; + power_mu_message_direction_t responseDir = kPower_MsgDirAonToMain; + power_user_callback_t curCallback = NULL; + void *curCallbackData = NULL; + uint32_t lpConfigAddr = POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset + offsetof(power_handle_t, lpConfig[0]); + power_mu_message_t msg; + msg.wordFormat = message; + power_low_power_mode_t targetLowPowerMode = msg.strcutFormat.reqestLowPowerMode; + bool userAllowed = false; + uint16_t lowerHalfWordValue = 0U; + status_t status = kStatus_Success; + uint32_t channelId = 0U; + power_handle_t *sharedHandle = (power_handle_t *)(POWER_SHARED_RAM_BASE_ADDR + g_Handle_Offset); + + if (Power_VerifyMuMessage(message) != kStatus_Success) + { + lowerHalfWordValue |= kPower_MsgNACK_WrongMsgReceived; + status = kStatus_POWER_MuTransferError; + } + else + { + channelId = sharedHandle->muChannelId; #if __CORTEX_M == 33U - curCallback = sharedHandle->cm33Callback; - curCallbackData = sharedHandle->cm33UserData; + curCallback = sharedHandle->cm33Callback; + curCallbackData = sharedHandle->cm33UserData; #else - curCallback = sharedHandle->cm0pCallback; - curCallbackData = sharedHandle->cm0pUserData; + curCallback = sharedHandle->cm0pCallback; + curCallbackData = sharedHandle->cm0pUserData; #endif - if (curCallback != NULL) - { - userAllowed = curCallback(targetLowPowerMode, (void *)lpConfigAddr, curCallbackData); - } - - resType = ((userAllowed == false) ? kPower_MsgTypeNACK : kPower_MsgTypeACK); - } + if (curCallback != NULL) + { + userAllowed = curCallback(targetLowPowerMode, (void *)lpConfigAddr, curCallbackData); } - /* Return response to CM0P */ - tmp32 = Power_PopulateMuMessage(resType, kPower_MsgDirAonToMain, targetLowPowerMode, false, msg.strcutFormat.sharedHandleAddrOff); - MU_SendMsg(POWER_USED_MU, channelId, tmp32); - if (userAllowed) + if (userAllowed == false) { + lowerHalfWordValue |= kPower_MsgNACK_TargetModeNotAllowed; + status = kStatus_POWER_RequestNotAllowed; + } + } + + if (lowerHalfWordValue != 0UL) + { + resType = kPower_MsgTypeNACK; + } + + if (Power_GetMuMessageDir(message) == kPower_MsgDirAonToMain) + { + responseDir = kPower_MsgDirMainToAon; + } + uint32_t tmp32 = Power_PopulateMuMessage(resType, responseDir, targetLowPowerMode, lowerHalfWordValue); + MU_SendMsg(POWER_USED_MU, channelId, tmp32); + + /* Until now, response already send to requester. */ + if (userAllowed && (resType != kPower_MsgTypeNACK)) + { #if __CORTEX_M == 33U - (void)Power_EnterLowPowerMode(targetLowPowerMode, (void *)lpConfigAddr); + (void)Power_EnterLowPowerMode(targetLowPowerMode, (void *)lpConfigAddr); #elif __CORTEX_M == 0U - if ((targetLowPowerMode == kPower_PowerDown2) || ((targetLowPowerMode >= kPower_DeepPowerDown2) && (targetLowPowerMode < kPower_Active))) + if ((targetLowPowerMode == kPower_PowerDown2) || + ((targetLowPowerMode >= kPower_DeepPowerDown2) && (targetLowPowerMode < kPower_Active))) + { + /* If CM0P approve to enter target low power mode, execute WFI. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + sharedHandle->cm0pWFI = true; + sharedHandle->targetPowerMode = targetLowPowerMode; + if (targetLowPowerMode == kPower_DeepPowerDown2) { - /* If CM0P approve to enter target low power mode, execute WFI. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __ISB(); - __WFI(); + if ((((power_dpd2_config_t *)lpConfigAddr)->aonRamArraysToRetain != kPower_AonDomainNoneRams) && + (((power_dpd2_config_t *)lpConfigAddr)->wakeToDpd1 == true)) + { + if (Power_PushContext((uint32_t)sharedHandle) == 0UL) + { + __DSB(); + __ISB(); + __WFI(); + } + AON__SMM->MSB_BCKP1 = SMM_MSB_BCKP1_MSB1(0UL); + g_Handle_Offset = (uint32_t)((uint32_t)sharedHandle - POWER_SHARED_RAM_BASE_ADDR); + sharedHandle->previousPowerMode = targetLowPowerMode; + } } + else + { + __DSB(); + __ISB(); + __WFI(); + } + } #endif /* __CORTEX_M */ + } - } + return status; +} + +/*! + * brief Interpre responce of message. + * + * param message The message which responce to requester. + * + * retval kStatus_POWER_MuTransferError Something wrong during transfer. + * retval kStatus_POWER_RequestNotAllowed Request is not allowed. + * retval kStatus_Power_NackWithMultiReasons Responce as NACK with multiple reasons. + * retval kStatus_Success Interpret response message successfully. + */ +status_t Power_InterpretResponse(uint32_t message) +{ + status_t status = kStatus_Success; + + if (Power_VerifyMuMessage(message) != kStatus_Success) + { + g_powerMuTransferState = kPower_MuTransferWrong; + status = kStatus_POWER_MuTransferError; + } + + if (Power_GetMuMessageType(message) == kPower_MsgTypeACK) + { + g_powerMuTransferState = kPower_MuTransferEndWithACK; } else { - /* Handle response from CM0P */ - if (Power_VerifyMuMessage(message, false) != kStatus_Success) + g_powerMuTransferState = kPower_MuTransferEndWithNACK; + power_mu_nack_reason_t reason; + reason = Power_GetMuNackReason(message); + if (reason == kPower_MsgNACK_TargetModeNotAllowed) { - g_powerMuTransferState = kPower_MuTransferWrong; + status = kStatus_POWER_RequestNotAllowed; } - if (msg.strcutFormat.type == kPower_MsgTypeACK) + else if ((reason == kPower_MsgNACK_ChannelMisMatch) || (reason == kPower_MsgNACK_WrongMsgReceived)) { - g_powerMuTransferState = kPower_MuTransferEndWithACK; + status = kStatus_POWER_MuTransferError; } else { - g_powerMuTransferState = kPower_MuTransferEndWithNACK; + status = kStatus_Power_NackWithMultiReasons; } } -} + return status; +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_power.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_power.h index bfa021960..9583c3731 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_power.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_power.h @@ -9,6 +9,8 @@ #include "fsl_common.h" +#include "fsl_pmu.h" + /*! * @addtogroup power * @{ @@ -20,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief power driver version 2.0.0. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief power driver version 2.1.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ #if __CORTEX_M == 33U @@ -32,27 +34,34 @@ enum { - kStatus_POWER_MuTransferError = MAKE_STATUS(kStatusGroup_POWER, 0), /*!< Fail due to Mu transfer error. */ - kStatus_POWER_RequestNotAllowed = MAKE_STATUS(kStatusGroup_POWER, 1), /*!< Request not allowed by another core. */ - kStatus_Power_HandleDuplicated = MAKE_STATUS(kStatusGroup_POWER, 2), /*!< Handle already be created. */ - kStatus_Power_NotInTargetMode = MAKE_STATUS(kStatusGroup_POWER, 3), /*!< Not in target low power mode. */ + kStatus_POWER_MuTransferError = MAKE_STATUS(kStatusGroup_POWER, 0), /*!< Fail due to Mu transfer error. */ + kStatus_POWER_RequestNotAllowed = MAKE_STATUS(kStatusGroup_POWER, 1), /*!< Request not allowed by another core. */ + kStatus_Power_HandleDuplicated = MAKE_STATUS(kStatusGroup_POWER, 2), /*!< Handle already be created. */ + kStatus_Power_NotInTargetMode = MAKE_STATUS(kStatusGroup_POWER, 3), /*!< Not in target low power mode. */ + kStatus_Power_NackWithMultiReasons = MAKE_STATUS(kStatusGroup_POWER, 4), /*!< The response is NACK, and serval + reasons cause NACK response. */ + kStatus_Power_SyncFailed = MAKE_STATUS(kStatusGroup_POWER, 5), /*!< Failed to sync dual core. */ + kStatus_Power_CM0PNotWFI = MAKE_STATUS(kStatusGroup_POWER, 6), /*!< CM0P do not execute WFI after approve + to enter target low power mode. */ + kStatus_Power_WakeupFromDPD1 = MAKE_STATUS(kStatusGroup_POWER, 7), /*!< Wakeup from DPD1 mode successfully. */ + kStatus_Power_WakeupFromDPD2 = MAKE_STATUS(kStatusGroup_POWER, 8), /*!< Wakeup from DPD2 mode successfully. */ }; /*! * @brief The enumeration of low power modes. - * + * */ typedef enum _power_low_power_mode { - kPower_Sleep = 0U, /*!< Sleep Mode. */ - kPower_DeepSleep = 1U, /*!< Deep Sleep Mode. */ - kPower_PowerDown1 = 2U, /*!< Power Down Mode 1. */ - kPower_PowerDown2 = 3U, /*!< Power Down Mode 2.*/ - kPower_DeepPowerDown1 = 4U, /*!< Deep Power Down Mode 1. */ - kPower_DeepPowerDown2 = 5U, /*!< Deep Power Down Mode 2. */ - kPower_DeepPowerDown3 = 6U, /*!< Deep Power Down Mode 3. */ - kPower_ShutDown = 7, /*!< ShutDown Mode */ - kPower_Active = 8U, /*!< Active Mode. */ + kPower_Sleep = 0U, /*!< Sleep Mode. */ + kPower_DeepSleep = 1U, /*!< Deep Sleep Mode. */ + kPower_PowerDown1 = 2U, /*!< Power Down Mode 1. */ + kPower_PowerDown2 = 3U, /*!< Power Down Mode 2.*/ + kPower_DeepPowerDown1 = 4U, /*!< Deep Power Down Mode 1. */ + kPower_DeepPowerDown2 = 5U, /*!< Deep Power Down Mode 2. */ + kPower_DeepPowerDown3 = 6U, /*!< Deep Power Down Mode 3. */ + kPower_ShutDown = 7, /*!< ShutDown Mode */ + kPower_Active = 8U, /*!< Active Mode. */ } power_low_power_mode_t; typedef bool (*power_user_callback_t)(power_low_power_mode_t targetPowerMode, void *ptrPowerConfig, void *userData); @@ -62,33 +71,18 @@ typedef bool (*power_user_callback_t)(power_low_power_mode_t targetPowerMode, vo * * @note * bit 7 - 0: aon control bit index; - * bit 15 - 8: wuu control bit index; - * bit 19 - 16: wuu event(0: interrupt, 1: DMA request, 2: trigger event); * bit 23 - 20: external pin edge(1: rising edge, 2: falling edge, 3: any edge); - * bit 27 - 24: Wakeup domain(0: only Main, 1: only Aon, 2: Both Main and Aon), in some low power mode(such as PD2) + * bit 27 - 24: Wakeup domain(0: only Main, 1: only Aon, 2: Both Main and Aon), in some low power mode(such as PD2) * it is possible only wakeup Aon Domain. - * bit 30: external pin or internal module(0: internal module, 1: external pin); - * bit 31: wakeup source in aon domain or cm33 domain(0: In AON domain, 1: In CM33 domain). - * */ -#define POWER_ENCODE_WS(cm33Ws, wuuExtPin, wakeupDomain, pinEdge, wuuEvent, wuuIndex, aonIndex) \ - ((((uint32_t)(cm33Ws) << 31UL) & (0x80000000UL)) | (((uint32_t)(wuuExtPin) << 30UL) & (0x40000000UL)) | \ - (((uint32_t)(pinEdge) << 20UL) & 0xF00000UL) | (((uint32_t)(wuuEvent) << 16UL) & 0xF0000UL) | \ - (((uint32_t)(wuuIndex) << 8UL) & 0xFF00UL) | ((uint32_t)(aonIndex)&0xFFUL) | \ - (((uint32_t)(wakeupDomain) << 24UL) & (0xF000000UL))) - -#define POWER_DECODE_WS(wsCode) \ - aonIndex = (wsCode)&0xFFUL; \ - wuuIndex = ((wsCode)&0xFF00UL) >> 8UL; \ - wuuEvent = ((wsCode)&0xF0000UL) >> 16UL; \ - pinEdge = ((wsCode)&0xF00000UL) >> 20UL; \ - isWuuExtPin = (bool)(((wsCode)&0x40000000UL) != 0UL); \ - isCm33Ws = (bool)(((wsCode)&0x80000000UL) != 0UL); \ - wakeupDomain = ((wsCode)&0xF000000UL) >> 24UL +#define POWER_ENCODE_WS(wakeupDomain, pinEdge, aonIndex) \ + (uint32_t)(((uint32_t)(aonIndex) & 0xFFUL) | (((uint32_t)(pinEdge) << 20UL) & 0xF00000UL) | \ + (((uint32_t)(wakeupDomain) << 24UL) & (0xF000000UL))) -#define POWER_DPD2_WS_BIT_MASK (0xFFUL) -#define POWER_DPD3_WS_BIT_MASK (0x37UL) -#define POWER_SHUTDOWN_WS_BIT_MASK (0x20UL) +#define POWER_DECODE_WS(wsCode) \ + aonIndex = (wsCode) & 0xFFUL; \ + pinEdge = ((wsCode) & 0xF00000UL) >> 20UL; \ + wakeupDomain = ((wsCode) & 0xF000000UL) >> 24UL /*! * @brief The enumeration of wakeup sources for different low power modes. @@ -96,453 +90,171 @@ typedef bool (*power_user_callback_t)(power_low_power_mode_t targetPowerMode, vo */ typedef enum _power_wakeup_source { - kPower_WS_Main_RtcAlarm0 = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 0U), /*!< RTC Alarm0 as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_RtcAlarm0 = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 0U), /*!< RTC Alarm0 as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_RtcAlarm0 = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 0U), /*!< RTC Alarm0 as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_RtcAlarm1 = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 1U), /*!< RTC Alarm1 as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_RtcAlarm1 = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 1U), /*!< RTC Alarm1 as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_RtcAlarm1 = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 1U), /*!< RTC Alarm1 as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_QTimerIrq = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 2U), /*!< QTimer IRQ as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_QTimerIrq = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 2U), /*!< QTimer IRQ as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_QTimerIrq = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 2U), /*!< QTimer IRQ as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_RtcWDT = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 3U), /*!< RTC watch dog as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_RtcWDT = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 3U), /*!< RTC watch dog as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_RtcWDT = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 3U), /*!< RTC watch dog as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_RtcXtalFail = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 4U), /*!< RTC XTAL fail as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_RtcXtalFail = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 4U), /*!< RTC XTAL fail as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_RtcXtalFail = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 4U), /*!< RTC XTAL fail as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_ExternalINTFallEdge = POWER_ENCODE_WS(0U, 0U, 0U, 2U, 0U, 0U, 5U), /*!< External INT falling edge as wakeup - source, only wakeup Main Domain */ - kPower_WS_Aon_ExternalINTFallEdge = POWER_ENCODE_WS(0U, 0U, 1U, 2U, 0U, 0U, 5U), /*!< External INT falling edge as wakeup - source, only wakeup AON Domain */ - kPower_WS_Both_ExternalINTFallEdge = POWER_ENCODE_WS(0U, 0U, 2U, 2U, 0U, 0U, 5U), /*!< External INT falling edge as wakeup - source, wakeup both Main and AON Domains */ - - kPower_WS_Main_ExternalINTRiseEdge = POWER_ENCODE_WS(0U, 0U, 0U, 1U, 0U, 0U, 5U), /*!< External INT rising edge as wakeup - source, only wakeup Main Domain */ - kPower_WS_Aon_ExternalINTRiseEdge = POWER_ENCODE_WS(0U, 0U, 1U, 1U, 0U, 0U, 5U), /*!< External INT rising edge as wakeup - source, only wakeup AON Domain */ - kPower_WS_Both_ExternalINTRiseEdge = POWER_ENCODE_WS(0U, 0U, 2U, 1U, 0U, 0U, 5U), /*!< External INT rising edge as wakeup - source, wakeup both Main and AON Domains */ - - kPower_WS_Main_SMMTimer = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 6U), /*!< Deep sleep counter as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_SMMTimer = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 6U), /*!< Deep sleep counter as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_SMMTimer = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 6U), /*!< Deep sleep counter as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_Comparator = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 7U), /*!< Voltage comparator as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_Comparator = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 7U), /*!< Voltage comparator as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_Comparator = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 7U), /*!< Voltage comparator as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_AonHsGpioWakeup0 = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 8U), /*!< HS_GPIO wakeup0 as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_AonHsGpioWakeup0 = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 8U), /*!< HS_GPIO wakeup0 as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_AonHsGpioWakeup0 = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 8U), /*!< HS_GPIO wakeup0 as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_Lpuart0 = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 9U), /*!< LPUART0 Interrupt as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_Lpuart0 = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 9U), /*!< LPUART0 Interrupt as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_Lpuart0 = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 9U), /*!< LPUART0 Interrupt as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_AdvcOrACMP = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 10U), /*!< ADVC or ACMP as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_AdvcOrACMP = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 10U), /*!< ADVC or ACMP as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_AdvcOrACMP = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 10U), /*!< ADVC or ACMP as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_Lpi2cInt = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 11U), /*!< AON Lpi2c interrupt as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_Lpi2cInt = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 11U), /*!< AON Lpi2c interrupt as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_Lpi2cInt = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 11U), /*!< AON Lpi2c interrupt as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_AdcInt = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 12U), /*!< ADC interrupt as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_AdcInt = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 12U), /*!< ADC interrupt as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_AdcInt = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 12U), /*!< ADC interrupt as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_LptmrInt = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 13U), /*!< LPTMR interrupt as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_LptmrInt = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 13U), /*!< LPTMR interrupt as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_LptmrInt = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 13U), /*!< LPTMR interrupt as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_TamperDetect = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 14U), /*!< Tamper detect as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_TamperDetect = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 14U), /*!< Tamper detect as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_TamperDetect = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 14U), /*!< Tamper detect as wakeup source, - wakeup both Main and AON Domains */ - - kPower_WS_Main_LcdInt = POWER_ENCODE_WS(0U, 0U, 0U, 0U, 0U, 0U, 15U), /*!< LCD interrupt as wakeup source, only - wakeup Main Domain */ - kPower_WS_Aon_LcdInt = POWER_ENCODE_WS(0U, 0U, 1U, 0U, 0U, 0U, 15U), /*!< LCD interrupt as wakeup source, only - wakeup AON Domain */ - kPower_WS_Both_LcdInt = POWER_ENCODE_WS(0U, 0U, 2U, 0U, 0U, 0U, 15U), /*!< LCD interrupt as wakeup source, - wakeup both Main and AON Domains */ - - /* Following wakeup sources reside in CM33 domain and shall not wakeup device from Power Down mode. */ - kPower_WS_Main_P0_0RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 2U, 0U), /*!< Pin P0_0 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_0RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 2U, 0U), /*!< Pin P0_0 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_0RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 2U, 0U), /*!< Pin P0_0 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_0FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 2U, 0U), /*!< Pin P0_0 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_0FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 2U, 0U), /*!< Pin P0_0 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_0FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 2U, 0U), /*!< Pin P0_0 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_0AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 2U, 0U), /*!< Pin P0_0 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_0AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 2U, 0U), /*!< Pin P0_0 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_0AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 2U, 0U), /*!< Pin P0_0 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P0_15RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 6U, 0U), /*!< Pin P0_15 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_15RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 6U, 0U), /*!< Pin P0_15 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_15RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 6U, 0U), /*!< Pin P0_15 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_15FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 6U, 0U), /*!< Pin P0_15 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_15FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 6U, 0U), /*!< Pin P0_15 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_15FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 6U, 0U), /*!< Pin P0_15 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_15AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 6U, 0U), /*!< Pin P0_15 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_15AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 6U, 0U), /*!< Pin P0_15 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_15AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 6U, 0U), /*!< Pin P0_15 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P1_16RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 7U, 0U), /*!< Pin P1_16 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_16RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 7U, 0U), /*!< Pin P1_16 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_16RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 7U, 0U), /*!< Pin P1_16 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_16FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 7U, 0U), /*!< Pin P1_16 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_16FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 7U, 0U), /*!< Pin P1_16 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_16FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 7U, 0U), /*!< Pin P1_16 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_16AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 7U, 0U), /*!< Pin P1_16 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_16AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 7U, 0U), /*!< Pin P1_16 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_16AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 7U, 0U), /*!< Pin P1_16 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P1_17RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 8U, 0U), /*!< Pin P1_17 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_17RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 8U, 0U), /*!< Pin P1_17 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_17RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 8U, 0U), /*!< Pin P1_17 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_17FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 8U, 0U), /*!< Pin P1_17 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_17FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 8U, 0U), /*!< Pin P1_17 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_17FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 8U, 0U), /*!< Pin P1_17 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_17AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 8U, 0U), /*!< Pin P1_17 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_17AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 8U, 0U), /*!< Pin P1_17 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_17AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 8U, 0U), /*!< Pin P1_17 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P0_20RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 9U, 0U), /*!< Pin P0_20 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_20RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 9U, 0U), /*!< Pin P0_20 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_20RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 9U, 0U), /*!< Pin P0_20 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_20FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 9U, 0U), /*!< Pin P0_20 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_20FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 9U, 0U), /*!< Pin P0_20 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_20FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 9U, 0U), /*!< Pin P0_20 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_20AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 9U, 0U), /*!< Pin P0_20 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_20AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 9U, 0U), /*!< Pin P0_20 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_20AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 9U, 0U), /*!< Pin P0_20 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P0_23RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 10U, 0U), /*!< Pin P0_23 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_23RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 10U, 0U), /*!< Pin P0_23 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_23RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 10U, 0U), /*!< Pin P0_23 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_23FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 10U, 0U), /*!< Pin P0_23 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_23FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 10U, 0U), /*!< Pin P0_23 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_23FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 10U, 0U), /*!< Pin P0_23 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_23AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 10U, 0U), /*!< Pin P0_23 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_23AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 10U, 0U), /*!< Pin P0_23 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_23AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 10U, 0U), /*!< Pin P0_23 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P0_3RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 11U, 0U), /*!< Pin P0_3 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_3RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 11U, 0U), /*!< Pin P0_3 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_3RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 11U, 0U), /*!< Pin P0_3 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_3FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 11U, 0U), /*!< Pin P0_3 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_3FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 11U, 0U), /*!< Pin P0_3 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_3FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 11U, 0U), /*!< Pin P0_3 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_3AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 11U, 0U), /*!< Pin P0_3 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_3AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 11U, 0U), /*!< Pin P0_3 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_3AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 11U, 0U), /*!< Pin P0_3 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P0_4RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 12U, 0U), /*!< Pin P0_4 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_4RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 12U, 0U), /*!< Pin P0_4 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_4RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 12U, 0U), /*!< Pin P0_4 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_4FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 12U, 0U), /*!< Pin P0_4 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_4FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 12U, 0U), /*!< Pin P0_4 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_4FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 12U, 0U), /*!< Pin P0_4 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_4AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 12U, 0U), /*!< Pin P0_4 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_4AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 12U, 0U), /*!< Pin P0_4 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_4AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 12U, 0U), /*!< Pin P0_4 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P0_13RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 18U, 0U), /*!< Pin P0_13 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_13RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 18U, 0U), /*!< Pin P0_13 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_13RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 18U, 0U), /*!< Pin P0_13 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_13FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 18U, 0U), /*!< Pin P0_13 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_13FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 18U, 0U), /*!< Pin P0_13 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_13FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 18U, 0U), /*!< Pin P0_13 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_13AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 18U, 0U), /*!< Pin P0_13 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_13AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 18U, 0U), /*!< Pin P0_13 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P0_13AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 18U, 0U), /*!< Pin P0_13 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P1_13RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 19U, 0U), /*!< Pin P1_13 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_13RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 19U, 0U), /*!< Pin P1_13 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_13RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 19U, 0U), /*!< Pin P1_13 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_13FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 19U, 0U), /*!< Pin P1_13 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_13FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 19U, 0U), /*!< Pin P1_13 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_13FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 19U, 0U), /*!< Pin P1_13 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_13AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 19U, 0U), /*!< Pin P1_13 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_13AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 19U, 0U), /*!< Pin P1_13 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_13AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 19U, 0U), /*!< Pin P1_13 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P1_1RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 20U, 0U), /*!< Pin P1_1 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_1RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 20U, 0U), /*!< Pin P1_1 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_1RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 20U, 0U), /*!< Pin P1_1 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_1FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 20U, 0U), /*!< Pin P1_1 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_1FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 20U, 0U), /*!< Pin P1_1 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_1FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 20U, 0U), /*!< Pin P1_1 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_1AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 20U, 0U), /*!< Pin P1_1 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_1AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 20U, 0U), /*!< Pin P1_1 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_1AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 20U, 0U), /*!< Pin P1_1 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P1_2RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 22U, 0U), /*!< Pin P1_2 rising edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_2RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 22U, 0U), /*!< Pin P1_2 rising edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_2RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 22U, 0U), /*!< Pin P1_2 rising edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_2FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 22U, 0U), /*!< Pin P1_2 falling edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_2FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 22U, 0U), /*!< Pin P1_2 falling edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_2FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 22U, 0U), /*!< Pin P1_2 falling edge trigger as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_2AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 22U, 0U), /*!< Pin P1_2 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_2AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 22U, 0U), /*!< Pin P1_2 any edge DMA request as - wakeup source, can be used to wakeup from DS mode. */ - kPower_WS_Main_P1_2AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 22U, 0U), /*!< Pin P1_2 any edge interrupt as - wakeup source, can be used to wakeup from DS mode. */ - - kPower_WS_Main_P1_5RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 23U, 0U), /*!< P1_5 pin rising edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_5RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 23U, 0U), /*!< P1_5 pin rising edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_5RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 23U, 0U), /*!< P1_5 pin rising edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_5FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 23U, 0U), /*!< P1_5 pin falling edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_5FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 23U, 0U), /*!< P1_5 pin falling edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_5FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 23U, 0U), /*!< P1_5 pin falling edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_5AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 23U, 0U), /*!< P1_5 pin any edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_5AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 23U, 0U), /*!< P1_5 pin any edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_5AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 23U, 0U), /*!< P1_5 pin any edge trigger as wakeup source, wakeup Main Domain */ - - kPower_WS_Main_P1_14RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 5U, 0U), /*!< P1_14 pin rising edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_14RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 5U, 0U), /*!< P1_14 pin rising edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_14RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 5U, 0U), /*!< P1_14 pin rising edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_14FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 5U, 0U), /*!< P1_14 pin falling edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_14FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 5U, 0U), /*!< P1_14 pin falling edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_14FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 5U, 0U), /*!< P1_14 pin falling edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_14AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 5U, 0U), /*!< P1_14 pin any edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_14AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 5U, 0U), /*!< P1_14 pin any edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_14AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 5U, 0U), /*!< P1_14 pin any edge trigger as wakeup source, wakeup Main Domain */ - - kPower_WS_Main_P1_19RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 25U, 0U), /*!< P1_19 pin rising edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_19RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 25U, 0U), /*!< P1_19 pin rising edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_19RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 25U, 0U), /*!< P1_19 pin rising edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_19FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 25U, 0U), /*!< P1_19 pin falling edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_19FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 25U, 0U), /*!< P1_19 pin falling edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_19FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 25U, 0U), /*!< P1_19 pin falling edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_19AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 25U, 0U), /*!< P1_19 pin any edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_19AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 25U, 0U), /*!< P1_19 pin any edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_19AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 25U, 0U), /*!< P1_19 pin any edge trigger as wakeup source, wakeup Main Domain */ - - kPower_WS_Main_P1_23RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 26U, 0U), /*!< P1_23 pin rising edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_23RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 26U, 0U), /*!< P1_23 pin rising edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_23RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 26U, 0U), /*!< P1_23 pin rising edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_23FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 26U, 0U), /*!< P1_23 pin falling edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_23FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 26U, 0U), /*!< P1_23 pin falling edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_23FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 26U, 0U), /*!< P1_23 pin falling edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_23AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 26U, 0U), /*!< P1_23 pin any edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_23AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 26U, 0U), /*!< P1_23 pin any edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_23AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 26U, 0U), /*!< P1_23 pin any edge trigger as wakeup source, wakeup Main Domain */ - - kPower_WS_Main_P1_22RiseEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 0U, 27U, 0U), /*!< P1_22 pin rising edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_22RiseEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 1U, 27U, 0U), /*!< P1_22 pin rising edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_22RiseEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 1U, 2U, 27U, 0U), /*!< P1_22 pin rising edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_22FallEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 0U, 27U, 0U), /*!< P1_22 pin falling edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_22FallEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 1U, 27U, 0U), /*!< P1_22 pin falling edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_22FallEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 2U, 2U, 27U, 0U), /*!< P1_22 pin falling edge trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_22AnyEdgeInt = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 0U, 27U, 0U), /*!< P1_22 pin any edge interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_22AnyEdgeDma = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 1U, 27U, 0U), /*!< P1_22 pin any edge DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_P1_22AnyEdgeTrig = POWER_ENCODE_WS(1U, 1U, 0U, 3U, 2U, 27U, 0U), /*!< P1_22 pin any edge trigger as wakeup source, wakeup Main Domain */ - - kPower_WS_Main_Lptmr0Int = POWER_ENCODE_WS(1U, 0U, 0U, 0U, 0U, 6U, 0U), /*!< LPTMR0 interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_Cmp0Int = POWER_ENCODE_WS(1U, 0U, 0U, 0U, 0U, 8U, 0U), /*!< CMP0 interrupt as wakeup source, wakeup Main Domain */ - kPower_WS_Main_Lptmr0Dma = POWER_ENCODE_WS(1U, 0U, 0U, 0U, 1U, 4U, 0U), /*!< LPTMR0 DMA as wakeup source, wakeup Main Domain */ - kPower_WS_Main_Lptmr0Trig = POWER_ENCODE_WS(1U, 0U, 0U, 0U, 1U, 6U, 0U), /*!< LPTMR0 trigger as wakeup source, wakeup Main Domain */ - kPower_WS_Main_Cmp0DMA = POWER_ENCODE_WS(1U, 0U, 0U, 0U, 1U, 8U, 0U), /*!< CMP0 DMA as wakeup source, wakeup Main Domain */ + kPower_WS_NONE = 0xFFFFFFFFUL, + + kPower_WS_Main_RtcAlarm0 = POWER_ENCODE_WS(0U, 0U, 0U), /*!< RTC Alarm0 as wakeup source, only wakeup Main Domain */ + kPower_WS_Aon_RtcAlarm0 = POWER_ENCODE_WS(1U, 0U, 0U), /*!< RTC Alarm0 as wakeup source, only wakeup AON Domain */ + kPower_WS_Both_RtcAlarm0 = POWER_ENCODE_WS(2U, 0U, 0U), /*!< RTC Alarm0 as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_RtcAlarm1 = POWER_ENCODE_WS(0U, 0U, 1U), /*!< RTC Alarm1 as wakeup source, only wakeup Main Domain */ + kPower_WS_Aon_RtcAlarm1 = POWER_ENCODE_WS(1U, 0U, 1U), /*!< RTC Alarm1 as wakeup source, only wakeup AON Domain */ + kPower_WS_Both_RtcAlarm1 = POWER_ENCODE_WS(2U, 0U, 1U), /*!< RTC Alarm1 as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_QTimerIrq = POWER_ENCODE_WS(0U, 0U, 2U), /*!< QTimer IRQ as wakeup source, only wakeup Main Domain */ + kPower_WS_Aon_QTimerIrq = POWER_ENCODE_WS(1U, 0U, 2U), /*!< QTimer IRQ as wakeup source, only wakeup AON Domain */ + kPower_WS_Both_QTimerIrq = POWER_ENCODE_WS(2U, 0U, 2U), /*!< QTimer IRQ as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_RtcWDT = POWER_ENCODE_WS(0U, 0U, 3U), /*!< RTC watch dog as wakeup source, only wakeup Main Domain */ + kPower_WS_Aon_RtcWDT = POWER_ENCODE_WS(1U, 0U, 3U), /*!< RTC watch dog as wakeup source, only wakeup AON Domain */ + kPower_WS_Both_RtcWDT = POWER_ENCODE_WS(2U, 0U, 3U), /*!< RTC watch dog as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_RtcXtalFail = POWER_ENCODE_WS(0U, 0U, 4U), /*!< RTC XTAL fail as wakeup source, + only wakeup Main Domain */ + kPower_WS_Aon_RtcXtalFail = POWER_ENCODE_WS(1U, 0U, 4U), /*!< RTC XTAL fail as wakeup source, + only wakeup AON Domain */ + kPower_WS_Both_RtcXtalFail = POWER_ENCODE_WS(2U, 0U, 4U), /*!< RTC XTAL fail as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_ExternalINTFallEdge = POWER_ENCODE_WS(0U, 2U, 5U), /*!< External INT falling edge as + wakeup source, only wakeup Main Domain */ + kPower_WS_Aon_ExternalINTFallEdge = POWER_ENCODE_WS(1U, 2U, 5U), /*!< External INT falling edge as + wakeup source, only wakeup AON Domain */ + kPower_WS_Both_ExternalINTFallEdge = POWER_ENCODE_WS(2U, 2U, 5U), /*!< External INT falling edge as + wakeup source, wakeup both Main and AON Domains */ + + kPower_WS_Main_ExternalINTRiseEdge = POWER_ENCODE_WS(0U, 1U, 5U), /*!< External INT rising edge as + wakeup source, only wakeup Main Domain */ + kPower_WS_Aon_ExternalINTRiseEdge = POWER_ENCODE_WS(1U, 1U, 5U), /*!< External INT rising edge as + wakeup source, only wakeup AON Domain */ + kPower_WS_Both_ExternalINTRiseEdge = POWER_ENCODE_WS(2U, 1U, 5U), /*!< External INT rising edge as + wakeup source, wakeup both Main and AON Domains */ + + kPower_WS_Main_SMMTimer = POWER_ENCODE_WS(0U, 0U, 6U), /*!< Deep sleep counter as wakeup source, + only wakeup Main Domain */ + kPower_WS_Aon_SMMTimer = POWER_ENCODE_WS(1U, 0U, 6U), /*!< Deep sleep counter as wakeup source, only + wakeup AON Domain */ + kPower_WS_Both_SMMTimer = POWER_ENCODE_WS(2U, 0U, 6U), /*!< Deep sleep counter as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_Comparator = POWER_ENCODE_WS(0U, 0U, 7U), /*!< Voltage comparator as wakeup source, + only wakeup Main Domain */ + kPower_WS_Aon_Comparator = POWER_ENCODE_WS(1U, 0U, 7U), /*!< Voltage comparator as wakeup source, + only wakeup AON Domain */ + kPower_WS_Both_Comparator = POWER_ENCODE_WS(2U, 0U, 7U), /*!< Voltage comparator as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_AonHsGpioWakeup0 = POWER_ENCODE_WS(0U, 0U, 8U), /*!< HS_GPIO wakeup0 as wakeup + source, only wakeup Main Domain */ + kPower_WS_Aon_AonHsGpioWakeup0 = POWER_ENCODE_WS(1U, 0U, 8U), /*!< HS_GPIO wakeup0 as wakeup source, + only wakeup AON Domain */ + kPower_WS_Both_AonHsGpioWakeup0 = POWER_ENCODE_WS(2U, 0U, 8U), /*!< HS_GPIO wakeup0 as wakeup + source, wakeup both Main and AON Domains */ + + kPower_WS_Main_Lpuart0 = POWER_ENCODE_WS(0U, 0U, 9U), /*!< LPUART0 Interrupt as wakeup source, only + wakeup Main Domain */ + kPower_WS_Aon_Lpuart0 = POWER_ENCODE_WS(1U, 0U, 9U), /*!< LPUART0 Interrupt as wakeup source, only + wakeup AON Domain */ + kPower_WS_Both_Lpuart0 = POWER_ENCODE_WS(2U, 0U, 9U), /*!< LPUART0 Interrupt as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_AdvcOrACMP = POWER_ENCODE_WS(0U, 0U, 10U), /*!< ADVC or ACMP as wakeup source, only + wakeup Main Domain */ + kPower_WS_Aon_AdvcOrACMP = POWER_ENCODE_WS(1U, 0U, 10U), /*!< ADVC or ACMP as wakeup source, only + wakeup AON Domain */ + kPower_WS_Both_AdvcOrACMP = POWER_ENCODE_WS(2U, 0U, 10U), /*!< ADVC or ACMP as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_Lpi2cInt = POWER_ENCODE_WS(0U, 0U, 11U), /*!< AON Lpi2c interrupt as wakeup source, + only wakeup Main Domain */ + kPower_WS_Aon_Lpi2cInt = POWER_ENCODE_WS(1U, 0U, 11U), /*!< AON Lpi2c interrupt as wakeup source, + only wakeup AON Domain */ + kPower_WS_Both_Lpi2cInt = POWER_ENCODE_WS(2U, 0U, 11U), /*!< AON Lpi2c interrupt as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_AdcInt = POWER_ENCODE_WS(0U, 0U, 12U), /*!< ADC interrupt as wakeup source, only + wakeup Main Domain */ + kPower_WS_Aon_AdcInt = POWER_ENCODE_WS(1U, 0U, 12U), /*!< ADC interrupt as wakeup source, only + wakeup AON Domain */ + kPower_WS_Both_AdcInt = POWER_ENCODE_WS(2U, 0U, 12U), /*!< ADC interrupt as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_LptmrInt = POWER_ENCODE_WS(0U, 0U, 13U), /*!< LPTMR interrupt as wakeup source, only + wakeup Main Domain */ + kPower_WS_Aon_LptmrInt = POWER_ENCODE_WS(1U, 0U, 13U), /*!< LPTMR interrupt as wakeup source, only + wakeup AON Domain */ + kPower_WS_Both_LptmrInt = POWER_ENCODE_WS(2U, 0U, 13U), /*!< LPTMR interrupt as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_TamperDetect = POWER_ENCODE_WS(0U, 0U, 14U), /*!< Tamper detect as wakeup source, + only wakeup Main Domain */ + kPower_WS_Aon_TamperDetect = POWER_ENCODE_WS(1U, 0U, 14U), /*!< Tamper detect as wakeup source, only + wakeup AON Domain */ + kPower_WS_Both_TamperDetect = POWER_ENCODE_WS(2U, 0U, 14U), /*!< Tamper detect as wakeup source, + wakeup both Main and AON Domains */ + + kPower_WS_Main_LcdInt = POWER_ENCODE_WS(0U, 0U, 15U), /*!< LCD interrupt as wakeup source, only + wakeup Main Domain */ + kPower_WS_Aon_LcdInt = POWER_ENCODE_WS(1U, 0U, 15U), /*!< LCD interrupt as wakeup source, only + wakeup AON Domain */ + kPower_WS_Both_LcdInt = POWER_ENCODE_WS(2U, 0U, 15U), /*!< LCD interrupt as wakeup source, + wakeup both Main and AON Domains */ } power_wakeup_source_t; /*! - * @brief The structure of dumped wakeup source information. + * @brief + * @anchor power_main_domain_sram_array_t */ -typedef struct _power_wakeup_source_info +enum _power_main_domain_sram_array { - uint32_t aonWakeupSourceMask; /*!< The mask of wakeup sources in AON domain. */ - uint32_t wuuPinIntEnable[2]; /*!< Information of enabled Pin interrupts. */ - uint32_t wuuModuleIntEnable; /*!< Information of enabled internal module interrupts. */ - uint32_t wuuModuleDmaTrigEnable; /*!< Information of enabled internal module DMA request/trigger. */ - uint32_t wuuPinDmaTrigConfig[2]; /*!< Information of enabled pin DMA request/trigger. */ -} power_wakeup_source_info_t; + kPower_MainDomainNoneRams = 0UL, + kPower_MainDomainRamX0 = 1UL << 0UL, /*!< Main Domain RAM X0, bitmask representation for power control */ + kPower_MainDomainRamX1 = 1UL << 1UL, /*!< Main Domain RAM X1, bitmask representation for power control */ + kPower_MainDomainRamA0 = 1UL << 2UL, /*!< Main Domain RAM A0, bitmask representation for power control */ + kPower_MainDomainRamA1 = 1UL << 3UL, /*!< Main Domain RAM A1, bitmask representation for power control */ + kPower_MainDomainRamA2 = 1UL << 4UL, /*!< Main Domain RAM A2, bitmask representation for power control */ + kPower_MainDomainRamA3 = 1UL << 5UL, /*!< Main Domain RAM A3, bitmask representation for power control */ + kPower_MainDomainRamB0 = 1UL << 6UL, /*!< Main Domain RAM B0, bitmask representation for power control */ + kPower_MainDomainRamB1 = 1UL << 7UL, /*!< Main Domain RAM B1, bitmask representation for power control */ + kPower_MainDomainRamB2ToB4 = 1UL << 8UL, /*!< Main Domain RAM B2 to B4, bitmask representation for power control */ + kPower_MainDomainAllRams = 0x1FFUL, /*!< Represents all RAMs in the Main Domain, bitmask for power control */ +}; /*! - * @brief - * @anchor power_main_domain_sram_array_t + * @brief The enumeration of VDD_CORE_AON output voltage. */ -enum _power_main_domain_sram_array +typedef enum _power_vdd_core_aon_output_voltage { - kPower_MainDomainNoneRams = 0UL, - kPower_MainDomainRamX0 = 1UL << 0UL, /*!< Main Domain RAM X0, bitmask representation for power control */ - kPower_MainDomainRamX1 = 1UL << 1UL, /*!< Main Domain RAM X1, bitmask representation for power control */ - kPower_MainDomainRamA0 = 1UL << 2UL, /*!< Main Domain RAM A0, bitmask representation for power control */ - kPower_MainDomainRamA1 = 1UL << 3UL, /*!< Main Domain RAM A1, bitmask representation for power control */ - kPower_MainDomainRamA2 = 1UL << 4UL, /*!< Main Domain RAM A2, bitmask representation for power control */ - kPower_MainDomainRamA3 = 1UL << 5UL, /*!< Main Domain RAM A3, bitmask representation for power control */ - kPower_MainDomainRamB0 = 1UL << 6UL, /*!< Main Domain RAM B0, bitmask representation for power control */ - kPower_MainDomainRamB1 = 1UL << 7UL, /*!< Main Domain RAM B1, bitmask representation for power control */ - kPower_MainDomainRamB2ToB4 = 1UL << 8UL, /*!< Main Domain RAM B2 to B4, bitmask representation for power control */ - kPower_MainDomainAllRams = 0x1FFUL, /*!< Represents all RAMs in the Main Domain, bitmask for power control */ -}; + kPower_VddCoreAon_820mV = 0x14U, /*!< The output voltage of VDD_CORE_AON is about 820mV. */ + kPower_VddCoreAon_801mV = 0x16U, /*!< The output voltage of VDD_CORE_AON is about 801mV. */ + kPower_VddCoreAon_782mV = 0x18U, /*!< The output voltage of VDD_CORE_AON is about 782mV. */ + kPower_VddCoreAon_763mV = 0x1AU, /*!< The output voltage of VDD_CORE_AON is about 763mV. */ + kPower_VddCoreAon_744mV = 0x1CU, /*!< The output voltage of VDD_CORE_AON is about 744mV. */ + kPower_VddCoreAon_725mV = 0x1EU, /*!< The output voltage of VDD_CORE_AON is about 725mV. */ + kPower_VddCoreAon_706mV = 0x20U, /*!< The output voltage of VDD_CORE_AON is about 706mV. */ + kPower_VddCoreAon_687mV = 0x22U, /*!< The output voltage of VDD_CORE_AON is about 687mV. */ + kPower_VddCoreAon_668mV = 0x24U, /*!< The output voltage of VDD_CORE_AON is about 668mV. */ + kPower_VddCoreAon_649mV = 0x26U, /*!< The output voltage of VDD_CORE_AON is about 649mV. */ + kPower_VddCoreAon_630mV = 0x28U, /*!< The output voltage of VDD_CORE_AON is about 630mV. */ + kPower_VddCoreAon_611mV = 0x2AU, /*!< The output voltage of VDD_CORE_AON is about 611mV. */ + kPower_VddCoreAon_592mV = 0x2CU, /*!< The output voltage of VDD_CORE_AON is about 592mV. */ + kPower_VddCoreAon_AdvcControl = 0xFFU, /*!< The output voltage of VDD_CORE_AON is controlled by ADVC. */ +} power_vdd_core_output_voltage_t; /*! - * @brief + * @brief * @anchor power_aon_domain_sram_array_t */ enum _power_aon_domain_sram_array { - kPower_AonDomainNoneRams = 0UL, /*!< No AON Domain RAMs. */ - kPower_AonDomainRam1stHalf16kB = 1UL << 0UL, /*!< First half (16kB) of AON Domain RAM, bitmask for power control */ - kPower_AonDomainRam2nd8kB = 1UL << 1UL, /*!< Second 8kB of AON Domain RAM, bitmask for power control */ - kPower_AonDomainRamLower8kB = 1UL << 2UL, /*!< Lower 8kB of AON Domain RAM, bitmask for power control */ - kPower_AonDomainAllRams = 0x7UL, /*!< Represents all RAMs in the AON Domain, bitmask for power control */ + kPower_AonDomainNoneRams = 0UL, /*!< No AON Domain RAMs. */ + kPower_AonDomainRam1stHalf16kB = 1UL << 0UL, /*!< First half (16kB) of AON Domain RAM, bitmask for power control */ + kPower_AonDomainRam2nd8kB = 1UL << 1UL, /*!< Second 8kB of AON Domain RAM, bitmask for power control */ + kPower_AonDomainRamLower8kB = 1UL << 2UL, /*!< Lower 8kB of AON Domain RAM, bitmask for power control */ + kPower_AonDomainAllRams = 0x7UL, /*!< Represents all RAMs in the AON Domain, bitmask for power control */ }; /*! @@ -550,8 +262,8 @@ enum _power_aon_domain_sram_array */ typedef enum _power_mu_message_direction { - kPower_MsgDirMainToAon = 0U, /*!< Message direction from Main to AON domain */ - kPower_MsgDirAonToMain = 1U, /*!< Message direction from AON to Main domain */ + kPower_MsgDirMainToAon = 0U, /*!< Message direction from Main to AON domain */ + kPower_MsgDirAonToMain = 1U, /*!< Message direction from AON to Main domain */ } power_mu_message_direction_t; /*! @@ -559,39 +271,27 @@ typedef enum _power_mu_message_direction */ typedef enum _power_mu_message_type { - kPower_MsgTypeRequest = 0U, /*!< Message type is a request */ - kPower_MsgTypeACK = 1U, /*!< Message type is an ACKnowledgment */ - kPower_MsgTypeNACK = 2U, /*!< Message type is a Negative ACKnowledgment */ + kPower_MsgTypeRequest = 0U, /*!< Message type is a request */ + kPower_MsgTypeACK = 1U, /*!< Message type is response with ACKnowledgment */ + kPower_MsgTypeNACK = 2U, /*!< Message type is response with Negative ACKnowledgment */ + kPower_MsgTypeSync = 3U, /*!< Message type is to sync dual cores. */ } power_mu_message_type_t; /*! - * @brief Union representing a power MU message. + * @brief The reason of NACK response. */ -typedef union _power_mu_message +typedef enum _power_mu_nack_reason { - struct { - uint32_t syncCode : 8U; /*!< Synchronization code for the message */ - power_mu_message_type_t type : 2U; /*!< Type of the message, refer to @ref power_mu_message_type_t */ - power_mu_message_direction_t direction : 1U; /*!< Direction of the message, refer to @ref power_mu_message_direction_t */ - power_low_power_mode_t reqestLowPowerMode : 4U; /*!< Requested low power mode */ - bool init : 1U; /*!< Initialization flag */ - uint32_t sharedHandleAddrOff : 16U; /*!< Offset from shared ram base address */ - } strcutFormat; - uint32_t wordFormat; /*!< Message in word format */ -} power_mu_message_t; - -/*! - * @brief Output voltage options for VDDCore in low power modes. - * - */ -typedef enum _power_vdd_core_output_voltage -{ - kPower_VddCoreOutput1P0V, -} power_vdd_core_output_voltage_t; + kPower_MsgNACK_ChannelMisMatch = 1U << 0U, /*!< NACK response due to channel mismatch. */ + kPower_MsgNACK_TargetModeNotAllowed = 1U << 1U, /*!< NACK response due to target mode not allowed.. */ + kPower_MsgNACK_WrongMsgReceived = 1U << 2U, /*!< NACK response due to wrong message. */ +} power_mu_nack_reason_t; +/*! + * @brief Configuration structure for deep sleep mode. + */ typedef struct _power_ds_config { - } power_ds_config_t; /*! @@ -599,21 +299,40 @@ typedef struct _power_ds_config */ typedef struct _power_pd1_config { - uint32_t mainRamArraysToRetain : 16U; /*!< Bitmask representing the main domain RAM arrays to retain during power down */ - power_vdd_core_output_voltage_t VDDCoreOutputVoltage : 8U; - bool disableBandgap : 1U; /*!< Flag to indicate whether to disable the bandgap during power down */ - bool enableIVSMode : 1U; /*!< Enable/disable IVS mode for the Main domain SRAM retention. */ + power_wakeup_source_t mainWakeupSource; /*!< Specify the wakeup source to main domain. If the selected wakeup + source is not already enabled, it will be enabled before entering PD1 mode. + Setting it to #kPower_WS_NONE indicates that this structure does not + control any wakeup source. Pre-enabled wakeup sources are not affected. + Wakeup sources can also be enabled manually by + invoking Power_EnableWakeupSource(). */ + uint32_t mainRamArraysToRetain : 16U; /*!< Bitmask representing the main domain RAM + arrays to retain during power down */ + bool disableBandgap : 1U; /*!< Flag to indicate whether to disable the bandgap during power down */ + bool enableIVSMode : 1U; /*!< Enable/disable IVS mode for the Main domain SRAM retention. */ } power_pd1_config_t; typedef struct _power_pd2_config { - uint32_t mainRamArraysToRetain : 16U; /*!< Bitmask representing the main domain RAM arrays to retain during DPD2 mode */ - uint32_t aonRamArraysToRetain : 16U; /*!< Bitmask representing the AON domain RAM arrays to retain during DPD2 mode */ - power_vdd_core_output_voltage_t VDDCoreOutputVoltage : 8U; - bool enableIVSMode : 1U; /*!< Enable/disable IVS mode for the Main domain SRAM retention. */ - bool disableBandgap : 1U; /*!< Flag to indicate whether to disable the bandgap during DPD2 mode */ - bool switchToX32K : 1U; /*!< Flag to indicate whether to switch to X32K clock source during DPD2 mode */ - bool disableFRO10M : 1U; /*!< Flag to indicate whether to disable the FRO10M clock during DPD2 mode */ + power_wakeup_source_t mainWakeupSource; /* Specify the wakeup source to main domain. If the selected wakeup + source is not already enabled, it will be enabled before entering PD2 mode. + Setting it to #kPower_WS_NONE indicates that this structure does not + control any wakeup source. Pre-enabled wakeup sources are not affected. + Wakeup sources can also be enabled manually by + invoking Power_EnableWakeupSource().. */ + power_wakeup_source_t aonWakeupSource; /* Specify the wakeup source to aon domain. If the selected wakeup + source is not already enabled, it will be enabled before entering PD2 mode. + Setting it to #kPower_WS_NONE indicates that this structure does not + control any wakeup source. Pre-enabled wakeup sources are not affected. + Wakeup sources can also be enabled manually by + invoking Power_EnableWakeupSource(). */ + uint32_t mainRamArraysToRetain : 16U; /*!< Bitmask representing the main domain RAM arrays + to retain during DPD2 mode */ + uint32_t aonRamArraysToRetain : 16U; /*!< Bitmask representing the AON domain RAM arrays + to retain during DPD2 mode */ + bool enableIVSMode : 1U; /*!< Enable/disable IVS mode for the Main domain SRAM retention. */ + bool disableBandgap : 1U; /*!< Flag to indicate whether to disable the bandgap during DPD2 mode */ + bool disableFRO10M : 1U; /*!< Flag to indicate whether to disable the FRO10M clock during DPD2 mode */ + power_vdd_core_output_voltage_t vddCoreAonVoltage : 8U; /*!< Specify output voltage of VDD_CORE_AON */ } power_pd2_config_t; /*! @@ -621,22 +340,30 @@ typedef struct _power_pd2_config */ typedef enum _power_dpd1_transition { - kPower_Dpd1ToActive = 0U, /*!< Transition from DPD1 to Active mode */ - kPower_Dpd1ToDpd2WakeToDpd1, /*!< Transition from DPD1 to DPD2 wakeup to DPD1 mode */ + kPower_Dpd1ToActive = 0U, /*!< Transition from DPD1 to Active mode */ + kPower_Dpd1ToDpd2WakeToDpd1, /*!< Transition from DPD1 to DPD2 wakeup to DPD1 mode */ kPower_Dpd1ToDpd2WakeToActive, /*!< Transition from DPD1 to DPD2 wakeup to Active mode */ } power_dpd1_transition_t; /*! * @brief Configuration structure for deep power down mode 1. - * + * */ typedef struct _power_dpd1_config { - uint32_t mainRamArraysToRetain : 16U; /*!< Bitmask representing the main domain RAM arrays to retain during power down */ - power_vdd_core_output_voltage_t VDDCoreOutputVoltage : 8U; - bool disableBandgap : 1U; /*!< Flag to indicate whether to disable the bandgap during power down */ - bool enableIVSMode : 1U; /*!< Enable/disable IVS mode for the Main domain SRAM retention. */ - power_dpd1_transition_t nextTrans: 2U; /*!< Next transition after DPD1 mode, refer to @ref power_dpd1_transition_t */ + power_wakeup_source_t mainWakeupSource; /* Specify the wakeup source to main domain. If the selected wakeup + source is not already enabled, it will be enabled before entering DPD1 mode. + Setting it to #kPower_WS_NONE indicates that this structure does not + control any wakeup source. Pre-enabled wakeup sources are not affected. + Wakeup sources can also be enabled manually by + invoking Power_EnableWakeupSource(). */ + uint32_t + mainRamArraysToRetain : 16U; /*!< Bitmask representing the main domain RAM arrays to retain during power down */ + bool disableBandgap : 1U; /*!< Flag to indicate whether to disable the bandgap during power down */ + bool enableIVSMode : 1U; /*!< Enable/disable IVS mode for the Main domain SRAM retention. */ + power_dpd1_transition_t + nextTrans : 2U; /*!< Next transition after DPD1 mode, refer to @ref power_dpd1_transition_t */ + power_vdd_core_output_voltage_t vddCoreAonVoltage : 8U; /*!< Specify output voltage of VDD_CORE_AON */ } power_dpd1_config_t; /*! @@ -644,14 +371,30 @@ typedef struct _power_dpd1_config */ typedef struct _power_dpd2_config { - uint32_t mainRamArraysToRetain : 16U; /*!< Bitmask representing the main domain RAM arrays to retain during DPD2 mode */ - uint32_t aonRamArraysToRetain : 16U; /*!< Bitmask representing the AON domain RAM arrays to retain during DPD2 mode */ - power_vdd_core_output_voltage_t VDDCoreOutputVoltage : 8U; - bool enableIVSMode : 1U; /*!< Enable/disable IVS mode for the Main domain SRAM retention. */ - bool disableBandgap : 1U; /*!< Flag to indicate whether to disable the bandgap during DPD2 mode */ - bool switchToX32K : 1U; /*!< Flag to indicate whether to switch to X32K clock source during DPD2 mode */ - bool disableFRO10M : 1U; /*!< Flag to indicate whether to disable the FRO10M clock during DPD2 mode */ - bool wakeToDpd1 : 1U; /*!< Flag to indicate whether to wake up to DPD1 mode after DPD2 mode */ + power_wakeup_source_t mainWakeupSource; /*!< Specify the wakeup source to main domain. If the selected wakeup + source is not already enabled, it will be enabled before entering DPD2 mode. + Setting it to #kPower_WS_NONE indicates that this structure does not + control any wakeup source. Pre-enabled wakeup sources are not affected. + Wakeup sources can also be enabled manually by + invoking Power_EnableWakeupSource(). */ + power_wakeup_source_t aonWakeupSource; /*!< Specify the wakeup source to aon domain. If the selected wakeup + source is not already enabled, it will be enabled before entering DPD2 mode. + Setting it to #kPower_WS_NONE indicates that this structure does not + control any wakeup source. Pre-enabled wakeup sources are not affected. + Wakeup sources can also be enabled manually by + invoking Power_EnableWakeupSource(). */ + uint32_t + mainRamArraysToRetain : 16U; /*!< Bitmask representing the main domain RAM arrays to retain during DPD2 mode */ + uint32_t + aonRamArraysToRetain : 16U; /*!< Bitmask representing the AON domain RAM arrays to retain during DPD2 mode */ + bool enableIVSMode : 1U; /*!< Enable/disable IVS mode for the Main domain SRAM retention. */ + bool disableBandgap : 1U; /*!< Flag to indicate whether to disable the bandgap during DPD2 mode */ + bool switchToX32K : 1U; /*!< Flag to indicate whether to switch to X32K clock source during DPD2 mode */ + bool disableFRO10M : 1U; /*!< Flag to indicate whether to disable the FRO10M clock during DPD2 mode */ + bool wakeToDpd1 : 1U; /*!< Flag to indicate whether to wake up to DPD1 mode after DPD2 mode */ + power_vdd_core_output_voltage_t + dpd2VddCoreAonVoltage : 8U; /*!< Specify output voltage of VDD_CORE AON in DPD2 mode, + in type of @ref power_vdd_core_output_voltage_t. */ } power_dpd2_config_t; /*! @@ -659,7 +402,12 @@ typedef struct _power_dpd2_config */ typedef struct _power_dpd3_config { - power_vdd_core_output_voltage_t VDDCoreOutputVoltage : 8U; + power_wakeup_source_t wakeupSource; /* Specify the wakeup source to main and aon domain. If the selected wakeup + source is not already enabled, it will be enabled before entering DPD3 mode. + Setting it to #kPower_WS_NONE indicates that this structure does not + control any wakeup source. Pre-enabled wakeup sources are not affected. + Wakeup sources can also be enabled manually by + invoking Power_EnableWakeupSource(). */ } power_dpd3_config_t; /*! @@ -667,23 +415,43 @@ typedef struct _power_dpd3_config */ typedef struct _power_sd_config { + power_wakeup_source_t wakeupSource; /* Specify the wakeup source to main and aon domain. If the selected wakeup + source is not already enabled, it will be enabled before entering SD mode. + Setting it to #kPower_WS_NONE indicates that this structure does not + control any wakeup source. Pre-enabled wakeup sources are not affected. + Wakeup sources can also be enabled manually by + invoking Power_EnableWakeupSource(). */ + pmu_fro16k_output_freq_t fro16KOutputFreq; /*!< Specify the output frequency of FRO16K */ } power_sd_config_t; +/*! + * @brief The structure of dumped wakeup source information. + */ +typedef struct _power_wakeup_source_info +{ + uint32_t aonWakeupSourceMask; /*!< The mask of wakeup sources in AON domain. */ + uint32_t mainWakeupSourceMask; /*!< The mask of wakeup sources in Main domain. */ +} power_wakeup_source_info_t; /*! * @brief Structure to handle power management operations. */ typedef struct _power_handle { - uint32_t muChannelId; /*!< ID of the Message Unit (MU) channel used for power communication */ - power_low_power_mode_t targetPowerMode; /*!< Current low power mode of the system */ - uint32_t lpConfig[2U]; /*!< Array of two 32-bit values for low power configuration */ - bool dualCoreSynced; /*!< Flag indicating whether dual cores are synchronized */ - bool requestCM33Start; /*!< Flag indicating whether a request to start CM33 core is made */ - power_user_callback_t cm33Callback; /*!< Callback function for CM33 core operations, in type of @ref power_user_callback_t */ - void *cm33UserData; /*!< User data pointer for CM33 core operations */ - power_user_callback_t cm0pCallback; /*!< Callback function for CM0+ core operations, in type of @ref power_user_callback_t */ - void *cm0pUserData; /*!< User data pointer for CM0+ core operations */ + uint32_t lpConfig[4U]; /*!< Array of two 32-bit values for low power configuration */ + power_user_callback_t cm33Callback; /*!< Callback function for CM33 core operations, + in type of @ref power_user_callback_t */ + void *cm33UserData; /*!< User data pointer for CM33 core operations */ + power_user_callback_t cm0pCallback; /*!< Callback function for CM0+ core operations, + in type of @ref power_user_callback_t */ + void *cm0pUserData; /*!< User data pointer for CM0+ core operations */ + power_wakeup_source_info_t enabledWsInfo; /*!< Used to record all enabled wakeup sources. */ + uint32_t muChannelId : 4U; /*!< ID of the Message Unit (MU) channel used for power communication */ + power_low_power_mode_t targetPowerMode : 4U; /*!< Current low power mode of the system */ + power_low_power_mode_t previousPowerMode : 4U; /*!< Used to record previous low power mode. */ + bool dualCoreSynced : 1U; /*!< Flag indicating whether dual cores are synchronized */ + bool requestCM33Start : 1U; /*!< Flag indicating whether a request to start CM33 core is made */ + bool cm0pWFI : 1U; /*!< Flag indicating whether CM0P execute WFI. */ } power_handle_t; /******************************************************************************* @@ -695,7 +463,7 @@ extern "C" { /*! * @brief Create shared power handle. - * + * * @param[in] handle Pointer to a handle in type of @ref power_handle_t, must be in shared RAM. * @param[in] muChannelId MU channel ID used by power driver. * @@ -703,21 +471,32 @@ extern "C" { * @retval kStatus_Power_HandleDuplicated Shared power handle already be created. * @retval kStatus_Success Created handle successfully. */ -status_t Power_CreateHandle(power_handle_t *handle, - uint32_t muChannelId); +status_t Power_CreateHandle(power_handle_t *handle, uint32_t muChannelId); +/*! + * @brief Dump contents of handle. + * + * @param[out] ptrDumpBuffer The pointer to a buffer in type of @ref power_handle_t to store dumped handle value. + */ void Power_DumpHandleValue(power_handle_t *ptrDumpBuffer); +/*! + * @brief Get configurations of latest requested low power mode. + * + * @param[out] config The pointer to a buffer to store configurations of latest requested low power mode + */ +void Power_GetPowerModeConfig(void *config); + /*! * @brief Get the offset of shared handle in shared RAM. - * + * * @return Offset of shared handle in shared RAM, in bytes. */ uint32_t Power_GetHandleOffset(void); /*! * @brief Restore the shared handle from offset in shared RAM. - * + * * @param[in] offset Offset of shared handle in shared RAM, in bytes. */ void Power_RestoreHandleOffset(uint32_t offset); @@ -728,7 +507,12 @@ void Power_RestoreHandleOffset(uint32_t offset); */ /*! - * @brief Enable input wakeup source, once enabled it will be effective until disabled + * @brief Enable input wakeup source, once enabled it will be effective until disabled. + * + * @details The enabled wakeup sources are recorded, and set to register before entering low power modes. + * @note There are two ways to enable wakeup source: The first one is invoking Power_EnableWakeupSource(), the + * way is used to enable more than one wakeup source; The second one is specify the wakeup source in configuration + * of low power mode. * * @param[in] ws Specify the coded wakeup source, please refer to @ref power_wakeup_source_t for details. */ @@ -741,6 +525,11 @@ void Power_EnableWakeupSource(power_wakeup_source_t ws); */ void Power_DisableWakeupSource(power_wakeup_source_t ws); +/*! + * @brief Disable all enabled wakeup sources to both main domain and aon domain. + */ +void Power_DisableAllWakeupSources(void); + /*! * @brief Dump information of all configured wakeup sources, in type of @ref power_wakeup_source_info_t. * @@ -755,6 +544,20 @@ void Power_DumpEnabledWakeSource(power_wakeup_source_info_t *ptrWsInfo); */ void Power_GetWakeupSource(uint32_t *ptrWakeupSourceMask); +/*! + * @brief Check whether the selected wakeup source is already enabled, if it is then disable it. + * + * @param ws Specify the wakeup source in type of @ref power_wakeup_source_t. + */ +void Power_CheckThenDisableWakeupSource(power_wakeup_source_t ws); + +/*! + * @brief Check whether the selected wakeup source is disabled, if it is then enable it. + * + * @param ws Specify the wakeup source in type of @ref power_wakeup_source_t. + */ +void Power_CheckThenEnableWakeupSource(power_wakeup_source_t ws); + /*! * @} */ @@ -766,7 +569,7 @@ void Power_GetWakeupSource(uint32_t *ptrWakeupSourceMask); /*! * @brief Register user callback. - * + * * @param[in] callback Pointer to callback in type of @ref power_user_callback_t. * @param[in] userData Pointer to user data. */ @@ -785,8 +588,27 @@ void Power_UnRegisterUserCallback(void); */ /*! - * @brief - * + * @brief Get the target low power mode of latest request. + * + * @return The target low power mode @ref power_low_power_mode_t of latest request. + */ +power_low_power_mode_t Power_GetTargetLowPowerMode(void); + +/*! + * @brief Get previous power mode. + * + * @return The previous power mode. + */ +power_low_power_mode_t Power_GetPreviousPowerMode(void); + +/*! + * @brief Reset previous power mode as active mode. + */ +void Power_ResetPreviousPowerMode(void); + +/*! + * @brief Get current power mode. + * * @param[out] ptrCurLpMode Pointer to store current low power mode * * @retval kStatus_Success Successfully retrieved current low power mode. @@ -795,15 +617,15 @@ status_t Power_GetCurrentPowerMode(power_low_power_mode_t *ptrCurLpMode); /*! * @brief Get the target low power mode. - * - * @return Requested low power mode, in type of @ref power_low_power_mode_t. + * + * @return Requested low power mode, in type of @ref power_low_power_mode_t. */ power_low_power_mode_t Power_GetTargetPowerMode(void); /*! * @brief Clear the target low power mode. */ -void Power_ClearTargatePowerMode(void); +void Power_ClearTargetPowerMode(void); /*! * @brief Clear all low power settings. @@ -811,50 +633,47 @@ void Power_ClearTargatePowerMode(void); void Power_ClearLpPowerSettings(void); /*! -* @brief Enter selected low power mode. -* -* @param[in] lowpowerMode Indicate specific low power mode. -* @param config Point to low power configurations. -* -* @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. -* @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. -*/ + * @brief Enter selected low power mode. + * + * @param[in] lowpowerMode Indicate specific target low power mode. + * @param config Point to low power configurations. + * + * @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. + * @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. + */ status_t Power_EnterLowPowerMode(power_low_power_mode_t lowpowerMode, void *config); - /*! * @brief Enter the sleep mode. - * + * * This function is used to put the system into sleep mode. - * + * * @retval kStatus_Success Successfully entered sleep mode. * @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. */ -status_t Power_EnterSleep(void); - +status_t Power_EnterSleep(void); /*! * @brief Enter Deep Sleep mode. - * + * * This function attempts to put the system into Deep Sleep mode with the provided configuration. - * + * * @param[in] config Pointer to the Deep Sleep mode configuration. - * + * * @retval kStatus_Success Successfully entered Deep Sleep mode. * @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. */ status_t Power_EnterDeepSleep(power_ds_config_t *config); - /*! * @brief Enter Power Down 1 mode. - * + * * This function attempts to put the system into Power Down 1 mode with the provided configuration. - * + * * @param[in] config Pointer to the Power Down 1 mode configuration. - * + * * @retval kStatus_Success Successfully entered Power Down 1 mode. * @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -863,11 +682,11 @@ status_t Power_EnterPowerDown1(power_pd1_config_t *config); /*! * @brief Enter Power Down 2 mode. - * + * * This function attempts to put the system into Power Down 2 mode with the provided configuration. - * + * * @param[in] config Pointer to the Power Down 2 mode configuration. - * + * * @retval kStatus_Success Successfully entered Power Down 2 mode. * @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -876,11 +695,11 @@ status_t Power_EnterPowerDown2(power_pd2_config_t *config); /*! * @brief Enter Deep Power Down 1 mode. - * + * * This function attempts to put the system into Deep Power Down 1 mode with the provided configuration. - * + * * @param[in] config Pointer to the Deep Power Down 1 mode configuration. - * + * * @retval kStatus_Success Successfully entered Deep Power Down 1 mode. * @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -889,18 +708,18 @@ status_t Power_EnterDeepPowerDown1(power_dpd1_config_t *config); /*! * @brief Get the next transition after Deep Power Down 1 mode. - * - * @return Next transition after Deep Power Down 1 mode, in type of @ref power_dpd1_transition_t. + * + * @return Next transition after Deep Power Down 1 mode, in type of @ref power_dpd1_transition_t. */ power_dpd1_transition_t Power_GetDeepPowerDown1NextTransition(void); /*! * @brief Enter Deep Power Down 2 mode. - * + * * This function attempts to put the system into Deep Power Down 2 mode with the provided configuration. - * + * * @param[in] config Pointer to the Deep Power Down 2 mode configuration. - * + * * @retval kStatus_Success Successfully entered Deep Power Down 2 mode. * @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -909,11 +728,11 @@ status_t Power_EnterDeepPowerDown2(power_dpd2_config_t *config); /*! * @brief Enter Deep Power Down 3 mode. - * + * * This function attempts to put the system into Deep Power Down 3 mode with the provided configuration. - * + * * @param[in] config Pointer to the Deep Power Down 3 mode configuration. - * + * * @retval kStatus_Success Successfully entered Deep Power Down 3 mode. * @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -922,11 +741,11 @@ status_t Power_EnterDeepPowerDown3(power_dpd3_config_t *config); /*! * @brief Enter Shutdown mode. - * + * * This function attempts to put the system into Shutdown mode with the provided configuration. - * + * * @param[in] config Pointer to the Shutdown mode configuration. - * + * * @retval kStatus_Success Successfully entered Shutdown mode. * @retval kStatus_POWER_MuTransferError Something error occurs during MU transfer. * @retval kStatus_POWER_RequestNotAllowed Request not allowed by another core. @@ -934,29 +753,154 @@ status_t Power_EnterDeepPowerDown3(power_dpd3_config_t *config); status_t Power_EnterShutDown(power_sd_config_t *config); /*! - * @} + * @brief Save current context into stack. + * --------- <-----High address + | D15 | ----- + --------- | + | D14 | | + --------- | + | D13 | | + --------- | + | D12 | | + --------- |---- Only CM33 + | D11 | | + --------- | + | D10 | | + --------- | + | D9 | | + --------- | + | D8 | ----- + --------- + | LR | + --------- + | R12 | + --------- + | R11 | + --------- + | R10 | + --------- + | R9 | + --------- + | R8 | + --------- + | R7 | + --------- + | R6 | + --------- + | R5 | + --------- + | R4 | + --------- + | handle| + | value | + --------- + | handle| + | addr | + --------- + | ASPR | + --------- + | PSR | + --------- + |PRIMASK| + --------- + |CONTROL| + --------- <------ SP Address saved in backup register + * + * @note When use this function, please ensure the ram block which used as stack is retained in + * target low power mode. + * @note This function should used together with @ref Power_LowPowerBoot(). * + * @param handleAddr The address of handle. + * + * @retval 0 Return 0 before entering low power modes. + * @retval 1 Return 1 after waking up from low power modes. */ +uint32_t Power_PushContext(uint32_t handleAddr); +/*! + * @brief Restore saved context from stack. + */ +void Power_LowPowerBoot(void); + +/*! + * @} + * + */ /*!@name Power MU Transfer Callback @{ */ +/*! + * @brief Get type of received MU message. + * + * @param message The received message. + * + * @return The type of MU message. + */ +power_mu_message_type_t Power_GetMuMessageType(uint32_t message); + +/*! + * @brief Get direction of received MU message. + * + * @param message The received message. + * + * @return The direction of MU message. + */ +power_mu_message_direction_t Power_GetMuMessageDir(uint32_t message); + +/*! + * @brief The callback when one core want to sync with another, that is when the message type is #kPower_MsgTypeSync. + * + * @param message Received message value. + * @param channelId The channel which transfer the message. + * + * @retval kStatus_Power_SyncFailed Failed to sync between dual cores. + * @retval kStatus_Success Sync dual cores successfully. + */ +status_t Power_MuSyncCallback(uint32_t message, uint32_t channelId); + +/*! + * @brief Interpret request message from requester. + * + * @param message The message which request from requester. + * + * @retval kStatus_POWER_MuTransferError Something wrong during transfer. + * @retval kStatus_POWER_RequestNotAllowed Request is not allowed. + * @retval kStatus_Success Interpret request message successfully. + */ +status_t Power_InterpretRequest(uint32_t message); + +/*! + * @brief Interpret responce of message. + * + * @param message The message which responce to requester. + * + * @retval kStatus_POWER_MuTransferError Something wrong during transfer. + * @retval kStatus_POWER_RequestNotAllowed Request is not allowed. + * @retval kStatus_Power_NackWithMultiReasons Responce as NACK with multiple reasons. + * @retval kStatus_Success Interpret response message successfully. + */ +status_t Power_InterpretResponse(uint32_t message); + /*! * @brief Callback function for handling power MU messages. - * - * This function is called when a power MU message is received. It processes the message + * + * @details This function is called when a power MU message is received. It processes the message * based on the given message content and the channel ID. - * + * + * @note This function integrate #Power_MuSyncCallback(), #Power_InterpretRequest(), and + * #Power_InterpretResponse(). + * * @param[in] message The received power MU message. * @param[in] channelId The ID of the channel on which the message was received. - * - * @retval None This function does not return a value. + * + * @retval kStatus_Power_SyncFailed Failed to sync between dual cores. + * @retval kStatus_POWER_MuTransferError Something wrong during transfer. + * @retval kStatus_POWER_RequestNotAllowed Request is not allowed. + * @retval kStatus_Success Interpret request/response message successfully. */ -void Power_MuMessageCallback(uint32_t message, uint32_t channelId); - - +status_t Power_MuMessageCallback(uint32_t message, uint32_t channelId); /*! * @} */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_reset.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_reset.c index 0d1f0e453..873fabe9b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_reset.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_reset.c @@ -1,5 +1,5 @@ /* - * Copyright 2023, NXP + * Copyright 2023, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -58,7 +58,7 @@ void RESET_SetPeripheralReset(reset_ip_name_t peripheral) /* clear bit */ if (regIndex == 2U) { - AON__CGU->RST_SUB_BLK |= bitMask; + AON__CGU->RST_SUB_BLK &= ~bitMask; } else { diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_reset.h index 9e76a6c13..f29f5daa6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_reset.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/drivers/fsl_reset.h @@ -54,7 +54,7 @@ typedef enum _SYSCON_RSTn kLPUART0_RST_SHIFT_RSTn = (0U | (18U)), /*!< LPUART0 reset control */ kADC0_RST_SHIFT_RSTn = (0U | (19U)), /*!< ADC0 reset control */ kATX0_RST_SHIFT_RSTn = (0U | (20U)), /*!< ATX0 reset control */ - kCMP0_RST_SHIFT_RSTn = (0U | (21U)), /*!< CMP0 reset control */ + kACMP0_RST_SHIFT_RSTn = (0U | (21U)), /*!< ACMP0 reset control */ kDMA1_RST_SHIFT_RSTn = (0U | (22U)), /*!< DMA1 reset control */ kGPIO1_RST_SHIFT_RSTn = (0U | (24U)), /*!< GPIO1 reset control */ kGPIO2_RST_SHIFT_RSTn = (0U | (25U)), /*!< GPIO2 reset control */ @@ -72,18 +72,19 @@ typedef enum _SYSCON_RSTn #endif /* Building on the main core */ /* Check AON CGU RST_SUB_BLK in RM */ - kAonUART_RST_SHIFT_RSTn = ((2U << 8) | (0U)), /*!< AON UART reset control */ - kAonI2C_RST_SHIFT_RSTn = ((2U << 8) | (1U)), /*!< AON I2C reset control */ - kAonCAL_RST_SHIFT_RSTn = ((2U << 8) | (2U)), /*!< AON CAL reset control */ - kAonQTMR0_RST_SHIFT_RSTn = ((2U << 8) | (5U)), /*!< AON QTMR0 reset control */ - kAonLPTMR_RST_SHIFT_RSTn = ((2U << 8) | (7U)), /*!< AON LPTMR reset control */ - kAonKPP_RST_SHIFT_RSTn = ((2U << 8) | (8U)), /*!< AON KPP reset control */ - kAonLPADC_RST_SHIFT_RSTn = ((2U << 8) | (9U)), /*!< AON LPADC reset control */ - kAonLCD_RST_SHIFT_RSTn = ((2U << 8) | (10U)), /*!< AON LCD reset control */ - kAonCMP0_RST_SHIFT_RSTn = ((2U << 8) | (12U)), /*!< AON ACMP reset control */ - kAonADVC2P0_RST_SHIFT_RSTn = ((2U << 8) | (13U)), /*!< AON ADVC2P0 reset control */ + kAonUART_RST_SHIFT_RSTn = ((2U << 8) | (0U)), /*!< AON UART reset control */ + kAonI2C_RST_SHIFT_RSTn = ((2U << 8) | (1U)), /*!< AON I2C reset control */ + kAonCAL_RST_SHIFT_RSTn = ((2U << 8) | (2U)), /*!< AON CAL reset control */ + kAonQTMR0_RST_SHIFT_RSTn = ((2U << 8) | (5U)), /*!< AON QTMR0 reset control */ + kAonLPTMR_RST_SHIFT_RSTn = ((2U << 8) | (7U)), /*!< AON LPTMR reset control */ + kAonKPP_RST_SHIFT_RSTn = ((2U << 8) | (8U)), /*!< AON KPP reset control */ + kAonLPADC_RST_SHIFT_RSTn = ((2U << 8) | (9U)), /*!< AON LPADC reset control */ + kAonLCD_RST_SHIFT_RSTn = ((2U << 8) | (10U)), /*!< AON LCD reset control */ + kAonSecurity_RST_SHIFT_RSTn = ((2U << 8) | (11U)), /*!< AON Security reset control */ + kAonACMP0_RST_SHIFT_RSTn = ((2U << 8) | (12U)), /*!< AON ACMP reset control */ + kAonADVC2P0_RST_SHIFT_RSTn = ((2U << 8) | (13U)), /*!< AON ADVC2P0 reset control */ - NotAvail_RSTn = (0xFFFFU), /*!< No reset control */ + NotAvail_RSTn = (0xFFFFU), /*!< No reset control */ } SYSCON_RSTn_t; #if __CORTEX_M == (33U) /* Building on the main core */ @@ -137,14 +138,10 @@ typedef enum _SYSCON_RSTn { \ kLPI2C0_RST_SHIFT_RSTn, kLPI2C1_RST_SHIFT_RSTn, kAonI2C_RST_SHIFT_RSTn \ } /* Reset bits for LPI2C peripheral */ -#define CMP_RSTS \ - { \ - kAonCMP0_RST_SHIFT_RSTn, kCMP0_RST_SHIFT_RSTn \ - } /* Reset bits for CMP peripherals */ -#define LPACMP_RSTS \ - { \ - NotAvail_RSTn \ - } /* Reset bits for LPCMP peripheral */ +#define LPCMP_RSTS \ + { \ + kACMP0_RST_SHIFT_RSTn, kAonACMP0_RST_SHIFT_RSTn \ + } /* Reset bits for ACMP peripheral */ #define OSTIMER_RSTS \ { \ kOSTIMER0_RST_SHIFT_RSTn \ @@ -153,6 +150,10 @@ typedef enum _SYSCON_RSTn { \ NotAvail_RSTn, kPORT0_RST_SHIFT_RSTn, kPORT1_RST_SHIFT_RSTn, kPORT2_RST_SHIFT_RSTn \ } /* Reset bits for PORT peripheral */ +#define TRNG_RSTS \ + { \ + kTRNG0_RST_SHIFT_RSTn \ + } /* Reset bits for TRNG peripheral */ #define UTICK_RSTS \ { \ kUTICK0_RST_SHIFT_RSTn \ @@ -180,14 +181,10 @@ typedef enum _SYSCON_RSTn { \ NotAvail_RSTn \ } /* Reset bits for GPIO peripheral */ -#define CMP_RSTS \ - { \ - kAonCMP0_RST_SHIFT_RSTn, NotAvail_RSTn \ - } /* Reset bits for CMP peripherals */ -#define LPACMP_RSTS \ - { \ - NotAvail_RSTn \ - } /* Reset bits for LPCMP peripheral */ +#define LPCMP_RSTS \ + { \ + NotAvail_RSTn, kAonACMP0_RST_SHIFT_RSTn \ + } /* Reset bits for ACMP peripherals */ #define PORT_RSTS_N \ { \ NotAvail_RSTn \ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm0plus.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm0plus.c index 3864426e4..375a6fe1f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm0plus.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm0plus.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL255_cm0plus * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL255_cm0plus (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm0plus.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm0plus.h index a7926f2c5..07b02a45e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm0plus.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm0plus.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL255_cm0plus * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL255_cm0plus (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm33.c b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm33.c index a0c9c4237..055c6f184 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm33.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm33.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL255_cm33 * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL255_cm33 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm33.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm33.h index 61f903268..3d033bbd8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm33.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/MCXL255/system_MCXL255_cm33.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXL25xRM DraftF -** Version: rev. 1.0, 2023-01-09 -** Build: b250327 +** Reference manual: MCXL25xRM DraftH +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -25,8 +25,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -34,7 +34,7 @@ /*! * @file MCXL255_cm33 * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief Device specific configuration file for MCXL255_cm33 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ADC.h index d580fa6e5..5f13a5800 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ADC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_ADC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for ADC * * CMSIS Peripheral Access Layer for ADC @@ -988,9 +988,9 @@ typedef struct { #define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK #define ADC_DE_FWMDE_SHIFT ADC_DE_FWMDE0_SHIFT #define ADC_DE_FWMDE(x) ADC_DE_FWMDE0(x) -/* ADC temperature sensor related parameters */ +/* ADC temperature sensor related parameters (see ADC0 electrical characteristics in datasheet) */ /* @brief Temperature sensor parameter A (slope). */ -#define TEMP_PARAMETER_A (783.0f) +#define TEMP_PARAMETER_A (738.0f) /* @brief Temperature sensor parameter B (offset). */ #define TEMP_PARAMETER_B (287.5f) /* @brief Temperature sensor parameter Alpha. */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_AHBSC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_AHBSC.h index 2b73f8b67..e124a1fef 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_AHBSC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_AHBSC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for AHBSC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_AHBSC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for AHBSC * * CMSIS Peripheral Access Layer for AHBSC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_AOI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_AOI.h index e4a8b33fe..361f6d62d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_AOI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_AOI.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for AOI @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_AOI.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for AOI * * CMSIS Peripheral Access Layer for AOI diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ATX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ATX.h index adb6a7293..b035b4ef5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ATX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ATX.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for ATX @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_ATX.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for ATX * * CMSIS Peripheral Access Layer for ATX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CDOG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CDOG.h index cf9322908..7971a6f56 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CDOG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CDOG.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for CDOG @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_CDOG.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for CDOG * * CMSIS Peripheral Access Layer for CDOG diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CGU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CGU.h index 83f7adff2..60e7a3b4c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CGU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CGU.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for CGU @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_CGU.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for CGU * * CMSIS Peripheral Access Layer for CGU @@ -102,17 +102,12 @@ /** CGU - Register Layout Typedef */ typedef struct { __IO uint32_t CLK_CONFIG; /**< AON Clock Configuration, offset: 0x0 */ - __IO uint32_t PER_CLK_CONFIG; /**< Peripheral Clock Enable, offset: 0x4 */ + __IO uint32_t PER_CLK_CONFIG; /**< Peripheral Clock Configuration, offset: 0x4 */ __IO uint32_t CLOCK_DIV; /**< Clock Divider, offset: 0x8 */ __IO uint32_t PER_CLK_EN; /**< Peripheral Clock Enable, offset: 0xC */ __IO uint32_t RST_SUB_BLK; /**< Reset Subsystem Blocks, offset: 0x10 */ - uint8_t RESERVED_0[28]; - __IO uint32_t FRO10M_CONFIG; /**< FRO10M Configuration, offset: 0x30 */ - __IO uint32_t FRO10M_TRIM; /**< FRO10M Trim, offset: 0x34 */ - uint8_t RESERVED_1[4]; - __IO uint32_t FRO2M_CONFIG; /**< FRO2M Configuration, offset: 0x3C */ - __IO uint32_t FRO2M_TRIM; /**< FRO2M_TRIM, offset: 0x40 */ - __IO uint32_t ACMP_CLK_DIV; /**< ACMP Clock Divider, offset: 0x44 */ + uint8_t RESERVED_0[48]; + __IO uint32_t ACMP_CLK; /**< ACMP Clock, offset: 0x44 */ __IO uint32_t INT; /**< Interrupt Flag, offset: 0x48 */ } CGU_Type; @@ -147,12 +142,9 @@ typedef struct { #define CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK (0xCU) #define CGU_CLK_CONFIG_ROOT_CLK_SEL_SHIFT (2U) /*! ROOT_CLK_SEL - Root Clock Select - * 0b00..Option between 10.0 MHz or 2.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. - * 0b01..Option between 5.0 MHz or 1.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. - * 0b10..Option between 2.5 MHz or 0.5 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. + * 0b00..Option based on the selected FRO, if FRO10M is used then the clock will be 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. + * 0b01..Option based on the selected FRO, if FRO10M is used then the clock will be 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. + * 0b10..Option based on the selected FRO, if FRO10M is used then the clock will be 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. * 0b11..32 kHz */ #define CGU_CLK_CONFIG_ROOT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CGU_CLK_CONFIG_ROOT_CLK_SEL_SHIFT)) & CGU_CLK_CONFIG_ROOT_CLK_SEL_MASK) @@ -172,7 +164,7 @@ typedef struct { #define CGU_CLK_CONFIG_XTAL32_OUT_EN_MASK (0x40U) #define CGU_CLK_CONFIG_XTAL32_OUT_EN_SHIFT (6U) -/*! XTAL32_OUT_EN - XTAL32 Output Enable +/*! XTAL32_OUT_EN - XTAL32K[1] Output Enable * 0b0..Disable * 0b1..Enable */ @@ -195,18 +187,15 @@ typedef struct { #define CGU_CLK_CONFIG_FRO2M_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_CLK_CONFIG_FRO2M_EN_SHIFT)) & CGU_CLK_CONFIG_FRO2M_EN_MASK) /*! @} */ -/*! @name PER_CLK_CONFIG - Peripheral Clock Enable */ +/*! @name PER_CLK_CONFIG - Peripheral Clock Configuration */ /*! @{ */ #define CGU_PER_CLK_CONFIG_COM_GRP_SEL_MASK (0x3U) #define CGU_PER_CLK_CONFIG_COM_GRP_SEL_SHIFT (0U) -/*! COM_GRP_SEL - Comparator Group Select - * 0b00..Option between 10.0 MHz or 2.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. - * 0b01..Option between 5.0 MHz or 1.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. - * 0b10..Option between 2.5 MHz or 0.5 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. +/*! COM_GRP_SEL - Communication Group Select + * 0b00..Option based on the selected FRO, if FRO10M is used then the clock will be 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. + * 0b01..Option based on the selected FRO, if FRO10M is used then the clock will be 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. + * 0b10..Option based on the selected FRO, if FRO10M is used then the clock will be 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. * 0b11..32 kHz */ #define CGU_PER_CLK_CONFIG_COM_GRP_SEL(x) (((uint32_t)(((uint32_t)(x)) << CGU_PER_CLK_CONFIG_COM_GRP_SEL_SHIFT)) & CGU_PER_CLK_CONFIG_COM_GRP_SEL_MASK) @@ -214,12 +203,9 @@ typedef struct { #define CGU_PER_CLK_CONFIG_TMR_GRP_SEL_MASK (0xCU) #define CGU_PER_CLK_CONFIG_TMR_GRP_SEL_SHIFT (2U) /*! TMR_GRP_SEL - Timer Group Select - * 0b00..Option between 10.0 MHz or 2.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. - * 0b01..Option between 5.0 MHz or 1.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. - * 0b10..Option between 2.5 MHz or 0.5 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. + * 0b00..Option based on the selected FRO, if FRO10M is used then the clock will be 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. + * 0b01..Option based on the selected FRO, if FRO10M is used then the clock will be 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. + * 0b10..Option based on the selected FRO, if FRO10M is used then the clock will be 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. * 0b11..32 kHz */ #define CGU_PER_CLK_CONFIG_TMR_GRP_SEL(x) (((uint32_t)(((uint32_t)(x)) << CGU_PER_CLK_CONFIG_TMR_GRP_SEL_SHIFT)) & CGU_PER_CLK_CONFIG_TMR_GRP_SEL_MASK) @@ -227,10 +213,10 @@ typedef struct { #define CGU_PER_CLK_CONFIG_LPTMR_GRP_SEL_MASK (0x30U) #define CGU_PER_CLK_CONFIG_LPTMR_GRP_SEL_SHIFT (4U) /*! LPTMR_GRP_SEL - Low-Power Timer Group Select - * 0b00..aon_timer_clk - * 0b01..fro16K - * 0b10..16K_clk - * 0b11..Empty + * 0b00..AON_TIMER_CLK + * 0b01..FRO16K + * 0b10..clk_16k + * 0b11..Reserved */ #define CGU_PER_CLK_CONFIG_LPTMR_GRP_SEL(x) (((uint32_t)(((uint32_t)(x)) << CGU_PER_CLK_CONFIG_LPTMR_GRP_SEL_SHIFT)) & CGU_PER_CLK_CONFIG_LPTMR_GRP_SEL_MASK) @@ -238,59 +224,49 @@ typedef struct { #define CGU_PER_CLK_CONFIG_KPP_CLK_SEL_SHIFT (6U) /*! KPP_CLK_SEL - KPP Clock Select * 0b0..Xtal 32 kHz. - * 0b1..fro16K + * 0b1..FRO16K */ #define CGU_PER_CLK_CONFIG_KPP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CGU_PER_CLK_CONFIG_KPP_CLK_SEL_SHIFT)) & CGU_PER_CLK_CONFIG_KPP_CLK_SEL_MASK) #define CGU_PER_CLK_CONFIG_AON_SYS_CLK_SEL_MASK (0x180U) #define CGU_PER_CLK_CONFIG_AON_SYS_CLK_SEL_SHIFT (7U) -/*! AON_SYS_CLK_SEL - AON System Clock Select - * 0b00..Option between 10.0 MHz or 2.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. - * 0b01..Option between 5.0 MHz or 1.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 5.0 MHz and if FRO2M is used then clock will be 1.0 MHz. - * 0b10..Option between 2.5 MHz or 0.5 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. - * 0b11..Empty +/*! AON_SYS_CLK_SEL - AON SysTick Clock Select + * 0b00..Option based on the selected FRO, if FRO10M is used then the clock will be 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. + * 0b01..Option based on the selected FRO, if FRO10M is used then the clock will be 5.0 MHz and if FRO2M is used then clock will be 1.0 MHz. + * 0b10..Option based on the selected FRO, if FRO10M is used then the clock will be 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. + * 0b11..Reserved */ #define CGU_PER_CLK_CONFIG_AON_SYS_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CGU_PER_CLK_CONFIG_AON_SYS_CLK_SEL_SHIFT)) & CGU_PER_CLK_CONFIG_AON_SYS_CLK_SEL_MASK) #define CGU_PER_CLK_CONFIG_LPADC_CLK_SEL_MASK (0xE00U) #define CGU_PER_CLK_CONFIG_LPADC_CLK_SEL_SHIFT (9U) /*! LPADC_CLK_SEL - LPADC Clock Select - * 0b000..Option between 10.0 MHz or 2.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. - * 0b001..Option between 5.0 MHz or 1.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. - * 0b010..Option between 2.5 MHz or 0.5 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. - * 0b011..Option between 32 kHz clock (from RTC) or aon_aux_clk based on the selected FRO, if FRO10M is used then - * clock will be aon_aux_clk and if FRO2M is used then clock will be aon_aux_clk. - * 0b100..XTAL 32 K + * 0b000..Option based on the selected FRO, if FRO10M is used then the clock will be 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. + * 0b001..Option based on the selected FRO, if FRO10M is used then the clock will be 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. + * 0b010..Option based on the selected FRO, if FRO10M is used then the clock will be 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. + * 0b011..Option based on the selected FRO, if FRO10M is used then clock will be aon_aux_clk and if FRO2M is used then clock will be aon_aux_clk. + * 0b100..XTAL32K * 0b101..FRO16K - * 0b110..Empty - * 0b111..Empty + * 0b110..Reserved + * 0b111..Reserved */ #define CGU_PER_CLK_CONFIG_LPADC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CGU_PER_CLK_CONFIG_LPADC_CLK_SEL_SHIFT)) & CGU_PER_CLK_CONFIG_LPADC_CLK_SEL_MASK) #define CGU_PER_CLK_CONFIG_LCD_CLK_SEL_MASK (0x1000U) #define CGU_PER_CLK_CONFIG_LCD_CLK_SEL_SHIFT (12U) /*! LCD_CLK_SEL - LCD Clock Select - * 0b0..clk_16K - * 0b1..fro16K + * 0b0..clk_16k[1] + * 0b1..FRO16K */ #define CGU_PER_CLK_CONFIG_LCD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CGU_PER_CLK_CONFIG_LCD_CLK_SEL_SHIFT)) & CGU_PER_CLK_CONFIG_LCD_CLK_SEL_MASK) #define CGU_PER_CLK_CONFIG_ACMP0_CLK_SEL_MASK (0x6000U) #define CGU_PER_CLK_CONFIG_ACMP0_CLK_SEL_SHIFT (13U) /*! ACMP0_CLK_SEL - ACMP0 clock mux select - * 0b00..Option between 10.0 MHz or 2.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. - * 0b01..Option between 5.0 MHz or 1.0 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. - * 0b10..Option between 2.5 MHz or 0.5 MHz based on the selected FRO, if FRO10M is used then the clock will be - * 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. - * 0b11..fro16K + * 0b00..Option based on the selected FRO, if FRO10M is used then the clock will be 10.0 MHz and if FRO2M is used then the clock will be 2.0 MHz. + * 0b01..Option based on the selected FRO, if FRO10M is used then the clock will be 5.0 MHz and if FRO2M is used then the clock will be 1.0 MHz. + * 0b10..Option based on the selected FRO, if FRO10M is used then the clock will be 2.5 MHz and if FRO2M is used then the clock will be 0.5 MHz. + * 0b11..FRO16K */ #define CGU_PER_CLK_CONFIG_ACMP0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CGU_PER_CLK_CONFIG_ACMP0_CLK_SEL_SHIFT)) & CGU_PER_CLK_CONFIG_ACMP0_CLK_SEL_MASK) /*! @} */ @@ -308,7 +284,7 @@ typedef struct { #define CGU_CLOCK_DIV_COM_GRP_CLK_EN_MASK (0x2U) #define CGU_CLOCK_DIV_COM_GRP_CLK_EN_SHIFT (1U) -/*! COM_GRP_CLK_EN - Comparator Group Clock Divider Enable +/*! COM_GRP_CLK_EN - Communication Group Clock Divider Enable * 0b0..Disable * 0b1..Enable */ @@ -316,25 +292,25 @@ typedef struct { #define CGU_CLOCK_DIV_SYS_CLK_DIV_EN_MASK (0x4U) #define CGU_CLOCK_DIV_SYS_CLK_DIV_EN_SHIFT (2U) -/*! SYS_CLK_DIV_EN - SysTic Clock Divider Enable +/*! SYS_CLK_DIV_EN - SysTick Clock Divider Enable * 0b0..Disable * 0b1..Enable */ #define CGU_CLOCK_DIV_SYS_CLK_DIV_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_CLOCK_DIV_SYS_CLK_DIV_EN_SHIFT)) & CGU_CLOCK_DIV_SYS_CLK_DIV_EN_MASK) -#define CGU_CLOCK_DIV_AONCPU_CLK_DIV_MASK (0x38U) -#define CGU_CLOCK_DIV_AONCPU_CLK_DIV_SHIFT (3U) -/*! AONCPU_CLK_DIV - AON CPU Clock Divider */ -#define CGU_CLOCK_DIV_AONCPU_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << CGU_CLOCK_DIV_AONCPU_CLK_DIV_SHIFT)) & CGU_CLOCK_DIV_AONCPU_CLK_DIV_MASK) +#define CGU_CLOCK_DIV_AON_CPU_CLK_DIV_MASK (0x38U) +#define CGU_CLOCK_DIV_AON_CPU_CLK_DIV_SHIFT (3U) +/*! AON_CPU_CLK_DIV - AON CPU Clock Divider */ +#define CGU_CLOCK_DIV_AON_CPU_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << CGU_CLOCK_DIV_AON_CPU_CLK_DIV_SHIFT)) & CGU_CLOCK_DIV_AON_CPU_CLK_DIV_MASK) #define CGU_CLOCK_DIV_COM_GRP_CLK_DIV_MASK (0x1C0U) #define CGU_CLOCK_DIV_COM_GRP_CLK_DIV_SHIFT (6U) -/*! COM_GRP_CLK_DIV - Comparator Group Clock Divider */ +/*! COM_GRP_CLK_DIV - Communication Group Clock Divider */ #define CGU_CLOCK_DIV_COM_GRP_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << CGU_CLOCK_DIV_COM_GRP_CLK_DIV_SHIFT)) & CGU_CLOCK_DIV_COM_GRP_CLK_DIV_MASK) #define CGU_CLOCK_DIV_AON_SYS_CLK_DIV_MASK (0xE00U) #define CGU_CLOCK_DIV_AON_SYS_CLK_DIV_SHIFT (9U) -/*! AON_SYS_CLK_DIV - AON SysTic Clock Divider */ +/*! AON_SYS_CLK_DIV - AON SysTick Clock Divider */ #define CGU_CLOCK_DIV_AON_SYS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << CGU_CLOCK_DIV_AON_SYS_CLK_DIV_SHIFT)) & CGU_CLOCK_DIV_AON_SYS_CLK_DIV_MASK) /*! @} */ @@ -399,7 +375,7 @@ typedef struct { #define CGU_PER_CLK_EN_QTMR0_CLK_EN_MASK (0x80U) #define CGU_PER_CLK_EN_QTMR0_CLK_EN_SHIFT (7U) -/*! QTMR0_CLK_EN - Qtimer0 Clock Enable +/*! QTMR0_CLK_EN - QTimer0 Clock Enable * 0b0..Disable * 0b1..Enable */ @@ -431,7 +407,7 @@ typedef struct { #define CGU_PER_CLK_EN_SYS_CLK_EN_MASK (0x1000U) #define CGU_PER_CLK_EN_SYS_CLK_EN_SHIFT (12U) -/*! SYS_CLK_EN - SysTic Clock Enable +/*! SYS_CLK_EN - SysTick Clock Enable * 0b0..Disable * 0b1..Enable */ @@ -439,7 +415,7 @@ typedef struct { #define CGU_PER_CLK_EN_COMP_CLK_EN_MASK (0x2000U) #define CGU_PER_CLK_EN_COMP_CLK_EN_SHIFT (13U) -/*! COMP_CLK_EN - Comparator Clock Enable +/*! COMP_CLK_EN - Communication Clock Enable * 0b0..Disable * 0b1..Enable */ @@ -467,27 +443,39 @@ typedef struct { #define CGU_RST_SUB_BLK_UART_RST_N_MASK (0x1U) #define CGU_RST_SUB_BLK_UART_RST_N_SHIFT (0U) -/*! UART_RST_N - UART Reset N */ +/*! UART_RST_N - UART Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_UART_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_UART_RST_N_SHIFT)) & CGU_RST_SUB_BLK_UART_RST_N_MASK) #define CGU_RST_SUB_BLK_I2C_RST_N_MASK (0x2U) #define CGU_RST_SUB_BLK_I2C_RST_N_SHIFT (1U) -/*! I2C_RST_N - I2C Software Reset N */ +/*! I2C_RST_N - I2C Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_I2C_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_I2C_RST_N_SHIFT)) & CGU_RST_SUB_BLK_I2C_RST_N_MASK) #define CGU_RST_SUB_BLK_CAL_RST_N_MASK (0x4U) #define CGU_RST_SUB_BLK_CAL_RST_N_SHIFT (2U) -/*! CAL_RST_N - Calibration Software Reset N */ +/*! CAL_RST_N - Calibration Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_CAL_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_CAL_RST_N_SHIFT)) & CGU_RST_SUB_BLK_CAL_RST_N_MASK) #define CGU_RST_SUB_BLK_CPU_SW_RST_N_MASK (0x8U) #define CGU_RST_SUB_BLK_CPU_SW_RST_N_SHIFT (3U) -/*! CPU_SW_RST_N - CPU Software Reset N */ +/*! CPU_SW_RST_N - CPU Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_CPU_SW_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_CPU_SW_RST_N_SHIFT)) & CGU_RST_SUB_BLK_CPU_SW_RST_N_MASK) #define CGU_RST_SUB_BLK_CM0P_RST_REL_MASK (0x10U) #define CGU_RST_SUB_BLK_CM0P_RST_REL_SHIFT (4U) -/*! CM0P_RST_REL - CMOP_RST_REL +/*! CM0P_RST_REL - CM0P_RST_REL * 0b0..Keep CM0+ at reset state. * 0b1..Release CM0+ at reset */ @@ -495,143 +483,147 @@ typedef struct { #define CGU_RST_SUB_BLK_QTMR0_SW_RST_N_MASK (0x20U) #define CGU_RST_SUB_BLK_QTMR0_SW_RST_N_SHIFT (5U) -/*! QTMR0_SW_RST_N - Qtimer0 Software Reset N */ +/*! QTMR0_SW_RST_N - Qtimer0 Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_QTMR0_SW_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_QTMR0_SW_RST_N_SHIFT)) & CGU_RST_SUB_BLK_QTMR0_SW_RST_N_MASK) #define CGU_RST_SUB_BLK_LPTMR_SW_RST_N_MASK (0x80U) #define CGU_RST_SUB_BLK_LPTMR_SW_RST_N_SHIFT (7U) -/*! LPTMR_SW_RST_N - LP Timer Software Reset N */ +/*! LPTMR_SW_RST_N - LP Timer Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_LPTMR_SW_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_LPTMR_SW_RST_N_SHIFT)) & CGU_RST_SUB_BLK_LPTMR_SW_RST_N_MASK) #define CGU_RST_SUB_BLK_KPP_SW_RST_N_MASK (0x100U) #define CGU_RST_SUB_BLK_KPP_SW_RST_N_SHIFT (8U) -/*! KPP_SW_RST_N - KPP Timer Software Reset N */ +/*! KPP_SW_RST_N - KPP Timer Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_KPP_SW_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_KPP_SW_RST_N_SHIFT)) & CGU_RST_SUB_BLK_KPP_SW_RST_N_MASK) #define CGU_RST_SUB_BLK_LPADC_SW_RST_N_MASK (0x200U) #define CGU_RST_SUB_BLK_LPADC_SW_RST_N_SHIFT (9U) -/*! LPADC_SW_RST_N - LPADC Timer Software Reset N */ +/*! LPADC_SW_RST_N - LPADC Timer Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_LPADC_SW_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_LPADC_SW_RST_N_SHIFT)) & CGU_RST_SUB_BLK_LPADC_SW_RST_N_MASK) #define CGU_RST_SUB_BLK_LCD_SW_RST_N_MASK (0x400U) #define CGU_RST_SUB_BLK_LCD_SW_RST_N_SHIFT (10U) -/*! LCD_SW_RST_N - LCD Software Reset N */ +/*! LCD_SW_RST_N - LCD Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_LCD_SW_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_LCD_SW_RST_N_SHIFT)) & CGU_RST_SUB_BLK_LCD_SW_RST_N_MASK) #define CGU_RST_SUB_BLK_EN_RST_SEC_DET_MASK (0x800U) #define CGU_RST_SUB_BLK_EN_RST_SEC_DET_SHIFT (11U) -/*! EN_RST_SEC_DET - Enable Reset Security Detect. */ +/*! EN_RST_SEC_DET - Enable Reset Security Detect. + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_EN_RST_SEC_DET(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_EN_RST_SEC_DET_SHIFT)) & CGU_RST_SUB_BLK_EN_RST_SEC_DET_MASK) #define CGU_RST_SUB_BLK_ACMP_SW_RST_N_MASK (0x1000U) #define CGU_RST_SUB_BLK_ACMP_SW_RST_N_SHIFT (12U) -/*! ACMP_SW_RST_N - ACMP Software Reset N */ +/*! ACMP_SW_RST_N - ACMP Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_ACMP_SW_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_ACMP_SW_RST_N_SHIFT)) & CGU_RST_SUB_BLK_ACMP_SW_RST_N_MASK) #define CGU_RST_SUB_BLK_ADVC2P0_SW_RST_N_MASK (0x2000U) #define CGU_RST_SUB_BLK_ADVC2P0_SW_RST_N_SHIFT (13U) -/*! ADVC2P0_SW_RST_N - ADVC2P0 Software Reset N */ +/*! ADVC2P0_SW_RST_N - ADVC2P0 Software Reset + * 0b0..Enable + * 0b1..Disable + */ #define CGU_RST_SUB_BLK_ADVC2P0_SW_RST_N(x) (((uint32_t)(((uint32_t)(x)) << CGU_RST_SUB_BLK_ADVC2P0_SW_RST_N_SHIFT)) & CGU_RST_SUB_BLK_ADVC2P0_SW_RST_N_MASK) /*! @} */ -/*! @name FRO10M_CONFIG - FRO10M Configuration */ -/*! @{ */ - -#define CGU_FRO10M_CONFIG_TRIM_CCO_LV_MASK (0x3FU) -#define CGU_FRO10M_CONFIG_TRIM_CCO_LV_SHIFT (0U) -/*! TRIM_CCO_LV - TRIM CCO Coarse Calibrate */ -#define CGU_FRO10M_CONFIG_TRIM_CCO_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO10M_CONFIG_TRIM_CCO_LV_SHIFT)) & CGU_FRO10M_CONFIG_TRIM_CCO_LV_MASK) - -#define CGU_FRO10M_CONFIG_TRIM_CLK_LV_MASK (0xFC0U) -#define CGU_FRO10M_CONFIG_TRIM_CLK_LV_SHIFT (6U) -/*! TRIM_CLK_LV - TRIM CCO Fine Calibrate */ -#define CGU_FRO10M_CONFIG_TRIM_CLK_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO10M_CONFIG_TRIM_CLK_LV_SHIFT)) & CGU_FRO10M_CONFIG_TRIM_CLK_LV_MASK) -/*! @} */ - -/*! @name FRO10M_TRIM - FRO10M Trim */ -/*! @{ */ - -#define CGU_FRO10M_TRIM_TRIM_TC_LV_MASK (0x1FU) -#define CGU_FRO10M_TRIM_TRIM_TC_LV_SHIFT (0U) -/*! TRIM_TC_LV - TRIM_TC_LV */ -#define CGU_FRO10M_TRIM_TRIM_TC_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO10M_TRIM_TRIM_TC_LV_SHIFT)) & CGU_FRO10M_TRIM_TRIM_TC_LV_MASK) - -#define CGU_FRO10M_TRIM_TRIM_FVCH_LV_MASK (0x3E0U) -#define CGU_FRO10M_TRIM_TRIM_FVCH_LV_SHIFT (5U) -/*! TRIM_FVCH_LV - TRIM_FVCH_LV */ -#define CGU_FRO10M_TRIM_TRIM_FVCH_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO10M_TRIM_TRIM_FVCH_LV_SHIFT)) & CGU_FRO10M_TRIM_TRIM_FVCH_LV_MASK) -/*! @} */ - -/*! @name FRO2M_CONFIG - FRO2M Configuration */ +/*! @name ACMP_CLK - ACMP Clock */ /*! @{ */ -#define CGU_FRO2M_CONFIG_TRIM_COA_LV_MASK (0x3FU) -#define CGU_FRO2M_CONFIG_TRIM_COA_LV_SHIFT (0U) -/*! TRIM_COA_LV - TRIM Bus Coarse Calibrate */ -#define CGU_FRO2M_CONFIG_TRIM_COA_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO2M_CONFIG_TRIM_COA_LV_SHIFT)) & CGU_FRO2M_CONFIG_TRIM_COA_LV_MASK) - -#define CGU_FRO2M_CONFIG_TRIM_FINE_LV_MASK (0xFC0U) -#define CGU_FRO2M_CONFIG_TRIM_FINE_LV_SHIFT (6U) -/*! TRIM_FINE_LV - TRIM Fine Calibrate */ -#define CGU_FRO2M_CONFIG_TRIM_FINE_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO2M_CONFIG_TRIM_FINE_LV_SHIFT)) & CGU_FRO2M_CONFIG_TRIM_FINE_LV_MASK) -/*! @} */ - -/*! @name FRO2M_TRIM - FRO2M_TRIM */ -/*! @{ */ +#define CGU_ACMP_CLK_ACMP0_CLK_EN_MASK (0x1U) +#define CGU_ACMP_CLK_ACMP0_CLK_EN_SHIFT (0U) +/*! ACMP0_CLK_EN - ACMP0 Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CGU_ACMP_CLK_ACMP0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_ACMP0_CLK_EN_SHIFT)) & CGU_ACMP_CLK_ACMP0_CLK_EN_MASK) -#define CGU_FRO2M_TRIM_TRIM_TC_LV_MASK (0x1FU) -#define CGU_FRO2M_TRIM_TRIM_TC_LV_SHIFT (0U) -/*! TRIM_TC_LV - Trim Bus to Calibrate Fraquency. */ -#define CGU_FRO2M_TRIM_TRIM_TC_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO2M_TRIM_TRIM_TC_LV_SHIFT)) & CGU_FRO2M_TRIM_TRIM_TC_LV_MASK) - -#define CGU_FRO2M_TRIM_TRIM_FVCH_LV_MASK (0x3E0U) -#define CGU_FRO2M_TRIM_TRIM_FVCH_LV_SHIFT (5U) -/*! TRIM_FVCH_LV - Trim Bus to Calibrate Voltage. */ -#define CGU_FRO2M_TRIM_TRIM_FVCH_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO2M_TRIM_TRIM_FVCH_LV_SHIFT)) & CGU_FRO2M_TRIM_TRIM_FVCH_LV_MASK) - -#define CGU_FRO2M_TRIM_TEST_EN_LV_MASK (0x400U) -#define CGU_FRO2M_TRIM_TEST_EN_LV_SHIFT (10U) -/*! TEST_EN_LV - TEST_EN_LV */ -#define CGU_FRO2M_TRIM_TEST_EN_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO2M_TRIM_TEST_EN_LV_SHIFT)) & CGU_FRO2M_TRIM_TEST_EN_LV_MASK) - -#define CGU_FRO2M_TRIM_EN_CKO_DIV16_LV_MASK (0x800U) -#define CGU_FRO2M_TRIM_EN_CKO_DIV16_LV_SHIFT (11U) -/*! EN_CKO_DIV16_LV - Test pin for BACEs test IDD */ -#define CGU_FRO2M_TRIM_EN_CKO_DIV16_LV(x) (((uint32_t)(((uint32_t)(x)) << CGU_FRO2M_TRIM_EN_CKO_DIV16_LV_SHIFT)) & CGU_FRO2M_TRIM_EN_CKO_DIV16_LV_MASK) -/*! @} */ +#define CGU_ACMP_CLK_ACMP1_CLK_EN_MASK (0x2U) +#define CGU_ACMP_CLK_ACMP1_CLK_EN_SHIFT (1U) +/*! ACMP1_CLK_EN - ACMP1 Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CGU_ACMP_CLK_ACMP1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_ACMP1_CLK_EN_SHIFT)) & CGU_ACMP_CLK_ACMP1_CLK_EN_MASK) -/*! @name ACMP_CLK_DIV - ACMP Clock Divider */ -/*! @{ */ +#define CGU_ACMP_CLK_ACMP_CLK0_DIV_EN_MASK (0x4U) +#define CGU_ACMP_CLK_ACMP_CLK0_DIV_EN_SHIFT (2U) +/*! ACMP_CLK0_DIV_EN - ACMP Clock 0 Divider Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CGU_ACMP_CLK_ACMP_CLK0_DIV_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_ACMP_CLK0_DIV_EN_SHIFT)) & CGU_ACMP_CLK_ACMP_CLK0_DIV_EN_MASK) -#define CGU_ACMP_CLK_DIV_ACMP0_CLK_EN_MASK (0x1U) -#define CGU_ACMP_CLK_DIV_ACMP0_CLK_EN_SHIFT (0U) -/*! ACMP0_CLK_EN - ACMP0 Clock Enable */ -#define CGU_ACMP_CLK_DIV_ACMP0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_DIV_ACMP0_CLK_EN_SHIFT)) & CGU_ACMP_CLK_DIV_ACMP0_CLK_EN_MASK) - -#define CGU_ACMP_CLK_DIV_ACMP1_CLK_EN_MASK (0x2U) -#define CGU_ACMP_CLK_DIV_ACMP1_CLK_EN_SHIFT (1U) -/*! ACMP1_CLK_EN - ACMP1 Clock Enable */ -#define CGU_ACMP_CLK_DIV_ACMP1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_DIV_ACMP1_CLK_EN_SHIFT)) & CGU_ACMP_CLK_DIV_ACMP1_CLK_EN_MASK) - -#define CGU_ACMP_CLK_DIV_ACMP_CLK0_DIV_EN_MASK (0x4U) -#define CGU_ACMP_CLK_DIV_ACMP_CLK0_DIV_EN_SHIFT (2U) -/*! ACMP_CLK0_DIV_EN - ACMP Clock 0 Divider Enable */ -#define CGU_ACMP_CLK_DIV_ACMP_CLK0_DIV_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_DIV_ACMP_CLK0_DIV_EN_SHIFT)) & CGU_ACMP_CLK_DIV_ACMP_CLK0_DIV_EN_MASK) - -#define CGU_ACMP_CLK_DIV_ACMP_CLK1_DIV_EN_MASK (0x8U) -#define CGU_ACMP_CLK_DIV_ACMP_CLK1_DIV_EN_SHIFT (3U) -/*! ACMP_CLK1_DIV_EN - ACMP Clock 1 Divider Enable */ -#define CGU_ACMP_CLK_DIV_ACMP_CLK1_DIV_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_DIV_ACMP_CLK1_DIV_EN_SHIFT)) & CGU_ACMP_CLK_DIV_ACMP_CLK1_DIV_EN_MASK) - -#define CGU_ACMP_CLK_DIV_AON_ACMP_CLK0_DIV_MASK (0xF0U) -#define CGU_ACMP_CLK_DIV_AON_ACMP_CLK0_DIV_SHIFT (4U) -/*! AON_ACMP_CLK0_DIV - ACMP Clock 0 Divider Enable */ -#define CGU_ACMP_CLK_DIV_AON_ACMP_CLK0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_DIV_AON_ACMP_CLK0_DIV_SHIFT)) & CGU_ACMP_CLK_DIV_AON_ACMP_CLK0_DIV_MASK) - -#define CGU_ACMP_CLK_DIV_AON_ACMP_CLK1_DIV_MASK (0xF00U) -#define CGU_ACMP_CLK_DIV_AON_ACMP_CLK1_DIV_SHIFT (8U) -/*! AON_ACMP_CLK1_DIV - ACMP Clock 1 Divider Enable */ -#define CGU_ACMP_CLK_DIV_AON_ACMP_CLK1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_DIV_AON_ACMP_CLK1_DIV_SHIFT)) & CGU_ACMP_CLK_DIV_AON_ACMP_CLK1_DIV_MASK) +#define CGU_ACMP_CLK_ACMP_CLK1_DIV_EN_MASK (0x8U) +#define CGU_ACMP_CLK_ACMP_CLK1_DIV_EN_SHIFT (3U) +/*! ACMP_CLK1_DIV_EN - ACMP Clock 1 Divider Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CGU_ACMP_CLK_ACMP_CLK1_DIV_EN(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_ACMP_CLK1_DIV_EN_SHIFT)) & CGU_ACMP_CLK_ACMP_CLK1_DIV_EN_MASK) + +#define CGU_ACMP_CLK_AON_ACMP_CLK0_DIV_MASK (0xF0U) +#define CGU_ACMP_CLK_AON_ACMP_CLK0_DIV_SHIFT (4U) +/*! AON_ACMP_CLK0_DIV - ACMP Clock 0 Divider Control + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b0010..Divide by 3 + * 0b0011..Divide by 4 + * 0b0100..Divide by 5 + * 0b0101..Divide by 6 + * 0b0110..Divide by 7 + * 0b0111..Divide by 8 + * 0b1000..Divide by 9 + * 0b1001..Divide by 10 + * 0b1010..Divide by 11 + * 0b1011..Divide by 12 + * 0b1100..Divide by 13 + * 0b1101..Divide by 14 + * 0b1110..Divide by 15 + * 0b1111..Divide by 16 + */ +#define CGU_ACMP_CLK_AON_ACMP_CLK0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_AON_ACMP_CLK0_DIV_SHIFT)) & CGU_ACMP_CLK_AON_ACMP_CLK0_DIV_MASK) + +#define CGU_ACMP_CLK_AON_ACMP_CLK1_DIV_MASK (0xF00U) +#define CGU_ACMP_CLK_AON_ACMP_CLK1_DIV_SHIFT (8U) +/*! AON_ACMP_CLK1_DIV - ACMP Clock 1 Divider Control + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b0010..Divide by 3 + * 0b0011..Divide by 4 + * 0b0100..Divide by 5 + * 0b0101..Divide by 6 + * 0b0110..Divide by 7 + * 0b0111..Divide by 8 + * 0b1000..Divide by 9 + * 0b1001..Divide by 10 + * 0b1010..Divide by 11 + * 0b1011..Divide by 12 + * 0b1100..Divide by 13 + * 0b1101..Divide by 14 + * 0b1110..Divide by 15 + * 0b1111..Divide by 16 + */ +#define CGU_ACMP_CLK_AON_ACMP_CLK1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CGU_ACMP_CLK_AON_ACMP_CLK1_DIV_SHIFT)) & CGU_ACMP_CLK_AON_ACMP_CLK1_DIV_MASK) /*! @} */ /*! @name INT - Interrupt Flag */ @@ -649,7 +641,7 @@ typedef struct { #define CGU_INT_SEC_RST_IE_MASK (0x4U) #define CGU_INT_SEC_RST_IE_SHIFT (2U) -/*! SEC_RST_IE - Security Reset Interrupt */ +/*! SEC_RST_IE - Security Reset Interrupt Enable */ #define CGU_INT_SEC_RST_IE(x) (((uint32_t)(((uint32_t)(x)) << CGU_INT_SEC_RST_IE_SHIFT)) & CGU_INT_SEC_RST_IE_MASK) #define CGU_INT_AUTO_CAL_VAL_IF_MASK (0x100U) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CMC.h index f2ce7bca3..79bdcad14 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CMC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_CMC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for CMC * * CMSIS Peripheral Access Layer for CMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CRC.h index 324869258..fbf0aa96a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CRC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_CRC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for CRC * * CMSIS Peripheral Access Layer for CRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CTIMER.h index db0dcb24f..3a867f6d4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CTIMER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_CTIMER.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for CTIMER @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_CTIMER.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for CTIMER * * CMSIS Peripheral Access Layer for CTIMER diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_DEBUGMAILBOX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_DEBUGMAILBOX.h index 9ae9c6c3f..ab6b50011 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_DEBUGMAILBOX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_DEBUGMAILBOX.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for DEBUGMAILBOX @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_DEBUGMAILBOX.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for DEBUGMAILBOX * * CMSIS Peripheral Access Layer for DEBUGMAILBOX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_DMA.h index ba34ee2b0..dc028deed 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_DMA.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_DMA.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for DMA * * CMSIS Peripheral Access Layer for DMA diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ERM.h index 2bc6c46b5..ef966477e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ERM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_ERM.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for ERM @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_ERM.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for ERM * * CMSIS Peripheral Access Layer for ERM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMC.h index c86f692a2..5cc4ab897 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_FMC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for FMC * * CMSIS Peripheral Access Layer for FMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMU.h index 3c38a8623..ff0df4a6e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMU.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMU @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_FMU.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for FMU * * CMSIS Peripheral Access Layer for FMU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMUTEST.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMUTEST.h index 7954340f6..7440d5b5e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMUTEST.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FMUTEST.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMUTEST @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_FMUTEST.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for FMUTEST * * CMSIS Peripheral Access Layer for FMUTEST diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FREQME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FREQME.h index e9d7eeb7d..951749065 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FREQME.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_FREQME.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for FREQME @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_FREQME.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for FREQME * * CMSIS Peripheral Access Layer for FREQME diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_GLIKEY.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_GLIKEY.h index f93209c7d..d9104ab8c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_GLIKEY.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_GLIKEY.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for GLIKEY @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_GLIKEY.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for GLIKEY * * CMSIS Peripheral Access Layer for GLIKEY diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_GPIO.h index cb66c06ce..749cadfa3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_GPIO.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_GPIO.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for GPIO * * CMSIS Peripheral Access Layer for GPIO diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_INPUTMUX_AON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_INPUTMUX_AON.h index df637b160..99fcd5e97 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_INPUTMUX_AON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_INPUTMUX_AON.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for INPUTMUX_AON @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_INPUTMUX_AON.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for INPUTMUX_AON * * CMSIS Peripheral Access Layer for INPUTMUX_AON @@ -158,10 +158,10 @@ typedef struct { * 0b000111..AON_TRIG_IN6 input is selected * 0b001000..AON_TRIG_IN7 input is selected * 0b001001..CM33 transmit event is selected - * 0b001010..QTMR1_tmr0_output is selected - * 0b001011..QTMR1_tmr1_output is selected - * 0b001100..QTMR1_tmr2_output is selected - * 0b001101..QTMR1_tmr3_output is selected + * 0b001010..QTMR1 counter[0] direction is selected + * 0b001011..QTMR1 counter[1] direction is selected + * 0b001100..QTMR1 counter[2] direction is selected + * 0b001101..QTMR1 counter[3] direction is selected * 0b001110..CMP0_OUT is selected * 0b001111..Reserved * 0b010000..LPI2C0 Controller End of Packet is selected @@ -174,24 +174,24 @@ typedef struct { * 0b010111..Reserved * 0b011000..Reserved * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected * 0b011110..LPTMR0 output is selected * 0b011111..Reserved * 0b100000..LC_ROT_SOC_LOGIC_OUT1 is selected * 0b100001..LC_ROT_SOC_LOGIC_OUT2 is selected * 0b100010..LC_ROT_SOC_LOGIC_OUT3 is selected * 0b100011..LC_ROT_SOC_LOGIC_OUT4 is selected - * 0b100100..QTMR0_tmr0_dir is selected - * 0b100101..QTMR0_tmr1_dir is selected - * 0b100110..QTMR0_tmr2_dir is selected - * 0b100111..QTMR0_tmr3_dir is selected - * 0b101000..QTMR1_tmr0_dir is selected - * 0b101001..QTMR1_tmr1_dir is selected - * 0b101010..QTMR1_tmr2_dir is selected - * 0b101011..QTMR1_tmr3_dir is selected + * 0b100100..QTMR0 counter[0] direction is selected + * 0b100101..QTMR0 counter[1] direction is selected + * 0b100110..QTMR0 counter[2] direction is selected + * 0b100111..QTMR0 counter[3] direction is selected + * 0b101000..QTMR1 counter[0] direction is selected + * 0b101001..QTMR1 counter[1] direction is selected + * 0b101010..QTMR1 counter[2] direction is selected + * 0b101011..QTMR1 counter[3] direction is selected * 0b101100..ACMP0 raw analog comparator output is selected * 0b101101..ACMP0_AON_cout is selected * 0b101110..logic_0 is selected @@ -201,10 +201,10 @@ typedef struct { * 0b110010..Reserved * 0b110011..soc_glue_XOR0_out is selected * 0b110100..Reserved - * 0b110101..QTMR0_tmr0_output is selected - * 0b110110..QTMR0_tmr1_output is selected - * 0b110111..QTMR0_tmr2_output is selected - * 0b111000..QTMR0_tmr3_output is selected + * 0b110101..QTMR0 counter[0] direction is selected + * 0b110110..QTMR0 counter[1] direction is selected + * 0b110111..QTMR0 counter[2] direction is selected + * 0b111000..QTMR0 counter[3] direction is selected * 0b111001..LCSense_Sequencer_Primary_Trigger_glue_out is selected */ #define INPUTMUX_AON_QTMR0_TMR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AON_QTMR0_TMR_INP_SHIFT)) & INPUTMUX_AON_QTMR0_TMR_INP_MASK) @@ -229,10 +229,10 @@ typedef struct { * 0b000111..AON_TRIG_IN6 input is selected * 0b001000..AON_TRIG_IN7 input is selected * 0b001001..CM33 transmit event is selected - * 0b001010..QTMR1_tmr0_output is selected - * 0b001011..QTMR1_tmr1_output is selected - * 0b001100..QTMR1_tmr2_output is selected - * 0b001101..QTMR1_tmr3_output is selected + * 0b001010..QTMR1 channel[0] output is selected + * 0b001011..QTMR1 channel[1] output is selected + * 0b001100..QTMR1 channel[2] output is selected + * 0b001101..QTMR1 channel[3] output is selected * 0b001110..CMP0_OUT is selected * 0b001111..Reserved * 0b010000..LPI2C0 Controller End of Packet is selected @@ -245,24 +245,24 @@ typedef struct { * 0b010111..Reserved * 0b011000..Reserved * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected - * 0b011110..LPTMR0 output is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected + * 0b011110..AON.LPTMR0 output is selected * 0b011111..Reserved * 0b100000..LC_ROT_SOC_LOGIC_OUT1 is selected * 0b100001..LC_ROT_SOC_LOGIC_OUT2 is selected * 0b100010..LC_ROT_SOC_LOGIC_OUT3 is selected * 0b100011..LC_ROT_SOC_LOGIC_OUT4 is selected - * 0b100100..QTMR0_tmr0_dir is selected - * 0b100101..QTMR0_tmr1_dir is selected - * 0b100110..QTMR0_tmr2_dir is selected - * 0b100111..QTMR0_tmr3_dir is selected - * 0b101000..QTMR1_tmr0_dir is selected - * 0b101001..QTMR1_tmr1_dir is selected - * 0b101010..QTMR1_tmr2_dir is selected - * 0b101011..QTMR1_tmr3_dir is selected + * 0b100100..QTMR0 counter[0] direction is selected + * 0b100101..QTMR0 counter[1] direction is selected + * 0b100110..QTMR0 counter[2] direction is selected + * 0b100111..QTMR0 counter[3] direction is selected + * 0b101000..QTMR1 counter[0] direction is selected + * 0b101001..QTMR1 counter[1] direction is selected + * 0b101010..QTMR1 counter[2] direction is selected + * 0b101011..QTMR1 counter[3] direction is selected * 0b101100..ACMP0 raw analog comparator output is selected * 0b101101..ACMP0_AON_cout is selected * 0b101110..logic_0 is selected @@ -272,10 +272,10 @@ typedef struct { * 0b110010..Reserved * 0b110011..soc_glue_XOR0_out is selected * 0b110100..Reserved - * 0b110101..QTMR0_tmr0_output is selected - * 0b110110..QTMR0_tmr1_output is selected - * 0b110111..QTMR0_tmr2_output is selected - * 0b111000..QTMR0_tmr3_output is selected + * 0b110101..QTMR0 channel[0] output is selected + * 0b110110..QTMR0 channel[1] output is selected + * 0b110111..QTMR0 channel[2] output is selected + * 0b111000..QTMR0 channel[3] output is selected * 0b111001..LCSense_Sequencer_Primary_Trigger_glue_out is selected */ #define INPUTMUX_AON_SOC_GLUE_XOR0_IN_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AON_SOC_GLUE_XOR0_IN_INP_SHIFT)) & INPUTMUX_AON_SOC_GLUE_XOR0_IN_INP_MASK) @@ -300,10 +300,10 @@ typedef struct { * 0b000111..AON_TRIG_IN6 input is selected * 0b001000..AON_TRIG_IN7 input is selected * 0b001001..CM33 transmit event is selected - * 0b001010..QTMR1_tmr0_output is selected - * 0b001011..QTMR1_tmr1_output is selected - * 0b001100..QTMR1_tmr2_output is selected - * 0b001101..QTMR1_tmr3_output is selected + * 0b001010..QTMR1 channel[0] output is selected + * 0b001011..QTMR1 channel[1] output is selected + * 0b001100..QTMR1 channel[2] output is selected + * 0b001101..QTMR1 channel[3] output is selected * 0b001110..CMP0_OUT is selected * 0b001111..Reserved * 0b010000..LPI2C0 Controller End of Packet is selected @@ -316,24 +316,24 @@ typedef struct { * 0b010111..Reserved * 0b011000..Reserved * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected - * 0b011110..LPTMR0 output is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected + * 0b011110..AON.LPTMR0 output is selected * 0b011111..Reserved * 0b100000..LC_ROT_SOC_LOGIC_OUT1 is selected * 0b100001..LC_ROT_SOC_LOGIC_OUT2 is selected * 0b100010..LC_ROT_SOC_LOGIC_OUT3 is selected * 0b100011..LC_ROT_SOC_LOGIC_OUT4 is selected - * 0b100100..QTMR0_tmr0_dir is selected - * 0b100101..QTMR0_tmr1_dir is selected - * 0b100110..QTMR0_tmr2_dir is selected - * 0b100111..QTMR0_tmr3_dir is selected - * 0b101000..QTMR1_tmr0_dir is selected - * 0b101001..QTMR1_tmr1_dir is selected - * 0b101010..QTMR1_tmr2_dir is selected - * 0b101011..QTMR1_tmr3_dir is selected + * 0b100100..QTMR0 counter[0] direction is selected + * 0b100101..QTMR0 counter[1] direction is selected + * 0b100110..QTMR0 counter[2] direction is selected + * 0b100111..QTMR0 counter[3] direction is selected + * 0b101000..QTMR1 counter[0] direction is selected + * 0b101001..QTMR1 counter[1] direction is selected + * 0b101010..QTMR1 counter[2] direction is selected + * 0b101011..QTMR1 counter[3] direction is selected * 0b101100..ACMP0 raw analog comparator output is selected * 0b101101..ACMP0_AON_cout is selected * 0b101110..logic_0 is selected @@ -343,10 +343,10 @@ typedef struct { * 0b110010..Reserved * 0b110011..soc_glue_XOR0_out is selected * 0b110100..Reserved - * 0b110101..QTMR0_tmr0_output is selected - * 0b110110..QTMR0_tmr1_output is selected - * 0b110111..QTMR0_tmr2_output is selected - * 0b111000..QTMR0_tmr3_output is selected + * 0b110101..QTMR0 channel[0] output is selected + * 0b110110..QTMR0 channel[1] output is selected + * 0b110111..QTMR0 channel[2] output is selected + * 0b111000..QTMR0 channel[3] output is selected * 0b111001..LCSense_Sequencer_Primary_Trigger_glue_out is selected */ #define INPUTMUX_AON_SOC_GLUE_CMPPADS_PCTRL_XOR_IN0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AON_SOC_GLUE_CMPPADS_PCTRL_XOR_IN0_INP_SHIFT)) & INPUTMUX_AON_SOC_GLUE_CMPPADS_PCTRL_XOR_IN0_INP_MASK) @@ -368,10 +368,10 @@ typedef struct { * 0b000111..AON_TRIG_IN6 input is selected * 0b001000..AON_TRIG_IN7 input is selected * 0b001001..CM33 transmit event is selected - * 0b001010..QTMR1_tmr0_output is selected - * 0b001011..QTMR1_tmr1_output is selected - * 0b001100..QTMR1_tmr2_output is selected - * 0b001101..QTMR1_tmr3_output is selected + * 0b001010..QTMR1 channel[0] output is selected + * 0b001011..QTMR1 channel[1] output is selected + * 0b001100..QTMR1 channel[2] output is selected + * 0b001101..QTMR1 channel[3] output is selected * 0b001110..CMP0_OUT is selected * 0b001111..Reserved * 0b010000..LPI2C0 Controller End of Packet is selected @@ -384,24 +384,24 @@ typedef struct { * 0b010111..Reserved * 0b011000..Reserved * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected - * 0b011110..LPTMR0 output is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected + * 0b011110..AON.LPTMR0 output is selected * 0b011111..Reserved * 0b100000..LC_ROT_SOC_LOGIC_OUT1 is selected * 0b100001..LC_ROT_SOC_LOGIC_OUT2 is selected * 0b100010..LC_ROT_SOC_LOGIC_OUT3 is selected * 0b100011..LC_ROT_SOC_LOGIC_OUT4 is selected - * 0b100100..QTMR0_tmr0_dir is selected - * 0b100101..QTMR0_tmr1_dir is selected - * 0b100110..QTMR0_tmr2_dir is selected - * 0b100111..QTMR0_tmr3_dir is selected - * 0b101000..QTMR1_tmr0_dir is selected - * 0b101001..QTMR1_tmr1_dir is selected - * 0b101010..QTMR1_tmr2_dir is selected - * 0b101011..QTMR1_tmr3_dir is selected + * 0b100100..QTMR0 counter[0] direction is selected + * 0b100101..QTMR0 counter[1] direction is selected + * 0b100110..QTMR0 counter[2] direction is selected + * 0b100111..QTMR0 counter[3] direction is selected + * 0b101000..QTMR1 counter[0] direction is selected + * 0b101001..QTMR1 counter[1] direction is selected + * 0b101010..QTMR1 counter[2] direction is selected + * 0b101011..QTMR1 counter[3] direction is selected * 0b101100..ACMP0 raw analog comparator output is selected * 0b101101..ACMP0_AON_cout is selected * 0b101110..logic_0 is selected @@ -411,10 +411,10 @@ typedef struct { * 0b110010..Reserved * 0b110011..soc_glue_XOR0_out is selected * 0b110100..Reserved - * 0b110101..QTMR0_tmr0_output is selected - * 0b110110..QTMR0_tmr1_output is selected - * 0b110111..QTMR0_tmr2_output is selected - * 0b111000..QTMR0_tmr3_output is selected + * 0b110101..QTMR0 channel[0] output is selected + * 0b110110..QTMR0 channel[1] output is selected + * 0b110111..QTMR0 channel[2] output is selected + * 0b111000..QTMR0 channel[3] output is selected * 0b111001..LCSense_Sequencer_Primary_Trigger_glue_out is selected */ #define INPUTMUX_AON_SOC_GLUE_CTRLPADS_PCTRL_XOR_IN0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AON_SOC_GLUE_CTRLPADS_PCTRL_XOR_IN0_INP_SHIFT)) & INPUTMUX_AON_SOC_GLUE_CTRLPADS_PCTRL_XOR_IN0_INP_MASK) @@ -425,7 +425,7 @@ typedef struct { #define INPUTMUX_AON_QTMR1_TMR_INP_MASK (0x3FU) #define INPUTMUX_AON_QTMR1_TMR_INP_SHIFT (0U) -/*! INP - Input number for AON QTMR0 +/*! INP - Input number for AON QTMR1 * 0b000000..Reserved * 0b000001..AON_TRIG_IN0 input is selected * 0b000010..AON_TRIG_IN1 input is selected @@ -436,10 +436,10 @@ typedef struct { * 0b000111..AON_TRIG_IN6 input is selected * 0b001000..AON_TRIG_IN7 input is selected * 0b001001..CM33 transmit event is selected - * 0b001010..QTMR1_tmr0_output is selected - * 0b001011..QTMR1_tmr1_output is selected - * 0b001100..QTMR1_tmr2_output is selected - * 0b001101..QTMR1_tmr3_output is selected + * 0b001010..QTMR1 channel[0] output is selected + * 0b001011..QTMR1 channel[1] output is selected + * 0b001100..QTMR1 channel[2] output is selected + * 0b001101..QTMR1 channel[3] output is selected * 0b001110..CMP0_OUT is selected * 0b001111..Reserved * 0b010000..LPI2C0 Controller End of Packet is selected @@ -452,24 +452,24 @@ typedef struct { * 0b010111..Reserved * 0b011000..Reserved * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected - * 0b011110..LPTMR0 output is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected + * 0b011110..AON.LPTMR0 output is selected * 0b011111..Reserved * 0b100000..LC_ROT_SOC_LOGIC_OUT1 is selected * 0b100001..LC_ROT_SOC_LOGIC_OUT2 is selected * 0b100010..LC_ROT_SOC_LOGIC_OUT3 is selected * 0b100011..LC_ROT_SOC_LOGIC_OUT4 is selected - * 0b100100..QTMR0_tmr0_dir is selected - * 0b100101..QTMR0_tmr1_dir is selected - * 0b100110..QTMR0_tmr2_dir is selected - * 0b100111..QTMR0_tmr3_dir is selected - * 0b101000..QTMR1_tmr0_dir is selected - * 0b101001..QTMR1_tmr1_dir is selected - * 0b101010..QTMR1_tmr2_dir is selected - * 0b101011..QTMR1_tmr3_dir is selected + * 0b100100..QTMR0 counter[0] direction is selected + * 0b100101..QTMR0 counter[1] direction is selected + * 0b100110..QTMR0 counter[2] direction is selected + * 0b100111..QTMR0 counter[3] direction is selected + * 0b101000..QTMR1 counter[0] direction is selected + * 0b101001..QTMR1 counter[1] direction is selected + * 0b101010..QTMR1 counter[2] direction is selected + * 0b101011..QTMR1 counter[3] direction is selected * 0b101100..ACMP0 raw analog comparator output is selected * 0b101101..ACMP0_AON_cout is selected * 0b101110..logic_0 is selected @@ -479,10 +479,10 @@ typedef struct { * 0b110010..Reserved * 0b110011..soc_glue_XOR0_out is selected * 0b110100..Reserved - * 0b110101..QTMR0_tmr0_output is selected - * 0b110110..QTMR0_tmr1_output is selected - * 0b110111..QTMR0_tmr2_output is selected - * 0b111000..QTMR0_tmr3_output is selected + * 0b110101..QTMR0 channel[0] output is selected + * 0b110110..QTMR0 channel[1] output is selected + * 0b110111..QTMR0 channel[2] output is selected + * 0b111000..QTMR0 channel[3] output is selected * 0b111001..LCSense_Sequencer_Primary_Trigger_glue_out is selected */ #define INPUTMUX_AON_QTMR1_TMR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AON_QTMR1_TMR_INP_SHIFT)) & INPUTMUX_AON_QTMR1_TMR_INP_MASK) @@ -507,10 +507,10 @@ typedef struct { * 0b000111..AON_TRIG_IN6 input is selected * 0b001000..AON_TRIG_IN7 input is selected * 0b001001..CM33 transmit event is selected - * 0b001010..QTMR1_tmr0_output is selected - * 0b001011..QTMR1_tmr1_output is selected - * 0b001100..QTMR1_tmr2_output is selected - * 0b001101..QTMR1_tmr3_output is selected + * 0b001010..QTMR1 channel[0] output is selected + * 0b001011..QTMR1 channel[1] output is selected + * 0b001100..QTMR1 channel[2] output is selected + * 0b001101..QTMR1 channel[3] output is selected * 0b001110..CMP0_OUT is selected * 0b001111..Reserved * 0b010000..LPI2C0 Controller End of Packet is selected @@ -523,24 +523,24 @@ typedef struct { * 0b010111..Reserved * 0b011000..Reserved * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected - * 0b011110..LPTMR0 output is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected + * 0b011110..AON.LPTMR0 output is selected * 0b011111..Reserved * 0b100000..LC_ROT_SOC_LOGIC_OUT1 is selected * 0b100001..LC_ROT_SOC_LOGIC_OUT2 is selected * 0b100010..LC_ROT_SOC_LOGIC_OUT3 is selected * 0b100011..LC_ROT_SOC_LOGIC_OUT4 is selected - * 0b100100..QTMR0_tmr0_dir is selected - * 0b100101..QTMR0_tmr1_dir is selected - * 0b100110..QTMR0_tmr2_dir is selected - * 0b100111..QTMR0_tmr3_dir is selected - * 0b101000..QTMR1_tmr0_dir is selected - * 0b101001..QTMR1_tmr1_dir is selected - * 0b101010..QTMR1_tmr2_dir is selected - * 0b101011..QTMR1_tmr3_dir is selected + * 0b100100..QTMR0 counter[0] direction is selected + * 0b100101..QTMR0 counter[1] direction is selected + * 0b100110..QTMR0 counter[2] direction is selected + * 0b100111..QTMR0 counter[3] direction is selected + * 0b101000..QTMR1 counter[0] direction is selected + * 0b101001..QTMR1 counter[1] direction is selected + * 0b101010..QTMR1 counter[2] direction is selected + * 0b101011..QTMR1 counter[3] direction is selected * 0b101100..ACMP0 raw analog comparator output is selected * 0b101101..ACMP0_AON_cout is selected * 0b101110..logic_0 is selected @@ -550,10 +550,10 @@ typedef struct { * 0b110010..Reserved * 0b110011..soc_glue_XOR0_out is selected * 0b110100..Reserved - * 0b110101..QTMR0_tmr0_output is selected - * 0b110110..QTMR0_tmr1_output is selected - * 0b110111..QTMR0_tmr2_output is selected - * 0b111000..QTMR0_tmr3_output is selected + * 0b110101..QTMR0 channel[0] output is selected + * 0b110110..QTMR0 channel[1] output is selected + * 0b110111..QTMR0 channel[2] output is selected + * 0b111000..QTMR0 channel[3] output is selected * 0b111001..LCSense_Sequencer_Primary_Trigger_glue_out is selected */ #define INPUTMUX_AON_LC_ROT_SOC_LOGIC_IN_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AON_LC_ROT_SOC_LOGIC_IN_INP_SHIFT)) & INPUTMUX_AON_LC_ROT_SOC_LOGIC_IN_INP_MASK) @@ -575,10 +575,10 @@ typedef struct { * 0b000111..AON_TRIG_IN6 input is selected * 0b001000..AON_TRIG_IN7 input is selected * 0b001001..CM33 transmit event is selected - * 0b001010..QTMR1_tmr0_output is selected - * 0b001011..QTMR1_tmr1_output is selected - * 0b001100..QTMR1_tmr2_output is selected - * 0b001101..QTMR1_tmr3_output is selected + * 0b001010..QTMR1 channel[0] output is selected + * 0b001011..QTMR1 channel[1] output is selected + * 0b001100..QTMR1 channel[2] output is selected + * 0b001101..QTMR1 channel[3] output is selected * 0b001110..CMP0_OUT is selected * 0b001111..Reserved * 0b010000..LPI2C0 Controller End of Packet is selected @@ -591,24 +591,24 @@ typedef struct { * 0b010111..Reserved * 0b011000..Reserved * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected - * 0b011110..LPTMR0 output is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected + * 0b011110..AON.LPTMR0 output is selected * 0b011111..Reserved * 0b100000..LC_ROT_SOC_LOGIC_OUT1 is selected * 0b100001..LC_ROT_SOC_LOGIC_OUT2 is selected * 0b100010..LC_ROT_SOC_LOGIC_OUT3 is selected * 0b100011..LC_ROT_SOC_LOGIC_OUT4 is selected - * 0b100100..QTMR0_tmr0_dir is selected - * 0b100101..QTMR0_tmr1_dir is selected - * 0b100110..QTMR0_tmr2_dir is selected - * 0b100111..QTMR0_tmr3_dir is selected - * 0b101000..QTMR1_tmr0_dir is selected - * 0b101001..QTMR1_tmr1_dir is selected - * 0b101010..QTMR1_tmr2_dir is selected - * 0b101011..QTMR1_tmr3_dir is selected + * 0b100100..QTMR0 counter[0] direction is selected + * 0b100101..QTMR0 counter[1] direction is selected + * 0b100110..QTMR0 counter[2] direction is selected + * 0b100111..QTMR0 counter[3] direction is selected + * 0b101000..QTMR1 counter[0] direction is selected + * 0b101001..QTMR1 counter[1] direction is selected + * 0b101010..QTMR1 counter[2] direction is selected + * 0b101011..QTMR1 counter[3] direction is selected * 0b101100..ACMP0 raw analog comparator output is selected * 0b101101..ACMP0_AON_cout is selected * 0b101110..logic_0 is selected @@ -618,10 +618,10 @@ typedef struct { * 0b110010..Reserved * 0b110011..soc_glue_XOR0_out is selected * 0b110100..Reserved - * 0b110101..QTMR0_tmr0_output is selected - * 0b110110..QTMR0_tmr1_output is selected - * 0b110111..QTMR0_tmr2_output is selected - * 0b111000..QTMR0_tmr3_output is selected + * 0b110101..QTMR0 channel[0] output is selected + * 0b110110..QTMR0 channel[1] output is selected + * 0b110111..QTMR0 channel[2] output is selected + * 0b111000..QTMR0 channel[3] output is selected * 0b111001..LCSense_Sequencer_Primary_Trigger_glue_out is selected */ #define INPUTMUX_AON_LCSENSE_SEQ_PTRIG_GLUE_IN_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AON_LCSENSE_SEQ_PTRIG_GLUE_IN_INP_SHIFT)) & INPUTMUX_AON_LCSENSE_SEQ_PTRIG_GLUE_IN_INP_MASK) @@ -643,10 +643,10 @@ typedef struct { * 0b000111..AON_TRIG_IN6 input is selected * 0b001000..AON_TRIG_IN7 input is selected * 0b001001..CM33 transmit event is selected - * 0b001010..QTMR1_tmr0_output is selected - * 0b001011..QTMR1_tmr1_output is selected - * 0b001100..QTMR1_tmr2_output is selected - * 0b001101..QTMR1_tmr3_output is selected + * 0b001010..QTMR1 channel[0] output is selected + * 0b001011..QTMR1 channel[1] output is selected + * 0b001100..QTMR1 channel[2] output is selected + * 0b001101..QTMR1 channel[3] output is selected * 0b001110..CMP0_OUT is selected * 0b001111..Reserved * 0b010000..LPI2C0 Controller End of Packet is selected @@ -659,24 +659,24 @@ typedef struct { * 0b010111..Reserved * 0b011000..Reserved * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected - * 0b011110..LPTMR0 output is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected + * 0b011110..AON.LPTMR0 output is selected * 0b011111..Reserved * 0b100000..LC_ROT_SOC_LOGIC_OUT1 is selected * 0b100001..LC_ROT_SOC_LOGIC_OUT2 is selected * 0b100010..LC_ROT_SOC_LOGIC_OUT3 is selected * 0b100011..LC_ROT_SOC_LOGIC_OUT4 is selected - * 0b100100..QTMR0_tmr0_dir is selected - * 0b100101..QTMR0_tmr1_dir is selected - * 0b100110..QTMR0_tmr2_dir is selected - * 0b100111..QTMR0_tmr3_dir is selected - * 0b101000..QTMR1_tmr0_dir is selected - * 0b101001..QTMR1_tmr1_dir is selected - * 0b101010..QTMR1_tmr2_dir is selected - * 0b101011..QTMR1_tmr3_dir is selected + * 0b100100..QTMR0 counter[0] direction is selected + * 0b100101..QTMR0 counter[1] direction is selected + * 0b100110..QTMR0 counter[2] direction is selected + * 0b100111..QTMR0 counter[3] direction is selected + * 0b101000..QTMR1 counter[0] direction is selected + * 0b101001..QTMR1 counter[1] direction is selected + * 0b101010..QTMR1 counter[2] direction is selected + * 0b101011..QTMR1 counter[3] direction is selected * 0b101100..ACMP0 raw analog comparator output is selected * 0b101101..ACMP0_AON_cout is selected * 0b101110..logic_0 is selected @@ -686,10 +686,10 @@ typedef struct { * 0b110010..Reserved * 0b110011..soc_glue_XOR0_out is selected * 0b110100..Reserved - * 0b110101..QTMR0_tmr0_output is selected - * 0b110110..QTMR0_tmr1_output is selected - * 0b110111..QTMR0_tmr2_output is selected - * 0b111000..QTMR0_tmr3_output is selected + * 0b110101..QTMR0 channel[0] output is selected + * 0b110110..QTMR0 channel[1] output is selected + * 0b110111..QTMR0 channel[2] output is selected + * 0b111000..QTMR0 channel[3] output is selected * 0b111001..LCSense_Sequencer_Primary_Trigger_glue_out is selected */ #define INPUTMUX_AON_LCSENSE_SEQ_TICKS_GLUE_IN_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AON_LCSENSE_SEQ_TICKS_GLUE_IN_INP_SHIFT)) & INPUTMUX_AON_LCSENSE_SEQ_TICKS_GLUE_IN_INP_MASK) @@ -713,24 +713,24 @@ typedef struct { * 0b001001..CM33 transmit event is selected * 0b001010..Reserved * 0b001011..Reserved - * 0b001100..QTMR0_tmr0_output is selected - * 0b001101..QTMR0_tmr1_output is selected - * 0b001110..QTMR0_tmr2_output is selected - * 0b001111..QTMR0_tmr3_output is selected - * 0b010000..LPTMR0 output is selected + * 0b001100..QTMR0 channel[0] output is selected + * 0b001101..QTMR0 channel[1] output is selected + * 0b001110..QTMR0 channel[2] output is selected + * 0b001111..QTMR0 channel[3] output is selected + * 0b010000..AON.LPTMR0 output is selected * 0b010001..Reserved - * 0b010010..QTMR1_tmr0_output is selected - * 0b010011..QTMR1_tmr1_output is selected - * 0b010100..QTMR1_tmr2_output is selected - * 0b010101..QTMR1_tmr3_output is selected + * 0b010010..QTMR1 channel[0] output is selected + * 0b010011..QTMR1 channel[1] output is selected + * 0b010100..QTMR1 channel[2] output is selected + * 0b010101..QTMR1 channel[3] output is selected * 0b010110..Reserved - * 0b010111..WUU is selected + * 0b010111..WUU output is selected * 0b011000..GPIO (AON) Pin Event Trig 0 is selected * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected * 0b011110..ACMP0 raw analog comparator output is selected * 0b011111..ACMP0_AON_cout is selected * 0b100000..Reserved @@ -762,18 +762,18 @@ typedef struct { * 0b01001..CM33 transmit event is selected * 0b01010..LPCMP_OUT is selected * 0b01011..Reserved - * 0b01100..QTMR0_tmr0_output is selected - * 0b01101..QTMR0_tmr1_output is selected - * 0b01110..QTMR0_tmr2_output is selected - * 0b01111..QTMR0_tmr3_output is selected - * 0b10000..LPTMR0 output is selected + * 0b01100..QTMR0 channel[0] output is selected + * 0b01101..QTMR0 channel[1] output is selected + * 0b01110..QTMR0 channel[2] output is selected + * 0b01111..QTMR0 channel[3] output is selected + * 0b10000..AON.LPTMR0 output is selected * 0b10001..Reserved - * 0b10010..QTMR1_tmr0_output is selected - * 0b10011..QTMR1_tmr1_output is selected - * 0b10100..QTMR1_tmr2_output is selected - * 0b10101..QTMR1_tmr3_output is selected + * 0b10010..QTMR1 channel[0] output is selected + * 0b10011..QTMR1 channel[1] output is selected + * 0b10100..QTMR1 channel[2] output is selected + * 0b10101..QTMR1 channel[3] output is selected * 0b10110..Reserved - * 0b10111..WUU is selected + * 0b10111..WUU output is selected * 0b11000..GPIO (AON) Pin Event Trig 0 is selected * 0b11001..ACMP0 raw analog comparator output is selected * 0b11010..ACMP0_AON_cout is selected @@ -796,17 +796,17 @@ typedef struct { /*! INP - EXT trigger input connections * 0b00000..Reserved * 0b00001..CM33 transmit event is selected - * 0b00010..AON_LPUART0 (ipp_do_lpuart_txd) is selected + * 0b00010..AON_LPUART0 is selected * 0b00011..Reserved * 0b00100..Reserved * 0b00101..Reserved * 0b00110..Reserved * 0b00111..Reserved - * 0b01000..LPADC_trigger_out[0] is selected - * 0b01001..LPADC_trigger_out[1] is selected - * 0b01010..LPADC_trigger_out[2] is selected + * 0b01000..LPADC trigger complete pulse output[0] is selected + * 0b01001..LPADC trigger complete pulse output[1] is selected + * 0b01010..LPADC trigger complete pulse output[2] is selected * 0b01011..parked_out_intverted is selected - * 0b01100..AON_LPTMR0 output is selected + * 0b01100..AON.LPTMR0 output is selected * 0b01101..Reserved * 0b01110..LPCOMP0_out is selected * 0b01111..Reserved @@ -814,14 +814,14 @@ typedef struct { * 0b10001..ACMP0_AON_cout is selected * 0b10010..Reserved * 0b10011..Reserved - * 0b10100..QTMR0_tmr0_output is selected - * 0b10101..QTMR0_tmr1_output is selected - * 0b10110..QTMR0_tmr2_output is selected - * 0b10111..QTMR0_tmr3_output is selected - * 0b11000..QTMR1_tmr0_output is selected - * 0b11001..QTMR1_tmr1_output is selected - * 0b11010..QTMR1_tmr2_output is selected - * 0b11011..QTMR1_tmr3_output is selected + * 0b10100..QTMR0 channel[0] output is selected + * 0b10101..QTMR0 channel[1] output is selected + * 0b10110..QTMR0 channel[2] output is selected + * 0b10111..QTMR0 channel[3] output is selected + * 0b11000..QTMR1 channel[0] output is selected + * 0b11001..QTMR1 channel[1] output is selected + * 0b11010..QTMR1 channel[2] output is selected + * 0b11011..QTMR1 channel[3] output is selected */ #define INPUTMUX_AON_AON_TRIG_OUT_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AON_AON_TRIG_OUT_INP_SHIFT)) & INPUTMUX_AON_AON_TRIG_OUT_INP_MASK) /*! @} */ @@ -847,24 +847,24 @@ typedef struct { * 0b001001..CM33 transmit event is selected * 0b001010..LPCMP_OUT is selected * 0b001011..Reserved - * 0b001100..QTMR0_tmr0_output is selected - * 0b001101..QTMR0_tmr1_output is selected - * 0b001110..QTMR0_tmr2_output is selected - * 0b001111..QTMR0_tmr3_output is selected - * 0b010000..LPTMR0 output is selected + * 0b001100..QTMR0 channel[0] output is selected + * 0b001101..QTMR0 channel[1] output is selected + * 0b001110..QTMR0 channel[2] output is selected + * 0b001111..QTMR0 channel[3] output is selected + * 0b010000..AON.LPTMR0 output is selected * 0b010001..Reserved - * 0b010010..QTMR1_tmr0_output is selected - * 0b010011..QTMR1_tmr1_output is selected - * 0b010100..QTMR1_tmr2_output is selected - * 0b010101..QTMR1_tmr3_output is selected + * 0b010010..QTMR1 channel[0] output is selected + * 0b010011..QTMR1 channel[1] output is selected + * 0b010100..QTMR1 channel[2] output is selected + * 0b010101..QTMR1 channel[3] output is selected * 0b010110..Reserved - * 0b010111..WUU is selected + * 0b010111..WUU output is selected * 0b011000..GPIO (AON) Pin Event Trig 0 is selected * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected * 0b011110..Reserved * 0b011111..Reserved * 0b100000..Reserved @@ -893,24 +893,24 @@ typedef struct { * 0b001001..CM33 transmit event is selected * 0b001010..LPCMP_OUT is selected * 0b001011..Reserved - * 0b001100..QTMR0_tmr0_output is selected - * 0b001101..QTMR0_tmr1_output is selected - * 0b001110..QTMR0_tmr2_output is selected - * 0b001111..QTMR0_tmr3_output is selected - * 0b010000..LPTMR0 output is selected + * 0b001100..QTMR0 channel[0] output is selected + * 0b001101..QTMR0 channel[1] output is selected + * 0b001110..QTMR0 channel[2] output is selected + * 0b001111..QTMR0 channel[3] output is selected + * 0b010000..AON.LPTMR0 output is selected * 0b010001..Reserved - * 0b010010..QTMR1_tmr0_output is selected - * 0b010011..QTMR1_tmr1_output is selected - * 0b010100..QTMR1_tmr2_output is selected - * 0b010101..QTMR1_tmr3_output is selected + * 0b010010..QTMR1 channel[0] output is selected + * 0b010011..QTMR1 channel[1] output is selected + * 0b010100..QTMR1 channel[2] output is selected + * 0b010101..QTMR1 channel[3] output is selected * 0b010110..Reserved - * 0b010111..WUU is selected + * 0b010111..WUU output is selected * 0b011000..GPIO (AON) Pin Event Trig 0 is selected * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected * 0b011110..Reserved * 0b011111..Reserved * 0b100000..Reserved @@ -939,24 +939,24 @@ typedef struct { * 0b001001..CM33 transmit event is selected * 0b001010..LPCMP_OUT is selected * 0b001011..Reserved - * 0b001100..QTMR0_tmr0_output is selected - * 0b001101..QTMR0_tmr1_output is selected - * 0b001110..QTMR0_tmr2_output is selected - * 0b001111..QTMR0_tmr3_output is selected - * 0b010000..LPTMR0 output is selected + * 0b001100..QTMR0 channel[0] output is selected + * 0b001101..QTMR0 channel[1] output is selected + * 0b001110..QTMR0 channel[2] output is selected + * 0b001111..QTMR0 channel[3] output is selected + * 0b010000..AON.LPTMR0 output is selected * 0b010001..Reserved - * 0b010010..QTMR1_tmr0_output is selected - * 0b010011..QTMR1_tmr1_output is selected - * 0b010100..QTMR1_tmr2_output is selected - * 0b010101..QTMR1_tmr3_output is selected + * 0b010010..QTMR1 channel[0] output is selected + * 0b010011..QTMR1 channel[1] output is selected + * 0b010100..QTMR1 channel[2] output is selected + * 0b010101..QTMR1 channel[3] output is selected * 0b010110..Reserved - * 0b010111..WUU is selected + * 0b010111..WUU output is selected * 0b011000..GPIO (AON) Pin Event Trig 0 is selected * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected * 0b011110..ACMP0 raw analog comparator output is selected * 0b011111..ACMP0_AON_cout is selected * 0b100000..Reserved @@ -985,24 +985,24 @@ typedef struct { * 0b001001..CM33 transmit event is selected * 0b001010..LPCMP_OUT is selected * 0b001011..Reserved - * 0b001100..QTMR0_tmr0_output is selected - * 0b001101..QTMR0_tmr1_output is selected - * 0b001110..QTMR0_tmr2_output is selected - * 0b001111..QTMR0_tmr3_output is selected - * 0b010000..LPTMR0 output is selected + * 0b001100..QTMR0 channel[0] output is selected + * 0b001101..QTMR0 channel[1] output is selected + * 0b001110..QTMR0 channel[2] output is selected + * 0b001111..QTMR0 channel[3] output is selected + * 0b010000..AON.LPTMR0 output is selected * 0b010001..Reserved - * 0b010010..QTMR1_tmr0_output is selected - * 0b010011..QTMR1_tmr1_output is selected - * 0b010100..QTMR1_tmr2_output is selected - * 0b010101..QTMR1_tmr3_output is selected + * 0b010010..QTMR1 channel[0] output is selected + * 0b010011..QTMR1 channel[1] output is selected + * 0b010100..QTMR1 channel[2] output is selected + * 0b010101..QTMR1 channel[3] output is selected * 0b010110..Reserved - * 0b010111..WUU is selected + * 0b010111..WUU output is selected * 0b011000..GPIO (AON) Pin Event Trig 0 is selected * 0b011001..Reserved - * 0b011010..LPADC_trigger_out[0] is selected - * 0b011011..LPADC_trigger_out[1] is selected - * 0b011100..LPADC_trigger_out[2] is selected - * 0b011101..LPADC_trigger_out[3] is selected + * 0b011010..LPADC trigger complete pulse output[0] is selected + * 0b011011..LPADC trigger complete pulse output[1] is selected + * 0b011100..LPADC trigger complete pulse output[2] is selected + * 0b011101..LPADC trigger complete pulse output[3] is selected * 0b011110..ACMP0 raw analog comparator output is selected * 0b011111..ACMP0_AON_cout is selected * 0b100000..Reserved diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_INPUTMUX_MAIN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_INPUTMUX_MAIN.h index 7a333e72e..c43658129 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_INPUTMUX_MAIN.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_INPUTMUX_MAIN.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for INPUTMUX_MAIN @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_INPUTMUX_MAIN.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for INPUTMUX_MAIN * * CMSIS Peripheral Access Layer for INPUTMUX_MAIN @@ -117,26 +117,29 @@ typedef struct { __IO uint32_t CTIMER1TRIG; /**< Trigger register for CTIMER1, offset: 0x50 */ uint8_t RESERVED_2[12]; __IO uint32_t CTIMER2CAP[INPUTMUX_MAIN_CTIMERC_COUNT]; /**< Capture select register for CTIMER2 inputs, array offset: 0x60, array step: 0x4 */ - __IO uint32_t TIMER2TRIG; /**< Trigger register for CTIMER2 inputs, offset: 0x70 */ - uint8_t RESERVED_3[492]; + __IO uint32_t CTIMER2TRIG; /**< Trigger register for CTIMER2 inputs, offset: 0x70 */ + uint8_t RESERVED_3[268]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TAR; /**< Selection for frequency measurement target clock, offset: 0x184 */ + uint8_t RESERVED_4[216]; __IO uint32_t CMP0_TRIG; /**< CMP0 Input Connections, offset: 0x260 */ - uint8_t RESERVED_4[28]; + uint8_t RESERVED_5[28]; __IO uint32_t ADC0_TRIG[INPUTMUX_MAIN_ADC0_TRIGM_COUNT]; /**< ADC Trigger Input Connections, array offset: 0x280, array step: 0x4 */ - uint8_t RESERVED_5[432]; + uint8_t RESERVED_6[432]; __IO uint32_t AOI0_MUX[INPUTMUX_MAIN_AOI0_MUXK_COUNT]; /**< AOI0 Trigger Input Connections, array offset: 0x440, array step: 0x4 */ - uint8_t RESERVED_6[64]; + uint8_t RESERVED_7[64]; __IO uint32_t EXT_TRIG[INPUTMUX_MAIN_EXT_TRIGN_COUNT]; /**< EXT Trigger Connections, array offset: 0x4C0, array step: 0x4 */ - uint8_t RESERVED_7[192]; + uint8_t RESERVED_8[192]; __IO uint32_t LPI2C0_TRIG; /**< LPI2C0 Trigger Input Connections, offset: 0x5A0 */ - uint8_t RESERVED_8[28]; - __IO uint32_t LPI2C1_TRIG; /**< LPI2C1 Trigger Input Connections, offset: 0x5C0 */ uint8_t RESERVED_9[28]; - __IO uint32_t LPSPI0_TRIG; /**< LPSPI0 Trigger Input Connections, offset: 0x5E0 */ + __IO uint32_t LPI2C1_TRIG; /**< LPI2C1 Trigger Input Connections, offset: 0x5C0 */ uint8_t RESERVED_10[28]; - __IO uint32_t LPSPI1_TRIG; /**< LPSPI1 Trigger Input Connections, offset: 0x600 */ + __IO uint32_t LPSPI0_TRIG; /**< LPSPI0 Trigger Input Connections, offset: 0x5E0 */ uint8_t RESERVED_11[28]; - __IO uint32_t LPUART0r; /**< LPUART0 Trigger Input Connections, offset: 0x620, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART0' */ + __IO uint32_t LPSPI1_TRIG; /**< LPSPI1 Trigger Input Connections, offset: 0x600 */ uint8_t RESERVED_12[28]; + __IO uint32_t LPUART0r; /**< LPUART0 Trigger Input Connections, offset: 0x620, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART0' */ + uint8_t RESERVED_13[28]; __IO uint32_t LPUART1r; /**< LPUART1 Trigger Input Connections, offset: 0x640, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART1' */ } INPUTMUX_MAIN_Type; @@ -156,26 +159,26 @@ typedef struct { #define INPUTMUX_MAIN_CTIMER0CAP_INP_SHIFT (0U) /*! INP - Input number for CTIMER0 * 0b0000000..Reserved - * 0b0000001..CT_INP0 input is selected - * 0b0000010..CT_INP1 input is selected - * 0b0000011..CT_INP2 input is selected - * 0b0000100..CT_INP3 input is selected - * 0b0000101..CT_INP4 input is selected - * 0b0000110..CT_INP5 input is selected - * 0b0000111..CT_INP6 input is selected - * 0b0001000..CT_INP7 input is selected - * 0b0001001..CT_INP8 input is selected - * 0b0001010..CT_INP9 input is selected - * 0b0001011..CT_INP10 input is selected - * 0b0001100..CT_INP11 input is selected - * 0b0001101..CT_INP12 input is selected - * 0b0001110..CT_INP13 input is selected - * 0b0001111..CT_INP14 input is selected - * 0b0010000..CT_INP15 input is selected - * 0b0010001..CT_INP16 input is selected - * 0b0010010..CT_INP17 input is selected - * 0b0010011..CT_INP18 input is selected - * 0b0010100..CT_INP19 input is selected + * 0b0000001..TRIG_INP0 input is selected + * 0b0000010..TRIG_INP1 input is selected + * 0b0000011..TRIG_INP2 input is selected + * 0b0000100..TRIG_INP3 input is selected + * 0b0000101..TRIG_INP4 input is selected + * 0b0000110..TRIG_INP5 input is selected + * 0b0000111..TRIG_INP6 input is selected + * 0b0001000..TRIG_INP7 input is selected + * 0b0001001..TRIG_INP8 input is selected + * 0b0001010..TRIG_INP9 input is selected + * 0b0001011..TRIG_INP10 input is selected + * 0b0001100..TRIG_INP11 input is selected + * 0b0001101..TRIG_INP12 input is selected + * 0b0001110..TRIG_INP13 input is selected + * 0b0001111..TRIG_INP14 input is selected + * 0b0010000..TRIG_INP15 input is selected + * 0b0010001..TRIG_INP16 input is selected + * 0b0010010..TRIG_INP17 input is selected + * 0b0010011..TRIG_INP18 input is selected + * 0b0010100..TRIG_INP19 input is selected * 0b0010101..Reserved * 0b0010110..AOI0_OUT0 input is selected * 0b0010111..AOI0_OUT1 input is selected @@ -234,26 +237,26 @@ typedef struct { #define INPUTMUX_MAIN_CTIMER0TRIG_INP_SHIFT (0U) /*! INP - Input number for CTIMER0 * 0b0000000..Reserved - * 0b0000001..CT_INP0 input is selected - * 0b0000010..CT_INP1 input is selected - * 0b0000011..CT_INP2 input is selected - * 0b0000100..CT_INP3 input is selected - * 0b0000101..CT_INP4 input is selected - * 0b0000110..CT_INP5 input is selected - * 0b0000111..CT_INP6 input is selected - * 0b0001000..CT_INP7 input is selected - * 0b0001001..CT_INP8 input is selected - * 0b0001010..CT_INP9 input is selected - * 0b0001011..CT_INP10 input is selected - * 0b0001100..CT_INP11 input is selected - * 0b0001101..CT_INP12 input is selected - * 0b0001110..CT_INP13 input is selected - * 0b0001111..CT_INP14 input is selected - * 0b0010000..CT_INP15 input is selected - * 0b0010001..CT_INP16 input is selected - * 0b0010010..CT_INP17 input is selected - * 0b0010011..CT_INP18 input is selected - * 0b0010100..CT_INP19 input is selected + * 0b0000001..TRIG_INP0 input is selected + * 0b0000010..TRIG_INP1 input is selected + * 0b0000011..TRIG_INP2 input is selected + * 0b0000100..TRIG_INP3 input is selected + * 0b0000101..TRIG_INP4 input is selected + * 0b0000110..TRIG_INP5 input is selected + * 0b0000111..TRIG_INP6 input is selected + * 0b0001000..TRIG_INP7 input is selected + * 0b0001001..TRIG_INP8 input is selected + * 0b0001010..TRIG_INP9 input is selected + * 0b0001011..TRIG_INP10 input is selected + * 0b0001100..TRIG_INP11 input is selected + * 0b0001101..TRIG_INP12 input is selected + * 0b0001110..TRIG_INP13 input is selected + * 0b0001111..TRIG_INP14 input is selected + * 0b0010000..TRIG_INP15 input is selected + * 0b0010001..TRIG_INP16 input is selected + * 0b0010010..TRIG_INP17 input is selected + * 0b0010011..TRIG_INP18 input is selected + * 0b0010100..TRIG_INP19 input is selected * 0b0010101..Reserved * 0b0010110..AOI0_OUT0 input is selected * 0b0010111..AOI0_OUT1 input is selected @@ -309,26 +312,26 @@ typedef struct { #define INPUTMUX_MAIN_CTIMER1CAP_INP_SHIFT (0U) /*! INP - Input number for CTIMER1 * 0b0000000..Reserved - * 0b0000001..CT_INP0 input is selected - * 0b0000010..CT_INP1 input is selected - * 0b0000011..CT_INP2 input is selected - * 0b0000100..CT_INP3 input is selected - * 0b0000101..Reserved - * 0b0000110..CT_INP5 input is selected - * 0b0000111..CT_INP6 input is selected - * 0b0001000..CT_INP7 input is selected - * 0b0001001..CT_INP8 input is selected - * 0b0001010..CT_INP9 input is selected - * 0b0001011..CT_INP10 input is selected - * 0b0001100..CT_INP11 input is selected - * 0b0001101..CT_INP12 input is selected - * 0b0001110..CT_INP13 input is selected - * 0b0001111..CT_INP14 input is selected - * 0b0010000..CT_INP15 input is selected - * 0b0010001..CT_INP16 input is selected - * 0b0010010..CT_INP17 input is selected - * 0b0010011..CT_INP18 input is selected - * 0b0010100..CT_INP19 input is selected + * 0b0000001..TRIG_INP0 input is selected + * 0b0000010..TRIG_INP1 input is selected + * 0b0000011..TRIG_INP2 input is selected + * 0b0000100..TRIG_INP3 input is selected + * 0b0000101..TRIG_INP4 input is selected + * 0b0000110..TRIG_INP5 input is selected + * 0b0000111..TRIG_INP6 input is selected + * 0b0001000..TRIG_INP7 input is selected + * 0b0001001..TRIG_INP8 input is selected + * 0b0001010..TRIG_INP9 input is selected + * 0b0001011..TRIG_INP10 input is selected + * 0b0001100..TRIG_INP11 input is selected + * 0b0001101..TRIG_INP12 input is selected + * 0b0001110..TRIG_INP13 input is selected + * 0b0001111..TRIG_INP14 input is selected + * 0b0010000..TRIG_INP15 input is selected + * 0b0010001..TRIG_INP16 input is selected + * 0b0010010..TRIG_INP17 input is selected + * 0b0010011..TRIG_INP18 input is selected + * 0b0010100..TRIG_INP19 input is selected * 0b0010101..Reserved * 0b0010110..AOI0_OUT0 input is selected * 0b0010111..AOI0_OUT1 input is selected @@ -387,26 +390,26 @@ typedef struct { #define INPUTMUX_MAIN_CTIMER1TRIG_INP_SHIFT (0U) /*! INP - Input number for CTIMER1 * 0b0000000..Reserved - * 0b0000001..CT_INP0 input is selected - * 0b0000010..CT_INP1 input is selected - * 0b0000011..CT_INP2 input is selected - * 0b0000100..CT_INP3 input is selected - * 0b0000101..Reserved - * 0b0000110..CT_INP5 input is selected - * 0b0000111..CT_INP6 input is selected - * 0b0001000..CT_INP7 input is selected - * 0b0001001..CT_INP8 input is selected - * 0b0001010..CT_INP9 input is selected - * 0b0001011..CT_INP10 input is selected - * 0b0001100..CT_INP11 input is selected - * 0b0001101..CT_INP12 input is selected - * 0b0001110..CT_INP13 input is selected - * 0b0001111..CT_INP14 input is selected - * 0b0010000..CT_INP15 input is selected - * 0b0010001..CT_INP16 input is selected - * 0b0010010..CT_INP17 input is selected - * 0b0010011..CT_INP18 input is selected - * 0b0010100..CT_INP19 input is selected + * 0b0000001..TRIG_INP0 input is selected + * 0b0000010..TRIG_INP1 input is selected + * 0b0000011..TRIG_INP2 input is selected + * 0b0000100..TRIG_INP3 input is selected + * 0b0000101..TRIG_INP4 input is selected + * 0b0000110..TRIG_INP5 input is selected + * 0b0000111..TRIG_INP6 input is selected + * 0b0001000..TRIG_INP7 input is selected + * 0b0001001..TRIG_INP8 input is selected + * 0b0001010..TRIG_INP9 input is selected + * 0b0001011..TRIG_INP10 input is selected + * 0b0001100..TRIG_INP11 input is selected + * 0b0001101..TRIG_INP12 input is selected + * 0b0001110..TRIG_INP13 input is selected + * 0b0001111..TRIG_INP14 input is selected + * 0b0010000..TRIG_INP15 input is selected + * 0b0010001..TRIG_INP16 input is selected + * 0b0010010..TRIG_INP17 input is selected + * 0b0010011..TRIG_INP18 input is selected + * 0b0010100..TRIG_INP19 input is selected * 0b0010101..Reserved * 0b0010110..AOI0_OUT0 input is selected * 0b0010111..AOI0_OUT1 input is selected @@ -462,26 +465,26 @@ typedef struct { #define INPUTMUX_MAIN_CTIMER2CAP_INP_SHIFT (0U) /*! INP - Input number for CTIMER2 * 0b0000000..Reserved - * 0b0000001..CT_INP0 input is selected - * 0b0000010..CT_INP1 input is selected - * 0b0000011..CT_INP2 input is selected - * 0b0000100..CT_INP3 input is selected - * 0b0000101..Reserved - * 0b0000110..CT_INP5 input is selected - * 0b0000111..CT_INP6 input is selected - * 0b0001000..CT_INP7 input is selected - * 0b0001001..CT_INP8 input is selected - * 0b0001010..CT_INP9 input is selected - * 0b0001011..CT_INP10 input is selected - * 0b0001100..CT_INP11 input is selected - * 0b0001101..CT_INP12 input is selected - * 0b0001110..CT_INP13 input is selected - * 0b0001111..CT_INP14 input is selected - * 0b0010000..CT_INP15 input is selected - * 0b0010001..CT_INP16 input is selected - * 0b0010010..CT_INP17 input is selected - * 0b0010011..CT_INP18 input is selected - * 0b0010100..CT_INP19 input is selected + * 0b0000001..TRIG_INP0 input is selected + * 0b0000010..TRIG_INP1 input is selected + * 0b0000011..TRIG_INP2 input is selected + * 0b0000100..TRIG_INP3 input is selected + * 0b0000101..TRIG_INP4 input is selected + * 0b0000110..TRIG_INP5 input is selected + * 0b0000111..TRIG_INP6 input is selected + * 0b0001000..TRIG_INP7 input is selected + * 0b0001001..TRIG_INP8 input is selected + * 0b0001010..TRIG_INP9 input is selected + * 0b0001011..TRIG_INP10 input is selected + * 0b0001100..TRIG_INP11 input is selected + * 0b0001101..TRIG_INP12 input is selected + * 0b0001110..TRIG_INP13 input is selected + * 0b0001111..TRIG_INP14 input is selected + * 0b0010000..TRIG_INP15 input is selected + * 0b0010001..TRIG_INP16 input is selected + * 0b0010010..TRIG_INP17 input is selected + * 0b0010011..TRIG_INP18 input is selected + * 0b0010100..TRIG_INP19 input is selected * 0b0010101..Reserved * 0b0010110..AOI0_OUT0 input is selected * 0b0010111..AOI0_OUT1 input is selected @@ -533,33 +536,33 @@ typedef struct { /* The count of INPUTMUX_MAIN_CTIMER2CAP */ #define INPUTMUX_MAIN_CTIMER2CAP_COUNT (4U) -/*! @name TIMER2TRIG - Trigger register for CTIMER2 inputs */ +/*! @name CTIMER2TRIG - Trigger register for CTIMER2 inputs */ /*! @{ */ -#define INPUTMUX_MAIN_TIMER2TRIG_INP_MASK (0x7FU) -#define INPUTMUX_MAIN_TIMER2TRIG_INP_SHIFT (0U) +#define INPUTMUX_MAIN_CTIMER2TRIG_INP_MASK (0x7FU) +#define INPUTMUX_MAIN_CTIMER2TRIG_INP_SHIFT (0U) /*! INP - Input number for CTIMER2 * 0b0000000..Reserved - * 0b0000001..CT_INP0 input is selected - * 0b0000010..CT_INP1 input is selected - * 0b0000011..CT_INP2 input is selected - * 0b0000100..CT_INP3 input is selected - * 0b0000101..Reserved - * 0b0000110..CT_INP5 input is selected - * 0b0000111..CT_INP6 input is selected - * 0b0001000..CT_INP7 input is selected - * 0b0001001..CT_INP8 input is selected - * 0b0001010..CT_INP9 input is selected - * 0b0001011..CT_INP10 input is selected - * 0b0001100..CT_INP11 input is selected - * 0b0001101..CT_INP12 input is selected - * 0b0001110..CT_INP13 input is selected - * 0b0001111..CT_INP14 input is selected - * 0b0010000..CT_INP15 input is selected - * 0b0010001..CT_INP16 input is selected - * 0b0010010..CT_INP17 input is selected - * 0b0010011..CT_INP18 input is selected - * 0b0010100..CT_INP19 input is selected + * 0b0000001..TRIG_INP0 input is selected + * 0b0000010..TRIG_INP1 input is selected + * 0b0000011..TRIG_INP2 input is selected + * 0b0000100..TRIG_INP3 input is selected + * 0b0000101..TRIG_INP4 input is selected + * 0b0000110..TRIG_INP5 input is selected + * 0b0000111..TRIG_INP6 input is selected + * 0b0001000..TRIG_INP7 input is selected + * 0b0001001..TRIG_INP8 input is selected + * 0b0001010..TRIG_INP9 input is selected + * 0b0001011..TRIG_INP10 input is selected + * 0b0001100..TRIG_INP11 input is selected + * 0b0001101..TRIG_INP12 input is selected + * 0b0001110..TRIG_INP13 input is selected + * 0b0001111..TRIG_INP14 input is selected + * 0b0010000..TRIG_INP15 input is selected + * 0b0010001..TRIG_INP16 input is selected + * 0b0010010..TRIG_INP17 input is selected + * 0b0010011..TRIG_INP18 input is selected + * 0b0010100..TRIG_INP19 input is selected * 0b0010101..Reserved * 0b0010110..AOI0_OUT0 input is selected * 0b0010111..AOI0_OUT1 input is selected @@ -605,7 +608,61 @@ typedef struct { * 0b0111111..Reserved * 0b1000000..Reserved */ -#define INPUTMUX_MAIN_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_MAIN_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_MAIN_TIMER2TRIG_INP_MASK) +#define INPUTMUX_MAIN_CTIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_MAIN_CTIMER2TRIG_INP_SHIFT)) & INPUTMUX_MAIN_CTIMER2TRIG_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_MAIN_FREQMEAS_REF_INP_MASK (0x1FU) +#define INPUTMUX_MAIN_FREQMEAS_REF_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b00000..Reserved + * 0b00001..Reserved + * 0b00010..FRO12M input is selected + * 0b00011..fro_hf_div input is selected + * 0b00100..XTAL32K[2] input is selected + * 0b00101..clk_16k[0] input is selected + * 0b00110..SLOW_CLK input is selected + * 0b00111..FREQME_CLK_IN0 input is selected + * 0b01000..FREQME_CLK_IN1 input is selected input is selected + * 0b01001..AOI0_OUT0 input is selected + * 0b01010..AOI0_OUT1 + * 0b01011..Reserved + * 0b01100..Reserved + * 0b01101..Reserved + * 0b01110..Reserved + * 0b01111..Reserved + * 0b10000..Reserved + */ +#define INPUTMUX_MAIN_FREQMEAS_REF_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_MAIN_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_MAIN_FREQMEAS_REF_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_TAR - Selection for frequency measurement target clock */ +/*! @{ */ + +#define INPUTMUX_MAIN_FREQMEAS_TAR_INP_MASK (0x1FU) +#define INPUTMUX_MAIN_FREQMEAS_TAR_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b00000..Reserved + * 0b00001..Reserved + * 0b00010..FRO12M input is selected + * 0b00011..fro_hf_div input is selected + * 0b00100..XTAL32K[2] input is selected + * 0b00101..clk_16k[0] input is selected + * 0b00110..SLOW_CLK input is selected + * 0b00111..FREQME_CLK_IN0 input is selected + * 0b01000..FREQME_CLK_IN1 input is selected input is selected + * 0b01001..AOI0_OUT0 input is selected + * 0b01010..AOI0_OUT1 + * 0b01011..Reserved + * 0b01100..Reserved + * 0b01101..Reserved + * 0b01110..Reserved + * 0b01111..Reserved + * 0b10000..Reserved + */ +#define INPUTMUX_MAIN_FREQMEAS_TAR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_MAIN_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_MAIN_FREQMEAS_TAR_INP_MASK) /*! @} */ /*! @name CMP0_TRIG - CMP0 Input Connections */ @@ -615,7 +672,7 @@ typedef struct { #define INPUTMUX_MAIN_CMP0_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - CMP0 input trigger * 0b000000..Reserved - * 0b000001..ARM_TXEV input is selected + * 0b000001..CM33 transmit event is selected * 0b000010..AOI0_OUT0 input is selected * 0b000011..AOI0_OUT1 input is selected * 0b000100..AOI0_OUT2 input is selected @@ -656,7 +713,7 @@ typedef struct { #define INPUTMUX_MAIN_ADC0_TRIG_TRIGIN_SHIFT (0U) /*! TRIGIN - ADC0 trigger inputs * 0b000000..Reserved - * 0b000001..ARM_TXEV input is selected + * 0b000001..CM33 transmit event is selected * 0b000010..AOI0_OUT0 input is selected * 0b000011..AOI0_OUT1 input is selected * 0b000100..AOI0_OUT2 input is selected @@ -670,7 +727,7 @@ typedef struct { * 0b001100..CTIMER1_MAT1 input is selected * 0b001101..CTIMER2_MAT0 input is selected * 0b001110..CTIMER2_MAT1 input is selected - * 0b001111..Reserved + * 0b001111..LPTMR0 is selected * 0b010000..Reserved * 0b010001..Reserved * 0b010010..Reserved @@ -686,7 +743,7 @@ typedef struct { * 0b011100..GPIO2 Pin Event Trig 0 input is selected * 0b011101..GPIO3 Pin Event Trig 0 input is selected * 0b011110..Reserved - * 0b011111..WUU + * 0b011111..WUU is selected */ #define INPUTMUX_MAIN_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_MAIN_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_MAIN_ADC0_TRIG_TRIGIN_MASK) /*! @} */ @@ -720,7 +777,7 @@ typedef struct { * 0b010001..CTIMER2_MAT1 input is selected * 0b010010..CTIMER2_MAT2 input is selected * 0b010011..CTIMER2_MAT3 input is selected - * 0b010100..Reserved + * 0b010100..LPTMR0 is selected * 0b010101..Reserved * 0b010110..Reserved * 0b010111..Reserved @@ -765,7 +822,7 @@ typedef struct { #define INPUTMUX_MAIN_EXT_TRIG_INP_SHIFT (0U) /*! INP - EXT trigger input connections * 0b00000..Reserved - * 0b00001..ARM_TXEV input is selected + * 0b00001..CM33 transmit event is selected * 0b00010..AOI0_OUT0 input is selected * 0b00011..AOI0_OUT1 input is selected * 0b00100..AOI0_OUT2 input is selected @@ -773,8 +830,8 @@ typedef struct { * 0b00110..CMP0_OUT input is selected * 0b00111..Reserved * 0b01000..Reserved - * 0b01001..LPUART0 input is selected - * 0b01010..LPUART1 input is selected + * 0b01001..LPUART0 (Transmit data) input is selected + * 0b01010..LPUART1 (Transmit data) input is selected * 0b01011..Reserved */ #define INPUTMUX_MAIN_EXT_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_MAIN_EXT_TRIG_INP_SHIFT)) & INPUTMUX_MAIN_EXT_TRIG_INP_MASK) @@ -790,7 +847,7 @@ typedef struct { #define INPUTMUX_MAIN_LPI2C0_TRIG_INP_SHIFT (0U) /*! INP - LPI2C0 trigger input connections * 0b000000..Reserved - * 0b000001..ARM_TXEV + * 0b000001..CM33 transmit event is selected * 0b000010..AOI0_OUT0 input is selected * 0b000011..AOI0_OUT1 input is selected * 0b000100..AOI0_OUT2 input is selected @@ -816,8 +873,8 @@ typedef struct { * 0b011000..TRIG_IN7 input is selected * 0b011001..Reserved * 0b011010..GPIO1 Pin Event Trig 0 input is selected - * 0b011011..GPIO1 Pin Event Trig 0 input is selected - * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected * 0b011101..Reserved * 0b011110..WUU input is selected */ @@ -831,7 +888,7 @@ typedef struct { #define INPUTMUX_MAIN_LPI2C1_TRIG_INP_SHIFT (0U) /*! INP - LPI2C1 trigger input connections * 0b000000..Reserved - * 0b000001..ARM_TXEV + * 0b000001..CM33 transmit event is selected * 0b000010..AOI0_OUT0 input is selected * 0b000011..AOI0_OUT1 input is selected * 0b000100..AOI0_OUT2 input is selected @@ -872,7 +929,7 @@ typedef struct { #define INPUTMUX_MAIN_LPSPI0_TRIG_INP_SHIFT (0U) /*! INP - LPSPI0 trigger input connections * 0b000000..Reserved - * 0b000001..ARM_TXEV + * 0b000001..CM33 transmit event is selected * 0b000010..AOI0_OUT0 input is selected * 0b000011..AOI0_OUT1 input is selected * 0b000100..AOI0_OUT2 input is selected @@ -913,7 +970,7 @@ typedef struct { #define INPUTMUX_MAIN_LPSPI1_TRIG_INP_SHIFT (0U) /*! INP - LPSPI1 trigger input connections * 0b000000..Reserved - * 0b000001..ARM_TXEV + * 0b000001..CM33 transmit event is selected * 0b000010..AOI0_OUT0 input is selected * 0b000011..AOI0_OUT1 input is selected * 0b000100..AOI0_OUT2 input is selected @@ -954,7 +1011,7 @@ typedef struct { #define INPUTMUX_MAIN_LPUART0_INP_SHIFT (0U) /*! INP - LPUART0 trigger input connections * 0b000000..Reserved - * 0b000001..ARM_TXEV + * 0b000001..CM33 transmit event is selected * 0b000010..AOI0_OUT0 input is selected * 0b000011..AOI0_OUT1 input is selected * 0b000100..AOI0_OUT2 input is selected @@ -999,7 +1056,7 @@ typedef struct { #define INPUTMUX_MAIN_LPUART1_INP_SHIFT (0U) /*! INP - LPUART1 trigger input connections * 0b000000..Reserved - * 0b000001..ARM_TXEV + * 0b000001..CM33 transmit event is selected * 0b000010..AOI0_OUT0 input is selected * 0b000011..AOI0_OUT1 input is selected * 0b000100..AOI0_OUT2 input is selected diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_KPP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_KPP.h index bdec26c24..7c7f8bd69 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_KPP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_KPP.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for KPP @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_KPP.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for KPP * * CMSIS Peripheral Access Layer for KPP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPACMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPACMP.h index 277265f52..ac61a104e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPACMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPACMP.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPACMP @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_LPACMP.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for LPACMP * * CMSIS Peripheral Access Layer for LPACMP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPADC.h index cabb31744..97ebb3ab8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPADC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPADC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPADC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_LPADC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for LPADC * * CMSIS Peripheral Access Layer for LPADC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPCMP.h index ade9cf3ca..8c871fc86 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPCMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPCMP.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPCMP @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_LPCMP.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for LPCMP * * CMSIS Peripheral Access Layer for LPCMP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPI2C.h index 4d1d13dff..34d8b9cb5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPI2C.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_LPI2C.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for LPI2C * * CMSIS Peripheral Access Layer for LPI2C diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPSPI.h index 07dde6bfb..33dc42790 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPSPI.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_LPSPI.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for LPSPI * * CMSIS Peripheral Access Layer for LPSPI diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPTMR.h index 7783c3b61..767f15095 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPTMR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPTMR.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPTMR @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_LPTMR.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for LPTMR * * CMSIS Peripheral Access Layer for LPTMR diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPUART.h index bb818194e..8e2e22ed2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_LPUART.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_LPUART.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for LPUART * * CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_MRCC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_MRCC.h index 196d5654d..48a0f8117 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_MRCC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_MRCC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for MRCC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_MRCC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MRCC * * CMSIS Peripheral Access Layer for MRCC @@ -101,11 +101,11 @@ /** MRCC - Register Layout Typedef */ typedef struct { - __IO uint32_t GLB_RST0; /**< Peripheral Reset Control 0, offset: 0x0 */ + __IO uint32_t GLB_RST0; /**< Global Reset Control 0, offset: 0x0 */ __O uint32_t GLB_RSTSET0; /**< Peripheral Reset Control Set 0, offset: 0x4 */ __O uint32_t GLB_RSTCLR0; /**< Peripheral Reset Control Clear 0, offset: 0x8 */ uint8_t RESERVED_0[4]; - __IO uint32_t GLB_RST1; /**< Peripheral Reset Control 1, offset: 0x10 */ + __IO uint32_t GLB_RST1; /**< Peripheral Resets Control 1, offset: 0x10 */ __O uint32_t GLB_RSTSET1; /**< Peripheral Reset Control Set 1, offset: 0x14 */ __O uint32_t GLB_RSTCLR1; /**< Peripheral Reset Control Clear 1, offset: 0x18 */ uint8_t RESERVED_1[36]; @@ -121,7 +121,7 @@ typedef struct { __IO uint32_t GLB_ACC1; /**< Control Automatic Clock Gating 1, offset: 0x84 */ uint8_t RESERVED_4[8]; __IO uint32_t GLB_PR0; /**< Peripheral Enable Configuration 0, offset: 0x90 */ - __IO uint32_t GLB_PR1; /**< Peripheral Enable Configuration 1, offset: 0x94 */ + __IO uint32_t GLB_PR1; /**< Global Enable Configuration 1, offset: 0x94 */ uint8_t RESERVED_5[8]; __IO uint32_t CTIMERGRP0CLKSEL; /**< CTIMER_Group_0 clock selection control, offset: 0xA0 */ __IO uint32_t CTIMERGRP0CLKDIV; /**< CTIMER_Group_0 clock divider control, offset: 0xA4 */ @@ -134,7 +134,7 @@ typedef struct { __IO uint32_t ADC0CLKDIV; /**< ADC0 clock divider control, offset: 0xC4 */ uint8_t RESERVED_7[4]; __IO uint32_t CMP0FUNCCLKDIV; /**< CMP0_FUNC clock divider control, offset: 0xCC */ - __IO uint32_t CMP0RRCLKSEL; /**< CMP0 clock selection control, offset: 0xD0 */ + __IO uint32_t CMP0RRCLKSEL; /**< CMP0_RR clock selection control, offset: 0xD0 */ __IO uint32_t CMP0RRCLKDIV; /**< CMP0_RR clock divider control, offset: 0xD4 */ __IO uint32_t DBGTRACECLKSEL; /**< DBG_TRACE clock selection control, offset: 0xD8 */ __IO uint32_t DBGTRACECLKDIV; /**< DBG_TRACE clock divider control, offset: 0xDC */ @@ -162,12 +162,12 @@ typedef struct { * @{ */ -/*! @name GLB_RST0 - Peripheral Reset Control 0 */ +/*! @name GLB_RST0 - Global Reset Control 0 */ /*! @{ */ #define MRCC_GLB_RST0_INPUTMUX0_MASK (0x1U) #define MRCC_GLB_RST0_INPUTMUX0_SHIFT (0U) -/*! INPUTMUX0 - Write to INPUTMUX0 +/*! INPUTMUX0 - Resets INPUTMUX0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -175,7 +175,7 @@ typedef struct { #define MRCC_GLB_RST0_CTIMER0_MASK (0x2U) #define MRCC_GLB_RST0_CTIMER0_SHIFT (1U) -/*! CTIMER0 - Write to CTIMER0 +/*! CTIMER0 - Resets CTIMER0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -183,7 +183,7 @@ typedef struct { #define MRCC_GLB_RST0_CTIMER1_MASK (0x4U) #define MRCC_GLB_RST0_CTIMER1_SHIFT (2U) -/*! CTIMER1 - Write to CTIMER1 +/*! CTIMER1 - Resets CTIMER1 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -191,7 +191,7 @@ typedef struct { #define MRCC_GLB_RST0_CTIMER2_MASK (0x8U) #define MRCC_GLB_RST0_CTIMER2_SHIFT (3U) -/*! CTIMER2 - Write to CTIMER2 +/*! CTIMER2 - Resets CTIMER2 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -199,7 +199,7 @@ typedef struct { #define MRCC_GLB_RST0_FREQME_MASK (0x10U) #define MRCC_GLB_RST0_FREQME_SHIFT (4U) -/*! FREQME - Write to FREQME +/*! FREQME - Resets FREQME * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -207,7 +207,7 @@ typedef struct { #define MRCC_GLB_RST0_UTICK0_MASK (0x20U) #define MRCC_GLB_RST0_UTICK0_SHIFT (5U) -/*! UTICK0 - Write to UTICK0 +/*! UTICK0 - Resets UTICK0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -215,7 +215,7 @@ typedef struct { #define MRCC_GLB_RST0_DMA0_MASK (0x80U) #define MRCC_GLB_RST0_DMA0_SHIFT (7U) -/*! DMA0 - Write to DMA0 +/*! DMA0 - Resets DMA0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -223,7 +223,7 @@ typedef struct { #define MRCC_GLB_RST0_AOI0_MASK (0x100U) #define MRCC_GLB_RST0_AOI0_SHIFT (8U) -/*! AOI0 - Write to AOI0 +/*! AOI0 - Resets AOI0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -231,7 +231,7 @@ typedef struct { #define MRCC_GLB_RST0_CRC_MASK (0x200U) #define MRCC_GLB_RST0_CRC_SHIFT (9U) -/*! CRC - Write to CRC +/*! CRC - Resets CRC * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -239,7 +239,7 @@ typedef struct { #define MRCC_GLB_RST0_ERM0_MASK (0x400U) #define MRCC_GLB_RST0_ERM0_SHIFT (10U) -/*! ERM0 - Write to ERM0 +/*! ERM0 - Resets ERM0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -247,7 +247,7 @@ typedef struct { #define MRCC_GLB_RST0_LPI2C0_MASK (0x4000U) #define MRCC_GLB_RST0_LPI2C0_SHIFT (14U) -/*! LPI2C0 - Write to LPI2C0 +/*! LPI2C0 - Resets LPI2C0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -255,7 +255,7 @@ typedef struct { #define MRCC_GLB_RST0_LPI2C1_MASK (0x8000U) #define MRCC_GLB_RST0_LPI2C1_SHIFT (15U) -/*! LPI2C1 - Write to LPI2C1 +/*! LPI2C1 - Resets LPI2C1 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -263,7 +263,7 @@ typedef struct { #define MRCC_GLB_RST0_LPSPI0_MASK (0x10000U) #define MRCC_GLB_RST0_LPSPI0_SHIFT (16U) -/*! LPSPI0 - Write to LPSPI0 +/*! LPSPI0 - Resets LPSPI0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -271,7 +271,7 @@ typedef struct { #define MRCC_GLB_RST0_LPSPI1_MASK (0x20000U) #define MRCC_GLB_RST0_LPSPI1_SHIFT (17U) -/*! LPSPI1 - Write to LPSPI1 +/*! LPSPI1 - Resets LPSPI1 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -279,7 +279,7 @@ typedef struct { #define MRCC_GLB_RST0_LPUART0_MASK (0x40000U) #define MRCC_GLB_RST0_LPUART0_SHIFT (18U) -/*! LPUART0 - Write to LPUART0 +/*! LPUART0 - Resets LPUART0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -287,23 +287,15 @@ typedef struct { #define MRCC_GLB_RST0_ADC0_MASK (0x80000U) #define MRCC_GLB_RST0_ADC0_SHIFT (19U) -/*! ADC0 - Write to ADC0 +/*! ADC0 - Resets ADC0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ #define MRCC_GLB_RST0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_RST0_ADC0_SHIFT)) & MRCC_GLB_RST0_ADC0_MASK) -#define MRCC_GLB_RST0_ATX0_MASK (0x100000U) -#define MRCC_GLB_RST0_ATX0_SHIFT (20U) -/*! ATX0 - Write to ATX0 - * 0b0..Peripheral is held in reset - * 0b1..Peripheral is released from reset - */ -#define MRCC_GLB_RST0_ATX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_RST0_ATX0_SHIFT)) & MRCC_GLB_RST0_ATX0_MASK) - #define MRCC_GLB_RST0_CMP0_MASK (0x200000U) #define MRCC_GLB_RST0_CMP0_SHIFT (21U) -/*! CMP0 - write to CMP0 +/*! CMP0 - Resets CMP0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -311,7 +303,7 @@ typedef struct { #define MRCC_GLB_RST0_DMA1_MASK (0x400000U) #define MRCC_GLB_RST0_DMA1_SHIFT (22U) -/*! DMA1 - write to DMA1 +/*! DMA1 - Resets DMA1 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -319,7 +311,7 @@ typedef struct { #define MRCC_GLB_RST0_GPIO1_MASK (0x1000000U) #define MRCC_GLB_RST0_GPIO1_SHIFT (24U) -/*! GPIO1 - Write to GPIO1 +/*! GPIO1 - Resets GPIO1 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -327,7 +319,7 @@ typedef struct { #define MRCC_GLB_RST0_GPIO2_MASK (0x2000000U) #define MRCC_GLB_RST0_GPIO2_SHIFT (25U) -/*! GPIO2 - Write to GPIO2 +/*! GPIO2 - Resets GPIO2 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -335,7 +327,7 @@ typedef struct { #define MRCC_GLB_RST0_GPIO3_MASK (0x4000000U) #define MRCC_GLB_RST0_GPIO3_SHIFT (26U) -/*! GPIO3 - Write to GPIO3 +/*! GPIO3 - Resets GPIO3 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -343,7 +335,7 @@ typedef struct { #define MRCC_GLB_RST0_LPUART1_MASK (0x8000000U) #define MRCC_GLB_RST0_LPUART1_SHIFT (27U) -/*! LPUART1 - Write to LPUART1 +/*! LPUART1 - Resets LPUART1 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -351,7 +343,7 @@ typedef struct { #define MRCC_GLB_RST0_OSTIMER0_MASK (0x20000000U) #define MRCC_GLB_RST0_OSTIMER0_SHIFT (29U) -/*! OSTIMER0 - Write to OSTIMER0 +/*! OSTIMER0 - Resets OSTIMER0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -376,12 +368,12 @@ typedef struct { #define MRCC_GLB_RSTCLR0_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_RSTCLR0_DATA_SHIFT)) & MRCC_GLB_RSTCLR0_DATA_MASK) /*! @} */ -/*! @name GLB_RST1 - Peripheral Reset Control 1 */ +/*! @name GLB_RST1 - Peripheral Resets Control 1 */ /*! @{ */ #define MRCC_GLB_RST1_PKC0_MASK (0x1U) #define MRCC_GLB_RST1_PKC0_SHIFT (0U) -/*! PKC0 - write to PKC0 +/*! PKC0 - Resets PKC0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -389,7 +381,7 @@ typedef struct { #define MRCC_GLB_RST1_PORT1_MASK (0x2U) #define MRCC_GLB_RST1_PORT1_SHIFT (1U) -/*! PORT1 - Write to PORT1 +/*! PORT1 - Resets PORT1 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -397,7 +389,7 @@ typedef struct { #define MRCC_GLB_RST1_PORT2_MASK (0x4U) #define MRCC_GLB_RST1_PORT2_SHIFT (2U) -/*! PORT2 - Write to PORT2 +/*! PORT2 - Resets PORT2 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -405,7 +397,7 @@ typedef struct { #define MRCC_GLB_RST1_PORT3_MASK (0x8U) #define MRCC_GLB_RST1_PORT3_SHIFT (3U) -/*! PORT3 - Write to PORT3 +/*! PORT3 - Resets PORT3 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -413,7 +405,7 @@ typedef struct { #define MRCC_GLB_RST1_SGLCD0_MASK (0x40U) #define MRCC_GLB_RST1_SGLCD0_SHIFT (6U) -/*! SGLCD0 - write to SGLCD0 +/*! SGLCD0 - Resets SGLCD0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -421,7 +413,7 @@ typedef struct { #define MRCC_GLB_RST1_TRNG0_MASK (0x100U) #define MRCC_GLB_RST1_TRNG0_SHIFT (8U) -/*! TRNG0 - write to TRNG0 +/*! TRNG0 - Resets TRNG0 * 0b0..Peripheral is held in reset * 0b1..Peripheral is released from reset */ @@ -451,7 +443,7 @@ typedef struct { #define MRCC_GLB_CC0_INPUTMUX0_MASK (0x1U) #define MRCC_GLB_CC0_INPUTMUX0_SHIFT (0U) -/*! INPUTMUX0 - Write to INPUTMUX0 +/*! INPUTMUX0 - Clock gate control INPUTMUX0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -459,7 +451,7 @@ typedef struct { #define MRCC_GLB_CC0_CTIMER0_MASK (0x2U) #define MRCC_GLB_CC0_CTIMER0_SHIFT (1U) -/*! CTIMER0 - Write to CTIMER0 +/*! CTIMER0 - Clock gate control CTIMER0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -467,7 +459,7 @@ typedef struct { #define MRCC_GLB_CC0_CTIMER1_MASK (0x4U) #define MRCC_GLB_CC0_CTIMER1_SHIFT (2U) -/*! CTIMER1 - Write to CTIMER1 +/*! CTIMER1 - Clock gate control CTIMER1 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -475,7 +467,7 @@ typedef struct { #define MRCC_GLB_CC0_CTIMER2_MASK (0x8U) #define MRCC_GLB_CC0_CTIMER2_SHIFT (3U) -/*! CTIMER2 - Write to CTIMER2 +/*! CTIMER2 - Clock gate control CTIMER2 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -483,7 +475,7 @@ typedef struct { #define MRCC_GLB_CC0_FREQME_MASK (0x10U) #define MRCC_GLB_CC0_FREQME_SHIFT (4U) -/*! FREQME - Write to FREQME +/*! FREQME - Clock gate control FREQME * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -491,7 +483,7 @@ typedef struct { #define MRCC_GLB_CC0_UTICK0_MASK (0x20U) #define MRCC_GLB_CC0_UTICK0_SHIFT (5U) -/*! UTICK0 - Write to UTICK0 +/*! UTICK0 - Clock gate control UTICK0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -499,7 +491,7 @@ typedef struct { #define MRCC_GLB_CC0_WWDT0_MASK (0x40U) #define MRCC_GLB_CC0_WWDT0_SHIFT (6U) -/*! WWDT0 - Write to WWDT0 +/*! WWDT0 - Clock gate control WWDT0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -507,7 +499,7 @@ typedef struct { #define MRCC_GLB_CC0_DMA0_MASK (0x80U) #define MRCC_GLB_CC0_DMA0_SHIFT (7U) -/*! DMA0 - Write to DMA0 +/*! DMA0 - Clock gate control DMA0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -515,7 +507,7 @@ typedef struct { #define MRCC_GLB_CC0_AOI0_MASK (0x100U) #define MRCC_GLB_CC0_AOI0_SHIFT (8U) -/*! AOI0 - Write to AOI0 +/*! AOI0 - Clock gate control AOI0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -523,7 +515,7 @@ typedef struct { #define MRCC_GLB_CC0_CRC_MASK (0x200U) #define MRCC_GLB_CC0_CRC_SHIFT (9U) -/*! CRC - Write to CRC +/*! CRC - Clock gate control CRC * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -531,7 +523,7 @@ typedef struct { #define MRCC_GLB_CC0_ERM0_MASK (0x400U) #define MRCC_GLB_CC0_ERM0_SHIFT (10U) -/*! ERM0 - Write to ERM0 +/*! ERM0 - Clock gate control ERM0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -539,7 +531,7 @@ typedef struct { #define MRCC_GLB_CC0_LPI2C0_MASK (0x4000U) #define MRCC_GLB_CC0_LPI2C0_SHIFT (14U) -/*! LPI2C0 - Write to LPI2C0 +/*! LPI2C0 - Clock gate control LPI2C0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -547,7 +539,7 @@ typedef struct { #define MRCC_GLB_CC0_LPI2C1_MASK (0x8000U) #define MRCC_GLB_CC0_LPI2C1_SHIFT (15U) -/*! LPI2C1 - Write to LPI2C1 +/*! LPI2C1 - Clock gate control LPI2C1 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -555,7 +547,7 @@ typedef struct { #define MRCC_GLB_CC0_LPSPI0_MASK (0x10000U) #define MRCC_GLB_CC0_LPSPI0_SHIFT (16U) -/*! LPSPI0 - Write to LPSPI0 +/*! LPSPI0 - Clock gate control LPSPI0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -563,7 +555,7 @@ typedef struct { #define MRCC_GLB_CC0_LPSPI1_MASK (0x20000U) #define MRCC_GLB_CC0_LPSPI1_SHIFT (17U) -/*! LPSPI1 - Write to LPSPI1 +/*! LPSPI1 - Clock gate control LPSPI1 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -571,7 +563,7 @@ typedef struct { #define MRCC_GLB_CC0_LPUART0_MASK (0x40000U) #define MRCC_GLB_CC0_LPUART0_SHIFT (18U) -/*! LPUART0 - Write to LPUART0 +/*! LPUART0 - Clock gate control LPUART0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -579,23 +571,15 @@ typedef struct { #define MRCC_GLB_CC0_ADC0_MASK (0x80000U) #define MRCC_GLB_CC0_ADC0_SHIFT (19U) -/*! ADC0 - Write to ADC0 +/*! ADC0 - Clock gate control ADC0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ #define MRCC_GLB_CC0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_CC0_ADC0_SHIFT)) & MRCC_GLB_CC0_ADC0_MASK) -#define MRCC_GLB_CC0_ATX0_MASK (0x100000U) -#define MRCC_GLB_CC0_ATX0_SHIFT (20U) -/*! ATX0 - Write to ATX0 - * 0b0..Peripheral clock is disabled - * 0b1..Peripheral clock is enabled - */ -#define MRCC_GLB_CC0_ATX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_CC0_ATX0_SHIFT)) & MRCC_GLB_CC0_ATX0_MASK) - #define MRCC_GLB_CC0_CMP0_MASK (0x200000U) #define MRCC_GLB_CC0_CMP0_SHIFT (21U) -/*! CMP0 - Write to CMP0 +/*! CMP0 - Clock gate control CMP0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -603,7 +587,7 @@ typedef struct { #define MRCC_GLB_CC0_DMA1_MASK (0x400000U) #define MRCC_GLB_CC0_DMA1_SHIFT (22U) -/*! DMA1 - write to DMA1 +/*! DMA1 - Clock gate control DMA1 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -611,7 +595,7 @@ typedef struct { #define MRCC_GLB_CC0_SRAMA_MASK (0x800000U) #define MRCC_GLB_CC0_SRAMA_SHIFT (23U) -/*! SRAMA - Write to SRAM A0/A1 +/*! SRAMA - Clock gate control SRAM A0/A1 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -619,7 +603,7 @@ typedef struct { #define MRCC_GLB_CC0_GPIO1_MASK (0x1000000U) #define MRCC_GLB_CC0_GPIO1_SHIFT (24U) -/*! GPIO1 - Write to GPIO1 +/*! GPIO1 - Clock gate control GPIO1 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -627,7 +611,7 @@ typedef struct { #define MRCC_GLB_CC0_GPIO2_MASK (0x2000000U) #define MRCC_GLB_CC0_GPIO2_SHIFT (25U) -/*! GPIO2 - Write to GPIO2 +/*! GPIO2 - Clock gate control GPIO2 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -635,7 +619,7 @@ typedef struct { #define MRCC_GLB_CC0_GPIO3_MASK (0x4000000U) #define MRCC_GLB_CC0_GPIO3_SHIFT (26U) -/*! GPIO3 - Write to GPIO3 +/*! GPIO3 - Clock gate control GPIO3 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -643,7 +627,7 @@ typedef struct { #define MRCC_GLB_CC0_LPUART1_MASK (0x8000000U) #define MRCC_GLB_CC0_LPUART1_SHIFT (27U) -/*! LPUART1 - Write to LPUART1 +/*! LPUART1 - Clock gate control LPUART1 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -651,7 +635,7 @@ typedef struct { #define MRCC_GLB_CC0_MTR_MASK (0x10000000U) #define MRCC_GLB_CC0_MTR_SHIFT (28U) -/*! MTR - Write to MTR +/*! MTR - Clock gate control MTR * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -659,7 +643,7 @@ typedef struct { #define MRCC_GLB_CC0_OSTIMER0_MASK (0x20000000U) #define MRCC_GLB_CC0_OSTIMER0_SHIFT (29U) -/*! OSTIMER0 - Write to OSTIMER0 +/*! OSTIMER0 - Clock gate control OSTIMER0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -667,7 +651,7 @@ typedef struct { #define MRCC_GLB_CC0_PGRP0_MASK (0x40000000U) #define MRCC_GLB_CC0_PGRP0_SHIFT (30U) -/*! PGRP0 - Write to PERIPH_GROUP_0 +/*! PGRP0 - Clock gate control PERIPH_GROUP_0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -675,7 +659,7 @@ typedef struct { #define MRCC_GLB_CC0_PGRP1_MASK (0x80000000U) #define MRCC_GLB_CC0_PGRP1_SHIFT (31U) -/*! PGRP1 - Write to PERIPH_GROUP_1 +/*! PGRP1 - Clock gate control PERIPH_GROUP_1 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -705,7 +689,7 @@ typedef struct { #define MRCC_GLB_CC1_PKC0_MASK (0x1U) #define MRCC_GLB_CC1_PKC0_SHIFT (0U) -/*! PKC0 - Write to PKC0 +/*! PKC0 - Clock gate control PKC0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -713,7 +697,7 @@ typedef struct { #define MRCC_GLB_CC1_PORT1_MASK (0x2U) #define MRCC_GLB_CC1_PORT1_SHIFT (1U) -/*! PORT1 - Write to PORT1 +/*! PORT1 - Clock gate control PORT1 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -721,7 +705,7 @@ typedef struct { #define MRCC_GLB_CC1_PORT2_MASK (0x4U) #define MRCC_GLB_CC1_PORT2_SHIFT (2U) -/*! PORT2 - Write to PORT2 +/*! PORT2 - Clock gate control PORT2 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -729,7 +713,7 @@ typedef struct { #define MRCC_GLB_CC1_PORT3_MASK (0x8U) #define MRCC_GLB_CC1_PORT3_SHIFT (3U) -/*! PORT3 - Write to PORT3 +/*! PORT3 - Clock gate control PORT3 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -737,7 +721,7 @@ typedef struct { #define MRCC_GLB_CC1_ROMCP_MASK (0x10U) #define MRCC_GLB_CC1_ROMCP_SHIFT (4U) -/*! ROMCP - Write to ROMCP +/*! ROMCP - Clock gate control ROMCP * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -745,7 +729,7 @@ typedef struct { #define MRCC_GLB_CC1_SGI0_MASK (0x20U) #define MRCC_GLB_CC1_SGI0_SHIFT (5U) -/*! SGI0 - Write to SGI0 +/*! SGI0 - Clock gate control SGI0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -753,7 +737,7 @@ typedef struct { #define MRCC_GLB_CC1_SGLCD0_MASK (0x40U) #define MRCC_GLB_CC1_SGLCD0_SHIFT (6U) -/*! SGLCD0 - write to SGLCD0 +/*! SGLCD0 - Clock gate control SGLCD0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -761,7 +745,7 @@ typedef struct { #define MRCC_GLB_CC1_TCU_MASK (0x80U) #define MRCC_GLB_CC1_TCU_SHIFT (7U) -/*! TCU - Write to TCU +/*! TCU - Clock gate control TCU * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ @@ -769,19 +753,11 @@ typedef struct { #define MRCC_GLB_CC1_TRNG0_MASK (0x100U) #define MRCC_GLB_CC1_TRNG0_SHIFT (8U) -/*! TRNG0 - Write to TRNG0 +/*! TRNG0 - Clock gate control TRNG0 * 0b0..Peripheral clock is disabled * 0b1..Peripheral clock is enabled */ #define MRCC_GLB_CC1_TRNG0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_CC1_TRNG0_SHIFT)) & MRCC_GLB_CC1_TRNG0_MASK) - -#define MRCC_GLB_CC1_UDF0_MASK (0x200U) -#define MRCC_GLB_CC1_UDF0_SHIFT (9U) -/*! UDF0 - Write to UDF0 - * 0b0..Peripheral clock is disabled - * 0b1..Peripheral clock is enabled - */ -#define MRCC_GLB_CC1_UDF0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_CC1_UDF0_SHIFT)) & MRCC_GLB_CC1_UDF0_MASK) /*! @} */ /*! @name GLB_CCSET1 - AHB Clock Control Set 1 */ @@ -807,7 +783,7 @@ typedef struct { #define MRCC_GLB_ACC0_INPUTMUX0_MASK (0x1U) #define MRCC_GLB_ACC0_INPUTMUX0_SHIFT (0U) -/*! INPUTMUX0 - Write to INPUTMUX0 +/*! INPUTMUX0 - Automatic clock control INPUTMUX0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -815,7 +791,7 @@ typedef struct { #define MRCC_GLB_ACC0_CTIMER0_MASK (0x2U) #define MRCC_GLB_ACC0_CTIMER0_SHIFT (1U) -/*! CTIMER0 - Write to CTIMER0 +/*! CTIMER0 - Automatic clock control CTIMER0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -823,7 +799,7 @@ typedef struct { #define MRCC_GLB_ACC0_CTIMER1_MASK (0x4U) #define MRCC_GLB_ACC0_CTIMER1_SHIFT (2U) -/*! CTIMER1 - Write to CTIMER1 +/*! CTIMER1 - Automatic clock control CTIMER1 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -831,7 +807,7 @@ typedef struct { #define MRCC_GLB_ACC0_CTIMER2_MASK (0x8U) #define MRCC_GLB_ACC0_CTIMER2_SHIFT (3U) -/*! CTIMER2 - Write to CTIMER2 +/*! CTIMER2 - Automatic clock control CTIMER2 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -839,7 +815,7 @@ typedef struct { #define MRCC_GLB_ACC0_FREQME_MASK (0x10U) #define MRCC_GLB_ACC0_FREQME_SHIFT (4U) -/*! FREQME - Write to FREQME +/*! FREQME - Automatic clock control FREQME * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -847,7 +823,7 @@ typedef struct { #define MRCC_GLB_ACC0_UTICK0_MASK (0x20U) #define MRCC_GLB_ACC0_UTICK0_SHIFT (5U) -/*! UTICK0 - Write to UTICK0 +/*! UTICK0 - Automatic clock control UTICK0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -855,7 +831,7 @@ typedef struct { #define MRCC_GLB_ACC0_WWDT0_MASK (0x40U) #define MRCC_GLB_ACC0_WWDT0_SHIFT (6U) -/*! WWDT0 - Write to WWDT0 +/*! WWDT0 - Automatic clock control WWDT0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -863,7 +839,7 @@ typedef struct { #define MRCC_GLB_ACC0_DMA0_MASK (0x80U) #define MRCC_GLB_ACC0_DMA0_SHIFT (7U) -/*! DMA0 - Write to DMA0 +/*! DMA0 - Automatic clock control DMA0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -871,7 +847,7 @@ typedef struct { #define MRCC_GLB_ACC0_AOI0_MASK (0x100U) #define MRCC_GLB_ACC0_AOI0_SHIFT (8U) -/*! AOI0 - Write to AOI0 +/*! AOI0 - Automatic clock control AOI0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -879,7 +855,7 @@ typedef struct { #define MRCC_GLB_ACC0_CRC_MASK (0x200U) #define MRCC_GLB_ACC0_CRC_SHIFT (9U) -/*! CRC - Write to CRC +/*! CRC - Automatic clock control CRC * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -887,7 +863,7 @@ typedef struct { #define MRCC_GLB_ACC0_ERM0_MASK (0x400U) #define MRCC_GLB_ACC0_ERM0_SHIFT (10U) -/*! ERM0 - Write to ERM0 +/*! ERM0 - Automatic clock control ERM0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -895,7 +871,7 @@ typedef struct { #define MRCC_GLB_ACC0_NVM_MBC_MASK (0x800U) #define MRCC_GLB_ACC0_NVM_MBC_SHIFT (11U) -/*! NVM_MBC - Write to NVM_MBC +/*! NVM_MBC - Automatic clock control NVM_MBC * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -903,7 +879,7 @@ typedef struct { #define MRCC_GLB_ACC0_NVM_NPX_CTL_MASK (0x1000U) #define MRCC_GLB_ACC0_NVM_NPX_CTL_SHIFT (12U) -/*! NVM_NPX_CTL - Write to NVM_NPX_CTL +/*! NVM_NPX_CTL - Automatic clock control NVM_NPX_CTL * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -911,7 +887,7 @@ typedef struct { #define MRCC_GLB_ACC0_FMU0_MASK (0x2000U) #define MRCC_GLB_ACC0_FMU0_SHIFT (13U) -/*! FMU0 - Write to FMU0 +/*! FMU0 - Automatic clock control FMU0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -919,7 +895,7 @@ typedef struct { #define MRCC_GLB_ACC0_LPI2C0_MASK (0x4000U) #define MRCC_GLB_ACC0_LPI2C0_SHIFT (14U) -/*! LPI2C0 - Write to LPI2C0 +/*! LPI2C0 - Automatic clock control LPI2C0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -927,7 +903,7 @@ typedef struct { #define MRCC_GLB_ACC0_LPI2C1_MASK (0x8000U) #define MRCC_GLB_ACC0_LPI2C1_SHIFT (15U) -/*! LPI2C1 - Write to LPI2C1 +/*! LPI2C1 - Automatic clock control LPI2C1 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -935,7 +911,7 @@ typedef struct { #define MRCC_GLB_ACC0_LPSPI0_MASK (0x10000U) #define MRCC_GLB_ACC0_LPSPI0_SHIFT (16U) -/*! LPSPI0 - Write to LPSPI0 +/*! LPSPI0 - Automatic clock control LPSPI0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -943,7 +919,7 @@ typedef struct { #define MRCC_GLB_ACC0_LPSPI1_MASK (0x20000U) #define MRCC_GLB_ACC0_LPSPI1_SHIFT (17U) -/*! LPSPI1 - Write to LPSPI1 +/*! LPSPI1 - Automatic clock control LPSPI1 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -951,7 +927,7 @@ typedef struct { #define MRCC_GLB_ACC0_LPUART0_MASK (0x40000U) #define MRCC_GLB_ACC0_LPUART0_SHIFT (18U) -/*! LPUART0 - Write to LPUART0 +/*! LPUART0 - Automatic clock control LPUART0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -959,23 +935,15 @@ typedef struct { #define MRCC_GLB_ACC0_ADC0_MASK (0x80000U) #define MRCC_GLB_ACC0_ADC0_SHIFT (19U) -/*! ADC0 - Write to ADC0 +/*! ADC0 - Automatic clock control ADC0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ #define MRCC_GLB_ACC0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_ACC0_ADC0_SHIFT)) & MRCC_GLB_ACC0_ADC0_MASK) -#define MRCC_GLB_ACC0_ATX0_MASK (0x100000U) -#define MRCC_GLB_ACC0_ATX0_SHIFT (20U) -/*! ATX0 - Write to ATX0 - * 0b0..Automatic clock gating is disabled - * 0b1..Automatic clock gating is enabled - */ -#define MRCC_GLB_ACC0_ATX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_ACC0_ATX0_SHIFT)) & MRCC_GLB_ACC0_ATX0_MASK) - #define MRCC_GLB_ACC0_CMP0_MASK (0x200000U) #define MRCC_GLB_ACC0_CMP0_SHIFT (21U) -/*! CMP0 - Write to CMP0 +/*! CMP0 - Automatic clock control CMP0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -983,7 +951,7 @@ typedef struct { #define MRCC_GLB_ACC0_DMA1_MASK (0x400000U) #define MRCC_GLB_ACC0_DMA1_SHIFT (22U) -/*! DMA1 - write to DMA1 +/*! DMA1 - Automatic clock control DMA1 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -991,7 +959,7 @@ typedef struct { #define MRCC_GLB_ACC0_SRAMA_MASK (0x800000U) #define MRCC_GLB_ACC0_SRAMA_SHIFT (23U) -/*! SRAMA - Write to SRAM A0/A1 +/*! SRAMA - Automatic clock control SRAM A0/A1 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -999,7 +967,7 @@ typedef struct { #define MRCC_GLB_ACC0_GPIO1_MASK (0x1000000U) #define MRCC_GLB_ACC0_GPIO1_SHIFT (24U) -/*! GPIO1 - Write to GPIO1 +/*! GPIO1 - Automatic clock control GPIO1 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1007,7 +975,7 @@ typedef struct { #define MRCC_GLB_ACC0_GPIO2_MASK (0x2000000U) #define MRCC_GLB_ACC0_GPIO2_SHIFT (25U) -/*! GPIO2 - Write to GPIO2 +/*! GPIO2 - Automatic clock control GPIO2 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1015,7 +983,7 @@ typedef struct { #define MRCC_GLB_ACC0_GPIO3_MASK (0x4000000U) #define MRCC_GLB_ACC0_GPIO3_SHIFT (26U) -/*! GPIO3 - Write to GPIO3 +/*! GPIO3 - Automatic clock control GPIO3 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1023,7 +991,7 @@ typedef struct { #define MRCC_GLB_ACC0_LPUART1_MASK (0x8000000U) #define MRCC_GLB_ACC0_LPUART1_SHIFT (27U) -/*! LPUART1 - Write to LPUART1 +/*! LPUART1 - Automatic clock control LPUART1 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1031,7 +999,7 @@ typedef struct { #define MRCC_GLB_ACC0_OSTIMER0_MASK (0x20000000U) #define MRCC_GLB_ACC0_OSTIMER0_SHIFT (29U) -/*! OSTIMER0 - Write to OSTIMER0 +/*! OSTIMER0 - Automatic clock control OSTIMER0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1039,7 +1007,7 @@ typedef struct { #define MRCC_GLB_ACC0_PGRP0_MASK (0x40000000U) #define MRCC_GLB_ACC0_PGRP0_SHIFT (30U) -/*! PGRP0 - Write to PERIPH_GROUP_0 +/*! PGRP0 - Automatic clock control PERIPH_GROUP_0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1047,7 +1015,7 @@ typedef struct { #define MRCC_GLB_ACC0_PGRP1_MASK (0x80000000U) #define MRCC_GLB_ACC0_PGRP1_SHIFT (31U) -/*! PGRP1 - Write to PERIPH_GROUP_1 +/*! PGRP1 - Automatic clock control PERIPH_GROUP_1 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1059,7 +1027,7 @@ typedef struct { #define MRCC_GLB_ACC1_PKC0_MASK (0x1U) #define MRCC_GLB_ACC1_PKC0_SHIFT (0U) -/*! PKC0 - write to PKC0 +/*! PKC0 - Automatic clock control PKC0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1067,7 +1035,7 @@ typedef struct { #define MRCC_GLB_ACC1_PORT1_MASK (0x2U) #define MRCC_GLB_ACC1_PORT1_SHIFT (1U) -/*! PORT1 - write to PORT1 +/*! PORT1 - Automatic clock control PORT1 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1075,7 +1043,7 @@ typedef struct { #define MRCC_GLB_ACC1_PORT2_MASK (0x4U) #define MRCC_GLB_ACC1_PORT2_SHIFT (2U) -/*! PORT2 - Write to PORT2 +/*! PORT2 - Automatic clock control PORT2 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1083,7 +1051,7 @@ typedef struct { #define MRCC_GLB_ACC1_PORT3_MASK (0x8U) #define MRCC_GLB_ACC1_PORT3_SHIFT (3U) -/*! PORT3 - Write to PORT3 +/*! PORT3 - Automatic clock control PORT3 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1091,7 +1059,7 @@ typedef struct { #define MRCC_GLB_ACC1_ROMCP_MASK (0x10U) #define MRCC_GLB_ACC1_ROMCP_SHIFT (4U) -/*! ROMCP - Write to ROMCP +/*! ROMCP - Automatic clock control ROMCP * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1099,7 +1067,7 @@ typedef struct { #define MRCC_GLB_ACC1_SGI0_MASK (0x20U) #define MRCC_GLB_ACC1_SGI0_SHIFT (5U) -/*! SGI0 - Write to SGI0 +/*! SGI0 - Automatic clock control SGI0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1107,7 +1075,7 @@ typedef struct { #define MRCC_GLB_ACC1_SGLCD0_MASK (0x40U) #define MRCC_GLB_ACC1_SGLCD0_SHIFT (6U) -/*! SGLCD0 - write to SGLCD0 +/*! SGLCD0 - Automatic clock control SGLCD0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ @@ -1115,19 +1083,11 @@ typedef struct { #define MRCC_GLB_ACC1_TRNG0_MASK (0x100U) #define MRCC_GLB_ACC1_TRNG0_SHIFT (8U) -/*! TRNG0 - Write to TRNG0 +/*! TRNG0 - Automatic clock control TRNG0 * 0b0..Automatic clock gating is disabled * 0b1..Automatic clock gating is enabled */ #define MRCC_GLB_ACC1_TRNG0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_ACC1_TRNG0_SHIFT)) & MRCC_GLB_ACC1_TRNG0_MASK) - -#define MRCC_GLB_ACC1_UDF0_MASK (0x200U) -#define MRCC_GLB_ACC1_UDF0_SHIFT (9U) -/*! UDF0 - Write to UDF0 - * 0b0..Automatic clock gating is disabled - * 0b1..Automatic clock gating is enabled - */ -#define MRCC_GLB_ACC1_UDF0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_ACC1_UDF0_SHIFT)) & MRCC_GLB_ACC1_UDF0_MASK) /*! @} */ /*! @name GLB_PR0 - Peripheral Enable Configuration 0 */ @@ -1135,7 +1095,7 @@ typedef struct { #define MRCC_GLB_PR0_CTIMER0_MASK (0x2U) #define MRCC_GLB_PR0_CTIMER0_SHIFT (1U) -/*! CTIMER0 - Write to CTIMER0 +/*! CTIMER0 - Enable/Disable CTIMER0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1143,7 +1103,7 @@ typedef struct { #define MRCC_GLB_PR0_CTIMER1_MASK (0x4U) #define MRCC_GLB_PR0_CTIMER1_SHIFT (2U) -/*! CTIMER1 - Write to CTIMER1 +/*! CTIMER1 - Enable/Disable CTIMER1 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1151,7 +1111,7 @@ typedef struct { #define MRCC_GLB_PR0_CTIMER2_MASK (0x8U) #define MRCC_GLB_PR0_CTIMER2_SHIFT (3U) -/*! CTIMER2 - Write to CTIMER2 +/*! CTIMER2 - Enable/Disable CTIMER2 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1159,7 +1119,7 @@ typedef struct { #define MRCC_GLB_PR0_FREQME_MASK (0x10U) #define MRCC_GLB_PR0_FREQME_SHIFT (4U) -/*! FREQME - Write to FREQME +/*! FREQME - Enable/Disable FREQME * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1167,7 +1127,7 @@ typedef struct { #define MRCC_GLB_PR0_UTICK0_MASK (0x20U) #define MRCC_GLB_PR0_UTICK0_SHIFT (5U) -/*! UTICK0 - Write to UTICK0 +/*! UTICK0 - Enable/Disable UTICK0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1175,7 +1135,7 @@ typedef struct { #define MRCC_GLB_PR0_DMA0_MASK (0x80U) #define MRCC_GLB_PR0_DMA0_SHIFT (7U) -/*! DMA0 - Write to DMA0 +/*! DMA0 - Enable/Disable DMA0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1183,7 +1143,7 @@ typedef struct { #define MRCC_GLB_PR0_AOI0_MASK (0x100U) #define MRCC_GLB_PR0_AOI0_SHIFT (8U) -/*! AOI0 - Write to AOI0 +/*! AOI0 - Enable/Disable AOI0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1191,7 +1151,7 @@ typedef struct { #define MRCC_GLB_PR0_CRC_MASK (0x200U) #define MRCC_GLB_PR0_CRC_SHIFT (9U) -/*! CRC - Write to CRC +/*! CRC - Enable/Disable CRC * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1199,7 +1159,7 @@ typedef struct { #define MRCC_GLB_PR0_ERM0_MASK (0x400U) #define MRCC_GLB_PR0_ERM0_SHIFT (10U) -/*! ERM0 - Write to ERM0 +/*! ERM0 - Enable/Disable ERM0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1207,7 +1167,7 @@ typedef struct { #define MRCC_GLB_PR0_LPI2C0_MASK (0x4000U) #define MRCC_GLB_PR0_LPI2C0_SHIFT (14U) -/*! LPI2C0 - Write to LPI2C0 +/*! LPI2C0 - Enable/Disable LPI2C0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1215,7 +1175,7 @@ typedef struct { #define MRCC_GLB_PR0_LPI2C1_MASK (0x8000U) #define MRCC_GLB_PR0_LPI2C1_SHIFT (15U) -/*! LPI2C1 - Write to LPI2C1 +/*! LPI2C1 - Enable/Disable LPI2C1 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1223,7 +1183,7 @@ typedef struct { #define MRCC_GLB_PR0_LPSPI0_MASK (0x10000U) #define MRCC_GLB_PR0_LPSPI0_SHIFT (16U) -/*! LPSPI0 - Write to LPSPI0 +/*! LPSPI0 - Enable/Disable LPSPI0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1231,7 +1191,7 @@ typedef struct { #define MRCC_GLB_PR0_LPSPI1_MASK (0x20000U) #define MRCC_GLB_PR0_LPSPI1_SHIFT (17U) -/*! LPSPI1 - Write to LPSPI1 +/*! LPSPI1 - Enable/Disable LPSPI1 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1239,7 +1199,7 @@ typedef struct { #define MRCC_GLB_PR0_LPUART0_MASK (0x40000U) #define MRCC_GLB_PR0_LPUART0_SHIFT (18U) -/*! LPUART0 - Write to LPUART0 +/*! LPUART0 - Enable/Disable LPUART0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1247,23 +1207,15 @@ typedef struct { #define MRCC_GLB_PR0_ADC0_MASK (0x80000U) #define MRCC_GLB_PR0_ADC0_SHIFT (19U) -/*! ADC0 - Write to ADC0 +/*! ADC0 - Enable/Disable ADC0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ #define MRCC_GLB_PR0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_PR0_ADC0_SHIFT)) & MRCC_GLB_PR0_ADC0_MASK) -#define MRCC_GLB_PR0_ATX0_MASK (0x100000U) -#define MRCC_GLB_PR0_ATX0_SHIFT (20U) -/*! ATX0 - Write to ATX0 - * 0b0..Peripheral is disabled - * 0b1..Peripheral is enabled - */ -#define MRCC_GLB_PR0_ATX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_PR0_ATX0_SHIFT)) & MRCC_GLB_PR0_ATX0_MASK) - #define MRCC_GLB_PR0_CMP0_MASK (0x200000U) #define MRCC_GLB_PR0_CMP0_SHIFT (21U) -/*! CMP0 - Write to CMP0 +/*! CMP0 - Enable/Disable CMP0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1271,7 +1223,7 @@ typedef struct { #define MRCC_GLB_PR0_DMA1_MASK (0x400000U) #define MRCC_GLB_PR0_DMA1_SHIFT (22U) -/*! DMA1 - write to DMA1 +/*! DMA1 - Enable/Disable DMA1 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1279,7 +1231,7 @@ typedef struct { #define MRCC_GLB_PR0_GPIO1_MASK (0x1000000U) #define MRCC_GLB_PR0_GPIO1_SHIFT (24U) -/*! GPIO1 - Write to GPIO1 +/*! GPIO1 - Enable/Disable GPIO1 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1287,7 +1239,7 @@ typedef struct { #define MRCC_GLB_PR0_GPIO2_MASK (0x2000000U) #define MRCC_GLB_PR0_GPIO2_SHIFT (25U) -/*! GPIO2 - Write to GPIO2 +/*! GPIO2 - Enable/Disable GPIO2 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1295,7 +1247,7 @@ typedef struct { #define MRCC_GLB_PR0_GPIO3_MASK (0x4000000U) #define MRCC_GLB_PR0_GPIO3_SHIFT (26U) -/*! GPIO3 - Write to GPIO3 +/*! GPIO3 - Enable/Disable GPIO3 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1303,7 +1255,7 @@ typedef struct { #define MRCC_GLB_PR0_LPUART1_MASK (0x8000000U) #define MRCC_GLB_PR0_LPUART1_SHIFT (27U) -/*! LPUART1 - Write to LPUART1 +/*! LPUART1 - Enable/Disable LPUART1 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1311,7 +1263,7 @@ typedef struct { #define MRCC_GLB_PR0_MTR_MASK (0x10000000U) #define MRCC_GLB_PR0_MTR_SHIFT (28U) -/*! MTR - Write to MTR +/*! MTR - Enable/Disable MTR * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1319,7 +1271,7 @@ typedef struct { #define MRCC_GLB_PR0_OSTIMER0_MASK (0x20000000U) #define MRCC_GLB_PR0_OSTIMER0_SHIFT (29U) -/*! OSTIMER0 - Write to OSTIMER0 +/*! OSTIMER0 - Enable/Disable OSTIMER0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1327,7 +1279,7 @@ typedef struct { #define MRCC_GLB_PR0_PGRP0_MASK (0x40000000U) #define MRCC_GLB_PR0_PGRP0_SHIFT (30U) -/*! PGRP0 - Write to PERIPH_GROUP_0 +/*! PGRP0 - Enable/Disable PERIPH_GROUP_0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1335,19 +1287,19 @@ typedef struct { #define MRCC_GLB_PR0_PGRP1_MASK (0x80000000U) #define MRCC_GLB_PR0_PGRP1_SHIFT (31U) -/*! PGRP1 - Write to PERIPH_GROUP_1 +/*! PGRP1 - Enable/Disable PERIPH_GROUP_1 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ #define MRCC_GLB_PR0_PGRP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_PR0_PGRP1_SHIFT)) & MRCC_GLB_PR0_PGRP1_MASK) /*! @} */ -/*! @name GLB_PR1 - Peripheral Enable Configuration 1 */ +/*! @name GLB_PR1 - Global Enable Configuration 1 */ /*! @{ */ #define MRCC_GLB_PR1_PKC0_MASK (0x1U) #define MRCC_GLB_PR1_PKC0_SHIFT (0U) -/*! PKC0 - Write to PKC0 +/*! PKC0 - Enable/Disable PKC0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1355,7 +1307,7 @@ typedef struct { #define MRCC_GLB_PR1_PORT1_MASK (0x2U) #define MRCC_GLB_PR1_PORT1_SHIFT (1U) -/*! PORT1 - Write to PORT1 +/*! PORT1 - Enable/Disable PORT1 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1363,7 +1315,7 @@ typedef struct { #define MRCC_GLB_PR1_PORT2_MASK (0x4U) #define MRCC_GLB_PR1_PORT2_SHIFT (2U) -/*! PORT2 - write to PORT2 +/*! PORT2 - Enable/Disable PORT2 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1371,7 +1323,7 @@ typedef struct { #define MRCC_GLB_PR1_PORT3_MASK (0x8U) #define MRCC_GLB_PR1_PORT3_SHIFT (3U) -/*! PORT3 - Write to PORT3 +/*! PORT3 - Enable/Disable PORT3 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1379,7 +1331,7 @@ typedef struct { #define MRCC_GLB_PR1_SGI0_MASK (0x20U) #define MRCC_GLB_PR1_SGI0_SHIFT (5U) -/*! SGI0 - Write to SGI0 +/*! SGI0 - Enable/Disable SGI0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1387,7 +1339,7 @@ typedef struct { #define MRCC_GLB_PR1_SGLCD0_MASK (0x40U) #define MRCC_GLB_PR1_SGLCD0_SHIFT (6U) -/*! SGLCD0 - write to SGLCD0 +/*! SGLCD0 - Enable/Disable SGLCD0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1395,7 +1347,7 @@ typedef struct { #define MRCC_GLB_PR1_TCU_MASK (0x80U) #define MRCC_GLB_PR1_TCU_SHIFT (7U) -/*! TCU - Write to TCU +/*! TCU - Enable/Disable TCU * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ @@ -1403,19 +1355,11 @@ typedef struct { #define MRCC_GLB_PR1_TRNG0_MASK (0x100U) #define MRCC_GLB_PR1_TRNG0_SHIFT (8U) -/*! TRNG0 - Write to TRNG0 +/*! TRNG0 - Enable/Disable TRNG0 * 0b0..Peripheral is disabled * 0b1..Peripheral is enabled */ #define MRCC_GLB_PR1_TRNG0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_PR1_TRNG0_SHIFT)) & MRCC_GLB_PR1_TRNG0_MASK) - -#define MRCC_GLB_PR1_UDF0_MASK (0x200U) -#define MRCC_GLB_PR1_UDF0_SHIFT (9U) -/*! UDF0 - write to UDF0 - * 0b0..Peripheral is disabled - * 0b1..Peripheral is enabled - */ -#define MRCC_GLB_PR1_UDF0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_GLB_PR1_UDF0_SHIFT)) & MRCC_GLB_PR1_UDF0_MASK) /*! @} */ /*! @name CTIMERGRP0CLKSEL - CTIMER_Group_0 clock selection control */ @@ -1442,7 +1386,7 @@ typedef struct { #define MRCC_CTIMERGRP0CLKDIV_RESET_MASK (0x20000000U) #define MRCC_CTIMERGRP0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1489,7 +1433,7 @@ typedef struct { #define MRCC_CTIMERGRP1CLKDIV_RESET_MASK (0x20000000U) #define MRCC_CTIMERGRP1CLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1536,7 +1480,7 @@ typedef struct { #define MRCC_WWDT0CLKDIV_RESET_MASK (0x20000000U) #define MRCC_WWDT0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1583,7 +1527,7 @@ typedef struct { #define MRCC_ADC0CLKDIV_RESET_MASK (0x20000000U) #define MRCC_ADC0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1616,7 +1560,7 @@ typedef struct { #define MRCC_CMP0FUNCCLKDIV_RESET_MASK (0x20000000U) #define MRCC_CMP0FUNCCLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1639,7 +1583,7 @@ typedef struct { #define MRCC_CMP0FUNCCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_CMP0FUNCCLKDIV_UNSTAB_SHIFT)) & MRCC_CMP0FUNCCLKDIV_UNSTAB_MASK) /*! @} */ -/*! @name CMP0RRCLKSEL - CMP0 clock selection control */ +/*! @name CMP0RRCLKSEL - CMP0_RR clock selection control */ /*! @{ */ #define MRCC_CMP0RRCLKSEL_MUX_MASK (0x3U) @@ -1663,7 +1607,7 @@ typedef struct { #define MRCC_CMP0RRCLKDIV_RESET_MASK (0x20000000U) #define MRCC_CMP0RRCLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1710,7 +1654,7 @@ typedef struct { #define MRCC_DBGTRACECLKDIV_RESET_MASK (0x20000000U) #define MRCC_DBGTRACECLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1757,7 +1701,7 @@ typedef struct { #define MRCC_CLKOUTCLKDIV_RESET_MASK (0x20000000U) #define MRCC_CLKOUTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1788,6 +1732,7 @@ typedef struct { /*! MUX - Functional Clock Mux Select * 0b00..clk_16k[2] * 0b01..FRO_16K + * 0b10.. * 0b11..clk_1m */ #define MRCC_OSTIMER0CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_OSTIMER0CLKSEL_MUX_SHIFT)) & MRCC_OSTIMER0CLKSEL_MUX_MASK) @@ -1817,7 +1762,7 @@ typedef struct { #define MRCC_PGRP0CLKDIV_RESET_MASK (0x20000000U) #define MRCC_PGRP0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1864,7 +1809,7 @@ typedef struct { #define MRCC_PGRP1CLKDIV_RESET_MASK (0x20000000U) #define MRCC_PGRP1CLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ @@ -1911,7 +1856,7 @@ typedef struct { #define MRCC_SYSTICKCLKDIV_RESET_MASK (0x20000000U) #define MRCC_SYSTICKCLKDIV_RESET_SHIFT (29U) -/*! RESET - Reset divider counter +/*! RESET - Resets divider counter * 0b0..Divider is not reset * 0b1..Divider is reset */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_MU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_MU.h index d1b350eee..07b1895ff 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_MU.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_MU.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for MU * * CMSIS Peripheral Access Layer for MU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_OSTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_OSTIMER.h index 5efc03ee2..eaaf9944e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_OSTIMER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_OSTIMER.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSTIMER @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_OSTIMER.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for OSTIMER * * CMSIS Peripheral Access Layer for OSTIMER diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PKC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PKC.h index 7fe858d0f..44ec8c34f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PKC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PKC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for PKC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_PKC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for PKC * * CMSIS Peripheral Access Layer for PKC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PMU.h index c23824c1f..9b6a60e7a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PMU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PMU.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for PMU @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_PMU.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for PMU * * CMSIS Peripheral Access Layer for PMU @@ -102,8 +102,8 @@ /** PMU - Register Layout Typedef */ typedef struct { __IO uint32_t PCTRL; /**< Power Control, offset: 0x0 */ - __IO uint32_t VDD_CORE_PCONFIG; /**< VDD Core Power Configuration, offset: 0x4 */ - __IO uint32_t VDD_CORE_1P1_CONFIG; /**< VDD_CORE_1P1 Configuration, offset: 0x8 */ + __IO uint32_t VDD_CORE_PCONFIG; /**< VDD_CORE DCDC_AON Power Configuration, offset: 0x4 */ + __IO uint32_t VDD_CORE_1P1_CONFIG; /**< VDD_CORE DCDC_MAIN Configuration, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t FRO_CTRL; /**< 16KHz FRO Control, offset: 0x10 */ uint8_t RESERVED_1[72]; @@ -127,33 +127,38 @@ typedef struct { #define PMU_PCTRL_VDDP_EN_SHIFT (0U) /*! VDDP_EN - VDD Power Enable */ #define PMU_PCTRL_VDDP_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCTRL_VDDP_EN_SHIFT)) & PMU_PCTRL_VDDP_EN_MASK) + +#define PMU_PCTRL_VDD_CORE_1P1_EN_MASK (0x2U) +#define PMU_PCTRL_VDD_CORE_1P1_EN_SHIFT (1U) +/*! VDD_CORE_1P1_EN - VDD_CORE_1P1 Power Enable */ +#define PMU_PCTRL_VDD_CORE_1P1_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCTRL_VDD_CORE_1P1_EN_SHIFT)) & PMU_PCTRL_VDD_CORE_1P1_EN_MASK) /*! @} */ -/*! @name VDD_CORE_PCONFIG - VDD Core Power Configuration */ +/*! @name VDD_CORE_PCONFIG - VDD_CORE DCDC_AON Power Configuration */ /*! @{ */ #define PMU_VDD_CORE_PCONFIG_VDD_ACONFIG_MASK (0x3FU) #define PMU_VDD_CORE_PCONFIG_VDD_ACONFIG_SHIFT (0U) -/*! VDD_ACONFIG - VDD_CORE Active Configuration */ +/*! VDD_ACONFIG - VDD_CORE DCDC_AON Active Configuration */ #define PMU_VDD_CORE_PCONFIG_VDD_ACONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_VDD_CORE_PCONFIG_VDD_ACONFIG_SHIFT)) & PMU_VDD_CORE_PCONFIG_VDD_ACONFIG_MASK) #define PMU_VDD_CORE_PCONFIG_VDD_DSCONFIG_MASK (0xFC0U) #define PMU_VDD_CORE_PCONFIG_VDD_DSCONFIG_SHIFT (6U) -/*! VDD_DSCONFIG - VDD_CORE Deep Sleep mode Configuration */ +/*! VDD_DSCONFIG - VDD_CORE Deep Sleep Mode Configuration */ #define PMU_VDD_CORE_PCONFIG_VDD_DSCONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_VDD_CORE_PCONFIG_VDD_DSCONFIG_SHIFT)) & PMU_VDD_CORE_PCONFIG_VDD_DSCONFIG_MASK) /*! @} */ -/*! @name VDD_CORE_1P1_CONFIG - VDD_CORE_1P1 Configuration */ +/*! @name VDD_CORE_1P1_CONFIG - VDD_CORE DCDC_MAIN Configuration */ /*! @{ */ #define PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_ACONFIG_MASK (0xFFU) #define PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_ACONFIG_SHIFT (0U) -/*! VDD_CORE_1P1_ACONFIG - VDD_CORE_1P1 Active Configuration */ +/*! VDD_CORE_1P1_ACONFIG - VDD_CORE DCDC_MAIN Active Configuration */ #define PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_ACONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_ACONFIG_SHIFT)) & PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_ACONFIG_MASK) #define PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_VOUTSEL_LPWR_MASK (0x1F00U) #define PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_VOUTSEL_LPWR_SHIFT (8U) -/*! VDD_CORE_1P1_VOUTSEL_LPWR - VDD_CORE_1P1 Voute Select Low Power */ +/*! VDD_CORE_1P1_VOUTSEL_LPWR - VDD CORE DCDC_MAIN Vout Select Low Power */ #define PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_VOUTSEL_LPWR(x) (((uint32_t)(((uint32_t)(x)) << PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_VOUTSEL_LPWR_SHIFT)) & PMU_VDD_CORE_1P1_CONFIG_VDD_CORE_1P1_VOUTSEL_LPWR_MASK) /*! @} */ @@ -162,7 +167,10 @@ typedef struct { #define PMU_FRO_CTRL_FRO16K_EN_MASK (0x1U) #define PMU_FRO_CTRL_FRO16K_EN_SHIFT (0U) -/*! FRO16K_EN - FRO16K Enable */ +/*! FRO16K_EN - FRO16K Enable + * 0b0..Enable + * 0b1..Disable + */ #define PMU_FRO_CTRL_FRO16K_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_FRO_CTRL_FRO16K_EN_SHIFT)) & PMU_FRO_CTRL_FRO16K_EN_MASK) #define PMU_FRO_CTRL_CLOCK_SEL_MASK (0x2000U) @@ -179,7 +187,7 @@ typedef struct { #define PMU_VDD_WKUP_WDTC_DCDC_WKUP_WDOG_MASK (0x7FFFU) #define PMU_VDD_WKUP_WDTC_DCDC_WKUP_WDOG_SHIFT (0U) -/*! DCDC_WKUP_WDOG - DCDC Wakeup Watchdog */ +/*! DCDC_WKUP_WDOG - DCDC_AON Wakeup Watchdog */ #define PMU_VDD_WKUP_WDTC_DCDC_WKUP_WDOG(x) (((uint32_t)(((uint32_t)(x)) << PMU_VDD_WKUP_WDTC_DCDC_WKUP_WDOG_SHIFT)) & PMU_VDD_WKUP_WDTC_DCDC_WKUP_WDOG_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PORT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PORT.h index 72af70d9c..b023938db 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PORT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_PORT.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for PORT @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_PORT.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for PORT * * CMSIS Peripheral Access Layer for PORT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_RTC.h index 0629dd91e..bff167ea9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_RTC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_RTC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for RTC * * CMSIS Peripheral Access Layer for RTC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SCG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SCG.h index 97c72ea00..6cef6865a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SCG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SCG.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for SCG @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_SCG.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for SCG * * CMSIS Peripheral Access Layer for SCG diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGI.h index 7421b9368..38b9b2e79 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGI.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for SGI @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_SGI.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for SGI * * CMSIS Peripheral Access Layer for SGI diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGLCD_CONTROL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGLCD_CONTROL.h index 84b3fade2..39f77abf0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGLCD_CONTROL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGLCD_CONTROL.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for SGLCD_CONTROL @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_SGLCD_CONTROL.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for SGLCD_CONTROL * * CMSIS Peripheral Access Layer for SGLCD_CONTROL diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGLCD_FAULT_DETECT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGLCD_FAULT_DETECT.h index 301538b83..d1d9d54fb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGLCD_FAULT_DETECT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SGLCD_FAULT_DETECT.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for SGLCD_FAULT_DETECT @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_SGLCD_FAULT_DETECT.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for SGLCD_FAULT_DETECT * * CMSIS Peripheral Access Layer for SGLCD_FAULT_DETECT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SMM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SMM.h index 643447de0..0daa58ebf 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SMM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SMM.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for SMM @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_SMM.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for SMM * * CMSIS Peripheral Access Layer for SMM @@ -302,7 +302,7 @@ typedef struct { #define SMM_PWDN_CONFIG_DPD1_VDD1P1_SRC_MASK (0x2U) #define SMM_PWDN_CONFIG_DPD1_VDD1P1_SRC_SHIFT (1U) -/*! DPD1_VDD1P1_SRC - DPD1 VDD1P1 power supply +/*! DPD1_VDD1P1_SRC - DPD1_MAIN power supply * 0b0..Keep as is * 0b1..Move to Low Power mode of the DCDC fixed. */ @@ -535,10 +535,10 @@ typedef struct { /*! MAIN_CPU_SRAM_RET - SRAM retain */ #define SMM_MEMORY_RTN_MAIN_CPU_SRAM_RET(x) (((uint32_t)(((uint32_t)(x)) << SMM_MEMORY_RTN_MAIN_CPU_SRAM_RET_SHIFT)) & SMM_MEMORY_RTN_MAIN_CPU_SRAM_RET_MASK) -#define SMM_MEMORY_RTN_CPU_RAM_PWD_MASK (0x1C00U) -#define SMM_MEMORY_RTN_CPU_RAM_PWD_SHIFT (10U) -/*! CPU_RAM_PWD - AON CPU core RAM powerdown */ -#define SMM_MEMORY_RTN_CPU_RAM_PWD(x) (((uint32_t)(((uint32_t)(x)) << SMM_MEMORY_RTN_CPU_RAM_PWD_SHIFT)) & SMM_MEMORY_RTN_CPU_RAM_PWD_MASK) +#define SMM_MEMORY_RTN_CPU_SRAMBn_PWD_MASK (0x1C00U) +#define SMM_MEMORY_RTN_CPU_SRAMBn_PWD_SHIFT (10U) +/*! CPU_SRAMBn_PWD - AON CPU core RAM powerdown */ +#define SMM_MEMORY_RTN_CPU_SRAMBn_PWD(x) (((uint32_t)(((uint32_t)(x)) << SMM_MEMORY_RTN_CPU_SRAMBn_PWD_SHIFT)) & SMM_MEMORY_RTN_CPU_SRAMBn_PWD_MASK) #define SMM_MEMORY_RTN_IVS_EN_MASK (0x4000U) #define SMM_MEMORY_RTN_IVS_EN_SHIFT (14U) @@ -578,15 +578,15 @@ typedef struct { /*! @name XTAL_TRIM - XTAL Trim */ /*! @{ */ -#define SMM_XTAL_TRIM_TRIM_DIR_MASK (0x3FFU) -#define SMM_XTAL_TRIM_TRIM_DIR_SHIFT (0U) -/*! TRIM_DIR - XTAL Trim interval */ -#define SMM_XTAL_TRIM_TRIM_DIR(x) (((uint32_t)(((uint32_t)(x)) << SMM_XTAL_TRIM_TRIM_DIR_SHIFT)) & SMM_XTAL_TRIM_TRIM_DIR_MASK) +#define SMM_XTAL_TRIM_TRIM_INTV_MASK (0x3FFU) +#define SMM_XTAL_TRIM_TRIM_INTV_SHIFT (0U) +/*! TRIM_INTV - XTAL Trim interval */ +#define SMM_XTAL_TRIM_TRIM_INTV(x) (((uint32_t)(((uint32_t)(x)) << SMM_XTAL_TRIM_TRIM_INTV_SHIFT)) & SMM_XTAL_TRIM_TRIM_INTV_MASK) -#define SMM_XTAL_TRIM_TRIM_VAL_MASK (0x400U) -#define SMM_XTAL_TRIM_TRIM_VAL_SHIFT (10U) -/*! TRIM_VAL - XTAL Trim up */ -#define SMM_XTAL_TRIM_TRIM_VAL(x) (((uint32_t)(((uint32_t)(x)) << SMM_XTAL_TRIM_TRIM_VAL_SHIFT)) & SMM_XTAL_TRIM_TRIM_VAL_MASK) +#define SMM_XTAL_TRIM_TRIM_UP_MASK (0x400U) +#define SMM_XTAL_TRIM_TRIM_UP_SHIFT (10U) +/*! TRIM_UP - XTAL Trim up */ +#define SMM_XTAL_TRIM_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << SMM_XTAL_TRIM_TRIM_UP_SHIFT)) & SMM_XTAL_TRIM_TRIM_UP_MASK) /*! @} */ /*! @name TAMP_CTRL - Tamper Control */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SYSCON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SYSCON.h index a1428a1ac..064f7579a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SYSCON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SYSCON.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_SYSCON.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for SYSCON * * CMSIS Peripheral Access Layer for SYSCON @@ -433,17 +433,17 @@ typedef struct { #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK (0x10000U) #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U) -/*! DIS_MBECC_ERR_INST - Bus error on instruction multi-bit ecc error control - * 0b0..Enables bus error on multi-bit ecc error for instruction - * 0b1..Disables bus error on multi-bit ecc error for instruction +/*! DIS_MBECC_ERR_INST - Bus error on instruction multi-bit ECC error control + * 0b0..Enables bus error on multi-bit ECC error for instruction + * 0b1..Disables bus error on multi-bit ECC error for instruction */ #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK) #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK (0x20000U) #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U) -/*! DIS_MBECC_ERR_DATA - Bus error on data multi-bit ecc error control - * 0b0..Enables bus error on multi-bit ecc error for data - * 0b1..Disables bus error on multi-bit ecc error for data +/*! DIS_MBECC_ERR_DATA - Bus error on data multi-bit ECC error control + * 0b0..Enables bus error on multi-bit ECC error for data + * 0b1..Disables bus error on multi-bit ECC error for data */ #define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK) /*! @} */ @@ -453,7 +453,7 @@ typedef struct { #define SYSCON_ROMCR_ROM_WAIT_MASK (0x1U) #define SYSCON_ROMCR_ROM_WAIT_SHIFT (0U) -/*! ROM_WAIT - ROM waiting Arm core and other masters */ +/*! ROM_WAIT - ROM waiting Arm CM33 core and other controllers */ #define SYSCON_ROMCR_ROM_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROMCR_ROM_WAIT_SHIFT)) & SYSCON_ROMCR_ROM_WAIT_MASK) /*! @} */ @@ -494,12 +494,12 @@ typedef struct { #define SYSCON_SRAMCTL_SRAMCTL_TMTR_REQ_MASK (0x40000000U) #define SYSCON_SRAMCTL_SRAMCTL_TMTR_REQ_SHIFT (30U) -/*! SRAMCTL_TMTR_REQ - This bit will give TMTR values written req */ +/*! SRAMCTL_TMTR_REQ - This bit will give TMTR values written on request. */ #define SYSCON_SRAMCTL_SRAMCTL_TMTR_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTL_SRAMCTL_TMTR_REQ_SHIFT)) & SYSCON_SRAMCTL_SRAMCTL_TMTR_REQ_MASK) #define SYSCON_SRAMCTL_SRAMCTL_TMTR_ACK_MASK (0x80000000U) #define SYSCON_SRAMCTL_SRAMCTL_TMTR_ACK_SHIFT (31U) -/*! SRAMCTL_TMTR_ACK - This bit will give TMTR values written ack. write this bit 1 to clear the ack */ +/*! SRAMCTL_TMTR_ACK - This bit will give TMTR values written on acknowledgment. Write this bit 1 to clear the acknowledgment. */ #define SYSCON_SRAMCTL_SRAMCTL_TMTR_ACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTL_SRAMCTL_TMTR_ACK_SHIFT)) & SYSCON_SRAMCTL_SRAMCTL_TMTR_ACK_MASK) /*! @} */ @@ -522,13 +522,13 @@ typedef struct { */ #define SYSCON_PULSECAPSYNC_BYPASS_LPUART1_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PULSECAPSYNC_BYPASS_LPUART1_0_SHIFT)) & SYSCON_PULSECAPSYNC_BYPASS_LPUART1_0_MASK) -#define SYSCON_PULSECAPSYNC_BYPASS_LPCMP0_0_MASK (0x4U) -#define SYSCON_PULSECAPSYNC_BYPASS_LPCMP0_0_SHIFT (2U) -/*! LPCMP0_0 - LPCMP0 Trigger Bypass Control Bit +#define SYSCON_PULSECAPSYNC_BYPASS_CMP0_0_MASK (0x4U) +#define SYSCON_PULSECAPSYNC_BYPASS_CMP0_0_SHIFT (2U) +/*! CMP0_0 - CMP0 Trigger Bypass Control Bit * 0b0..Pulse capture sync bypassed * 0b1..Pulse capture sync enabled */ -#define SYSCON_PULSECAPSYNC_BYPASS_LPCMP0_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PULSECAPSYNC_BYPASS_LPCMP0_0_SHIFT)) & SYSCON_PULSECAPSYNC_BYPASS_LPCMP0_0_MASK) +#define SYSCON_PULSECAPSYNC_BYPASS_CMP0_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PULSECAPSYNC_BYPASS_CMP0_0_SHIFT)) & SYSCON_PULSECAPSYNC_BYPASS_CMP0_0_MASK) #define SYSCON_PULSECAPSYNC_BYPASS_CTIMER2_4_MASK (0x8U) #define SYSCON_PULSECAPSYNC_BYPASS_CTIMER2_4_SHIFT (3U) @@ -985,80 +985,80 @@ typedef struct { #define SYSCON_SRAM_XEN_RAMX0_XEN_MASK (0x1U) #define SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT (0U) /*! RAMX0_XEN - RAMX0 Execute permission control. - * 0b0..Execute permission is disabled, R/W are enabled. - * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, Read/Write are enabled. + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled. */ #define SYSCON_SRAM_XEN_RAMX0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX0_XEN_MASK) #define SYSCON_SRAM_XEN_RAMX1_XEN_MASK (0x2U) #define SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT (1U) /*! RAMX1_XEN - RAMX1 Execute permission control. - * 0b0..Execute permission is disabled, R/W are enabled. - * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, Read/Write are enabled. + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled. */ #define SYSCON_SRAM_XEN_RAMX1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX1_XEN_MASK) #define SYSCON_SRAM_XEN_RAMA0_XEN_MASK (0x4U) #define SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT (2U) /*! RAMA0_XEN - RAMA0 Execute permission control. - * 0b0..Execute permission is disabled, R/W are enabled. - * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, Read/Write are enabled. + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled. */ #define SYSCON_SRAM_XEN_RAMA0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA0_XEN_MASK) #define SYSCON_SRAM_XEN_RAMA1_XEN_MASK (0x8U) #define SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT (3U) /*! RAMA1_XEN - RAMA1 Execute permission control. - * 0b0..Execute permission is disabled, R/W are enabled. - * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, Read/Write are enabled. + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled. */ #define SYSCON_SRAM_XEN_RAMA1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA1_XEN_MASK) #define SYSCON_SRAM_XEN_RAMB0_XEN_MASK (0x10U) #define SYSCON_SRAM_XEN_RAMB0_XEN_SHIFT (4U) /*! RAMB0_XEN - RAMB0 Executable Permission Control - * 0b0..Execute permission is disabled, R/W are enabled - * 0b1..Execute permission is enabled, R/W/X are enabled + * 0b0..Execute permission is disabled, Read/Write are enabled + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled */ #define SYSCON_SRAM_XEN_RAMB0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMB0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMB0_XEN_MASK) #define SYSCON_SRAM_XEN_RAMA2_XEN_MASK (0x20U) #define SYSCON_SRAM_XEN_RAMA2_XEN_SHIFT (5U) /*! RAMA2_XEN - RAMA1 Execute permission control. - * 0b0..Execute permission is disabled, R/W are enabled. - * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, Read/Write are enabled. + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled. */ #define SYSCON_SRAM_XEN_RAMA2_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA2_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA2_XEN_MASK) #define SYSCON_SRAM_XEN_RAMA3_XEN_MASK (0x40U) #define SYSCON_SRAM_XEN_RAMA3_XEN_SHIFT (6U) /*! RAMA3_XEN - RAMA1 Execute permission control. - * 0b0..Execute permission is disabled, R/W are enabled. - * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, Read/Write are enabled. + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled. */ #define SYSCON_SRAM_XEN_RAMA3_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA3_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA3_XEN_MASK) #define SYSCON_SRAM_XEN_RAMB1_XEN_MASK (0x80U) #define SYSCON_SRAM_XEN_RAMB1_XEN_SHIFT (7U) /*! RAMB1_XEN - RAMB1 Executable Permission Control - * 0b0..Execute permission is disabled, R/W are enabled - * 0b1..Execute permission is enabled, R/W/X are enabled + * 0b0..Execute permission is disabled, Read/Write are enabled + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled */ #define SYSCON_SRAM_XEN_RAMB1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMB1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMB1_XEN_MASK) #define SYSCON_SRAM_XEN_RAMB2_XEN_MASK (0x100U) #define SYSCON_SRAM_XEN_RAMB2_XEN_SHIFT (8U) /*! RAMB2_XEN - RAMB2 Executable Permission Control - * 0b0..Execute permission is disabled, R/W are enabled - * 0b1..Execute permission is enabled, R/W/X are enabled + * 0b0..Execute permission is disabled, Read/Write are enabled + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled */ #define SYSCON_SRAM_XEN_RAMB2_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMB2_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMB2_XEN_MASK) #define SYSCON_SRAM_XEN_RAMB3_XEN_MASK (0x200U) #define SYSCON_SRAM_XEN_RAMB3_XEN_SHIFT (9U) /*! RAMB3_XEN - RAMB3 and RAMB4 Interleaved Executable Permission Control - * 0b0..Execute permission is disabled, R/W are enabled - * 0b1..Execute permission is enabled, R/W/X are enabled + * 0b0..Execute permission is disabled, Read/Write are enabled + * 0b1..Execute permission is enabled, Read/Write/Execute are enabled */ #define SYSCON_SRAM_XEN_RAMB3_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMB3_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMB3_XEN_MASK) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SYSCON_AON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SYSCON_AON.h index 02ab0e2a1..283f75410 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SYSCON_AON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_SYSCON_AON.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON_AON @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_SYSCON_AON.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for SYSCON_AON * * CMSIS Peripheral Access Layer for SYSCON_AON @@ -110,7 +110,7 @@ typedef struct { uint8_t RESERVED_1[4]; __IO uint32_t CPU_SLEEP_SELECT; /**< CPU Sleep Select, offset: 0x1C */ __IO uint32_t PULSE_CAP_ACMP_CLK_MUXSEL; /**< CMP Pulse Capture Clock MUXSEL, offset: 0x20 */ - __IO uint32_t PINMUXCLKCTRL; /**< Pinmux Clock Control, offset: 0x24 */ + __IO uint32_t INPUTMUXCLKCTRL; /**< INPUTMUX Clock Control, offset: 0x24 */ __IO uint32_t SYNC_EN_INPUTMUX_AON; /**< Synchronization Enable INPUTMUX, offset: 0x28 */ uint8_t RESERVED_2[4]; __IO uint32_t IPG_DEBUG_ENABLE; /**< IPG Debug Enable, offset: 0x30 */ @@ -289,16 +289,16 @@ typedef struct { #define SYSCON_AON_PULSE_CAP_ACMP_CLK_MUXSEL_ACMP0_PULSE_CAP_SYNC_CLK_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AON_PULSE_CAP_ACMP_CLK_MUXSEL_ACMP0_PULSE_CAP_SYNC_CLK_MUX_SEL_SHIFT)) & SYSCON_AON_PULSE_CAP_ACMP_CLK_MUXSEL_ACMP0_PULSE_CAP_SYNC_CLK_MUX_SEL_MASK) /*! @} */ -/*! @name PINMUXCLKCTRL - Pinmux Clock Control */ +/*! @name INPUTMUXCLKCTRL - INPUTMUX Clock Control */ /*! @{ */ -#define SYSCON_AON_PINMUXCLKCTRL_PINMUX_CLK_CTRL_MASK (0x1U) -#define SYSCON_AON_PINMUXCLKCTRL_PINMUX_CLK_CTRL_SHIFT (0U) -/*! PINMUX_CLK_CTRL - This signal acts as a clock disable signal for pinmux clock - * 0b0..Clock is not disabled - * 0b1..Clock is disabled +#define SYSCON_AON_INPUTMUXCLKCTRL_INPUTMUX_CLK_CTRL_MASK (0x1U) +#define SYSCON_AON_INPUTMUXCLKCTRL_INPUTMUX_CLK_CTRL_SHIFT (0U) +/*! INPUTMUX_CLK_CTRL - This signal acts as a clock enable/disable signal + * 0b0..Clock Enable + * 0b1..Clock Disable */ -#define SYSCON_AON_PINMUXCLKCTRL_PINMUX_CLK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AON_PINMUXCLKCTRL_PINMUX_CLK_CTRL_SHIFT)) & SYSCON_AON_PINMUXCLKCTRL_PINMUX_CLK_CTRL_MASK) +#define SYSCON_AON_INPUTMUXCLKCTRL_INPUTMUX_CLK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AON_INPUTMUXCLKCTRL_INPUTMUX_CLK_CTRL_SHIFT)) & SYSCON_AON_INPUTMUXCLKCTRL_INPUTMUX_CLK_CTRL_MASK) /*! @} */ /*! @name SYNC_EN_INPUTMUX_AON - Synchronization Enable INPUTMUX */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TMR.h index db9ea4ec0..8abc60cd8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TMR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TMR.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMR @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_TMR.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for TMR * * CMSIS Peripheral Access Layer for TMR diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TRDC.h index d5092f197..eafa74fda 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TRDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TRDC.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_TRDC.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for TRDC * * CMSIS Peripheral Access Layer for TRDC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TRNG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TRNG.h index aba8f3363..dc320eeb2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TRNG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_TRNG.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRNG @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_TRNG.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for TRNG * * CMSIS Peripheral Access Layer for TRNG @@ -520,6 +520,14 @@ typedef struct { * 0b1..Enables the INT_STATUS[FRQ_CT_FAIL] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition. */ #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) + +#define TRNG_INT_CTRL_INTG_FLT_MASK (0x8U) +#define TRNG_INT_CTRL_INTG_FLT_SHIFT (3U) +/*! INTG_FLT + * 0b0..Clears the INT_STATUS[INTG_FLT] bit. Will automatically set after writing. + * 0b1..Enables the INT_STATUS[INTG_FLT] bit to be set, thereby enabling interrupt generation for the INTG_FLT condition. + */ +#define TRNG_INT_CTRL_INTG_FLT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_INTG_FLT_SHIFT)) & TRNG_INT_CTRL_INTG_FLT_MASK) /*! @} */ /*! @name INT_MASK - Mask Register */ @@ -548,6 +556,14 @@ typedef struct { * 0b1..FRQ_CT_FAIL interrupt is enabled. */ #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) + +#define TRNG_INT_MASK_INTG_FLT_MASK (0x8U) +#define TRNG_INT_MASK_INTG_FLT_SHIFT (3U) +/*! INTG_FLT + * 0b0..INTG_FLT interrupt is disabled. + * 0b1..INTG_FLT interrupt is enabled. + */ +#define TRNG_INT_MASK_INTG_FLT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_INTG_FLT_SHIFT)) & TRNG_INT_MASK_INTG_FLT_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ @@ -576,6 +592,14 @@ typedef struct { * 0b1..The frequency counter has detected a failure. */ #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) + +#define TRNG_INT_STATUS_INTG_FLT_MASK (0x8U) +#define TRNG_INT_STATUS_INTG_FLT_SHIFT (3U) +/*! INTG_FLT + * 0b0..No internal fault has been detected. + * 0b1..TRNG has detected internal fault. + */ +#define TRNG_INT_STATUS_INTG_FLT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_INTG_FLT_SHIFT)) & TRNG_INT_STATUS_INTG_FLT_MASK) /*! @} */ /*! @name CSER - Common Security Error Register */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_UDF.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_UDF.h index 2da44858a..29e229394 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_UDF.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_UDF.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for UDF @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_UDF.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for UDF * * CMSIS Peripheral Access Layer for UDF diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_UTICK.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_UTICK.h index 878d52c72..fa9a1a4a6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_UTICK.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_UTICK.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for UTICK @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_UTICK.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for UTICK * * CMSIS Peripheral Access Layer for UTICK diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_WUU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_WUU.h index 483eba0ae..1f4ad3723 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_WUU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_WUU.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for WUU @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_WUU.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for WUU * * CMSIS Peripheral Access Layer for WUU @@ -1527,7 +1527,7 @@ typedef struct { #define WUU_FMC_FILTM1_MASK (0x1U) #define WUU_FMC_FILTM1_SHIFT (0U) /*! FILTM1 - Filter Mode for FILTn - * 0b0..Active only during Deep Sleep 1/Deep Power Down mode + * 0b0..Active only during Deep Sleep/Deep Power Down mode * 0b1..Active during all power modes */ #define WUU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK) @@ -1535,7 +1535,7 @@ typedef struct { #define WUU_FMC_FILTM2_MASK (0x2U) #define WUU_FMC_FILTM2_SHIFT (1U) /*! FILTM2 - Filter Mode for FILTn - * 0b0..Active only during Deep Sleep 1/Deep Power Down mode + * 0b0..Active only during Deep Sleep/Deep Power Down mode * 0b1..Active during all power modes */ #define WUU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_WWDT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_WWDT.h index 7e9144fca..134eb64a1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_WWDT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXL/periph_L2/PERI_WWDT.h @@ -13,8 +13,8 @@ ** MCXL255VLL_cm0plus ** MCXL255VLL_cm33 ** -** Version: rev. 1.0, 2023-01-09 -** Build: b250520 +** Version: rev. 1.0, 2025-06-13 +** Build: b250723 ** ** Abstract: ** CMSIS Peripheral Access Layer for WWDT @@ -27,8 +27,8 @@ ** mail: support@nxp.com ** ** Revisions: -** - rev. 1.0 (2023-01-09) -** Generated based on Rev1 DraftI. +** - rev. 1.0 (2025-06-13) +** Generated based on Rev1 DraftH. ** ** ################################################################### */ @@ -36,7 +36,7 @@ /*! * @file PERI_WWDT.h * @version 1.0 - * @date 2023-01-09 + * @date 2025-06-13 * @brief CMSIS Peripheral Access Layer for WWDT * * CMSIS Peripheral Access Layer for WWDT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN235/MCXN235_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN235/MCXN235_COMMON.h index 4bedfddca..4ea8c2b0c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN235/MCXN235_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN235/MCXN235_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: MCXN23XRM ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250623 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN235 @@ -1004,14 +1004,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1020,14 +1012,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1036,14 +1020,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1052,14 +1028,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1068,14 +1036,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1084,6 +1044,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1093,72 +1093,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* I2S - Peripheral instance base addresses */ @@ -2655,9 +2649,9 @@ typedef enum IRQn { /* USBHSDCD - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBHS1_PHY_DCD base address */ - #define USBHS1_PHY_DCD_BASE (0x5010A000u) + #define USBHS1_PHY_DCD_BASE (0x5010A800u) /** Peripheral USBHS1_PHY_DCD base address */ - #define USBHS1_PHY_DCD_BASE_NS (0x4010A000u) + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) /** Peripheral USBHS1_PHY_DCD base pointer */ #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) /** Peripheral USBHS1_PHY_DCD base pointer */ @@ -2672,7 +2666,7 @@ typedef enum IRQn { #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } #else /** Peripheral USBHS1_PHY_DCD base address */ - #define USBHS1_PHY_DCD_BASE (0x4010A000u) + #define USBHS1_PHY_DCD_BASE (0x4010A800u) /** Peripheral USBHS1_PHY_DCD base pointer */ #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) /** Array initializer of USBHSDCD peripheral base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN235/MCXN235_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN235/MCXN235_features.h index eedcaaaa6..e5a75f9d3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN235/MCXN235_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN235/MCXN235_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -275,6 +275,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -282,6 +286,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -432,8 +438,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -462,6 +466,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -488,14 +494,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -586,8 +592,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -630,6 +634,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -766,7 +774,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -811,8 +819,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -841,14 +847,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SPC module features */ @@ -937,7 +947,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -961,10 +971,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN235_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN236/MCXN236_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN236/MCXN236_COMMON.h index 406011318..667db6570 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN236/MCXN236_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN236/MCXN236_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: MCXN23XRM ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250623 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN236 @@ -1004,14 +1004,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1020,14 +1012,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1036,14 +1020,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1052,14 +1028,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1068,14 +1036,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1084,6 +1044,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1093,72 +1093,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* I2S - Peripheral instance base addresses */ @@ -2655,9 +2649,9 @@ typedef enum IRQn { /* USBHSDCD - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBHS1_PHY_DCD base address */ - #define USBHS1_PHY_DCD_BASE (0x5010A000u) + #define USBHS1_PHY_DCD_BASE (0x5010A800u) /** Peripheral USBHS1_PHY_DCD base address */ - #define USBHS1_PHY_DCD_BASE_NS (0x4010A000u) + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) /** Peripheral USBHS1_PHY_DCD base pointer */ #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) /** Peripheral USBHS1_PHY_DCD base pointer */ @@ -2672,7 +2666,7 @@ typedef enum IRQn { #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } #else /** Peripheral USBHS1_PHY_DCD base address */ - #define USBHS1_PHY_DCD_BASE (0x4010A000u) + #define USBHS1_PHY_DCD_BASE (0x4010A800u) /** Peripheral USBHS1_PHY_DCD base pointer */ #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) /** Array initializer of USBHSDCD peripheral base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN236/MCXN236_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN236/MCXN236_features.h index 6ecef175e..15b6d6b8f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN236/MCXN236_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN236/MCXN236_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -275,6 +275,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -282,6 +286,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -432,8 +438,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -462,6 +466,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -488,14 +494,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -586,8 +592,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -630,6 +634,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -766,7 +774,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -811,8 +819,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -841,14 +847,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SPC module features */ @@ -937,7 +947,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -961,10 +971,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN236_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/CMakeLists.txt new file mode 100644 index 000000000..2140a5abd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/MCXN247.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/MCXN247.h new file mode 100644 index 000000000..0fd160390 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/MCXN247.h @@ -0,0 +1,121 @@ +/* +** ################################################################### +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN247 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN247.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN247 + * + * CMSIS Peripheral Access Layer for MCXN247 + */ + +#if !defined(MCXN247_H_) /* Check if memory map has not been already included */ +#define MCXN247_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EMVSIM.h" +#include "PERI_ENET.h" +#include "PERI_ERM.h" +#include "PERI_EVTG.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_HPDAC.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PLU.h" +#include "PERI_PORT.h" +#include "PERI_PUF.h" +#include "PERI_PWM.h" +#include "PERI_QDC.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SINC.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN247_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/MCXN247_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/MCXN247_COMMON.h new file mode 100644 index 000000000..2462bbafd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/MCXN247_COMMON.h @@ -0,0 +1,3329 @@ +/* +** ################################################################### +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN247 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN247_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN247 + * + * CMSIS Peripheral Access Layer for MCXN247 + */ + +#if !defined(MCXN247_COMMON_H_) +#define MCXN247_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + Reserved64_IRQn = 48, /**< Reserved interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + Reserved66_IRQn = 50, /**< Reserved interrupt */ + Reserved67_IRQn = 51, /**< Reserved interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + Reserved70_IRQn = 54, /**< Reserved interrupt */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + Reserved75_IRQn = 59, /**< Reserved interrupt */ + Reserved76_IRQn = 60, /**< Reserved interrupt */ + Reserved77_IRQn = 61, /**< Reserved interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + CAN1_IRQn = 63, /**< Controller Area Network 1 interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + PLU_IRQn = 70, /**< Programmable Logic Unit interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + EMVSIM0_IRQn = 103, /**< EMVSIM0 interrupt */ + EMVSIM1_IRQn = 104, /**< EMVSIM1 interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + DAC1_IRQn = 107, /**< Digital-to-Analog Converter 1 - General Purpose interrupt */ + DAC2_IRQn = 108, /**< 14-bit Digital-to-Analog Converter interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 118, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 119, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 120, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 121, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 122, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 123, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + QDC0_COMPARE_IRQn = 124, /**< QDC0_Compare interrupt */ + QDC0_HOME_IRQn = 125, /**< QDC0_Home interrupt */ + QDC0_WDG_SAB_IRQn = 126, /**< QDC0_WDG_IRQ/SAB interrupt */ + QDC0_IDX_IRQn = 127, /**< QDC0_IDX interrupt */ + QDC1_COMPARE_IRQn = 128, /**< QDC1_Compare interrupt */ + QDC1_HOME_IRQn = 129, /**< QDC1_Home interrupt */ + QDC1_WDG_SAB_IRQn = 130, /**< QDC1_WDG_IRQ/SAB interrupt */ + QDC1_IDX_IRQn = 131, /**< QDC1_IDX interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + ETHERNET_IRQn = 139, /**< Ethernet QoS interrupt */ + ETHERNET_PMT_IRQn = 140, /**< Ethernet QoS power management interrupt */ + ETHERNET_MACLP_IRQn = 141, /**< Ethernet QoS MAC interrupt */ + SINC_FILTER_IRQn = 142, /**< SINC Filter interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN247.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN247_SERIES +#define MCXN247_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN247_features.h" + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CAN - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Peripheral CAN1 base address */ + #define CAN1_BASE (0x500D8000u) + /** Peripheral CAN1 base address */ + #define CAN1_BASE_NS (0x400D8000u) + /** Peripheral CAN1 base pointer */ + #define CAN1 ((CAN_Type *)CAN1_BASE) + /** Peripheral CAN1 base pointer */ + #define CAN1_NS ((CAN_Type *)CAN1_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0, CAN1 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS, CAN1_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS, CAN1_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN1 base address */ + #define CAN1_BASE (0x400D8000u) + /** Peripheral CAN1 base pointer */ + #define CAN1 ((CAN_Type *)CAN1_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0, CAN1 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn, CAN1_IRQn } + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* EMVSIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EMVSIM0 base address */ + #define EMVSIM0_BASE (0x50103000u) + /** Peripheral EMVSIM0 base address */ + #define EMVSIM0_BASE_NS (0x40103000u) + /** Peripheral EMVSIM0 base pointer */ + #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) + /** Peripheral EMVSIM0 base pointer */ + #define EMVSIM0_NS ((EMVSIM_Type *)EMVSIM0_BASE_NS) + /** Peripheral EMVSIM1 base address */ + #define EMVSIM1_BASE (0x50104000u) + /** Peripheral EMVSIM1 base address */ + #define EMVSIM1_BASE_NS (0x40104000u) + /** Peripheral EMVSIM1 base pointer */ + #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) + /** Peripheral EMVSIM1 base pointer */ + #define EMVSIM1_NS ((EMVSIM_Type *)EMVSIM1_BASE_NS) + /** Array initializer of EMVSIM peripheral base addresses */ + #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } + /** Array initializer of EMVSIM peripheral base pointers */ + #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } + /** Array initializer of EMVSIM peripheral base addresses */ + #define EMVSIM_BASE_ADDRS_NS { EMVSIM0_BASE_NS, EMVSIM1_BASE_NS } + /** Array initializer of EMVSIM peripheral base pointers */ + #define EMVSIM_BASE_PTRS_NS { EMVSIM0_NS, EMVSIM1_NS } +#else + /** Peripheral EMVSIM0 base address */ + #define EMVSIM0_BASE (0x40103000u) + /** Peripheral EMVSIM0 base pointer */ + #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) + /** Peripheral EMVSIM1 base address */ + #define EMVSIM1_BASE (0x40104000u) + /** Peripheral EMVSIM1 base pointer */ + #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) + /** Array initializer of EMVSIM peripheral base addresses */ + #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } + /** Array initializer of EMVSIM peripheral base pointers */ + #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } +#endif +/** Interrupt vectors for the EMVSIM peripheral type */ +#define EMVSIM_IRQS { EMVSIM0_IRQn, EMVSIM1_IRQn } + +/* ENET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ENET0 base address */ + #define ENET0_BASE (0x50100000u) + /** Peripheral ENET0 base address */ + #define ENET0_BASE_NS (0x40100000u) + /** Peripheral ENET0 base pointer */ + #define ENET0 ((ENET_Type *)ENET0_BASE) + /** Peripheral ENET0 base pointer */ + #define ENET0_NS ((ENET_Type *)ENET0_BASE_NS) + /** Array initializer of ENET peripheral base addresses */ + #define ENET_BASE_ADDRS { ENET0_BASE } + /** Array initializer of ENET peripheral base pointers */ + #define ENET_BASE_PTRS { ENET0 } + /** Array initializer of ENET peripheral base addresses */ + #define ENET_BASE_ADDRS_NS { ENET0_BASE_NS } + /** Array initializer of ENET peripheral base pointers */ + #define ENET_BASE_PTRS_NS { ENET0_NS } +#else + /** Peripheral ENET0 base address */ + #define ENET0_BASE (0x40100000u) + /** Peripheral ENET0 base pointer */ + #define ENET0 ((ENET_Type *)ENET0_BASE) + /** Array initializer of ENET peripheral base addresses */ + #define ENET_BASE_ADDRS { ENET0_BASE } + /** Array initializer of ENET peripheral base pointers */ + #define ENET_BASE_PTRS { ENET0 } +#endif +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_IRQS { ETHERNET_IRQn } +#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn } +#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn } +/* Backward compatibility */ +#define ENET ENET0 + + +/* ERM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EVTG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x500D2000u) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE_NS (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Peripheral EVTG0 base pointer */ + #define EVTG0_NS ((EVTG_Type *)EVTG0_BASE_NS) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS_NS { EVTG0_BASE_NS } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS_NS { EVTG0_NS } +#else + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* HPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x50114000u) + /** Peripheral DAC2 base address */ + #define DAC2_BASE_NS (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Peripheral DAC2 base pointer */ + #define DAC2_NS ((HPDAC_Type *)DAC2_BASE_NS) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS_NS { DAC2_BASE_NS } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS_NS { DAC2_NS } +#else + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } +#endif + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x50112000u) + /** Peripheral DAC1 base address */ + #define DAC1_BASE_NS (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Peripheral DAC1 base pointer */ + #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OPAMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x50110000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x50113000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x50115000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PLU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x50034000u) + /** Peripheral PLU0 base address */ + #define PLU0_BASE_NS (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Peripheral PLU0 base pointer */ + #define PLU0_NS ((PLU_Type *)PLU0_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU0_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU0_NS } +#else + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* PWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Peripheral PWM1 base address */ + #define PWM1_BASE (0x500D0000u) + /** Peripheral PWM1 base address */ + #define PWM1_BASE_NS (0x400D0000u) + /** Peripheral PWM1 base pointer */ + #define PWM1 ((PWM_Type *)PWM1_BASE) + /** Peripheral PWM1 base pointer */ + #define PWM1_NS ((PWM_Type *)PWM1_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0, PWM1 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS, PWM1_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS, PWM1_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM1 base address */ + #define PWM1_BASE (0x400D0000u) + /** Peripheral PWM1 base pointer */ + #define PWM1 ((PWM_Type *)PWM1_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0, PWM1 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/* QDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x500CF000u) + /** Peripheral QDC0 base address */ + #define QDC0_BASE_NS (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC0 base pointer */ + #define QDC0_NS ((QDC_Type *)QDC0_BASE_NS) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x500D1000u) + /** Peripheral QDC1 base address */ + #define QDC1_BASE_NS (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Peripheral QDC1 base pointer */ + #define QDC1_NS ((QDC_Type *)QDC1_BASE_NS) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS_NS { QDC0_BASE_NS, QDC1_BASE_NS } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS_NS { QDC0_NS, QDC1_NS } +#else + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } +#endif +/** Interrupt vectors for the QDC peripheral type */ +#define QDC_COMPARE_IRQS { QDC0_COMPARE_IRQn, QDC1_COMPARE_IRQn } +#define QDC_HOME_IRQS { QDC0_HOME_IRQn, QDC1_HOME_IRQn } +#define QDC_WDOG_IRQS { QDC0_WDG_SAB_IRQn, QDC1_WDG_SAB_IRQn } +#define QDC_INDEX_IRQS { QDC0_IDX_IRQn, QDC1_IDX_IRQn } + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SINC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SINC0 base address */ + #define SINC0_BASE (0x50108000u) + /** Peripheral SINC0 base address */ + #define SINC0_BASE_NS (0x40108000u) + /** Peripheral SINC0 base pointer */ + #define SINC0 ((SINC_Type *)SINC0_BASE) + /** Peripheral SINC0 base pointer */ + #define SINC0_NS ((SINC_Type *)SINC0_BASE_NS) + /** Array initializer of SINC peripheral base addresses */ + #define SINC_BASE_ADDRS { SINC0_BASE } + /** Array initializer of SINC peripheral base pointers */ + #define SINC_BASE_PTRS { SINC0 } + /** Array initializer of SINC peripheral base addresses */ + #define SINC_BASE_ADDRS_NS { SINC0_BASE_NS } + /** Array initializer of SINC peripheral base pointers */ + #define SINC_BASE_PTRS_NS { SINC0_NS } +#else + /** Peripheral SINC0 base address */ + #define SINC0_BASE (0x40108000u) + /** Peripheral SINC0 base pointer */ + #define SINC0 ((SINC_Type *)SINC0_BASE) + /** Array initializer of SINC peripheral base addresses */ + #define SINC_BASE_ADDRS { SINC0_BASE } + /** Array initializer of SINC peripheral base pointers */ + #define SINC_BASE_PTRS { SINC0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* USBHS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN247_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/MCXN247_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/MCXN247_features.h new file mode 100644 index 000000000..b19d88d10 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/MCXN247_features.h @@ -0,0 +1,1072 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN247_FEATURES_H_ +#define _MCXN247_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (2) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (8) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (8) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief MCX_ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SINC availability on the SoC. */ +#define FSL_FEATURE_SOC_SINC_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (0) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (0) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EVTG module features */ + +/* @brief OPAMP support force bypass */ +#define FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) + +/* QDC module features */ + +/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ +#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0) +/* @brief Has register CTRL3. */ +#define FSL_FEATURE_QDC_HAS_CTRL3 (1) +/* @brief Has register LASTEDGE or LASTEDGEH. */ +#define FSL_FEATURE_QDC_HAS_LASTEDGE (1) +/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ +#define FSL_FEATURE_QDC_HAS_POSDPER (1) +/* @brief Has bitfiled FILT[FILT_PRSC]. */ +#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SINC module features */ + +/* @brief SINC channel count. */ +#define FSL_FEATURE_SINC_CHANNEL_COUNT (5) +/* @brief SINC CACFR register has bitfield ADMASEL. */ +#define FSL_FEATURE_SINC_CACFR_HAS_ADMASEL (1) +/* @brief SINC CACFR register has no bitfield PTMUX. */ +#define FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX (1) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (2097152) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN247_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/fsl_device_registers.h new file mode 100644 index 000000000..e0591f8fb --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/fsl_device_registers.h @@ -0,0 +1,26 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/system_MCXN247.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/system_MCXN247.c new file mode 100644 index 000000000..c106d4d3b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/system_MCXN247.c @@ -0,0 +1,141 @@ +/* +** ################################################################### +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250709 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN247 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN247 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/system_MCXN247.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/system_MCXN247.h new file mode 100644 index 000000000..53be079fe --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/system_MCXN247.h @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250709 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN247 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN247 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN247_H_ +#define _SYSTEM_MCXN247_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN247_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/variable.cmake new file mode 100644 index 000000000..7800eed8b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN247/variable.cmake @@ -0,0 +1,13 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXN247) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXN) +mcux_set_variable(soc_periph periph) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/CMakeLists.txt new file mode 100644 index 000000000..2140a5abd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core0.h new file mode 100644 index 000000000..629968be5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core0.h @@ -0,0 +1,119 @@ +/* +** ################################################################### +** Processors: MCXN526VDF_cm33_core0 +** MCXN526VKL_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN526_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN526_cm33_core0.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN526_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN526_cm33_core0 + */ + +#if !defined(MCXN526_cm33_core0_H_) /* Check if memory map has not been already included */ +#define MCXN526_cm33_core0_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_BSP32.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_ERM.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_HPDAC.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PLU.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_USB.h" +#include "PERI_USBDCD.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN526_cm33_core0_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core0_COMMON.h new file mode 100644 index 000000000..b4c891fed --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core0_COMMON.h @@ -0,0 +1,3368 @@ +/* +** ################################################################### +** Processors: MCXN526VDF_cm33_core0 +** MCXN526VKL_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN526_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN526_cm33_core0_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN526_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN526_cm33_core0 + */ + +#if !defined(MCXN526_CM33_CORE0_COMMON_H_) +#define MCXN526_CM33_CORE0_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + Reserved64_IRQn = 48, /**< Reserved interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + USB0_FS_IRQn = 50, /**< Universal Serial Bus - Full Speed interrupt */ + USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + Reserved75_IRQn = 59, /**< Reserved interrupt */ + Reserved76_IRQn = 60, /**< Reserved interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + PLU_IRQn = 70, /**< Programmable Logic Unit interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + DAC1_IRQn = 107, /**< Digital-to-Analog Converter 1 - General Purpose interrupt */ + DAC2_IRQn = 108, /**< 14-bit Digital-to-Analog Converter interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + HSCMP2_IRQn = 111, /**< High-Speed comparator2 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + Reserved140_IRQn = 124, /**< Reserved interrupt */ + Reserved141_IRQn = 125, /**< Reserved interrupt */ + Reserved142_IRQn = 126, /**< Reserved interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + BSP32_IRQn = 133, /**< CoolFlux BSP32 interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN526_cm33_core0.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN526_cm33_core0_SERIES +#define MCXN526_cm33_core0_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN526_cm33_core0_features.h" + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* BSP32 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE (0x50032000u) + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE_NS (0x40032000u) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0_NS ((BSP32_Type *)BSP32_0_BASE_NS) + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS { BSP32_0_BASE } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS { BSP32_0 } + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS_NS { BSP32_0_BASE_NS } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS_NS { BSP32_0_NS } +#else + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE (0x40032000u) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS { BSP32_0_BASE } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS { BSP32_0 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* ERM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* HPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x50114000u) + /** Peripheral DAC2 base address */ + #define DAC2_BASE_NS (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Peripheral DAC2 base pointer */ + #define DAC2_NS ((HPDAC_Type *)DAC2_BASE_NS) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS_NS { DAC2_BASE_NS } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS_NS { DAC2_NS } +#else + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } +#endif + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x50053000u) + /** Peripheral CMP2 base address */ + #define CMP2_BASE_NS (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Peripheral CMP2 base pointer */ + #define CMP2_NS ((LPCMP_Type *)CMP2_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS, CMP2_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS, CMP2_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x50112000u) + /** Peripheral DAC1 base address */ + #define DAC1_BASE_NS (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Peripheral DAC1 base pointer */ + #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OPAMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x50110000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x50113000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x50115000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PLU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x50034000u) + /** Peripheral PLU0 base address */ + #define PLU0_BASE_NS (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Peripheral PLU0 base pointer */ + #define PLU0_NS ((PLU_Type *)PLU0_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU0_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU0_NS } +#else + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* USB - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x500DD000u) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE_NS (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Peripheral USBFS0 base pointer */ + #define USBFS0_NS ((USB_Type *)USBFS0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USBFS0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USBFS0_NS } +#else + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_FS_IRQn } + +/* USBDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x500DC000u) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE_NS (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0_NS ((USBDCD_Type *)USBDCD0_BASE_NS) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS_NS { USBDCD0_BASE_NS } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS_NS { USBDCD0_NS } +#else + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } +#endif +/** Interrupt vectors for the USBDCD peripheral type */ +#define USBDCD_IRQS { USB0_DCD_IRQn } + +/* USBHS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN526_CM33_CORE0_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core0_features.h new file mode 100644 index 000000000..32b8c7f5b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core0_features.h @@ -0,0 +1,1011 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN526_cm33_core0_FEATURES_H_ +#define _MCXN526_cm33_core0_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) \ + (((x) == CMP0) ? (0) : \ + (((x) == CMP1) ? (0) : \ + (((x) == CMP2) ? (1) : (-1)))) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1048576) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* USBHSDCD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (1074503680) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074503680) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) +/* @brief Mode control of the USB Keep Alive */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN526_cm33_core0_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core1.h new file mode 100644 index 000000000..c92c4dcbf --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core1.h @@ -0,0 +1,119 @@ +/* +** ################################################################### +** Processors: MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN526_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN526_cm33_core1.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN526_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN526_cm33_core1 + */ + +#if !defined(MCXN526_cm33_core1_H_) /* Check if memory map has not been already included */ +#define MCXN526_cm33_core1_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_BSP32.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_ERM.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_HPDAC.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PLU.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_USB.h" +#include "PERI_USBDCD.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN526_cm33_core1_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core1_COMMON.h new file mode 100644 index 000000000..efb4c4ed8 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core1_COMMON.h @@ -0,0 +1,3368 @@ +/* +** ################################################################### +** Processors: MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN526_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN526_cm33_core1_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN526_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN526_cm33_core1 + */ + +#if !defined(MCXN526_CM33_CORE1_COMMON_H_) +#define MCXN526_CM33_CORE1_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + Reserved64_IRQn = 48, /**< Reserved interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + USB0_FS_IRQn = 50, /**< Universal Serial Bus - Full Speed interrupt */ + USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + Reserved75_IRQn = 59, /**< Reserved interrupt */ + Reserved76_IRQn = 60, /**< Reserved interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + PLU_IRQn = 70, /**< Programmable Logic Unit interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + DAC1_IRQn = 107, /**< Digital-to-Analog Converter 1 - General Purpose interrupt */ + DAC2_IRQn = 108, /**< 14-bit Digital-to-Analog Converter interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + HSCMP2_IRQn = 111, /**< High-Speed comparator2 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + Reserved140_IRQn = 124, /**< Reserved interrupt */ + Reserved141_IRQn = 125, /**< Reserved interrupt */ + Reserved142_IRQn = 126, /**< Reserved interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + BSP32_IRQn = 133, /**< CoolFlux BSP32 interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN526_cm33_core1.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN526_cm33_core1_SERIES +#define MCXN526_cm33_core1_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN526_cm33_core1_features.h" + +/* ADC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* BSP32 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE (0x50032000u) + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE_NS (0x40032000u) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0_NS ((BSP32_Type *)BSP32_0_BASE_NS) + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS { BSP32_0_BASE } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS { BSP32_0 } + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS_NS { BSP32_0_BASE_NS } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS_NS { BSP32_0_NS } +#else + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE (0x40032000u) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS { BSP32_0_BASE } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS { BSP32_0 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CDOG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* ERM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* HPDAC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x50114000u) + /** Peripheral DAC2 base address */ + #define DAC2_BASE_NS (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Peripheral DAC2 base pointer */ + #define DAC2_NS ((HPDAC_Type *)DAC2_BASE_NS) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS_NS { DAC2_BASE_NS } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS_NS { DAC2_NS } +#else + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } +#endif + +/* I3C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x50053000u) + /** Peripheral CMP2 base address */ + #define CMP2_BASE_NS (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Peripheral CMP2 base pointer */ + #define CMP2_NS ((LPCMP_Type *)CMP2_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS, CMP2_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS, CMP2_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x50112000u) + /** Peripheral DAC1 base address */ + #define DAC1_BASE_NS (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Peripheral DAC1 base pointer */ + #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OPAMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x50110000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x50113000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x50115000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PINT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PLU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x50034000u) + /** Peripheral PLU0 base address */ + #define PLU0_BASE_NS (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Peripheral PLU0 base pointer */ + #define PLU0_NS ((PLU_Type *)PLU0_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU0_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU0_NS } +#else + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* RTC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* USB - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x500DD000u) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE_NS (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Peripheral USBFS0 base pointer */ + #define USBFS0_NS ((USB_Type *)USBFS0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USBFS0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USBFS0_NS } +#else + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_FS_IRQn } + +/* USBDCD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x500DC000u) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE_NS (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0_NS ((USBDCD_Type *)USBDCD0_BASE_NS) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS_NS { USBDCD0_BASE_NS } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS_NS { USBDCD0_NS } +#else + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } +#endif +/** Interrupt vectors for the USBDCD peripheral type */ +#define USBDCD_IRQS { USB0_DCD_IRQn } + +/* USBHS - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN526_CM33_CORE1_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core1_features.h new file mode 100644 index 000000000..155d21df7 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/MCXN526_cm33_core1_features.h @@ -0,0 +1,1004 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN526_cm33_core1_FEATURES_H_ +#define _MCXN526_cm33_core1_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) \ + (((x) == CMP0) ? (0) : \ + (((x) == CMP1) ? (0) : \ + (((x) == CMP2) ? (1) : (-1)))) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1048576) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* USBHSDCD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (1074503680) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074503680) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) +/* @brief Mode control of the USB Keep Alive */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN526_cm33_core1_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/cm33_core0/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/cm33_core0/variable.cmake new file mode 100644 index 000000000..292d91c99 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/cm33_core0/variable.cmake @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core0) +mcux_set_variable(multicore_foldername cm33_core0) +mcux_set_variable(multicore_sec_core_foldername cm33_core1) \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/cm33_core1/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/cm33_core1/variable.cmake new file mode 100644 index 000000000..b38aabbc1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/cm33_core1/variable.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core1) +mcux_set_variable(multicore_foldername cm33_core1) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/fsl_device_registers.h new file mode 100644 index 000000000..ae5373bb5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/fsl_device_registers.h @@ -0,0 +1,28 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core0.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core0.c new file mode 100644 index 000000000..372285604 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core0.c @@ -0,0 +1,140 @@ +/* +** ################################################################### +** Processors: MCXN526VDF_cm33_core0 +** MCXN526VKL_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN526_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN526_cm33_core0 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core0.h new file mode 100644 index 000000000..65c06f984 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core0.h @@ -0,0 +1,109 @@ +/* +** ################################################################### +** Processors: MCXN526VDF_cm33_core0 +** MCXN526VKL_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN526_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN526_cm33_core0 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN526_cm33_core0_H_ +#define _SYSTEM_MCXN526_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN526_cm33_core0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core1.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core1.c new file mode 100644 index 000000000..e837f5d19 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core1.c @@ -0,0 +1,134 @@ +/* +** ################################################################### +** Processors: MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN526_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN526_cm33_core1 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core1.h new file mode 100644 index 000000000..55453c607 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/system_MCXN526_cm33_core1.h @@ -0,0 +1,109 @@ +/* +** ################################################################### +** Processors: MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN526_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN526_cm33_core1 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN526_cm33_core1_H_ +#define _SYSTEM_MCXN526_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN526_cm33_core1_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/variable.cmake new file mode 100644 index 000000000..09d6ba0d2 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN526/variable.cmake @@ -0,0 +1,19 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXN526) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXN) +mcux_set_variable(soc_periph periph) + +if (NOT DEFINED core_id) + message(FATAL_ERROR "Please specify core_id for multicore device.") +endif() + +include(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN526/${core_id}/variable.cmake) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/CMakeLists.txt new file mode 100644 index 000000000..2140a5abd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core0.h new file mode 100644 index 000000000..19a4ed49a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core0.h @@ -0,0 +1,120 @@ +/* +** ################################################################### +** Processors: MCXN527VAB_cm33_core0 +** MCXN527VDF_cm33_core0 +** MCXN527VKL_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN527_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN527_cm33_core0.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN527_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN527_cm33_core0 + */ + +#if !defined(MCXN527_cm33_core0_H_) /* Check if memory map has not been already included */ +#define MCXN527_cm33_core0_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_BSP32.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_ERM.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_HPDAC.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PLU.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_USB.h" +#include "PERI_USBDCD.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN527_cm33_core0_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core0_COMMON.h new file mode 100644 index 000000000..f3c5427db --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core0_COMMON.h @@ -0,0 +1,3369 @@ +/* +** ################################################################### +** Processors: MCXN527VAB_cm33_core0 +** MCXN527VDF_cm33_core0 +** MCXN527VKL_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN527_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN527_cm33_core0_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN527_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN527_cm33_core0 + */ + +#if !defined(MCXN527_CM33_CORE0_COMMON_H_) +#define MCXN527_CM33_CORE0_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + Reserved64_IRQn = 48, /**< Reserved interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + USB0_FS_IRQn = 50, /**< Universal Serial Bus - Full Speed interrupt */ + USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + Reserved75_IRQn = 59, /**< Reserved interrupt */ + Reserved76_IRQn = 60, /**< Reserved interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + PLU_IRQn = 70, /**< Programmable Logic Unit interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + DAC1_IRQn = 107, /**< Digital-to-Analog Converter 1 - General Purpose interrupt */ + DAC2_IRQn = 108, /**< 14-bit Digital-to-Analog Converter interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + HSCMP2_IRQn = 111, /**< High-Speed comparator2 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + Reserved140_IRQn = 124, /**< Reserved interrupt */ + Reserved141_IRQn = 125, /**< Reserved interrupt */ + Reserved142_IRQn = 126, /**< Reserved interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + BSP32_IRQn = 133, /**< CoolFlux BSP32 interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN527_cm33_core0.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN527_cm33_core0_SERIES +#define MCXN527_cm33_core0_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN527_cm33_core0_features.h" + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* BSP32 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE (0x50032000u) + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE_NS (0x40032000u) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0_NS ((BSP32_Type *)BSP32_0_BASE_NS) + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS { BSP32_0_BASE } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS { BSP32_0 } + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS_NS { BSP32_0_BASE_NS } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS_NS { BSP32_0_NS } +#else + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE (0x40032000u) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS { BSP32_0_BASE } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS { BSP32_0 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* ERM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* HPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x50114000u) + /** Peripheral DAC2 base address */ + #define DAC2_BASE_NS (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Peripheral DAC2 base pointer */ + #define DAC2_NS ((HPDAC_Type *)DAC2_BASE_NS) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS_NS { DAC2_BASE_NS } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS_NS { DAC2_NS } +#else + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } +#endif + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x50053000u) + /** Peripheral CMP2 base address */ + #define CMP2_BASE_NS (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Peripheral CMP2 base pointer */ + #define CMP2_NS ((LPCMP_Type *)CMP2_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS, CMP2_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS, CMP2_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x50112000u) + /** Peripheral DAC1 base address */ + #define DAC1_BASE_NS (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Peripheral DAC1 base pointer */ + #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OPAMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x50110000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x50113000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x50115000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PLU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x50034000u) + /** Peripheral PLU0 base address */ + #define PLU0_BASE_NS (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Peripheral PLU0 base pointer */ + #define PLU0_NS ((PLU_Type *)PLU0_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU0_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU0_NS } +#else + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* USB - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x500DD000u) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE_NS (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Peripheral USBFS0 base pointer */ + #define USBFS0_NS ((USB_Type *)USBFS0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USBFS0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USBFS0_NS } +#else + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_FS_IRQn } + +/* USBDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x500DC000u) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE_NS (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0_NS ((USBDCD_Type *)USBDCD0_BASE_NS) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS_NS { USBDCD0_BASE_NS } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS_NS { USBDCD0_NS } +#else + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } +#endif +/** Interrupt vectors for the USBDCD peripheral type */ +#define USBDCD_IRQS { USB0_DCD_IRQn } + +/* USBHS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN527_CM33_CORE0_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core0_features.h new file mode 100644 index 000000000..9db3693a7 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core0_features.h @@ -0,0 +1,1011 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN527_cm33_core0_FEATURES_H_ +#define _MCXN527_cm33_core0_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) \ + (((x) == CMP0) ? (0) : \ + (((x) == CMP1) ? (0) : \ + (((x) == CMP2) ? (1) : (-1)))) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (2097152) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* USBHSDCD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (1074503680) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074503680) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) +/* @brief Mode control of the USB Keep Alive */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN527_cm33_core0_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core1.h new file mode 100644 index 000000000..3e04512d4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core1.h @@ -0,0 +1,120 @@ +/* +** ################################################################### +** Processors: MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN527_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN527_cm33_core1.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN527_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN527_cm33_core1 + */ + +#if !defined(MCXN527_cm33_core1_H_) /* Check if memory map has not been already included */ +#define MCXN527_cm33_core1_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_BSP32.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_ERM.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_HPDAC.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PLU.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_USB.h" +#include "PERI_USBDCD.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN527_cm33_core1_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core1_COMMON.h new file mode 100644 index 000000000..7b7be702c --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core1_COMMON.h @@ -0,0 +1,3369 @@ +/* +** ################################################################### +** Processors: MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN527_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN527_cm33_core1_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN527_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN527_cm33_core1 + */ + +#if !defined(MCXN527_CM33_CORE1_COMMON_H_) +#define MCXN527_CM33_CORE1_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + Reserved64_IRQn = 48, /**< Reserved interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + USB0_FS_IRQn = 50, /**< Universal Serial Bus - Full Speed interrupt */ + USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + Reserved75_IRQn = 59, /**< Reserved interrupt */ + Reserved76_IRQn = 60, /**< Reserved interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + PLU_IRQn = 70, /**< Programmable Logic Unit interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + DAC1_IRQn = 107, /**< Digital-to-Analog Converter 1 - General Purpose interrupt */ + DAC2_IRQn = 108, /**< 14-bit Digital-to-Analog Converter interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + HSCMP2_IRQn = 111, /**< High-Speed comparator2 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + Reserved140_IRQn = 124, /**< Reserved interrupt */ + Reserved141_IRQn = 125, /**< Reserved interrupt */ + Reserved142_IRQn = 126, /**< Reserved interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + BSP32_IRQn = 133, /**< CoolFlux BSP32 interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN527_cm33_core1.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN527_cm33_core1_SERIES +#define MCXN527_cm33_core1_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN527_cm33_core1_features.h" + +/* ADC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* BSP32 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE (0x50032000u) + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE_NS (0x40032000u) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0_NS ((BSP32_Type *)BSP32_0_BASE_NS) + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS { BSP32_0_BASE } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS { BSP32_0 } + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS_NS { BSP32_0_BASE_NS } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS_NS { BSP32_0_NS } +#else + /** Peripheral BSP32_0 base address */ + #define BSP32_0_BASE (0x40032000u) + /** Peripheral BSP32_0 base pointer */ + #define BSP32_0 ((BSP32_Type *)BSP32_0_BASE) + /** Array initializer of BSP32 peripheral base addresses */ + #define BSP32_BASE_ADDRS { BSP32_0_BASE } + /** Array initializer of BSP32 peripheral base pointers */ + #define BSP32_BASE_PTRS { BSP32_0 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CDOG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* ERM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* HPDAC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x50114000u) + /** Peripheral DAC2 base address */ + #define DAC2_BASE_NS (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Peripheral DAC2 base pointer */ + #define DAC2_NS ((HPDAC_Type *)DAC2_BASE_NS) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS_NS { DAC2_BASE_NS } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS_NS { DAC2_NS } +#else + /** Peripheral DAC2 base address */ + #define DAC2_BASE (0x40114000u) + /** Peripheral DAC2 base pointer */ + #define DAC2 ((HPDAC_Type *)DAC2_BASE) + /** Array initializer of HPDAC peripheral base addresses */ + #define HPDAC_BASE_ADDRS { DAC2_BASE } + /** Array initializer of HPDAC peripheral base pointers */ + #define HPDAC_BASE_PTRS { DAC2 } +#endif + +/* I3C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x50053000u) + /** Peripheral CMP2 base address */ + #define CMP2_BASE_NS (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Peripheral CMP2 base pointer */ + #define CMP2_NS ((LPCMP_Type *)CMP2_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS, CMP2_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS, CMP2_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x50112000u) + /** Peripheral DAC1 base address */ + #define DAC1_BASE_NS (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Peripheral DAC1 base pointer */ + #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OPAMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x50110000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x50113000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x50115000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PINT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PLU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x50034000u) + /** Peripheral PLU0 base address */ + #define PLU0_BASE_NS (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Peripheral PLU0 base pointer */ + #define PLU0_NS ((PLU_Type *)PLU0_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU0_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU0_NS } +#else + /** Peripheral PLU0 base address */ + #define PLU0_BASE (0x40034000u) + /** Peripheral PLU0 base pointer */ + #define PLU0 ((PLU_Type *)PLU0_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU0_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* RTC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* USB - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x500DD000u) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE_NS (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Peripheral USBFS0 base pointer */ + #define USBFS0_NS ((USB_Type *)USBFS0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USBFS0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USBFS0_NS } +#else + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_FS_IRQn } + +/* USBDCD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x500DC000u) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE_NS (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0_NS ((USBDCD_Type *)USBDCD0_BASE_NS) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS_NS { USBDCD0_BASE_NS } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS_NS { USBDCD0_NS } +#else + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } +#endif +/** Interrupt vectors for the USBDCD peripheral type */ +#define USBDCD_IRQS { USB0_DCD_IRQn } + +/* USBHS - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN527_CM33_CORE1_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core1_features.h new file mode 100644 index 000000000..17ffe71ba --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/MCXN527_cm33_core1_features.h @@ -0,0 +1,1004 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN527_cm33_core1_FEATURES_H_ +#define _MCXN527_cm33_core1_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) \ + (((x) == CMP0) ? (0) : \ + (((x) == CMP1) ? (0) : \ + (((x) == CMP2) ? (1) : (-1)))) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (2097152) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* USBHSDCD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (1074503680) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074503680) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) +/* @brief Mode control of the USB Keep Alive */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN527_cm33_core1_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/cm33_core0/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/cm33_core0/variable.cmake new file mode 100644 index 000000000..292d91c99 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/cm33_core0/variable.cmake @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core0) +mcux_set_variable(multicore_foldername cm33_core0) +mcux_set_variable(multicore_sec_core_foldername cm33_core1) \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/cm33_core1/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/cm33_core1/variable.cmake new file mode 100644 index 000000000..b38aabbc1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/cm33_core1/variable.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core1) +mcux_set_variable(multicore_foldername cm33_core1) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/fsl_device_registers.h new file mode 100644 index 000000000..7d62d0157 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/fsl_device_registers.h @@ -0,0 +1,28 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core0.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core0.c new file mode 100644 index 000000000..012d0a9cf --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core0.c @@ -0,0 +1,141 @@ +/* +** ################################################################### +** Processors: MCXN527VAB_cm33_core0 +** MCXN527VDF_cm33_core0 +** MCXN527VKL_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250811 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN527_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN527_cm33_core0 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core0.h new file mode 100644 index 000000000..7136070a4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core0.h @@ -0,0 +1,110 @@ +/* +** ################################################################### +** Processors: MCXN527VAB_cm33_core0 +** MCXN527VDF_cm33_core0 +** MCXN527VKL_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250811 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN527_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN527_cm33_core0 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN527_cm33_core0_H_ +#define _SYSTEM_MCXN527_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN527_cm33_core0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core1.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core1.c new file mode 100644 index 000000000..828f9ec34 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core1.c @@ -0,0 +1,135 @@ +/* +** ################################################################### +** Processors: MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250811 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN527_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN527_cm33_core1 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core1.h new file mode 100644 index 000000000..783031c39 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/system_MCXN527_cm33_core1.h @@ -0,0 +1,110 @@ +/* +** ################################################################### +** Processors: MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250811 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN527_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN527_cm33_core1 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN527_cm33_core1_H_ +#define _SYSTEM_MCXN527_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN527_cm33_core1_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/variable.cmake new file mode 100644 index 000000000..17b30abbc --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN527/variable.cmake @@ -0,0 +1,19 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXN527) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXN) +mcux_set_variable(soc_periph periph) + +if (NOT DEFINED core_id) + message(FATAL_ERROR "Please specify core_id for multicore device.") +endif() + +include(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN527/${core_id}/variable.cmake) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/CMakeLists.txt new file mode 100644 index 000000000..2140a5abd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core0.h new file mode 100644 index 000000000..d9d855938 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core0.h @@ -0,0 +1,121 @@ +/* +** ################################################################### +** Processors: MCXN536VAB_cm33_core0 +** MCXN536VDF_cm33_core0 +** MCXN536VKL_cm33_core0 +** MCXN536VPB_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN536_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN536_cm33_core0.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN536_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN536_cm33_core0 + */ + +#if !defined(MCXN536_cm33_core0_H_) /* Check if memory map has not been already included */ +#define MCXN536_cm33_core0_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_ERM.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_I2S.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PDM.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_TSI.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN536_cm33_core0_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core0_COMMON.h new file mode 100644 index 000000000..91aaf1c4f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core0_COMMON.h @@ -0,0 +1,3384 @@ +/* +** ################################################################### +** Processors: MCXN536VAB_cm33_core0 +** MCXN536VDF_cm33_core0 +** MCXN536VKL_cm33_core0 +** MCXN536VPB_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN536_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN536_cm33_core0_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN536_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN536_cm33_core0 + */ + +#if !defined(MCXN536_CM33_CORE0_COMMON_H_) +#define MCXN536_CM33_CORE0_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + Reserved66_IRQn = 50, /**< Reserved interrupt */ + Reserved67_IRQn = 51, /**< Reserved interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ + SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + TSI_END_OF_SCAN_IRQn = 101, /**< TSI End of Scan interrupt */ + TSI_OUT_OF_SCAN_IRQn = 102, /**< TSI Out of Scan interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + Reserved124_IRQn = 108, /**< Reserved interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + HSCMP2_IRQn = 111, /**< High-Speed comparator2 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + Reserved140_IRQn = 124, /**< Reserved interrupt */ + Reserved141_IRQn = 125, /**< Reserved interrupt */ + Reserved142_IRQn = 126, /**< Reserved interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN536_cm33_core0.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN536_cm33_core0_SERIES +#define MCXN536_cm33_core0_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN536_cm33_core0_features.h" + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CAN - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* ERM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x50106000u) + /** Peripheral SAI0 base address */ + #define SAI0_BASE_NS (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI0 base pointer */ + #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x50107000u) + /** Peripheral SAI1 base address */ + #define SAI1_BASE_NS (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI1 base pointer */ + #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } +#else + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } +#define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x50053000u) + /** Peripheral CMP2 base address */ + #define CMP2_BASE_NS (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Peripheral CMP2 base pointer */ + #define CMP2_NS ((LPCMP_Type *)CMP2_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS, CMP2_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS, CMP2_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OPAMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x50110000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x50113000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x50115000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PDM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PDM base address */ + #define PDM_BASE (0x5010C000u) + /** Peripheral PDM base address */ + #define PDM_BASE_NS (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Peripheral PDM base pointer */ + #define PDM_NS ((PDM_Type *)PDM_BASE_NS) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS_NS { PDM_NS } +#else + /** Peripheral PDM base address */ + #define PDM_BASE (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } +#endif +/** Interrupt vectors for the PDM peripheral type */ +#define PDM_IRQS { PDM_EVENT_IRQn } + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* PWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TSI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x50050000u) + /** Peripheral TSI0 base address */ + #define TSI0_BASE_NS (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Peripheral TSI0 base pointer */ + #define TSI0_NS ((TSI_Type *)TSI0_BASE_NS) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS_NS { TSI0_BASE_NS } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS_NS { TSI0_NS } +#else + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } +#endif + +/* USBHS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN536_CM33_CORE0_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core0_features.h new file mode 100644 index 000000000..59595a5d6 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core0_features.h @@ -0,0 +1,1165 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN536_cm33_core0_FEATURES_H_ +#define _MCXN536_cm33_core0_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) \ + (((x) == CMP0) ? (0) : \ + (((x) == CMP1) ? (0) : \ + (((x) == CMP2) ? (1) : (-1)))) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1048576) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* TSI module features */ + +/* @brief TSI Version */ +#define FSL_FEATURE_TSI_VERSION (6U) +/* @brief TSI Channel Count */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN536_cm33_core0_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core1.h new file mode 100644 index 000000000..a787d05a4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core1.h @@ -0,0 +1,121 @@ +/* +** ################################################################### +** Processors: MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN536_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN536_cm33_core1.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN536_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN536_cm33_core1 + */ + +#if !defined(MCXN536_cm33_core1_H_) /* Check if memory map has not been already included */ +#define MCXN536_cm33_core1_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_ERM.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_I2S.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PDM.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_TSI.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN536_cm33_core1_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core1_COMMON.h new file mode 100644 index 000000000..8fbc1a409 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core1_COMMON.h @@ -0,0 +1,3384 @@ +/* +** ################################################################### +** Processors: MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN536_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN536_cm33_core1_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN536_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN536_cm33_core1 + */ + +#if !defined(MCXN536_CM33_CORE1_COMMON_H_) +#define MCXN536_CM33_CORE1_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + Reserved66_IRQn = 50, /**< Reserved interrupt */ + Reserved67_IRQn = 51, /**< Reserved interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ + SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + TSI_END_OF_SCAN_IRQn = 101, /**< TSI End of Scan interrupt */ + TSI_OUT_OF_SCAN_IRQn = 102, /**< TSI Out of Scan interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + Reserved124_IRQn = 108, /**< Reserved interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + HSCMP2_IRQn = 111, /**< High-Speed comparator2 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + Reserved140_IRQn = 124, /**< Reserved interrupt */ + Reserved141_IRQn = 125, /**< Reserved interrupt */ + Reserved142_IRQn = 126, /**< Reserved interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN536_cm33_core1.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN536_cm33_core1_SERIES +#define MCXN536_cm33_core1_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN536_cm33_core1_features.h" + +/* ADC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CAN - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* ERM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* I2S - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x50106000u) + /** Peripheral SAI0 base address */ + #define SAI0_BASE_NS (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI0 base pointer */ + #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x50107000u) + /** Peripheral SAI1 base address */ + #define SAI1_BASE_NS (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI1 base pointer */ + #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } +#else + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } +#define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } + +/* I3C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x50053000u) + /** Peripheral CMP2 base address */ + #define CMP2_BASE_NS (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Peripheral CMP2 base pointer */ + #define CMP2_NS ((LPCMP_Type *)CMP2_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS, CMP2_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS, CMP2_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OPAMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x50110000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x50113000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x50115000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PDM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PDM base address */ + #define PDM_BASE (0x5010C000u) + /** Peripheral PDM base address */ + #define PDM_BASE_NS (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Peripheral PDM base pointer */ + #define PDM_NS ((PDM_Type *)PDM_BASE_NS) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS_NS { PDM_NS } +#else + /** Peripheral PDM base address */ + #define PDM_BASE (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } +#endif +/** Interrupt vectors for the PDM peripheral type */ +#define PDM_IRQS { PDM_EVENT_IRQn } + +/* PINT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* PWM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TSI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x50050000u) + /** Peripheral TSI0 base address */ + #define TSI0_BASE_NS (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Peripheral TSI0 base pointer */ + #define TSI0_NS ((TSI_Type *)TSI0_BASE_NS) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS_NS { TSI0_BASE_NS } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS_NS { TSI0_NS } +#else + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } +#endif + +/* USBHS - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN536_CM33_CORE1_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core1_features.h new file mode 100644 index 000000000..c5bd0a496 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/MCXN536_cm33_core1_features.h @@ -0,0 +1,1158 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN536_cm33_core1_FEATURES_H_ +#define _MCXN536_cm33_core1_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) \ + (((x) == CMP0) ? (0) : \ + (((x) == CMP1) ? (0) : \ + (((x) == CMP2) ? (1) : (-1)))) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1048576) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* TSI module features */ + +/* @brief TSI Version */ +#define FSL_FEATURE_TSI_VERSION (6U) +/* @brief TSI Channel Count */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN536_cm33_core1_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/cm33_core0/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/cm33_core0/variable.cmake new file mode 100644 index 000000000..292d91c99 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/cm33_core0/variable.cmake @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core0) +mcux_set_variable(multicore_foldername cm33_core0) +mcux_set_variable(multicore_sec_core_foldername cm33_core1) \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/cm33_core1/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/cm33_core1/variable.cmake new file mode 100644 index 000000000..b38aabbc1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/cm33_core1/variable.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core1) +mcux_set_variable(multicore_foldername cm33_core1) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/fsl_device_registers.h new file mode 100644 index 000000000..10bb0e1b5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/fsl_device_registers.h @@ -0,0 +1,28 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core0.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core0.c new file mode 100644 index 000000000..3408683e0 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core0.c @@ -0,0 +1,142 @@ +/* +** ################################################################### +** Processors: MCXN536VAB_cm33_core0 +** MCXN536VDF_cm33_core0 +** MCXN536VKL_cm33_core0 +** MCXN536VPB_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN536_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN536_cm33_core0 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core0.h new file mode 100644 index 000000000..90a927830 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core0.h @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: MCXN536VAB_cm33_core0 +** MCXN536VDF_cm33_core0 +** MCXN536VKL_cm33_core0 +** MCXN536VPB_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN536_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN536_cm33_core0 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN536_cm33_core0_H_ +#define _SYSTEM_MCXN536_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN536_cm33_core0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core1.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core1.c new file mode 100644 index 000000000..6b071512d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core1.c @@ -0,0 +1,136 @@ +/* +** ################################################################### +** Processors: MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN536_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN536_cm33_core1 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core1.h new file mode 100644 index 000000000..921cfadc1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/system_MCXN536_cm33_core1.h @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN536_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN536_cm33_core1 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN536_cm33_core1_H_ +#define _SYSTEM_MCXN536_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN536_cm33_core1_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/variable.cmake new file mode 100644 index 000000000..a5f038ebb --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN536/variable.cmake @@ -0,0 +1,19 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXN536) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXN) +mcux_set_variable(soc_periph periph) + +if (NOT DEFINED core_id) + message(FATAL_ERROR "Please specify core_id for multicore device.") +endif() + +include(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN536/${core_id}/variable.cmake) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/CMakeLists.txt new file mode 100644 index 000000000..2140a5abd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core0.h new file mode 100644 index 000000000..d6e3ed58d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core0.h @@ -0,0 +1,121 @@ +/* +** ################################################################### +** Processors: MCXN537VAB_cm33_core0 +** MCXN537VDF_cm33_core0 +** MCXN537VKL_cm33_core0 +** MCXN537VPB_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN537_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN537_cm33_core0.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN537_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN537_cm33_core0 + */ + +#if !defined(MCXN537_cm33_core0_H_) /* Check if memory map has not been already included */ +#define MCXN537_cm33_core0_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_ERM.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_I2S.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PDM.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_TSI.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN537_cm33_core0_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core0_COMMON.h new file mode 100644 index 000000000..58518a0ea --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core0_COMMON.h @@ -0,0 +1,3384 @@ +/* +** ################################################################### +** Processors: MCXN537VAB_cm33_core0 +** MCXN537VDF_cm33_core0 +** MCXN537VKL_cm33_core0 +** MCXN537VPB_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN537_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN537_cm33_core0_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN537_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN537_cm33_core0 + */ + +#if !defined(MCXN537_CM33_CORE0_COMMON_H_) +#define MCXN537_CM33_CORE0_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + Reserved66_IRQn = 50, /**< Reserved interrupt */ + Reserved67_IRQn = 51, /**< Reserved interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ + SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + TSI_END_OF_SCAN_IRQn = 101, /**< TSI End of Scan interrupt */ + TSI_OUT_OF_SCAN_IRQn = 102, /**< TSI Out of Scan interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + Reserved124_IRQn = 108, /**< Reserved interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + HSCMP2_IRQn = 111, /**< High-Speed comparator2 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + Reserved140_IRQn = 124, /**< Reserved interrupt */ + Reserved141_IRQn = 125, /**< Reserved interrupt */ + Reserved142_IRQn = 126, /**< Reserved interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN537_cm33_core0.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN537_cm33_core0_SERIES +#define MCXN537_cm33_core0_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN537_cm33_core0_features.h" + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CAN - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* ERM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x50106000u) + /** Peripheral SAI0 base address */ + #define SAI0_BASE_NS (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI0 base pointer */ + #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x50107000u) + /** Peripheral SAI1 base address */ + #define SAI1_BASE_NS (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI1 base pointer */ + #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } +#else + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } +#define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x50053000u) + /** Peripheral CMP2 base address */ + #define CMP2_BASE_NS (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Peripheral CMP2 base pointer */ + #define CMP2_NS ((LPCMP_Type *)CMP2_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS, CMP2_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS, CMP2_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OPAMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x50110000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x50113000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x50115000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PDM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PDM base address */ + #define PDM_BASE (0x5010C000u) + /** Peripheral PDM base address */ + #define PDM_BASE_NS (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Peripheral PDM base pointer */ + #define PDM_NS ((PDM_Type *)PDM_BASE_NS) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS_NS { PDM_NS } +#else + /** Peripheral PDM base address */ + #define PDM_BASE (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } +#endif +/** Interrupt vectors for the PDM peripheral type */ +#define PDM_IRQS { PDM_EVENT_IRQn } + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* PWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TSI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x50050000u) + /** Peripheral TSI0 base address */ + #define TSI0_BASE_NS (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Peripheral TSI0 base pointer */ + #define TSI0_NS ((TSI_Type *)TSI0_BASE_NS) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS_NS { TSI0_BASE_NS } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS_NS { TSI0_NS } +#else + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } +#endif + +/* USBHS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN537_CM33_CORE0_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core0_features.h new file mode 100644 index 000000000..38875884e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core0_features.h @@ -0,0 +1,1165 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN537_cm33_core0_FEATURES_H_ +#define _MCXN537_cm33_core0_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) \ + (((x) == CMP0) ? (0) : \ + (((x) == CMP1) ? (0) : \ + (((x) == CMP2) ? (1) : (-1)))) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (2097152) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* TSI module features */ + +/* @brief TSI Version */ +#define FSL_FEATURE_TSI_VERSION (6U) +/* @brief TSI Channel Count */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN537_cm33_core0_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core1.h new file mode 100644 index 000000000..ccc4421b4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core1.h @@ -0,0 +1,121 @@ +/* +** ################################################################### +** Processors: MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN537_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN537_cm33_core1.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN537_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN537_cm33_core1 + */ + +#if !defined(MCXN537_cm33_core1_H_) /* Check if memory map has not been already included */ +#define MCXN537_cm33_core1_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_ERM.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_I2S.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OPAMP.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PDM.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_PWM.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_TSI.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN537_cm33_core1_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core1_COMMON.h new file mode 100644 index 000000000..f9efb5d5e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core1_COMMON.h @@ -0,0 +1,3384 @@ +/* +** ################################################################### +** Processors: MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN537_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN537_cm33_core1_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN537_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN537_cm33_core1 + */ + +#if !defined(MCXN537_CM33_CORE1_COMMON_H_) +#define MCXN537_CM33_CORE1_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + Reserved66_IRQn = 50, /**< Reserved interrupt */ + Reserved67_IRQn = 51, /**< Reserved interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ + SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + TSI_END_OF_SCAN_IRQn = 101, /**< TSI End of Scan interrupt */ + TSI_OUT_OF_SCAN_IRQn = 102, /**< TSI Out of Scan interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + Reserved124_IRQn = 108, /**< Reserved interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + HSCMP2_IRQn = 111, /**< High-Speed comparator2 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + Reserved140_IRQn = 124, /**< Reserved interrupt */ + Reserved141_IRQn = 125, /**< Reserved interrupt */ + Reserved142_IRQn = 126, /**< Reserved interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN537_cm33_core1.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN537_cm33_core1_SERIES +#define MCXN537_cm33_core1_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN537_cm33_core1_features.h" + +/* ADC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CAN - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* ERM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* I2S - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x50106000u) + /** Peripheral SAI0 base address */ + #define SAI0_BASE_NS (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI0 base pointer */ + #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x50107000u) + /** Peripheral SAI1 base address */ + #define SAI1_BASE_NS (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI1 base pointer */ + #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } +#else + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } +#define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } + +/* I3C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x50053000u) + /** Peripheral CMP2 base address */ + #define CMP2_BASE_NS (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Peripheral CMP2 base pointer */ + #define CMP2_NS ((LPCMP_Type *)CMP2_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS, CMP2_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS, CMP2_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP2 base address */ + #define CMP2_BASE (0x40053000u) + /** Peripheral CMP2 base pointer */ + #define CMP2 ((LPCMP_Type *)CMP2_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1, CMP2 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OPAMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x50110000u) + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE_NS (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0_NS ((OPAMP_Type *)OPAMP0_BASE_NS) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x50113000u) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE_NS (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1_NS ((OPAMP_Type *)OPAMP1_BASE_NS) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x50115000u) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE_NS (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2_NS ((OPAMP_Type *)OPAMP2_BASE_NS) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS_NS { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS_NS { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS } +#else + /** Peripheral OPAMP0 base address */ + #define OPAMP0_BASE (0x40110000u) + /** Peripheral OPAMP0 base pointer */ + #define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) + /** Peripheral OPAMP1 base address */ + #define OPAMP1_BASE (0x40113000u) + /** Peripheral OPAMP1 base pointer */ + #define OPAMP1 ((OPAMP_Type *)OPAMP1_BASE) + /** Peripheral OPAMP2 base address */ + #define OPAMP2_BASE (0x40115000u) + /** Peripheral OPAMP2 base pointer */ + #define OPAMP2 ((OPAMP_Type *)OPAMP2_BASE) + /** Array initializer of OPAMP peripheral base addresses */ + #define OPAMP_BASE_ADDRS { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE } + /** Array initializer of OPAMP peripheral base pointers */ + #define OPAMP_BASE_PTRS { OPAMP0, OPAMP1, OPAMP2 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PDM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PDM base address */ + #define PDM_BASE (0x5010C000u) + /** Peripheral PDM base address */ + #define PDM_BASE_NS (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Peripheral PDM base pointer */ + #define PDM_NS ((PDM_Type *)PDM_BASE_NS) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS_NS { PDM_NS } +#else + /** Peripheral PDM base address */ + #define PDM_BASE (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } +#endif +/** Interrupt vectors for the PDM peripheral type */ +#define PDM_IRQS { PDM_EVENT_IRQn } + +/* PINT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* PWM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn } + +/* RTC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TSI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x50050000u) + /** Peripheral TSI0 base address */ + #define TSI0_BASE_NS (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Peripheral TSI0 base pointer */ + #define TSI0_NS ((TSI_Type *)TSI0_BASE_NS) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS_NS { TSI0_BASE_NS } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS_NS { TSI0_NS } +#else + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } +#endif + +/* USBHS - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN537_CM33_CORE1_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core1_features.h new file mode 100644 index 000000000..96190496a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/MCXN537_cm33_core1_features.h @@ -0,0 +1,1158 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN537_cm33_core1_FEATURES_H_ +#define _MCXN537_cm33_core1_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (1) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) \ + (((x) == CMP0) ? (0) : \ + (((x) == CMP1) ? (0) : \ + (((x) == CMP2) ? (1) : (-1)))) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (2097152) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* TSI module features */ + +/* @brief TSI Version */ +#define FSL_FEATURE_TSI_VERSION (6U) +/* @brief TSI Channel Count */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN537_cm33_core1_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/cm33_core0/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/cm33_core0/variable.cmake new file mode 100644 index 000000000..292d91c99 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/cm33_core0/variable.cmake @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core0) +mcux_set_variable(multicore_foldername cm33_core0) +mcux_set_variable(multicore_sec_core_foldername cm33_core1) \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/cm33_core1/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/cm33_core1/variable.cmake new file mode 100644 index 000000000..b38aabbc1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/cm33_core1/variable.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core1) +mcux_set_variable(multicore_foldername cm33_core1) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/fsl_device_registers.h new file mode 100644 index 000000000..20357604a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/fsl_device_registers.h @@ -0,0 +1,28 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core0.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core0.c new file mode 100644 index 000000000..634f4bfbd --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core0.c @@ -0,0 +1,142 @@ +/* +** ################################################################### +** Processors: MCXN537VAB_cm33_core0 +** MCXN537VDF_cm33_core0 +** MCXN537VKL_cm33_core0 +** MCXN537VPB_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN537_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN537_cm33_core0 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core0.h new file mode 100644 index 000000000..ea186fe9d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core0.h @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: MCXN537VAB_cm33_core0 +** MCXN537VDF_cm33_core0 +** MCXN537VKL_cm33_core0 +** MCXN537VPB_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN537_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN537_cm33_core0 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN537_cm33_core0_H_ +#define _SYSTEM_MCXN537_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN537_cm33_core0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core1.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core1.c new file mode 100644 index 000000000..908d1b95e --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core1.c @@ -0,0 +1,136 @@ +/* +** ################################################################### +** Processors: MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN537_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN537_cm33_core1 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core1.h new file mode 100644 index 000000000..c3c2f3b5d --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/system_MCXN537_cm33_core1.h @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN537_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN537_cm33_core1 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN537_cm33_core1_H_ +#define _SYSTEM_MCXN537_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN537_cm33_core1_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/variable.cmake new file mode 100644 index 000000000..ea872e3a4 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN537/variable.cmake @@ -0,0 +1,19 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXN537) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXN) +mcux_set_variable(soc_periph periph) + +if (NOT DEFINED core_id) + message(FATAL_ERROR "Please specify core_id for multicore device.") +endif() + +include(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN537/${core_id}/variable.cmake) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/CMakeLists.txt index 14bd1cbed..2140a5abd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/CMakeLists.txt @@ -6,6 +6,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) #### MCX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0.h index f5efd9e4d..d2c77b428 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN546VAB_cm33_core0 +** MCXN546VDF_cm33_core0 ** MCXN546VKL_cm33_core0 ** MCXN546VNL_cm33_core0 ** MCXN546VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN546_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0_COMMON.h index d9f1d5db7..90e7ed9ff 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0_COMMON.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN546VAB_cm33_core0 +** MCXN546VDF_cm33_core0 ** MCXN546VKL_cm33_core0 ** MCXN546VNL_cm33_core0 ** MCXN546VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN546_cm33_core0 @@ -1045,25 +1046,25 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif @@ -1209,14 +1210,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1225,14 +1218,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1241,14 +1226,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1257,14 +1234,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1273,14 +1242,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1289,6 +1250,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1298,72 +1299,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* I2S - Peripheral instance base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0_features.h index c3cdc89f8..426c3bd59 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -310,6 +310,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -317,6 +321,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -482,8 +488,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -512,27 +516,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) -/* @brief FlexSPI IPED REGION COUNT */ -#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* FMU module features */ @@ -576,6 +620,22 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* INPUTMUX module features */ @@ -660,8 +720,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -704,6 +762,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -850,7 +912,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -895,8 +957,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -925,14 +985,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -944,6 +1008,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -1107,7 +1173,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -1131,10 +1197,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN546_cm33_core0_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1.h index aef35192a..d12c45afa 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core1 +** Processors: MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core1 ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN546_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1_COMMON.h index b96710430..60f6795d0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1_COMMON.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core1 +** Processors: MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core1 ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN546_cm33_core1 @@ -1045,25 +1046,25 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) -#else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif @@ -1209,14 +1210,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1225,14 +1218,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1241,14 +1226,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1257,14 +1234,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1273,14 +1242,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1289,6 +1250,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1298,72 +1299,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* I2S - Peripheral instance base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1_features.h index 8c55b6920..95e901f8a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/MCXN546_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -310,6 +310,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -317,6 +321,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -482,8 +488,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -512,27 +516,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) -/* @brief FlexSPI IPED REGION COUNT */ -#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* FMU module features */ @@ -576,6 +620,22 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* INPUTMUX module features */ @@ -660,8 +720,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -704,6 +762,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -850,7 +912,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -895,8 +957,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -925,14 +985,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -944,6 +1008,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -1100,7 +1166,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -1124,10 +1190,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN546_cm33_core1_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/fsl_device_registers.h index fc44a1c74..d227fd03a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/fsl_device_registers.h @@ -13,9 +13,9 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core0.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core0.c index 57cd25014..a58b25b02 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core0.c @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN546VAB_cm33_core0 +** MCXN546VDF_cm33_core0 ** MCXN546VKL_cm33_core0 ** MCXN546VNL_cm33_core0 ** MCXN546VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core0.h index c3225c46d..e3225a081 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core0.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN546VAB_cm33_core0 +** MCXN546VDF_cm33_core0 ** MCXN546VKL_cm33_core0 ** MCXN546VNL_cm33_core0 ** MCXN546VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core1.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core1.c index 23c00ef9e..aa0d0b8d5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core1.c @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core1 +** Processors: MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core1 ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core1.h index 0b17adbbc..ed7f27995 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN546/system_MCXN546_cm33_core1.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core1 +** Processors: MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core1 ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/CMakeLists.txt index 14bd1cbed..2140a5abd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/CMakeLists.txt @@ -6,6 +6,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) #### MCX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0.h index c53433ac8..4dbeecddd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN547VDF_cm33_core0 +** Processors: MCXN547VAB_cm33_core0 +** MCXN547VDF_cm33_core0 ** MCXN547VKL_cm33_core0 ** MCXN547VNL_cm33_core0 ** MCXN547VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN547_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0_COMMON.h index bff924803..e1be7ee8f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0_COMMON.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN547VDF_cm33_core0 +** Processors: MCXN547VAB_cm33_core0 +** MCXN547VDF_cm33_core0 ** MCXN547VKL_cm33_core0 ** MCXN547VNL_cm33_core0 ** MCXN547VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN547_cm33_core0 @@ -1045,25 +1046,25 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif @@ -1209,14 +1210,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1225,14 +1218,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1241,14 +1226,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1257,14 +1234,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1273,14 +1242,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1289,6 +1250,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1298,72 +1299,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* I2S - Peripheral instance base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0_features.h index a8d239882..d87f2c058 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -310,6 +310,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -317,6 +321,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -482,8 +488,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -512,27 +516,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) -/* @brief FlexSPI IPED REGION COUNT */ -#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* FMU module features */ @@ -576,6 +620,22 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* INPUTMUX module features */ @@ -660,8 +720,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -704,6 +762,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -850,7 +912,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -895,8 +957,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -925,14 +985,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -944,6 +1008,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -1107,7 +1173,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -1131,10 +1197,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN547_cm33_core0_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1.h index 621e7bd69..5b1deba87 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN547VDF_cm33_core1 +** Processors: MCXN547VAB_cm33_core1 +** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core1 ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN547_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1_COMMON.h index 0ce911dc4..a8de08d3d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1_COMMON.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN547VDF_cm33_core1 +** Processors: MCXN547VAB_cm33_core1 +** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core1 ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN547_cm33_core1 @@ -1045,25 +1046,25 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) -#else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif @@ -1209,14 +1210,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1225,14 +1218,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1241,14 +1226,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1257,14 +1234,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1273,14 +1242,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1289,6 +1250,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1298,72 +1299,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* I2S - Peripheral instance base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1_features.h index 129bd6f21..03c5c1192 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/MCXN547_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -310,6 +310,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -317,6 +321,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -482,8 +488,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -512,27 +516,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) -/* @brief FlexSPI IPED REGION COUNT */ -#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* FMU module features */ @@ -576,6 +620,22 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* INPUTMUX module features */ @@ -660,8 +720,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -704,6 +762,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -850,7 +912,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -895,8 +957,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -925,14 +985,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -944,6 +1008,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -1100,7 +1166,7 @@ /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -1124,10 +1190,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN547_cm33_core1_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/fsl_device_registers.h index 5546042df..9ecc70091 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/fsl_device_registers.h @@ -13,9 +13,9 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#if (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core0.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core0.c index be7b261bf..ff204091d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core0.c @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN547VDF_cm33_core0 +** Processors: MCXN547VAB_cm33_core0 +** MCXN547VDF_cm33_core0 ** MCXN547VKL_cm33_core0 ** MCXN547VNL_cm33_core0 ** MCXN547VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core0.h index f8d6e2475..a251a45c6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core0.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN547VDF_cm33_core0 +** Processors: MCXN547VAB_cm33_core0 +** MCXN547VDF_cm33_core0 ** MCXN547VKL_cm33_core0 ** MCXN547VNL_cm33_core0 ** MCXN547VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core1.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core1.c index b46d6653a..98cf0dc70 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core1.c @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN547VDF_cm33_core1 +** Processors: MCXN547VAB_cm33_core1 +** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core1 ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core1.h index 4b7e97cac..74f6a4118 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN547/system_MCXN547_cm33_core1.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN547VDF_cm33_core1 +** Processors: MCXN547VAB_cm33_core1 +** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core1 ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/CMakeLists.txt new file mode 100644 index 000000000..208b41d8a --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### device spepcific drivers +include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN556S/drivers/romapi) + +#### MCX shared drivers/components/middlewares, project segments +include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core0.h new file mode 100644 index 000000000..2e934d74f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core0.h @@ -0,0 +1,122 @@ +/* +** ################################################################### +** Processor: MCXN556SCDF_cm33_core0 +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN556S_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN556S_cm33_core0.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN556S_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN556S_cm33_core0 + */ + +#if !defined(MCXN556S_cm33_core0_H_) /* Check if memory map has not been already included */ +#define MCXN556S_cm33_core0_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EMVSIM.h" +#include "PERI_ENET.h" +#include "PERI_ERM.h" +#include "PERI_EVTG.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_I2S.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PDM.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_PWM.h" +#include "PERI_QDC.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_TSI.h" +#include "PERI_USB.h" +#include "PERI_USBDCD.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN556S_cm33_core0_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core0_COMMON.h new file mode 100644 index 000000000..3d6d63e81 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core0_COMMON.h @@ -0,0 +1,3531 @@ +/* +** ################################################################### +** Processor: MCXN556SCDF_cm33_core0 +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN556S_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN556S_cm33_core0_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN556S_cm33_core0 + * + * CMSIS Peripheral Access Layer for MCXN556S_cm33_core0 + */ + +#if !defined(MCXN556S_CM33_CORE0_COMMON_H_) +#define MCXN556S_CM33_CORE0_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + USB0_FS_IRQn = 50, /**< Universal Serial Bus - Full Speed interrupt */ + USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ + SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + TSI_END_OF_SCAN_IRQn = 101, /**< TSI End of Scan interrupt */ + TSI_OUT_OF_SCAN_IRQn = 102, /**< TSI Out of Scan interrupt */ + EMVSIM0_IRQn = 103, /**< EMVSIM0 interrupt */ + EMVSIM1_IRQn = 104, /**< EMVSIM1 interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + DAC1_IRQn = 107, /**< Digital-to-Analog Converter 1 - General Purpose interrupt */ + Reserved124_IRQn = 108, /**< Reserved interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + QDC0_COMPARE_IRQn = 124, /**< QDC0_Compare interrupt */ + QDC0_HOME_IRQn = 125, /**< QDC0_Home interrupt */ + QDC0_WDG_SAB_IRQn = 126, /**< QDC0_WDG_IRQ/SAB interrupt */ + QDC0_IDX_IRQn = 127, /**< QDC0_IDX interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + ETHERNET_IRQn = 139, /**< Ethernet QoS interrupt */ + ETHERNET_PMT_IRQn = 140, /**< Ethernet QoS power management interrupt */ + ETHERNET_MACLP_IRQn = 141, /**< Ethernet QoS MAC interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN556S_cm33_core0.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN556S_cm33_core0_SERIES +#define MCXN556S_cm33_core0_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN556S_cm33_core0_features.h" + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CAN - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* EMVSIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EMVSIM0 base address */ + #define EMVSIM0_BASE (0x50103000u) + /** Peripheral EMVSIM0 base address */ + #define EMVSIM0_BASE_NS (0x40103000u) + /** Peripheral EMVSIM0 base pointer */ + #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) + /** Peripheral EMVSIM0 base pointer */ + #define EMVSIM0_NS ((EMVSIM_Type *)EMVSIM0_BASE_NS) + /** Peripheral EMVSIM1 base address */ + #define EMVSIM1_BASE (0x50104000u) + /** Peripheral EMVSIM1 base address */ + #define EMVSIM1_BASE_NS (0x40104000u) + /** Peripheral EMVSIM1 base pointer */ + #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) + /** Peripheral EMVSIM1 base pointer */ + #define EMVSIM1_NS ((EMVSIM_Type *)EMVSIM1_BASE_NS) + /** Array initializer of EMVSIM peripheral base addresses */ + #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } + /** Array initializer of EMVSIM peripheral base pointers */ + #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } + /** Array initializer of EMVSIM peripheral base addresses */ + #define EMVSIM_BASE_ADDRS_NS { EMVSIM0_BASE_NS, EMVSIM1_BASE_NS } + /** Array initializer of EMVSIM peripheral base pointers */ + #define EMVSIM_BASE_PTRS_NS { EMVSIM0_NS, EMVSIM1_NS } +#else + /** Peripheral EMVSIM0 base address */ + #define EMVSIM0_BASE (0x40103000u) + /** Peripheral EMVSIM0 base pointer */ + #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) + /** Peripheral EMVSIM1 base address */ + #define EMVSIM1_BASE (0x40104000u) + /** Peripheral EMVSIM1 base pointer */ + #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) + /** Array initializer of EMVSIM peripheral base addresses */ + #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } + /** Array initializer of EMVSIM peripheral base pointers */ + #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } +#endif +/** Interrupt vectors for the EMVSIM peripheral type */ +#define EMVSIM_IRQS { EMVSIM0_IRQn, EMVSIM1_IRQn } + +/* ENET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ENET0 base address */ + #define ENET0_BASE (0x50100000u) + /** Peripheral ENET0 base address */ + #define ENET0_BASE_NS (0x40100000u) + /** Peripheral ENET0 base pointer */ + #define ENET0 ((ENET_Type *)ENET0_BASE) + /** Peripheral ENET0 base pointer */ + #define ENET0_NS ((ENET_Type *)ENET0_BASE_NS) + /** Array initializer of ENET peripheral base addresses */ + #define ENET_BASE_ADDRS { ENET0_BASE } + /** Array initializer of ENET peripheral base pointers */ + #define ENET_BASE_PTRS { ENET0 } + /** Array initializer of ENET peripheral base addresses */ + #define ENET_BASE_ADDRS_NS { ENET0_BASE_NS } + /** Array initializer of ENET peripheral base pointers */ + #define ENET_BASE_PTRS_NS { ENET0_NS } +#else + /** Peripheral ENET0 base address */ + #define ENET0_BASE (0x40100000u) + /** Peripheral ENET0 base pointer */ + #define ENET0 ((ENET_Type *)ENET0_BASE) + /** Array initializer of ENET peripheral base addresses */ + #define ENET_BASE_ADDRS { ENET0_BASE } + /** Array initializer of ENET peripheral base pointers */ + #define ENET_BASE_PTRS { ENET0 } +#endif +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_IRQS { ETHERNET_IRQn } +#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn } +#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn } +/* Backward compatibility */ +#define ENET ENET0 + + +/* ERM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EVTG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x500D2000u) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE_NS (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Peripheral EVTG0 base pointer */ + #define EVTG0_NS ((EVTG_Type *)EVTG0_BASE_NS) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS_NS { EVTG0_BASE_NS } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS_NS { EVTG0_NS } +#else + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x50106000u) + /** Peripheral SAI0 base address */ + #define SAI0_BASE_NS (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI0 base pointer */ + #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x50107000u) + /** Peripheral SAI1 base address */ + #define SAI1_BASE_NS (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI1 base pointer */ + #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } +#else + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } +#define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x50112000u) + /** Peripheral DAC1 base address */ + #define DAC1_BASE_NS (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Peripheral DAC1 base pointer */ + #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PDM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PDM base address */ + #define PDM_BASE (0x5010C000u) + /** Peripheral PDM base address */ + #define PDM_BASE_NS (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Peripheral PDM base pointer */ + #define PDM_NS ((PDM_Type *)PDM_BASE_NS) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS_NS { PDM_NS } +#else + /** Peripheral PDM base address */ + #define PDM_BASE (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } +#endif +/** Interrupt vectors for the PDM peripheral type */ +#define PDM_IRQS { PDM_EVENT_IRQn } + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* PWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn } + +/* QDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x500CF000u) + /** Peripheral QDC0 base address */ + #define QDC0_BASE_NS (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC0 base pointer */ + #define QDC0_NS ((QDC_Type *)QDC0_BASE_NS) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0 } + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS_NS { QDC0_BASE_NS } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS_NS { QDC0_NS } +#else + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0 } +#endif +/** Interrupt vectors for the QDC peripheral type */ +#define QDC_COMPARE_IRQS { QDC0_COMPARE_IRQn } +#define QDC_HOME_IRQS { QDC0_HOME_IRQn } +#define QDC_WDOG_IRQS { QDC0_WDG_SAB_IRQn } +#define QDC_INDEX_IRQS { QDC0_IDX_IRQn } + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TSI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x50050000u) + /** Peripheral TSI0 base address */ + #define TSI0_BASE_NS (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Peripheral TSI0 base pointer */ + #define TSI0_NS ((TSI_Type *)TSI0_BASE_NS) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS_NS { TSI0_BASE_NS } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS_NS { TSI0_NS } +#else + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } +#endif + +/* USB - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x500DD000u) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE_NS (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Peripheral USBFS0 base pointer */ + #define USBFS0_NS ((USB_Type *)USBFS0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USBFS0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USBFS0_NS } +#else + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_FS_IRQn } + +/* USBDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x500DC000u) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE_NS (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0_NS ((USBDCD_Type *)USBDCD0_BASE_NS) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS_NS { USBDCD0_BASE_NS } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS_NS { USBDCD0_NS } +#else + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } +#endif +/** Interrupt vectors for the USBDCD peripheral type */ +#define USBDCD_IRQS { USB0_DCD_IRQn } + +/* USBHS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN556S_CM33_CORE0_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core0_features.h new file mode 100644 index 000000000..7a474f0e6 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core0_features.h @@ -0,0 +1,1207 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN556S_cm33_core0_FEATURES_H_ +#define _MCXN556S_cm33_core0_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (2) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MCX_ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (0) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (0) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EVTG module features */ + +/* @brief OPAMP support force bypass */ +#define FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) + +/* QDC module features */ + +/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ +#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0) +/* @brief Has register CTRL3. */ +#define FSL_FEATURE_QDC_HAS_CTRL3 (1) +/* @brief Has register LASTEDGE or LASTEDGEH. */ +#define FSL_FEATURE_QDC_HAS_LASTEDGE (1) +/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ +#define FSL_FEATURE_QDC_HAS_POSDPER (1) +/* @brief Has bitfiled FILT[FILT_PRSC]. */ +#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1048576) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* TSI module features */ + +/* @brief TSI Version */ +#define FSL_FEATURE_TSI_VERSION (6U) +/* @brief TSI Channel Count */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) + +/* USBHSDCD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (1074503680) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074503680) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) +/* @brief Mode control of the USB Keep Alive */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN556S_cm33_core0_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core1.h new file mode 100644 index 000000000..988c831ea --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core1.h @@ -0,0 +1,122 @@ +/* +** ################################################################### +** Processor: MCXN556SCDF_cm33_core1 +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN556S_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN556S_cm33_core1.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN556S_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN556S_cm33_core1 + */ + +#if !defined(MCXN556S_cm33_core1_H_) /* Check if memory map has not been already included */ +#define MCXN556S_cm33_core1_H_ + +/* IP Header Files List */ +#include "PERI_ADC.h" +#include "PERI_AHBSC.h" +#include "PERI_CACHE64_CTRL.h" +#include "PERI_CACHE64_POLSEL.h" +#include "PERI_CAN.h" +#include "PERI_CDOG.h" +#include "PERI_CMC.h" +#include "PERI_CRC.h" +#include "PERI_CTIMER.h" +#include "PERI_DIGTMP.h" +#include "PERI_DM.h" +#include "PERI_DMA.h" +#include "PERI_EIM.h" +#include "PERI_EMVSIM.h" +#include "PERI_ENET.h" +#include "PERI_ERM.h" +#include "PERI_EVTG.h" +#include "PERI_EWM.h" +#include "PERI_FLEXIO.h" +#include "PERI_FLEXSPI.h" +#include "PERI_FMU.h" +#include "PERI_FMUTEST.h" +#include "PERI_FREQME.h" +#include "PERI_GDET.h" +#include "PERI_GPIO.h" +#include "PERI_I2S.h" +#include "PERI_I3C.h" +#include "PERI_INPUTMUX.h" +#include "PERI_INTM.h" +#include "PERI_ITRC.h" +#include "PERI_LPCMP.h" +#include "PERI_LPDAC.h" +#include "PERI_LPI2C.h" +#include "PERI_LPSPI.h" +#include "PERI_LPTMR.h" +#include "PERI_LPUART.h" +#include "PERI_LP_FLEXCOMM.h" +#include "PERI_MAILBOX.h" +#include "PERI_MRT.h" +#include "PERI_NPX.h" +#include "PERI_OSTIMER.h" +#include "PERI_OTPC.h" +#include "PERI_PDM.h" +#include "PERI_PINT.h" +#include "PERI_PKC.h" +#include "PERI_PORT.h" +#include "PERI_POWERQUAD.h" +#include "PERI_PUF.h" +#include "PERI_PWM.h" +#include "PERI_QDC.h" +#include "PERI_RTC.h" +#include "PERI_S50.h" +#include "PERI_SCG.h" +#include "PERI_SCT.h" +#include "PERI_SEMA42.h" +#include "PERI_SMARTDMA.h" +#include "PERI_SPC.h" +#include "PERI_SYSCON.h" +#include "PERI_SYSPM.h" +#include "PERI_TRDC.h" +#include "PERI_TSI.h" +#include "PERI_USB.h" +#include "PERI_USBDCD.h" +#include "PERI_USBHS.h" +#include "PERI_USBHSDCD.h" +#include "PERI_USBNC.h" +#include "PERI_USBPHY.h" +#include "PERI_USDHC.h" +#include "PERI_UTICK.h" +#include "PERI_VBAT.h" +#include "PERI_VREF.h" +#include "PERI_WUU.h" +#include "PERI_WWDT.h" + +#endif /* #if !defined(MCXN556S_cm33_core1_H_) */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core1_COMMON.h new file mode 100644 index 000000000..7be36be43 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core1_COMMON.h @@ -0,0 +1,3531 @@ +/* +** ################################################################### +** Processor: MCXN556SCDF_cm33_core1 +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250901 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN556S_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN556S_cm33_core1_COMMON.h + * @version 3.0 + * @date 2024-10-29 + * @brief CMSIS Peripheral Access Layer for MCXN556S_cm33_core1 + * + * CMSIS Peripheral Access Layer for MCXN556S_cm33_core1 + */ + +#if !defined(MCXN556S_CM33_CORE1_COMMON_H_) +#define MCXN556S_CM33_CORE1_COMMON_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + SCT0_IRQn = 33, /**< SCTimer/PWM interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM8_IRQn = 43, /**< LP_FLEXCOMM8 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM9_IRQn = 44, /**< LP_FLEXCOMM9 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + USB0_FS_IRQn = 50, /**< Universal Serial Bus - Full Speed interrupt */ + USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + MAILBOX_IRQn = 54, /**< Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU Mailbox interrupt1 for CPU1 */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + FLEXSPI0_IRQn = 58, /**< Flexible Serial Peripheral Interface interrupt */ + SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ + SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ + USDHC0_IRQn = 61, /**< Ultra Secured Digital Host Controller interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + PQ_IRQn = 76, /**< Power Quad interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + EDMA_1_CH8_IRQn = 85, /**< eDMA_1_CH8 error or transfer complete */ + EDMA_1_CH9_IRQn = 86, /**< eDMA_1_CH9 error or transfer complete */ + EDMA_1_CH10_IRQn = 87, /**< eDMA_1_CH10 error or transfer complete */ + EDMA_1_CH11_IRQn = 88, /**< eDMA_1_CH11 error or transfer complete */ + EDMA_1_CH12_IRQn = 89, /**< eDMA_1_CH12 error or transfer complete */ + EDMA_1_CH13_IRQn = 90, /**< eDMA_1_CH13 error or transfer complete */ + EDMA_1_CH14_IRQn = 91, /**< eDMA_1_CH14 error or transfer complete */ + EDMA_1_CH15_IRQn = 92, /**< eDMA_1_CH15 error or transfer complete */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + NPU_IRQn = 97, /**< NPU interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + TSI_END_OF_SCAN_IRQn = 101, /**< TSI End of Scan interrupt */ + TSI_OUT_OF_SCAN_IRQn = 102, /**< TSI Out of Scan interrupt */ + EMVSIM0_IRQn = 103, /**< EMVSIM0 interrupt */ + EMVSIM1_IRQn = 104, /**< EMVSIM1 interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + DAC0_IRQn = 106, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + DAC1_IRQn = 107, /**< Digital-to-Analog Converter 1 - General Purpose interrupt */ + Reserved124_IRQn = 108, /**< Reserved interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + QDC0_COMPARE_IRQn = 124, /**< QDC0_Compare interrupt */ + QDC0_HOME_IRQn = 125, /**< QDC0_Home interrupt */ + QDC0_WDG_SAB_IRQn = 126, /**< QDC0_WDG_IRQ/SAB interrupt */ + QDC0_IDX_IRQn = 127, /**< QDC0_IDX interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + Reserved145_IRQn = 129, /**< Reserved interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + ETHERNET_IRQn = 139, /**< Ethernet QoS interrupt */ + ETHERNET_PMT_IRQn = 140, /**< Ethernet QoS power management interrupt */ + ETHERNET_MACLP_IRQn = 141, /**< Ethernet QoS MAC interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + ETB0_IRQn = 149, /**< ETB counter expires interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + CTI0_IRQn = 155 /**< Cross Trigger Interface interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN556S_cm33_core1.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +#ifndef MCXN556S_cm33_core1_SERIES +#define MCXN556S_cm33_core1_SERIES +#endif +/* CPU specific feature definitions */ +#include "MCXN556S_cm33_core1_features.h" + +/* ADC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* AHBSC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/* CACHE64_CTRL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x5001B000u) + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS } +#else + /** Peripheral CACHE64_CTRL0 base address */ + #define CACHE64_CTRL0_BASE (0x4001B000u) + /** Peripheral CACHE64_CTRL0 base pointer */ + #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) + /** Array initializer of CACHE64_CTRL peripheral base addresses */ + #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } + /** Array initializer of CACHE64_CTRL peripheral base pointers */ + #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } +#endif +/** CACHE64_CTRL physical memory base alias count */ + #define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#else +/** CACHE64_CTRL physical memory base address */ + #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } +/** CACHE64_CTRL physical memory size */ + #define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} } +/** CACHE64_CTRL remap base address */ + #define CACHE64_CTRL_ALIAS_REMAPPED_BASE_ADDR {0x80000000u, 0x80000000u, 0x90000000u} +#endif +/* Backward compatibility */ + + +/* CACHE64_POLSEL - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x5001B000u) + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE_NS (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS } +#else + /** Peripheral CACHE64_POLSEL0 base address */ + #define CACHE64_POLSEL0_BASE (0x4001B000u) + /** Peripheral CACHE64_POLSEL0 base pointer */ + #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE) + /** Array initializer of CACHE64_POLSEL peripheral base addresses */ + #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE } + /** Array initializer of CACHE64_POLSEL peripheral base pointers */ + #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } +#endif + +/* CAN - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/* CDOG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/* CMC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif + +/* CRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/* CTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/* DIGTMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/* DM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/* DMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn } } + +/* EIM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/* EMVSIM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EMVSIM0 base address */ + #define EMVSIM0_BASE (0x50103000u) + /** Peripheral EMVSIM0 base address */ + #define EMVSIM0_BASE_NS (0x40103000u) + /** Peripheral EMVSIM0 base pointer */ + #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) + /** Peripheral EMVSIM0 base pointer */ + #define EMVSIM0_NS ((EMVSIM_Type *)EMVSIM0_BASE_NS) + /** Peripheral EMVSIM1 base address */ + #define EMVSIM1_BASE (0x50104000u) + /** Peripheral EMVSIM1 base address */ + #define EMVSIM1_BASE_NS (0x40104000u) + /** Peripheral EMVSIM1 base pointer */ + #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) + /** Peripheral EMVSIM1 base pointer */ + #define EMVSIM1_NS ((EMVSIM_Type *)EMVSIM1_BASE_NS) + /** Array initializer of EMVSIM peripheral base addresses */ + #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } + /** Array initializer of EMVSIM peripheral base pointers */ + #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } + /** Array initializer of EMVSIM peripheral base addresses */ + #define EMVSIM_BASE_ADDRS_NS { EMVSIM0_BASE_NS, EMVSIM1_BASE_NS } + /** Array initializer of EMVSIM peripheral base pointers */ + #define EMVSIM_BASE_PTRS_NS { EMVSIM0_NS, EMVSIM1_NS } +#else + /** Peripheral EMVSIM0 base address */ + #define EMVSIM0_BASE (0x40103000u) + /** Peripheral EMVSIM0 base pointer */ + #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) + /** Peripheral EMVSIM1 base address */ + #define EMVSIM1_BASE (0x40104000u) + /** Peripheral EMVSIM1 base pointer */ + #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) + /** Array initializer of EMVSIM peripheral base addresses */ + #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } + /** Array initializer of EMVSIM peripheral base pointers */ + #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } +#endif +/** Interrupt vectors for the EMVSIM peripheral type */ +#define EMVSIM_IRQS { EMVSIM0_IRQn, EMVSIM1_IRQn } + +/* ENET - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ENET0 base address */ + #define ENET0_BASE (0x50100000u) + /** Peripheral ENET0 base address */ + #define ENET0_BASE_NS (0x40100000u) + /** Peripheral ENET0 base pointer */ + #define ENET0 ((ENET_Type *)ENET0_BASE) + /** Peripheral ENET0 base pointer */ + #define ENET0_NS ((ENET_Type *)ENET0_BASE_NS) + /** Array initializer of ENET peripheral base addresses */ + #define ENET_BASE_ADDRS { ENET0_BASE } + /** Array initializer of ENET peripheral base pointers */ + #define ENET_BASE_PTRS { ENET0 } + /** Array initializer of ENET peripheral base addresses */ + #define ENET_BASE_ADDRS_NS { ENET0_BASE_NS } + /** Array initializer of ENET peripheral base pointers */ + #define ENET_BASE_PTRS_NS { ENET0_NS } +#else + /** Peripheral ENET0 base address */ + #define ENET0_BASE (0x40100000u) + /** Peripheral ENET0 base pointer */ + #define ENET0 ((ENET_Type *)ENET0_BASE) + /** Array initializer of ENET peripheral base addresses */ + #define ENET_BASE_ADDRS { ENET0_BASE } + /** Array initializer of ENET peripheral base pointers */ + #define ENET_BASE_PTRS { ENET0 } +#endif +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_IRQS { ETHERNET_IRQn } +#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn } +#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn } +/* Backward compatibility */ +#define ENET ENET0 + + +/* ERM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/* EVTG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x500D2000u) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE_NS (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Peripheral EVTG0 base pointer */ + #define EVTG0_NS ((EVTG_Type *)EVTG0_BASE_NS) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS_NS { EVTG0_BASE_NS } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS_NS { EVTG0_NS } +#else + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } +#endif + +/* EWM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM0_IRQn } + +/* FLEXIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/* FLEXSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x500C8000u) + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE_NS (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS } +#else + /** Peripheral FLEXSPI0 base address */ + #define FLEXSPI0_BASE (0x400C8000u) + /** Peripheral FLEXSPI0 base pointer */ + #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) + /** Array initializer of FLEXSPI peripheral base addresses */ + #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE } + /** Array initializer of FLEXSPI peripheral base pointers */ + #define FLEXSPI_BASE_PTRS { FLEXSPI0 } +#endif +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI0_IRQn } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) +#endif + + +/* FMU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/* FMUTEST - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/* FREQME - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/* GDET - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif +/** Interrupt vectors for the GDET peripheral type */ +#define GDET_IRQS { GDET_IRQn, GDET_IRQn } + +/* GPIO - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif + +/* I2S - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x50106000u) + /** Peripheral SAI0 base address */ + #define SAI0_BASE_NS (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI0 base pointer */ + #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x50107000u) + /** Peripheral SAI1 base address */ + #define SAI1_BASE_NS (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI1 base pointer */ + #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } +#else + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } +#define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } + +/* I3C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/* INPUTMUX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif + +/* INTM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/* ITRC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/* LPCMP - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn } + +/* LPDAC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x5010F000u) + /** Peripheral DAC0 base address */ + #define DAC0_BASE_NS (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC0 base pointer */ + #define DAC0_NS ((LPDAC_Type *)DAC0_BASE_NS) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x50112000u) + /** Peripheral DAC1 base address */ + #define DAC1_BASE_NS (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Peripheral DAC1 base pointer */ + #define DAC1_NS ((LPDAC_Type *)DAC1_BASE_NS) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS_NS { DAC0_BASE_NS, DAC1_BASE_NS } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS_NS { DAC0_NS, DAC1_NS } +#else + /** Peripheral DAC0 base address */ + #define DAC0_BASE (0x4010F000u) + /** Peripheral DAC0 base pointer */ + #define DAC0 ((LPDAC_Type *)DAC0_BASE) + /** Peripheral DAC1 base address */ + #define DAC1_BASE (0x40112000u) + /** Peripheral DAC1 base pointer */ + #define DAC1 ((LPDAC_Type *)DAC1_BASE) + /** Array initializer of LPDAC peripheral base addresses */ + #define LPDAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } + /** Array initializer of LPDAC peripheral base pointers */ + #define LPDAC_BASE_PTRS { DAC0, DAC1 } +#endif +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/* LPI2C - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x500B8800u) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE_NS (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8_NS ((LPI2C_Type *)LPI2C8_BASE_NS) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x500B9800u) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE_NS (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9_NS ((LPI2C_Type *)LPI2C9_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS, LPI2C8_BASE_NS, LPI2C9_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS, LPI2C8_NS, LPI2C9_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C8 base address */ + #define LPI2C8_BASE (0x400B8800u) + /** Peripheral LPI2C8 base pointer */ + #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) + /** Peripheral LPI2C9 base address */ + #define LPI2C9_BASE (0x400B9800u) + /** Peripheral LPI2C9 base pointer */ + #define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE, LPI2C9_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPSPI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x500B8000u) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE_NS (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8_NS ((LPSPI_Type *)LPSPI8_BASE_NS) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x500B9000u) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE_NS (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9_NS ((LPSPI_Type *)LPSPI9_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS, LPSPI8_BASE_NS, LPSPI9_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS, LPSPI8_NS, LPSPI9_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI8 base address */ + #define LPSPI8_BASE (0x400B8000u) + /** Peripheral LPSPI8 base pointer */ + #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) + /** Peripheral LPSPI9 base address */ + #define LPSPI9_BASE (0x400B9000u) + /** Peripheral LPSPI9 base pointer */ + #define LPSPI9 ((LPSPI_Type *)LPSPI9_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE, LPSPI9_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LPTMR - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/* LPUART - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x500B8000u) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE_NS (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART8 base pointer */ + #define LPUART8_NS ((LPUART_Type *)LPUART8_BASE_NS) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x500B9000u) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE_NS (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Peripheral LPUART9 base pointer */ + #define LPUART9_NS ((LPUART_Type *)LPUART9_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS, LPUART9_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS, LPUART9_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART8 base address */ + #define LPUART8_BASE (0x400B8000u) + /** Peripheral LPUART8 base pointer */ + #define LPUART8 ((LPUART_Type *)LPUART8_BASE) + /** Peripheral LPUART9 base address */ + #define LPUART9_BASE (0x400B9000u) + /** Peripheral LPUART9 base pointer */ + #define LPUART9 ((LPUART_Type *)LPUART9_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x500B8000u) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE_NS (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE_NS) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x500B9000u) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE_NS (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS, LP_FLEXCOMM8_BASE_NS, LP_FLEXCOMM9_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS, LP_FLEXCOMM8_NS, LP_FLEXCOMM9_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM8 base address */ + #define LP_FLEXCOMM8_BASE (0x400B8000u) + /** Peripheral LP_FLEXCOMM8 base pointer */ + #define LP_FLEXCOMM8 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM8_BASE) + /** Peripheral LP_FLEXCOMM9 base address */ + #define LP_FLEXCOMM9_BASE (0x400B9000u) + /** Peripheral LP_FLEXCOMM9 base pointer */ + #define LP_FLEXCOMM9 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM9_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE, LP_FLEXCOMM8_BASE, LP_FLEXCOMM9_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn } + +/* MAILBOX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x500B2000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x400B2000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif + +/* MRT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/* NPX - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/* OSTIMER - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/* OTPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/* PDM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PDM base address */ + #define PDM_BASE (0x5010C000u) + /** Peripheral PDM base address */ + #define PDM_BASE_NS (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Peripheral PDM base pointer */ + #define PDM_NS ((PDM_Type *)PDM_BASE_NS) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS_NS { PDM_NS } +#else + /** Peripheral PDM base address */ + #define PDM_BASE (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } +#endif +/** Interrupt vectors for the PDM peripheral type */ +#define PDM_IRQS { PDM_EVENT_IRQn } + +/* PINT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } + +/* PKC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/* PORT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/* POWERQUAD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500BF000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400BF000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } + +/* PUF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/* PWM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn } + +/* QDC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x500CF000u) + /** Peripheral QDC0 base address */ + #define QDC0_BASE_NS (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC0 base pointer */ + #define QDC0_NS ((QDC_Type *)QDC0_BASE_NS) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0 } + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS_NS { QDC0_BASE_NS } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS_NS { QDC0_NS } +#else + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0 } +#endif +/** Interrupt vectors for the QDC peripheral type */ +#define QDC_COMPARE_IRQS { QDC0_COMPARE_IRQn } +#define QDC_HOME_IRQS { QDC0_HOME_IRQn } +#define QDC_WDOG_IRQS { QDC0_WDG_SAB_IRQn } +#define QDC_INDEX_IRQS { QDC0_IDX_IRQn } + +/* RTC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/* S50 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/* SCG - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/* SCT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50091000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40091000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/* SEMA42 - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x500B1000u) + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE_NS (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0_NS ((SEMA42_Type *)SEMA42_0_BASE_NS) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS_NS { SEMA42_0_BASE_NS } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS_NS { SEMA42_0_NS } +#else + /** Peripheral SEMA42_0 base address */ + #define SEMA42_0_BASE (0x400B1000u) + /** Peripheral SEMA42_0 base pointer */ + #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) + /** Array initializer of SEMA42 peripheral base addresses */ + #define SEMA42_BASE_ADDRS { SEMA42_0_BASE } + /** Array initializer of SEMA42 peripheral base pointers */ + #define SEMA42_BASE_PTRS { SEMA42_0 } +#endif + +/* SMARTDMA - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/* SPC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/* SYSCON - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif + +/* SYSPM - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x500C2000u) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE_NS (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1_NS ((SYSPM_Type *)CMX_PERFMON1_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS, CMX_PERFMON1_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS, CMX_PERFMON1_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON1 base address */ + #define CMX_PERFMON1_BASE (0x400C2000u) + /** Peripheral CMX_PERFMON1 base pointer */ + #define CMX_PERFMON1 ((SYSPM_Type *)CMX_PERFMON1_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE, CMX_PERFMON1_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0, CMX_PERFMON1 } +#endif + +/* TRDC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/* TSI - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x50050000u) + /** Peripheral TSI0 base address */ + #define TSI0_BASE_NS (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Peripheral TSI0 base pointer */ + #define TSI0_NS ((TSI_Type *)TSI0_BASE_NS) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS_NS { TSI0_BASE_NS } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS_NS { TSI0_NS } +#else + /** Peripheral TSI0 base address */ + #define TSI0_BASE (0x40050000u) + /** Peripheral TSI0 base pointer */ + #define TSI0 ((TSI_Type *)TSI0_BASE) + /** Array initializer of TSI peripheral base addresses */ + #define TSI_BASE_ADDRS { TSI0_BASE } + /** Array initializer of TSI peripheral base pointers */ + #define TSI_BASE_PTRS { TSI0 } +#endif + +/* USB - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x500DD000u) + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE_NS (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Peripheral USBFS0 base pointer */ + #define USBFS0_NS ((USB_Type *)USBFS0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USBFS0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USBFS0_NS } +#else + /** Peripheral USBFS0 base address */ + #define USBFS0_BASE (0x400DD000u) + /** Peripheral USBFS0 base pointer */ + #define USBFS0 ((USB_Type *)USBFS0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USBFS0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USBFS0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_FS_IRQn } + +/* USBDCD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x500DC000u) + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE_NS (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0_NS ((USBDCD_Type *)USBDCD0_BASE_NS) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS_NS { USBDCD0_BASE_NS } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS_NS { USBDCD0_NS } +#else + /** Peripheral USBDCD0 base address */ + #define USBDCD0_BASE (0x400DC000u) + /** Peripheral USBDCD0 base pointer */ + #define USBDCD0 ((USBDCD_Type *)USBDCD0_BASE) + /** Array initializer of USBDCD peripheral base addresses */ + #define USBDCD_BASE_ADDRS { USBDCD0_BASE } + /** Array initializer of USBDCD peripheral base pointers */ + #define USBDCD_BASE_PTRS { USBDCD0 } +#endif +/** Interrupt vectors for the USBDCD peripheral type */ +#define USBDCD_IRQS { USB0_DCD_IRQn } + +/* USBHS - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } + +/* USBHSDCD - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A800u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A800u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif + +/* USBNC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif + +/* USBPHY - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/* USDHC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x50109000u) + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE_NS (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Peripheral USDHC0 base pointer */ + #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS_NS { USDHC0_NS } +#else + /** Peripheral USDHC0 base address */ + #define USDHC0_BASE (0x40109000u) + /** Peripheral USDHC0 base pointer */ + #define USDHC0 ((USDHC_Type *)USDHC0_BASE) + /** Array initializer of USDHC peripheral base addresses */ + #define USDHC_BASE_ADDRS { USDHC0_BASE } + /** Array initializer of USDHC peripheral base pointers */ + #define USDHC_BASE_PTRS { USDHC0 } +#endif +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { USDHC0_IRQn } + +/* UTICK - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/* VBAT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/* VREF - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/* WUU - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/* WWDT - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN556S_CM33_CORE1_COMMON_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core1_features.h new file mode 100644 index 000000000..e06a77aec --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/MCXN556S_cm33_core1_features.h @@ -0,0 +1,1200 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b250901 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN556S_cm33_core1_FEATURES_H_ +#define _MCXN556S_cm33_core1_FEATURES_H_ + +/* SOC module features */ + +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (2) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MCX_ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */ +#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (0) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* CACHE64_CTRL module features */ + +/* @brief Cache Line size in byte. */ +#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32) + +/* CACHE64_POLSEL module features */ + +/* No feature definitions */ + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) + +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) +/* @brief CDOG Load default configurations during init function */ +#define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR0_CMP_STOP_EN (0) +/* @brief CMP instance support CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(x) (0) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EVTG module features */ + +/* @brief OPAMP support force bypass */ +#define FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief FLEXIO support reset from RSTCTL */ +#define FSL_FEATURE_FLEXIO_HAS_RESET (0) +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) + +/* FMU module features */ + +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register. */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) +/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ +#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) + +/* QDC module features */ + +/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ +#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0) +/* @brief Has register CTRL3. */ +#define FSL_FEATURE_QDC_HAS_CTRL3 (1) +/* @brief Has register LASTEDGE or LASTEDGEH. */ +#define FSL_FEATURE_QDC_HAS_LASTEDGE (1) +/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ +#define FSL_FEATURE_QDC_HAS_POSDPER (1) +/* @brief Has bitfiled FILT[FILT_PRSC]. */ +#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) +/* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ +#define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (16) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1048576) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief Has parity miss (bitfield LPCAC_CTRL[PARITY_MISS_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_MISS_EN_BIT (1) +/* @brief Has parity error report (bitfield LPCAC_CTRL[PARITY_FAULT_EN]). */ +#define FSL_FEATURE_SYSCON_HAS_LPCAC_CTRL_PARITY_FAULT_EN_BIT (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* TSI module features */ + +/* @brief TSI Version */ +#define FSL_FEATURE_TSI_VERSION (6U) +/* @brief TSI Channel Count */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) + +/* USBHSDCD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (1074503680) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (2048) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074503680) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) +/* @brief Mode control of the USB Keep Alive */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* UTICK module features */ + +/* @brief UTICK does not support power down configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) + +#endif /* _MCXN556S_cm33_core1_FEATURES_H_ */ + diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/cm33_core0/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/cm33_core0/variable.cmake new file mode 100644 index 000000000..292d91c99 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/cm33_core0/variable.cmake @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core0) +mcux_set_variable(multicore_foldername cm33_core0) +mcux_set_variable(multicore_sec_core_foldername cm33_core1) \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/cm33_core1/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/cm33_core1/variable.cmake new file mode 100644 index 000000000..b38aabbc1 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/cm33_core1/variable.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### Source record +mcux_set_variable(core_id_suffix_name _cm33_core1) +mcux_set_variable(multicore_foldername cm33_core1) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/CMakeLists.txt new file mode 100644 index 000000000..1840402f3 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/CMakeLists.txt @@ -0,0 +1,70 @@ +if (CONFIG_MCUX_COMPONENT_driver.romapi) + mcux_component_version(2.0.0) + + mcux_add_source( + SOURCES + ./flash/fsl_flash.h + ) + + mcux_add_include( + INCLUDES ./flash + ) + + +endif() + +if (CONFIG_MCUX_COMPONENT_driver.mem_interface) + mcux_component_version(2.0.0) + mcux_add_source( + SOURCES + ./mem_interface/src/fsl_mem_interface.c + ./mem_interface/fsl_mem_interface.h + ./mem_interface/fsl_sbloader.h + ./mem_interface/fsl_sbloader_v4.h + ) + + mcux_add_include( + INCLUDES ./mem_interface + ) + +endif() + +if (CONFIG_MCUX_COMPONENT_driver.romapi_nboot) + mcux_component_version(2.0.0) + mcux_add_source( + SOURCES + ./nboot/src/fsl_nboot.c + ./nboot/fsl_nboot_hal.h + ./nboot/fsl_nboot.h) + mcux_add_include( INCLUDES ./nboot ) +endif() + +if (CONFIG_MCUX_COMPONENT_driver.runbootloader) + mcux_component_version(2.0.0) + mcux_add_source( + SOURCES + ./runbootloader/fsl_runbootloader.h + ./runbootloader/src/fsl_runbootloader.c + ) + + mcux_add_include( + INCLUDES ./runbootloader + ) + +endif() + +if (CONFIG_MCUX_COMPONENT_driver.romapi_flashiap) + mcux_component_version(2.0.0) + mcux_add_source( + SOURCES + ./flash/src/fsl_flash.c + ./flash/fsl_flash.h + ./flash/fsl_efuse.h + ./flash/fsl_flash_ffr.h + ) + + mcux_add_include( + INCLUDES ./flash + ) + +endif() diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/fsl_efuse.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/fsl_efuse.h new file mode 100644 index 000000000..eb322be00 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/fsl_efuse.h @@ -0,0 +1,112 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_EFUSE_H_ +#define FSL_EFUSE_H_ + +#include "fsl_flash.h" + +/*! + * @addtogroup efuse_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EFUSE APIs + * @{ + */ + +/*! + * @brief Initialize EFUSE controller. + * + * This function enables EFUSE Controller clock. + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Init(void); + +/*! + * @brief De-Initialize EFUSE controller. + * + * This functin disables EFUSE Controller Clock. + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Deinit(void); + +/*! + * @brief Read Fuse value from eFuse word. + * + * This function read fuse data from eFuse word to specified data buffer. + * + * @param addr Fuse address + * @param data Buffer to hold the data read from eFuse word + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Read(uint32_t addr, uint32_t *data); + +/*! + * @brief Program value to eFuse block. + * + * This function program data to specified eFuse address. + * + * @param addr Fuse address + * @param data data to be programmed into eFuse Fuse block + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Program(uint32_t addr, uint32_t data); + +/*! @} */ + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /*! FSL_EFUSE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/fsl_flash.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/fsl_flash.h new file mode 100644 index 000000000..abe32dc18 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/fsl_flash.h @@ -0,0 +1,595 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_FLASH_H_ +#define FSL_FLASH_H_ + +#include "fsl_common.h" +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief ROMAPI_FLASH driver version 2.0.0. */ +#define FSL_ROMAPI_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 1, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ +}; +/*! @} */ + +/*! + * @name Flash driver support feature + * @{ + */ +#define FSL_FEATURE_SYSCON_HAS_FLASH_HIDING 1U + +/*! @} */ + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group) * 100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ + kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, + 0x10), /*!< A correctable or uncorrectable error during command execution. */ + kStatus_FLASH_CompareError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ + kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ + kStatus_FLASH_InvalidWaitStateCycles = + MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ + + kStatus_FLASH_OutOfDateCfpaPage = + MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ + kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ + kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = + MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ + kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( + kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ + kStatus_FLASH_HashCheckError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ + kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ + kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( + kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ + kStatus_FLASH_NmpaAccessNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ + kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ + kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ + kStatus_FLASH_CfpaScratchPageInvalid = + MAKE_STATUS(kStatusGroupFlashDriver, 0x30), /*!< CFPA Scratch Page is invalid*/ + kStatus_FLASH_CfpaVersionRollbackDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x31), /*!< CFPA version rollback is not allowed */ + kStatus_FLASH_ReadHidingAreaDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x32), /*!< Flash hiding read is not allowed */ + kStatus_FLASH_ModifyProtectedAreaDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x33), /*!< Flash firewall page locked erase and program are not allowed */ + kStatus_FLASH_CommandOperationInProgress = MAKE_STATUS( + kStatusGroupFlashDriver, 0x34), /*!< The flash state is busy, indicate that a flash command in progress. */ +}; +/*! @} */ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*! @} */ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ + + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! + * @brief Enumeration for flash max pages to erase. + */ +enum _flash_max_erase_page_value +{ + kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ +}; + +/*! + * @brief Enumeration for flash alignment property. + */ +enum _flash_alignment_property +{ + kFLASH_AlignementUnitVerifyErase = 4U, /*!< The alignment unit in bytes used for verify erase operation.*/ + kFLASH_AlignementUnitProgram = 512U, /*!< The alignment unit in bytes used for program operation.*/ + /*kFLASH_AlignementUnitVerifyProgram = 4U,*/ /*!< The alignment unit in bytes used for verify program operation.*/ + kFLASH_AlignementUnitSingleWordRead = 16U /*!< The alignment unit in bytes used for SingleWordRead command.*/ +}; + +/*! + * @brief Enumeration for flash read ecc option + */ +enum _flash_read_ecc_option +{ + kFLASH_ReadWithEccOn = 0U, /*! ECC is on */ + kFLASH_ReadWithEccOff = 1U /*! ECC is off */ +}; + +/*! + * @brief Enumeration for flash read margin option + */ +enum _flash_read_margin_option +{ + kFLASH_ReadMarginNormal = 0U, /*!< Normal read */ + kFLASH_ReadMarginVsProgram = 1U, /*!< Margin vs. program */ + kFLASH_ReadMarginVsErase = 2U, /*!< Margin vs. erase */ + kFLASH_ReadMarginIllegalBitCombination = 3U /*!< Illegal bit combination */ +}; + +/*! + * @brief Enumeration for flash read dmacc option + */ +enum _flash_read_dmacc_option +{ + kFLASH_ReadDmaccDisabled = 0U, /*!< Memory word */ + kFLASH_ReadDmaccEnabled = 1U /*!< DMACC word */ +}; + +/*! + * @brief Enumeration for flash ramp control option + */ +enum _flash_ramp_control_option +{ + kFLASH_RampControlDivisionFactorReserved = 0U, /*!< Reserved */ + kFLASH_RampControlDivisionFactor256 = 1U, /*!< clk48mhz / 256 = 187.5KHz */ + kFLASH_RampControlDivisionFactor128 = 2U, /*!< clk48mhz / 128 = 375KHz */ + kFLASH_RampControlDivisionFactor64 = 3U /*!< clk48mhz / 64 = 750KHz */ +}; + +/*! @brief Flash ECC log info. */ +typedef struct _flash_ecc_log +{ + uint32_t firstEccEventAddress; + uint32_t eccErrorCount; + uint32_t eccCorrectionCount; + uint32_t reserved; +} flash_ecc_log_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_mode_config +{ + uint32_t sysFreqInMHz; + /* ReadSingleWord parameter. */ + struct + { + uint8_t readWithEccOff : 1; + uint8_t readMarginLevel : 2; + uint8_t readDmaccWord : 1; + uint8_t reserved0 : 4; + uint8_t reserved1[3]; + } readSingleWord; + /* SetWriteMode parameter. */ + struct + { + uint8_t programRampControl; + uint8_t eraseRampControl; + uint8_t reserved[2]; + } setWriteMode; + /* SetReadMode parameter. */ + struct + { + uint16_t readInterfaceTimingTrim; + uint16_t readControllerTimingTrim; + uint8_t readWaitStates; + uint8_t reserved[3]; + } setReadMode; +} flash_mode_config_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t sectorSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; + flash_mode_config_t modeConfig; + uint32_t *nbootCtx; + bool useAhbRead; +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FLASH_Init(flash_config_t *config); + +/*! + * @brief De-Initializes the global flash properties structure members. + * + * This API De-initializes the FLASH default parameters and related FLASH clock for the FLASH and FMC. + * The flash_deinit API should be called after all the other FLASH APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FLASH_Deinit(flash_config_t *config); + +/*! @} */ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * NOTE: The start address need to be 4 Bytes-aligned. + * + * @param lengthInBytes The length, given in bytes need be 4 Bytes-aligned. + * + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*! @} */ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + +/*! + * @name Reading + * @{ + */ + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + +/*! @} */ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param margin Read margin choice. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + +/*! @} */ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*! @} */ + +/*! + * @name CustKeyStore + * @{ + */ + +/*! + * @brief Get the customer key store data from the customer key store region . + * + * @param config Pointer to flash_config_t data structure in memory to store driver runtime state. + * @param pData Pointer to the customer key store data buffer, which got from the customer key store region. + * @param offset Point to the offset value based on the customer key store address(0x3e400) of the device. + * @param len Point to the length of the expected get customer key store data, and the offset + len <= 512B. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FLASH_GetCustKeyStore(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! @} */ + +/*! + * @name flash status + * @{ + */ +#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) +/*! + * @brief Validates the given address range is loaded in the flash hiding region. + * + * @param config A pointer to the storage for the driver runtime state. + * @param startAddress The start address of the desired flash memory to be verified. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed. + */ +status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +#endif + +/*! @} */ + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /* _FLASH_FLASH_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/fsl_flash_ffr.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/fsl_flash_ffr.h new file mode 100644 index 000000000..1c39de6c8 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/fsl_flash_ffr.h @@ -0,0 +1,591 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_FLASH_FFR_H_ +#define FSL_FLASH_FFR_H_ + +#include "fsl_flash.h" + +/*! + * @addtogroup flash_ffr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define FLASH_FFR_MAX_PAGE_SIZE (512u) +#define FLASH_FFR_CUST_ADDRESS (0x200U) +#define FLASH_FFR_CUST_PAGE_NUMBER (15u) + +#define FLASH_FFR_HASH_DIGEST_SIZE (32u) +#define FLASH_FFR_IV_CODE_SIZE (52u) +#define FLASH_FFR_KETBLOB_OFFSET (0x160u) +#define FLASH_FFR_KETBLOB_SIZE (0x30u) +#define CFPA_HEADER_MARKER (0x9635u) +#define CMPA_HEADER_MARKER (0x5963u) +#define FLASH_FFR_UUID_SIZE (16u) +enum flash_ffr_page_offset +{ + kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ + kFfrPageOffset_CFPA_CfgPing = 0, /*!< CFPA Configuration area (Ping page)*/ + kFfrPageOffset_CFPA_CfgPong = 1, /*!< Same as CFPA page (Pong page)*/ + kFfrPageOffset_CMPA_Cfg = 2, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Cfg = 3, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_SBL_Cfg = 4, /*!< SBL recovery programmed area*/ + kFfrPageOffset_B0_IFR1_Visible = 128, /*!< Trim programmed area*/ + +}; + +enum flash_ffr_page_num +{ + kFfrSectorNum_CFPA = 2, /*!< Customer In-Field programmed area*/ + kFfrSectorNum_CMPA = 1, /*!< Customer Manufacturing programmed area*/ + kFfrSectorNum_NMPA = 1, /*!< NXP Manufacturing programmed area*/ + kFfrSectorNum_SBL = 4, /*!< SBL Cus programmed area*/ + kFfrSectorNum_Total = (kFfrSectorNum_CFPA + kFfrSectorNum_CMPA + kFfrSectorNum_NMPA + kFfrSectorNum_SBL), +}; + +enum flash_ffr_block_size +{ + kFfrBlockSize_Key = 52u, + kFfrBlockSize_ActivationCode = 1000u, +}; + +enum cfpa_cfg_cmpa_prog_status +{ + kFfrCmpaProgStatus_Idle = 0x0u, + kFfrCmpaProgStatus_InProgress = 0x5CC55AA5u, +}; + +typedef enum +{ + kFfrCmpaProgProcess_Pre = 0x0u, + kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, +} cmpa_prog_process_t; + +typedef struct +{ + struct + { + uint32_t cfpa_lc_state : 8; + uint32_t cfpa_lc_state_inv : 8; + uint32_t header_marker : 16; + } header; //!< [0x000-0x003] + + struct //!< [0x004-0x007] + { + uint32_t version : 24; //!< cfpa version + uint32_t img_upd : 2; //!< image cmac update + uint32_t reserved0 : 1; + uint32_t cmpa_update : 3; //!< CFPA page updated through SB command. + uint32_t dice_alias_key_upd : 1; + uint32_t dice_en : 1; //!< Update DICE certificate during next boot + } cfpa_page_version; + + uint32_t secureFwVersion; //!< [0x008-0x00b] + uint32_t nsFwVersion; //!< [0x00c-0x00f] + uint32_t recFwVersion; //!< [0x010-0x013] + uint32_t secBootFlags; //!< [0x014-0x01f] + uint32_t imageKeyRevoke; //!< [0x018-0x01b] + uint32_t lpVectorAddr; //!< [0x01c-0x01f] + uint32_t vendorUsage; //!< [0x020-0x02f] + uint32_t dcfgNsPin; //!< [0x024-0x027] + uint32_t dcfgNsDflt; //!< [0x028-0x02b] + uint32_t reserved0; //!< [0x02c-0x02f] + uint32_t ivPrince[4]; //!< [0x030-0x03f] + uint32_t ivIped[8]; //!< [0x040-0x05f] + + uint32_t errCnt[8]; //!< [0x060-0x07f] + + uint32_t custCtr[8]; //!< [0x080-0x09f] + uint32_t mflagCtr[8]; //!< [0x0a0-0x0bf] + uint32_t flashAcl[8]; //!< [0x0C0-0x0Df] + uint32_t sblImg0Cmac[4]; //!< [0x0E0-0x0Ef] + uint32_t img1Cmac[4]; //!< [0x0F0-0x0Ff] + uint32_t diceCert[36]; //!< [0x100-0x18f] + uint32_t reserved2[23]; //!< [0x190-0x1eb] + uint32_t cfpaCrc; //!< [0x1ec-0x1ef] + uint32_t cfpaCmac[4]; //!< [0x1f0-0x1ff] +} cfpa_cfg_info_t; + +#define FFR_BOOTCFG_USBSPEED_SHIFT (9U) +#define FFR_BOOTCFG_USBSPEED_MASK (0x3u << FFR_BOOTCFG_USBSPEED_SHIFT) +#define FFR_BOOTCFG_USBSPEED_NMPASEL0 (0x0U) +#define FFR_BOOTCFG_USBSPEED_FS (0x1U) +#define FFR_BOOTCFG_USBSPEED_HS (0x2U) +#define FFR_BOOTCFG_USBSPEED_NMPASEL3 (0x3U) + +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) +#define FFR_BOOTCFG_BOOTSPEED_NMPASEL (0x0U) +#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x1U) +#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x2U) + +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_PRODUCTID_SHIFT (16U) + +#define FFR_IMAGE0_CMAC_UPDATE_MASK (0x1) +#define FFR_IMAGE1_CMAC_UPDATE_MASK (0x2) + +#define FFR_IFR1_PUF_AC_CODE_ADDR (0x01100200UL) +#define FFR_IFR1_PUF_AC_CODE_LEN (1024UL) + +#define FFR_IFR1_NXP_CERT_ADDR (0x01100600UL) +#define FFR_IFR1_NXP_CERT_LEN (1448UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY0_ADDR (0x01101900UL) +#define FFR_IFR1_ROM_PATCH_ARRAY0_LEN (1792UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY1_ADDR (0x01102000UL) +#define FFR_IFR1_ROM_PATCH_ARRAY1_LEN (3584UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY2_ADDR (0x01103000UL) +#define FFR_IFR1_ROM_PATCH_ARRAY2_LEN (2048UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY3_ADDR (0x01103800UL) +#define FFR_IFR1_ROM_PATCH_ARRAY3_LEN (2048UL) + +#define FFR_IFR1_NXP_WRITEABLE_REGION0_START (FFR_IFR1_PUF_AC_CODE_ADDR) +#define FFR_IFR1_NXP_WRITEABLE_REGION0_END \ + (FFR_IFR1_PUF_AC_CODE_ADDR + FFR_IFR1_PUF_AC_CODE_LEN + FFR_IFR1_NXP_CERT_LEN) +#define FFR_IFR1_NXP_WRITEABLE_REGION1_START (FFR_IFR1_ROM_PATCH_ARRAY0_ADDR) +#define FFR_IFR1_NXP_WRITEABLE_REGION1_END \ + (FFR_IFR1_ROM_PATCH_ARRAY0_ADDR + FFR_IFR1_ROM_PATCH_ARRAY0_LEN + FFR_IFR1_ROM_PATCH_ARRAY1_LEN) +#define FFR_IFR1_NXP_WRITEABLE_REGION2_START (FFR_IFR1_ROM_PATCH_ARRAY2_ADDR) +#define FFR_IFR1_NXP_WRITEABLE_REGION2_END \ + (FFR_IFR1_ROM_PATCH_ARRAY2_ADDR + FFR_IFR1_ROM_PATCH_ARRAY2_LEN + FFR_IFR1_ROM_PATCH_ARRAY3_LEN) + +typedef struct +{ + struct + { + uint32_t boot_src : 2; + uint32_t rsv0 : 2; + uint32_t isp_boot_if : 3; + uint32_t rsv1 : 1; + uint32_t rec_boot_src : 2; + uint32_t rsv2 : 2; + uint32_t boot_speed : 2; + uint32_t rsv3 : 2; + uint32_t header_marker : 16; + } bootCfg; //!< [0x000-0x003] + + struct + { + uint32_t flash_remap_size : 5; + uint32_t bank1_ifr0_usage : 3; + uint32_t reserved : 24; + } FlashCfg; //!< [0x004-0x007] + + struct + { + uint8_t recLed; + uint8_t ispLed; + uint8_t bootFailLed; + uint8_t resv0; + } bootLedStatus; //!< [0x008-0x00b] + + struct + { + uint16_t powerDnTimeout; + uint16_t wdogTimeout; + } bootTimers; //!< [0x00c-0x00f] + + uint32_t resv2; //!< [0x010-0x013] + uint32_t resv3; //!< [0x014-0x017] + + uint32_t recSpiFlashCfg0; //!< [0x018-0x01b] + uint32_t recSpiFlashCfg1; //!< [0x01c-0x01f] + + uint32_t isp_uart_cfg; //!< [0x020-0x023] + uint32_t isp_i2c_cfg; //!< [0x024-0x027] + uint32_t isp_can_cfg; //!< [0x028-0x02b] + uint32_t isp_spi_cfg0; //!< [0x02c-0x02f] + uint32_t isp_spi_cfg1; //!< [0x030-0x034] + + struct + { + uint16_t vid; + uint16_t pid; + } usbId; //!< [0x034-0x037] + + uint32_t isp_usb_cfg; //!< [0x038-0x038] + uint32_t isp_misc_cfg; //!< [0x03c-0x03f] + uint32_t dcfgPin; //!< [0x040-0x043] + uint32_t dcfgDflt; //!< [0x044-0x047] + uint32_t dapVendorUsage; //!< [0x048-0x04b] + uint32_t resv1; //!< [0x04c-0x04f] + uint32_t secureBootCfg; //!< [0x050-0x053] + uint32_t rokthUsage; //!< [0x054-0x057] + uint32_t resv4; //!< [0x058-0x05b] + uint32_t resv5; //!< [0x05c-0x05f] + uint32_t rotkh[12]; //!< [0x060-0x08f] + + struct + { + uint32_t npx_w0; + uint32_t npx_w1; + } princeSr[4]; //!< [0x090-0x0af] + + struct + { + uint32_t ipedStartAddr; + uint32_t ipedEndAddr; + } ipedRegions[8]; //!< [0x0b0-0x11f] + + uint32_t rec_img_exit0; + uint32_t rec_img_exit1; + + uint32_t resv6[10]; + + struct + { + uint32_t set0; + uint32_t clr0; + } quickSetGpio[6]; //!< [0x120-0x14f] + + uint32_t resv7[4]; //!< [0x150-0x15f] + uint32_t cust_key_blob[12]; //!< [0x160-0x18f] + + uint32_t resv8[23]; //!< [0x190-0x1eb] + uint32_t cmpaCrc; //!< [0x1ec-0x1ef] + uint32_t cmpaCmac[4]; //!< [0x1f0-0x1ff] + +} cmpa_cfg_info_t; + +typedef struct +{ + uint32_t header; + uint8_t reserved[4]; +} cmpa_key_store_header_t; + +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) + +#define FFR_USBCFG_USBSPEED_HS (0x0U) +#define FFR_USBCFG_USBSPEED_FS (0x1U) +#define FFR_USBCFG_USBSPEED_NO (0x2U) + +#define FFR_MCAN_BAUDRATE_MASK (0xF0000U) +#define FFR_MCAN_BAUDRATE_SHIFT (16U) + +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) + +#define FFR_PUF_SRAM_CONFIG_MASK (0x3FFFF07) +#define FFR_PUF_SRAM_CONFIG_MASK_SHIFT (0U) +#define FFR_PUF_SRAM_VALID_MASK (0x1U) +#define FFR_PUF_SRAM_VALID_SHIFT (0U) +#define FFR_PUF_SRAM_MODE_MASK (0x2U) +#define FFR_PUF_SRAM_MODE_SHIFT (1U) +#define FFR_PUF_SRAM_CKGATING_MASK (0x4U) +#define FFR_PUF_SRAM_CKGATING_SHIFT (2) +#define FFR_PUF_SRAM_SMB_MASK (0x300U) +#define FFR_PUF_SRAM_SMB_SHIFT (8U) +#define FFR_PUF_SRAM_RM_MASK (0x1C00U) +#define FFR_PUF_SRAM_RM_SHIFT (10U) +#define FFR_PUF_SRAM_WM_MASK (0xE000U) +#define FFR_PUF_SRAM_WM_SHIFT (13U) +#define FFR_PUF_SRAM_WRME_MASK (0x10000U) +#define FFR_PUF_SRAM_WRME_SHIFT (16U) +#define FFR_PUF_SRAM_RAEN_MASK (0x20000U) +#define FFR_PUF_SRAM_RAEN_SHIFT (17U) +#define FFR_PUF_SRAM_RAM_MASK (0x3C0000U) +#define FFR_PUF_SRAM_RAM_SHIFT (18U) +#define FFR_PUF_SRAM_WAEN_MASK (0x400000U) +#define FFR_PUF_SRAM_WAEN_SHIFT (22U) +#define FFR_PUF_SRAM_WAM_MASK (0x1800000U) +#define FFR_PUF_SRAM_WAM_SHIFT (23U) +#define FFR_PUF_SRAM_STBP_MASK (0x2000000U) +#define FFR_PUF_SRAM_STBP_SHIFT (25U) + +typedef struct +{ + uint32_t fro32kCfg; //!< [0x000-0x003] + uint32_t puf_cfg; //!< [0x004-0x007] + uint32_t bod; //!< [0x008-0x00b] + uint32_t trim; //!< [0x00c-0x00f] + uint32_t deviceID; //!< [0x010-0x03f] + uint32_t peripheralCfg; //!< [0x014-0x017] + uint32_t dcdPowerProFileLOW[2]; //!< [0x018-0x01f] + uint32_t deviceType; //!< [0x020-0x023] + uint32_t ldo_ao; //!< [0x024-0x027] + uint32_t gdetDelayCfg; //!< [0x028-0x02b] + uint32_t gdetMargin; //!< [0x02c-0x02f] + uint32_t gdetTrim1; //!< [0x030-0x033] + uint32_t gdetEanble1; //!< [0x034-0x037] + uint32_t gdetCtrl1; //!< [0x038-0x03b] + uint32_t gdetUpdateTimer; //!< [0x03c-0x03f] + uint32_t GpoDataChecksum[4]; //!< [0x040-0x04f] + uint32_t finalTestBatchId[4]; //!< [0x050-0x05f] + uint32_t ecidBackup[4]; //!< [0x060-0x06f] + uint32_t uuid[4]; //!< [0x070-0x07f] + uint32_t reserved1[7]; //!< [0x080-0x09b] + struct + { + uint8_t xo32mReadyTimeoutInMs; + uint8_t usbSpeed; + uint8_t reserved[2]; + } usbCfg; //!< [0x09c-0x09f] + uint32_t reserved2[80]; //!< [0x0a0-0x1df] + uint8_t cmac[16]; //!< [0x1e0-0x1ef] + uint32_t pageChecksum[4]; //!< [0x1f0-0x1ff] +} nmpa_cfg_info_t; + +typedef struct +{ + uint8_t reserved[1][FLASH_FFR_MAX_PAGE_SIZE]; +} ffr_key_store_t; + +typedef enum +{ + kFFR_KeyTypeSbkek = 0x00U, + kFFR_KeyTypeUser = 0x01U, + kFFR_KeyTypeUds = 0x02U, + kFFR_KeyTypePrinceRegion0 = 0x03U, + kFFR_KeyTypePrinceRegion1 = 0x04U, + kFFR_KeyTypePrinceRegion2 = 0x05U, +} ffr_key_type_t; + +typedef enum +{ + kFFR_BankTypeBank0_CFPA0 = 0x00u, + kFFR_BankTypeBank0_CFPA1 = 0x01u, + kFFR_BankTypeBank0_CMPA = 0x02U, + kFFR_BankTypeBank0_NMPA = 0x03U, + kFFR_BankTypeBank0_SBL = 0x04U, + +} ffr_bank_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FFR APIs + * @{ + */ + +/*! + * @brief Initializes the global FFR properties structure members. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + */ +status_t FFR_Init(flash_config_t *config); + +/*! + * @brief Enable firewall for all flash banks. + * + * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; + * Unless the board is reset again. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + */ +status_t FFR_Lock(flash_config_t *config); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the CFPA. + * @param valid_len The length, given in bytes, to be programmed. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_SizeError Error size + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + +/*! + * @brief APIs to access CFPA pages + * + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. + * @param offset An offset from the 'Customer In-field Page' start address. + * @param len The length, given in bytes, to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA pages + * + * This routine will erase "customer factory page" and program the page with passed data. + * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of + * the page contents and then programs the pages. + * 1.During development customer code uses this API with 'seal_part' set to FALSE. + * 2.During manufacturing this parameter should be set to TRUE to seal the part + * from further modifications + * 3.This routine checks if the page is sealed or not. A page is said to be sealed if + * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for + * the region if hash is programmed anyways. So, write/erase commands will fail eventually. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the "customer factory page". + * @param seal_part Set fasle for During development customer code. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_Fail Generic status for Fail. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); + +/*! + * @brief APIs to access CMPA page + * + * Read data stored in 'Customer Factory CFG Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C + * 0x3e600), and the API should be called after the FLASH_Init and FFR_Init. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AddressError Address is out of range + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A pointer to the source buffer of data that is to be programmed + * into the "Key store". + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_SealedFfrRegion The FFR region is sealed. + * @retval #kStatus_FLASH_FfrBankIsLocked The FFR bank region is locked. + * @retval #kStatus_FLASH_AddressError Address is out of range + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + */ +status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*! + * @brief APIs to access CMPA page + * + * 1.SW should use this API routine to get the UUID of the chip. + * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +/*! @} */ + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /*! FSL_FLASH_FFR_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/src/fsl_flash.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/src/fsl_flash.c new file mode 100644 index 000000000..aa8f35a56 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/flash/src/fsl_flash.c @@ -0,0 +1,423 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flashiap" +#endif + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303e000u) + +/*! + * @name flash, ffr Structure + * @{ + */ + +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*isFlashAreaReadable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); + status_t (*isFlashAreaModifiable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +} function_command_option_t; + +/*! + * @brief Structure of version property. + * + * @ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number. */ + /* Flash driver */ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + const uint32_t reserved0[3]; + + /*!< Flash FFR driver */ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_cust_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t reserved1; + status_t reserved2; + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_read)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + const uint32_t reserved3; + status_t (*flash_get_cust_keystore)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_deinit)(flash_config_t *config); +} flash_driver_interface_t; + +/* !@brief EFUSE driver API Interface */ +typedef struct +{ + standard_version_t version; + status_t (*init)(void); + status_t (*deinit)(void); + status_t (*read)(uint32_t addr, uint32_t *data); + status_t (*program)(uint32_t addr, uint32_t data); +} efuse_driver_t; + +/*! @}*/ + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + standard_version_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const flash_driver_interface_t *flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const uint32_t reserved2; /*!< reserved*/ + const efuse_driver_t *efuseDriver; /*!< eFuse driver API */ + const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ +} bootloader_tree_t; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************** + * Internal Flash driver API + *******************************************************************************/ +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + */ +status_t FLASH_Init(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_init(config); +} + +/*! + * @brief De-Initializes the global flash properties structure members. + * + * This API De-initializes the FLASH default parameters and related FLASH clock for the FLASH and FMC. + */ +status_t FLASH_Deinit(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_deinit(config); +} + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase(config, start, lengthInBytes, key); +} + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program(config, start, src, lengthInBytes); +} + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_erase(config, start, lengthInBytes); +} + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_read(config, start, dest, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program(config, start, lengthInBytes, expectedData, + failedAddress, failedData); +} + +/*! + * @brief Returns the desired flash property. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_property(config, whichProperty, value); +} + +status_t FLASH_GetCustKeyStore(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_cust_keystore(config, pData, offset, len); +} + +#if defined(BL_FEATURE_HAS_BUS_CRYPTO_ENGINE) && BL_FEATURE_HAS_BUS_CRYPTO_ENGINE +status_t FLASH_ErasePrologue(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase_with_checker(config, start, lengthInBytes, key); +} + +status_t FLASH_ProgramPrologue(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program_with_checker(config, start, src, lengthInBytes); +} + +status_t FLASH_VerifyProgramPrologue(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program_with_checker( + config, start, lengthInBytes, expectedData, failedAddress, failedData); +} + +#endif // BL_FEATURE_HAS_BUS_CRYPTO_ENGINE + +#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) +/*! + * @brief Validates the given address range is loaded in the flash hiding region. + */ +status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes) +{ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x130366f9u; + return runCmdFuncOption.isFlashAreaReadable(config, startAddress, lengthInBytes); +} +#endif + +/******************************************************************************** + * fsl iap ffr CODE + *******************************************************************************/ + +/*! + * @brief Initializes the global FFR properties structure members. + */ +status_t FFR_Init(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_init(config); +} + +/*! + * @brief Enable firewall for all flash banks. + */ +status_t FFR_Lock(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_lock(config); +} + +/*! + * @brief APIs to access CMPA pages; + * This routine will erase "customer factory page" and program the page with passed data. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_factory_page_write(config, page_data, seal_part); +} + +/*! + * @brief See fsl_iap_ffr.h for documentation of this function. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_uuid(config, uuid); +} + +/*! + * @brief APIs to access CMPA pages + * Read data stored in 'Customer Factory CFG Page'. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_data(config, pData, offset, len); +} + +/*! + * @brief This routine writes the 3 pages allocated for Key store data. + */ +status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_keystore_write(config, pKeyStore); +} + +/*! + * @brief APIs to access CFPA pages + * This routine will erase CFPA and program the CFPA page with passed data. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_infield_page_write(config, page_data, valid_len); +} + +/*! + * @brief APIs to access CFPA pages + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_infield_data(config, pData, offset, len); +} + +/*! + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C + * 0x3e600), and the API should be called after the FLASH_Init and FFR_Init. + */ +status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_cust_keystore(config, pData, offset, len); +} + +/******************************************************************************** + * EFUSE driver API + *******************************************************************************/ + +/*! + * @brief Initialize EFUSE controller. + */ +status_t EFUSE_Init(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->efuseDriver->init(); +} + +/*! + * @brief De-Initialize EFUSE controller. + */ +status_t EFUSE_Deinit(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->efuseDriver->deinit(); +} + +/*! + * @brief Read Fuse value from eFuse word. + */ +status_t EFUSE_Read(uint32_t addr, uint32_t *data) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->efuseDriver->read(addr, data); +} + +/*! + * @brief Program value to eFuse block. + */ +status_t EFUSE_Program(uint32_t addr, uint32_t data) +{ + assert(BOOTLOADER_API_TREE_POINTER); + status_t status; + bool is_hvd_enabled = false; + + /* Workaround for ROM Errata ERR052108 */ + /* Disable SYS_HVD */ + if (0U != (SPC0->ACTIVE_CFG & SPC_ACTIVE_CFG_SYS_HVDE_MASK)) + { + is_hvd_enabled = true; + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + /* Call ROM API to program efuse */ + status = BOOTLOADER_API_TREE_POINTER->efuseDriver->program(addr, data); + + /* Bring VDD_SYS back to 1.8v */ + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK; + + /* Wait for voltage to settle */ + SDK_DelayAtLeastUs(5000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Enable SYS_HVD back */ + if (is_hvd_enabled) + { + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + return status; +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/fsl_mem_interface.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/fsl_mem_interface.h new file mode 100644 index 000000000..d24bed2d6 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/fsl_mem_interface.h @@ -0,0 +1,385 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_MEM_INTERFACE_H_ +#define FSL_MEM_INTERFACE_H_ + +#include "fsl_sbloader.h" +#include "fsl_common.h" + +/*! + * @addtogroup memory_interface + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ROMAPI_MEM_INTERFACE driver version 2.0.0. */ +#define FSL_ROMAPI_MEM_INTERFACE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Bit mask for device ID. */ +#define DEVICE_ID_MASK (0xffU) +/*! @brief Bit position of device ID. */ +#define DEVICE_ID_SHIFT 0U +/*! @brief Bit mask for group ID. */ +#define GROUP_ID_MASK (0xf00U) +/*! @brief Bit position of group ID. */ +#define GROUP_ID_SHIFT 8U + +/*! @brief Construct a memory ID from a given group ID and device ID. */ +#define MAKE_MEMORYID(group, device) \ + ((((group) << GROUP_ID_SHIFT) & GROUP_ID_MASK) | (((device) << DEVICE_ID_SHIFT) & DEVICE_ID_MASK)) +/*! @brief Get group ID from a given memory ID. */ +#define GROUPID(memoryId) (((memoryId) & GROUP_ID_MASK) >> GROUP_ID_SHIFT) + +/*! @brief Get device ID from a given memory ID. */ +#define DEVICEID(memoryId) (((memoryId) & DEVICE_ID_MASK) >> DEVICE_ID_SHIFT) + +/*! @brief Memory group definition. */ +enum +{ + kMemoryGroup_Internal = 0U, /*!< Memory belongs internal 4G memory region. */ + kMemoryGroup_External = 1U, /*!< Memory belongs external memory region. */ +}; + +/*! @brief Memory device ID definition. */ +enum +{ + /* Memory ID bitfiled definition. + | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + | Reserved | INT/EXT | Type | Sub-Type | + | | 0: INT | INT: | | + | | 1: EXT | 0: NorFlash0 | 0: Internal Flash(FTFX) | + | | | | 1: QSPI | + | | | | 4: IFR | + | | | | 5: LPC FFR | + | | | | 8: SEMC | + | | | | 9: FlexSPI | + | | | | others: Unused | + | | | | | + | | | 1: ExecuteOnlyRegion | 0: Internal Flash(FTFX) | + | | | | others: Unused | + | | | | | + | | | others: Unused | | + | | | | | + | | | EXT: | | + | | | 0: NandFlash | 0: SEMC | + | | | | 1: FlexSPI | + | | | | others: Unused | + | | | | | + | | | 1: NorFlash/EEPROM | 0: LPSPI | + | | | | 1: LPI2C | + | | | | others: Unused | + | | | | | + | | | 2: SD/SDHC/SDXC/MMC/eMMC | 0: uSDHC SD | + | | | | 1: uSDHC MMC | + | | | | others: Unused | + | | | others: Unused | | + + INT : Internal 4G memory, including internal memory modules, and XIP external memory modules. + EXT : Non-XIP external memory modules. + */ + kMemoryInternal = MAKE_MEMORYID(kMemoryGroup_Internal, 0U), /*!< Internal memory (include all on chip memory) */ + kMemoryQuadSpi0 = MAKE_MEMORYID(kMemoryGroup_Internal, 1U), /*!< Qsuad SPI memory 0 */ + kMemoryIFR0 = + MAKE_MEMORYID(kMemoryGroup_Internal, 4U), /*!< Nonvolatile information register 0. Only used by SB loader. */ + kMemoryFFR = MAKE_MEMORYID(kMemoryGroup_Internal, 5U), /*!< LPCc040hd flash FFR region. */ + kMemorySemcNor = MAKE_MEMORYID(kMemoryGroup_Internal, 8U), /*!< SEMC Nor memory */ + kMemoryFlexSpiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 9U), /*!< Flex SPI Nor memory */ + kMemorySpifiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 0xAU), /*!< SPIFI Nor memory */ + kMemoryFlashExecuteOnly = MAKE_MEMORYID(kMemoryGroup_Internal, 0x10U), /*!< Execute-only region on internal Flash */ + + kMemorySemcNand = MAKE_MEMORYID(kMemoryGroup_External, 0U), /*!< SEMC NAND memory */ + kMemorySpiNand = MAKE_MEMORYID(kMemoryGroup_External, 1U), /*!< SPI NAND memory */ + kMemorySpiNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x10U), /*!< SPI NOR/EEPROM memory */ + kMemoryI2cNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x11U), /*!< I2C NOR/EEPROM memory */ + kMemorySDCard = MAKE_MEMORYID(kMemoryGroup_External, 0x20U), /*!< eSD, SD, SDHC, SDXC memory Card */ + kMemoryMMCCard = MAKE_MEMORYID(kMemoryGroup_External, 0x21U), /*!< MMC, eMMC memory Card */ +}; + +/*! @brief Bootloader status group numbers. + * + * @ingroup bl_core + */ +enum +{ + kStatusGroup_Bootloader = 100, /*!< Bootloader status group number (100). */ + kStatusGroup_MemoryInterface = 102, /*!< Memory interface status group number (102). */ +}; + +/*! @brief Memory interface status codes. */ +enum +{ + kStatusMemoryRangeInvalid = MAKE_STATUS(kStatusGroup_MemoryInterface, 0), + kStatusMemoryReadFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 1), + kStatusMemoryWriteFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 2), + kStatusMemoryCumulativeWrite = MAKE_STATUS(kStatusGroup_MemoryInterface, 3), + kStatusMemoryAppOverlapWithExecuteOnlyRegion = MAKE_STATUS(kStatusGroup_MemoryInterface, 4), + kStatusMemoryNotConfigured = MAKE_STATUS(kStatusGroup_MemoryInterface, 5), + kStatusMemoryAlignmentError = MAKE_STATUS(kStatusGroup_MemoryInterface, 6), + kStatusMemoryVerifyFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 7), + kStatusMemoryWriteProtected = MAKE_STATUS(kStatusGroup_MemoryInterface, 8), + kStatusMemoryAddressError = MAKE_STATUS(kStatusGroup_MemoryInterface, 9), + kStatusMemoryBlankCheckFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 10), + kStatusMemoryBlankPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 11), + kStatusMemoryProtectedPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 12), + kStatusMemoryFfrSpecRegionWriteBroken = MAKE_STATUS(kStatusGroup_MemoryInterface, 13), + kStatusMemoryUnsupportedCommand = MAKE_STATUS(kStatusGroup_MemoryInterface, 14), +}; + +/*! @brief Bootloader status codes. */ +enum +{ + kStatus_UnknownCommand = MAKE_STATUS(kStatusGroup_Bootloader, 0), + kStatus_SecurityViolation = MAKE_STATUS(kStatusGroup_Bootloader, 1), + kStatus_AbortDataPhase = MAKE_STATUS(kStatusGroup_Bootloader, 2), + kStatus_Ping = MAKE_STATUS(kStatusGroup_Bootloader, 3), + kStatus_NoResponse = MAKE_STATUS(kStatusGroup_Bootloader, 4), + kStatus_NoResponseExpected = MAKE_STATUS(kStatusGroup_Bootloader, 5), + kStatus_CommandUnsupported = MAKE_STATUS(kStatusGroup_Bootloader, 6), +}; + +/*! + * @brief Interface to memory operations. + * + * This is the main abstract interface to all memory operations. + */ +typedef struct +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer, uint32_t memoryId); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer, uint32_t memoryId); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*finalize)(void); + status_t (*erase)(uint32_t address, uint32_t length, uint32_t memoryId); +} memory_interface_t; + +/*! @brief Interface to memory operations for one region of memory. */ +typedef struct +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*erase)(uint32_t address, uint32_t length); + status_t (*config)(uint32_t *buffer); + status_t (*erase_all)(void); +} memory_region_interface_t; + +//! @brief Structure of a memory map entry. +typedef struct +{ + uint32_t startAddress; + uint32_t endAddress; + uint32_t memoryProperty; + uint32_t memoryId; + const memory_region_interface_t *memoryInterface; +} memory_map_entry_t; + +/*! @brief Structure of version property. */ +typedef union StandardVersion +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ +} standard_version_t; + +/*! @brief API initialization data structure */ +typedef struct kb_api_parameter_struct +{ + uint32_t allocStart; + uint32_t allocSize; +} kp_api_init_param_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +standard_version_t API_Version(void); + +/*! @brief Initialize the IAP API runtime environment */ +status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param); + +/*! @brief Deinitialize the IAP API runtime environment */ +status_t API_Deinit(api_core_context_t *coreCtx); + +/*! + * @brief Initialize memory interface. + * + * @retval #kStatus_Fail + * @retval #kStatus_Success + */ +status_t MEM_Init(api_core_context_t *coreCtx); + +/*! + * @brief Configure memory interface + * + * @param config A pointer to the storage for the driver runtime state. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport +*/ +status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId); + +/*! + * @brief Write memory. + * + * @param address The start address of the desired flash memory to be programmed. + For internal flash the address need to be 512bytes-aligned. + * @param length Number of bytes to be programmed. + * @param buffer A pointer to the source buffer of data that is to be programmed into the flash. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + * @retval #kStatus_FLASH_CompareError + * @retval #kStatusMemoryNotConfigured + * @retval #kStatusMemoryVerifyFailed + */ +status_t MEM_Write( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId); + +/*! + * @brief Fill memory with a word pattern. + * + * @param address The start address of the desired flash memory to be programmed. + * For internal flash the address need to be 512bytes-aligned. + * @param length Number of bytes to be programmed. + * @param pattern The data to be written into the specified memory area. + * + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_Success + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_Fail + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + */ +status_t MEM_Fill( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId); + +/*! + * @brief Flush memory. + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + * @retval #kStatusMemoryVerifyFailed + */ +status_t MEM_Flush(api_core_context_t *coreCtx); + +/*! + * @brief Erase memory. + * + * @param address The start address of the desired flash memory to be erased. + * @param length Number of bytes to be read. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatusMemoryAddressError + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_EraseKeyError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_Fail + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatusMemoryNotConfigured + * @retval #kStatusMemoryVerifyFailed + + */ +status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId); + +/*! + * @brief Erase entire memory based on memoryId + * + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_EraseKeyError + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryVerifyFailed + * @retval #kStatusMemoryNotConfigured + * @retval #kStatus_InvalidArgument + */ +status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* FSL_MEM_INTERFACE_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/fsl_sbloader.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/fsl_sbloader.h new file mode 100644 index 000000000..917217142 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/fsl_sbloader.h @@ -0,0 +1,368 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_SBLOADER_H_ +#define FSL_SBLOADER_H_ + +#include "fsl_flash.h" +#include "fsl_sbloader_v4.h" +#include "fsl_common.h" +/*! + * @addtogroup sbloader + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Determines the version of SB loader implementation (1: sb1.0; 2: sb2.0; 3.1: sb3.1, ; 4: sb4.0) */ +#define SB_FILE_MAJOR_VERSION (4) +#define SB_FILE_MINOR_VERSION (0) + +/*! @brief Bootloader status group numbers */ +#define kStatusGroup_SBLoader (101U) + +/*! @brief Contiguous RAM region count */ +#define RAM_REGION_COUNT (2U) + +/*! @brief Contiguous FLASH region count */ +#define FLASH_REGION_COUNT (1U) + +/*! @brief Contiguous FFR region count */ +#define FFR_REGION_COUNT (1U) + +/*! @brief Memory Interface count */ +#define MEM_INTERFACE_COUNT (3U) + +/*! @brief Contiguous FLEXSPINOR meomry count */ +#define FLEXSPINOR_REGION_COUNT (1U) + +/*! @brief SB loader status codes.*/ +enum +{ + kStatusRomLdrSectionOverrun = MAKE_STATUS(kStatusGroup_SBLoader, 0), + kStatusRomLdrSignature = MAKE_STATUS(kStatusGroup_SBLoader, 1), + kStatusRomLdrSectionLength = MAKE_STATUS(kStatusGroup_SBLoader, 2), + kStatusRomLdrUnencryptedOnly = MAKE_STATUS(kStatusGroup_SBLoader, 3), + kStatusRomLdrEOFReached = MAKE_STATUS(kStatusGroup_SBLoader, 4), + kStatusRomLdrChecksum = MAKE_STATUS(kStatusGroup_SBLoader, 5), + kStatusRomLdrCrc32Error = MAKE_STATUS(kStatusGroup_SBLoader, 6), + kStatusRomLdrUnknownCommand = MAKE_STATUS(kStatusGroup_SBLoader, 7), + kStatusRomLdrIdNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 8), + kStatusRomLdrDataUnderrun = MAKE_STATUS(kStatusGroup_SBLoader, 9), + kStatusRomLdrJumpReturned = MAKE_STATUS(kStatusGroup_SBLoader, 10), + kStatusRomLdrCallFailed = MAKE_STATUS(kStatusGroup_SBLoader, 11), + kStatusRomLdrKeyNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 12), + kStatusRomLdrSecureOnly = MAKE_STATUS(kStatusGroup_SBLoader, 13), + kStatusRomLdrResetReturned = MAKE_STATUS(kStatusGroup_SBLoader, 14), + + kStatusRomLdrRollbackBlocked = MAKE_STATUS(kStatusGroup_SBLoader, 15), + kStatusRomLdrInvalidSectionMacCount = MAKE_STATUS(kStatusGroup_SBLoader, 16), + kStatusRomLdrUnexpectedCommand = MAKE_STATUS(kStatusGroup_SBLoader, 17), + kStatusRomLdrBadSBKEK = MAKE_STATUS(kStatusGroup_SBLoader, 18), + kStatusRomLdrPendingJumpCommand = MAKE_STATUS(kStatusGroup_SBLoader, 19), +}; + +/*! + * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by + * the encryption algorithm. + */ +#define BYTES_PER_CHUNK 16 + +#define SB_SECTION_COUNT_MAX 8 + +/*! @brief Boot image signature in 32-bit little-endian format "PMTS" */ +#define BOOT_SIGNATURE 0x504d5453 + +/*! @brief Boot image signature in 32-bit little-endian format "ltgs" */ +#define BOOT_SIGNATURE2 0x6c746773 + +/*! @brief These define file header flags */ +#define FFLG_DISPLAY_PROGRESS 0x0001 + +/*! @brief These define section header flags */ +#define SFLG_SECTION_BOOTABLE 0x0001 + +/*! @brief These define boot command flags */ +#define CFLG_LAST_TAG 0x01 + +/*! @brief ROM_ERASE_CMD flags */ +#define ROM_ERASE_ALL_MASK 0x01 +#define ROM_ERASE_ALL_UNSECURE_MASK 0x02 + +/*! @brief ROM_JUMP_CMD flags */ +#define ROM_JUMP_SP_MASK 0x02 + +/*! @brief Memory device id shift at sb command flags */ +#define ROM_MEM_DEVICE_ID_SHIFT 0x8 + +/*! @brief Memory device id mask */ +#define ROM_MEM_DEVICE_ID_MASK 0xff00 + +/*! @brief Memory group id shift at sb command flags */ +#define ROM_MEM_GROUP_ID_SHIFT 0x4 + +/*! @brief Memory group id flags mask */ +#define ROM_MEM_GROUP_ID_MASK 0xf0 + +/*! @brief ROM_PROG_CMD flags */ +#define ROM_PROG_8BYTE_MASK 0x01 + +/*! @brief These define the boot command tags */ +#define ROM_NOP_CMD 0x00 +#define ROM_TAG_CMD 0x01 +#define ROM_LOAD_CMD 0x02 +#define ROM_FILL_CMD 0x03 +#define ROM_JUMP_CMD 0x04 +#define ROM_CALL_CMD 0x05 +#define ROM_MODE_CMD 0x06 +#define ROM_ERASE_CMD 0x07 +#define ROM_RESET_CMD 0x08 +#define ROM_MEM_ENABLE_CMD 0x09 +#define ROM_PROG_CMD 0x0a +#define ROM_FW_VER_CHK 0x0b + +#if SB_FILE_MAJOR_VERSION == 2 +#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V2_CMD_SET_IN_ISP_MODE) +#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V2_CMD_SET_IN_REC_MODE) +#elif SB_FILE_MAJOR_VERSION == 3 +#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V3_CMD_SET_IN_ISP_MODE) +#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V3_CMD_SET_IN_REC_MODE) +#elif SB_FILE_MAJOR_VERSION == 4 +#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V4_CMD_SET_IN_ISP_MODE) +#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V4_CMD_SET_IN_REC_MODE) +#endif + +/*! @brief Plugin return codes */ +#define ROM_BOOT_SECTION_ID 1 +#define ROM_BOOT_IMAGE_ID 2 + +enum _fw_version_check_option +{ + kRomLdr_FwCheckOption_SecureVersion = 0x0U, + kRomLdr_FwCheckOption_NonSecureVersion = 0x1U, +}; + +typedef uint8_t chunk_t[BYTES_PER_CHUNK]; + +/*! @brief Boot command definition */ +typedef struct _boot_cmd +{ + uint8_t checksum; /*!< 8-bit checksum over command chunk */ + uint8_t tag; /*!< command tag (identifier) */ + uint16_t flags; /*!< command flags (modifier) */ + uint32_t address; /*!< address argument */ + uint32_t count; /*!< count argument */ + uint32_t data; /*!< data argument */ +} boot_cmd_t; + +/*! @brief Definition for boot image file header chunk 1 */ +typedef struct _boot_hdr1 +{ + uint32_t hash; /*!< last 32-bits of SHA-1 hash */ + uint32_t signature; /*!< must equal "STMP" */ + uint8_t major; /*!< major file format version */ + uint8_t minor; /*!< minor file format version */ + uint16_t fileFlags; /*!< global file flags */ + uint32_t fileChunks; /*!< total chunks in the file */ +} boot_hdr1_t; + +/*! @brief Definition for boot image file header chunk 2 */ +typedef struct _boot_hdr2 +{ + uint32_t bootOffset; /*!< chunk offset to the first boot section */ + uint32_t bootSectID; /*!< section ID of the first boot section */ + uint16_t keyCount; /*!< number of keys in the key dictionary */ + uint16_t keyOffset; /*!< chunk offset to the key dictionary */ + uint16_t hdrChunks; /*!< number of chunks in the header */ + uint16_t sectCount; /*!< number of sections in the image */ +} boot_hdr2_t; + +/*! @brief Provides forward reference to the loader context definition. */ +typedef struct _ldr_Context ldr_Context_t; + +/*! @brief Function pointer definition for all loader action functions. */ +typedef status_t (*pLdrFnc_t)(ldr_Context_t *context); + +/*! @brief Jump command function pointer definition. */ +typedef status_t (*pJumpFnc_t)(uint32_t parameter); + +/*! @brief Call command function pointer definition. */ +typedef status_t (*pCallFnc_t)(uint32_t parameter, uint32_t *func); + +/*! @brief State information for the CRC32 algorithm. */ +typedef struct Crc32Data +{ + uint32_t currentCrc; /*!< Current CRC value. */ + uint32_t byteCountCrc; /*!< Number of bytes processed. */ +} crc32_data_t; + +/*! @brief Loader context definition. */ +struct _ldr_Context +{ + pLdrFnc_t Action; /*!< pointer to loader action function */ + uint32_t fileChunks; /*!< chunks remaining in file */ + uint32_t sectChunks; /*!< chunks remaining in section */ + uint32_t bootSectChunks; /*!< number of chunks we need to complete the boot section */ + uint32_t receivedChunks; /*!< number of chunks we need to complete the boot section */ + uint16_t fileFlags; /*!< file header flags */ + uint16_t keyCount; /*!< number of keys in the key dictionary */ + uint32_t objectID; /*!< ID of the current boot section or image */ + crc32_data_t crc32; /*!< crc calculated over load command payload */ + uint8_t *src; /*!< source buffer address */ + chunk_t initVector; /*!< decryption initialization vector */ + chunk_t dek; /*!< chunk size DEK if the image is encrypted */ + chunk_t scratchPad; /*!< chunk size scratch pad area */ + boot_cmd_t bootCmd; /*!< current boot command */ + uint32_t skipCount; /*!< Number of chunks to skip */ + bool skipToEnd; /*!< true if skipping to end of file */ + + /* extended for SB 2.0 */ + uint32_t nonce[4]; + uint32_t keyBlobBlock; + uint32_t keyBlobBlockCount; + uint8_t *keyBlobBuffer; + uint32_t offsetSignatureBytes; /*!< offset to signagure block header in bytesn */ + uint8_t *headerBuffer; +}; + +typedef struct soc_memory_map_struct +{ + struct + { + uint32_t start; + uint32_t end; + } ramRegions[RAM_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } flashRegions[FLASH_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } ffrRegions[FFR_REGION_COUNT]; +} soc_mem_regions_t; + +typedef struct arena_context +{ + uint32_t start; + uint32_t end; + uint32_t nextAddr; +} arena_context_t; + +/*! @brief Memory region information table */ +typedef struct mem_region +{ + uint32_t start; + uint32_t end; +} mem_region_t; + +/*! @brief Memory Attribute Structure */ +typedef struct memory_attribute_struct +{ + uint32_t memId; + uint32_t regionCount; + mem_region_t *memRegions; + void *context; +} mem_attribute_t; + +/*! @brief Memory context structure */ +typedef struct memory_context_struct +{ + status_t (*flush)(mem_attribute_t *attr); + mem_attribute_t *attr; +} mem_context_t; + +/*! @brief Memory region interface structure */ +typedef struct api_memory_region_interface +{ + status_t (*init)(mem_attribute_t *attr); + status_t (*read)(mem_attribute_t *attr, uint32_t addr, uint32_t leth, uint8_t *buf); + status_t (*write)(mem_attribute_t *attr, uint32_t addr, uint32_t len, const uint8_t *buf); + status_t (*fill)(mem_attribute_t *attr, uint32_t addr, uint32_t len, uint32_t pattern); + status_t (*flush)(mem_attribute_t *attr); + status_t (*erase)(mem_attribute_t *attr, uint32_t addr, uint32_t len); + status_t (*config)(mem_attribute_t *attr, uint32_t *buf); + status_t (*erase_all)(mem_attribute_t *attr); + status_t (*alloc_ctx)(arena_context_t *ctx, mem_attribute_t *attr, void *miscParams); +} api_memory_region_interface_t; + +/*! @brief Memory entry data structure */ +typedef struct memory_map_entry +{ + mem_attribute_t *memoryAttribute; + const api_memory_region_interface_t *memoryInterface; +} api_memory_map_entry_t; + +/*! @brief The API context structure */ +typedef struct api_core_context +{ + soc_mem_regions_t memRegions; + arena_context_t arenaCtx; + flash_config_t flashConfig; + uint32_t reserved; + mem_context_t memCtx; + ldr_Context_v4_t *sbloaderCtx; + nboot_context_t *nbootCtx; + uint8_t *sharedBuf; + api_memory_map_entry_t memEntries[MEM_INTERFACE_COUNT]; +} api_core_context_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Perform the Sbloader runtime environment initialization + * This API is used for initializing the sbloader state machine before calling + * the api_sbloader_pump. This API should be called after the iap_api_init API. + * + * @param ctx Pointer to IAP API core context structure. + * + * @retval #kStatus_Success Api was executed succesfuly. + */ +status_t Sbloader_Init(api_core_context_t *ctx); + +/*! + * @brief Handle the SB data stream + * This API is used for handling the secure binary(SB3.1 format) data stream, + * which is used for image update, lifecycle advancing, etc. + * This API should be called after the iap_api_init and api_sbloader_init APIs. + + * @param ctx Pointer to IAP API core context structure. + * @param data Pointer to source data that is the sb file buffer data. + * @param length The size of the process buffer data. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument An invalid argument is provided. + * @retval #kStatus_Fail API execution failed. + */ +status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length); + +/*! + * @brief Finish the sbloader handling + * The API is used for finalizing the sbloader operations. + * + * @param ctx Pointer to IAP API core context structure. + * + * @retval #kStatus_Success Api was executed succesfuly. + */ +status_t Sbloader_Finalize(api_core_context_t *ctx); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_SBLOADER_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/fsl_sbloader_v4.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/fsl_sbloader_v4.h new file mode 100644 index 000000000..6af6b3627 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/fsl_sbloader_v4.h @@ -0,0 +1,275 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SBLOADER_V4_H_ +#define FSL_SBLOADER_V4_H_ + +#include + +#include "fsl_nboot_hal.h" + +/*! @addtogroup sbloader */ +/*! @{ */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! + * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by + * the encryption algorithm. + */ +#define SB4_BYTES_PER_CHUNK 16 + +typedef uint8_t chunk_v3_t[SB4_BYTES_PER_CHUNK]; + +typedef struct _ldr_buf ldr_buf_t; + +struct _ldr_buf +{ + chunk_v3_t data; + uint32_t fillPosition; +}; + +/*! @brief Provides forward reference to the loader context definition. */ +typedef struct _ldr_Context_v4 ldr_Context_v4_t; + +/*! @brief Function pointer definition for all loader action functions. */ +typedef status_t (*pLdrFnc_v4_t)(ldr_Context_v4_t *); + +/*! @brief sb4 section definitions */ +/*! @brief section type */ +typedef enum _sectionType +{ + kSectionNone = 0, /* end or invalid */ + kSectionDataRange = 1, + kSectionDiffUpdate = 2, + kSectionDDRConfig = 3, + kSectionRegister = 4, +} section_type_t; + +#define SB3_DATA_RANGE_HEADER_FLAGS_ERASE_MASK (0x1u) /* bit 0 */ +#define SB3_DATA_RANGE_HEADER_FLAGS_LOAD_MASK (0x2u) /* bit 1 */ + +/*! @brief section data range structure */ +typedef struct range_header +{ + uint32_t tag; + uint32_t startAddress; + uint32_t length; + uint32_t cmd; +} sb4_data_range_header_t; + +typedef struct range_header_expansion +{ + uint32_t memoryId; + uint32_t pad0; + uint32_t pad1; + uint32_t pad2; +} sb4_data_range_expansion_t; + +typedef struct copy_memory_expansion +{ + uint32_t destAddr; + uint32_t memoryIdFrom; + uint32_t memoryIdTo; + uint32_t pad; +} sb4_copy_memory_expansion_t; + +typedef struct copy +{ + sb4_data_range_header_t header; + sb4_copy_memory_expansion_t expansion; +} sb4_copy_memory_t; + +typedef struct load_keyblob +{ + uint32_t tag; + uint16_t offset; + uint16_t keyWrapId; + uint32_t length; + uint32_t cmd; +} sb4_load_keyblob_t; + +typedef struct fill_memory_expansion +{ + uint32_t pattern; /* word to be used as pattern */ + uint32_t pad0; + uint32_t pad1; + uint32_t pad2; +} sb4_fill_memory_expansion_t; + +typedef struct fill_memory +{ + sb4_data_range_header_t header; + sb4_fill_memory_expansion_t arg; +} sb4_fill_memory_t; + +typedef struct config_memory +{ + uint32_t tag; + uint32_t memoryId; + uint32_t address; /* address of config blob */ + uint32_t cmd; +} sb4_config_memory_t; + +enum +{ + kFwVerChk_Id_none = 0, + kFwVerChk_Id_nonsecure = 1, + kFwVerChk_Id_secure = 2, +}; + +typedef struct fw_ver_check +{ + uint32_t tag; + uint32_t version; + uint32_t id; + uint32_t cmd; +} sb4_fw_ver_check_t; + +/*! @brief sb4 DATA section header format */ +typedef struct section_header +{ + uint32_t sectionUid; + uint32_t sectionType; + uint32_t length; + uint32_t _pad; +} sb4_section_header_t; + +/*! @brief loader command enum */ +typedef enum _loader_command_sb4 +{ + kSB4_CmdInvalid = 0, + kSB4_CmdErase = 1, + kSB4_CmdLoad = 2, + kSB4_CmdExecute = 3, + kSB4_CmdCall = 4, + kSB4_CmdProgramFuse = 5, + kSB4_CmdProgramIFR = 6, + kSB4_CmdLoadCmac = 7, + kSB4_CmdCopy = 8, + kSB4_CmdLoadHashLocking = 9, + kSB4_CmdLoadKeyBlob = 10, + kSB4_CmdConfigMem = 11, + kSB4_CmdFillMem = 12, + kSB4_CmdFwVerCheck = 13, +} sb4_cmd_t; + +/*! @brief The all of the allowed command */ +#define SBLOADER_V4_CMD_SET_ALL \ + ((1u << kSB4_CmdErase) | (1u << kSB4_CmdLoad) | (1u << kSB4_CmdExecute) | (1u << kSB4_CmdCall) | \ + (1u << kSB4_CmdProgramFuse) | (1u << kSB4_CmdProgramIFR) | (1u << kSB4_CmdCopy) | (1u << kSB4_CmdLoadKeyBlob) | \ + (1u << kSB4_CmdConfigMem) | (1u << kSB4_CmdFillMem) | (1u << kSB4_CmdFwVerCheck)) +/*! @brief The allowed command set in ISP mode */ +#define SBLOADER_V4_CMD_SET_IN_ISP_MODE \ + ((1u << kSB4_CmdErase) | (1u << kSB4_CmdLoad) | (1u << kSB4_CmdExecute) | (1u << kSB4_CmdProgramFuse) | \ + (1u << kSB4_CmdProgramIFR) | (1u << kSB4_CmdCopy) | (1u << kSB4_CmdLoadKeyBlob) | (1u << kSB4_CmdConfigMem) | \ + (1u << kSB4_CmdFillMem) | (1u << kSB4_CmdFwVerCheck)) +/*! @brief The allowed command set in recovery mode */ +#define SBLOADER_V4_CMD_SET_IN_REC_MODE \ + ((1u << kSB4_CmdErase) | (1u << kSB4_CmdLoad) | (1u << kSB4_CmdExecute) | (1u << kSB4_CmdProgramFuse) | \ + (1u << kSB4_CmdProgramIFR) | (1u << kSB4_CmdCopy) | (1u << kSB4_CmdLoadKeyBlob) | (1u << kSB4_CmdConfigMem) | \ + (1u << kSB4_CmdFillMem) | (1u << kSB4_CmdFwVerCheck)) + +#define SB3_DATA_BUFFER_SIZE_IN_BYTE (MAX(512, NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX)) + +/*! @brief Memory region definition. */ +typedef struct +{ + uint32_t address; + uint32_t length; +} kb_region_t; + +/*! + * @brief Details of the operation to be performed by the ROM. + * + * The #kRomAuthenticateImage operation requires the entire signed image to be + * available to the application. + */ +typedef enum +{ + kRomAuthenticateImage = 1, /*!< Authenticate a signed image. */ + kRomLoadImage = 2, /*!< Load SB file. */ + kRomOperationCount = 3, +} kb_operation_t; + +typedef struct +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t overrideSBBootSectionID; + uint32_t *userSBKEK; + uint32_t regionCount; + const kb_region_t *regions; +} kb_load_sb_t; + +typedef struct +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t maxImageLength; + uint32_t *userRHK; +} kb_authenticate_t; + +typedef struct +{ + uint32_t version; /*!< Should be set to #kKbootApiVersion. */ + uint8_t *buffer; /*!< Caller-provided buffer used by Kboot. */ + uint32_t bufferLength; + kb_operation_t op; + union + { + /*! Settings for #kKbootAuthenticate operation. */ + kb_authenticate_t authenticate; + /*! Settings for #kKbootLoadSB operation. */ + kb_load_sb_t loadSB; + }; +} kb_options_t; + +/*! @brief Loader context definition. */ +struct _ldr_Context_v4 +{ + pLdrFnc_v4_t Action; /*!< pointer to loader action function */ + uint32_t block_size; /*!< size of each block in bytes */ + uint32_t block_data_size; /*!< data size in bytes (NBOOT_SB4_CHUNK_SIZE_IN_BYTES) */ + uint32_t block_data_total; /*!< data max size in bytes (block_size * data_size */ + uint32_t block_buffer_size; /*!< block0 and block size */ + uint32_t block_buffer_position; + uint8_t block_buffer[MAX(NBOOT_SB4_MANIFEST_MAX_SIZE_IN_BYTES, + NBOOT_SB4_BLOCK_MAX_SIZE_IN_BYTES)]; /*! will be used for both block0 and blockx */ + uint32_t processedBlocks; + uint32_t totalBlocks; + uint32_t nextBlockSize; + + uint8_t data_block_offset; /*! data block offset in a block. */ + bool in_data_block; /*!< in progress of handling a data block within a block */ + uint8_t *data_block; + uint32_t data_block_position; + + bool in_data_section; /*!< in progress of handling a data section within a data block */ + uint32_t data_section_handled; + sb4_section_header_t data_section_header; + + bool in_data_range; /*!< in progress of handling a data range within a data section */ + uint32_t data_range_handled; + uint32_t data_range_gap; + sb4_data_range_header_t data_range_header; + bool has_data_range_expansion; + sb4_data_range_expansion_t data_range_expansion; + + uint32_t commandSet; /*!< support command set during sb file handling */ + + uint32_t data_position; + uint8_t data_buffer[SB3_DATA_BUFFER_SIZE_IN_BYTE]; /*!< temporary data buffer */ + + kb_options_t fromAPI; /* options from ROM API */ +}; + +/*! @} */ + +#endif /* FSL_SBLOADER_V4_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/src/fsl_mem_interface.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/src/fsl_mem_interface.c new file mode 100644 index 000000000..533c46ac0 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/mem_interface/src/fsl_mem_interface.c @@ -0,0 +1,153 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_mem_interface.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.memInterface" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303e000u) + +/*! @brief IAP API Interface structure */ +typedef struct iap_api_interface_struct +{ + standard_version_t version; /*!< IAP API version number. */ + status_t (*api_init)(api_core_context_t *coreCtx, const kp_api_init_param_t *param); + status_t (*api_deinit)(api_core_context_t *coreCtx); + status_t (*mem_init)(api_core_context_t *ctx); + status_t (*mem_read)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint8_t *buf, uint32_t memoryId); + status_t (*mem_write)(api_core_context_t *ctx, uint32_t addr, uint32_t len, const uint8_t *buf, uint32_t memoryId); + status_t (*mem_fill)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t pattern, uint32_t memoryId); + status_t (*mem_flush)(api_core_context_t *ctx); + status_t (*mem_erase)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t memoryId); + status_t (*mem_config)(api_core_context_t *ctx, uint32_t *buf, uint32_t memoryId); + status_t (*mem_erase_all)(api_core_context_t *ctx, uint32_t memoryId); + status_t (*sbloader_init)(api_core_context_t *ctx); + status_t (*sbloader_pump)(api_core_context_t *ctx, uint8_t *data, uint32_t length); + status_t (*sbloader_finalize)(api_core_context_t *ctx); +} iap_api_interface_t; + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + standard_version_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const uint32_t flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const uint32_t reserved2; /*!< reserved*/ + const uint32_t efuseDriver; /*!< eFuse driver API */ + const iap_api_interface_t *iapAPIDriver; /*!< IAP driver API */ +} bootloader_tree_t; +/******************************************************************************* + * API + ******************************************************************************/ + +standard_version_t API_Version(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->version; +} + +/*! @brief Initialize the IAP API runtime environment */ +status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->api_init(coreCtx, param); +} + +/*! @brief Deinitialize the IAP API runtime environment */ +status_t API_Deinit(api_core_context_t *coreCtx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->api_deinit(coreCtx); +} + +/*! @brief Intialize the memory interface of the IAP API */ +status_t MEM_Init(api_core_context_t *coreCtx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_init(coreCtx); +} + +/*! @brief Perform the memory write operation */ +status_t MEM_Write( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_write(coreCtx, start, lengthInBytes, buf, memoryId); +} + +/*! @brief Perform the Fill operation */ +status_t MEM_Fill( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_fill(coreCtx, start, lengthInBytes, pattern, memoryId); +} + +/*! @brief Perform the Memory erase operation */ +status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_erase(coreCtx, start, lengthInBytes, memoryId); +} +/*! @brief Perform the full Memory erase operation */ +status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_erase_all(coreCtx, memoryId); +} + +/*! @brief Perform the Memory configuration operation */ +status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_config(coreCtx, config, memoryId); +} + +/*! @brief Perform the Memory Flush operation */ +status_t MEM_Flush(api_core_context_t *coreCtx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_flush(coreCtx); +} + +/*! @brief Perform the Sbloader runtime environment initialization */ +status_t Sbloader_Init(api_core_context_t *ctx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->sbloader_init(ctx); +} + +/*! @brief Handle the SB data stream */ +status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->sbloader_pump(ctx, data, length); +} +/*! @brief Finish the sbloader handling */ +status_t Sbloader_Finalize(api_core_context_t *ctx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->sbloader_finalize(ctx); +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/nboot/fsl_nboot.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/nboot/fsl_nboot.h new file mode 100644 index 000000000..8ed5a4452 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/nboot/fsl_nboot.h @@ -0,0 +1,370 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_NBOOT_H_ +#define FSL_NBOOT_H_ + +#include "fsl_common.h" +#include "fsl_nboot_hal.h" + +/*! + * @addtogroup nboot + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ROMAPI_NBOOT driver version 2.0.0. */ +#define FSL_ROMAPI_NBOOT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define NBOOT_SB4_MANIFEST_MAX_SIZE_IN_BYTES (16UL * 1024UL) +#define NBOOT_SB4_BLOCK_MAX_SIZE_IN_BYTES (2UL * sizeof(uint32_t) + 48UL + 4UL * 1024UL) + +/* size in bytes from start of the manifest, enough bytes that contain encoding of whole manifest size */ +#define NBOOT_SB4_GET_INITIAL_FETCH_SIZE (0x90UL) + +/* SB4 types */ +#define NBOOT_SB4_FWTYPE_DEFAULT 0x123400a1u +#define NBOOT_SB4_FWTYPE_NXP_MFW 0x43215005u +#define NBOOT_SB4_FWTYPE_OEM_MFW 0x1423ccccu +typedef uint32_t nboot_sb4_fwtype_t; + +/*! + * @brief NBOOT type for the root key usage + * + * This type defines the NBOOT root key usage + * + */ +#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA_ImageKey_FwKey (0x0u) +#define kNBOOT_RootKeyUsage_DebugCA (0x1u) +#define kNBOOT_RootKeyUsage_ImageCA_FwCA (0x2u) +#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA (0x3u) +#define kNBOOT_RootKeyUsage_ImageKey_FwKey (0x4u) +#define kNBOOT_RootKeyUsage_ImageKey (0x5u) +#define kNBOOT_RootKeyUsage_FwKey (0x6u) +#define kNBOOT_RootKeyUsage_Unused (0x7u) + +/* any other value means the root key is not valid (treat as if revoked) */ +typedef uint32_t nboot_root_key_usage_t; + +#define NBOOT_ROOT_CERT_COUNT (4u) + +/*! + * @brief NBOOT type for the root key revocation + * + * This type defines the NBOOT root key revocation + * + */ +#define kNBOOT_RootKey_Enabled (0xAAu) +#define kNBOOT_RootKey_Revoked (0xBBu) +/* any other value means the root key is revoked */ +typedef uint32_t nboot_root_key_revocation_t; + +/*! + * @brief NBOOT type specifying the elliptic curve to be used + * + * This type defines the elliptic curve type and length + * + */ +#define kNBOOT_RootKey_Ecdsa_P256 (0x0000FE01u) +#define kNBOOT_RootKey_Ecdsa_P384 (0x0000FD02u) +#define kNBOOT_RootKey_MlDsa_87 (0x0000FD03u) +#define kNBOOT_RootKey_Ecdsa_P384_MlDsa_87 (0x0000FD04u) +typedef uint32_t nboot_root_key_type_and_length_t; + +/*! @brief Enumeration for SoC Lifecycle. */ +#define nboot_lc_nxpBlank (0xFFFF0000u) +#define nboot_lc_nxpFab (0xFFFE0001u) +#define nboot_lc_nxpDev (0xFF0300FCu) +#define nboot_lc_nxpProvisioned (0xFFFC0003u) +#define nboot_lc_oemOpen (0xFFFC0003u) +#define nboot_lc_oemSecureWorld (0xFFF80007u) +#define nboot_lc_oemClosed (0xFFF0000Fu) +#define nboot_lc_oemLocked (0xFF3000CFu) +#define nboot_lc_oemFieldReturn (0xFFE0001Fu) +#define nboot_lc_nxpFieldReturn (0xFF80007Fu) +#define nboot_lc_shredded (0xFF0000FFu) +typedef uint32_t nboot_soc_lifecycle_t; + +/*! @brief Type for nboot status codes */ +typedef uint32_t nboot_status_t; + +/*! @brief Type for nboot protected status codes */ +typedef uint64_t nboot_status_protected_t; + +/*! @brief Enumeration for MCUX_CSSL_FP_FUNCID */ +#define MCUX_CSSL_FP_FUNCID_NBOOT_ContextInit (0x5DA1u) +#define MCUX_CSSL_FP_FUNCID_NBOOT_ContextDeinit (0x30DBu) +#define MCUX_CSSL_FP_FUNCID_NBOOT_ContextSetUuid (0x5E38u) +#define MCUX_CSSL_FP_FUNCID_NBOOT_Sb4LoadManifest (0x42E7u) +#define MCUX_CSSL_FP_FUNCID_NBOOT_Sb4LoadBlock (0x275Au) +#define MCUX_CSSL_FP_FUNCID_NBOOT_SB4CheckAuthenticityAndCompleteness (0x22E7u) +#define MCUX_CSSL_FP_FUNCID_NBOOT_ImgAuthenticate (0x2EA5u) +#define NBOOT_CONTEXT_RTF_OFFSET (0x100u) + +/** + * \defgroup nbootStatusValues This type defines status return values used by NBOOT functions that are not easily + * disturbed by Fault Attacks + * @{ + */ +#define kStatus_NBOOT_Success ((nboot_status_t)0x5A5A5A5Au) /*!< Operation completed successfully. */ +#define kStatus_NBOOT_Fail ((nboot_status_t)0x5A5AA5A5u) /*!< Operation failed. */ +#define kStatus_NBOOT_InvalidArgument ((nboot_status_t)0x5A5AA5F0u) /*!< Invalid argument passed to the function. */ +#define kStatus_NBOOT_RequestTimeout ((nboot_status_t)0x5A5AA5E1u) /*!< Operation timed out. */ +#define kStatus_NBOOT_KeyNotLoaded ((nboot_status_t)0x5A5AA5E2u) /*!< The requested key is not loaded. */ +#define kStatus_NBOOT_AuthFail ((nboot_status_t)0x5A5AA5E4u) /*!< Authentication failed. */ +#define kStatus_NBOOT_OperationNotAvaialable ((nboot_status_t)0x5A5AA5E5u) /*!< Operation not available on this HW. */ +#define kStatus_NBOOT_KeyNotAvailable ((nboot_status_t)0x5A5AA5E6u) /*!< Key is not avaialble. */ +#define kStatus_NBOOT_IvCounterOverflow ((nboot_status_t)0x5A5AA5E7u) /*!< Overflow of IV counter (PRINCE/IPED). */ +#define kStatus_NBOOT_SelftestFail ((nboot_status_t)0x5A5AA5E8u) /*!< FIPS self-test failure. */ +#define kStatus_NBOOT_InvalidDataFormat ((nboot_status_t)0x5A5AA5E9u) /*!< Invalid data format for example antipole */ +#define kStatus_NBOOT_IskCertUserDataTooBig \ + ((nboot_status_t)0x5A5AA5EAu) /*!< Size of User data in ISK certificate is greater than 96 bytes */ +#define kStatus_NBOOT_IskCertSignatureOffsetTooSmall \ + ((nboot_status_t)0x5A5AA5EBu) /*!< Signature offset in ISK certificate is smaller than expected */ +#define kStatus_NBOOT_MemcpyFail ((nboot_status_t)0x5A5A845A) /*!< Unexpected error detected during nboot_memcpy() */ +#define kStatus_NBOOT_RegionIsLocked ((nboot_status_t)0x5A5AA5ECu) /*!< IPED/NPX region is locked */ +#define kStatus_NBOOT_SB3_Hashing \ + ((nboot_status_t)0x5A2112CCu) /*!< nboot_sb3_load_block () background hashing started */ +#define kStatus_NBOOT_SB3_Decrypting \ + ((nboot_status_t)0x5ACC1221u) /*!< nboot_sb3_load_block () background decrypting started */ +#define kStatus_NBOOT_SB4_Hashing \ + ((nboot_status_t)0x5A2112CEu) /*!< nboot_sb4_load_block () background hashing started */ +#define kStatus_NBOOT_SB4_Decrypting \ + ((nboot_status_t)0x5ACC122Eu) /*!< nboot_sb4_load_block () background decrypting started */ +/**@}*/ + +#define NBOOT_RKTH_SIZE_IN_WORDS (12u) + +/*! @brief Data structure holding secure counter value used by nboot library */ +typedef struct _nboot_secure_counter +{ + uint32_t sc; + uint32_t scAp; +} nboot_secure_counter_t; + +typedef struct nboot_trng_cfg_load +{ + uint32_t configData[13]; +} nboot_trng_cfg_load_t; + +typedef struct nboot_context_struct +{ + uint8_t opaque[0x00000858u]; +} nboot_context_t; +/*! + * @brief NBOOT type for the root of trust parameters + * + * This type defines the NBOOT root of trust parameters + * + */ +typedef struct nboot_rot_auth_parms_ +{ + /* trusted information originated from CFPA */ + nboot_root_key_revocation_t soc_rootKeyRevocation[NBOOT_ROOT_CERT_COUNT]; /*!< Provided by caller based on NVM + information in CFPA: ROTKH_REVOKE */ + uint32_t soc_imageKeyRevocation; /*!< Provided by caller based on NVM information in CFPA: IMAGE_KEY_REVOKE */ + + /* trusted information originated from CMPA */ + uint32_t soc_rkh[NBOOT_RKTH_SIZE_IN_WORDS]; /*!< Provided by caller based on NVM information in CMPA: ROTKH (hash of + hashes) */ + /*!< In case of kNBOOT_RootKey_Ecdsa_P384, sock_rkh[0..11] are used */ + /*!< In case of kNBOOT_RootKey_Ecdsa_P256, sock_rkh[0..7] are used */ + /*!< In case of kNBOOT_RootKey_MlDsa_87, sock_rkh[0..11] are used */ + + uint32_t soc_rkh_1[NBOOT_RKTH_SIZE_IN_WORDS]; /*!< Provided by caller based on NVM information in CMPA: ROTKH (hash + of hashes) */ + /*!< In case of kNBOOT_RootKey_MlDsa_87, sock_rkh[0..11] are used */ + + uint32_t soc_numberOfRootKeys; /* unsigned int, must be 4 */ + nboot_root_key_usage_t soc_rootKeyUsage[NBOOT_ROOT_CERT_COUNT]; /* CMPA */ + nboot_root_key_type_and_length_t + soc_rootKeyTypeAndLength; /* static selection between ECDSA P-256 or ECDSA P-384 based root keys */ + + /* trusted information originated from OTP fuses */ + nboot_soc_lifecycle_t soc_lifecycle; +} nboot_rot_auth_parms_t; + +/* +typedef struct nboot_prng_context +{ + uint32_t ctxA; + uint32_t ctxB; + uint32_t ctxC; + uint32_t ctxD; + uint32_t status; +} nboot_prng_context_t; +*/ + +/*! @brief Data structure holding input arguments to POR secure boot (authentication) algorithm. Shall be read from SoC + * trusted NVM or SoC fuses. */ +typedef struct nboot_img_auth_parms_struct +{ + /* trusted information originated from CFPA and NMPA */ + nboot_rot_auth_parms_t soc_RoTNVM; + + uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ +} nboot_img_auth_parms_t; + +/*! + * @brief manifest loading parameters + * + * This type defines the NBOOT SB4 manifest loading parameters + * + */ +typedef struct nboot_sb4_load_manifest_parms_struct +{ + nboot_rot_auth_parms_t soc_RoTNVM; /*! trusted information originated from CFPA and NMPA */ + uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ + uint32_t maxBlockSize; /*!< Provided by caller: supported maximal data block size (complete block)*/ + uint8_t pckBlob[48]; /* CUST_MK_SK rfc3394 blob. It is maximum size, that maps to RFC3394 for ELS S50 symmetric + 256-bit key. */ +} nboot_sb4_load_manifest_parms_t; + +/*! + * @brief Boolean type for the NBOOT functions + * + * This type defines boolean values used by NBOOT functions that are not easily disturbed by Fault Attacks + */ +typedef enum _nboot_bool +{ + kNBOOT_TRUE = 0x3C5AC33CU, /*!< Value for TRUE. */ + kNBOOT_TRUE256 = 0x3C5AC35AU, /*!< Value for TRUE when P256 was used to sign the image. */ + kNBOOT_TRUE384 = 0x3C5AC3A5U, /*!< Value for TRUE when P384 was used to sign the image. */ + kNBOOT_FALSE = 0x5AA55AA5U, /*!< Value for FALSE. */ + kNBOOT_OperationAllowed = 0x3c5a33ccU, + kNBOOT_OperationDisallowed = 0x5aa5cc33U, +} nboot_bool_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief The function is used for initializing of the nboot context data structure. + * It should be called prior to any other calls of nboot API. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_ContextInit(nboot_context_t *context); + +/*! + * @brief The function is used to deinitialize nboot context data structure. + * Its contents are overwritten with random data so that any sensitive data does not remain in memory. + * + * @param context Pointer to nboot_context_t structure. + + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_ContextDeinit(nboot_context_t *context); + +/*! + * @brief Set UUID in the nboot context + * + * This function sets the UUID (Universally Unique Identifier) in the nboot context structure. + * The NBOOT context has to be initialized by the function nboot_context_init before calling + * this function. + * + * @param context Pointer to nboot_context_t structure. + * @param uuid Pointer to 16-byte UUID array to be set in the context. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_ContextSetUuid(nboot_context_t *context, const uint8_t uuid[16]); + +/*! + * @brief Load NBOOT SB4 manifest + * + * This function loads and processes an NBOOT SB4 manifest. The manifest contains metadata + * and configuration information for the SB4 file processing. The NBOOT context has to be + * initialized by the function nboot_context_init before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param manifest Pointer to the SB4 manifest data. + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_Sb4LoadManifest(nboot_context_t *context, + const uint32_t *manifest, + nboot_sb4_load_manifest_parms_t *parms); + +/*! + * @brief Load NBOOT SB4 block + * + * This function loads and processes an NBOOT SB4 block. The NBOOT context has to be + * initialized by the function nboot_context_init before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param block Pointer to the SB4 block data to be loaded. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_Sb4LoadBlock(nboot_context_t *context, uint32_t *block); + +/*! + * @brief Check authenticity and completeness of NBOOT SB4 file + * + * This function verifies the authenticity and completeness of an NBOOT SB4 file. + * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param address Pointer to the SB4 file data in memory. + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_SB4CheckAuthenticityAndCompleteness(nboot_context_t *context, + const uint32_t *address, + nboot_sb4_load_manifest_parms_t *parms); + +/*! + * @brief Authenticate NBOOT image + * + * This function authenticates an NBOOT image by verifying its signature and integrity. + * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to the start address of the image data to be authenticated. + * @param isSignatureVerified Pointer to a boolean flag that will be set to indicate if the signature was verified. + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_ImgAuthenticate(nboot_context_t *context, + const uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_parms_t *parms); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* FSL_NBOOT_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/nboot/fsl_nboot_hal.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/nboot/fsl_nboot_hal.h new file mode 100644 index 000000000..07cd0264f --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/nboot/fsl_nboot_hal.h @@ -0,0 +1,82 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_NBOOT_HAL_H_ +#define FSL_NBOOT_HAL_H_ + +#include "fsl_nboot.h" + +/*! @addtogroup nbot_hal */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The size of the UUID. */ +#define NBOOT_UUID_SIZE_IN_WORD (4) +#define NBOOT_UUID_SIZE_IN_BYTE (NBOOT_UUID_SIZE_IN_WORD * 4) + +/*! @brief The size of the PUF activation code. */ +#define NBOOT_PUF_AC_SIZE_IN_BYTE (1000u) +/*! @brief The size of the PUF key code. */ +#define NBOOT_PUF_KC_SIZE_IN_BYTE (84) + +/*! @brief The size of the key store. */ +#define NBOOT_KEY_STORE_SIZE_IN_BYTE (NBOOT_PUF_AC_SIZE_IN_BYTE + 8) + +/*! @brief The size of the root of trust key table hash. */ +#define NBOOT_ROOT_ROTKH_SIZE_IN_WORD (12) +#define NBOOT_ROOT_ROTKH_SIZE_IN_BYTE (NBOOT_ROOT_ROTKH_SIZE_IN_WORD * 4) + +/*! @brief The size of the blob with Part Common Key. */ +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_256 (32) +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_384 (48) +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX (NBOOT_KEY_BLOB_SIZE_IN_BYTE_384) + +/*! @brief The mask of the value of the debug state . */ +#define NBOOT_DBG_AUTH_DBG_STATE_MASK (0x0000FFFFu) +/*! @brief The shift inverted value of the debug state. */ +#define NBOOT_DBG_AUTH_DBG_STATE_SHIFT (16) +/*! @brief The value with all debug feature disabled. */ +#define NBOOT_DBG_AUTH_DBG_STATE_ALL_DISABLED (0xFFFF0000u) + +#define NBOOT_DICE_CSR_SIZE_IN_WORD (36) +#define NBOOT_DICE_CSR_SIZE_IN_BYTES (NBOOT_DICE_CSR_SIZE_IN_WORD * 4) +#define NBOOT_DICE_CSR_ADDRESS (0x30000000u) +/*! @brief The offset for the PRCINE/IPED erase region return by nboot mem checker. */ +#define NBOOT_IPED_IV_OFFSET (4U) + +#define NBOOT_IMAGE_CMAC_UPDATE_NONE (0u) +#define NBOOT_IMAGE_CMAC_UPDATE_INDEX0 (1u) +#define NBOOT_IMAGE_CMAC_UPDATE_INDEX1 (2u) +#define NBOOT_IMAGE_CMAC_UPDATE_BOTH (3u) +#define NBOOT_IMAGE_CMAC_UPDATE_MASK (3u) + +#define NBOOT_CMPA_CMAC_UPDATE_MASK (0x38000000u) +#define NBOOT_CMPA_CMAC_UPDATE_SHIFT (0x27u) + +#define NBOOT_CMPA_UPDATE_CMAC_PFR (0x2u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_SECURE (0x3u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_CLOSE (0x5u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_LOCKED (0x6u) +#define EFUSE_PART_CFG_FUSE_INDEX (12U) + +/*! @brief Algorithm used for nboot HASH operation */ +typedef enum _nboot_hash_algo_t +{ + kHASH_Sha1 = 1, /*!< SHA_1 */ + kHASH_Sha256 = 2, /*!< SHA_256 */ + kHASH_Sha512 = 3, /*!< SHA_512 */ + kHASH_Aes = 4, /*!< AES */ + kHASH_AesIcb = 5, /*!< AES_ICB */ +} nboot_hash_algo_t; + +/*! @} */ + +#endif /*FSL_NBOOT_HAL_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/nboot/src/fsl_nboot.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/nboot/src/fsl_nboot.c new file mode 100644 index 000000000..4a77c5984 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/nboot/src/fsl_nboot.c @@ -0,0 +1,205 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_nboot_hal.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.nboot" +#endif + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303e000u) + +/** + * @brief Image authentication operations. + * + * These abstract interface are used for image verification operations. + */ + +typedef struct nboot_interface_struct +{ + nboot_status_protected_t (*nboot_context_init)(nboot_context_t *context); + nboot_status_protected_t (*nboot_context_deinit)(nboot_context_t *context); + nboot_status_protected_t (*nboot_context_set_uuid)(nboot_context_t *context, const uint8_t uuid[16]); + nboot_status_protected_t (*nboot_sb4_load_manifest)(nboot_context_t *context, + const uint32_t *manifest, + nboot_sb4_load_manifest_parms_t *parms); + nboot_status_protected_t (*nboot_sb4_load_block)(nboot_context_t *context, uint32_t *block); + nboot_status_protected_t (*nboot_sb4_check_authenticity_and_completeness_romapi)( + nboot_context_t *context, const uint32_t *address, nboot_sb4_load_manifest_parms_t *parms); + nboot_status_protected_t (*nboot_img_authenticate_romapi)(nboot_context_t *context, + const uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_parms_t *parms); +} nboot_interface_t; + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + const uint32_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const uint32_t flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const nboot_interface_t *nbootDriver; /*!< nBoot driver API */ + const uint32_t reserved2; /*!< reserved.*/ + const uint32_t efuseDriver; /*!< eFuse driver API */ + const uint32_t iapAPIDriver; /*!< IAP driver API */ +} bootloader_tree_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief The function is used for initializing of the nboot context data structure. + * It should be called prior to any other calls of nboot API. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_ContextInit(nboot_context_t *context) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_context_init(context); +} + +/*! + * @brief The function is used to deinitialize nboot context data structure. + * Its contents are overwritten with random data so that any sensitive data does not remain in memory. + * + * @param context Pointer to nboot_context_t structure. + + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_ContextDeinit(nboot_context_t *context) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_context_deinit(context); +} + +/*! + * @brief Set UUID in the nboot context + * + * This function sets the UUID (Universally Unique Identifier) in the nboot context structure. + * The NBOOT context has to be initialized by the function nboot_context_init before calling + * this function. + * + * @param context Pointer to nboot_context_t structure. + * @param uuid Pointer to 16-byte UUID array to be set in the context. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_ContextSetUuid(nboot_context_t *context, const uint8_t uuid[16]) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_context_set_uuid(context, uuid); +} + +/*! + * @brief Load NBOOT SB4 manifest + * + * This function loads and processes an NBOOT SB4 manifest. The manifest contains metadata + * and configuration information for the SB4 file processing. The NBOOT context has to be + * initialized by the function nboot_context_init before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param manifest Pointer to the SB4 manifest data. + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_Sb4LoadManifest(nboot_context_t *context, + const uint32_t *manifest, + nboot_sb4_load_manifest_parms_t *parms) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_sb4_load_manifest(context, manifest, parms); +} + +/*! + * @brief Load NBOOT SB4 block + * + * This function loads and processes an NBOOT SB4 block. The NBOOT context has to be + * initialized by the function nboot_context_init before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param block Pointer to the SB4 block data to be loaded. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_Sb4LoadBlock(nboot_context_t *context, uint32_t *block) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_sb4_load_block(context, block); +} + +/*! + * @brief Check authenticity and completeness of NBOOT SB4 file + * + * This function verifies the authenticity and completeness of an NBOOT SB4 file. + * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param address Pointer to the SB4 file data in memory. + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_SB4CheckAuthenticityAndCompleteness(nboot_context_t *context, + const uint32_t *address, + nboot_sb4_load_manifest_parms_t *parms) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_sb4_check_authenticity_and_completeness_romapi( + context, address, parms); +} + +/*! + * @brief Authenticate NBOOT image + * + * This function authenticates an NBOOT image by verifying its signature and integrity. + * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to the start address of the image data to be authenticated. + * @param isSignatureVerified Pointer to a boolean flag that will be set to indicate if the signature was verified. + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_ImgAuthenticate(nboot_context_t *context, + const uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_parms_t *parms) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_img_authenticate_romapi(context, imageStartAddress, + isSignatureVerified, parms); +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/runbootloader/fsl_runbootloader.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/runbootloader/fsl_runbootloader.h new file mode 100644 index 000000000..4177df325 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/runbootloader/fsl_runbootloader.h @@ -0,0 +1,77 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_RUN_BOOTLOADER_H_ +#define FSL_RUN_BOOTLOADER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup runbootloader + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ROMAPI_RUNBOOTLOADER driver version 2.0.0. */ +#define FSL_ROMAPI_RUNBOOTLOADER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* API prototype fields definition. +| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | +| Tag | Boot mode | ISP Interface | Instance | Image Index | Reserved | +| 0xEB | 0: Master boot mode | 0 - Auto detection | Used For Boot mode 0 | | | +| | 1: ISP mode | 1 - UART | | | | +| | | 2 - SPI | | | | +| | | 3 - I2C | | | | +| | | 4 - USB FS HID | | | | +| | | 5 - USB HS HID | | | | +| | | 6 - CAN | | | | +*/ +typedef struct +{ + union + { + struct + { + uint32_t reserved : 8; + uint32_t boot_image_index : 4; + uint32_t instance : 4; + uint32_t boot_interface : 4; + uint32_t mode : 4; + uint32_t tag : 8; + } B; + uint32_t U; + } option; +} user_app_boot_invoke_option_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Run the Bootloader API to force into the ISP mode base on the user arg + * + * @param arg Indicates API prototype fields definition. Refer to the above user_app_boot_invoke_option_t structure + */ +void bootloader_user_entry(void *arg); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* FSL_RUN_BOOTLOADER_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/runbootloader/src/fsl_runbootloader.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/runbootloader/src/fsl_runbootloader.c new file mode 100644 index 000000000..131c3e3e5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/drivers/romapi/runbootloader/src/fsl_runbootloader.c @@ -0,0 +1,49 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_runbootloader.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.runBootloader" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303e000u) + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + const uint32_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const uint32_t flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const uint32_t reserved2; /*!< reserved */ + const uint32_t efuseDriver; /*!< eFuse driver API */ + const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ +} bootloader_tree_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +void bootloader_user_entry(void *arg) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->runBootloader(arg); +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/fsl_device_registers.h new file mode 100644 index 000000000..c0229c000 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/fsl_device_registers.h @@ -0,0 +1,28 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1.h" +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core0.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core0.c new file mode 100644 index 000000000..c7ae39304 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core0.c @@ -0,0 +1,138 @@ +/* +** ################################################################### +** Processor: MCXN556SCDF_cm33_core0 +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN556S_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN556S_cm33_core0 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core0.h new file mode 100644 index 000000000..a1a1935d5 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core0.h @@ -0,0 +1,108 @@ +/* +** ################################################################### +** Processor: MCXN556SCDF_cm33_core0 +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN556S_cm33_core0 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN556S_cm33_core0 (header + * file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN556S_cm33_core0_H_ +#define _SYSTEM_MCXN556S_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN556S_cm33_core0_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core1.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core1.c new file mode 100644 index 000000000..9f0a0c6b8 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core1.c @@ -0,0 +1,132 @@ +/* +** ################################################################### +** Processor: MCXN556SCDF_cm33_core1 +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN556S_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN556S_cm33_core1 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#if __has_include("fsl_clock.h") +#include "fsl_clock.h" +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if !defined(__ZEPHYR__) +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + /* Route the PMC bandgap buffer signal to the ADC */ + SPC0->CORELDO_CFG |= (1U << 24U); + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +#if __has_include("fsl_clock.h") + /* Get frequency of Core System */ + SystemCoreClock = CLOCK_GetCoreSysClkFreq(); +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core1.h new file mode 100644 index 000000000..3ccfc5627 --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/system_MCXN556S_cm33_core1.h @@ -0,0 +1,108 @@ +/* +** ################################################################### +** Processor: MCXN556SCDF_cm33_core1 +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 3.0, 2024-10-29 +** Build: b250703 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-10-01) +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B +** - rev. 3.0 (2024-10-29) +** Change the device header file from single flat file to multiple files based on peripherals, +** each peripheral with dedicated header file located in periphN folder. +** +** ################################################################### +*/ + +/*! + * @file MCXN556S_cm33_core1 + * @version 3.0 + * @date 2024-10-29 + * @brief Device specific configuration file for MCXN556S_cm33_core1 (header + * file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN556S_cm33_core1_H_ +#define _SYSTEM_MCXN556S_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN556S_cm33_core1_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/variable.cmake b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/variable.cmake new file mode 100644 index 000000000..af17d084b --- /dev/null +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN556S/variable.cmake @@ -0,0 +1,19 @@ +# Copyright 2024 NXP +# All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +#### chip related +include(${SdkRootDirPath}/devices/MCX/variable.cmake) +mcux_set_variable(device MCXN556S) +mcux_set_variable(device_root devices) +mcux_set_variable(soc_series MCXN) +mcux_set_variable(soc_periph periph) + +if (NOT DEFINED core_id) + message(FATAL_ERROR "Please specify core_id for multicore device.") +endif() + +include(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN556S/${core_id}/variable.cmake) + +#### Source record diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/CMakeLists.txt index 14bd1cbed..2140a5abd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/CMakeLists.txt @@ -6,6 +6,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) #### MCX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0.h index 799f5f49b..4a51ec3aa 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN946VDF_cm33_core0 +** Processors: MCXN946VAB_cm33_core0 +** MCXN946VDF_cm33_core0 ** MCXN946VKL_cm33_core0 ** MCXN946VNL_cm33_core0 ** MCXN946VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN946_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0_COMMON.h index 023f36e66..d15010d29 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0_COMMON.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN946VDF_cm33_core0 +** Processors: MCXN946VAB_cm33_core0 +** MCXN946VDF_cm33_core0 ** MCXN946VKL_cm33_core0 ** MCXN946VNL_cm33_core0 ** MCXN946VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN946_cm33_core0 @@ -1043,25 +1044,25 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif @@ -1207,14 +1208,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1223,14 +1216,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1239,14 +1224,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1255,14 +1232,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1271,14 +1240,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1287,6 +1248,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1296,72 +1297,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* HPDAC - Peripheral instance base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0_features.h index a261e3544..d1dd09734 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -25,239 +25,124 @@ /* SOC module features */ -#if defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (2) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (2) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EVTG availability on the SoC. */ - #define FSL_FEATURE_SOC_EVTG_COUNT (1) - /* @brief EWM availability on the SoC. */ - #define FSL_FEATURE_SOC_EWM_COUNT (1) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (12) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief HPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_HPDAC_COUNT (1) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (2) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (2) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief ITRC availability on the SoC. */ - #define FSL_FEATURE_SOC_ITRC_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (2) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (10) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (10) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (2) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (10) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MCX_ENET availability on the SoC. */ - #define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) - /* @brief MPU availability on the SoC. */ - #define FSL_FEATURE_SOC_MPU_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief PKC availability on the SoC. */ - #define FSL_FEATURE_SOC_PKC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (6) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (4) - /* @brief QDC availability on the SoC. */ - #define FSL_FEATURE_SOC_QDC_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (1) - /* @brief SINC availability on the SoC. */ - #define FSL_FEATURE_SOC_SINC_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSPM availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSPM_COUNT (2) - /* @brief USB availability on the SoC. */ - #define FSL_FEATURE_SOC_USB_COUNT (1) - /* @brief USBC availability on the SoC. */ - #define FSL_FEATURE_SOC_USBC_COUNT (1) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) - /* @brief USBNC availability on the SoC. */ - #define FSL_FEATURE_SOC_USBNC_COUNT (1) - /* @brief USBPHY availability on the SoC. */ - #define FSL_FEATURE_SOC_USBPHY_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (2) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#elif defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (2) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (2) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EVTG availability on the SoC. */ - #define FSL_FEATURE_SOC_EVTG_COUNT (1) - /* @brief EWM availability on the SoC. */ - #define FSL_FEATURE_SOC_EWM_COUNT (1) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (12) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief HPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_HPDAC_COUNT (1) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (2) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (2) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief ITRC availability on the SoC. */ - #define FSL_FEATURE_SOC_ITRC_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (2) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (10) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (10) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (2) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (10) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MCX_ENET availability on the SoC. */ - #define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) - /* @brief MPU availability on the SoC. */ - #define FSL_FEATURE_SOC_MPU_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief PKC availability on the SoC. */ - #define FSL_FEATURE_SOC_PKC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (6) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (4) - /* @brief QDC availability on the SoC. */ - #define FSL_FEATURE_SOC_QDC_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (1) - /* @brief SINC availability on the SoC. */ - #define FSL_FEATURE_SOC_SINC_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSPM availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSPM_COUNT (2) - /* @brief USB availability on the SoC. */ - #define FSL_FEATURE_SOC_USB_COUNT (1) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (2) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#endif +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MCX_ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SINC availability on the SoC. */ +#define FSL_FEATURE_SOC_SINC_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) /* LPADC module features */ @@ -423,6 +308,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -430,6 +319,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -598,8 +489,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -628,27 +517,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) -/* @brief FlexSPI IPED REGION COUNT */ -#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* FMU module features */ @@ -692,6 +621,22 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* INPUTMUX module features */ @@ -776,8 +721,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -820,6 +763,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -950,7 +897,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -995,8 +942,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -1025,14 +970,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -1044,6 +993,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -1173,18 +1124,16 @@ /* USBPHY module features */ -#if defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0) - /* @brief USBPHY contain DCD analog module */ - #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) - /* @brief USBPHY has register TRIM_OVERRIDE_EN */ - #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) - /* @brief USBPHY is 28FDSOI */ - #define FSL_FEATURE_USBPHY_28FDSOI (0) -#endif /* defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0) */ +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -1208,10 +1157,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN946_cm33_core0_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1.h index 8793fc6ce..7a083587a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN946VDF_cm33_core1 +** Processors: MCXN946VAB_cm33_core1 +** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core1 ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN946_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1_COMMON.h index 5843e0e8c..3ef4200f0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1_COMMON.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN946VDF_cm33_core1 +** Processors: MCXN946VAB_cm33_core1 +** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core1 ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN946_cm33_core1 @@ -1043,25 +1044,25 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) -#else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif @@ -1207,14 +1208,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1223,14 +1216,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1239,14 +1224,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1255,14 +1232,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1271,14 +1240,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1287,6 +1248,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1296,72 +1297,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* HPDAC - Peripheral instance base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1_features.h index 28c97ab40..6d54ccab5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/MCXN946_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -25,239 +25,124 @@ /* SOC module features */ -#if defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (2) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (2) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EVTG availability on the SoC. */ - #define FSL_FEATURE_SOC_EVTG_COUNT (1) - /* @brief EWM availability on the SoC. */ - #define FSL_FEATURE_SOC_EWM_COUNT (1) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (12) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief HPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_HPDAC_COUNT (1) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (2) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (2) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief ITRC availability on the SoC. */ - #define FSL_FEATURE_SOC_ITRC_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (2) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (10) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (10) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (2) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (10) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MCX_ENET availability on the SoC. */ - #define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) - /* @brief MPU availability on the SoC. */ - #define FSL_FEATURE_SOC_MPU_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief PKC availability on the SoC. */ - #define FSL_FEATURE_SOC_PKC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (6) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (4) - /* @brief QDC availability on the SoC. */ - #define FSL_FEATURE_SOC_QDC_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (1) - /* @brief SINC availability on the SoC. */ - #define FSL_FEATURE_SOC_SINC_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSPM availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSPM_COUNT (2) - /* @brief USB availability on the SoC. */ - #define FSL_FEATURE_SOC_USB_COUNT (1) - /* @brief USBC availability on the SoC. */ - #define FSL_FEATURE_SOC_USBC_COUNT (1) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) - /* @brief USBNC availability on the SoC. */ - #define FSL_FEATURE_SOC_USBNC_COUNT (1) - /* @brief USBPHY availability on the SoC. */ - #define FSL_FEATURE_SOC_USBPHY_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (2) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#elif defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (2) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (2) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EVTG availability on the SoC. */ - #define FSL_FEATURE_SOC_EVTG_COUNT (1) - /* @brief EWM availability on the SoC. */ - #define FSL_FEATURE_SOC_EWM_COUNT (1) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (12) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief HPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_HPDAC_COUNT (1) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (2) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (2) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief ITRC availability on the SoC. */ - #define FSL_FEATURE_SOC_ITRC_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (2) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (10) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (10) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (2) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (10) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MCX_ENET availability on the SoC. */ - #define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) - /* @brief MPU availability on the SoC. */ - #define FSL_FEATURE_SOC_MPU_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief PKC availability on the SoC. */ - #define FSL_FEATURE_SOC_PKC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (6) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (4) - /* @brief QDC availability on the SoC. */ - #define FSL_FEATURE_SOC_QDC_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (1) - /* @brief SINC availability on the SoC. */ - #define FSL_FEATURE_SOC_SINC_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSPM availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSPM_COUNT (2) - /* @brief USB availability on the SoC. */ - #define FSL_FEATURE_SOC_USB_COUNT (1) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (2) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#endif +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MCX_ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SINC availability on the SoC. */ +#define FSL_FEATURE_SOC_SINC_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) /* LPADC module features */ @@ -423,6 +308,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -430,6 +319,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -598,8 +489,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -628,27 +517,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) -/* @brief FlexSPI IPED REGION COUNT */ -#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* FMU module features */ @@ -692,6 +621,22 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* INPUTMUX module features */ @@ -776,8 +721,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -820,6 +763,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -950,7 +897,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -995,8 +942,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -1025,14 +970,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -1044,6 +993,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -1166,18 +1117,16 @@ /* USBPHY module features */ -#if defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1) - /* @brief USBPHY contain DCD analog module */ - #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) - /* @brief USBPHY has register TRIM_OVERRIDE_EN */ - #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) - /* @brief USBPHY is 28FDSOI */ - #define FSL_FEATURE_USBPHY_28FDSOI (0) -#endif /* defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1) */ +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -1201,10 +1150,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN946_cm33_core1_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/fsl_device_registers.h index 6c874ccd1..65583d36a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/fsl_device_registers.h @@ -13,9 +13,9 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#if (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core0.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core0.c index d7df1f8a7..5408bfeda 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core0.c @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN946VDF_cm33_core0 +** Processors: MCXN946VAB_cm33_core0 +** MCXN946VDF_cm33_core0 ** MCXN946VKL_cm33_core0 ** MCXN946VNL_cm33_core0 ** MCXN946VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core0.h index af0e8ec60..74c89c079 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core0.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN946VDF_cm33_core0 +** Processors: MCXN946VAB_cm33_core0 +** MCXN946VDF_cm33_core0 ** MCXN946VKL_cm33_core0 ** MCXN946VNL_cm33_core0 ** MCXN946VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core1.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core1.c index ba9e8275d..1bd33a802 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core1.c @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN946VDF_cm33_core1 +** Processors: MCXN946VAB_cm33_core1 +** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core1 ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core1.h index dfa272747..8afa654c3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN946/system_MCXN946_cm33_core1.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN946VDF_cm33_core1 +** Processors: MCXN946VAB_cm33_core1 +** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core1 ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/CMakeLists.txt index 14bd1cbed..2140a5abd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/CMakeLists.txt @@ -6,6 +6,7 @@ #### device spepcific drivers include(${SdkRootDirPath}/devices/arm/device_header_multicore.cmake) mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers) +mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) #### MCX shared drivers/components/middlewares, project segments include(${SdkRootDirPath}/devices/MCX/shared.cmake) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0.h index 9055fac42..a5da8ab87 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN947VDF_cm33_core0 +** Processors: MCXN947VAB_cm33_core0 +** MCXN947VDF_cm33_core0 ** MCXN947VKL_cm33_core0 ** MCXN947VNL_cm33_core0 ** MCXN947VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN947_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0_COMMON.h index 974b50b96..9a87400e6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0_COMMON.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN947VDF_cm33_core0 +** Processors: MCXN947VAB_cm33_core0 +** MCXN947VDF_cm33_core0 ** MCXN947VKL_cm33_core0 ** MCXN947VNL_cm33_core0 ** MCXN947VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN947_cm33_core0 @@ -1086,25 +1087,25 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif @@ -1250,14 +1251,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1266,14 +1259,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1282,14 +1267,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1298,14 +1275,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1314,14 +1283,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1330,6 +1291,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1339,72 +1340,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* HPDAC - Peripheral instance base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0_features.h index f10bcbd51..f9115a6cd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -25,247 +25,132 @@ /* SOC module features */ -#if defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (2) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (2) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EMVSIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EMVSIM_COUNT (2) - /* @brief EVTG availability on the SoC. */ - #define FSL_FEATURE_SOC_EVTG_COUNT (1) - /* @brief EWM availability on the SoC. */ - #define FSL_FEATURE_SOC_EWM_COUNT (1) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (12) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief HPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_HPDAC_COUNT (1) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (2) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (2) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief ITRC availability on the SoC. */ - #define FSL_FEATURE_SOC_ITRC_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (2) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (10) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (10) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (2) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (10) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MCX_ENET availability on the SoC. */ - #define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) - /* @brief MPU availability on the SoC. */ - #define FSL_FEATURE_SOC_MPU_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PDM availability on the SoC. */ - #define FSL_FEATURE_SOC_PDM_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief PKC availability on the SoC. */ - #define FSL_FEATURE_SOC_PKC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (6) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (4) - /* @brief QDC availability on the SoC. */ - #define FSL_FEATURE_SOC_QDC_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (1) - /* @brief SINC availability on the SoC. */ - #define FSL_FEATURE_SOC_SINC_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSPM availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSPM_COUNT (2) - /* @brief TSI availability on the SoC. */ - #define FSL_FEATURE_SOC_TSI_COUNT (1) - /* @brief USB availability on the SoC. */ - #define FSL_FEATURE_SOC_USB_COUNT (1) - /* @brief USBC availability on the SoC. */ - #define FSL_FEATURE_SOC_USBC_COUNT (1) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) - /* @brief USBNC availability on the SoC. */ - #define FSL_FEATURE_SOC_USBNC_COUNT (1) - /* @brief USBPHY availability on the SoC. */ - #define FSL_FEATURE_SOC_USBPHY_COUNT (1) - /* @brief USDHC availability on the SoC. */ - #define FSL_FEATURE_SOC_USDHC_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (2) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#elif defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (2) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (2) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EVTG availability on the SoC. */ - #define FSL_FEATURE_SOC_EVTG_COUNT (1) - /* @brief EWM availability on the SoC. */ - #define FSL_FEATURE_SOC_EWM_COUNT (1) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (12) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief HPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_HPDAC_COUNT (1) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (2) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (2) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief ITRC availability on the SoC. */ - #define FSL_FEATURE_SOC_ITRC_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (2) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (10) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (10) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (2) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (10) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MCX_ENET availability on the SoC. */ - #define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) - /* @brief MPU availability on the SoC. */ - #define FSL_FEATURE_SOC_MPU_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief PKC availability on the SoC. */ - #define FSL_FEATURE_SOC_PKC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (6) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (4) - /* @brief QDC availability on the SoC. */ - #define FSL_FEATURE_SOC_QDC_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (1) - /* @brief SINC availability on the SoC. */ - #define FSL_FEATURE_SOC_SINC_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSPM availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSPM_COUNT (2) - /* @brief USB availability on the SoC. */ - #define FSL_FEATURE_SOC_USB_COUNT (1) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (2) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#endif +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (2) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MCX_ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SINC availability on the SoC. */ +#define FSL_FEATURE_SOC_SINC_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) /* LPADC module features */ @@ -431,6 +316,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -438,6 +327,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -606,8 +497,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -636,27 +525,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) -/* @brief FlexSPI IPED REGION COUNT */ -#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* FMU module features */ @@ -700,6 +629,22 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* INPUTMUX module features */ @@ -784,8 +729,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -828,6 +771,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -862,38 +809,36 @@ /* PDM module features */ -#if defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0) - /* @brief PDM FIFO offset */ - #define FSL_FEATURE_PDM_FIFO_OFFSET (4) - /* @brief PDM Channel Number */ - #define FSL_FEATURE_PDM_CHANNEL_NUM (4) - /* @brief PDM FIFO WIDTH Size */ - #define FSL_FEATURE_PDM_FIFO_WIDTH (4) - /* @brief PDM FIFO DEPTH Size */ - #define FSL_FEATURE_PDM_FIFO_DEPTH (16) - /* @brief PDM has RANGE_CTRL register */ - #define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) - /* @brief PDM Has Low Frequency */ - #define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) - /* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ - #define FSL_FEATURE_PDM_HAS_NO_VADEF (1) - /* @brief PDM Has no minimum clkdiv */ - #define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) - /* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ - #define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) - /* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ - #define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) - /* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ - #define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) - /* @brief PDM Has DC_OUT_CTRL */ - #define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) - /* @brief PDM Has Fixed DC CTRL VALUE. */ - #define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) - /* @brief PDM Has no independent error IRQ */ - #define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) - /* @brief PDM has no hardware Voice Activity Detector */ - #define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) -#endif /* defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0) */ +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) /* PINT module features */ @@ -993,7 +938,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -1038,8 +983,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -1068,14 +1011,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -1087,6 +1034,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -1180,12 +1129,10 @@ /* TSI module features */ -#if defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0) - /* @brief TSI Version */ - #define FSL_FEATURE_TSI_VERSION (6U) - /* @brief TSI Channel Count */ - #define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) -#endif /* defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0) */ +/* @brief TSI Version */ +#define FSL_FEATURE_TSI_VERSION (6U) +/* @brief TSI Channel Count */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) /* USBHSDCD module features */ @@ -1225,47 +1172,43 @@ /* USBPHY module features */ -#if defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0) - /* @brief USBPHY contain DCD analog module */ - #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) - /* @brief USBPHY has register TRIM_OVERRIDE_EN */ - #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) - /* @brief USBPHY is 28FDSOI */ - #define FSL_FEATURE_USBPHY_28FDSOI (0) -#endif /* defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0) */ +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) /* USDHC module features */ -#if defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0) - /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ - #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) - /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ - #define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) - /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ - #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) - /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ - #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) - /* @brief USDHC has reset control */ - #define FSL_FEATURE_USDHC_HAS_RESET (0) - /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ - #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) - /* @brief If USDHC instance support 8 bit width */ - #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) - /* @brief If USDHC instance support HS400 mode */ - #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) - /* @brief If USDHC instance support 1v8 signal */ - #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) - /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ - #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) - /* @brief Has no VSELECT bit in VEND_SPEC register */ - #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) - /* @brief Has no VS18 bit in HOST_CTRL_CAP register */ - #define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) -#endif /* defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0) */ +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -1289,10 +1232,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN947_cm33_core0_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1.h index 73affc45b..5fe1ab3a6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN947VDF_cm33_core1 +** Processors: MCXN947VAB_cm33_core1 +** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core1 ** MCXN947VNL_cm33_core1 ** MCXN947VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN947_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1_COMMON.h index 9db400b8d..7f0c5a37d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1_COMMON.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN947VDF_cm33_core1 +** Processors: MCXN947VAB_cm33_core1 +** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core1 ** MCXN947VNL_cm33_core1 ** MCXN947VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN947_cm33_core1 @@ -1086,25 +1087,25 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) -#else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } -/** FlexSPI0 AMBA base address */ -#define FlexSPI0_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x90000000u, 0xB0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x9FFFFFFFu, 0xBFFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) +#else + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x80000000u, 0xA0000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x8FFFFFFFu, 0xAFFFFFFFu} } + /** FlexSPI0 AMBA base address */ + #define FlexSPI0_AMBA_BASE (0x08000000u) #endif @@ -1250,14 +1251,6 @@ typedef enum IRQn { #define GPIO0 ((GPIO_Type *)GPIO0_BASE) /** Peripheral GPIO0 base pointer */ #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x50097000u) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE_NS (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x50098000u) /** Peripheral GPIO1 base address */ @@ -1266,14 +1259,6 @@ typedef enum IRQn { #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO1 base pointer */ #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x50099000u) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE_NS (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x5009A000u) /** Peripheral GPIO2 base address */ @@ -1282,14 +1267,6 @@ typedef enum IRQn { #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO2 base pointer */ #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x5009B000u) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x5009C000u) /** Peripheral GPIO3 base address */ @@ -1298,14 +1275,6 @@ typedef enum IRQn { #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO3 base pointer */ #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x5009D000u) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x5009E000u) /** Peripheral GPIO4 base address */ @@ -1314,14 +1283,6 @@ typedef enum IRQn { #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO4 base pointer */ #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x5009F000u) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x50040000u) /** Peripheral GPIO5 base address */ @@ -1330,6 +1291,46 @@ typedef enum IRQn { #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Peripheral GPIO5 base pointer */ #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x50041000u) /** Peripheral GPIO5_ALIAS1 base address */ @@ -1339,72 +1340,66 @@ typedef enum IRQn { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } - #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } - #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS, GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) - /** Peripheral GPIO0_ALIAS1 base address */ - #define GPIO0_ALIAS1_BASE (0x40097000u) - /** Peripheral GPIO0_ALIAS1 base pointer */ - #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x40098000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) - /** Peripheral GPIO1_ALIAS1 base address */ - #define GPIO1_ALIAS1_BASE (0x40099000u) - /** Peripheral GPIO1_ALIAS1 base pointer */ - #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x4009A000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) - /** Peripheral GPIO2_ALIAS1 base address */ - #define GPIO2_ALIAS1_BASE (0x4009B000u) - /** Peripheral GPIO2_ALIAS1 base pointer */ - #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x4009C000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) - /** Peripheral GPIO3_ALIAS1 base address */ - #define GPIO3_ALIAS1_BASE (0x4009D000u) - /** Peripheral GPIO3_ALIAS1 base pointer */ - #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x4009E000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) - /** Peripheral GPIO4_ALIAS1 base address */ - #define GPIO4_ALIAS1_BASE (0x4009F000u) - /** Peripheral GPIO4_ALIAS1 base pointer */ - #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x40040000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) /** Peripheral GPIO5_ALIAS1 base address */ #define GPIO5_ALIAS1_BASE (0x40041000u) /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } - #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } - #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* HPDAC - Peripheral instance base addresses */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1_features.h index 62283d13c..3d554b283 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/MCXN947_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -25,247 +25,132 @@ /* SOC module features */ -#if defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (2) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (2) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EMVSIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EMVSIM_COUNT (2) - /* @brief EVTG availability on the SoC. */ - #define FSL_FEATURE_SOC_EVTG_COUNT (1) - /* @brief EWM availability on the SoC. */ - #define FSL_FEATURE_SOC_EWM_COUNT (1) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (12) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief HPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_HPDAC_COUNT (1) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (2) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (2) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief ITRC availability on the SoC. */ - #define FSL_FEATURE_SOC_ITRC_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (2) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (10) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (10) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (2) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (10) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MCX_ENET availability on the SoC. */ - #define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) - /* @brief MPU availability on the SoC. */ - #define FSL_FEATURE_SOC_MPU_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PDM availability on the SoC. */ - #define FSL_FEATURE_SOC_PDM_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief PKC availability on the SoC. */ - #define FSL_FEATURE_SOC_PKC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (6) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (4) - /* @brief QDC availability on the SoC. */ - #define FSL_FEATURE_SOC_QDC_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (1) - /* @brief SINC availability on the SoC. */ - #define FSL_FEATURE_SOC_SINC_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSPM availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSPM_COUNT (2) - /* @brief TSI availability on the SoC. */ - #define FSL_FEATURE_SOC_TSI_COUNT (1) - /* @brief USB availability on the SoC. */ - #define FSL_FEATURE_SOC_USB_COUNT (1) - /* @brief USBC availability on the SoC. */ - #define FSL_FEATURE_SOC_USBC_COUNT (1) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) - /* @brief USBNC availability on the SoC. */ - #define FSL_FEATURE_SOC_USBNC_COUNT (1) - /* @brief USBPHY availability on the SoC. */ - #define FSL_FEATURE_SOC_USBPHY_COUNT (1) - /* @brief USDHC availability on the SoC. */ - #define FSL_FEATURE_SOC_USDHC_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (2) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#elif defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) - /* @brief CACHE64_CTRL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) - /* @brief CACHE64_POLSEL availability on the SoC. */ - #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) - /* @brief CDOG availability on the SoC. */ - #define FSL_FEATURE_SOC_CDOG_COUNT (2) - /* @brief CMC availability on the SoC. */ - #define FSL_FEATURE_SOC_CMC_COUNT (1) - /* @brief CRC availability on the SoC. */ - #define FSL_FEATURE_SOC_CRC_COUNT (1) - /* @brief CTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_CTIMER_COUNT (5) - /* @brief EDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_EDMA_COUNT (2) - /* @brief EIM availability on the SoC. */ - #define FSL_FEATURE_SOC_EIM_COUNT (1) - /* @brief EVTG availability on the SoC. */ - #define FSL_FEATURE_SOC_EVTG_COUNT (1) - /* @brief EWM availability on the SoC. */ - #define FSL_FEATURE_SOC_EWM_COUNT (1) - /* @brief FLEXCAN availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) - /* @brief FLEXIO availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) - /* @brief FLEXSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) - /* @brief FMC availability on the SoC. */ - #define FSL_FEATURE_SOC_FMC_COUNT (1) - /* @brief FREQME availability on the SoC. */ - #define FSL_FEATURE_SOC_FREQME_COUNT (1) - /* @brief GPIO availability on the SoC. */ - #define FSL_FEATURE_SOC_GPIO_COUNT (12) - /* @brief SPC availability on the SoC. */ - #define FSL_FEATURE_SOC_SPC_COUNT (1) - /* @brief HPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_HPDAC_COUNT (1) - /* @brief I3C availability on the SoC. */ - #define FSL_FEATURE_SOC_I3C_COUNT (2) - /* @brief I2S availability on the SoC. */ - #define FSL_FEATURE_SOC_I2S_COUNT (2) - /* @brief INPUTMUX availability on the SoC. */ - #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) - /* @brief ITRC availability on the SoC. */ - #define FSL_FEATURE_SOC_ITRC_COUNT (1) - /* @brief LPADC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPADC_COUNT (2) - /* @brief LPCMP availability on the SoC. */ - #define FSL_FEATURE_SOC_LPCMP_COUNT (3) - /* @brief LPDAC availability on the SoC. */ - #define FSL_FEATURE_SOC_LPDAC_COUNT (2) - /* @brief LPI2C availability on the SoC. */ - #define FSL_FEATURE_SOC_LPI2C_COUNT (10) - /* @brief LPSPI availability on the SoC. */ - #define FSL_FEATURE_SOC_LPSPI_COUNT (10) - /* @brief LPTMR availability on the SoC. */ - #define FSL_FEATURE_SOC_LPTMR_COUNT (2) - /* @brief LPUART availability on the SoC. */ - #define FSL_FEATURE_SOC_LPUART_COUNT (10) - /* @brief MAILBOX availability on the SoC. */ - #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) - /* @brief MCX_ENET availability on the SoC. */ - #define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) - /* @brief MPU availability on the SoC. */ - #define FSL_FEATURE_SOC_MPU_COUNT (1) - /* @brief MRT availability on the SoC. */ - #define FSL_FEATURE_SOC_MRT_COUNT (1) - /* @brief OPAMP availability on the SoC. */ - #define FSL_FEATURE_SOC_OPAMP_COUNT (3) - /* @brief OSTIMER availability on the SoC. */ - #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) - /* @brief PINT availability on the SoC. */ - #define FSL_FEATURE_SOC_PINT_COUNT (1) - /* @brief PKC availability on the SoC. */ - #define FSL_FEATURE_SOC_PKC_COUNT (1) - /* @brief POWERQUAD availability on the SoC. */ - #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) - /* @brief PORT availability on the SoC. */ - #define FSL_FEATURE_SOC_PORT_COUNT (6) - /* @brief PWM availability on the SoC. */ - #define FSL_FEATURE_SOC_PWM_COUNT (2) - /* @brief PUF availability on the SoC. */ - #define FSL_FEATURE_SOC_PUF_COUNT (4) - /* @brief QDC availability on the SoC. */ - #define FSL_FEATURE_SOC_QDC_COUNT (2) - /* @brief RTC availability on the SoC. */ - #define FSL_FEATURE_SOC_RTC_COUNT (1) - /* @brief SCG availability on the SoC. */ - #define FSL_FEATURE_SOC_SCG_COUNT (1) - /* @brief SCT availability on the SoC. */ - #define FSL_FEATURE_SOC_SCT_COUNT (1) - /* @brief SEMA42 availability on the SoC. */ - #define FSL_FEATURE_SOC_SEMA42_COUNT (1) - /* @brief SINC availability on the SoC. */ - #define FSL_FEATURE_SOC_SINC_COUNT (1) - /* @brief SMARTDMA availability on the SoC. */ - #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) - /* @brief SYSCON availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSCON_COUNT (1) - /* @brief SYSPM availability on the SoC. */ - #define FSL_FEATURE_SOC_SYSPM_COUNT (2) - /* @brief USB availability on the SoC. */ - #define FSL_FEATURE_SOC_USB_COUNT (1) - /* @brief USBHSDCD availability on the SoC. */ - #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) - /* @brief UTICK availability on the SoC. */ - #define FSL_FEATURE_SOC_UTICK_COUNT (1) - /* @brief VREF availability on the SoC. */ - #define FSL_FEATURE_SOC_VREF_COUNT (1) - /* @brief WWDT availability on the SoC. */ - #define FSL_FEATURE_SOC_WWDT_COUNT (2) - /* @brief WUU availability on the SoC. */ - #define FSL_FEATURE_SOC_WUU_COUNT (1) -#endif +/* @brief CACHE64_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) +/* @brief CACHE64_POLSEL availability on the SoC. */ +#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (2) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (3) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (10) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (10) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (10) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MCX_ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_MCX_ENET_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (3) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SINC availability on the SoC. */ +#define FSL_FEATURE_SOC_SINC_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBC_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) /* LPADC module features */ @@ -431,6 +316,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CDOG module features */ @@ -438,6 +327,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* CMC module features */ @@ -606,8 +497,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -636,27 +525,67 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) -/* @brief FlexSPI IPED REGION COUNT */ -#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (7) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* FMU module features */ @@ -700,6 +629,22 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* INPUTMUX module features */ @@ -784,8 +729,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -828,6 +771,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LP_FLEXCOMM module features */ @@ -862,38 +809,36 @@ /* PDM module features */ -#if defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1) - /* @brief PDM FIFO offset */ - #define FSL_FEATURE_PDM_FIFO_OFFSET (4) - /* @brief PDM Channel Number */ - #define FSL_FEATURE_PDM_CHANNEL_NUM (4) - /* @brief PDM FIFO WIDTH Size */ - #define FSL_FEATURE_PDM_FIFO_WIDTH (4) - /* @brief PDM FIFO DEPTH Size */ - #define FSL_FEATURE_PDM_FIFO_DEPTH (16) - /* @brief PDM has RANGE_CTRL register */ - #define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) - /* @brief PDM Has Low Frequency */ - #define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) - /* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ - #define FSL_FEATURE_PDM_HAS_NO_VADEF (1) - /* @brief PDM Has no minimum clkdiv */ - #define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) - /* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ - #define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) - /* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ - #define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) - /* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ - #define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) - /* @brief PDM Has DC_OUT_CTRL */ - #define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) - /* @brief PDM Has Fixed DC CTRL VALUE. */ - #define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) - /* @brief PDM Has no independent error IRQ */ - #define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) - /* @brief PDM has no hardware Voice Activity Detector */ - #define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) -#endif /* defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1) */ +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) /* PINT module features */ @@ -993,7 +938,7 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) -/* @brief Has ERRATA_51989. */ +/* @brief Is affected by errata with ID 51989. */ #define FSL_FEATURE_PWM_HAS_ERRATA_51989 (1) /* QDC module features */ @@ -1038,8 +983,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -1068,14 +1011,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -1087,6 +1034,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -1173,12 +1122,10 @@ /* TSI module features */ -#if defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1) - /* @brief TSI Version */ - #define FSL_FEATURE_TSI_VERSION (6U) - /* @brief TSI Channel Count */ - #define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) -#endif /* defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1) */ +/* @brief TSI Version */ +#define FSL_FEATURE_TSI_VERSION (6U) +/* @brief TSI Channel Count */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (25U) /* USBHSDCD module features */ @@ -1218,47 +1165,43 @@ /* USBPHY module features */ -#if defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1) - /* @brief USBPHY contain DCD analog module */ - #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) - /* @brief USBPHY has register TRIM_OVERRIDE_EN */ - #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) - /* @brief USBPHY is 28FDSOI */ - #define FSL_FEATURE_USBPHY_28FDSOI (0) -#endif /* defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1) */ +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) /* USDHC module features */ -#if defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1) - /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ - #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) - /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ - #define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) - /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ - #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) - /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ - #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) - /* @brief USDHC has reset control */ - #define FSL_FEATURE_USDHC_HAS_RESET (0) - /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ - #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) - /* @brief If USDHC instance support 8 bit width */ - #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) - /* @brief If USDHC instance support HS400 mode */ - #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) - /* @brief If USDHC instance support 1v8 signal */ - #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) - /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ - #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) - /* @brief Has no VSELECT bit in VEND_SPEC register */ - #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) - /* @brief Has no VS18 bit in HOST_CTRL_CAP register */ - #define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) -#endif /* defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1) */ +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) /* UTICK module features */ -/* @brief UTICK does not support PD configure. */ +/* @brief UTICK does not support power down configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) /* VBAT module features */ @@ -1282,10 +1225,16 @@ /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) -/* @brief WWDT does not support power down configure */ +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) +/* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXN947_cm33_core1_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/CMakeLists.txt index 795ddee6b..8784a0a75 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/CMakeLists.txt @@ -3,8 +3,6 @@ # # SPDX-License-Identifier: BSD-3-Clause -mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/MCX/MCXN/MCXN947/drivers/romapi) - if (CONFIG_MCUX_COMPONENT_driver.clock) mcux_component_version(2.0.0) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_clock.c index f26e4d85f..71d2db01f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_clock.c @@ -682,7 +682,11 @@ status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t m } case (uint32_t)kOD_Mode: { +#if defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) + if (system_freq_hz > 170000000U) +#else if (system_freq_hz > 150000000U) +#endif { return kStatus_Fail; } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_clock.h index 021ab7808..907dfd5fd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2022-2024 NXP + * Copyright 2022-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,8 +20,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.0.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief CLOCK driver version 2.0.1. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @brief Configure whether driver controls clock @@ -51,8 +51,12 @@ /* Definition for delay API in clock driver, users can redefine it to the real application. */ #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#if defined(MCXN556S_cm33_core0_SERIES) || defined(MCXN556S_cm33_core1_SERIES) +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (170000000UL) +#else #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) #endif +#endif /*! @brief Clock ip name array for ROM. */ #define ROM_CLOCKS \ @@ -80,9 +84,9 @@ kCLOCK_Enet \ } /*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4 \ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_None \ } /*! @brief Clock ip name array for GDET. */ #define GDET_CLOCKS \ @@ -1490,6 +1494,11 @@ static inline void CLOCK_EnableClock(clock_ip_name_t clk) uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + if (clk == kCLOCK_None) + { + return; + } + if (index == (uint32_t)REG_PWM0SUBCTL) { SYSCON->PWM0SUBCTL |= (1UL << bit); @@ -1516,6 +1525,11 @@ static inline void CLOCK_DisableClock(clock_ip_name_t clk) uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + if (clk == kCLOCK_None) + { + return; + } + if (index == (uint32_t)REG_PWM0SUBCTL) { SYSCON->PWM0SUBCTL &= ~(1UL << bit); diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_reset.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_reset.c index 58c059950..25c6a2b1a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_reset.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_reset.c @@ -1,5 +1,5 @@ /* - * Copyright 2022, NXP + * Copyright 2022-2025, NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -47,6 +47,11 @@ void RESET_SetPeripheralReset(reset_ip_name_t peripheral) assert(bitPos < 32u); + if (peripheral == kRST_None) + { + return; + } + /* reset register is in SYSCON */ /* set bit */ SYSCON->PRESETCTRLSET[regIndex] = bitMask; @@ -74,6 +79,11 @@ void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) assert(bitPos < 32u); + if (peripheral == kRST_None) + { + return; + } + /* reset register is in SYSCON */ /* clear bit */ @@ -95,6 +105,11 @@ void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) */ void RESET_PeripheralReset(reset_ip_name_t peripheral) { + if (peripheral == kRST_None) + { + return; + } + RESET_SetPeripheralReset(peripheral); RESET_ClearPeripheralReset(peripheral); } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_reset.h index cea66bb44..19687bcf0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_reset.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/fsl_reset.h @@ -1,5 +1,5 @@ /* - * Copyright 2022, 2024 NXP + * Copyright 2022-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,8 +24,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief reset driver version 2.4.0 */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*! @brief reset driver version 2.4.1 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) /*@}*/ /*! @@ -35,6 +35,8 @@ */ typedef enum _SYSCON_RSTn { + kRST_None, /*!< None RESET gate. */ + kFMU_RST_SHIFT_RSTn = 0 | 9U, /**< Flash management unit reset control */ kFLEXSPI_RST_SHIFT_RSTn = 0 | 11U, /**< FLEXSPI reset control */ kMUX_RST_SHIFT_RSTn = 0 | 12U, /**< Input mux reset control */ @@ -153,7 +155,7 @@ typedef enum _SYSCON_RSTn #define GPIO_RSTS_N \ { \ kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ - kGPIO4_RST_SHIFT_RSTn \ + kGPIO4_RST_SHIFT_RSTn, kRST_None \ } /* Reset bits for GPIO peripheral */ #define INPUTMUX_RSTS \ { \ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/romapi/CMakeLists.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/romapi/CMakeLists.txt index e2a5cc046..afb150454 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/romapi/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/romapi/CMakeLists.txt @@ -1,30 +1,16 @@ if (CONFIG_MCUX_COMPONENT_driver.romapi) mcux_component_version(2.0.0) + mcux_add_source( SOURCES - ./flash/fsl_efuse.h ./flash/fsl_flash.h - ./flash/fsl_flash_ffr.h - ./flash/fsl_flexspi_nor_flash.h - ./flash/src/fsl_flash.c - ./mem_interface/fsl_mem_interface.h - ./mem_interface/fsl_sbloader.h - ./mem_interface/fsl_sbloader_v3.h - ./mem_interface/src/fsl_mem_interface.c - ./nboot/fsl_nboot.h - ./nboot/fsl_nboot_hal.h - ./nboot/src/fsl_nboot.c - ./runbootloader/fsl_runbootloader.h - ./runbootloader/src/fsl_runbootloader.c ) mcux_add_include( - INCLUDES ./mem_interface - ./flash - ./nboot - ./runbootloader + INCLUDES ./flash ) + endif() if (CONFIG_MCUX_COMPONENT_driver.mem_interface) @@ -35,17 +21,10 @@ if (CONFIG_MCUX_COMPONENT_driver.mem_interface) ./mem_interface/fsl_mem_interface.h ./mem_interface/fsl_sbloader.h ./mem_interface/fsl_sbloader_v3.h - ./flash/fsl_flash.h - ./flash/fsl_flash_ffr.h - ./flash/fsl_flexspi_nor_flash.h - ./nboot/fsl_nboot.h - ./nboot/fsl_nboot_hal.h ) mcux_add_include( INCLUDES ./mem_interface - ./flash - ./nboot ) endif() @@ -64,24 +43,12 @@ if (CONFIG_MCUX_COMPONENT_driver.runbootloader) mcux_component_version(2.0.0) mcux_add_source( SOURCES - ./mem_interface/fsl_mem_interface.h - ./mem_interface/fsl_sbloader.h - ./mem_interface/fsl_sbloader_v3.h - ./flash/fsl_flash.h - ./flash/fsl_flash_ffr.h - ./flash/fsl_flexspi_nor_flash.h - ./nboot/src/fsl_nboot.c - ./nboot/fsl_nboot.h - ./nboot/fsl_nboot_hal.h ./runbootloader/fsl_runbootloader.h ./runbootloader/src/fsl_runbootloader.c ) mcux_add_include( - INCLUDES ./mem_interface - ./flash - ./nboot - ./runbootloader + INCLUDES ./runbootloader ) endif() diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/romapi/runbootloader/src/fsl_runbootloader.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/romapi/runbootloader/src/fsl_runbootloader.c index ebfe866f1..1bfec3325 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/romapi/runbootloader/src/fsl_runbootloader.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/drivers/romapi/runbootloader/src/fsl_runbootloader.c @@ -4,9 +4,6 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#include "fsl_flash.h" -#include "fsl_flash_ffr.h" -#include "fsl_flexspi_nor_flash.h" #include "fsl_runbootloader.h" /*! @brief Component ID definition, used by tools. */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/fsl_device_registers.h index d1003fded..f24b202f3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/fsl_device_registers.h @@ -13,9 +13,9 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#if (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core0.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core0.c index ac36ee26b..e1dafae0f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core0.c @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN947VDF_cm33_core0 +** Processors: MCXN947VAB_cm33_core0 +** MCXN947VDF_cm33_core0 ** MCXN947VKL_cm33_core0 ** MCXN947VNL_cm33_core0 ** MCXN947VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core0.h index 19e4b516c..f7e336412 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core0.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN947VDF_cm33_core0 +** Processors: MCXN947VAB_cm33_core0 +** MCXN947VDF_cm33_core0 ** MCXN947VKL_cm33_core0 ** MCXN947VNL_cm33_core0 ** MCXN947VPB_cm33_core0 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core1.c b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core1.c index 8dc03faef..d2ac3a80a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core1.c @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN947VDF_cm33_core1 +** Processors: MCXN947VAB_cm33_core1 +** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core1 ** MCXN947VNL_cm33_core1 ** MCXN947VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core1.h index a8a4a14fa..3060b07ba 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/MCXN947/system_MCXN947_cm33_core1.h @@ -1,6 +1,7 @@ /* ** ################################################################### -** Processors: MCXN947VDF_cm33_core1 +** Processors: MCXN947VAB_cm33_core1 +** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core1 ** MCXN947VNL_cm33_core1 ** MCXN947VPB_cm33_core1 @@ -12,7 +13,7 @@ ** ** Reference manual: MCXNx4x Reference Manual ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ADC.h index a84f7d7dc..153e5a91b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ADC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC @@ -70,21 +110,43 @@ #if !defined(PERI_ADC_H_) #define PERI_ADC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_AHBSC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_AHBSC.h index 28fadc23c..2d1e03c38 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_AHBSC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_AHBSC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for AHBSC @@ -70,21 +110,43 @@ #if !defined(PERI_AHBSC_H_) #define PERI_AHBSC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_BSP32.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_BSP32.h index 5cb351dc6..d3c140d63 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_BSP32.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_BSP32.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for BSP32 @@ -70,21 +110,43 @@ #if !defined(PERI_BSP32_H_) #define PERI_BSP32_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CACHE64_CTRL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CACHE64_CTRL.h index f0e980dc1..c22ab6d78 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CACHE64_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CACHE64_CTRL.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for CACHE64_CTRL @@ -70,21 +110,43 @@ #if !defined(PERI_CACHE64_CTRL_H_) #define PERI_CACHE64_CTRL_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CACHE64_POLSEL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CACHE64_POLSEL.h index 9b8efe8b3..4a937fae5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CACHE64_POLSEL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CACHE64_POLSEL.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for CACHE64_POLSEL @@ -70,21 +110,43 @@ #if !defined(PERI_CACHE64_POLSEL_H_) #define PERI_CACHE64_POLSEL_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CAN.h index 2a5e9749a..e757484d0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CAN.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN @@ -70,21 +110,43 @@ #if !defined(PERI_CAN_H_) #define PERI_CAN_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CDOG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CDOG.h index 8ae0a1966..fe037444b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CDOG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CDOG.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for CDOG @@ -70,21 +110,43 @@ #if !defined(PERI_CDOG_H_) #define PERI_CDOG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CMC.h index c50933462..b39bfa8be 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CMC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMC @@ -70,21 +110,43 @@ #if !defined(PERI_CMC_H_) #define PERI_CMC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CRC.h index c33af5911..2336cf316 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CRC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC @@ -70,21 +110,43 @@ #if !defined(PERI_CRC_H_) #define PERI_CRC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CTIMER.h index 9b0e7b424..8a5c43674 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CTIMER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_CTIMER.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for CTIMER @@ -70,21 +110,43 @@ #if !defined(PERI_CTIMER_H_) #define PERI_CTIMER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DIGTMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DIGTMP.h index 3d728d428..71b8dbe41 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DIGTMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DIGTMP.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for DIGTMP @@ -70,21 +110,43 @@ #if !defined(PERI_DIGTMP_H_) #define PERI_DIGTMP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DM.h index d1cbb14e4..8830119a1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for DM @@ -70,21 +110,43 @@ #if !defined(PERI_DM_H_) #define PERI_DM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DMA.h index 81a212a46..4f586158c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_DMA.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -70,21 +110,43 @@ #if !defined(PERI_DMA_H_) #define PERI_DMA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" @@ -170,6 +232,10 @@ typedef enum _dma_request_source kDma1RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ kDma0RequestMuxDac0FifoRequest = 25U, /**< DAC0 FIFO_request */ kDma1RequestMuxDac0FifoRequest = 25U, /**< DAC0 FIFO_request */ + kDma0RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ + kDma1RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ + kDma0RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ + kDma1RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ kDma0RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ kDma1RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ kDma0RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ @@ -206,12 +272,30 @@ typedef enum _dma_request_source kDma1RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ kDma0RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ kDma1RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma0RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma1RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma0RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma1RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma0RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma1RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma0RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma1RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma0RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma1RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma0RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma1RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma0RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma1RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma0RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ kDma0RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ kDma1RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ kDma0RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ kDma1RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ kDma0RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ kDma1RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma0RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ + kDma1RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ kDma0RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ kDma1RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ kDma0RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ @@ -292,6 +376,16 @@ typedef enum _dma_request_source kDma1RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ kDma0RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ kDma1RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma0RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ + kDma1RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ + kDma0RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ + kDma1RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ + kDma0RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ + kDma1RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ + kDma0RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ + kDma1RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ + kDma0RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ + kDma1RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ kDma0RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ kDma1RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ kDma0RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ @@ -316,44 +410,12 @@ typedef enum _dma_request_source kDma1RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ kDma0RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ kDma1RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ + kDma0RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ + kDma1RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ kDma0RequestMuxTsi0EndOfScan = 120U, /**< TSI0 End of Scan */ kDma1RequestMuxTsi0EndOfScan = 120U, /**< TSI0 End of Scan */ kDma0RequestMuxTsi0OutOfRange = 121U, /**< TSI0 Out of Range */ kDma1RequestMuxTsi0OutOfRange = 121U, /**< TSI0 Out of Range */ - kDma0RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ - kDma1RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ - kDma0RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ - kDma1RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ - kDma0RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ - kDma1RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ - kDma0RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ - kDma1RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ - kDma0RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ - kDma1RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ - kDma0RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ - kDma1RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ - kDma0RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ - kDma1RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ - kDma0RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ - kDma1RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ - kDma0RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ - kDma1RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ - kDma0RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ - kDma1RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ - kDma0RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ - kDma1RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ - kDma0RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ - kDma1RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ - kDma0RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ - kDma1RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ - kDma0RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ - kDma1RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ - kDma0RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ - kDma1RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ - kDma0RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ - kDma1RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ - kDma0RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ - kDma1RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ } dma_request_source_t; /* @} */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EIM.h index c83906152..dfa5d6adb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EIM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EIM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for EIM @@ -70,21 +110,43 @@ #if !defined(PERI_EIM_H_) #define PERI_EIM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EMVSIM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EMVSIM.h index 29212f3da..1148eff7b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EMVSIM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EMVSIM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for EMVSIM @@ -70,21 +110,43 @@ #if !defined(PERI_EMVSIM_H_) #define PERI_EMVSIM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ENET.h index 51e1032e9..1ede5bd34 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ENET.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET @@ -70,21 +110,43 @@ #if !defined(PERI_ENET_H_) #define PERI_ENET_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ERM.h index 15a775d37..3348262b7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ERM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ERM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for ERM @@ -70,21 +110,43 @@ #if !defined(PERI_ERM_H_) #define PERI_ERM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EVTG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EVTG.h index 04bb77fa3..e677a24d7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EVTG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EVTG.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for EVTG @@ -70,21 +110,43 @@ #if !defined(PERI_EVTG_H_) #define PERI_EVTG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EWM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EWM.h index e8999bf8e..4035f7a60 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EWM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_EWM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for EWM @@ -70,21 +110,43 @@ #if !defined(PERI_EWM_H_) #define PERI_EWM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FLEXIO.h index 815a1c436..6e11e14f9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FLEXIO.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO @@ -70,21 +110,43 @@ #if !defined(PERI_FLEXIO_H_) #define PERI_FLEXIO_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FLEXSPI.h index 9927d248e..ffbf3d125 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FLEXSPI.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -70,21 +110,43 @@ #if !defined(PERI_FLEXSPI_H_) #define PERI_FLEXSPI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FMU.h index 0d588850b..8684c6c0f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FMU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FMU.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMU @@ -70,21 +110,43 @@ #if !defined(PERI_FMU_H_) #define PERI_FMU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FMUTEST.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FMUTEST.h index db3899d9f..ca21e22a7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FMUTEST.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FMUTEST.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMUTEST @@ -70,21 +110,43 @@ #if !defined(PERI_FMUTEST_H_) #define PERI_FMUTEST_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FREQME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FREQME.h index c6befeb6e..74b2a166a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FREQME.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_FREQME.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for FREQME @@ -70,21 +110,43 @@ #if !defined(PERI_FREQME_H_) #define PERI_FREQME_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_GDET.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_GDET.h index 1de7a8bb6..c2e7621af 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_GDET.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_GDET.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for GDET @@ -70,21 +110,43 @@ #if !defined(PERI_GDET_H_) #define PERI_GDET_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_GPIO.h index 581d57d7a..e354196c6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_GPIO.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO @@ -70,21 +110,43 @@ #if !defined(PERI_GPIO_H_) #define PERI_GPIO_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_HPDAC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_HPDAC.h index af024a28d..d6112d32e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_HPDAC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_HPDAC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for HPDAC @@ -70,21 +110,43 @@ #if !defined(PERI_HPDAC_H_) #define PERI_HPDAC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_I2S.h index 0067bb989..daf828eb2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_I2S.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S @@ -70,21 +110,43 @@ #if !defined(PERI_I2S_H_) #define PERI_I2S_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_I3C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_I3C.h index 321a0434f..c359d0435 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_I3C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_I3C.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for I3C @@ -70,21 +110,43 @@ #if !defined(PERI_I3C_H_) #define PERI_I3C_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_INPUTMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_INPUTMUX.h index 5e6934996..83136d919 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_INPUTMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_INPUTMUX.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for INPUTMUX @@ -70,21 +110,43 @@ #if !defined(PERI_INPUTMUX_H_) #define PERI_INPUTMUX_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_INTM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_INTM.h index d6c401e05..e5f788249 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_INTM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_INTM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for INTM @@ -70,21 +110,43 @@ #if !defined(PERI_INTM_H_) #define PERI_INTM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ITRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ITRC.h index 51a2d0333..382c154df 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ITRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_ITRC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for ITRC @@ -70,21 +110,43 @@ #if !defined(PERI_ITRC_H_) #define PERI_ITRC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPCMP.h index 398027367..86ab1dcb6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPCMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPCMP.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPCMP @@ -70,21 +110,43 @@ #if !defined(PERI_LPCMP_H_) #define PERI_LPCMP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPDAC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPDAC.h index 1a2bb7512..14aaf6ded 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPDAC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPDAC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPDAC @@ -70,21 +110,43 @@ #if !defined(PERI_LPDAC_H_) #define PERI_LPDAC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPI2C.h index 049734e27..b1fa409e1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPI2C.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -70,21 +110,43 @@ #if !defined(PERI_LPI2C_H_) #define PERI_LPI2C_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPSPI.h index 6bf8944f4..55cf611a6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPSPI.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI @@ -70,21 +110,43 @@ #if !defined(PERI_LPSPI_H_) #define PERI_LPSPI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPTMR.h index f1abfbbb0..e27d59a0b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPTMR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPTMR.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPTMR @@ -70,21 +110,43 @@ #if !defined(PERI_LPTMR_H_) #define PERI_LPTMR_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPUART.h index 39ab8b4d1..b789e7fc0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LPUART.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART @@ -70,21 +110,43 @@ #if !defined(PERI_LPUART_H_) #define PERI_LPUART_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LP_FLEXCOMM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LP_FLEXCOMM.h index b54975e9b..e409032e1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LP_FLEXCOMM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_LP_FLEXCOMM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for LP_FLEXCOMM @@ -70,21 +110,43 @@ #if !defined(PERI_LP_FLEXCOMM_H_) #define PERI_LP_FLEXCOMM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_MAILBOX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_MAILBOX.h index 2f8d8777b..9d6919928 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_MAILBOX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_MAILBOX.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for MAILBOX @@ -70,21 +110,43 @@ #if !defined(PERI_MAILBOX_H_) #define PERI_MAILBOX_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_MRT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_MRT.h index 82f838e47..59f6fbab9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_MRT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_MRT.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for MRT @@ -70,21 +110,43 @@ #if !defined(PERI_MRT_H_) #define PERI_MRT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_NPX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_NPX.h index cf44c48ee..7f5284612 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_NPX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_NPX.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for NPX @@ -70,21 +110,43 @@ #if !defined(PERI_NPX_H_) #define PERI_NPX_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OPAMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OPAMP.h index b6dd5b006..52f5c02d5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OPAMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OPAMP.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for OPAMP @@ -70,21 +110,43 @@ #if !defined(PERI_OPAMP_H_) #define PERI_OPAMP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OSTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OSTIMER.h index fc43651c6..adb0bdc4a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OSTIMER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OSTIMER.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSTIMER @@ -70,21 +110,43 @@ #if !defined(PERI_OSTIMER_H_) #define PERI_OSTIMER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OTPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OTPC.h index 3f38ef3ed..b0fa07911 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OTPC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_OTPC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for OTPC @@ -70,21 +110,43 @@ #if !defined(PERI_OTPC_H_) #define PERI_OTPC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PDM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PDM.h index 6d00c419a..1c98ab27d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PDM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PDM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for PDM @@ -70,21 +110,43 @@ #if !defined(PERI_PDM_H_) #define PERI_PDM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PINT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PINT.h index df4b26ac8..f3fde4a09 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PINT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PINT.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for PINT @@ -70,21 +110,43 @@ #if !defined(PERI_PINT_H_) #define PERI_PINT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PKC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PKC.h index 8bd719c8c..c9ce7327f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PKC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PKC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for PKC @@ -70,21 +110,43 @@ #if !defined(PERI_PKC_H_) #define PERI_PKC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PLU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PLU.h index 34051ddda..a2aa55b86 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PLU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PLU.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for PLU @@ -70,21 +110,43 @@ #if !defined(PERI_PLU_H_) #define PERI_PLU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PORT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PORT.h index c29193050..c5478d74a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PORT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PORT.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for PORT @@ -70,21 +110,43 @@ #if !defined(PERI_PORT_H_) #define PERI_PORT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_POWERQUAD.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_POWERQUAD.h index 7b20c6fec..d4fcaeaf7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_POWERQUAD.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_POWERQUAD.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for POWERQUAD @@ -70,21 +110,43 @@ #if !defined(PERI_POWERQUAD_H_) #define PERI_POWERQUAD_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PUF.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PUF.h index b8263164a..6a6a308e6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PUF.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PUF.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for PUF @@ -70,21 +110,43 @@ #if !defined(PERI_PUF_H_) #define PERI_PUF_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PWM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PWM.h index a2aa51f8b..8757dae94 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PWM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_PWM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for PWM @@ -70,21 +110,43 @@ #if !defined(PERI_PWM_H_) #define PERI_PWM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_QDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_QDC.h index 049b8b294..5c3316455 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_QDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_QDC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for QDC @@ -70,21 +110,43 @@ #if !defined(PERI_QDC_H_) #define PERI_QDC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_RTC.h index c0f184ce4..ca9733ce2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_RTC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -70,21 +110,43 @@ #if !defined(PERI_RTC_H_) #define PERI_RTC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_S50.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_S50.h index ed3d295bc..6a985d263 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_S50.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_S50.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for S50 @@ -70,21 +110,43 @@ #if !defined(PERI_S50_H_) #define PERI_S50_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SCG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SCG.h index d19e6a689..131ebb2a1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SCG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SCG.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for SCG @@ -70,21 +110,43 @@ #if !defined(PERI_SCG_H_) #define PERI_SCG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SCT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SCT.h index ffa079e95..16fc992c0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SCT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SCT.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for SCT @@ -70,21 +110,43 @@ #if !defined(PERI_SCT_H_) #define PERI_SCT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SEMA42.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SEMA42.h index 1fb34f6cb..a5751213d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SEMA42.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SEMA42.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMA42 @@ -70,21 +110,43 @@ #if !defined(PERI_SEMA42_H_) #define PERI_SEMA42_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SINC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SINC.h index 2876c53a8..3a54b27a9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SINC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SINC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for SINC @@ -70,21 +110,43 @@ #if !defined(PERI_SINC_H_) #define PERI_SINC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SMARTDMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SMARTDMA.h index a5909c051..284574873 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SMARTDMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SMARTDMA.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for SMARTDMA @@ -70,21 +110,43 @@ #if !defined(PERI_SMARTDMA_H_) #define PERI_SMARTDMA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SPC.h index 4c6ac56b5..a152e53ce 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SPC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SPC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPC @@ -70,21 +110,43 @@ #if !defined(PERI_SPC_H_) #define PERI_SPC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SYSCON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SYSCON.h index ac15cd10b..4ae39d6fb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SYSCON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SYSCON.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON @@ -70,21 +110,43 @@ #if !defined(PERI_SYSCON_H_) #define PERI_SYSCON_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SYSPM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SYSPM.h index 59bd33e30..b58819635 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SYSPM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_SYSPM.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSPM @@ -70,21 +110,43 @@ #if !defined(PERI_SYSPM_H_) #define PERI_SYSPM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_TRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_TRDC.h index 73ec50828..53f734ef6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_TRDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_TRDC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC @@ -70,21 +110,43 @@ #if !defined(PERI_TRDC_H_) #define PERI_TRDC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_TSI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_TSI.h index 2f872cfbf..fcae8c8c1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_TSI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_TSI.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for TSI @@ -70,21 +110,43 @@ #if !defined(PERI_TSI_H_) #define PERI_TSI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USB.h index 719ba6eba..6f918432c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USB.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB @@ -70,21 +110,43 @@ #if !defined(PERI_USB_H_) #define PERI_USB_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBDCD.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBDCD.h index 5ab5d7b50..63f1eb411 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBDCD.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBDCD.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBDCD @@ -70,21 +110,43 @@ #if !defined(PERI_USBDCD_H_) #define PERI_USBDCD_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBHS.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBHS.h index 5e948662d..8e6ff856c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBHS.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBHS.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBHS @@ -70,21 +110,43 @@ #if !defined(PERI_USBHS_H_) #define PERI_USBHS_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBHSDCD.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBHSDCD.h index 27b15a966..8b62814da 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBHSDCD.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBHSDCD.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBHSDCD @@ -70,21 +110,43 @@ #if !defined(PERI_USBHSDCD_H_) #define PERI_USBHSDCD_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBNC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBNC.h index ce8433302..fba4fe9fc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBNC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBNC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBNC @@ -70,21 +110,43 @@ #if !defined(PERI_USBNC_H_) #define PERI_USBNC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBPHY.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBPHY.h index 697efc1fc..97ae96164 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBPHY.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USBPHY.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBPHY @@ -70,21 +110,43 @@ #if !defined(PERI_USBPHY_H_) #define PERI_USBPHY_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USDHC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USDHC.h index 00558e1d9..7f834076e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USDHC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_USDHC.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for USDHC @@ -70,21 +110,43 @@ #if !defined(PERI_USDHC_H_) #define PERI_USDHC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_UTICK.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_UTICK.h index 9442c6a3e..08c756428 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_UTICK.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_UTICK.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for UTICK @@ -70,21 +110,43 @@ #if !defined(PERI_UTICK_H_) #define PERI_UTICK_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_VBAT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_VBAT.h index af2d42b01..36251d27f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_VBAT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_VBAT.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for VBAT @@ -70,21 +110,43 @@ #if !defined(PERI_VBAT_H_) #define PERI_VBAT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_VREF.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_VREF.h index a3f845253..80910c73d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_VREF.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_VREF.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for VREF @@ -70,21 +110,43 @@ #if !defined(PERI_VREF_H_) #define PERI_VREF_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_WUU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_WUU.h index e9670af88..f578e8873 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_WUU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_WUU.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for WUU @@ -70,21 +110,43 @@ #if !defined(PERI_WUU_H_) #define PERI_WUU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_WWDT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_WWDT.h index 8f99c46ea..ba5a2d15a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_WWDT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph/PERI_WWDT.h @@ -1,6 +1,38 @@ /* ** ################################################################### -** Processors: MCXN546VDF_cm33_core0 +** Processors: MCXN247VAB +** MCXN247VDF +** MCXN247VKL +** MCXN247VPB +** MCXN526VDF_cm33_core0 +** MCXN526VDF_cm33_core1 +** MCXN526VKL_cm33_core0 +** MCXN526VKL_cm33_core1 +** MCXN527VAB_cm33_core0 +** MCXN527VAB_cm33_core1 +** MCXN527VDF_cm33_core0 +** MCXN527VDF_cm33_core1 +** MCXN527VKL_cm33_core0 +** MCXN527VKL_cm33_core1 +** MCXN536VAB_cm33_core0 +** MCXN536VAB_cm33_core1 +** MCXN536VDF_cm33_core0 +** MCXN536VDF_cm33_core1 +** MCXN536VKL_cm33_core0 +** MCXN536VKL_cm33_core1 +** MCXN536VPB_cm33_core0 +** MCXN536VPB_cm33_core1 +** MCXN537VAB_cm33_core0 +** MCXN537VAB_cm33_core1 +** MCXN537VDF_cm33_core0 +** MCXN537VDF_cm33_core1 +** MCXN537VKL_cm33_core0 +** MCXN537VKL_cm33_core1 +** MCXN537VPB_cm33_core0 +** MCXN537VPB_cm33_core1 +** MCXN546VAB_cm33_core0 +** MCXN546VAB_cm33_core1 +** MCXN546VDF_cm33_core0 ** MCXN546VDF_cm33_core1 ** MCXN546VKL_cm33_core0 ** MCXN546VKL_cm33_core1 @@ -8,6 +40,8 @@ ** MCXN546VNL_cm33_core1 ** MCXN546VPB_cm33_core0 ** MCXN546VPB_cm33_core1 +** MCXN547VAB_cm33_core0 +** MCXN547VAB_cm33_core1 ** MCXN547VDF_cm33_core0 ** MCXN547VDF_cm33_core1 ** MCXN547VKL_cm33_core0 @@ -16,6 +50,10 @@ ** MCXN547VNL_cm33_core1 ** MCXN547VPB_cm33_core0 ** MCXN547VPB_cm33_core1 +** MCXN556SCDF_cm33_core0 +** MCXN556SCDF_cm33_core1 +** MCXN946VAB_cm33_core0 +** MCXN946VAB_cm33_core1 ** MCXN946VDF_cm33_core0 ** MCXN946VDF_cm33_core1 ** MCXN946VKL_cm33_core0 @@ -24,6 +62,8 @@ ** MCXN946VNL_cm33_core1 ** MCXN946VPB_cm33_core0 ** MCXN946VPB_cm33_core1 +** MCXN947VAB_cm33_core0 +** MCXN947VAB_cm33_core1 ** MCXN947VDF_cm33_core0 ** MCXN947VDF_cm33_core1 ** MCXN947VKL_cm33_core0 @@ -34,7 +74,7 @@ ** MCXN947VPB_cm33_core1 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250521 +** Build: b250811 ** ** Abstract: ** CMSIS Peripheral Access Layer for WWDT @@ -70,21 +110,43 @@ #if !defined(PERI_WWDT_H_) #define PERI_WWDT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) +#if (defined(CPU_MCXN247VAB) || defined(CPU_MCXN247VDF) || defined(CPU_MCXN247VKL) || defined(CPU_MCXN247VPB)) +#include "MCXN247_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core0) || defined(CPU_MCXN526VKL_cm33_core0)) +#include "MCXN526_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN526VDF_cm33_core1) || defined(CPU_MCXN526VKL_cm33_core1)) +#include "MCXN526_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core0) || defined(CPU_MCXN527VDF_cm33_core0) || defined(CPU_MCXN527VKL_cm33_core0)) +#include "MCXN527_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN527VAB_cm33_core1) || defined(CPU_MCXN527VDF_cm33_core1) || defined(CPU_MCXN527VKL_cm33_core1)) +#include "MCXN527_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core0) || defined(CPU_MCXN536VDF_cm33_core0) || defined(CPU_MCXN536VKL_cm33_core0) || defined(CPU_MCXN536VPB_cm33_core0)) +#include "MCXN536_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN536VAB_cm33_core1) || defined(CPU_MCXN536VDF_cm33_core1) || defined(CPU_MCXN536VKL_cm33_core1) || defined(CPU_MCXN536VPB_cm33_core1)) +#include "MCXN536_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core0) || defined(CPU_MCXN537VDF_cm33_core0) || defined(CPU_MCXN537VKL_cm33_core0) || defined(CPU_MCXN537VPB_cm33_core0)) +#include "MCXN537_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN537VAB_cm33_core1) || defined(CPU_MCXN537VDF_cm33_core1) || defined(CPU_MCXN537VKL_cm33_core1) || defined(CPU_MCXN537VPB_cm33_core1)) +#include "MCXN537_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN546VAB_cm33_core0) || defined(CPU_MCXN546VDF_cm33_core0) || defined(CPU_MCXN546VKL_cm33_core0) || defined(CPU_MCXN546VNL_cm33_core0) || defined(CPU_MCXN546VPB_cm33_core0)) #include "MCXN546_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) +#elif (defined(CPU_MCXN546VAB_cm33_core1) || defined(CPU_MCXN546VDF_cm33_core1) || defined(CPU_MCXN546VKL_cm33_core1) || defined(CPU_MCXN546VNL_cm33_core1) || defined(CPU_MCXN546VPB_cm33_core1)) #include "MCXN546_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) +#elif (defined(CPU_MCXN547VAB_cm33_core0) || defined(CPU_MCXN547VDF_cm33_core0) || defined(CPU_MCXN547VKL_cm33_core0) || defined(CPU_MCXN547VNL_cm33_core0) || defined(CPU_MCXN547VPB_cm33_core0)) #include "MCXN547_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) +#elif (defined(CPU_MCXN547VAB_cm33_core1) || defined(CPU_MCXN547VDF_cm33_core1) || defined(CPU_MCXN547VKL_cm33_core1) || defined(CPU_MCXN547VNL_cm33_core1) || defined(CPU_MCXN547VPB_cm33_core1)) #include "MCXN547_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) +#elif (defined(CPU_MCXN556SCDF_cm33_core0)) +#include "MCXN556S_cm33_core0_COMMON.h" +#elif (defined(CPU_MCXN556SCDF_cm33_core1)) +#include "MCXN556S_cm33_core1_COMMON.h" +#elif (defined(CPU_MCXN946VAB_cm33_core0) || defined(CPU_MCXN946VDF_cm33_core0) || defined(CPU_MCXN946VKL_cm33_core0) || defined(CPU_MCXN946VNL_cm33_core0) || defined(CPU_MCXN946VPB_cm33_core0)) #include "MCXN946_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) +#elif (defined(CPU_MCXN946VAB_cm33_core1) || defined(CPU_MCXN946VDF_cm33_core1) || defined(CPU_MCXN946VKL_cm33_core1) || defined(CPU_MCXN946VNL_cm33_core1) || defined(CPU_MCXN946VPB_cm33_core1)) #include "MCXN946_cm33_core1_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) +#elif (defined(CPU_MCXN947VAB_cm33_core0) || defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VKL_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0) || defined(CPU_MCXN947VPB_cm33_core0)) #include "MCXN947_cm33_core0_COMMON.h" -#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) +#elif (defined(CPU_MCXN947VAB_cm33_core1) || defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VKL_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1) || defined(CPU_MCXN947VPB_cm33_core1)) #include "MCXN947_cm33_core1_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph_mapping.md b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph_mapping.md index c7362c6d2..bcbc7353b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph_mapping.md +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXN/periph_mapping.md @@ -1,3 +1,3 @@ #### Peripheral folder for devices -* periph:MCXN546,MCXN547,MCXN946,MCXN947 +* periph:MCXN247,MCXN526,MCXN527,MCXN536,MCXN537,MCXN546,MCXN547,MCXN556S,MCXN946,MCXN947 * periph1:MCXN235,MCXN236 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235.h index 8a908879b..4e53fbd78 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** ** Compilers: @@ -9,9 +11,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXW23x User manual Rev.0.1 1 September 2022 +** Reference manual: MCXW23x User manual Rev. 1.0 - 7 April 2025 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW235 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235_COMMON.h index 7e581bd85..8fd58941d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235_COMMON.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** ** Compilers: @@ -9,9 +11,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXW23x User manual Rev.0.1 1 September 2022 +** Reference manual: MCXW23x User manual Rev. 1.0 - 7 April 2025 ** Version: rev. 2.0, 2024-10-29 -** Build: b250526 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW235 @@ -1652,7 +1654,7 @@ typedef enum IRQn { #define WWDT_BASE_PTRS { WWDT } #endif /** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { { WDT_BOD_IRQn, WDT_IRQn } } +#define WWDT_IRQS { { WDT_IRQn, WDT_BOD_IRQn } } /* ---------------------------------------------------------------------------- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). @@ -1677,14 +1679,14 @@ typedef enum IRQn { * @param value Value of the bit field. * @return Masked and shifted value. */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +#define NXP_VAL2FLD(field, value) (((value) << (field##_SHIFT)) & (field##_MASK)) /** * @brief Mask and right-shift a register value to extract a bit field value. * @param field Name of the register bit field. * @param value Value of the register. * @return Masked and shifted bit field value. */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) +#define NXP_FLD2VAL(field, value) (((value) & (field##_MASK)) >> (field##_SHIFT)) /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235_features.h index c392a423d..602d3f9ca 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/MCXW235_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-08 -** Build: b250603 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -228,6 +228,8 @@ #define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (1079304) /* @brief Puf Activation Code Size. */ #define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1192) +/* @brief PUF has key reset. */ +#define FSL_FEATURE_PUF_HAS_KEYRESET (1) /* RTC module features */ @@ -244,6 +246,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -266,17 +270,22 @@ /* @brief Flash phrase size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_PHRASE_SIZE_BYTES (16) -#define FSL_FEATURE_FLASH_PHRASE_SIZE_BYTES FSL_FEATURE_SYSCON_FLASH_PHRASE_SIZE_BYTES +/* @brief Flash phrase size in bytes */ +#define FSL_FEATURE_FLASH_PHRASE_SIZE_BYTES (FSL_FEATURE_SYSCON_FLASH_PHRASE_SIZE_BYTES) /* @brief Flash page size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) -#define FSL_FEATURE_FLASH_PAGE_SIZE_BYTES FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_FLASH_PAGE_SIZE_BYTES (FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES) /* @brief Flash sector size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) -#define FSL_FEATURE_FLASH_SECTOR_SIZE_BYTES FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES -#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES * 56) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_FLASH_SECTOR_SIZE_BYTES (FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES) +/* @brief Flash block size in bytes */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (458752) /* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (655360) +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) /* @brief Has Power Down mode */ #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) /* @brief CCM_ANALOG availability on the SoC. */ @@ -301,12 +310,20 @@ /* @brief TRNG has no TRNG_ACC bitfield. */ #define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (0) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXW235_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/fsl_device_registers.h index eb25493ed..8061a7a8d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/fsl_device_registers.h @@ -13,7 +13,7 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/startup_MCXW235.c b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/startup_MCXW235.c index 49fa3ecf0..4aea87bcc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/startup_MCXW235.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/startup_MCXW235.c @@ -1,7 +1,7 @@ //***************************************************************************** // MCXW235 startup code // -// Version : 130525 +// Version : 190825 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/startup_MCXW235.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/startup_MCXW235.cpp index 49fa3ecf0..4aea87bcc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/startup_MCXW235.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/startup_MCXW235.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MCXW235 startup code // -// Version : 130525 +// Version : 190825 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/system_MCXW235.c b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/system_MCXW235.c index 6ef70dffd..6fc414ee8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/system_MCXW235.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/system_MCXW235.c @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** ** Compilers: @@ -9,9 +11,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXW23x User manual Rev.0.1 1 September 2022 +** Reference manual: MCXW23x User manual Rev. 1.0 - 7 April 2025 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -93,11 +95,11 @@ __attribute__ ((weak)) void SystemInit (void) { if (irq == BLE_LL_IRQn || irq == BLE_SLP_TMR_IRQn) { - NVIC_SetPriority(irq, NVIC_LL_IRQ_PRIORITY); + NVIC_SetPriority((IRQn_Type)irq, NVIC_LL_IRQ_PRIORITY); } else { - NVIC_SetPriority(irq, NVIC_DEFAULT_PRIORITY); + NVIC_SetPriority((IRQn_Type)irq, NVIC_DEFAULT_PRIORITY); } } #endif @@ -311,6 +313,7 @@ __attribute__((used)) void HardFaultHandler(uint32_t *hardfault_args) } } +#ifndef CONFIG_TFM_BUILDING_SPE __attribute__((naked)) void HardFault_Handler(void) { __asm volatile( @@ -340,3 +343,4 @@ __attribute__((naked)) void UsageFault_Handler(void) { __asm volatile(" b HardFault_Handler \n"); } +#endif diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/system_MCXW235.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/system_MCXW235.h index 3e24a3ffd..a13880f90 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/system_MCXW235.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW235/system_MCXW235.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** ** Compilers: @@ -9,9 +11,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXW23x User manual Rev.0.1 1 September 2022 +** Reference manual: MCXW23x User manual Rev. 1.0 - 7 April 2025 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -56,7 +58,7 @@ extern "C" { #include #if defined(SDK_OS_FREE_RTOS) #include "FreeRTOSConfig.h" -#endif +#endif #define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ #define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ @@ -155,4 +157,4 @@ extern void __assert_equal_func(uint32_t a, uint32_t b); } #endif -#endif /* _SYSTEM_MCXW235_H_ */ \ No newline at end of file +#endif /* _SYSTEM_MCXW235_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236.h index d58cac1ee..b0e8e4c38 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236.h @@ -11,9 +11,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXW23x User manual Rev.0.1 1 September 2022 +** Reference manual: MCXW23x User manual Rev. 1.0 - 7 April 2025 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW236 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236_COMMON.h index d4003448a..392465e3e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236_COMMON.h @@ -11,9 +11,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXW23x User manual Rev.0.1 1 September 2022 +** Reference manual: MCXW23x User manual Rev. 1.0 - 7 April 2025 ** Version: rev. 2.0, 2024-10-29 -** Build: b250526 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW236 @@ -1654,7 +1654,7 @@ typedef enum IRQn { #define WWDT_BASE_PTRS { WWDT } #endif /** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { { WDT_BOD_IRQn, WDT_IRQn } } +#define WWDT_IRQS { { WDT_IRQn, WDT_BOD_IRQn } } /* ---------------------------------------------------------------------------- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). @@ -1679,14 +1679,14 @@ typedef enum IRQn { * @param value Value of the bit field. * @return Masked and shifted value. */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +#define NXP_VAL2FLD(field, value) (((value) << (field##_SHIFT)) & (field##_MASK)) /** * @brief Mask and right-shift a register value to extract a bit field value. * @param field Name of the register bit field. * @param value Value of the register. * @return Masked and shifted bit field value. */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) +#define NXP_FLD2VAL(field, value) (((value) & (field##_MASK)) >> (field##_SHIFT)) /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236_features.h index 5bacbbe84..b962ac1ff 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/MCXW236_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2022-03-08 -** Build: b250603 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -246,6 +246,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECPINT module features */ @@ -268,15 +270,20 @@ /* @brief Flash phrase size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_PHRASE_SIZE_BYTES (16) -#define FSL_FEATURE_FLASH_PHRASE_SIZE_BYTES FSL_FEATURE_SYSCON_FLASH_PHRASE_SIZE_BYTES +/* @brief Flash phrase size in bytes */ +#define FSL_FEATURE_FLASH_PHRASE_SIZE_BYTES (FSL_FEATURE_SYSCON_FLASH_PHRASE_SIZE_BYTES) /* @brief Flash page size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) -#define FSL_FEATURE_FLASH_PAGE_SIZE_BYTES FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_FLASH_PAGE_SIZE_BYTES (FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES) /* @brief Flash sector size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) -#define FSL_FEATURE_FLASH_SECTOR_SIZE_BYTES FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES -#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES * 56) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_FLASH_SECTOR_SIZE_BYTES (FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES) +/* @brief Flash block size in bytes */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (458752) /* @brief Flash size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1040384) /* @brief Has Power Down mode */ @@ -303,12 +310,20 @@ /* @brief TRNG has no TRNG_ACC bitfield. */ #define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (0) +/* UTICK module features */ + +/* No feature definitions */ + /* WWDT module features */ -/* @brief Has no RESET register. */ -#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief soc has reset. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MCXW236_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/CMakeLists_clock.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/CMakeLists_clock.txt index 8654f72d6..fa2e3f56e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/CMakeLists_clock.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/CMakeLists_clock.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.1.1) + mcux_component_version(2.1.3) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h) mcux_add_include( INCLUDES . ) endif() diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/CMakeLists_power_manager.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/CMakeLists_power_manager.txt index 27748da72..102280bd2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/CMakeLists_power_manager.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/CMakeLists_power_manager.txt @@ -22,8 +22,4 @@ if (CONFIG_MCUX_COMPONENT_component.power_manager.mcxw23) mcux_add_include( INCLUDES power_manager_mcxw23/device ) - - mcux_add_configuration( - CC "-DENABLE_LOW_POWER=1" - ) endif() diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/fsl_clock.h index 0863e7cf6..a11ec0c2f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/fsl_clock.h @@ -19,8 +19,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.1.2. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @brief CLOCK driver version 2.1.3. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*@}*/ /* Definition for delay API in clock driver, users can redefine it to the real application. */ @@ -523,6 +523,7 @@ typedef enum _clock_attach_id kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, SCTCLKSEL_CLKIN), kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, SCTCLKSEL_FRO_32MHz), kFRO24M_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, SCTCLKSEL_FRO_24MHz), + kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, SCTCLKSEL_NO_CLOCK), kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, RTCOSC32K_SEL_FRO), kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, RTCOSC32K_SEL_XTAL), diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/power_manager_mcxw23/core/fsl_pm_app.c b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/power_manager_mcxw23/core/fsl_pm_app.c index 39e47b74e..200a66ee0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/power_manager_mcxw23/core/fsl_pm_app.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/drivers/power_manager_mcxw23/core/fsl_pm_app.c @@ -11,6 +11,9 @@ #ifdef SDK_OS_FREE_RTOS #include "task.h" #endif /* SDK_OS_FREE_RTOS */ +#ifdef FSL_RTOS_THREADX +#include "tx_low_power.h" +#endif static uint32_t s_initialSysTickLoad = 0; static uint64_t s_systickStopTimeUs = 0; @@ -35,7 +38,7 @@ status_t PMAPP_EnterLowPower(uint32_t sleepDuration) /* Capture the time at which the systick timer is stopped */ s_systickStopTimeUs = PMDEVICE_GetSleepTimer(); -#ifdef SDK_OS_FREE_RTOS +#if defined(SDK_OS_FREE_RTOS) || defined(FSL_RTOS_THREADX) /* Disable Systicks for tickless mode */ SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk); #endif /* SDK_OS_FREE_RTOS */ @@ -68,7 +71,7 @@ status_t PMAPP_EnterLowPower(uint32_t sleepDuration) s_smallestHeadroom = wakeupHeadroom; } } -#ifdef SDK_OS_FREE_RTOS +#if defined(SDK_OS_FREE_RTOS) || defined(FSL_RTOS_THREADX) uint32_t systickValue; uint64_t systickRestartTimeUs; @@ -88,7 +91,11 @@ status_t PMAPP_EnterLowPower(uint32_t sleepDuration) uint32_t correction = systickValue / s_initialSysTickLoad; /* Inform OS about the skipped OS ticks */ +#if defined(SDK_OS_FREE_RTOS) vTaskStepTick(correction); +#elif defined(FSL_RTOS_THREADX) + tx_time_increment(correction); +#endif /* Adjust the phase of systick. SysTick->VAL does not accept any value other than 0. * Hence, LOAD is manipulated to adjust the phase. It is restored to the diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/startup_MCXW236.c b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/startup_MCXW236.c index cf129f037..43976d51d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/startup_MCXW236.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/startup_MCXW236.c @@ -1,7 +1,7 @@ //***************************************************************************** // MCXW236 startup code // -// Version : 130525 +// Version : 190825 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/startup_MCXW236.cpp b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/startup_MCXW236.cpp index cf129f037..43976d51d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/startup_MCXW236.cpp +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/startup_MCXW236.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MCXW236 startup code // -// Version : 130525 +// Version : 190825 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/system_MCXW236.c b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/system_MCXW236.c index 969dcb313..c3181852e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/system_MCXW236.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/system_MCXW236.c @@ -11,9 +11,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXW23x User manual Rev.0.1 1 September 2022 +** Reference manual: MCXW23x User manual Rev. 1.0 - 7 April 2025 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -343,4 +343,4 @@ __attribute__((naked)) void UsageFault_Handler(void) { __asm volatile(" b HardFault_Handler \n"); } -#endif \ No newline at end of file +#endif diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/system_MCXW236.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/system_MCXW236.h index 6749ea03f..aaa45252a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/system_MCXW236.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW236/system_MCXW236.h @@ -11,9 +11,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCXW23x User manual Rev.0.1 1 September 2022 +** Reference manual: MCXW23x User manual Rev. 1.0 - 7 April 2025 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -58,7 +58,7 @@ extern "C" { #include #if defined(SDK_OS_FREE_RTOS) #include "FreeRTOSConfig.h" -#endif +#endif #define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ #define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ @@ -157,4 +157,4 @@ extern void __assert_equal_func(uint32_t a, uint32_t b); } #endif -#endif /* _SYSTEM_MCXW236_H_ */ \ No newline at end of file +#endif /* _SYSTEM_MCXW236_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716A/MCXW716A_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716A/MCXW716A_COMMON.h index e871017ac..de63b65d7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716A/MCXW716A_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716A/MCXW716A_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: Rev. 1, April 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW716A @@ -2245,6 +2245,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716A/MCXW716A_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716A/MCXW716A_features.h index 025c4046d..707287e30 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716A/MCXW716A_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716A/MCXW716A_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-21 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -203,6 +203,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -242,8 +247,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -272,6 +275,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -321,8 +326,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -409,8 +436,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -453,6 +478,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -546,14 +575,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -576,6 +617,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/MCXW716C_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/MCXW716C_COMMON.h index bc8576cba..9a6ecb1ac 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/MCXW716C_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/MCXW716C_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: Rev. 1, April 2024 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW716C @@ -2281,6 +2281,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/MCXW716C_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/MCXW716C_features.h index d5f0f8b39..35c30fae1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/MCXW716C_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/MCXW716C_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-03-21 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -253,6 +253,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -276,6 +280,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -315,8 +324,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -345,6 +352,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -394,8 +403,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -482,8 +513,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -526,6 +555,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -619,14 +652,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -649,6 +694,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/CMakeLists_clock.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/CMakeLists_clock.txt index a75567792..f4896e3f1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/CMakeLists_clock.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/CMakeLists_clock.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.2.2) + mcux_component_version(2.2.4) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) mcux_add_include( INCLUDES . ) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/CMakeLists_romapi.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/CMakeLists_romapi.txt index 59474a041..6d754d155 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/CMakeLists_romapi.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/CMakeLists_romapi.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.romapi_soc) - mcux_component_version(1.2.1) + mcux_component_version(1.2.2) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/fsl_clock.c index a28b2556d..b202e80ee 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/fsl_clock.c @@ -737,7 +737,7 @@ status_t CLOCK_InitRfFro192M(const fro192m_rf_clk_config_t *config) */ uint32_t CLOCK_GetRfFro192MFreq(void) { - static const uint32_t fro192mFreq[] = {16000000U, 24000000U, 32000000U, 48000000U, 64000000U}; + static const uint32_t fro192mFreq[] = {16000000U, 24000000U, 32000000U, 48000000U, 64000000U, 0U, 0U, 0U}; /* * $Branch Coverage Justification$ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/fsl_clock.h index 715bb63d2..088a57072 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/fsl_clock.h @@ -38,8 +38,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.2.2. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*! @brief CLOCK driver version 2.2.4. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) /*@}*/ /* Definition for delay API in clock driver, users can redefine it to the real application. */ @@ -349,6 +349,13 @@ typedef enum _scg_sys_clk /*! * @brief SCG system clock source. + * + * ERR052742: FRO6M clock(kSCG_SysClkSrcSirc) is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. */ typedef enum _scg_sys_clk_src { @@ -681,6 +688,12 @@ static inline void CLOCK_DisableTPM2(void) * Set the clock source for specific IP, not all modules need to set the * clock source, should only use this function for the modules need source * setting. + * ERR052742: FRO6M clock is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. * * @param name Which peripheral to check, see \ref clock_ip_name_t. * @param src Clock source to set. diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/romapi/fsl_flash_api.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/romapi/fsl_flash_api.h index 00aaa47de..e2b36bdcc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/romapi/fsl_flash_api.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/romapi/fsl_flash_api.h @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,7 +22,7 @@ * @{ */ /*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 1)) /*!< Version 1.2.1. */ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 2)) /*!< Version 1.2.2. */ /*@}*/ /*! @brief Constructs the four character code for the Flash driver API key. */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/romapi/fsl_romapi.c b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/romapi/fsl_romapi.c index 1e306e0be..6f70e9086 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/romapi/fsl_romapi.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW716C/drivers/romapi/fsl_romapi.c @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,7 +15,7 @@ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "driver.romapi" +#define FSL_COMPONENT_ID "driver.romapi_soc" #endif /* @@ -416,12 +416,12 @@ static status_t flash_check_param( status = kStatus_FLASH_Success; } #if defined(RF_FMU) - else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU))) + else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU)) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } #else - else if ((config == NULL) || (base == NULL) || (base != FMU0)) + else if ((config == NULL) || (base == NULL) || (base != FMU0) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0.h index 8e3358301..a99c04f42 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727A_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0_COMMON.h index 645b669c4..e38498f01 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727A_cm33_core0 @@ -2337,22 +2337,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2362,6 +2368,55 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(MCXW727A_cm33_core1_H_) || defined(MCXW727C_cm33_core1_H_) || defined(MCXW727D_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0_features.h index ab59aa2c4..6d2980956 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250522 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -207,6 +207,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -246,8 +251,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -276,6 +279,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -335,8 +340,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -423,8 +440,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -467,6 +482,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -552,18 +571,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -586,6 +619,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1.h index 901f4403e..6177a3487 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727A_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1_COMMON.h index 553c350e5..1214bfa48 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727A_cm33_core1 @@ -952,22 +952,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -977,6 +983,55 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(MCXW727A_cm33_core1_H_) || defined(MCXW727C_cm33_core1_H_) || defined(MCXW727D_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1_features.h index 14102b43d..fd5e98a7b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/MCXW727A_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250522 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -219,6 +219,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -258,8 +263,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -288,6 +291,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -347,8 +352,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -435,8 +452,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -479,6 +494,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -559,18 +578,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -593,6 +626,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/system_MCXW727A_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/system_MCXW727A_cm33_core0.h index 9b3e73c33..da5de86cf 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/system_MCXW727A_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/system_MCXW727A_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/system_MCXW727A_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/system_MCXW727A_cm33_core1.h index e3bfa25b5..43d1d4525 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/system_MCXW727A_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727A/system_MCXW727A_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0.h index f81c20381..2d49a8420 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727C_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0_COMMON.h index 510979b4a..dd15ddc21 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727C_cm33_core0 @@ -2414,22 +2414,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2439,6 +2445,55 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(MCXW727A_cm33_core1_H_) || defined(MCXW727C_cm33_core1_H_) || defined(MCXW727D_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0_features.h index 8a455674c..8433b03af 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250522 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -255,6 +255,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -282,6 +286,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -321,8 +330,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -351,6 +358,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -410,8 +419,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -498,8 +519,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -542,6 +561,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -674,18 +697,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -708,6 +745,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1.h index 6201b0b77..1aed740df 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727C_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1_COMMON.h index 08cef4a78..a428a14e5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727C_cm33_core1 @@ -976,22 +976,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -1001,6 +1007,55 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(MCXW727A_cm33_core1_H_) || defined(MCXW727C_cm33_core1_H_) || defined(MCXW727D_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1_features.h index 207fcf119..5ed0d5cc0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/MCXW727C_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250522 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -267,6 +267,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -294,6 +298,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -333,8 +342,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -363,6 +370,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -422,8 +431,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -510,8 +531,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -554,6 +573,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -681,18 +704,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -715,6 +752,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/CMakeLists_clock.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/CMakeLists_clock.txt index 153a43109..67fac9bef 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/CMakeLists_clock.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/CMakeLists_clock.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.2.3) + mcux_component_version(2.2.5) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) mcux_add_include( INCLUDES . ) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/CMakeLists_romapi.txt b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/CMakeLists_romapi.txt index 59474a041..fd1981e26 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/CMakeLists_romapi.txt +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/CMakeLists_romapi.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.romapi_soc) - mcux_component_version(1.2.1) + mcux_component_version(1.2.3) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/fsl_clock.c index 60c72b765..4853fd196 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/fsl_clock.c @@ -739,7 +739,7 @@ status_t CLOCK_InitRfFro192M(const fro192m_rf_clk_config_t *config) */ uint32_t CLOCK_GetRfFro192MFreq(void) { - static const uint32_t fro192mFreq[] = {16000000U, 24000000U, 32000000U, 48000000U, 64000000U}; + static const uint32_t fro192mFreq[] = {16000000U, 24000000U, 32000000U, 48000000U, 64000000U, 0U, 0U, 0U}; /* * $Branch Coverage Justification$ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/fsl_clock.h index 0f7b6e500..38d4e4832 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/fsl_clock.h @@ -39,8 +39,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.2.3. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) +/*! @brief CLOCK driver version 2.2.5. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) /*@}*/ /* Definition for delay API in clock driver, users can redefine it to the real application. */ @@ -369,6 +369,13 @@ typedef enum _scg_sys_clk /*! * @brief SCG system clock source. + * + * ERR052742: FRO6M clock(kSCG_SysClkSrcSirc) is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. */ typedef enum _scg_sys_clk_src { @@ -701,6 +708,12 @@ static inline void CLOCK_DisableTPM2(void) * Set the clock source for specific IP, not all modules need to set the * clock source, should only use this function for the modules need source * setting. + * ERR052742: FRO6M clock is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. * * @param name Which peripheral to check, see \ref clock_ip_name_t. * @param src Clock source to set. diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/romapi/fsl_flash_api.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/romapi/fsl_flash_api.h index f8c0bdce9..46d234824 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/romapi/fsl_flash_api.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/romapi/fsl_flash_api.h @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ * @{ */ /*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 1)) /*!< Version 1.2.1. */ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 3)) /*!< Version 1.2.3. */ /*@}*/ /*! @brief Constructs the four character code for the Flash driver API key. */ @@ -113,21 +113,11 @@ typedef enum _flash_property_tag kFLASH_PropertyPflash0BlockSize = 0x02U, /*!< Pflash block size property.*/ kFLASH_PropertyPflash0BlockCount = 0x03U, /*!< Pflash block count property.*/ kFLASH_PropertyPflash0BlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflash0FacSupport = 0x05U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflash0AccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflash0AccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ - kFLASH_PropertyPflash1SectorSize = 0x10U, /*!< Pflash sector size property.*/ kFLASH_PropertyPflash1TotalSize = 0x11U, /*!< Pflash total size property.*/ kFLASH_PropertyPflash1BlockSize = 0x12U, /*!< Pflash block size property.*/ kFLASH_PropertyPflash1BlockCount = 0x13U, /*!< Pflash block count property.*/ kFLASH_PropertyPflash1BlockBaseAddr = 0x14U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflash1FacSupport = 0x15U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflash1AccessSegmentSize = 0x16U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflash1AccessSegmentCount = 0x17U, /*!< Pflash access segment count property.*/ - - kFLASH_PropertyFlexRamBlockBaseAddr = 0x20U, /*!< FlexRam block base address property.*/ - kFLASH_PropertyFlexRamTotalSize = 0x21U, /*!< FlexRam total size property.*/ } flash_property_tag_t; /*! @@ -190,7 +180,8 @@ typedef struct FlashDriverInterface status_t (*flash_program_page)( flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t *src, uint32_t lengthInBytes); status_t (*flash_verify_erase_all)(FMU_Type *base); - status_t *reserved; + status_t (*flash_verify_erase_block)( + flash_config_t *config, FMU_Type *base, uint32_t blockaddr); status_t (*flash_verify_erase_phrase)(flash_config_t *config, FMU_Type *base, uint32_t start, diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/romapi/fsl_romapi.c b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/romapi/fsl_romapi.c index eafc68eb3..73549439c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/romapi/fsl_romapi.c +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/drivers/romapi/fsl_romapi.c @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -16,7 +16,7 @@ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "driver.romapi" +#define FSL_COMPONENT_ID "driver.romapi_soc" #endif /* @@ -330,6 +330,21 @@ status_t FLASH_VerifyEraseSector(flash_config_t *config, FMU_Type *base, uint32_ return status; } +/*! + * @brief Checking if a flash block is in the erased state. + */ +status_t FLASH_VerifyEraseBlock(flash_config_t *config, FMU_Type *base, uint32_t blockaddr) +{ + assert(BOOTLOADER_API_TREE_POINTER); + assert(config); + assert(base); + + status_t status; + status = BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_erase_block(config, base, blockaddr); + + return status; +} + /*! * @brief Read into MISR * @@ -362,6 +377,7 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro status_t status; status = BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_property(config, whichProperty, value); + status = kStatus_FLASH_Success; return status; } @@ -417,12 +433,12 @@ static status_t flash_check_param( status = kStatus_FLASH_Success; } #if defined(RF_FMU) - else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU))) + else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU)) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } #else - else if ((config == NULL) || (base == NULL) || (base != FMU0)) + else if ((config == NULL) || (base == NULL) || (base != FMU0) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/system_MCXW727C_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/system_MCXW727C_cm33_core0.h index a01068824..071453a19 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/system_MCXW727C_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/system_MCXW727C_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/system_MCXW727C_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/system_MCXW727C_cm33_core1.h index e917b3a13..d38c7851b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/system_MCXW727C_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727C/system_MCXW727C_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0.h index e6678ba1d..7099eb672 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727D_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0_COMMON.h index 913fc95ba..865ebdc11 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727D_cm33_core0 @@ -2366,22 +2366,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2391,6 +2397,55 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(MCXW727A_cm33_core1_H_) || defined(MCXW727C_cm33_core1_H_) || defined(MCXW727D_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0_features.h index b11b655d4..dd12c7a41 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250522 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -209,6 +209,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -248,8 +253,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -278,6 +281,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -337,8 +342,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -425,8 +442,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -469,6 +484,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -601,18 +620,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -635,6 +668,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1.h index 265754a9a..351b1a555 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727D_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1_COMMON.h index e14d7c743..7b936676e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXW727D_cm33_core1 @@ -962,22 +962,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -987,6 +993,55 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(MCXW727A_cm33_core1_H_) || defined(MCXW727C_cm33_core1_H_) || defined(MCXW727D_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1_features.h index 2707e438c..839b55cb3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/MCXW727D_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250522 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -221,6 +221,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -260,8 +265,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -290,6 +293,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -349,8 +354,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -437,8 +454,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -481,6 +496,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -608,18 +627,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -642,6 +675,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/system_MCXW727D_cm33_core0.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/system_MCXW727D_cm33_core0.h index 7918ad0ee..424ad5ddd 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/system_MCXW727D_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/system_MCXW727D_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/system_MCXW727D_cm33_core1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/system_MCXW727D_cm33_core1.h index 37a06a704..82f05b5e7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/system_MCXW727D_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/MCXW727D/system_MCXW727D_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250716 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ADC.h index 831542dfe..80d1f5515 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ADC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC @@ -719,6 +719,14 @@ typedef struct { */ #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + * 0b0..Disable + * 0b1..Enable + */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + #define ADC_TCTRL_TDLY_MASK (0xF0000U) #define ADC_TCTRL_TDLY_SHIFT (16U) /*! TDLY - Trigger Delay Select */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ATX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ATX.h index d7af39162..e67491708 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ATX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ATX.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for ATX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_AXBS.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_AXBS.h index 033e44cef..d470cc635 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_AXBS.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_AXBS.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for AXBS @@ -98,51 +98,51 @@ /** AXBS - Register Layout Typedef */ typedef struct { - __IO uint32_t PRS0; /**< Priority Slave Registers, offset: 0x0 */ + __IO uint32_t PRS0; /**< Priority Target Registers, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t CRS0; /**< Control Register, offset: 0x10 */ uint8_t RESERVED_1[236]; - __IO uint32_t PRS1; /**< Priority Slave Registers, offset: 0x100 */ + __IO uint32_t PRS1; /**< Priority Target Registers, offset: 0x100 */ uint8_t RESERVED_2[12]; __IO uint32_t CRS1; /**< Control Register, offset: 0x110 */ uint8_t RESERVED_3[236]; - __IO uint32_t PRS2; /**< Priority Slave Registers, offset: 0x200 */ + __IO uint32_t PRS2; /**< Priority Target Registers, offset: 0x200 */ uint8_t RESERVED_4[12]; __IO uint32_t CRS2; /**< Control Register, offset: 0x210 */ uint8_t RESERVED_5[236]; - __IO uint32_t PRS3; /**< Priority Slave Registers, offset: 0x300 */ + __IO uint32_t PRS3; /**< Priority Target Registers, offset: 0x300 */ uint8_t RESERVED_6[12]; __IO uint32_t CRS3; /**< Control Register, offset: 0x310 */ uint8_t RESERVED_7[236]; - __IO uint32_t PRS4; /**< Priority Slave Registers, offset: 0x400 */ + __IO uint32_t PRS4; /**< Priority Target Registers, offset: 0x400 */ uint8_t RESERVED_8[12]; __IO uint32_t CRS4; /**< Control Register, offset: 0x410 */ uint8_t RESERVED_9[236]; - __IO uint32_t PRS5; /**< Priority Slave Registers, offset: 0x500 */ + __IO uint32_t PRS5; /**< Priority Target Registers, offset: 0x500 */ uint8_t RESERVED_10[12]; __IO uint32_t CRS5; /**< Control Register, offset: 0x510 */ uint8_t RESERVED_11[236]; - __IO uint32_t PRS6; /**< Priority Slave Registers, offset: 0x600 */ + __IO uint32_t PRS6; /**< Priority Target Registers, offset: 0x600 */ uint8_t RESERVED_12[12]; __IO uint32_t CRS6; /**< Control Register, offset: 0x610 */ uint8_t RESERVED_13[236]; - __IO uint32_t PRS7; /**< Priority Slave Registers, offset: 0x700 */ + __IO uint32_t PRS7; /**< Priority Target Registers, offset: 0x700 */ uint8_t RESERVED_14[12]; __IO uint32_t CRS7; /**< Control Register, offset: 0x710 */ uint8_t RESERVED_15[236]; - __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ + __IO uint32_t MGPCR0; /**< Initiator General Purpose Control Register, offset: 0x800 */ uint8_t RESERVED_16[252]; - __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ + __IO uint32_t MGPCR1; /**< Initiator General Purpose Control Register, offset: 0x900 */ uint8_t RESERVED_17[252]; - __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ + __IO uint32_t MGPCR2; /**< Initiator General Purpose Control Register, offset: 0xA00 */ uint8_t RESERVED_18[252]; - __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ + __IO uint32_t MGPCR3; /**< Initiator General Purpose Control Register, offset: 0xB00 */ uint8_t RESERVED_19[252]; - __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ + __IO uint32_t MGPCR4; /**< Initiator General Purpose Control Register, offset: 0xC00 */ uint8_t RESERVED_20[252]; - __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ + __IO uint32_t MGPCR5; /**< Initiator General Purpose Control Register, offset: 0xD00 */ uint8_t RESERVED_21[252]; - __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */ + __IO uint32_t MGPCR6; /**< Initiator General Purpose Control Register, offset: 0xE00 */ } AXBS_Type; /* ---------------------------------------------------------------------------- @@ -154,104 +154,104 @@ typedef struct { * @{ */ -/*! @name PRS0 - Priority Slave Registers */ +/*! @name PRS0 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS0_M0_MASK (0x7U) #define AXBS_PRS0_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS0_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M0_SHIFT)) & AXBS_PRS0_M0_MASK) #define AXBS_PRS0_M1_MASK (0x70U) #define AXBS_PRS0_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS0_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M1_SHIFT)) & AXBS_PRS0_M1_MASK) #define AXBS_PRS0_M2_MASK (0x700U) #define AXBS_PRS0_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS0_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M2_SHIFT)) & AXBS_PRS0_M2_MASK) #define AXBS_PRS0_M3_MASK (0x7000U) #define AXBS_PRS0_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS0_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M3_SHIFT)) & AXBS_PRS0_M3_MASK) #define AXBS_PRS0_M4_MASK (0x70000U) #define AXBS_PRS0_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS0_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M4_SHIFT)) & AXBS_PRS0_M4_MASK) #define AXBS_PRS0_M5_MASK (0x700000U) #define AXBS_PRS0_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS0_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M5_SHIFT)) & AXBS_PRS0_M5_MASK) #define AXBS_PRS0_M6_MASK (0x7000000U) #define AXBS_PRS0_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS0_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M6_SHIFT)) & AXBS_PRS0_M6_MASK) /*! @} */ @@ -262,23 +262,23 @@ typedef struct { #define AXBS_CRS0_PARK_MASK (0x7U) #define AXBS_CRS0_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS0_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PARK_SHIFT)) & AXBS_CRS0_PARK_MASK) #define AXBS_CRS0_PCTL_MASK (0x30U) #define AXBS_CRS0_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS0_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PCTL_SHIFT)) & AXBS_CRS0_PCTL_MASK) @@ -296,119 +296,119 @@ typedef struct { #define AXBS_CRS0_HLP_MASK (0x40000000U) #define AXBS_CRS0_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS0_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HLP_SHIFT)) & AXBS_CRS0_HLP_MASK) #define AXBS_CRS0_RO_MASK (0x80000000U) #define AXBS_CRS0_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS0_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_RO_SHIFT)) & AXBS_CRS0_RO_MASK) /*! @} */ -/*! @name PRS1 - Priority Slave Registers */ +/*! @name PRS1 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS1_M0_MASK (0x7U) #define AXBS_PRS1_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS1_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M0_SHIFT)) & AXBS_PRS1_M0_MASK) #define AXBS_PRS1_M1_MASK (0x70U) #define AXBS_PRS1_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS1_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M1_SHIFT)) & AXBS_PRS1_M1_MASK) #define AXBS_PRS1_M2_MASK (0x700U) #define AXBS_PRS1_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS1_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M2_SHIFT)) & AXBS_PRS1_M2_MASK) #define AXBS_PRS1_M3_MASK (0x7000U) #define AXBS_PRS1_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS1_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M3_SHIFT)) & AXBS_PRS1_M3_MASK) #define AXBS_PRS1_M4_MASK (0x70000U) #define AXBS_PRS1_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS1_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M4_SHIFT)) & AXBS_PRS1_M4_MASK) #define AXBS_PRS1_M5_MASK (0x700000U) #define AXBS_PRS1_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS1_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M5_SHIFT)) & AXBS_PRS1_M5_MASK) #define AXBS_PRS1_M6_MASK (0x7000000U) #define AXBS_PRS1_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS1_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M6_SHIFT)) & AXBS_PRS1_M6_MASK) /*! @} */ @@ -419,23 +419,23 @@ typedef struct { #define AXBS_CRS1_PARK_MASK (0x7U) #define AXBS_CRS1_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS1_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PARK_SHIFT)) & AXBS_CRS1_PARK_MASK) #define AXBS_CRS1_PCTL_MASK (0x30U) #define AXBS_CRS1_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS1_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PCTL_SHIFT)) & AXBS_CRS1_PCTL_MASK) @@ -453,119 +453,119 @@ typedef struct { #define AXBS_CRS1_HLP_MASK (0x40000000U) #define AXBS_CRS1_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS1_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HLP_SHIFT)) & AXBS_CRS1_HLP_MASK) #define AXBS_CRS1_RO_MASK (0x80000000U) #define AXBS_CRS1_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS1_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_RO_SHIFT)) & AXBS_CRS1_RO_MASK) /*! @} */ -/*! @name PRS2 - Priority Slave Registers */ +/*! @name PRS2 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS2_M0_MASK (0x7U) #define AXBS_PRS2_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS2_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M0_SHIFT)) & AXBS_PRS2_M0_MASK) #define AXBS_PRS2_M1_MASK (0x70U) #define AXBS_PRS2_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS2_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M1_SHIFT)) & AXBS_PRS2_M1_MASK) #define AXBS_PRS2_M2_MASK (0x700U) #define AXBS_PRS2_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS2_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M2_SHIFT)) & AXBS_PRS2_M2_MASK) #define AXBS_PRS2_M3_MASK (0x7000U) #define AXBS_PRS2_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS2_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M3_SHIFT)) & AXBS_PRS2_M3_MASK) #define AXBS_PRS2_M4_MASK (0x70000U) #define AXBS_PRS2_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS2_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M4_SHIFT)) & AXBS_PRS2_M4_MASK) #define AXBS_PRS2_M5_MASK (0x700000U) #define AXBS_PRS2_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS2_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M5_SHIFT)) & AXBS_PRS2_M5_MASK) #define AXBS_PRS2_M6_MASK (0x7000000U) #define AXBS_PRS2_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS2_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M6_SHIFT)) & AXBS_PRS2_M6_MASK) /*! @} */ @@ -576,23 +576,23 @@ typedef struct { #define AXBS_CRS2_PARK_MASK (0x7U) #define AXBS_CRS2_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS2_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PARK_SHIFT)) & AXBS_CRS2_PARK_MASK) #define AXBS_CRS2_PCTL_MASK (0x30U) #define AXBS_CRS2_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS2_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PCTL_SHIFT)) & AXBS_CRS2_PCTL_MASK) @@ -610,119 +610,119 @@ typedef struct { #define AXBS_CRS2_HLP_MASK (0x40000000U) #define AXBS_CRS2_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS2_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HLP_SHIFT)) & AXBS_CRS2_HLP_MASK) #define AXBS_CRS2_RO_MASK (0x80000000U) #define AXBS_CRS2_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS2_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_RO_SHIFT)) & AXBS_CRS2_RO_MASK) /*! @} */ -/*! @name PRS3 - Priority Slave Registers */ +/*! @name PRS3 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS3_M0_MASK (0x7U) #define AXBS_PRS3_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS3_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M0_SHIFT)) & AXBS_PRS3_M0_MASK) #define AXBS_PRS3_M1_MASK (0x70U) #define AXBS_PRS3_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS3_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M1_SHIFT)) & AXBS_PRS3_M1_MASK) #define AXBS_PRS3_M2_MASK (0x700U) #define AXBS_PRS3_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS3_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M2_SHIFT)) & AXBS_PRS3_M2_MASK) #define AXBS_PRS3_M3_MASK (0x7000U) #define AXBS_PRS3_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS3_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M3_SHIFT)) & AXBS_PRS3_M3_MASK) #define AXBS_PRS3_M4_MASK (0x70000U) #define AXBS_PRS3_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS3_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M4_SHIFT)) & AXBS_PRS3_M4_MASK) #define AXBS_PRS3_M5_MASK (0x700000U) #define AXBS_PRS3_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS3_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M5_SHIFT)) & AXBS_PRS3_M5_MASK) #define AXBS_PRS3_M6_MASK (0x7000000U) #define AXBS_PRS3_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS3_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M6_SHIFT)) & AXBS_PRS3_M6_MASK) /*! @} */ @@ -733,23 +733,23 @@ typedef struct { #define AXBS_CRS3_PARK_MASK (0x7U) #define AXBS_CRS3_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS3_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PARK_SHIFT)) & AXBS_CRS3_PARK_MASK) #define AXBS_CRS3_PCTL_MASK (0x30U) #define AXBS_CRS3_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS3_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PCTL_SHIFT)) & AXBS_CRS3_PCTL_MASK) @@ -767,119 +767,119 @@ typedef struct { #define AXBS_CRS3_HLP_MASK (0x40000000U) #define AXBS_CRS3_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS3_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HLP_SHIFT)) & AXBS_CRS3_HLP_MASK) #define AXBS_CRS3_RO_MASK (0x80000000U) #define AXBS_CRS3_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS3_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_RO_SHIFT)) & AXBS_CRS3_RO_MASK) /*! @} */ -/*! @name PRS4 - Priority Slave Registers */ +/*! @name PRS4 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS4_M0_MASK (0x7U) #define AXBS_PRS4_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS4_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M0_SHIFT)) & AXBS_PRS4_M0_MASK) #define AXBS_PRS4_M1_MASK (0x70U) #define AXBS_PRS4_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS4_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M1_SHIFT)) & AXBS_PRS4_M1_MASK) #define AXBS_PRS4_M2_MASK (0x700U) #define AXBS_PRS4_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS4_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M2_SHIFT)) & AXBS_PRS4_M2_MASK) #define AXBS_PRS4_M3_MASK (0x7000U) #define AXBS_PRS4_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS4_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M3_SHIFT)) & AXBS_PRS4_M3_MASK) #define AXBS_PRS4_M4_MASK (0x70000U) #define AXBS_PRS4_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS4_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M4_SHIFT)) & AXBS_PRS4_M4_MASK) #define AXBS_PRS4_M5_MASK (0x700000U) #define AXBS_PRS4_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS4_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M5_SHIFT)) & AXBS_PRS4_M5_MASK) #define AXBS_PRS4_M6_MASK (0x7000000U) #define AXBS_PRS4_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS4_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M6_SHIFT)) & AXBS_PRS4_M6_MASK) /*! @} */ @@ -890,23 +890,23 @@ typedef struct { #define AXBS_CRS4_PARK_MASK (0x7U) #define AXBS_CRS4_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS4_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PARK_SHIFT)) & AXBS_CRS4_PARK_MASK) #define AXBS_CRS4_PCTL_MASK (0x30U) #define AXBS_CRS4_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS4_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PCTL_SHIFT)) & AXBS_CRS4_PCTL_MASK) @@ -924,119 +924,119 @@ typedef struct { #define AXBS_CRS4_HLP_MASK (0x40000000U) #define AXBS_CRS4_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS4_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HLP_SHIFT)) & AXBS_CRS4_HLP_MASK) #define AXBS_CRS4_RO_MASK (0x80000000U) #define AXBS_CRS4_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS4_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_RO_SHIFT)) & AXBS_CRS4_RO_MASK) /*! @} */ -/*! @name PRS5 - Priority Slave Registers */ +/*! @name PRS5 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS5_M0_MASK (0x7U) #define AXBS_PRS5_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS5_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M0_SHIFT)) & AXBS_PRS5_M0_MASK) #define AXBS_PRS5_M1_MASK (0x70U) #define AXBS_PRS5_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS5_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M1_SHIFT)) & AXBS_PRS5_M1_MASK) #define AXBS_PRS5_M2_MASK (0x700U) #define AXBS_PRS5_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS5_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M2_SHIFT)) & AXBS_PRS5_M2_MASK) #define AXBS_PRS5_M3_MASK (0x7000U) #define AXBS_PRS5_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS5_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M3_SHIFT)) & AXBS_PRS5_M3_MASK) #define AXBS_PRS5_M4_MASK (0x70000U) #define AXBS_PRS5_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS5_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M4_SHIFT)) & AXBS_PRS5_M4_MASK) #define AXBS_PRS5_M5_MASK (0x700000U) #define AXBS_PRS5_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS5_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M5_SHIFT)) & AXBS_PRS5_M5_MASK) #define AXBS_PRS5_M6_MASK (0x7000000U) #define AXBS_PRS5_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS5_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M6_SHIFT)) & AXBS_PRS5_M6_MASK) /*! @} */ @@ -1047,23 +1047,23 @@ typedef struct { #define AXBS_CRS5_PARK_MASK (0x7U) #define AXBS_CRS5_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS5_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PARK_SHIFT)) & AXBS_CRS5_PARK_MASK) #define AXBS_CRS5_PCTL_MASK (0x30U) #define AXBS_CRS5_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS5_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PCTL_SHIFT)) & AXBS_CRS5_PCTL_MASK) @@ -1081,119 +1081,119 @@ typedef struct { #define AXBS_CRS5_HLP_MASK (0x40000000U) #define AXBS_CRS5_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS5_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HLP_SHIFT)) & AXBS_CRS5_HLP_MASK) #define AXBS_CRS5_RO_MASK (0x80000000U) #define AXBS_CRS5_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS5_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_RO_SHIFT)) & AXBS_CRS5_RO_MASK) /*! @} */ -/*! @name PRS6 - Priority Slave Registers */ +/*! @name PRS6 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS6_M0_MASK (0x7U) #define AXBS_PRS6_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS6_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M0_SHIFT)) & AXBS_PRS6_M0_MASK) #define AXBS_PRS6_M1_MASK (0x70U) #define AXBS_PRS6_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS6_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M1_SHIFT)) & AXBS_PRS6_M1_MASK) #define AXBS_PRS6_M2_MASK (0x700U) #define AXBS_PRS6_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS6_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M2_SHIFT)) & AXBS_PRS6_M2_MASK) #define AXBS_PRS6_M3_MASK (0x7000U) #define AXBS_PRS6_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS6_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M3_SHIFT)) & AXBS_PRS6_M3_MASK) #define AXBS_PRS6_M4_MASK (0x70000U) #define AXBS_PRS6_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS6_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M4_SHIFT)) & AXBS_PRS6_M4_MASK) #define AXBS_PRS6_M5_MASK (0x700000U) #define AXBS_PRS6_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS6_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M5_SHIFT)) & AXBS_PRS6_M5_MASK) #define AXBS_PRS6_M6_MASK (0x7000000U) #define AXBS_PRS6_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS6_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M6_SHIFT)) & AXBS_PRS6_M6_MASK) /*! @} */ @@ -1204,23 +1204,23 @@ typedef struct { #define AXBS_CRS6_PARK_MASK (0x7U) #define AXBS_CRS6_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS6_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PARK_SHIFT)) & AXBS_CRS6_PARK_MASK) #define AXBS_CRS6_PCTL_MASK (0x30U) #define AXBS_CRS6_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS6_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PCTL_SHIFT)) & AXBS_CRS6_PCTL_MASK) @@ -1238,119 +1238,119 @@ typedef struct { #define AXBS_CRS6_HLP_MASK (0x40000000U) #define AXBS_CRS6_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS6_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HLP_SHIFT)) & AXBS_CRS6_HLP_MASK) #define AXBS_CRS6_RO_MASK (0x80000000U) #define AXBS_CRS6_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS6_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_RO_SHIFT)) & AXBS_CRS6_RO_MASK) /*! @} */ -/*! @name PRS7 - Priority Slave Registers */ +/*! @name PRS7 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS7_M0_MASK (0x7U) #define AXBS_PRS7_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS7_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M0_SHIFT)) & AXBS_PRS7_M0_MASK) #define AXBS_PRS7_M1_MASK (0x70U) #define AXBS_PRS7_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS7_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M1_SHIFT)) & AXBS_PRS7_M1_MASK) #define AXBS_PRS7_M2_MASK (0x700U) #define AXBS_PRS7_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS7_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M2_SHIFT)) & AXBS_PRS7_M2_MASK) #define AXBS_PRS7_M3_MASK (0x7000U) #define AXBS_PRS7_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS7_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M3_SHIFT)) & AXBS_PRS7_M3_MASK) #define AXBS_PRS7_M4_MASK (0x70000U) #define AXBS_PRS7_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS7_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M4_SHIFT)) & AXBS_PRS7_M4_MASK) #define AXBS_PRS7_M5_MASK (0x700000U) #define AXBS_PRS7_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS7_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M5_SHIFT)) & AXBS_PRS7_M5_MASK) #define AXBS_PRS7_M6_MASK (0x7000000U) #define AXBS_PRS7_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS7_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M6_SHIFT)) & AXBS_PRS7_M6_MASK) /*! @} */ @@ -1361,23 +1361,23 @@ typedef struct { #define AXBS_CRS7_PARK_MASK (0x7U) #define AXBS_CRS7_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS7_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PARK_SHIFT)) & AXBS_CRS7_PARK_MASK) #define AXBS_CRS7_PCTL_MASK (0x30U) #define AXBS_CRS7_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS7_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PCTL_SHIFT)) & AXBS_CRS7_PCTL_MASK) @@ -1395,22 +1395,22 @@ typedef struct { #define AXBS_CRS7_HLP_MASK (0x40000000U) #define AXBS_CRS7_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS7_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HLP_SHIFT)) & AXBS_CRS7_HLP_MASK) #define AXBS_CRS7_RO_MASK (0x80000000U) #define AXBS_CRS7_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS7_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_RO_SHIFT)) & AXBS_CRS7_RO_MASK) /*! @} */ -/*! @name MGPCR0 - Master General Purpose Control Register */ +/*! @name MGPCR0 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR0_AULB_MASK (0x7U) @@ -1428,7 +1428,7 @@ typedef struct { #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) /*! @} */ -/*! @name MGPCR1 - Master General Purpose Control Register */ +/*! @name MGPCR1 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR1_AULB_MASK (0x7U) @@ -1446,7 +1446,7 @@ typedef struct { #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) /*! @} */ -/*! @name MGPCR2 - Master General Purpose Control Register */ +/*! @name MGPCR2 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR2_AULB_MASK (0x7U) @@ -1464,7 +1464,7 @@ typedef struct { #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) /*! @} */ -/*! @name MGPCR3 - Master General Purpose Control Register */ +/*! @name MGPCR3 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR3_AULB_MASK (0x7U) @@ -1482,7 +1482,7 @@ typedef struct { #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) /*! @} */ -/*! @name MGPCR4 - Master General Purpose Control Register */ +/*! @name MGPCR4 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR4_AULB_MASK (0x7U) @@ -1500,7 +1500,7 @@ typedef struct { #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) /*! @} */ -/*! @name MGPCR5 - Master General Purpose Control Register */ +/*! @name MGPCR5 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR5_AULB_MASK (0x7U) @@ -1518,7 +1518,7 @@ typedef struct { #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) /*! @} */ -/*! @name MGPCR6 - Master General Purpose Control Register */ +/*! @name MGPCR6 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR6_AULB_MASK (0x7U) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BLE2_REG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BLE2_REG.h index e87121857..5c6b19803 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BLE2_REG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BLE2_REG.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLE2_REG diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BRIC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BRIC.h index bcdecef67..c3ceafdc3 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BRIC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BRIC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for BRIC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BTRTU1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BTRTU1.h index 6b372bdb8..3ce176839 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BTRTU1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BTRTU1.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for BTRTU1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BTU2_REG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BTU2_REG.h index 9abe34458..533ab6e5c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BTU2_REG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_BTU2_REG.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for BTU2_REG diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CAN.h index 785724475..4f61fedf0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CAN.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN @@ -316,7 +316,7 @@ typedef struct { #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) -/*! SLFWAK - Self Wake-up +/*! SLFWAK - Self-Wake-Up Feature * 0b0..Disable * 0b1..Enable */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CCM32K.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CCM32K.h index 2eaebbdad..649e43f29 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CCM32K.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CCM32K.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCM32K @@ -106,6 +106,8 @@ typedef struct { __IO uint32_t CLKMON_CTRL; /**< Clock Monitor Control Register, offset: 0x14 */ __IO uint32_t CLKMON_TST; /**< Clock Monitor Test Register, offset: 0x18 */ __IO uint32_t CGC32K; /**< 32 kHz Clock Gate Control Register, offset: 0x1C */ + uint8_t RESERVED_1[4]; + __IO uint32_t OSC32K_MON_TRIM; /**< 32 kHz OSC Internal Monitor Trim Register, offset: 0x24 */ } CCM32K_Type; /* ---------------------------------------------------------------------------- @@ -183,6 +185,14 @@ typedef struct { */ #define CCM32K_OSC32K_CTRL_OSC_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_OSC_BYP_EN_SHIFT)) & CCM32K_OSC32K_CTRL_OSC_BYP_EN_MASK) +#define CCM32K_OSC32K_CTRL_OSC_CLKMON_EN_MASK (0x4U) +#define CCM32K_OSC32K_CTRL_OSC_CLKMON_EN_SHIFT (2U) +/*! OSC_CLKMON_EN - Crystal Oscillator Internal Clock Monitor Enable + * 0b0..Oscillator internal clock monitor is disabled + * 0b1..Oscillator internal clock monitor is enabled + */ +#define CCM32K_OSC32K_CTRL_OSC_CLKMON_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_OSC_CLKMON_EN_SHIFT)) & CCM32K_OSC32K_CTRL_OSC_CLKMON_EN_MASK) + #define CCM32K_OSC32K_CTRL_CAP_TRIM_MASK (0x60U) #define CCM32K_OSC32K_CTRL_CAP_TRIM_SHIFT (5U) /*! CAP_TRIM - SOX Capacitor Trim */ @@ -245,6 +255,14 @@ typedef struct { /*! CMP_TRIM - SOX Comparator trim */ #define CCM32K_OSC32K_CTRL_CMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_CMP_TRIM_SHIFT)) & CCM32K_OSC32K_CTRL_CMP_TRIM_MASK) +#define CCM32K_OSC32K_CTRL_OSC_HP_EN_MASK (0x80000U) +#define CCM32K_OSC32K_CTRL_OSC_HP_EN_SHIFT (19U) +/*! OSC_HP_EN - Crystal Oscillator High Power Enable + * 0b0..Oscillator internal clock monitor is disabled + * 0b1..Oscillator internal clock monitor is enabled + */ +#define CCM32K_OSC32K_CTRL_OSC_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_OSC_HP_EN_SHIFT)) & CCM32K_OSC32K_CTRL_OSC_HP_EN_MASK) + #define CCM32K_OSC32K_CTRL_COARSE_AMP_GAIN_MASK (0x300000U) #define CCM32K_OSC32K_CTRL_COARSE_AMP_GAIN_SHIFT (20U) /*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external crystal ESR values. @@ -316,6 +334,14 @@ typedef struct { * 0b1..Clock error is detected */ #define CCM32K_STATUS_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_STATUS_CLOCK_DET_SHIFT)) & CCM32K_STATUS_CLOCK_DET_MASK) + +#define CCM32K_STATUS_AUTO_SWITCH_MASK (0x100U) +#define CCM32K_STATUS_AUTO_SWITCH_SHIFT (8U) +/*! AUTO_SWITCH - Clock Source Auto switch + * 0b0..Clock source do not switch + * 0b1..Clock source switch back to FRO + */ +#define CCM32K_STATUS_AUTO_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_STATUS_AUTO_SWITCH_SHIFT)) & CCM32K_STATUS_AUTO_SWITCH_MASK) /*! @} */ /*! @name CLKMON_CTRL - Clock Monitor Control Register */ @@ -349,6 +375,14 @@ typedef struct { */ #define CCM32K_CLKMON_CTRL_DIVIDE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_CLKMON_CTRL_DIVIDE_TRIM_SHIFT)) & CCM32K_CLKMON_CTRL_DIVIDE_TRIM_MASK) +#define CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN_MASK (0x100U) +#define CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN_SHIFT (8U) +/*! AUTO_SWITCH_EN - Automatic Switch Enable Bit + * 0b0..Automatic switch is disable + * 0b1..Automatic switch is enable + */ +#define CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN_SHIFT)) & CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN_MASK) + #define CCM32K_CLKMON_CTRL_LOCK_EN_MASK (0x80000000U) #define CCM32K_CLKMON_CTRL_LOCK_EN_SHIFT (31U) /*! LOCK_EN - Write Access Lock bit @@ -403,6 +437,40 @@ typedef struct { #define CCM32K_CGC32K_LOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_CGC32K_LOCK_EN_SHIFT)) & CCM32K_CGC32K_LOCK_EN_MASK) /*! @} */ +/*! @name OSC32K_MON_TRIM - 32 kHz OSC Internal Monitor Trim Register */ +/*! @{ */ + +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH_MASK (0x1FU) +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH_SHIFT (0U) +/*! CAP_TRIM_HIGH - OSC32K Internal Monitor Capacitance Trim for Clock High Level + * 0b11111..Default trim value + */ +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH_SHIFT)) & CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH_MASK) + +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW_MASK (0x1F00U) +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW_SHIFT (8U) +/*! CAP_TRIM_LOW - OSC32K Internal Monitor Capacitance Trim for Clock Low Level + * 0b11111..Default trim value + */ +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW_SHIFT)) & CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW_MASK) + +#define CCM32K_OSC32K_MON_TRIM_IFR_DIS_MASK (0x20000000U) +#define CCM32K_OSC32K_MON_TRIM_IFR_DIS_SHIFT (29U) +/*! IFR_DIS - IFR Loading Disable Control + * 0b0..IFR loading is enabled + * 0b1..IFR loading is disabled + */ +#define CCM32K_OSC32K_MON_TRIM_IFR_DIS(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_MON_TRIM_IFR_DIS_SHIFT)) & CCM32K_OSC32K_MON_TRIM_IFR_DIS_MASK) + +#define CCM32K_OSC32K_MON_TRIM_LOCK_EN_MASK (0x80000000U) +#define CCM32K_OSC32K_MON_TRIM_LOCK_EN_SHIFT (31U) +/*! LOCK_EN - Write Access Lock + * 0b0..Register write access is unlocked + * 0b1..Register write access is locked + */ +#define CCM32K_OSC32K_MON_TRIM_LOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_MON_TRIM_LOCK_EN_SHIFT)) & CCM32K_OSC32K_MON_TRIM_LOCK_EN_MASK) +/*! @} */ + /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CIU2.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CIU2.h index d83f8f6f1..4ef7eb5ed 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CIU2.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CIU2.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CIU2 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CMC.h index 08f2aa43d..25da85258 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CMC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CRC.h index 1e7fd277f..2e27c536a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_CRC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DBGMB.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DBGMB.h index 03bdb8c9e..2cde953fb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DBGMB.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DBGMB.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for DBGMB diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DMA.h index 40c8b333a..929356f9d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DMA.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -292,9 +292,9 @@ typedef struct { #define DMA_MP_CSR_GMRC_MASK (0x80U) #define DMA_MP_CSR_GMRC_SHIFT (7U) -/*! GMRC - Global Master ID Replication Control - * 0b0..Master ID replication disabled for all channels - * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting +/*! GMRC - Global Initiator ID Replication Control + * 0b0..Initiator ID replication disabled for all channels + * 0b1..Initiator ID replication available and controlled by each channel's CHn_SBR[EMI] setting */ #define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) @@ -595,7 +595,7 @@ typedef struct { #define DMA_CH_SBR_MID_MASK (0x3FU) #define DMA_CH_SBR_MID_SHIFT (0U) -/*! MID - Master ID */ +/*! MID - Initiator ID */ #define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) #define DMA_CH_SBR_SEC_MASK (0x4000U) @@ -616,9 +616,9 @@ typedef struct { #define DMA_CH_SBR_EMI_MASK (0x10000U) #define DMA_CH_SBR_EMI_SHIFT (16U) -/*! EMI - Enable Master ID Replication - * 0b0..Master ID replication is disabled - * 0b1..Master ID replication is enabled +/*! EMI - Enable Initiator ID Replication + * 0b0..Initiator ID replication is disabled + * 0b1..Initiator ID replication is enabled */ #define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) @@ -726,7 +726,6 @@ typedef struct { #define DMA_TCD_ATTR_SMOD_SHIFT (11U) /*! SMOD - Source Address Modulo * 0b00000..Source address modulo feature disabled - * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] */ #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DSB.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DSB.h index 6bde76295..c71ee88ac 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DSB.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_DSB.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for DSB @@ -157,6 +157,14 @@ typedef struct { * 0b1..Error interrupt requests enabled */ #define DSB_CSR_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DSB_CSR_ERR_EN_SHIFT)) & DSB_CSR_ERR_EN_MASK) + +#define DSB_CSR_CBT_EN_MASK (0x20U) +#define DSB_CSR_CBT_EN_SHIFT (5U) +/*! CBT_EN - Continuous Burst Transfer Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define DSB_CSR_CBT_EN(x) (((uint32_t)(((uint32_t)(x)) << DSB_CSR_CBT_EN_SHIFT)) & DSB_CSR_CBT_EN_MASK) /*! @} */ /*! @name INT - Interrupt Request Status */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ELEMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ELEMU.h index 217a90cc2..4aa12fd89 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ELEMU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ELEMU.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for ELEMU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_EWM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_EWM.h index 7ecbc392c..f534b033f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_EWM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_EWM.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for EWM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FLEXIO.h index 21a2f985a..a828ff5ef 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FLEXIO.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FMU.h index 9a2ba8e51..7d5efab95 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FMU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FMU.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FRO192M.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FRO192M.h index a5291e504..1cb0a3035 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FRO192M.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_FRO192M.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for FRO192M diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GEN4PHY.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GEN4PHY.h index 448e403fd..d0f4011e2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GEN4PHY.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GEN4PHY.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for GEN4PHY diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GENFSK.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GENFSK.h index 465af07c0..564944484 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GENFSK.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GENFSK.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for GENFSK diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GPIO.h index 610be6f3f..544bd7aea 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_GPIO.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_I3C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_I3C.h index cb69167aa..f3cc08018 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_I3C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_I3C.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for I3C @@ -201,7 +201,7 @@ typedef struct { #define I3C_MCONFIG_DISTO_SHIFT (3U) /*! DISTO - Disable Timeout * 0b0..Enabled - * 0b1..Disabled, if configured + * 0b1..Disabled */ #define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPCMP.h index 3d0b826b6..8ec1cf0e0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPCMP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPCMP.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPCMP diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPI2C.h index 0351f20a1..e33137161 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPI2C.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -1192,16 +1192,16 @@ typedef struct { #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) /*! TXCFG - Transmit Flag Configuration - * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty - * 0b1..MSR[TDF] is set whenever STDR is empty + * 0b0..SSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..SSR[TDF] is set whenever STDR is empty */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration - * 0b0..Return received data, clear MSR[RDF] - * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set + * 0b0..Return received data, clear SSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear SSR[RDF] when SSR[AFV] is not set */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPIT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPIT.h index 779251723..427afe659 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPIT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPIT.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPIT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPSPI.h index 5587f0c1e..b8ada51f6 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPSPI.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPTMR.h index 2d0bf0388..ebefa80b4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPTMR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPTMR.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPTMR diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPUART.h index 08ede7c40..9b2e18f0e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LPUART.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LTC.h index d9cab2105..c0f59e0b5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_LTC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LTC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MCM.h index a3296a077..1d846f88b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MCM.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCM @@ -330,7 +330,7 @@ typedef struct { #define MCM_FATR_BEMN_MASK (0xF00U) #define MCM_FATR_BEMN_SHIFT (8U) -/*! BEMN - Bus Error Master Number */ +/*! BEMN - Bus Error Initiator Number */ #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) #define MCM_FATR_BEOVR_MASK (0x80000000U) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MRCC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MRCC.h index a26140fbf..5e3559665 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MRCC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MRCC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MRCC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MSCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MSCM.h index b4dfeeff6..f02120c08 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MSCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MSCM.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MSCM @@ -1083,19 +1083,21 @@ typedef struct { #define MSCM_SID_PINID_MASK (0x70U) #define MSCM_SID_PINID_SHIFT (4U) /*! PINID - Pin Identification - * 0b010..40HVQFN + * 0b010..Reserved * 0b011..48HVQFN - * 0b100..56HVQFN + * 0b100..Reserved + * 0b101..Reserved + * 0b110..Reserved */ #define MSCM_SID_PINID(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_PINID_SHIFT)) & MSCM_SID_PINID_MASK) -#define MSCM_SID_CMP_MASK (0x80U) -#define MSCM_SID_CMP_SHIFT (7U) -/*! CMP - CMP Presence - * 0b0..No CMP - * 0b1..CMP present +#define MSCM_SID_LCE_MASK (0x80U) +#define MSCM_SID_LCE_SHIFT (7U) +/*! LCE - LCE Presence + * 0b0..No LCE + * 0b1..LCE present */ -#define MSCM_SID_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_CMP_SHIFT)) & MSCM_SID_CMP_MASK) +#define MSCM_SID_LCE(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_LCE_SHIFT)) & MSCM_SID_LCE_MASK) #define MSCM_SID_FLXIO_MASK (0x100U) #define MSCM_SID_FLXIO_SHIFT (8U) @@ -1140,16 +1142,19 @@ typedef struct { #define MSCM_SID_RAMSZ_MASK (0xE000U) #define MSCM_SID_RAMSZ_SHIFT (13U) /*! RAMSZ - RAM Size - * 0b000..96 KB - * 0b111..128 KB + * 0b101..136 KB + 171 KB + * 0b110..Reserved + * 0b111..264 KB + 171 KB */ #define MSCM_SID_RAMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_RAMSZ_SHIFT)) & MSCM_SID_RAMSZ_MASK) #define MSCM_SID_FLSZ_MASK (0xF0000U) #define MSCM_SID_FLSZ_SHIFT (16U) /*! FLSZ - Flash Size - * 0b1101..1 MB - * 0b1111..512 KB + * 0b1011..Reserved + * 0b1101..1 MB + 512 KB + * 0b1110..Reserved + * 0b1111..2 MB + 512 KB */ #define MSCM_SID_FLSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_FLSZ_SHIFT)) & MSCM_SID_FLSZ_MASK) @@ -1157,9 +1162,11 @@ typedef struct { #define MSCM_SID_BLEF_SHIFT (20U) /*! BLEF - Bluetooth LE Feature * 0b0000..No Bluetooth LE present - * 0b0001..Bluetooth LE 5.1 - * 0b0010..Bluetooth LE 5.2 - * 0b0011..Bluetooth LE 5.3 + * 0b0001..Reserved + * 0b0010..Reserved + * 0b0011..Reserved + * 0b0100..Reserved + * 0b1000..Reserved * 0b1111..Bluetooth LE Upgrade */ #define MSCM_SID_BLEF(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_BLEF_SHIFT)) & MSCM_SID_BLEF_MASK) @@ -1167,8 +1174,8 @@ typedef struct { #define MSCM_SID_RADIOF_MASK (0xF000000U) #define MSCM_SID_RADIOF_SHIFT (24U) /*! RADIOF - Radio Feature - * 0b0000..802.15.4 - * 0b0001..Bluetooth LE + * 0b0000..Reserved + * 0b0001..Reserved * 0b0010..Bluetooth LE + 802.15.4 */ #define MSCM_SID_RADIOF(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_RADIOF_SHIFT)) & MSCM_SID_RADIOF_MASK) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MSF1_B_TEST.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MSF1_B_TEST.h index 65d0002e6..4a6476f24 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MSF1_B_TEST.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MSF1_B_TEST.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MSF1_B_test diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MU.h index f22788451..6ad24b45a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_MU.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_NPX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_NPX.h index fe37be3b7..c03651a7a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_NPX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_NPX.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for NPX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_PORT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_PORT.h index 0557e643a..d35f9f7f0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_PORT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_PORT.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for PORT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RADIO_CTRL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RADIO_CTRL.h index 1cfd923e2..643d2bcf8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RADIO_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RADIO_CTRL.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RADIO_CTRL diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RBME.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RBME.h index d3ea32cad..de941c486 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RBME.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RBME.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RBME diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_REGFILE.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_REGFILE.h index 50ac1b913..399948c3b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_REGFILE.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_REGFILE.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for REGFILE diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RFMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RFMC.h index f9549aa85..529a51218 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RFMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RFMC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RFMC @@ -118,6 +118,7 @@ typedef struct { __IO uint32_t RF2P4GHZ_HOST2RADIO; /**< RF 2.4GHz Buffer from Host to Radio, offset: 0x48 */ __I uint32_t RF2P4GHZ_RADIO2HOST; /**< RF 2.4GHz Buffer from Radio to Host, offset: 0x4C */ __IO uint32_t RF2P4GHZ_CFG; /**< 2.4GHz Radio Configuration Register, offset: 0x50 */ + __I uint32_t RF2P4GHZ_WKUP_SRC; /**< 2.4GHz Radio WakeUp Source Register, offset: 0x54 */ } RFMC_Type; /* ---------------------------------------------------------------------------- @@ -365,8 +366,8 @@ typedef struct { #define RFMC_XO_TEST_CDAC_MASK (0x3F0U) #define RFMC_XO_TEST_CDAC_SHIFT (4U) /*! CDAC - XO On-chip Load Capacitor Trim - * 0b000000..6pF - * 0b111111..11pF + * 0b000000..C_FIX + * 0b111111..C_FIX + 14.36pF */ #define RFMC_XO_TEST_CDAC(x) (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_CDAC_SHIFT)) & RFMC_XO_TEST_CDAC_MASK) @@ -420,7 +421,12 @@ typedef struct { #define RFMC_XO_TEST_XO_CDAC_TRIM_MASK (0x600000U) #define RFMC_XO_TEST_XO_CDAC_TRIM_SHIFT (21U) -/*! XO_CDAC_TRIM - reg_xo_cdac_trim[1:0] */ +/*! XO_CDAC_TRIM - XO fixed cap bank C_FIX trimming + * 0b00..5.19pF + * 0b01..3.81pF + * 0b10..2.44pF + * 0b11..1.98pF + */ #define RFMC_XO_TEST_XO_CDAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_XO_CDAC_TRIM_SHIFT)) & RFMC_XO_TEST_XO_CDAC_TRIM_MASK) /*! @} */ @@ -941,6 +947,40 @@ typedef struct { #define RFMC_RF2P4GHZ_CFG_FORCE_DBG_PWRUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CFG_FORCE_DBG_PWRUP_ACK_SHIFT)) & RFMC_RF2P4GHZ_CFG_FORCE_DBG_PWRUP_ACK_MASK) /*! @} */ +/*! @name RF2P4GHZ_WKUP_SRC - 2.4GHz Radio WakeUp Source Register */ +/*! @{ */ + +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS_MASK (0x1U) +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS_SHIFT (0U) +/*! RFMC_RADIO_DEBUG_REQ_STATUS - Radio debug request status */ +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS_MASK (0x6U) +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS_SHIFT (1U) +/*! RFMC_EXT_WAKEUP_STATUS - Radio wakeup by external source status */ +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS_MASK (0x8U) +#define RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS_SHIFT (3U) +/*! BLE_WKUP_STATUS - RFMC BLE Wakeup status (Host Controlled) */ +#define RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS_MASK (0x10U) +#define RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS_SHIFT (4U) +/*! MAN_WKUP_STATUS - RFMC MAN Wakeup status (Host Controlled) */ +#define RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS_MASK (0x20U) +#define RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS_SHIFT (5U) +/*! WOR_WKUP_STATUS - RFMC WOR Wakeup status (Host Controlled) */ +#define RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS_MASK (0x40U) +#define RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS_SHIFT (6U) +/*! RF_CMC_BLE_WKUP_STATUS - RF_CMC BLE Wakeup status */ +#define RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS_MASK) +/*! @} */ + /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RF_CMC1.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RF_CMC1.h index f91cc2048..bc345aa21 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RF_CMC1.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RF_CMC1.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RF_CMC1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RF_FMCCFG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RF_FMCCFG.h index 49b8d6c92..85a29da4c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RF_FMCCFG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RF_FMCCFG.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RF_FMCCFG diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RTC.h index fb5542ed9..d169a8c77 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RTC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -195,7 +195,7 @@ typedef struct { #define RTC_CR_SWR_SHIFT (0U) /*! SWR - Software Reset * 0b0..No effect. - * 0b1..Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. + * 0b1..Resets all RTC registers except for this bit . This bit is cleared by POR and by software explicitly clearing it. */ #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) @@ -235,7 +235,7 @@ typedef struct { #define RTC_CR_CPE_SHIFT (24U) /*! CPE - Clock Pin Enable * 0b000..Disables - * 0b001..Enables on RTC_TAMPER[1] + * 0b001..Enables RTC_CLKOUT function on RTC_TAMPER[1]. * 0b010..Enables RTC_CLKOUT function on RTC_TAMPER[2]. * 0b011..Enables RTC_CLKOUT function on RTC_TAMPER[3]. * 0b100..Enables RTC_CLKOUT function on RTC_TAMPER[4]. @@ -383,7 +383,10 @@ typedef struct { #define RTC_LR_PCL_MASK (0xFF0000U) #define RTC_LR_PCL_SHIFT (16U) -/*! PCL - Pin Configuration Lock */ +/*! PCL - Pin Configuration Lock + * 0b00000000..Pin Configuration Register is locked and writes are ignored. + * 0b00000001..Pin Configuration Register is not locked and writes complete as normal. + */ #define RTC_LR_PCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_PCL_SHIFT)) & RTC_LR_PCL_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RX_PACKET_RAM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RX_PACKET_RAM.h index 7483f8188..26cd91e13 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RX_PACKET_RAM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_RX_PACKET_RAM.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RX_PACKET_RAM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SCG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SCG.h index 844ed3fd5..1e1be64a8 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SCG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SCG.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SCG diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SEMA42.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SEMA42.h index 1e5e91d7c..db121e94f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SEMA42.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SEMA42.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMA42 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SFA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SFA.h index 5c804fded..bb4b668ee 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SFA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SFA.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SFA diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SMSCM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SMSCM.h index accb08abc..d02e8c265 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SMSCM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SMSCM.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SMSCM @@ -769,14 +769,6 @@ typedef struct { * 0b1..AXBS0 in round robin arbitration mode at reset. */ #define SMSCM_CPCR_AXBS0_RREN(x) (((uint32_t)(((uint32_t)(x)) << SMSCM_CPCR_AXBS0_RREN_SHIFT)) & SMSCM_CPCR_AXBS0_RREN_MASK) - -#define SMSCM_CPCR_AXBS1_RREN_MASK (0x2U) -#define SMSCM_CPCR_AXBS1_RREN_SHIFT (1U) -/*! AXBS1_RREN - AXBS1 Round Robin Enable - * 0b0..AXBS1 in fixed priority arbitration mode at reset. - * 0b1..AXBS1 in round robin arbitration mode at reset. - */ -#define SMSCM_CPCR_AXBS1_RREN(x) (((uint32_t)(((uint32_t)(x)) << SMSCM_CPCR_AXBS1_RREN_SHIFT)) & SMSCM_CPCR_AXBS1_RREN_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SPC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SPC.h index 248de83f0..36187825c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SPC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SPC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPC @@ -439,8 +439,7 @@ typedef struct { #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU) #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U) /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level - * 0b00.. - * 0b00..Regulate to under voltage (0.95 V) + * 0b00..Regulate to boost voltage (0.95 V) * 0b01..Regulate to mid voltage (1.0 V) * 0b10..Regulate to normal voltage (1.1 V) * 0b11..Regulate to safe-mode voltage (1.15 V) @@ -474,10 +473,10 @@ typedef struct { #define SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level - * 0b00..Low undervoltage (1.25 V) - * 0b01..Midvoltage (1.35 V) - * 0b10..Normal voltage (1.5 V) - * 0b11..Safe-mode voltage (1.8 V) + * 0b00..Low undervoltage voltage (0.95 V) + * 0b01..Mid voltage (1 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.8 V) */ #define SPC_ACTIVE_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) @@ -598,10 +597,10 @@ typedef struct { #define SPC_LP_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level - * 0b00..Low under voltage (1.25 V) - * 0b01..Mid voltage (1.35 V) - * 0b10.. - * 0b11..Safe-mode voltage (1.8 V) + * 0b00..Low undervoltage (0.95 V) + * 0b01..Mid voltage (1 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.8 V) */ #define SPC_LP_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_LP_CFG_DCDC_VDD_LVL_MASK) @@ -744,10 +743,10 @@ typedef struct { #define SPC_HP_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_HP_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level - * 0b00..Low undervoltage (1.25 V) - * 0b01..Midvoltage (1.35 V) - * 0b10..Normal voltage (1.5 V) - * 0b11..Safe-mode voltage (1.8 V) + * 0b00..Low undervoltage (0.95 V) + * 0b01..Mid voltage (1 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.8 V) */ #define SPC_HP_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_HP_CFG_DCDC_VDD_LVL_MASK) @@ -987,6 +986,14 @@ typedef struct { */ #define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) +#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - System Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) + #define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) #define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) /*! LOCK - System Voltage Detect Reset Enable Lock diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SYSPM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SYSPM.h index 8bdc94c21..df06dafac 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SYSPM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_SYSPM.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSPM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TPM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TPM.h index 24ddecdb2..1f7b86d4f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TPM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TPM.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TPM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TRDC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TRDC.h index 895d6d35c..b4acc62e5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TRDC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TRDC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC @@ -268,10 +268,10 @@ typedef struct { __IO uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */ } MRC_DERR[TRDC_MRC_DERR_COUNT]; uint8_t RESERVED_8[880]; - __IO uint32_t MDA_W0_0_DFMT0; /**< DAC Master Domain Assignment Register, offset: 0x800 */ + __IO uint32_t MDA_W0_0_DFMT0; /**< DAC Initiator Domain Assignment Register, offset: 0x800 */ uint8_t RESERVED_9[28]; struct { /* offset: 0x820, array step: 0x20 */ - __IO uint32_t MDA_W0_x_DFMT1; /**< DAC Master Domain Assignment Register, array offset: 0x820, array step: 0x20 */ + __IO uint32_t MDA_W0_x_DFMT1; /**< DAC Initiator Domain Assignment Register, array offset: 0x820, array step: 0x20 */ uint8_t RESERVED_0[28]; } MDA_W0_DFMT1[TRDC_MDA_W0_DFMT1_COUNT]; uint8_t RESERVED_10[1888]; @@ -413,7 +413,7 @@ typedef struct { #define TRDC_TRDC_HWCFG0_NMSTR_MASK (0xFF00U) #define TRDC_TRDC_HWCFG0_NMSTR_SHIFT (8U) -/*! NMSTR - Number of bus masters */ +/*! NMSTR - Number of bus initiators */ #define TRDC_TRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_TRDC_HWCFG0_NMSTR_MASK) #define TRDC_TRDC_HWCFG0_NMBC_MASK (0x70000U) @@ -446,14 +446,14 @@ typedef struct { #define TRDC_DACFG_NMDAR_MASK (0xFU) #define TRDC_DACFG_NMDAR_SHIFT (0U) -/*! NMDAR - Number of master domain assignment registers for bus master m */ +/*! NMDAR - Number of initiator domain assignment registers for bus initiator m */ #define TRDC_DACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NMDAR_SHIFT)) & TRDC_DACFG_NMDAR_MASK) #define TRDC_DACFG_NCM_MASK (0x80U) #define TRDC_DACFG_NCM_SHIFT (7U) -/*! NCM - Non-CPU Master - * 0b0..Bus master is a processor. - * 0b1..Bus master is a non-processor. +/*! NCM - Non-CPU Initiator + * 0b0..Bus initiator is a processor. + * 0b1..Bus initiator is a non-processor. */ #define TRDC_DACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NCM_SHIFT)) & TRDC_DACFG_NCM_MASK) /*! @} */ @@ -463,42 +463,42 @@ typedef struct { #define TRDC_CFG_SLV0_NMBLK_MASK (0x3FFU) #define TRDC_CFG_SLV0_NMBLK_SHIFT (0U) -/*! SLV0_NMBLK - Number of blocks in slave 0. */ +/*! SLV0_NMBLK - Number of blocks in target 0. */ #define TRDC_CFG_SLV0_NMBLK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV0_NMBLK_SHIFT)) & TRDC_CFG_SLV0_NMBLK_MASK) #define TRDC_CFG_SLV2_NMBLK_MASK (0x3FFU) #define TRDC_CFG_SLV2_NMBLK_SHIFT (0U) -/*! SLV2_NMBLK - Number of blocks in slave 2. */ +/*! SLV2_NMBLK - Number of blocks in target 2. */ #define TRDC_CFG_SLV2_NMBLK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV2_NMBLK_SHIFT)) & TRDC_CFG_SLV2_NMBLK_MASK) #define TRDC_CFG_SLV0_BLKSZL2_MASK (0x7C00U) #define TRDC_CFG_SLV0_BLKSZL2_SHIFT (10U) -/*! SLV0_BLKSZL2 - Block size log2 in slave 0. */ +/*! SLV0_BLKSZL2 - Block size log2 in target 0. */ #define TRDC_CFG_SLV0_BLKSZL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV0_BLKSZL2_SHIFT)) & TRDC_CFG_SLV0_BLKSZL2_MASK) #define TRDC_CFG_SLV2_BLKSZL2_MASK (0x7C00U) #define TRDC_CFG_SLV2_BLKSZL2_SHIFT (10U) -/*! SLV2_BLKSZL2 - Block size log2 in slave 2. */ +/*! SLV2_BLKSZL2 - Block size log2 in target 2. */ #define TRDC_CFG_SLV2_BLKSZL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV2_BLKSZL2_SHIFT)) & TRDC_CFG_SLV2_BLKSZL2_MASK) #define TRDC_CFG_SLV1_NMBLK_MASK (0x3FF0000U) #define TRDC_CFG_SLV1_NMBLK_SHIFT (16U) -/*! SLV1_NMBLK - Number of blocks in slave 1. */ +/*! SLV1_NMBLK - Number of blocks in target 1. */ #define TRDC_CFG_SLV1_NMBLK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV1_NMBLK_SHIFT)) & TRDC_CFG_SLV1_NMBLK_MASK) #define TRDC_CFG_SLV3_NMBLK_MASK (0x3FF0000U) #define TRDC_CFG_SLV3_NMBLK_SHIFT (16U) -/*! SLV3_NMBLK - Number of blocks in slave 3. */ +/*! SLV3_NMBLK - Number of blocks in target 3. */ #define TRDC_CFG_SLV3_NMBLK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV3_NMBLK_SHIFT)) & TRDC_CFG_SLV3_NMBLK_MASK) #define TRDC_CFG_SLV1_BLKSZL2_MASK (0x7C000000U) #define TRDC_CFG_SLV1_BLKSZL2_SHIFT (26U) -/*! SLV1_BLKSZL2 - Block size log2 in slave 1. */ +/*! SLV1_BLKSZL2 - Block size log2 in target 1. */ #define TRDC_CFG_SLV1_BLKSZL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV1_BLKSZL2_SHIFT)) & TRDC_CFG_SLV1_BLKSZL2_MASK) #define TRDC_CFG_SLV3_BLKSZL2_MASK (0x7C000000U) #define TRDC_CFG_SLV3_BLKSZL2_SHIFT (26U) -/*! SLV3_BLKSZL2 - Block size log2 in slave 3. */ +/*! SLV3_BLKSZL2 - Block size log2 in target 3. */ #define TRDC_CFG_SLV3_BLKSZL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV3_BLKSZL2_SHIFT)) & TRDC_CFG_SLV3_BLKSZL2_MASK) /*! @} */ @@ -724,6 +724,26 @@ typedef struct { /*! EDID - Error domain identifier */ #define TRDC_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK) +#define TRDC_W1_SLV_DID_ERR_MASK (0x10U) +#define TRDC_W1_SLV_DID_ERR_SHIFT (4U) +/*! SLV_DID_ERR - DID check error */ +#define TRDC_W1_SLV_DID_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_DID_ERR_SHIFT)) & TRDC_W1_SLV_DID_ERR_MASK) + +#define TRDC_W1_SLV_PA_ERR_MASK (0x20U) +#define TRDC_W1_SLV_PA_ERR_SHIFT (5U) +/*! SLV_PA_ERR - Privilege attribute check error */ +#define TRDC_W1_SLV_PA_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_PA_ERR_SHIFT)) & TRDC_W1_SLV_PA_ERR_MASK) + +#define TRDC_W1_SLV_SA_ERR_MASK (0x40U) +#define TRDC_W1_SLV_SA_ERR_SHIFT (6U) +/*! SLV_SA_ERR - Secure attribute check error */ +#define TRDC_W1_SLV_SA_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_SA_ERR_SHIFT)) & TRDC_W1_SLV_SA_ERR_MASK) + +#define TRDC_W1_SLV_ABORT_MASK (0x80U) +#define TRDC_W1_SLV_ABORT_SHIFT (7U) +/*! SLV_ABORT - Bus protect error */ +#define TRDC_W1_SLV_ABORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_ABORT_SHIFT)) & TRDC_W1_SLV_ABORT_MASK) + #define TRDC_W1_EATR_MASK (0x700U) #define TRDC_W1_EATR_SHIFT (8U) /*! EATR - Error attributes @@ -803,6 +823,26 @@ typedef struct { /*! EDID - Error domain identifier */ #define TRDC_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK) +#define TRDC_W1_SLV_DID_ERR_MASK (0x10U) +#define TRDC_W1_SLV_DID_ERR_SHIFT (4U) +/*! SLV_DID_ERR - DID check error */ +#define TRDC_W1_SLV_DID_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_DID_ERR_SHIFT)) & TRDC_W1_SLV_DID_ERR_MASK) + +#define TRDC_W1_SLV_PA_ERR_MASK (0x20U) +#define TRDC_W1_SLV_PA_ERR_SHIFT (5U) +/*! SLV_PA_ERR - Privilege attribute check error */ +#define TRDC_W1_SLV_PA_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_PA_ERR_SHIFT)) & TRDC_W1_SLV_PA_ERR_MASK) + +#define TRDC_W1_SLV_SA_ERR_MASK (0x40U) +#define TRDC_W1_SLV_SA_ERR_SHIFT (6U) +/*! SLV_SA_ERR - Secure attribute check error */ +#define TRDC_W1_SLV_SA_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_SA_ERR_SHIFT)) & TRDC_W1_SLV_SA_ERR_MASK) + +#define TRDC_W1_SLV_ABORT_MASK (0x80U) +#define TRDC_W1_SLV_ABORT_SHIFT (7U) +/*! SLV_ABORT - Bus protect error */ +#define TRDC_W1_SLV_ABORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_ABORT_SHIFT)) & TRDC_W1_SLV_ABORT_MASK) + #define TRDC_W1_EATR_MASK (0x700U) #define TRDC_W1_EATR_SHIFT (8U) /*! EATR - Error attributes @@ -857,7 +897,7 @@ typedef struct { /* The count of TRDC_W3 */ #define TRDC_MRC_DERR_W3_COUNT (1U) -/*! @name MDA_W0_0_DFMT0 - DAC Master Domain Assignment Register */ +/*! @name MDA_W0_0_DFMT0 - DAC Initiator Domain Assignment Register */ /*! @{ */ #define TRDC_MDA_W0_0_DFMT0_DID_MASK (0xFU) @@ -878,21 +918,13 @@ typedef struct { #define TRDC_MDA_W0_0_DFMT0_SA_MASK (0xC000U) #define TRDC_MDA_W0_0_DFMT0_SA_SHIFT (14U) /*! SA - Secure attribute - * 0b00..Force the bus attribute for this master to secure. - * 0b01..Force the bus attribute for this master to nonsecure. - * 0b10..Use the bus master's secure/nonsecure attribute directly. - * 0b11..Use the bus master's secure/nonsecure attribute directly. + * 0b00..Force the bus attribute for this initiator to secure. + * 0b01..Force the bus attribute for this initiator to nonsecure. + * 0b10..Use the bus initiator's secure/nonsecure attribute directly. + * 0b11..Use the bus initiator's secure/nonsecure attribute directly. */ #define TRDC_MDA_W0_0_DFMT0_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_SA_SHIFT)) & TRDC_MDA_W0_0_DFMT0_SA_MASK) -#define TRDC_MDA_W0_0_DFMT0_KPA_MASK (0x10000000U) -#define TRDC_MDA_W0_0_DFMT0_KPA_SHIFT (28U) -/*! KPA - Known Physical Address - * 0b0..The address is non-physical and requires SMMU translation. - * 0b1..The address is physical and bypasses any downstream SMMU. - */ -#define TRDC_MDA_W0_0_DFMT0_KPA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_KPA_SHIFT)) & TRDC_MDA_W0_0_DFMT0_KPA_MASK) - #define TRDC_MDA_W0_0_DFMT0_DFMT_MASK (0x20000000U) #define TRDC_MDA_W0_0_DFMT0_DFMT_SHIFT (29U) /*! DFMT - Domain format @@ -918,7 +950,7 @@ typedef struct { #define TRDC_MDA_W0_0_DFMT0_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_VLD_SHIFT)) & TRDC_MDA_W0_0_DFMT0_VLD_MASK) /*! @} */ -/*! @name MDA_W0_x_DFMT1 - DAC Master Domain Assignment Register */ +/*! @name MDA_W0_x_DFMT1 - DAC Initiator Domain Assignment Register */ /*! @{ */ #define TRDC_MDA_W0_x_DFMT1_DID_MASK (0xFU) @@ -929,20 +961,20 @@ typedef struct { #define TRDC_MDA_W0_x_DFMT1_PA_MASK (0x30U) #define TRDC_MDA_W0_x_DFMT1_PA_SHIFT (4U) /*! PA - Privileged attribute - * 0b00..Force the bus attribute for this master to user. - * 0b01..Force the bus attribute for this master to privileged. - * 0b10..Use the bus master's privileged/user attribute directly. - * 0b11..Use the bus master's privileged/user attribute directly. + * 0b00..Force the bus attribute for this initiator to user. + * 0b01..Force the bus attribute for this initiator to privileged. + * 0b10..Use the bus initiator's privileged/user attribute directly. + * 0b11..Use the bus initiator's privileged/user attribute directly. */ #define TRDC_MDA_W0_x_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_PA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_PA_MASK) #define TRDC_MDA_W0_x_DFMT1_SA_MASK (0xC0U) #define TRDC_MDA_W0_x_DFMT1_SA_SHIFT (6U) /*! SA - Secure attribute - * 0b00..Force the bus attribute for this master to secure. - * 0b01..Force the bus attribute for this master to nonsecure. - * 0b10..Use the bus master's secure/nonsecure attribute directly. - * 0b11..Use the bus master's secure/nonsecure attribute directly. + * 0b00..Force the bus attribute for this initiator to secure. + * 0b01..Force the bus attribute for this initiator to nonsecure. + * 0b10..Use the bus initiator's secure/nonsecure attribute directly. + * 0b11..Use the bus initiator's secure/nonsecure attribute directly. */ #define TRDC_MDA_W0_x_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_SA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_SA_MASK) @@ -954,14 +986,6 @@ typedef struct { */ #define TRDC_MDA_W0_x_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_DIDB_SHIFT)) & TRDC_MDA_W0_x_DFMT1_DIDB_MASK) -#define TRDC_MDA_W0_x_DFMT1_KPA_MASK (0x10000000U) -#define TRDC_MDA_W0_x_DFMT1_KPA_SHIFT (28U) -/*! KPA - Known Physical Address - * 0b0..The address is non-physical and requires SMMU translation. - * 0b1..The address is physical and bypasses any downstream SMMU. - */ -#define TRDC_MDA_W0_x_DFMT1_KPA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_KPA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_KPA_MASK) - #define TRDC_MDA_W0_x_DFMT1_DFMT_MASK (0x20000000U) #define TRDC_MDA_W0_x_DFMT1_DFMT_SHIFT (29U) /*! DFMT - Domain format diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TRGMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TRGMUX.h index e60811789..f164034bc 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TRGMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TRGMUX.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRGMUX diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TSTMR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TSTMR.h index 0aaf50f21..6cc8f3356 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TSTMR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TSTMR.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TSTMR diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TX_PACKET_RAM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TX_PACKET_RAM.h index 81321d037..f6c31b91f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TX_PACKET_RAM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_TX_PACKET_RAM.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TX_PACKET_RAM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_UART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_UART.h index 206db5776..62bc02001 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_UART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_UART.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for UART diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_UART_PFU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_UART_PFU.h index e20bbc006..66b6ab7b0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_UART_PFU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_UART_PFU.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for UART_PFU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_VBAT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_VBAT.h index 46a48905b..32f33f8c1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_VBAT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_VBAT.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for VBAT diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_VREF.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_VREF.h index c8f6113d7..7fc095344 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_VREF.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_VREF.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for VREF @@ -230,7 +230,7 @@ typedef struct { #define VREF_UTRIM_TRIM2V1_MASK (0xFU) #define VREF_UTRIM_TRIM2V1_SHIFT (0U) -/*! TRIM2V1 - VREF 2.1 V Trim */ +/*! TRIM2V1 - VREF 2.048 V Trim */ #define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) #define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WDOG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WDOG.h index e5d24b939..56d81de6c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WDOG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WDOG.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for WDOG diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WOR.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WOR.h index d959d9fd6..c503e3c6d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WOR.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WOR.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for WOR diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WUU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WUU.h index 23ef14e1a..ea097f055 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WUU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_WUU.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for WUU diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_ANALOG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_ANALOG.h index 9ba4777e2..3fcb575b9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_ANALOG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_ANALOG.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_ANALOG @@ -469,8 +469,8 @@ typedef struct { /*! PLL_PD_TRIM_FCAL_BIAS - reg_pd_trim_fcal_bias_dig[1:0] * 0b00..0.276V (recommended setting for legacy operation) * 0b01..0.164V - * 0b10..0.320V - * 0b11..0.391V (recommended setting for PIC use) + * 0b10..0.320V (recommended setting for PIC use) + * 0b11..0.391V */ #define XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS_SHIFT)) & XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS_MASK) diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_MISC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_MISC.h index 67bd36894..6f09eb95f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_MISC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_MISC.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_MISC diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_PLL_DIG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_PLL_DIG.h index 25e883ff4..0f7f01d10 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_PLL_DIG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_PLL_DIG.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_PLL_DIG @@ -1160,6 +1160,11 @@ typedef struct { #define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_SHIFT (24U) /*! HPM_INTEGER_DELAY_DRS - DRS HPM_SDM_DELAY */ #define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_MASK) + +#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS_MASK (0xF0000000U) +#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS_SHIFT (28U) +/*! HPM_COUNT_ADJUST_DRS - HPM_COUNT_ADJUST_DRS */ +#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_RX_DIG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_RX_DIG.h index ac623db07..21863ee5a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_RX_DIG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_RX_DIG.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_RX_DIG @@ -198,6 +198,10 @@ typedef struct { __IO uint32_t CTRL2; /**< RXDIG Control 2, offset: 0x184 */ __IO uint32_t NADM_CTRL; /**< Controls for the NADM module, offset: 0x188 */ __I uint32_t NADM_RES; /**< NADM latest packet results., offset: 0x18C */ + __IO uint32_t FCFO_CTRL; /**< Fine CFO module controls., offset: 0x190 */ + __IO uint32_t FCFO_TN; /**< Tone parameters., offset: 0x194 */ + __IO uint32_t FCFO_TN_PH; /**< F2 carrier iq phases, offset: 0x198 */ + __I uint32_t FCFO_RES; /**< Fine CFO results., offset: 0x19C */ } XCVR_RX_DIG_Type; /* ---------------------------------------------------------------------------- @@ -3224,10 +3228,12 @@ typedef struct { #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_MASK (0xFFFFU) #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_SHIFT (0U) +/*! rx_tone_ana_out_q - Accumulator Q path result. */ #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_MASK) #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_MASK (0xFFFF0000U) #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_SHIFT (16U) +/*! rx_tone_ana_out_i - Accumulator I path result */ #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_MASK) /*! @} */ @@ -3299,7 +3305,7 @@ typedef struct { #define XCVR_RX_DIG_TQI_CTRL_TQI_EN_MASK (0x10000U) #define XCVR_RX_DIG_TQI_CTRL_TQI_EN_SHIFT (16U) -/*! TQI_EN +/*! TQI_EN - Enables TQI operation. * 0b0..TQI operation is disabled. * 0b1..TQI operation is enabled. */ @@ -3377,6 +3383,16 @@ typedef struct { #define XCVR_RX_DIG_NADM_CTRL_NADM_FIR_LATENCY_SHIFT (17U) /*! NADM_FIR_LATENCY - FM correlator path, delay between reference start and correlator start. */ #define XCVR_RX_DIG_NADM_CTRL_NADM_FIR_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NADM_CTRL_NADM_FIR_LATENCY_SHIFT)) & XCVR_RX_DIG_NADM_CTRL_NADM_FIR_LATENCY_MASK) + +#define XCVR_RX_DIG_NADM_CTRL_NADM_SIZE_MASK (0x1C00000U) +#define XCVR_RX_DIG_NADM_CTRL_NADM_SIZE_SHIFT (22U) +/*! NADM_SIZE - NADM size aligned on RTT_TYPE standard value */ +#define XCVR_RX_DIG_NADM_CTRL_NADM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NADM_CTRL_NADM_SIZE_SHIFT)) & XCVR_RX_DIG_NADM_CTRL_NADM_SIZE_MASK) + +#define XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE_MASK (0xE000000U) +#define XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE_SHIFT (25U) +/*! NADM_IDX_CAPTURE - Index used to get optimum fm_diff in DMA_DBG */ +#define XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE_SHIFT)) & XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE_MASK) /*! @} */ /*! @name NADM_RES - NADM latest packet results. */ @@ -3393,6 +3409,122 @@ typedef struct { #define XCVR_RX_DIG_NADM_RES_NADM_INST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NADM_RES_NADM_INST_SHIFT)) & XCVR_RX_DIG_NADM_RES_NADM_INST_MASK) /*! @} */ +/*! @name FCFO_CTRL - Fine CFO module controls. */ +/*! @{ */ + +#define XCVR_RX_DIG_FCFO_CTRL_A_MUL_MASK (0xFFU) +#define XCVR_RX_DIG_FCFO_CTRL_A_MUL_SHIFT (0U) +/*! A_MUL - Alpha linear multiplication coeficient */ +#define XCVR_RX_DIG_FCFO_CTRL_A_MUL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_A_MUL_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_A_MUL_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_A_DIV_MASK (0xF000U) +#define XCVR_RX_DIG_FCFO_CTRL_A_DIV_SHIFT (12U) +/*! A_DIV - Alpha linear division coeficient */ +#define XCVR_RX_DIG_FCFO_CTRL_A_DIV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_A_DIV_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_A_DIV_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA_MASK (0x10000U) +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA_SHIFT (16U) +/*! FCFO_ENA - Enables FCFO module. + * 0b0..Fcfo algorithm disabled. + * 0b1..Fcfo algorithm enabled. + */ +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_OUT_IQ_MASK (0x40000U) +#define XCVR_RX_DIG_FCFO_CTRL_OUT_IQ_SHIFT (18U) +/*! OUT_IQ - FCFO output format. + * 0b0..Fcfo output are g function values (previous/current). + * 0b1..Fcfo output are IQ values. + */ +#define XCVR_RX_DIG_FCFO_CTRL_OUT_IQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_OUT_IQ_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_OUT_IQ_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC_MASK (0x300000U) +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC_SHIFT (20U) +/*! TRIG_SRC - Selects FCFO trigger source. + * 0b00..Selects TPM as trigger source + * 0b01..Selects TFM as trigger source + * 0b10..Selects software as trigger source. + */ +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY_MASK (0x3000000U) +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY_SHIFT (24U) +/*! TRIG_DLY - Delay between trigger and fcfo start. + * 0b00..Selects 2us trigger delay. + * 0b01..Selects 5us trigger delay. + * 0b10..Selects 10us trigger delay. + * 0b11..Selects 15us trigger delay. + */ +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_A_OVF_MASK (0x10000000U) +#define XCVR_RX_DIG_FCFO_CTRL_A_OVF_SHIFT (28U) +/*! A_OVF - Alpha multiplier overflow. */ +#define XCVR_RX_DIG_FCFO_CTRL_A_OVF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_A_OVF_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_A_OVF_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR_MASK (0x20000000U) +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR_SHIFT (29U) +/*! FCFO_ERR - FCFO value error. */ +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE_MASK (0x40000000U) +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE_SHIFT (30U) +/*! FCFO_DONE - FCFO done. */ +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE_MASK) +/*! @} */ + +/*! @name FCFO_TN - Tone parameters. */ +/*! @{ */ + +#define XCVR_RX_DIG_FCFO_TN_TN_F1_INC_MASK (0x7FU) +#define XCVR_RX_DIG_FCFO_TN_TN_F1_INC_SHIFT (0U) +/*! TN_F1_INC - Tone F1 increment. */ +#define XCVR_RX_DIG_FCFO_TN_TN_F1_INC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_TN_F1_INC_SHIFT)) & XCVR_RX_DIG_FCFO_TN_TN_F1_INC_MASK) + +#define XCVR_RX_DIG_FCFO_TN_TN_F1_DIV_MASK (0x700U) +#define XCVR_RX_DIG_FCFO_TN_TN_F1_DIV_SHIFT (8U) +/*! TN_F1_DIV - Tone F1 clock divisor. */ +#define XCVR_RX_DIG_FCFO_TN_TN_F1_DIV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_TN_F1_DIV_SHIFT)) & XCVR_RX_DIG_FCFO_TN_TN_F1_DIV_MASK) + +#define XCVR_RX_DIG_FCFO_TN_TN_F2_INC_MASK (0x7F0000U) +#define XCVR_RX_DIG_FCFO_TN_TN_F2_INC_SHIFT (16U) +/*! TN_F2_INC - Tone F2 increment. */ +#define XCVR_RX_DIG_FCFO_TN_TN_F2_INC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_TN_F2_INC_SHIFT)) & XCVR_RX_DIG_FCFO_TN_TN_F2_INC_MASK) + +#define XCVR_RX_DIG_FCFO_TN_TN_F2_DIV_MASK (0x7000000U) +#define XCVR_RX_DIG_FCFO_TN_TN_F2_DIV_SHIFT (24U) +/*! TN_F2_DIV - Tone F2 clock divisor. */ +#define XCVR_RX_DIG_FCFO_TN_TN_F2_DIV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_TN_F2_DIV_SHIFT)) & XCVR_RX_DIG_FCFO_TN_TN_F2_DIV_MASK) +/*! @} */ + +/*! @name FCFO_TN_PH - F2 carrier iq phases */ +/*! @{ */ + +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I_MASK (0x1FFU) +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I_SHIFT (0U) +/*! F2_PH_I - F2 carrier I start phase */ +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I_SHIFT)) & XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I_MASK) + +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q_MASK (0x1FF0000U) +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q_SHIFT (16U) +/*! F2_PH_Q - F2 carrier Q start phase */ +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q_SHIFT)) & XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q_MASK) +/*! @} */ + +/*! @name FCFO_RES - Fine CFO results. */ +/*! @{ */ + +#define XCVR_RX_DIG_FCFO_RES_G_CUR_MASK (0xFFFFU) +#define XCVR_RX_DIG_FCFO_RES_G_CUR_SHIFT (0U) +/*! G_CUR - g function, current value. */ +#define XCVR_RX_DIG_FCFO_RES_G_CUR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_RES_G_CUR_SHIFT)) & XCVR_RX_DIG_FCFO_RES_G_CUR_MASK) + +#define XCVR_RX_DIG_FCFO_RES_G_PRV_MASK (0xFFFF0000U) +#define XCVR_RX_DIG_FCFO_RES_G_PRV_SHIFT (16U) +/*! G_PRV - g function, previous value. */ +#define XCVR_RX_DIG_FCFO_RES_G_PRV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_RES_G_PRV_SHIFT)) & XCVR_RX_DIG_FCFO_RES_G_PRV_MASK) +/*! @} */ + /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_TSM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_TSM.h index 52ee59897..a684a326d 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_TSM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_TSM.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_TSM diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_TX_DIG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_TX_DIG.h index fd1ff306c..440a98426 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_TX_DIG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_TX_DIG.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_TX_DIG diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_ZBDEMOD.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_ZBDEMOD.h index eaf46cbe9..7900bbf0a 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_ZBDEMOD.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_XCVR_ZBDEMOD.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_ZBDEMOD diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ZLL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ZLL.h index 7880d8800..942716ac1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ZLL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph3/PERI_ZLL.h @@ -8,7 +8,7 @@ ** MCXW727DMFTA_cm33_core1 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for ZLL diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_AHB_SECURE_CTRL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_AHB_SECURE_CTRL.h index b73300ce2..1639b2751 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_AHB_SECURE_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_AHB_SECURE_CTRL.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for AHB_SECURE_CTRL @@ -42,7 +44,7 @@ #if !defined(PERI_AHB_SECURE_CTRL_H_) #define PERI_AHB_SECURE_CTRL_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_ANACTRL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_ANACTRL.h index daad769c2..cd8c32058 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_ANACTRL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_ANACTRL.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANACTRL @@ -42,7 +44,7 @@ #if !defined(PERI_ANACTRL_H_) #define PERI_ANACTRL_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CASPER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CASPER.h index d7be42588..4664756cb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CASPER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CASPER.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for CASPER @@ -42,7 +44,7 @@ #if !defined(PERI_CASPER_H_) #define PERI_CASPER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CDOG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CDOG.h index 996dc440e..16444b867 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CDOG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CDOG.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for CDOG @@ -42,7 +44,7 @@ #if !defined(PERI_CDOG_H_) #define PERI_CDOG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CRC.h index e29e1ae0f..19dae6fe5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CRC.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC @@ -42,7 +44,7 @@ #if !defined(PERI_CRC_H_) #define PERI_CRC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CTIMER.h index 9730a1715..88d447081 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CTIMER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_CTIMER.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for CTIMER @@ -42,7 +44,7 @@ #if !defined(PERI_CTIMER_H_) #define PERI_CTIMER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_DBGMAILBOX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_DBGMAILBOX.h index e136af3a8..1651f606f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_DBGMAILBOX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_DBGMAILBOX.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for DBGMAILBOX @@ -42,7 +44,7 @@ #if !defined(PERI_DBGMAILBOX_H_) #define PERI_DBGMAILBOX_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_DMA.h index 15ca57e23..1bdb8e814 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_DMA.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -42,7 +44,7 @@ #if !defined(PERI_DMA_H_) #define PERI_DMA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_CFPA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_CFPA.h index 5617bb410..8b89bb92e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_CFPA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_CFPA.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH_CFPA @@ -42,7 +44,7 @@ #if !defined(PERI_FLASH_CFPA_H_) #define PERI_FLASH_CFPA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_CMPA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_CMPA.h index a0166900b..d83227828 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_CMPA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_CMPA.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH_CMPA @@ -42,7 +44,7 @@ #if !defined(PERI_FLASH_CMPA_H_) #define PERI_FLASH_CMPA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_KEY_STORE.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_KEY_STORE.h index 0359d38a1..099936ad7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_KEY_STORE.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_KEY_STORE.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH_KEY_STORE @@ -42,7 +44,7 @@ #if !defined(PERI_FLASH_KEY_STORE_H_) #define PERI_FLASH_KEY_STORE_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_NMPA.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_NMPA.h index e485a640b..8c343bcee 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_NMPA.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_NMPA.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250624 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH_NMPA @@ -42,7 +44,7 @@ #if !defined(PERI_FLASH_NMPA_H_) #define PERI_FLASH_NMPA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_ROMPATCH.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_ROMPATCH.h index 7b3b0c1f0..ef16d9310 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_ROMPATCH.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLASH_ROMPATCH.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLASH_ROMPATCH @@ -42,7 +44,7 @@ #if !defined(PERI_FLASH_ROMPATCH_H_) #define PERI_FLASH_ROMPATCH_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLEXCOMM.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLEXCOMM.h index 61645103e..d6ef7dc20 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLEXCOMM.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FLEXCOMM.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXCOMM @@ -42,7 +44,7 @@ #if !defined(PERI_FLEXCOMM_H_) #define PERI_FLEXCOMM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FMU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FMU.h index 088e9d2ac..7f4c4a78b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FMU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_FMU.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMU @@ -42,7 +44,7 @@ #if !defined(PERI_FMU_H_) #define PERI_FMU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_GINT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_GINT.h index aaa2b5f25..c2d4c7330 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_GINT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_GINT.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for GINT @@ -42,7 +44,7 @@ #if !defined(PERI_GINT_H_) #define PERI_GINT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_GPIO.h index 2d2db669a..d2815a4d2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_GPIO.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250609 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO @@ -42,7 +44,7 @@ #if !defined(PERI_GPIO_H_) #define PERI_GPIO_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_HASHCRYPT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_HASHCRYPT.h index 8ea2e74ae..de96901c0 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_HASHCRYPT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_HASHCRYPT.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for HASHCRYPT @@ -42,7 +44,7 @@ #if !defined(PERI_HASHCRYPT_H_) #define PERI_HASHCRYPT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_I2C.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_I2C.h index 9711f807d..1477a3f30 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_I2C.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_I2C.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2C @@ -42,7 +44,7 @@ #if !defined(PERI_I2C_H_) #define PERI_I2C_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_INPUTMUX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_INPUTMUX.h index 618bffcc6..9a45c69ca 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_INPUTMUX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_INPUTMUX.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250821 ** ** Abstract: ** CMSIS Peripheral Access Layer for INPUTMUX @@ -42,7 +44,7 @@ #if !defined(PERI_INPUTMUX_H_) #define PERI_INPUTMUX_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" @@ -332,7 +334,7 @@ typedef struct { * 0b01011..Timer CTIMER3 Match 1 * 0b01100..Timer CTIMER4 Match 0 * 0b01101..Timer CTIMER4 Match 1 - * 0b01110..COMP_OUTPUT + * 0b01110..Reserved * 0b01111..DMA0 output trigger mux 0 * 0b10000..DMA0 output trigger mux 1 * 0b10001..DMA0 output trigger mux 1 diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_IOCON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_IOCON.h index 76cff914c..37b5120bb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_IOCON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_IOCON.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOCON @@ -42,7 +44,7 @@ #if !defined(PERI_IOCON_H_) #define PERI_IOCON_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_MRT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_MRT.h index f74b763fc..51f0eb3ca 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_MRT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_MRT.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for MRT @@ -42,7 +44,7 @@ #if !defined(PERI_MRT_H_) #define PERI_MRT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_NPX.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_NPX.h index 0de0fe1ec..e1a3d50b7 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_NPX.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_NPX.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for NPX @@ -42,7 +44,7 @@ #if !defined(PERI_NPX_H_) #define PERI_NPX_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_OSTIMER.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_OSTIMER.h index ae66ee019..1bd22dbce 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_OSTIMER.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_OSTIMER.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSTIMER @@ -42,7 +44,7 @@ #if !defined(PERI_OSTIMER_H_) #define PERI_OSTIMER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PINT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PINT.h index a112d40c3..2c1e4a530 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PINT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PINT.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for PINT @@ -42,7 +44,7 @@ #if !defined(PERI_PINT_H_) #define PERI_PINT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PLU.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PLU.h index fd19e8446..aa469d420 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PLU.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PLU.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for PLU @@ -42,7 +44,7 @@ #if !defined(PERI_PLU_H_) #define PERI_PLU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PMC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PMC.h index a68d1aec1..b4d02614b 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PMC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PMC.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250624 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for PMC @@ -42,7 +44,7 @@ #if !defined(PERI_PMC_H_) #define PERI_PMC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PUF.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PUF.h index 7aa28aff9..7534af2c4 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PUF.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PUF.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for PUF @@ -42,7 +44,7 @@ #if !defined(PERI_PUF_H_) #define PERI_PUF_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PUF_SRAM_CTRL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PUF_SRAM_CTRL.h index 0ec6799a4..897588605 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PUF_SRAM_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_PUF_SRAM_CTRL.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for PUF_SRAM_CTRL @@ -42,7 +44,7 @@ #if !defined(PERI_PUF_SRAM_CTRL_H_) #define PERI_PUF_SRAM_CTRL_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_RADIO.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_RADIO.h index ce618cf2b..87c63e38f 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_RADIO.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_RADIO.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for RADIO @@ -42,7 +44,7 @@ #if !defined(PERI_RADIO_H_) #define PERI_RADIO_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_ROMCP.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_ROMCP.h index e14d99b13..cd644d6b5 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_ROMCP.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_ROMCP.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for ROMCP @@ -42,7 +44,7 @@ #if !defined(PERI_ROMCP_H_) #define PERI_ROMCP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_RTC.h index 389dc1abb..7e5871bdb 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_RTC.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -42,7 +44,7 @@ #if !defined(PERI_RTC_H_) #define PERI_RTC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SCT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SCT.h index 11ced7937..7b10ede54 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SCT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SCT.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for SCT @@ -42,7 +44,7 @@ #if !defined(PERI_SCT_H_) #define PERI_SCT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SPI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SPI.h index 6d44ff3c4..6adbabd78 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SPI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SPI.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPI @@ -42,7 +44,7 @@ #if !defined(PERI_SPI_H_) #define PERI_SPI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SPIFI.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SPIFI.h index 14f5acfdd..a2a9c8337 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SPIFI.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SPIFI.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPIFI @@ -42,7 +44,7 @@ #if !defined(PERI_SPIFI_H_) #define PERI_SPIFI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SYSCON.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SYSCON.h index 64e0f42a1..31f865144 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SYSCON.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SYSCON.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250624 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON @@ -42,7 +44,7 @@ #if !defined(PERI_SYSCON_H_) #define PERI_SYSCON_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SYSCTL.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SYSCTL.h index cee09e2c3..17c74404c 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SYSCTL.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_SYSCTL.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCTL @@ -42,7 +44,7 @@ #if !defined(PERI_SYSCTL_H_) #define PERI_SYSCTL_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_TRNG.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_TRNG.h index 166138a6c..92c66f7c1 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_TRNG.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_TRNG.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRNG @@ -42,7 +44,7 @@ #if !defined(PERI_TRNG_H_) #define PERI_TRNG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_USART.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_USART.h index f62590b33..0950776f2 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_USART.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_USART.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for USART @@ -42,7 +44,7 @@ #if !defined(PERI_USART_H_) #define PERI_USART_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_UTICK.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_UTICK.h index 4476bf8da..963df7d8e 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_UTICK.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_UTICK.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for UTICK @@ -42,7 +44,7 @@ #if !defined(PERI_UTICK_H_) #define PERI_UTICK_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" diff --git a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_WWDT.h b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_WWDT.h index 9abc4845a..caec81ab9 100644 --- a/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_WWDT.h +++ b/mcux/mcux-sdk-ng/devices/MCX/MCXW/periph4/PERI_WWDT.h @@ -1,6 +1,8 @@ /* ** ################################################################### -** Processors: MCXW235BIHNAR +** Processors: MCXW235AIHNAR +** MCXW235AIUKAR +** MCXW235BIHNAR ** MCXW235BIUKAR ** MCXW236AIHNAR ** MCXW236AIUKAR @@ -8,7 +10,7 @@ ** MCXW236BIUKAR ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250819 ** ** Abstract: ** CMSIS Peripheral Access Layer for WWDT @@ -42,7 +44,7 @@ #if !defined(PERI_WWDT_H_) #define PERI_WWDT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) +#if (defined(CPU_MCXW235AIHNAR) || defined(CPU_MCXW235AIUKAR) || defined(CPU_MCXW235BIHNAR) || defined(CPU_MCXW235BIUKAR)) #include "MCXW235_COMMON.h" #elif (defined(CPU_MCXW236AIHNAR) || defined(CPU_MCXW236AIUKAR) || defined(CPU_MCXW236BIHNAR) || defined(CPU_MCXW236BIUKAR)) #include "MCXW236_COMMON.h" From 314bf653d4c409ac8dc3ffa6c07f579c1ae8f3cb Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:30:21 +0800 Subject: [PATCH 08/21] hal_nxp: mcux-sdk-ng: Update device/RT to sdk 25.09.00 Signed-off-by: Zhaoxiang Jin --- .../RT/RT1010/MIMXRT1011/MIMXRT1011_COMMON.h | 10 +- .../RT1010/MIMXRT1011/MIMXRT1011_features.h | 61 ++++- .../devices/RT/RT1010/periph/PERI_FLEXSPI.h | 37 +-- .../devices/RT/RT1010/periph/PERI_RTWDOG.h | 6 +- .../RT/RT1015/MIMXRT1015/MIMXRT1015_COMMON.h | 10 +- .../RT1015/MIMXRT1015/MIMXRT1015_features.h | 61 ++++- .../devices/RT/RT1015/periph/PERI_FLEXSPI.h | 37 +-- .../devices/RT/RT1015/periph/PERI_RTWDOG.h | 6 +- .../devices/RT/RT1020/MIMXRT1021/MIMXRT1021.h | 2 +- .../RT/RT1020/MIMXRT1021/MIMXRT1021_COMMON.h | 10 +- .../RT1020/MIMXRT1021/MIMXRT1021_features.h | 83 ++++-- .../RT/RT1020/MIMXRT1021/system_MIMXRT1021.c | 2 +- .../RT/RT1020/MIMXRT1021/system_MIMXRT1021.h | 2 +- .../devices/RT/RT1020/MIMXRT1024/MIMXRT1024.h | 2 +- .../RT/RT1020/MIMXRT1024/MIMXRT1024_COMMON.h | 10 +- .../RT1020/MIMXRT1024/MIMXRT1024_features.h | 83 ++++-- .../RT/RT1020/MIMXRT1024/system_MIMXRT1024.c | 6 +- .../RT/RT1020/MIMXRT1024/system_MIMXRT1024.h | 4 +- .../devices/RT/RT1020/periph/PERI_ADC.h | 2 +- .../devices/RT/RT1020/periph/PERI_ADC_ETC.h | 2 +- .../devices/RT/RT1020/periph/PERI_AIPSTZ.h | 2 +- .../devices/RT/RT1020/periph/PERI_AOI.h | 2 +- .../devices/RT/RT1020/periph/PERI_BEE.h | 2 +- .../devices/RT/RT1020/periph/PERI_CAN.h | 2 +- .../devices/RT/RT1020/periph/PERI_CCM.h | 2 +- .../RT/RT1020/periph/PERI_CCM_ANALOG.h | 2 +- .../devices/RT/RT1020/periph/PERI_CM7_MCM.h | 2 +- .../devices/RT/RT1020/periph/PERI_CMP.h | 2 +- .../devices/RT/RT1020/periph/PERI_CSU.h | 2 +- .../devices/RT/RT1020/periph/PERI_DCDC.h | 2 +- .../devices/RT/RT1020/periph/PERI_DCP.h | 2 +- .../devices/RT/RT1020/periph/PERI_DMA.h | 2 +- .../devices/RT/RT1020/periph/PERI_DMAMUX.h | 2 +- .../devices/RT/RT1020/periph/PERI_ENC.h | 2 +- .../devices/RT/RT1020/periph/PERI_ENET.h | 2 +- .../devices/RT/RT1020/periph/PERI_EWM.h | 2 +- .../devices/RT/RT1020/periph/PERI_FLEXIO.h | 2 +- .../devices/RT/RT1020/periph/PERI_FLEXRAM.h | 2 +- .../devices/RT/RT1020/periph/PERI_FLEXSPI.h | 37 +-- .../devices/RT/RT1020/periph/PERI_GPC.h | 2 +- .../devices/RT/RT1020/periph/PERI_GPIO.h | 2 +- .../devices/RT/RT1020/periph/PERI_GPT.h | 2 +- .../devices/RT/RT1020/periph/PERI_I2S.h | 2 +- .../devices/RT/RT1020/periph/PERI_IOMUXC.h | 2 +- .../RT/RT1020/periph/PERI_IOMUXC_GPR.h | 2 +- .../RT/RT1020/periph/PERI_IOMUXC_SNVS.h | 2 +- .../RT/RT1020/periph/PERI_IOMUXC_SNVS_GPR.h | 2 +- .../devices/RT/RT1020/periph/PERI_KPP.h | 2 +- .../devices/RT/RT1020/periph/PERI_LPI2C.h | 2 +- .../devices/RT/RT1020/periph/PERI_LPSPI.h | 2 +- .../devices/RT/RT1020/periph/PERI_LPUART.h | 2 +- .../devices/RT/RT1020/periph/PERI_OCOTP.h | 2 +- .../devices/RT/RT1020/periph/PERI_PGC.h | 2 +- .../devices/RT/RT1020/periph/PERI_PIT.h | 2 +- .../devices/RT/RT1020/periph/PERI_PMU.h | 2 +- .../devices/RT/RT1020/periph/PERI_PWM.h | 2 +- .../devices/RT/RT1020/periph/PERI_RTWDOG.h | 6 +- .../devices/RT/RT1020/periph/PERI_SEMC.h | 2 +- .../devices/RT/RT1020/periph/PERI_SNVS.h | 2 +- .../devices/RT/RT1020/periph/PERI_SPDIF.h | 2 +- .../devices/RT/RT1020/periph/PERI_SRC.h | 2 +- .../devices/RT/RT1020/periph/PERI_TEMPMON.h | 2 +- .../devices/RT/RT1020/periph/PERI_TMR.h | 2 +- .../devices/RT/RT1020/periph/PERI_TRNG.h | 2 +- .../devices/RT/RT1020/periph/PERI_USB.h | 2 +- .../devices/RT/RT1020/periph/PERI_USBNC.h | 2 +- .../devices/RT/RT1020/periph/PERI_USBPHY.h | 2 +- .../RT/RT1020/periph/PERI_USB_ANALOG.h | 2 +- .../devices/RT/RT1020/periph/PERI_USDHC.h | 2 +- .../devices/RT/RT1020/periph/PERI_WDOG.h | 2 +- .../devices/RT/RT1020/periph/PERI_XBARA.h | 2 +- .../devices/RT/RT1020/periph/PERI_XBARB.h | 2 +- .../RT/RT1020/periph/PERI_XTALOSC24M.h | 2 +- .../RT/RT1040/MIMXRT1041/MIMXRT1041_COMMON.h | 12 +- .../RT1040/MIMXRT1041/MIMXRT1041_features.h | 85 ++++-- .../RT/RT1040/MIMXRT1042/MIMXRT1042_COMMON.h | 12 +- .../RT1040/MIMXRT1042/MIMXRT1042_features.h | 85 ++++-- .../RT/RT1040/MIMXRT1043/MIMXRT1043_COMMON.h | 12 +- .../RT1040/MIMXRT1043/MIMXRT1043_features.h | 85 ++++-- .../RT/RT1040/MIMXRT1046/MIMXRT1046_COMMON.h | 26 +- .../RT1040/MIMXRT1046/MIMXRT1046_features.h | 85 ++++-- .../devices/RT/RT1040/periph/PERI_FLEXSPI.h | 37 +-- .../devices/RT/RT1040/periph/PERI_RTWDOG.h | 6 +- .../RT/RT1050/MIMXRT1051/MIMXRT1051_COMMON.h | 10 +- .../RT1050/MIMXRT1051/MIMXRT1051_features.h | 83 ++++-- .../RT/RT1050/MIMXRT1052/MIMXRT1052_COMMON.h | 10 +- .../RT1050/MIMXRT1052/MIMXRT1052_features.h | 83 ++++-- .../devices/RT/RT1050/periph/PERI_FLEXSPI.h | 37 +-- .../devices/RT/RT1050/periph/PERI_RTWDOG.h | 6 +- .../RT/RT1060/MIMXRT1061/MIMXRT1061_COMMON.h | 12 +- .../RT1060/MIMXRT1061/MIMXRT1061_features.h | 85 ++++-- .../RT/RT1060/MIMXRT1062/MIMXRT1062_COMMON.h | 12 +- .../RT1060/MIMXRT1062/MIMXRT1062_features.h | 85 ++++-- .../devices/RT/RT1060/periph/PERI_FLEXSPI.h | 37 +-- .../devices/RT/RT1060/periph/PERI_RTWDOG.h | 6 +- .../RT/RT1064/MIMXRT1064/MIMXRT1064_COMMON.h | 12 +- .../RT1064/MIMXRT1064/MIMXRT1064_features.h | 85 ++++-- .../devices/RT/RT1064/periph/PERI_FLEXSPI.h | 37 +-- .../devices/RT/RT1064/periph/PERI_RTWDOG.h | 6 +- .../RT1160/MIMXRT1165/MIMXRT1165_cm4_COMMON.h | 6 +- .../MIMXRT1165/MIMXRT1165_cm4_features.h | 89 ++++-- .../RT1160/MIMXRT1165/MIMXRT1165_cm7_COMMON.h | 6 +- .../MIMXRT1165/MIMXRT1165_cm7_features.h | 87 ++++-- .../RT1160/MIMXRT1166/MIMXRT1166_cm4_COMMON.h | 6 +- .../MIMXRT1166/MIMXRT1166_cm4_features.h | 87 ++++-- .../RT1160/MIMXRT1166/MIMXRT1166_cm7_COMMON.h | 6 +- .../MIMXRT1166/MIMXRT1166_cm7_features.h | 87 ++++-- .../RT/RT1160/MIMXRT1166/drivers/fsl_clock.h | 90 +++++- .../devices/RT/RT1160/periph/PERI_FLEXSPI.h | 37 +-- .../devices/RT/RT1160/periph/PERI_RTWDOG.h | 6 +- .../devices/RT/RT1170/MIMXRT1171/MIMXRT1171.h | 2 +- .../RT/RT1170/MIMXRT1171/MIMXRT1171_COMMON.h | 6 +- .../RT1170/MIMXRT1171/MIMXRT1171_features.h | 89 ++++-- .../RT/RT1170/MIMXRT1171/system_MIMXRT1171.c | 4 +- .../RT/RT1170/MIMXRT1171/system_MIMXRT1171.h | 4 +- .../devices/RT/RT1170/MIMXRT1172/MIMXRT1172.h | 2 +- .../RT/RT1170/MIMXRT1172/MIMXRT1172_COMMON.h | 6 +- .../RT1170/MIMXRT1172/MIMXRT1172_features.h | 89 ++++-- .../RT/RT1170/MIMXRT1172/system_MIMXRT1172.c | 4 +- .../RT/RT1170/MIMXRT1172/system_MIMXRT1172.h | 4 +- .../RT/RT1170/MIMXRT1173/MIMXRT1173_cm4.h | 2 +- .../RT1170/MIMXRT1173/MIMXRT1173_cm4_COMMON.h | 6 +- .../MIMXRT1173/MIMXRT1173_cm4_features.h | 89 ++++-- .../RT/RT1170/MIMXRT1173/MIMXRT1173_cm7.h | 2 +- .../RT1170/MIMXRT1173/MIMXRT1173_cm7_COMMON.h | 6 +- .../MIMXRT1173/MIMXRT1173_cm7_features.h | 89 ++++-- .../RT1170/MIMXRT1173/system_MIMXRT1173_cm4.c | 4 +- .../RT1170/MIMXRT1173/system_MIMXRT1173_cm4.h | 4 +- .../RT1170/MIMXRT1173/system_MIMXRT1173_cm7.c | 4 +- .../RT1170/MIMXRT1173/system_MIMXRT1173_cm7.h | 4 +- .../RT/RT1170/MIMXRT1175/MIMXRT1175_cm4.h | 2 +- .../RT1170/MIMXRT1175/MIMXRT1175_cm4_COMMON.h | 6 +- .../MIMXRT1175/MIMXRT1175_cm4_features.h | 89 ++++-- .../RT/RT1170/MIMXRT1175/MIMXRT1175_cm7.h | 2 +- .../RT1170/MIMXRT1175/MIMXRT1175_cm7_COMMON.h | 6 +- .../MIMXRT1175/MIMXRT1175_cm7_features.h | 89 ++++-- .../RT1170/MIMXRT1175/system_MIMXRT1175_cm4.c | 4 +- .../RT1170/MIMXRT1175/system_MIMXRT1175_cm4.h | 4 +- .../RT1170/MIMXRT1175/system_MIMXRT1175_cm7.c | 4 +- .../RT1170/MIMXRT1175/system_MIMXRT1175_cm7.h | 4 +- .../RT/RT1170/MIMXRT1176/MIMXRT1176_cm4.h | 2 +- .../RT1170/MIMXRT1176/MIMXRT1176_cm4_COMMON.h | 6 +- .../MIMXRT1176/MIMXRT1176_cm4_features.h | 89 ++++-- .../RT/RT1170/MIMXRT1176/MIMXRT1176_cm7.h | 2 +- .../RT1170/MIMXRT1176/MIMXRT1176_cm7_COMMON.h | 6 +- .../MIMXRT1176/MIMXRT1176_cm7_features.h | 89 ++++-- .../RT/RT1170/MIMXRT1176/drivers/fsl_clock.h | 91 ++++++- .../MIMXRT1176/drivers/romapi/fsl_romapi.c | 29 +- .../MIMXRT1176/drivers/romapi/fsl_romapi.h | 4 +- .../RT1170/MIMXRT1176/system_MIMXRT1176_cm4.c | 4 +- .../RT1170/MIMXRT1176/system_MIMXRT1176_cm4.h | 4 +- .../RT1170/MIMXRT1176/system_MIMXRT1176_cm7.c | 4 +- .../RT1170/MIMXRT1176/system_MIMXRT1176_cm7.h | 4 +- .../devices/RT/RT1170/periph/PERI_ADC.h | 2 +- .../devices/RT/RT1170/periph/PERI_ADC_ETC.h | 2 +- .../RT/RT1170/periph/PERI_ANADIG_LDO_SNVS.h | 2 +- .../RT1170/periph/PERI_ANADIG_LDO_SNVS_DIG.h | 2 +- .../RT/RT1170/periph/PERI_ANADIG_MISC.h | 2 +- .../RT/RT1170/periph/PERI_ANADIG_OSC.h | 2 +- .../RT/RT1170/periph/PERI_ANADIG_PLL.h | 2 +- .../RT/RT1170/periph/PERI_ANADIG_PMU.h | 2 +- .../RT/RT1170/periph/PERI_ANADIG_TEMPSENSOR.h | 2 +- .../devices/RT/RT1170/periph/PERI_AOI.h | 2 +- .../devices/RT/RT1170/periph/PERI_ASRC.h | 2 +- .../devices/RT/RT1170/periph/PERI_AUDIO_PLL.h | 2 +- .../devices/RT/RT1170/periph/PERI_CAAM.h | 2 +- .../devices/RT/RT1170/periph/PERI_CAN.h | 2 +- .../RT/RT1170/periph/PERI_CAN_WRAPPER.h | 2 +- .../devices/RT/RT1170/periph/PERI_CCM.h | 2 +- .../devices/RT/RT1170/periph/PERI_CCM_OBS.h | 2 +- .../devices/RT/RT1170/periph/PERI_CDOG.h | 2 +- .../devices/RT/RT1170/periph/PERI_CMP.h | 2 +- .../devices/RT/RT1170/periph/PERI_CSI.h | 2 +- .../devices/RT/RT1170/periph/PERI_DAC.h | 2 +- .../devices/RT/RT1170/periph/PERI_DCDC.h | 2 +- .../devices/RT/RT1170/periph/PERI_DCIC.h | 2 +- .../devices/RT/RT1170/periph/PERI_DMA.h | 2 +- .../devices/RT/RT1170/periph/PERI_DMAMUX.h | 2 +- .../devices/RT/RT1170/periph/PERI_DSI_HOST.h | 2 +- .../RT1170/periph/PERI_DSI_HOST_APB_PKT_IF.h | 2 +- .../RT1170/periph/PERI_DSI_HOST_DPI_INTFC.h | 2 +- .../PERI_DSI_HOST_NXP_FDSOI28_DPHY_INTFC.h | 2 +- .../devices/RT/RT1170/periph/PERI_EMVSIM.h | 2 +- .../devices/RT/RT1170/periph/PERI_ENC.h | 7 +- .../devices/RT/RT1170/periph/PERI_ENET.h | 2 +- .../devices/RT/RT1170/periph/PERI_ENET_QOS.h | 2 +- .../RT/RT1170/periph/PERI_ETHERNET_PLL.h | 2 +- .../devices/RT/RT1170/periph/PERI_EWM.h | 2 +- .../devices/RT/RT1170/periph/PERI_FLEXIO.h | 2 +- .../devices/RT/RT1170/periph/PERI_FLEXRAM.h | 2 +- .../devices/RT/RT1170/periph/PERI_FLEXSPI.h | 37 +-- .../RT/RT1170/periph/PERI_GPC_CPU_MODE_CTRL.h | 2 +- .../RT1170/periph/PERI_GPC_SET_POINT_CTRL.h | 2 +- .../RT/RT1170/periph/PERI_GPC_STBY_CTRL.h | 2 +- .../devices/RT/RT1170/periph/PERI_GPIO.h | 2 +- .../devices/RT/RT1170/periph/PERI_GPT.h | 2 +- .../devices/RT/RT1170/periph/PERI_I2S.h | 2 +- .../devices/RT/RT1170/periph/PERI_IEE.h | 2 +- .../devices/RT/RT1170/periph/PERI_IEE_APC.h | 2 +- .../devices/RT/RT1170/periph/PERI_IOMUXC.h | 2 +- .../RT/RT1170/periph/PERI_IOMUXC_GPR.h | 2 +- .../RT/RT1170/periph/PERI_IOMUXC_LPSR.h | 2 +- .../RT/RT1170/periph/PERI_IOMUXC_LPSR_GPR.h | 2 +- .../RT/RT1170/periph/PERI_IOMUXC_SNVS.h | 2 +- .../RT/RT1170/periph/PERI_IOMUXC_SNVS_GPR.h | 2 +- .../RT/RT1170/periph/PERI_IPS_DOMAIN.h | 2 +- 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.../MIMXRT735S_cm33_core0_features.h | 51 +++- .../RT700/MIMXRT735S/MIMXRT735S_cm33_core1.h | 20 +- .../MIMXRT735S/MIMXRT735S_cm33_core1_COMMON.h | 57 +++- .../MIMXRT735S_cm33_core1_features.h | 51 +++- .../RT/RT700/MIMXRT735S/MIMXRT735S_ezhv.h | 17 +- .../RT700/MIMXRT735S/MIMXRT735S_ezhv_COMMON.h | 28 +- .../MIMXRT735S/MIMXRT735S_ezhv_features.h | 51 +++- .../RT/RT700/MIMXRT735S/MIMXRT735S_hifi1.h | 17 +- .../MIMXRT735S/MIMXRT735S_hifi1_COMMON.h | 47 +++- .../MIMXRT735S/MIMXRT735S_hifi1_features.h | 51 +++- .../RT700/MIMXRT735S/fsl_device_registers.h | 8 +- .../startup_MIMXRT735S_cm33_core0.c | 12 +- .../startup_MIMXRT735S_cm33_core0.cpp | 12 +- .../startup_MIMXRT735S_cm33_core1.c | 12 +- .../startup_MIMXRT735S_cm33_core1.cpp | 12 +- .../MIMXRT735S/system_MIMXRT735S_cm33_core0.c | 73 ++++- .../MIMXRT735S/system_MIMXRT735S_cm33_core0.h | 17 +- .../MIMXRT735S/system_MIMXRT735S_cm33_core1.c | 17 +- .../MIMXRT735S/system_MIMXRT735S_cm33_core1.h | 17 +- .../RT700/MIMXRT735S/system_MIMXRT735S_ezhv.c | 14 +- .../RT700/MIMXRT735S/system_MIMXRT735S_ezhv.h | 14 +- .../MIMXRT735S/system_MIMXRT735S_hifi1.c | 14 +- .../MIMXRT735S/system_MIMXRT735S_hifi1.h | 14 +- .../RT700/MIMXRT758S/MIMXRT758S_cm33_core0.h | 19 +- .../MIMXRT758S/MIMXRT758S_cm33_core0_COMMON.h | 24 +- .../MIMXRT758S_cm33_core0_features.h | 28 +- .../RT700/MIMXRT758S/MIMXRT758S_cm33_core1.h | 19 +- .../MIMXRT758S/MIMXRT758S_cm33_core1_COMMON.h | 24 +- .../MIMXRT758S_cm33_core1_features.h | 28 +- .../RT/RT700/MIMXRT758S/MIMXRT758S_ezhv.h | 16 +- .../RT700/MIMXRT758S/MIMXRT758S_ezhv_COMMON.h | 18 +- .../MIMXRT758S/MIMXRT758S_ezhv_features.h | 28 +- .../RT/RT700/MIMXRT758S/MIMXRT758S_hifi1.h | 16 +- .../MIMXRT758S/MIMXRT758S_hifi1_COMMON.h | 18 +- .../MIMXRT758S/MIMXRT758S_hifi1_features.h | 28 +- .../RT700/MIMXRT758S/fsl_device_registers.h | 8 +- .../startup_MIMXRT758S_cm33_core0.c | 2 +- .../startup_MIMXRT758S_cm33_core0.cpp | 2 +- .../startup_MIMXRT758S_cm33_core1.c | 2 +- .../startup_MIMXRT758S_cm33_core1.cpp | 2 +- .../MIMXRT758S/system_MIMXRT758S_cm33_core0.c | 73 ++++- .../MIMXRT758S/system_MIMXRT758S_cm33_core0.h | 17 +- .../MIMXRT758S/system_MIMXRT758S_cm33_core1.c | 17 +- .../MIMXRT758S/system_MIMXRT758S_cm33_core1.h | 17 +- .../RT700/MIMXRT758S/system_MIMXRT758S_ezhv.c | 14 +- .../RT700/MIMXRT758S/system_MIMXRT758S_ezhv.h | 14 +- .../MIMXRT758S/system_MIMXRT758S_hifi1.c | 14 +- .../MIMXRT758S/system_MIMXRT758S_hifi1.h | 14 +- .../RT700/MIMXRT798S/MIMXRT798S_cm33_core0.h | 19 +- .../MIMXRT798S/MIMXRT798S_cm33_core0_COMMON.h | 24 +- .../MIMXRT798S_cm33_core0_features.h | 28 +- .../RT700/MIMXRT798S/MIMXRT798S_cm33_core1.h | 19 +- .../MIMXRT798S/MIMXRT798S_cm33_core1_COMMON.h | 24 +- .../MIMXRT798S_cm33_core1_features.h | 28 +- .../RT/RT700/MIMXRT798S/MIMXRT798S_ezhv.h | 16 +- .../RT700/MIMXRT798S/MIMXRT798S_ezhv_COMMON.h | 18 +- .../MIMXRT798S/MIMXRT798S_ezhv_features.h | 28 +- .../RT/RT700/MIMXRT798S/MIMXRT798S_hifi1.h | 16 +- .../MIMXRT798S/MIMXRT798S_hifi1_COMMON.h | 18 +- .../MIMXRT798S/MIMXRT798S_hifi1_features.h | 28 +- .../RT/RT700/MIMXRT798S/MIMXRT798S_hifi4.h | 16 +- .../MIMXRT798S/MIMXRT798S_hifi4_COMMON.h | 18 +- .../MIMXRT798S/MIMXRT798S_hifi4_features.h | 28 +- .../MIMXRT798S/drivers/CMakeLists_clock.txt | 2 +- .../MIMXRT798S/drivers/CMakeLists_ezhv.txt | 2 +- .../MIMXRT798S/drivers/CMakeLists_power.txt | 2 +- .../MIMXRT798S/drivers/CMakeLists_pvts.txt | 2 +- .../RT/RT700/MIMXRT798S/drivers/fsl_clock.c | 246 +++++++++++++++-- .../RT/RT700/MIMXRT798S/drivers/fsl_clock.h | 126 ++++++--- .../RT/RT700/MIMXRT798S/drivers/fsl_ezhv.c | 6 +- .../RT/RT700/MIMXRT798S/drivers/fsl_ezhv.h | 10 +- .../drivers/fsl_inputmux_connections.h | 18 ++ .../RT/RT700/MIMXRT798S/drivers/fsl_iopctl.h | 6 +- .../RT/RT700/MIMXRT798S/drivers/fsl_power.c | 59 +++- .../RT/RT700/MIMXRT798S/drivers/fsl_power.h | 15 +- .../RT/RT700/MIMXRT798S/drivers/fsl_pvts.c | 14 +- .../RT/RT700/MIMXRT798S/drivers/fsl_pvts.h | 4 +- .../RT/RT700/MIMXRT798S/drivers/fsl_reset.h | 4 +- .../drivers/romapi/bootloader/fsl_romapi.h | 17 +- .../RT700/MIMXRT798S/fsl_device_registers.h | 10 +- .../startup_MIMXRT798S_cm33_core0.c | 2 +- .../startup_MIMXRT798S_cm33_core0.cpp | 2 +- .../startup_MIMXRT798S_cm33_core1.c | 2 +- .../startup_MIMXRT798S_cm33_core1.cpp | 2 +- .../MIMXRT798S/system_MIMXRT798S_cm33_core0.c | 73 ++++- .../MIMXRT798S/system_MIMXRT798S_cm33_core0.h | 17 +- .../MIMXRT798S/system_MIMXRT798S_cm33_core1.c | 17 +- .../MIMXRT798S/system_MIMXRT798S_cm33_core1.h | 17 +- .../RT700/MIMXRT798S/system_MIMXRT798S_ezhv.c | 14 +- .../RT700/MIMXRT798S/system_MIMXRT798S_ezhv.h | 14 +- .../MIMXRT798S/system_MIMXRT798S_hifi1.c | 14 +- .../MIMXRT798S/system_MIMXRT798S_hifi1.h | 14 +- .../MIMXRT798S/system_MIMXRT798S_hifi4.c | 14 +- .../MIMXRT798S/system_MIMXRT798S_hifi4.h | 14 +- .../devices/RT/RT700/periph/PERI_ADC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_AHBSC0.h | 88 +++--- .../devices/RT/RT700/periph/PERI_AHBSC3.h | 88 +++--- .../devices/RT/RT700/periph/PERI_AHBSC4.h | 88 +++--- .../RT/RT700/periph/PERI_CACHE64_CTRL.h | 88 +++--- .../RT/RT700/periph/PERI_CACHE64_POLSEL.h | 88 +++--- .../devices/RT/RT700/periph/PERI_CDOG.h | 88 +++--- .../devices/RT/RT700/periph/PERI_CLKCTL0.h | 112 +++++--- .../devices/RT/RT700/periph/PERI_CLKCTL1.h | 112 +++++--- .../devices/RT/RT700/periph/PERI_CLKCTL2.h | 88 +++--- .../devices/RT/RT700/periph/PERI_CLKCTL3.h | 142 ++++------ .../devices/RT/RT700/periph/PERI_CLKCTL4.h | 88 +++--- .../devices/RT/RT700/periph/PERI_CMP.h | 88 +++--- .../devices/RT/RT700/periph/PERI_CRC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_CTIMER.h | 88 +++--- .../RT/RT700/periph/PERI_DEBUG_MAILBOX.h | 88 +++--- .../devices/RT/RT700/periph/PERI_DMA.h | 102 +++---- .../devices/RT/RT700/periph/PERI_ELS.h | 88 +++--- .../devices/RT/RT700/periph/PERI_FLEXIO.h | 88 +++--- .../devices/RT/RT700/periph/PERI_FREQME.h | 88 +++--- .../devices/RT/RT700/periph/PERI_FRO.h | 88 +++--- .../devices/RT/RT700/periph/PERI_GDET.h | 88 +++--- .../devices/RT/RT700/periph/PERI_GLIKEY.h | 88 +++--- .../devices/RT/RT700/periph/PERI_GPIO.h | 88 +++--- .../devices/RT/RT700/periph/PERI_I2S.h | 90 +++--- .../devices/RT/RT700/periph/PERI_I3C.h | 88 +++--- .../devices/RT/RT700/periph/PERI_INPUTMUX0.h | 88 +++--- .../devices/RT/RT700/periph/PERI_INPUTMUX1.h | 88 +++--- .../devices/RT/RT700/periph/PERI_IOPCTL0.h | 88 +++--- .../devices/RT/RT700/periph/PERI_IOPCTL1.h | 88 +++--- .../devices/RT/RT700/periph/PERI_IOPCTL2.h | 88 +++--- .../devices/RT/RT700/periph/PERI_ITRC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_JPEGDEC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_JPGDECWRP.h | 88 +++--- .../devices/RT/RT700/periph/PERI_LCDIF.h | 88 +++--- .../devices/RT/RT700/periph/PERI_LPI2C.h | 88 +++--- .../devices/RT/RT700/periph/PERI_LPSPI.h | 88 +++--- .../devices/RT/RT700/periph/PERI_LPUART.h | 88 +++--- .../RT/RT700/periph/PERI_LP_FLEXCOMM.h | 88 +++--- .../RT/RT700/periph/PERI_MIPI_DSI_HOST.h | 88 +++--- .../devices/RT/RT700/periph/PERI_MMU.h | 88 +++--- .../devices/RT/RT700/periph/PERI_MRT.h | 88 +++--- .../devices/RT/RT700/periph/PERI_MU.h | 88 +++--- .../devices/RT/RT700/periph/PERI_NIC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_OCOTP.h | 88 +++--- .../devices/RT/RT700/periph/PERI_OSC32KNP.h | 88 +++--- .../devices/RT/RT700/periph/PERI_OSCCA.h | 88 +++--- .../devices/RT/RT700/periph/PERI_OSTIMER.h | 88 +++--- .../devices/RT/RT700/periph/PERI_PDM.h | 88 +++--- .../devices/RT/RT700/periph/PERI_PINT.h | 88 +++--- .../devices/RT/RT700/periph/PERI_PKC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_PMC.h | 130 ++++----- .../devices/RT/RT700/periph/PERI_PNGDEC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_PUF.h | 111 ++++---- .../devices/RT/RT700/periph/PERI_PVTS.h | 88 +++--- .../devices/RT/RT700/periph/PERI_ROMCP.h | 88 +++--- .../devices/RT/RT700/periph/PERI_RSTCTL0.h | 88 +++--- .../devices/RT/RT700/periph/PERI_RSTCTL1.h | 88 +++--- .../devices/RT/RT700/periph/PERI_RSTCTL2.h | 88 +++--- .../devices/RT/RT700/periph/PERI_RSTCTL3.h | 88 +++--- .../devices/RT/RT700/periph/PERI_RSTCTL4.h | 88 +++--- .../devices/RT/RT700/periph/PERI_RTC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_SCT.h | 88 +++--- .../devices/RT/RT700/periph/PERI_SDADC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_SEMA42.h | 88 +++--- .../devices/RT/RT700/periph/PERI_SLEEPCON0.h | 88 +++--- .../devices/RT/RT700/periph/PERI_SLEEPCON1.h | 88 +++--- .../devices/RT/RT700/periph/PERI_SYSCON0.h | 257 ++++++++++++++---- .../devices/RT/RT700/periph/PERI_SYSCON1.h | 92 ++++--- .../devices/RT/RT700/periph/PERI_SYSCON2.h | 88 +++--- .../devices/RT/RT700/periph/PERI_SYSCON3.h | 120 +++++--- .../devices/RT/RT700/periph/PERI_SYSCON4.h | 88 +++--- .../devices/RT/RT700/periph/PERI_SYSPM.h | 88 +++--- .../devices/RT/RT700/periph/PERI_TRNG.h | 88 +++--- .../devices/RT/RT700/periph/PERI_USB.h | 88 +++--- .../devices/RT/RT700/periph/PERI_USBHSDCD.h | 88 +++--- .../devices/RT/RT700/periph/PERI_USBNC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_USBPHY.h | 88 +++--- .../devices/RT/RT700/periph/PERI_USDHC.h | 88 +++--- .../devices/RT/RT700/periph/PERI_UTICK.h | 88 +++--- .../devices/RT/RT700/periph/PERI_WWDT.h | 88 +++--- .../devices/RT/RT700/periph/PERI_XCACHE.h | 88 +++--- .../devices/RT/RT700/periph/PERI_XSPI.h | 202 +++++++------- 598 files changed, 9493 insertions(+), 6293 deletions(-) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1010/MIMXRT1011/MIMXRT1011_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1010/MIMXRT1011/MIMXRT1011_COMMON.h index 93ed27be8..0dcddcaa1 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1010/MIMXRT1011/MIMXRT1011_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1010/MIMXRT1011/MIMXRT1011_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1010RM Rev.1, 10/2021 | IMXRT1010SRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1011 @@ -393,9 +393,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -659,6 +659,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SNVS - Peripheral instance base addresses */ /** Peripheral SNVS base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1010/MIMXRT1011/MIMXRT1011_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1010/MIMXRT1011/MIMXRT1011_features.h index bd0c5893e..0e7e6a0bb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1010/MIMXRT1011/MIMXRT1011_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1010/MIMXRT1011/MIMXRT1011_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2019-08-01 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -206,8 +206,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -236,6 +234,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -270,12 +270,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -362,8 +394,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -406,6 +436,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -444,6 +478,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -473,6 +509,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -483,8 +521,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -515,14 +551,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SNVS module features */ @@ -535,6 +575,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1010/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1010/periph/PERI_FLEXSPI.h index a4491ff78..5c2277648 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1010/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1010/periph/PERI_FLEXSPI.h @@ -4,7 +4,7 @@ ** MIMXRT1011DAE5A ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -92,11 +92,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 4u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -111,11 +111,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[48]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -126,7 +126,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -560,9 +560,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) - /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ @@ -572,9 +569,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ @@ -616,9 +610,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ @@ -668,9 +659,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ @@ -828,9 +816,6 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status Register 0 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1010/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1010/periph/PERI_RTWDOG.h index 38364b1a3..326b92189 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1010/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1010/periph/PERI_RTWDOG.h @@ -4,7 +4,7 @@ ** MIMXRT1011DAE5A ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG @@ -271,10 +271,6 @@ typedef struct { * @} */ /* end of group RTWDOG_Register_Masks */ -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1015/MIMXRT1015/MIMXRT1015_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1015/MIMXRT1015/MIMXRT1015_COMMON.h index 205f274e4..77926ec1e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1015/MIMXRT1015/MIMXRT1015_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1015/MIMXRT1015/MIMXRT1015_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: IMXRT1015RM Rev.1, 02/2021 | IMXRT102XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1015 @@ -485,9 +485,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -750,6 +750,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SNVS - Peripheral instance base addresses */ /** Peripheral SNVS base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1015/MIMXRT1015/MIMXRT1015_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1015/MIMXRT1015/MIMXRT1015_features.h index 9c1d71854..cf0f8c84f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1015/MIMXRT1015/MIMXRT1015_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1015/MIMXRT1015/MIMXRT1015_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2019-02-20 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -227,8 +227,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -257,6 +255,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -291,12 +291,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -383,8 +415,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -427,6 +457,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -454,6 +488,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -483,6 +519,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -493,8 +531,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -526,14 +562,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SNVS module features */ @@ -546,6 +586,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1015/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1015/periph/PERI_FLEXSPI.h index 390fedefd..e53b8455b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1015/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1015/periph/PERI_FLEXSPI.h @@ -6,7 +6,7 @@ ** MIMXRT1015DAF5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -96,11 +96,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 4u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -115,11 +115,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[48]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -130,7 +130,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -544,9 +544,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) - /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ @@ -556,9 +553,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ @@ -600,9 +594,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ @@ -652,9 +643,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ @@ -812,9 +800,6 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status Register 0 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1015/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1015/periph/PERI_RTWDOG.h index 5904a78d2..141c4543b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1015/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1015/periph/PERI_RTWDOG.h @@ -6,7 +6,7 @@ ** MIMXRT1015DAF5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG @@ -275,10 +275,6 @@ typedef struct { * @} */ /* end of group RTWDOG_Register_Masks */ -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021.h index 32a05aa5e..71ed56c99 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021.h @@ -17,7 +17,7 @@ ** ** Reference manual: IMXRT1020RM Rev.2, 01/2021 | IMXRT102XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1021 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021_COMMON.h index 337ce84d4..eb08106b4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021_COMMON.h @@ -17,7 +17,7 @@ ** ** Reference manual: IMXRT1020RM Rev.2, 01/2021 | IMXRT102XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1021 @@ -572,9 +572,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -873,6 +873,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021_features.h index 28a21baba..95645c73a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/MIMXRT1021_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-11-16 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -219,6 +219,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -338,13 +340,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -356,8 +358,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -386,6 +386,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -420,12 +422,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -512,8 +546,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -556,6 +588,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -583,6 +619,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -612,6 +650,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -622,8 +662,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -655,14 +693,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -688,14 +730,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (0) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -706,6 +740,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (0) /* SNVS module features */ @@ -718,6 +760,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/system_MIMXRT1021.c b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/system_MIMXRT1021.c index 3327ad21e..6e86c06a5 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/system_MIMXRT1021.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/system_MIMXRT1021.c @@ -17,7 +17,7 @@ ** ** Reference manual: IMXRT1020RM Rev.2, 01/2021 | IMXRT102XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/system_MIMXRT1021.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/system_MIMXRT1021.h index d0070277c..19dc21658 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/system_MIMXRT1021.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1021/system_MIMXRT1021.h @@ -17,7 +17,7 @@ ** ** Reference manual: IMXRT1020RM Rev.2, 01/2021 | IMXRT102XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024.h index 64294cd9c..66b21a210 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024.h @@ -13,7 +13,7 @@ ** ** Reference manual: IMXRT1024RM Rev.1, 02/2021 | IMXRT102XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1024 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024_COMMON.h index b18882730..d9363636b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: IMXRT1024RM Rev.1, 02/2021 | IMXRT102XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1024 @@ -568,9 +568,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -869,6 +869,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024_features.h index 24463b5fc..62203e357 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/MIMXRT1024_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2020-01-15 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -217,6 +217,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -336,13 +338,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -354,8 +356,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -384,6 +384,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -418,12 +420,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -510,8 +544,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -554,6 +586,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -581,6 +617,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -610,6 +648,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -620,8 +660,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -653,14 +691,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -686,14 +728,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (0) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -704,6 +738,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (0) /* SNVS module features */ @@ -716,6 +758,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/system_MIMXRT1024.c b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/system_MIMXRT1024.c index a13500f96..c9d329592 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/system_MIMXRT1024.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/system_MIMXRT1024.c @@ -13,7 +13,7 @@ ** ** Reference manual: IMXRT1024RM Rev.1, 02/2021 | IMXRT102XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -46,7 +46,7 @@ /*! * @file MIMXRT1024 * @version 1.0 - * @date 210525 + * @date 290525 * @brief Device specific configuration file for MIMXRT1024 (implementation file) * * Provides a system configuration function and a global variable that contains @@ -109,7 +109,7 @@ void SystemInit (void) { { *dstAddr++ = *srcAddr++; } - + flexspi_nor_config[12] = 1U; /* kFLEXSPIReadSampleClk_LoopbackFromDqsPad */ flexspi_nor_config[70] = 7U; /* kFLEXSPISerialClk_133MHz */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/system_MIMXRT1024.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/system_MIMXRT1024.h index 353b30ba2..00ad4696e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/system_MIMXRT1024.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/system_MIMXRT1024.h @@ -13,7 +13,7 @@ ** ** Reference manual: IMXRT1024RM Rev.1, 02/2021 | IMXRT102XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -46,7 +46,7 @@ /*! * @file MIMXRT1024 * @version 1.0 - * @date 2025-05-21 + * @date 2025-05-29 * @brief Device specific configuration file for MIMXRT1024 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ADC.h index a8db748c2..e846b9b81 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ADC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ADC_ETC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ADC_ETC.h index afa73533d..d954234a8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ADC_ETC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ADC_ETC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC_ETC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_AIPSTZ.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_AIPSTZ.h index 36a181c07..36a5088e8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_AIPSTZ.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_AIPSTZ.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for AIPSTZ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_AOI.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_AOI.h index 2d28a75c1..768121a26 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_AOI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_AOI.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for AOI diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_BEE.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_BEE.h index 8d0bc3651..0cce4fea1 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_BEE.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_BEE.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for BEE diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CAN.h index 20d125205..3724f2bd3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CAN.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CCM.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CCM.h index 1beea0c6a..48b657d0b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CCM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CCM.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CCM_ANALOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CCM_ANALOG.h index 00a16fe01..d0e31976f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CCM_ANALOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CCM_ANALOG.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCM_ANALOG diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CM7_MCM.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CM7_MCM.h index b8e5a747b..f13b24c07 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CM7_MCM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CM7_MCM.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for CM7_MCM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CMP.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CMP.h index 629998134..f87a1b178 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CMP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CMP.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CSU.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CSU.h index e507b5f38..ba0e59b23 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CSU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_CSU.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for CSU diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DCDC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DCDC.h index ec90deea3..f76355932 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DCDC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DCDC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCDC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DCP.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DCP.h index 8f93155a5..89eb85332 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DCP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DCP.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DMA.h index 2752290a9..6e6506ffb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DMA.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DMAMUX.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DMAMUX.h index 68c3d9a1d..a6710e05f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DMAMUX.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_DMAMUX.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMAMUX diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ENC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ENC.h index 845df91e8..c8010067d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ENC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ENC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ENET.h index a51205306..90f86602d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_ENET.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_EWM.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_EWM.h index fa65531ba..6682ef0b3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_EWM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_EWM.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for EWM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXIO.h index 14b958dd3..007feab07 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXIO.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXRAM.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXRAM.h index 4c508c5c7..b42df0bbf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXRAM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXRAM.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXRAM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXSPI.h index 48c5e4580..0361149e3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_FLEXSPI.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -104,11 +104,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 4u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -123,11 +123,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[48]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -138,7 +138,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -552,9 +552,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) - /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ @@ -564,9 +561,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ @@ -608,9 +602,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ @@ -660,9 +651,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ @@ -820,9 +808,6 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status Register 0 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPC.h index 290d09777..84c7899b7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPIO.h index 2730ec8a6..a1886de45 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPIO.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPT.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPT.h index 439f84e68..4730411c8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_GPT.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPT diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_I2S.h index e9d4f4191..639989a35 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_I2S.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC.h index 55e3df7d6..c0cf072fa 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_GPR.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_GPR.h index ea6688eab..b6807f847 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_GPR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_GPR.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_GPR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_SNVS.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_SNVS.h index 53ba1c82e..4d1d0de8f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_SNVS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_SNVS.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_SNVS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_SNVS_GPR.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_SNVS_GPR.h index b90cd5352..21afbe897 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_SNVS_GPR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_IOMUXC_SNVS_GPR.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_SNVS_GPR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_KPP.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_KPP.h index 549bcf70a..d35525477 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_KPP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_KPP.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for KPP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPI2C.h index 4d0a5dc17..455da1bdb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPI2C.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPSPI.h index af4a81b9e..bf8788d48 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPSPI.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPUART.h index 26d16437c..a2de9ee74 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_LPUART.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_OCOTP.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_OCOTP.h index 789b2f46c..cd82169bb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_OCOTP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_OCOTP.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for OCOTP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PGC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PGC.h index a94a0dff7..31c8b2753 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PGC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PGC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for PGC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PIT.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PIT.h index 9833a2f1a..4275a87c5 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PIT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PIT.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for PIT diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PMU.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PMU.h index 37a87e554..c7ffe4320 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PMU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PMU.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for PMU diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PWM.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PWM.h index acc019c23..06689219e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PWM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_PWM.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for PWM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_RTWDOG.h index 32d48307d..9a6d7efad 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_RTWDOG.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG @@ -283,10 +283,6 @@ typedef struct { * @} */ /* end of group RTWDOG_Register_Masks */ -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SEMC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SEMC.h index 12de9d9f2..d0b64ab6d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SEMC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SEMC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SNVS.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SNVS.h index e05db2531..3790b3134 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SNVS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SNVS.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for SNVS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SPDIF.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SPDIF.h index 28d34599d..437ff12a8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SPDIF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SPDIF.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPDIF diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SRC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SRC.h index 52c0c5d77..a1cc7f361 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SRC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_SRC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TEMPMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TEMPMON.h index 1346d74e2..f41955c2f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TEMPMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TEMPMON.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for TEMPMON diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TMR.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TMR.h index 04d223fd3..e163e06b4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TMR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TMR.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TRNG.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TRNG.h index 278509198..34c7eec64 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TRNG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_TRNG.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRNG diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USB.h index 1abc12854..4285cc740 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USB.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USBNC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USBNC.h index fc2925ea1..8f7ebe596 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USBNC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USBNC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBNC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USBPHY.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USBPHY.h index eda2f33c3..da517aaa8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USBPHY.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USBPHY.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBPHY diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USB_ANALOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USB_ANALOG.h index 5fe0dba03..710278f4c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USB_ANALOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USB_ANALOG.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB_ANALOG diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USDHC.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USDHC.h index a160ccdbe..273dafff9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USDHC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_USDHC.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for USDHC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_WDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_WDOG.h index 5603939d8..4de12a20d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_WDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_WDOG.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for WDOG diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XBARA.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XBARA.h index ec58d280a..9e2773427 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XBARA.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XBARA.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBARA diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XBARB.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XBARB.h index 9578fe472..996b0d4f0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XBARB.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XBARB.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBARB diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XTALOSC24M.h b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XTALOSC24M.h index e9a2b3e66..ceb5f9da9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XTALOSC24M.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1020/periph/PERI_XTALOSC24M.h @@ -14,7 +14,7 @@ ** MIMXRT1024DAG5B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250521 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for XTALOSC24M diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1041/MIMXRT1041_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1041/MIMXRT1041_COMMON.h index c0e2529cf..93e010e56 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1041/MIMXRT1041_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1041/MIMXRT1041_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: IMXRT1040RM Rev.1, 09/2022 ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1041 @@ -606,9 +606,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -619,7 +619,7 @@ typedef enum IRQn { #define FlexSPI_ATDF_BASE (0x7F800000u) /* FlexSPI2 AMBA address. */ #define FlexSPI2_AMBA_BASE (0x70000000u) -/* FlexSPI ASFM address. */ +/* FlexSPI2 ASFM address. */ #define FlexSPI2_ASFM_BASE (0x70000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ #define FlexSPI2_ARDF_BASE (0x7F400000u) @@ -928,6 +928,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1041/MIMXRT1041_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1041/MIMXRT1041_features.h index 672cb7e2f..3e225c31b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1041/MIMXRT1041_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1041/MIMXRT1041_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-07-20 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -187,7 +187,7 @@ /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ -#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ @@ -230,6 +230,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -349,13 +351,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -367,8 +369,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -397,6 +397,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -431,12 +433,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -523,8 +557,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -567,6 +599,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -594,6 +630,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMU module features */ @@ -628,6 +666,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -638,8 +678,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -671,14 +709,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -704,14 +746,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -722,6 +756,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -734,6 +776,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1042/MIMXRT1042_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1042/MIMXRT1042_COMMON.h index 71fd7ae47..e334799f4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1042/MIMXRT1042_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1042/MIMXRT1042_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: IMXRT1040RM Rev.1, 09/2022 ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1042 @@ -606,9 +606,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -619,7 +619,7 @@ typedef enum IRQn { #define FlexSPI_ATDF_BASE (0x7F800000u) /* FlexSPI2 AMBA address. */ #define FlexSPI2_AMBA_BASE (0x70000000u) -/* FlexSPI ASFM address. */ +/* FlexSPI2 ASFM address. */ #define FlexSPI2_ASFM_BASE (0x70000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ #define FlexSPI2_ARDF_BASE (0x7F400000u) @@ -952,6 +952,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1042/MIMXRT1042_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1042/MIMXRT1042_features.h index 42a274afa..c7f101e46 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1042/MIMXRT1042_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1042/MIMXRT1042_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-07-20 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -191,7 +191,7 @@ /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ -#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ @@ -234,6 +234,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -353,13 +355,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -371,8 +373,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -401,6 +401,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -435,12 +437,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -536,8 +570,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -580,6 +612,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -607,6 +643,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMU module features */ @@ -641,6 +679,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -670,8 +710,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -703,14 +741,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -736,14 +778,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -754,6 +788,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -766,6 +808,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1043/MIMXRT1043_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1043/MIMXRT1043_COMMON.h index c1259cb2c..6a4ef7f51 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1043/MIMXRT1043_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1043/MIMXRT1043_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1040RM Rev.1, 09/2022 ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1043 @@ -604,9 +604,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -617,7 +617,7 @@ typedef enum IRQn { #define FlexSPI_ATDF_BASE (0x7F800000u) /* FlexSPI2 AMBA address. */ #define FlexSPI2_AMBA_BASE (0x70000000u) -/* FlexSPI ASFM address. */ +/* FlexSPI2 ASFM address. */ #define FlexSPI2_ASFM_BASE (0x70000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ #define FlexSPI2_ARDF_BASE (0x7F400000u) @@ -950,6 +950,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1043/MIMXRT1043_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1043/MIMXRT1043_features.h index 143cc6846..57e43336f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1043/MIMXRT1043_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1043/MIMXRT1043_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-07-20 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -191,7 +191,7 @@ /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ -#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ @@ -234,6 +234,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -353,13 +355,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -371,8 +373,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -401,6 +401,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -435,12 +437,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -536,8 +570,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -580,6 +612,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -607,6 +643,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMU module features */ @@ -641,6 +679,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -670,8 +710,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -703,14 +741,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -736,14 +778,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -754,6 +788,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -766,6 +808,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1046/MIMXRT1046_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1046/MIMXRT1046_COMMON.h index f656916f8..015e9d335 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1046/MIMXRT1046_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1046/MIMXRT1046_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1040RM Rev.1, 09/2022 ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250813 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1046 @@ -536,15 +536,15 @@ typedef enum IRQn { /** Peripheral ENET2 base pointer */ #define ENET2 ((ENET_Type *)ENET2_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET_BASE, ENET2_BASE } +#define ENET_BASE_ADDRS { ENET_BASE, 0u, ENET2_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET, ENET2 } +#define ENET_BASE_PTRS { ENET, (ENET_Type *)0u, ENET2 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET_IRQn, ENET2_IRQn } -#define ENET_Receive_IRQS { ENET_IRQn, ENET2_IRQn } -#define ENET_Error_IRQS { ENET_IRQn, ENET2_IRQn } -#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, ENET2_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET_IRQn, ENET2_IRQn } +#define ENET_Transmit_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } +#define ENET_Receive_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } +#define ENET_Error_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } +#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, NotAvail_IRQn, ENET2_1588_Timer_IRQn } +#define ENET_Ts_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } /* EWM - Peripheral instance base addresses */ /** Peripheral EWM base address */ @@ -608,9 +608,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -621,7 +621,7 @@ typedef enum IRQn { #define FlexSPI_ATDF_BASE (0x7F800000u) /* FlexSPI2 AMBA address. */ #define FlexSPI2_AMBA_BASE (0x70000000u) -/* FlexSPI ASFM address. */ +/* FlexSPI2 ASFM address. */ #define FlexSPI2_ASFM_BASE (0x70000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ #define FlexSPI2_ARDF_BASE (0x7F400000u) @@ -934,6 +934,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1046/MIMXRT1046_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1046/MIMXRT1046_features.h index 787b8e71e..a08c41ac9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1046/MIMXRT1046_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/MIMXRT1046/MIMXRT1046_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-07-20 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -187,7 +187,7 @@ /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ -#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ @@ -230,6 +230,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -349,13 +351,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -367,8 +369,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -397,6 +397,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -431,12 +433,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -523,8 +557,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -567,6 +599,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -594,6 +630,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMU module features */ @@ -628,6 +666,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -638,8 +678,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -671,14 +709,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -704,14 +746,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -722,6 +756,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -734,6 +776,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/periph/PERI_FLEXSPI.h index 0296e8510..9c5712709 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/periph/PERI_FLEXSPI.h @@ -14,7 +14,7 @@ ** MIMXRT1046XFQ5B ** ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -102,11 +102,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 4u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -121,11 +121,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[48]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -136,7 +136,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -551,9 +551,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) - /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ @@ -563,9 +560,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ @@ -607,9 +601,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ @@ -665,9 +656,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ @@ -821,9 +809,6 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status Register 0 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1040/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1040/periph/PERI_RTWDOG.h index 184457fb7..ae874a15e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1040/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1040/periph/PERI_RTWDOG.h @@ -14,7 +14,7 @@ ** MIMXRT1046XFQ5B ** ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG @@ -281,10 +281,6 @@ typedef struct { * @} */ /* end of group RTWDOG_Register_Masks */ -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1051/MIMXRT1051_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1051/MIMXRT1051_COMMON.h index f279d735e..1c738a4ea 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1051/MIMXRT1051_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1051/MIMXRT1051_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: IMXRT1050RM Rev.5, 07/2021 | IMXRT1050SRM Rev.2 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1051 @@ -600,9 +600,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -923,6 +923,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1051/MIMXRT1051_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1051/MIMXRT1051_features.h index 83e15b44b..63837ccbf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1051/MIMXRT1051_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1051/MIMXRT1051_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2018-11-16 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -227,6 +227,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -346,13 +348,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -364,8 +366,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -394,6 +394,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -428,12 +430,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -520,8 +554,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -564,6 +596,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -591,6 +627,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMU module features */ @@ -625,6 +663,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -635,8 +675,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -668,14 +706,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -701,14 +743,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (0) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -719,6 +753,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (0) /* SNVS module features */ @@ -731,6 +773,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1052/MIMXRT1052_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1052/MIMXRT1052_COMMON.h index 08f239f56..f849f750a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1052/MIMXRT1052_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1052/MIMXRT1052_COMMON.h @@ -13,7 +13,7 @@ ** ** Reference manual: IMXRT1050RM Rev.5, 07/2021 | IMXRT1050SRM Rev.2 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1052 @@ -612,9 +612,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x7F7FFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -959,6 +959,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1052/MIMXRT1052_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1052/MIMXRT1052_features.h index e53a2e796..88ba666ba 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1052/MIMXRT1052_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1050/MIMXRT1052/MIMXRT1052_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.1, 2018-11-16 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -233,6 +233,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -352,13 +354,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -370,8 +372,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -400,6 +400,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -434,12 +436,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -535,8 +569,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -579,6 +611,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -606,6 +642,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMU module features */ @@ -640,6 +678,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -669,8 +709,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -702,14 +740,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -735,14 +777,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (0) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -753,6 +787,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (0) /* SNVS module features */ @@ -765,6 +807,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1050/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1050/periph/PERI_FLEXSPI.h index 3b4828356..bcf8616ac 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1050/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1050/periph/PERI_FLEXSPI.h @@ -11,7 +11,7 @@ ** MIMXRT105SDVL6B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -109,11 +109,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 4u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -128,11 +128,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[48]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -143,7 +143,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -540,9 +540,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) - /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ @@ -552,9 +549,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ @@ -596,9 +590,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ @@ -648,9 +639,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ @@ -805,9 +793,6 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status Register 0 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1050/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1050/periph/PERI_RTWDOG.h index 85faa2624..8aa91db52 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1050/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1050/periph/PERI_RTWDOG.h @@ -11,7 +11,7 @@ ** MIMXRT105SDVL6B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG @@ -288,10 +288,6 @@ typedef struct { * @} */ /* end of group RTWDOG_Register_Masks */ -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1061/MIMXRT1061_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1061/MIMXRT1061_COMMON.h index 4b0404ad5..bbe85fb54 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1061/MIMXRT1061_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1061/MIMXRT1061_COMMON.h @@ -18,7 +18,7 @@ ** ** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1061 @@ -625,9 +625,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -638,7 +638,7 @@ typedef enum IRQn { #define FlexSPI_ATDF_BASE (0x7F800000u) /* FlexSPI2 AMBA address. */ #define FlexSPI2_AMBA_BASE (0x70000000u) -/* FlexSPI ASFM address. */ +/* FlexSPI2 ASFM address. */ #define FlexSPI2_ASFM_BASE (0x70000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ #define FlexSPI2_ARDF_BASE (0x7F400000u) @@ -976,6 +976,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1061/MIMXRT1061_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1061/MIMXRT1061_features.h index 7d8901b24..9b1d3dbc2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1061/MIMXRT1061_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1061/MIMXRT1061_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2022-03-25 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -197,7 +197,7 @@ /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ -#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ @@ -240,6 +240,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -359,13 +361,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -377,8 +379,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -407,6 +407,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -441,12 +443,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -533,8 +567,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -577,6 +609,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -604,6 +640,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMU module features */ @@ -638,6 +676,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -648,8 +688,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -681,14 +719,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -714,14 +756,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -732,6 +766,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -744,6 +786,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1062/MIMXRT1062_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1062/MIMXRT1062_COMMON.h index f283269a1..2df1b360e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1062/MIMXRT1062_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1062/MIMXRT1062_COMMON.h @@ -19,7 +19,7 @@ ** ** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1062 @@ -638,9 +638,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -651,7 +651,7 @@ typedef enum IRQn { #define FlexSPI_ATDF_BASE (0x7F800000u) /* FlexSPI2 AMBA address. */ #define FlexSPI2_AMBA_BASE (0x70000000u) -/* FlexSPI ASFM address. */ +/* FlexSPI2 ASFM address. */ #define FlexSPI2_ASFM_BASE (0x70000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ #define FlexSPI2_ARDF_BASE (0x7F400000u) @@ -1013,6 +1013,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1062/MIMXRT1062_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1062/MIMXRT1062_features.h index fec0631df..646074916 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1062/MIMXRT1062_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1060/MIMXRT1062/MIMXRT1062_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 2.0, 2022-03-25 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -203,7 +203,7 @@ /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ -#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ @@ -246,6 +246,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -365,13 +367,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -383,8 +385,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -413,6 +413,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -447,12 +449,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -548,8 +582,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -592,6 +624,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -619,6 +655,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMU module features */ @@ -653,6 +691,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -682,8 +722,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -715,14 +753,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -748,14 +790,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -766,6 +800,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -778,6 +820,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1060/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1060/periph/PERI_FLEXSPI.h index d5bcb874e..853237a24 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1060/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1060/periph/PERI_FLEXSPI.h @@ -26,7 +26,7 @@ ** MIMXRT106SDVL6A ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -130,11 +130,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 4u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -149,11 +149,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[48]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -164,7 +164,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -579,9 +579,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) - /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ @@ -591,9 +588,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ @@ -635,9 +629,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ @@ -693,9 +684,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ @@ -850,9 +838,6 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status Register 0 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1060/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1060/periph/PERI_RTWDOG.h index 1595498f3..c91a7a8c4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1060/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1060/periph/PERI_RTWDOG.h @@ -26,7 +26,7 @@ ** MIMXRT106SDVL6A ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG @@ -309,10 +309,6 @@ typedef struct { * @} */ /* end of group RTWDOG_Register_Masks */ -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1064/MIMXRT1064/MIMXRT1064_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1064/MIMXRT1064/MIMXRT1064_COMMON.h index 53db8b313..a62cb83b3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1064/MIMXRT1064/MIMXRT1064_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1064/MIMXRT1064/MIMXRT1064_COMMON.h @@ -17,7 +17,7 @@ ** ** Reference manual: IMXRT1064RM Rev.2, 7/2021 | IMXRT106XSRM Rev.0 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1064 @@ -634,9 +634,9 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) /* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } +#define FlexSPI_AMBA_BASE_ARRAY { {0x60000000u}, {0u}, {0x70000000u} } /* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } +#define FlexSPI_AMBA_END_ARRAY { {0x6FFFFFFFu}, {0u}, {0x7EFFFFFFu} } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x60000000u) /* FlexSPI ASFM address. */ @@ -647,7 +647,7 @@ typedef enum IRQn { #define FlexSPI_ATDF_BASE (0x7F800000u) /* FlexSPI2 AMBA address. */ #define FlexSPI2_AMBA_BASE (0x70000000u) -/* FlexSPI ASFM address. */ +/* FlexSPI2 ASFM address. */ #define FlexSPI2_ASFM_BASE (0x70000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ #define FlexSPI2_ARDF_BASE (0x7F400000u) @@ -1009,6 +1009,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { RTWDOG } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMC - Peripheral instance base addresses */ /** Peripheral SEMC base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1064/MIMXRT1064/MIMXRT1064_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1064/MIMXRT1064/MIMXRT1064_features.h index 0c475d9f3..384c88861 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1064/MIMXRT1064/MIMXRT1064_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1064/MIMXRT1064/MIMXRT1064_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-11-16 -** Build: b250506 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -201,7 +201,7 @@ /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ -#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ @@ -244,6 +244,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -363,13 +365,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -381,8 +383,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -411,6 +411,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -445,12 +447,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (1024) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC module features */ @@ -546,8 +580,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -590,6 +622,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* interrupt module features */ @@ -617,6 +653,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PMU module features */ @@ -651,6 +689,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -680,8 +720,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -713,14 +751,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -746,14 +788,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (0) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (1) /* @brief If SEMC has errata 050577. */ @@ -764,6 +798,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -776,6 +818,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SRC module features */ /* @brief There is MASK_WDOG3_RST bit in SCR register. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1064/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1064/periph/PERI_FLEXSPI.h index f8caa189b..5cf318ae9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1064/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1064/periph/PERI_FLEXSPI.h @@ -10,7 +10,7 @@ ** MIMXRT1064DVL6B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -100,11 +100,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 4u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -119,11 +119,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[48]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -134,7 +134,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -548,9 +548,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) - /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ @@ -560,9 +557,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ @@ -604,9 +598,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ @@ -656,9 +647,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ @@ -816,9 +804,6 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status Register 0 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1064/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1064/periph/PERI_RTWDOG.h index 4108be86a..03447b9af 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1064/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1064/periph/PERI_RTWDOG.h @@ -10,7 +10,7 @@ ** MIMXRT1064DVL6B ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG @@ -279,10 +279,6 @@ typedef struct { * @} */ /* end of group RTWDOG_Register_Masks */ -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm4_COMMON.h index 16ddc8391..5554593f9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm4_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1160RM, Rev 0, 03/2021 ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1165_cm4 @@ -1538,6 +1538,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG4_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm4_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm4_features.h index f7ef62489..1ae7732f4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -235,6 +235,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -247,6 +249,8 @@ #define FSL_FEATURE_CDOG_HAS_NO_RESET (1) /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (0) +/* @brief CDOG Uses restart */ +#define FSL_FEATURE_CDOG_USE_RESTART (1) /* interrupt module features */ @@ -282,8 +286,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -296,6 +298,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -409,13 +413,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -427,8 +431,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -457,6 +459,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -491,12 +495,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -686,8 +722,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -730,6 +764,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -820,6 +858,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -849,6 +889,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -859,8 +901,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -893,14 +933,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -926,14 +970,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -944,6 +980,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -956,6 +1000,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm7_COMMON.h index 43c2c004c..73910675f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm7_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1160RM, Rev 0, 03/2021 ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1165_cm7 @@ -1519,6 +1519,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm7_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm7_features.h index 6f8dacdea..d52cccfea 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1165/MIMXRT1165_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -231,6 +231,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -304,8 +306,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -318,6 +318,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -431,13 +433,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -449,8 +451,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -479,6 +479,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -513,12 +515,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -695,8 +729,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -739,6 +771,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* CSI2RX module features */ @@ -824,6 +860,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -853,6 +891,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -863,8 +903,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -897,14 +935,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -930,14 +972,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -948,6 +982,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -960,6 +1002,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm4_COMMON.h index 4680c9cb5..806e11485 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm4_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1160RM, Rev 0, 03/2021 ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1166_cm4 @@ -1574,6 +1574,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG4_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm4_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm4_features.h index 93e342bc7..691a7c7db 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -241,6 +241,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -288,8 +290,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -302,6 +302,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* CSI module features */ @@ -420,13 +422,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -438,8 +440,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -468,6 +468,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -502,12 +504,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -706,8 +740,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -750,6 +782,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -840,6 +876,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -869,6 +907,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -898,8 +938,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -932,14 +970,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -965,14 +1007,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -983,6 +1017,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -995,6 +1037,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm7_COMMON.h index b7b4f6cc5..c2116f59a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm7_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1160RM, Rev 0, 03/2021 ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1166_cm7 @@ -1555,6 +1555,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm7_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm7_features.h index 1369d3c6b..fe735da45 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/MIMXRT1166_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -237,6 +237,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -310,8 +312,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -324,6 +324,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* CSI module features */ @@ -442,13 +444,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -460,8 +462,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -490,6 +490,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -524,12 +526,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -715,8 +749,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -759,6 +791,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* CSI2RX module features */ @@ -844,6 +880,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -873,6 +911,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -902,8 +942,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -936,14 +974,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -969,14 +1011,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -987,6 +1021,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -999,6 +1041,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/drivers/fsl_clock.h index 9e08a1d35..58f9cdaec 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/MIMXRT1166/drivers/fsl_clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2019-2023 NXP + * Copyright 2019-2023, 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -40,7 +40,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief CLOCK driver version. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /* Definition for delay API in clock driver, users can redefine it to the real application. */ #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY @@ -1731,6 +1731,37 @@ typedef enum _clock_pll_post_div kCLOCK_PllPostDiv1 = 3U, /*!< Divide by 1. */ } clock_pll_post_div_t; +/*! + * @brief The enumerater of clock output1's clock source. + */ +typedef enum _clock_output1_selection +{ + kCLOCK_CKO1OutputMuxOscRc48MDiv2 = 0U, /*!< CKO1 mux from MuxOscRc48MDiv2. */ + kCLOCK_CKO1OutputMuxOsc24MOut = 1U, /*!< CKO1 mux from MuxOsc24MOut. */ + kCLOCK_CKO1OutputMuxOscRc400M = 2U, /*!< CKO1 mux from MuxOscRc400M. */ + kCLOCK_CKO1OutputMuxOscRc16M = 3U, /*!< CKO1 mux from MuxOscRc16M. */ + kCLOCK_CKO1OutputMuxSysPll2Pfd2 = 4U, /*!< CKO1 mux from MuxSysPll2Pfd2. */ + kCLOCK_CKO1OutputMuxSysPll2Out = 5U, /*!< CKO1 mux from MuxSysPll2Out. */ + kkCLOCK_CKO1OutputMuxSysPll3Pfd1 = 6U, /*!< CKO1 mux from MuxSysPll3Pfd1. */ + kCLOCK_CKO1OutputMuxSysPll1Div5 = 7U, /*!< CKO1 mux from MuxSysPll1Div5. */ +} clock_output1_selection_t; + +/*! + * @brief The enumerater of clock output2's clock source. + * + */ +typedef enum _clock_output2_selection +{ + kCLOCK_CKO2OutputOscRc48MDiv2 = 0U, /*!< CKO2 mux from MuxOscRc48MDiv2. */ + kCLOCK_CKO2OutputOsc24MOut = 1U, /*!< CKO2 mux from MuxOsc24MOut. */ + kCLOCK_CKO2OutputOscRc400M = 2U, /*!< CKO2 mux from MuxOscRc400M. */ + kCLOCK_CKO2OutputOscRc16M = 3U, /*!< CKO2 mux from MuxOscRc16M. */ + kCLOCK_CKO2OutputSysPll2Pfd3 = 4U, /*!< CKO2 mux from MuxSysPll2Pfd3. */ + kCLOCK_CKO2OutputMuxOscRc48M = 5U, /*!< CKO2 mux from MuxOscRc48M. */ + kCLOCK_CKO2OutputMuxSysPll3Pfd1 = 6U, /*!< CKO2 mux from MuxSysPll3Pfd1. */ + kCLOCK_CKO2OutputMuxAudioPllOut = 7U, /*!< CKO2 mux from MuxAudioPllOut. */ +} clock_output2_selection_t; + /*! * @brief PLL configuration for ARM. * @@ -3215,6 +3246,61 @@ static inline void CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name, uint8_t dom CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_WHITE_LIST(domainId); } +/*! + * @name Clock Output Inferfaces + * @{ + */ + +/*! + * @brief Set the clock source and the divider of the clock output1. + * + * param selection The clock source to be output, please refer to clock_output1_selection_t. + * param divider The divider of the output clock signal. + */ +static inline void CLOCK_SetClockOutput1(clock_output1_selection_t selection, uint32_t divider) +{ + clock_root_config_t rootCfg = {0}; + + rootCfg.mux = selection; + rootCfg.div = divider; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); +} + +/*! + * @brief Set the clock source and the divider of the clock output2. + * + * param selection The clock source to be output, please refer to clock_output2_selection_t. + * param divider The divider of the output clock signal. + */ +static inline void CLOCK_SetClockOutput2(clock_output2_selection_t selection, uint32_t divider) +{ + clock_root_config_t rootCfg = {0}; + + rootCfg.mux = selection; + rootCfg.div = divider; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); +} + +/*! + * @brief Get the frequency of clock output1 clock signal. + * + * @return The frequency of clock output1 clock signal. + */ +static inline uint32_t CLOCK_GetClockOutCLKO1Freq(void) +{ + return CLOCK_GetRootClockFreq(kCLOCK_Root_Cko1); +} + +/*! + * @brief Get the frequency of clock output2 clock signal. + * + * @return The frequency of clock output2 clock signal. + */ +static inline uint32_t CLOCK_GetClockOutClkO2Freq(void) +{ + return CLOCK_GetRootClockFreq(kCLOCK_Root_Cko2); +} + /* @} */ #if defined(__cplusplus) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/periph/PERI_FLEXSPI.h index 9c0d85171..5ed54341a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/periph/PERI_FLEXSPI.h @@ -14,7 +14,7 @@ ** MIMXRT1166XVM5A_cm7 ** ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -102,11 +102,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 8u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 8u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -122,11 +122,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -137,7 +137,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[8]; __I uint32_t MISCCR4; /**< Misc Control Register 4, offset: 0xD0 */ __I uint32_t MISCCR5; /**< Misc Control Register 5, offset: 0xD4 */ @@ -690,9 +690,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) - /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ @@ -712,9 +709,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ @@ -756,9 +750,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ @@ -808,9 +799,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ @@ -989,9 +977,6 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name MISCCR4 - Misc Control Register 4 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1160/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1160/periph/PERI_RTWDOG.h index c36b6a8f0..81519de9d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1160/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1160/periph/PERI_RTWDOG.h @@ -14,7 +14,7 @@ ** MIMXRT1166XVM5A_cm7 ** ** Version: rev. 1.0, 2024-10-29 -** Build: b250520 +** Build: b250701 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG @@ -281,10 +281,6 @@ typedef struct { * @} */ /* end of group RTWDOG_Register_Masks */ -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171.h index 4ec0ee342..ff7ca9d67 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1171 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171_COMMON.h index 487151e33..cbd5ff9f0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171_COMMON.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1171 @@ -1524,6 +1524,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171_features.h index 9134d68bd..7ff49f6ec 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/MIMXRT1171_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -233,6 +233,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -306,8 +308,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -320,6 +320,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -397,7 +399,7 @@ /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ #define FSL_FEATURE_ENC_HAS_POSDPER (1) /* @brief Has bitfiled FILT[FILT_PRSC]. */ -#define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) +#define FSL_FEATURE_ENC_HAS_FILT_PRSC (0) /* ENET module features */ @@ -433,13 +435,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -451,8 +453,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -481,6 +481,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -515,12 +517,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -697,8 +731,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -741,6 +773,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* CSI2RX module features */ @@ -826,6 +862,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -855,6 +893,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -865,8 +905,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -899,14 +937,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -932,14 +974,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -950,6 +984,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -962,6 +1004,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/system_MIMXRT1171.c b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/system_MIMXRT1171.c index e6019c35e..f77c5e4db 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/system_MIMXRT1171.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/system_MIMXRT1171.c @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1171 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1171 (implementation file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/system_MIMXRT1171.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/system_MIMXRT1171.h index ad53e5892..3c4321923 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/system_MIMXRT1171.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1171/system_MIMXRT1171.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1171 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1171 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172.h index 9c536e7aa..b64a2af87 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1172 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172_COMMON.h index e905c784a..2c1de15d8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172_COMMON.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1172 @@ -1560,6 +1560,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172_features.h index 1819574f5..a21ad0601 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/MIMXRT1172_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -239,6 +239,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -312,8 +314,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -326,6 +326,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* CSI module features */ @@ -408,7 +410,7 @@ /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ #define FSL_FEATURE_ENC_HAS_POSDPER (1) /* @brief Has bitfiled FILT[FILT_PRSC]. */ -#define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) +#define FSL_FEATURE_ENC_HAS_FILT_PRSC (0) /* ENET module features */ @@ -444,13 +446,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -462,8 +464,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -492,6 +492,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -526,12 +528,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -717,8 +751,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -761,6 +793,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* CSI2RX module features */ @@ -846,6 +882,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -875,6 +913,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -904,8 +944,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -938,14 +976,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -971,14 +1013,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -989,6 +1023,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -1001,6 +1043,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/system_MIMXRT1172.c b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/system_MIMXRT1172.c index 8000c9d46..d95c6463c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/system_MIMXRT1172.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/system_MIMXRT1172.c @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1172 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1172 (implementation file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/system_MIMXRT1172.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/system_MIMXRT1172.h index 6118dbdbe..4a05e4bf1 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/system_MIMXRT1172.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1172/system_MIMXRT1172.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1172 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1172 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4.h index d27366aff..d31c40182 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1173_cm4 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4_COMMON.h index 505dd5e1e..aa2c4cfa4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1173_cm4 @@ -1575,6 +1575,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG4_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4_features.h index 32dfc8ff7..1cce2e623 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -243,6 +243,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -290,8 +292,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -304,6 +304,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* CSI module features */ @@ -386,7 +388,7 @@ /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ #define FSL_FEATURE_ENC_HAS_POSDPER (1) /* @brief Has bitfiled FILT[FILT_PRSC]. */ -#define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) +#define FSL_FEATURE_ENC_HAS_FILT_PRSC (0) /* ENET module features */ @@ -422,13 +424,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -440,8 +442,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -470,6 +470,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -504,12 +506,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -708,8 +742,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -752,6 +784,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -842,6 +878,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -871,6 +909,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -900,8 +940,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -934,14 +972,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -967,14 +1009,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -985,6 +1019,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -997,6 +1039,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (10) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7.h index e97a9ed3a..0b2c69b73 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1173_cm7 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7_COMMON.h index 7ed9565a0..593a03fd9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1173_cm7 @@ -1556,6 +1556,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7_features.h index a9c850cc0..dd76b5104 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/MIMXRT1173_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -239,6 +239,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -312,8 +314,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -326,6 +326,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* CSI module features */ @@ -408,7 +410,7 @@ /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ #define FSL_FEATURE_ENC_HAS_POSDPER (1) /* @brief Has bitfiled FILT[FILT_PRSC]. */ -#define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) +#define FSL_FEATURE_ENC_HAS_FILT_PRSC (0) /* ENET module features */ @@ -444,13 +446,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -462,8 +464,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -492,6 +492,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -526,12 +528,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -717,8 +751,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -761,6 +793,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* CSI2RX module features */ @@ -846,6 +882,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -875,6 +913,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -904,8 +944,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -938,14 +976,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -971,14 +1013,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -989,6 +1023,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -1001,6 +1043,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (10) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm4.c b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm4.c index 2a9b53c4f..9e26ae868 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm4.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm4.c @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -40,7 +40,7 @@ /*! * @file MIMXRT1173_cm4 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1173_cm4 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm4.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm4.h index b77cd2a98..3c57fbeec 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm4.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -40,7 +40,7 @@ /*! * @file MIMXRT1173_cm4 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1173_cm4 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm7.c b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm7.c index a8b43c10e..685ca90b8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm7.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm7.c @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -40,7 +40,7 @@ /*! * @file MIMXRT1173_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1173_cm7 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm7.h index d0a293618..5764535d5 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1173/system_MIMXRT1173_cm7.h @@ -11,7 +11,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -40,7 +40,7 @@ /*! * @file MIMXRT1173_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1173_cm7 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4.h index 4493b61d8..48cb61932 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1175_cm4 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4_COMMON.h index bdc7c4716..a15a93301 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4_COMMON.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1175_cm4 @@ -1543,6 +1543,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG4_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4_features.h index 5d710be40..9a9b665ce 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -237,6 +237,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -284,8 +286,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -298,6 +298,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -375,7 +377,7 @@ /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ #define FSL_FEATURE_ENC_HAS_POSDPER (1) /* @brief Has bitfiled FILT[FILT_PRSC]. */ -#define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) +#define FSL_FEATURE_ENC_HAS_FILT_PRSC (0) /* ENET module features */ @@ -411,13 +413,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -429,8 +431,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -459,6 +459,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -493,12 +495,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -688,8 +722,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -732,6 +764,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -822,6 +858,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -851,6 +889,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -861,8 +901,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -895,14 +933,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -928,14 +970,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -946,6 +980,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -958,6 +1000,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7.h index 92e3b710b..b29ccd15e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1175_cm7 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7_COMMON.h index d6afd5b49..496ffafde 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7_COMMON.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1175_cm7 @@ -1524,6 +1524,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7_features.h index 2777a8372..f43c7068f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/MIMXRT1175_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -233,6 +233,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -306,8 +308,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -320,6 +320,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -397,7 +399,7 @@ /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ #define FSL_FEATURE_ENC_HAS_POSDPER (1) /* @brief Has bitfiled FILT[FILT_PRSC]. */ -#define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) +#define FSL_FEATURE_ENC_HAS_FILT_PRSC (0) /* ENET module features */ @@ -433,13 +435,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -451,8 +453,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -481,6 +481,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -515,12 +517,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -697,8 +731,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -741,6 +773,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* CSI2RX module features */ @@ -826,6 +862,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -855,6 +893,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* RTWDOG module features */ @@ -865,8 +905,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -899,14 +937,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -932,14 +974,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -950,6 +984,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -962,6 +1004,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm4.c b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm4.c index 4fcb594d6..c1df9c4d6 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm4.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm4.c @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1175_cm4 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1175_cm4 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm4.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm4.h index 6ced569b4..257382efc 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm4.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1175_cm4 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1175_cm4 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm7.c b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm7.c index 0049b17c6..2d74f0549 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm7.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm7.c @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1175_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1175_cm7 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm7.h index c27088568..cfb51f0e2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1175/system_MIMXRT1175_cm7.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1175_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1175_cm7 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4.h index 04355d7b1..0709f119d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1176_cm4 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4_COMMON.h index 3323dff94..7c22cfe6d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4_COMMON.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1176_cm4 @@ -1592,6 +1592,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG4_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4_features.h index d334d9dce..339ce2362 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -245,6 +245,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -292,8 +294,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -306,6 +306,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* CSI module features */ @@ -388,7 +390,7 @@ /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ #define FSL_FEATURE_ENC_HAS_POSDPER (1) /* @brief Has bitfiled FILT[FILT_PRSC]. */ -#define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) +#define FSL_FEATURE_ENC_HAS_FILT_PRSC (0) /* ENET module features */ @@ -424,13 +426,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -447,8 +449,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -477,6 +477,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -511,12 +513,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -715,8 +749,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -759,6 +791,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MEMORY module features */ @@ -849,6 +885,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -878,6 +916,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -907,8 +947,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -941,14 +979,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -974,14 +1016,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -992,6 +1026,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -1004,6 +1046,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7.h index f3fc4dc0c..2ce7f125d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1176_cm7 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7_COMMON.h index 9451ca30a..dae79f1b9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7_COMMON.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1176_cm7 @@ -1573,6 +1573,10 @@ typedef enum IRQn { #define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } /** Interrupt vectors for the RTWDOG peripheral type */ #define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7_features.h index 7eed2c441..65703cdcf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/MIMXRT1176_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-12-29 -** Build: b250512 +** Build: b250814 ** ** Abstract: ** Chip specific module features. @@ -241,6 +241,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* CCM module features */ @@ -314,8 +316,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -328,6 +328,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* CSI module features */ @@ -410,7 +412,7 @@ /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ #define FSL_FEATURE_ENC_HAS_POSDPER (1) /* @brief Has bitfiled FILT[FILT_PRSC]. */ -#define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) +#define FSL_FEATURE_ENC_HAS_FILT_PRSC (0) /* ENET module features */ @@ -446,13 +448,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* ENET_QOS module features */ @@ -469,8 +471,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -499,6 +499,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXRAM module features */ @@ -533,12 +535,44 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPC_CPU_CTRL module features */ @@ -724,8 +758,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -768,6 +800,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* CSI2RX module features */ @@ -853,6 +889,8 @@ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) +/* @brief Has ERRATA 7914. */ +#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) /* PWM module features */ @@ -882,6 +920,8 @@ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) +/* @brief Is affected by errata with ID 51989. */ +#define FSL_FEATURE_PWM_HAS_ERRATA_51989 (0) /* PXP module features */ @@ -911,8 +951,6 @@ /* SAI module features */ -/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ -#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ @@ -945,14 +983,18 @@ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) -/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]). */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) /* @brief Support synchronous with another SAI. */ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMC module features */ @@ -978,14 +1020,6 @@ #define FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL (1) /* @brief Has read hold time feature (register bit field SRAMCR2[RDH] or SRAMCR6[RDH]). */ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) -/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ -#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) /* @brief If SEMC has errata 050577. */ @@ -996,6 +1030,14 @@ #define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* @brief SEMC supports hardware ECC on NAND flash interface. */ #define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) +/* @brief Has read hold time feature (register bit field SRAMCR0[SYNCEN] or SRAMCR4[SYNCEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITEN] or SRAMCR4[WAITEN]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITEN (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[WAITSP] or SRAMCR4[WAITSP]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_WAITSP (1) +/* @brief Has read hold time feature (register bit field SRAMCR0[ADVH] or SRAMCR4[ADVH]). */ +#define FSL_FEATURE_SEMC_HAS_SRAM_ADVH (1) /* SNVS module features */ @@ -1008,6 +1050,11 @@ /* @brief Number of TAMPER. */ #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) +/* SPDIF module features */ + +/* @brief SPDIF has no register SIC. */ +#define FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER (0) + /* SSARC_HP module features */ /* No feature definitions */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/fsl_clock.h index 3c6dc38e0..33ff185eb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/fsl_clock.h @@ -1,6 +1,5 @@ /* - * Copyright 2019-2023 NXP - * All rights reserved. + * Copyright 2019-2023, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,7 +39,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief CLOCK driver version. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 6)) +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) /* Definition for delay API in clock driver, users can redefine it to the real application. */ #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY @@ -1763,6 +1762,37 @@ typedef enum _clock_pll_post_div kCLOCK_PllPostDiv1 = 3U, /*!< Divide by 1. */ } clock_pll_post_div_t; +/*! + * @brief The enumerater of clock output1's clock source. + */ +typedef enum _clock_output1_selection +{ + kCLOCK_CKO1OutputMuxOscRc48MDiv2 = 0U, /*!< CKO1 mux from MuxOscRc48MDiv2. */ + kCLOCK_CKO1OutputMuxOsc24MOut = 1U, /*!< CKO1 mux from MuxOsc24MOut. */ + kCLOCK_CKO1OutputMuxOscRc400M = 2U, /*!< CKO1 mux from MuxOscRc400M. */ + kCLOCK_CKO1OutputMuxOscRc16M = 3U, /*!< CKO1 mux from MuxOscRc16M. */ + kCLOCK_CKO1OutputMuxSysPll2Pfd2 = 4U, /*!< CKO1 mux from MuxSysPll2Pfd2. */ + kCLOCK_CKO1OutputMuxSysPll2Out = 5U, /*!< CKO1 mux from MuxSysPll2Out. */ + kkCLOCK_CKO1OutputMuxSysPll3Pfd1 = 6U, /*!< CKO1 mux from MuxSysPll3Pfd1. */ + kCLOCK_CKO1OutputMuxSysPll1Div5 = 7U, /*!< CKO1 mux from MuxSysPll1Div5. */ +} clock_output1_selection_t; + +/*! + * @brief The enumerater of clock output2's clock source. + * + */ +typedef enum _clock_output2_selection +{ + kCLOCK_CKO2OutputOscRc48MDiv2 = 0U, /*!< CKO2 mux from MuxOscRc48MDiv2. */ + kCLOCK_CKO2OutputOsc24MOut = 1U, /*!< CKO2 mux from MuxOsc24MOut. */ + kCLOCK_CKO2OutputOscRc400M = 2U, /*!< CKO2 mux from MuxOscRc400M. */ + kCLOCK_CKO2OutputOscRc16M = 3U, /*!< CKO2 mux from MuxOscRc16M. */ + kCLOCK_CKO2OutputSysPll2Pfd3 = 4U, /*!< CKO2 mux from MuxSysPll2Pfd3. */ + kCLOCK_CKO2OutputMuxOscRc48M = 5U, /*!< CKO2 mux from MuxOscRc48M. */ + kCLOCK_CKO2OutputMuxSysPll3Pfd1 = 6U, /*!< CKO2 mux from MuxSysPll3Pfd1. */ + kCLOCK_CKO2OutputMuxAudioPllOut = 7U, /*!< CKO2 mux from MuxAudioPllOut. */ +} clock_output2_selection_t; + /*! * @brief PLL configuration for ARM. * @@ -3248,6 +3278,61 @@ static inline void CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name, uint8_t dom CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_WHITE_LIST(domainId); } +/*! + * @name Clock Output Inferfaces + * @{ + */ + +/*! + * @brief Set the clock source and the divider of the clock output1. + * + * param selection The clock source to be output, please refer to clock_output1_selection_t. + * param divider The divider of the output clock signal. + */ +static inline void CLOCK_SetClockOutput1(clock_output1_selection_t selection, uint32_t divider) +{ + clock_root_config_t rootCfg = {0}; + + rootCfg.mux = selection; + rootCfg.div = divider; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); +} + +/*! + * @brief Set the clock source and the divider of the clock output2. + * + * param selection The clock source to be output, please refer to clock_output2_selection_t. + * param divider The divider of the output clock signal. + */ +static inline void CLOCK_SetClockOutput2(clock_output2_selection_t selection, uint32_t divider) +{ + clock_root_config_t rootCfg = {0}; + + rootCfg.mux = selection; + rootCfg.div = divider; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); +} + +/*! + * @brief Get the frequency of clock output1 clock signal. + * + * @return The frequency of clock output1 clock signal. + */ +static inline uint32_t CLOCK_GetClockOutCLKO1Freq(void) +{ + return CLOCK_GetRootClockFreq(kCLOCK_Root_Cko1); +} + +/*! + * @brief Get the frequency of clock output2 clock signal. + * + * @return The frequency of clock output2 clock signal. + */ +static inline uint32_t CLOCK_GetClockOutClkO2Freq(void) +{ + return CLOCK_GetRootClockFreq(kCLOCK_Root_Cko2); +} + /* @} */ #if defined(__cplusplus) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/romapi/fsl_romapi.c b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/romapi/fsl_romapi.c index 5a52e7f2f..317c6c456 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/romapi/fsl_romapi.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/romapi/fsl_romapi.c @@ -246,22 +246,25 @@ status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance, /*! @brief Software reset for the FLEXSPI logic. */ void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance) { - uint32_t clearCacheFunctionAddress; - if (ANADIG_MISC->MISC_DIFPROG == 0x001170a0U) - { - clearCacheFunctionAddress = 0x0020426bU; - } - else if (ANADIG_MISC->MISC_DIFPROG == 0x001170b0U) - { - clearCacheFunctionAddress = 0x0021a3b7U; - } + /* + * Use Direct Manipulation of FlexSPI Instance + */ + FLEXSPI_Type* base = FLEXSPI1; + + if (instance == 1) + base = FLEXSPI1; + else if (instance == 2) + base = FLEXSPI2; else + assert(false); + + base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; + while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) { - clearCacheFunctionAddress = 0x0021a3bfU; } - clearCacheCommand_t clearCacheCommand; - MISRA_CAST(clearCacheCommand_t, clearCacheCommand, uint32_t, clearCacheFunctionAddress); - (void)clearCacheCommand(instance); + + // ISB is added here to make sure no instruction is fetched during flash reset process + __ISB(); } /*! @brief Wait until device is idle*/ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/romapi/fsl_romapi.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/romapi/fsl_romapi.h index 3bcc67e58..bbef56206 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/romapi/fsl_romapi.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/drivers/romapi/fsl_romapi.h @@ -16,7 +16,7 @@ */ /*! @brief ROM API version 1.1.2. */ -#define FSL_ROM_ROMAPI_VERSION (MAKE_VERSION(1U, 1U, 2U)) +#define FSL_ROM_ROMAPI_VERSION (MAKE_VERSION(1U, 1U, 3U)) /*! @brief ROM FLEXSPI NOR driver version 1.7.0. */ #define FSL_ROM_FLEXSPINOR_DRIVER_VERSION (MAKE_VERSION(1U, 7U, 0U)) @@ -716,7 +716,7 @@ status_t ROM_FLEXSPI_NorFlash_WaitBusy(uint32_t instance, * * @param instance storage the index of FLEXSPI. */ -void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance); +AT_QUICKACCESS_SECTION_CODE(void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance)); /*@}*/ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm4.c b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm4.c index dae76713d..45cd9c278 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm4.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm4.c @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1176_cm4 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1176_cm4 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm4.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm4.h index 707fb0e4a..830462dac 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm4.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1176_cm4 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1176_cm4 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm7.c b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm7.c index ff9169488..8aabcdeb5 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm7.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm7.c @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1176_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1176_cm7 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm7.h index 2ef601111..5ab54acdf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/MIMXRT1176/system_MIMXRT1176_cm7.h @@ -15,7 +15,7 @@ ** ** Reference manual: IMXRT1170RM, Rev 1, 02/2021 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -44,7 +44,7 @@ /*! * @file MIMXRT1176_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-03 * @brief Device specific configuration file for MIMXRT1176_cm7 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ADC.h index 6e439f775..90c565ebb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ADC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ADC_ETC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ADC_ETC.h index 375e9e0d0..fe0ad8d01 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ADC_ETC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ADC_ETC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC_ETC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_LDO_SNVS.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_LDO_SNVS.h index 7f1f93c00..c5047213e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_LDO_SNVS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_LDO_SNVS.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_LDO_SNVS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_LDO_SNVS_DIG.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_LDO_SNVS_DIG.h index d666950e7..b04882b8b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_LDO_SNVS_DIG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_LDO_SNVS_DIG.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_LDO_SNVS_DIG diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_MISC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_MISC.h index b2b8c1b21..e07ccdd44 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_MISC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_MISC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_MISC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_OSC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_OSC.h index d4dd91c84..e53eb2e34 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_OSC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_OSC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_OSC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_PLL.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_PLL.h index 38a76652d..b60e01609 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_PLL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_PLL.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_PLL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_PMU.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_PMU.h index e8d7f9a6b..b4a46cad0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_PMU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_PMU.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_PMU diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_TEMPSENSOR.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_TEMPSENSOR.h index e9c1691c3..a51f5ee60 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_TEMPSENSOR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ANADIG_TEMPSENSOR.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_TEMPSENSOR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_AOI.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_AOI.h index 4f609e51f..2e2d83873 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_AOI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_AOI.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for AOI diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ASRC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ASRC.h index f7b57255c..ec6e414f9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ASRC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ASRC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ASRC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_AUDIO_PLL.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_AUDIO_PLL.h index 13dd4da77..320002823 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_AUDIO_PLL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_AUDIO_PLL.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for AUDIO_PLL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAAM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAAM.h index c203ab308..0d825d5e9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAAM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAAM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAAM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAN.h index 43165235c..b55743f48 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAN.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAN_WRAPPER.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAN_WRAPPER.h index 15223b880..8a5936291 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAN_WRAPPER.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CAN_WRAPPER.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN_WRAPPER diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CCM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CCM.h index 04d70abda..ebc39da47 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CCM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CCM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CCM_OBS.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CCM_OBS.h index 2d4f90318..a89a82822 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CCM_OBS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CCM_OBS.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCM_OBS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CDOG.h index bf7044b18..b90ab4904 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CDOG.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for CDOG diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CMP.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CMP.h index 1812d4122..e35147456 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CMP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CMP.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CSI.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CSI.h index 56faeb9c7..6cf4d2092 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CSI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_CSI.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for CSI diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DAC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DAC.h index 83dbd678f..af0e13a94 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DAC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DAC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for DAC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DCDC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DCDC.h index 2213e3fff..c19099fd1 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DCDC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DCDC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCDC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DCIC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DCIC.h index 7817e1da4..24fee4daf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DCIC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DCIC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCIC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DMA.h index 59d020756..c2bf56351 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DMA.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DMAMUX.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DMAMUX.h index 7a09bb514..1230681c3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DMAMUX.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DMAMUX.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMAMUX diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST.h index b6661957a..170f5218e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for DSI_HOST diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_APB_PKT_IF.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_APB_PKT_IF.h index acd8bc36e..d5b7848ff 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_APB_PKT_IF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_APB_PKT_IF.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for DSI_HOST_APB_PKT_IF diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_DPI_INTFC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_DPI_INTFC.h index 18a124950..6227b0858 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_DPI_INTFC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_DPI_INTFC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for DSI_HOST_DPI_INTFC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_NXP_FDSOI28_DPHY_INTFC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_NXP_FDSOI28_DPHY_INTFC.h index 26a821de9..9dd5a5219 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_NXP_FDSOI28_DPHY_INTFC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_DSI_HOST_NXP_FDSOI28_DPHY_INTFC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for DSI_HOST_NXP_FDSOI28_DPHY_INTFC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_EMVSIM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_EMVSIM.h index 04394cc68..7b136e86b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_EMVSIM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_EMVSIM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for EMVSIM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENC.h index d2c1071ca..ff74d7da2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENC @@ -340,11 +340,6 @@ typedef struct { #define ENC_FILT_FILT_CNT_SHIFT (8U) /*! FILT_CNT - Input Filter Sample Count */ #define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) - -#define ENC_FILT_FILT_PRSC_MASK (0xE000U) -#define ENC_FILT_FILT_PRSC_SHIFT (13U) -/*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */ -#define ENC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK) /*! @} */ /*! @name WTR - Watchdog Timeout */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENET.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENET.h index a0e4084df..72573c086 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENET.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENET.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENET_QOS.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENET_QOS.h index 40a1433fd..12867ac92 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENET_QOS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ENET_QOS.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENET_QOS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ETHERNET_PLL.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ETHERNET_PLL.h index 81e428268..92d90c5e3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ETHERNET_PLL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_ETHERNET_PLL.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for ETHERNET_PLL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_EWM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_EWM.h index c72e2696e..7c373329b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_EWM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_EWM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for EWM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXIO.h index 95e151533..1a68c92a2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXIO.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXRAM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXRAM.h index 45a7bfc87..0a462db01 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXRAM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXRAM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXRAM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXSPI.h index dabd37ae5..56106c8f2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_FLEXSPI.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -156,11 +156,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 8u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 8u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -176,11 +176,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -191,7 +191,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[8]; __I uint32_t MISCCR4; /**< Misc Control 4, offset: 0xD0 */ __I uint32_t MISCCR5; /**< Miscellaneous Control 5, offset: 0xD4 */ @@ -834,9 +834,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) - /*! @name FLSHCR0 - Flash Control 0 */ /*! @{ */ @@ -862,9 +859,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control 1 */ /*! @{ */ @@ -905,9 +899,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control 2 */ /*! @{ */ @@ -955,9 +946,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control 4 */ /*! @{ */ @@ -1139,9 +1127,6 @@ typedef struct { #define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name MISCCR4 - Misc Control 4 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_CPU_MODE_CTRL.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_CPU_MODE_CTRL.h index 02ce05569..91ed99f66 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_CPU_MODE_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_CPU_MODE_CTRL.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_CPU_MODE_CTRL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_SET_POINT_CTRL.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_SET_POINT_CTRL.h index b370a9399..065afe2be 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_SET_POINT_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_SET_POINT_CTRL.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_SET_POINT_CTRL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_STBY_CTRL.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_STBY_CTRL.h index fddf5cd84..ccf2e7620 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_STBY_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPC_STBY_CTRL.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_STBY_CTRL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPIO.h index 990613da1..2db1e57c2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPIO.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPT.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPT.h index 81b549b58..c7500cc0d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_GPT.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPT diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_I2S.h index 309108ba7..ce80cc6e8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_I2S.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IEE.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IEE.h index 866816f62..9f5194d89 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IEE.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IEE.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for IEE diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IEE_APC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IEE_APC.h index 68f99d6e8..7a7acc9b8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IEE_APC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IEE_APC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for IEE_APC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC.h index 79d334f8b..7c53c5244 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_GPR.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_GPR.h index d4856d19b..6bc9be234 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_GPR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_GPR.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_GPR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_LPSR.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_LPSR.h index 9d24837a8..a134a5c14 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_LPSR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_LPSR.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_LPSR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_LPSR_GPR.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_LPSR_GPR.h index 4a92daa49..87060863f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_LPSR_GPR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_LPSR_GPR.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_LPSR_GPR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_SNVS.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_SNVS.h index 1f600671b..ab7d2b6ae 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_SNVS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_SNVS.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_SNVS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_SNVS_GPR.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_SNVS_GPR.h index c4a25a881..b8e72051e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_SNVS_GPR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IOMUXC_SNVS_GPR.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_SNVS_GPR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IPS_DOMAIN.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IPS_DOMAIN.h index 6bd0865cc..f6baf8e1a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IPS_DOMAIN.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_IPS_DOMAIN.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for IPS_DOMAIN diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_KEY_MANAGER.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_KEY_MANAGER.h index a028716e6..a38052adf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_KEY_MANAGER.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_KEY_MANAGER.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for KEY_MANAGER diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_KPP.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_KPP.h index 605c99e3c..89c146d85 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_KPP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_KPP.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for KPP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LCDIF.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LCDIF.h index f4b696f4f..6602aefc4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LCDIF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LCDIF.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for LCDIF diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LCDIFV2.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LCDIFV2.h index 930ec8759..65d21975d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LCDIFV2.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LCDIFV2.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for LCDIFV2 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LMEM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LMEM.h index 6e28189e3..5be0d23a1 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LMEM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LMEM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for LMEM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPI2C.h index d35a8be12..857dc89b6 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPI2C.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPSPI.h index 7f49ea02d..d930524d6 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPSPI.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPUART.h index 8eec37e08..8b18a3cba 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_LPUART.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MCM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MCM.h index a3cbec419..a52706bdc 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MCM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MCM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MECC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MECC.h index 7f8e0a937..a51eed07e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MECC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MECC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MECC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MIPI_CSI2RX.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MIPI_CSI2RX.h index 26dbe747a..b8cc52c0d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MIPI_CSI2RX.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MIPI_CSI2RX.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIPI_CSI2RX diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MMCAU.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MMCAU.h index 073b3622d..35cdbbcfd 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MMCAU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MMCAU.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MMCAU diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MU.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MU.h index 243ed9260..207d9493a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_MU.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OCOTP.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OCOTP.h index d3d7dbe49..5d2b0c949 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OCOTP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OCOTP.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for OCOTP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OSC_RC_400M.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OSC_RC_400M.h index 2fa8093f3..1281e7d45 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OSC_RC_400M.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OSC_RC_400M.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSC_RC_400M diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OTFAD.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OTFAD.h index b7f9b624b..b8759c0e7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OTFAD.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_OTFAD.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for OTFAD diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PDM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PDM.h index 96b683818..b44b461c9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PDM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PDM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PDM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_BPC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_BPC.h index febc7db9a..8062fd3c8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_BPC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_BPC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PGMC_BPC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_CPC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_CPC.h index 4b8059a56..e79c829bb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_CPC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_CPC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PGMC_CPC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_MIF.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_MIF.h index c0e04f41b..beddbc361 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_MIF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_MIF.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PGMC_MIF diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_PPC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_PPC.h index 3bd12d2ed..47b78bd8a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_PPC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PGMC_PPC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PGMC_PPC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PHY_LDO.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PHY_LDO.h index edf9fbfb0..c041e91f6 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PHY_LDO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PHY_LDO.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PHY_LDO diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PIT.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PIT.h index b075f72d2..07d9a069d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PIT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PIT.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PIT diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PUF.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PUF.h index d049be054..906aa43e7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PUF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PUF.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PUF diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PWM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PWM.h index 8f58f5f56..22b08503a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PWM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PWM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PWM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PXP.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PXP.h index 250bf9116..158764e9e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PXP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_PXP.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for PXP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RDC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RDC.h index 2d9c60adc..75752754f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RDC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RDC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for RDC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RDC_SEMAPHORE.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RDC_SEMAPHORE.h index fc978a3c1..181b10513 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RDC_SEMAPHORE.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RDC_SEMAPHORE.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for RDC_SEMAPHORE diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RTWDOG.h index 134b4805e..7cbd96fce 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_RTWDOG.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG @@ -335,10 +335,6 @@ typedef struct { * @} */ /* end of group RTWDOG_Register_Masks */ -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SEMA4.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SEMA4.h index 3676066f3..19551c398 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SEMA4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SEMA4.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMA4 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SEMC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SEMC.h index 3d0d8746f..1efe62bba 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SEMC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SEMC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SNVS.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SNVS.h index 93ab99ac7..39a7d869f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SNVS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SNVS.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for SNVS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SPDIF.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SPDIF.h index 3b98177a8..d22507053 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SPDIF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SPDIF.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPDIF diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SRAM.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SRAM.h index 7679f21ad..e45b4054e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SRAM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SRAM.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRAM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SRC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SRC.h index 815b4a572..13b648370 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SRC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SRC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SSARC_HP.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SSARC_HP.h index 6cb516710..131c8f6f7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SSARC_HP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SSARC_HP.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for SSARC_HP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SSARC_LP.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SSARC_LP.h index 110eb3500..e711f4cff 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SSARC_LP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_SSARC_LP.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for SSARC_LP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_TMPSNS.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_TMPSNS.h index 6cf5da177..96f1a70db 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_TMPSNS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_TMPSNS.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMPSNS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_TMR.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_TMR.h index 0206486e1..a40dcddb5 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_TMR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_TMR.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USB.h index 1b65c5822..ac61e5ee1 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USB.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBHSDCD.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBHSDCD.h index caaff8fee..7da21db89 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBHSDCD.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBHSDCD.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBHSDCD diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBNC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBNC.h index fd8d6c6c8..a11c26f93 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBNC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBNC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBNC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBPHY.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBPHY.h index e6b208894..c1425fc4d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBPHY.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USBPHY.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBPHY diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USDHC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USDHC.h index d7ba6f1aa..08d9a4a20 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USDHC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_USDHC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for USDHC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VIDEO_MUX.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VIDEO_MUX.h index c3f221be2..070ac7a25 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VIDEO_MUX.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VIDEO_MUX.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for VIDEO_MUX diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VIDEO_PLL.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VIDEO_PLL.h index 7d632f031..20f22a6c0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VIDEO_PLL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VIDEO_PLL.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for VIDEO_PLL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VMBANDGAP.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VMBANDGAP.h index b6dc2f01d..7a3cecd8e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VMBANDGAP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_VMBANDGAP.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for VMBANDGAP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_WDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_WDOG.h index 9b7b1c8a7..850582a6b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_WDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_WDOG.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for WDOG diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XBARA.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XBARA.h index 056757d29..208534773 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XBARA.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XBARA.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBARA diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XBARB.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XBARB.h index f1ab0adde..63600c8b0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XBARB.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XBARB.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBARB diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XECC.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XECC.h index b73802460..957dff0a9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XECC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XECC.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for XECC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XRDC2.h b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XRDC2.h index 799c63dae..6ec5e1c37 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XRDC2.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1170/periph/PERI_XRDC2.h @@ -54,7 +54,7 @@ ** MIMXRT117HDVMAB_cm7 ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250703 ** ** Abstract: ** CMSIS Peripheral Access Layer for XRDC2 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181.h index 77ce63af6..33661b15a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1181 @@ -52,7 +52,6 @@ #include "PERI_ADC.h" #include "PERI_ANADIG.h" #include "PERI_ANADIG_LDO_BBSM.h" -#include "PERI_ANADIG_MISC.h" #include "PERI_ANADIG_OSC.h" #include "PERI_ANADIG_PLL.h" #include "PERI_ANADIG_PMU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181_COMMON.h index ddb1d1831..d0a0e5575 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1181 @@ -395,6 +395,40 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup asrc_clock_source_mapping + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief The ASRC clock source + */ +typedef enum _asrc_clock_source +{ + kASRC_ClockSourceNotAvalible = -1, /**< not avalible */ + kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */ + kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */ + kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */ + kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */ + kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */ + kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */ + kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */ + kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */ + kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */ + kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */ + kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */ + kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */ + kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */ + kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */ + kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */ +} asrc_clock_source_t; + +/* @} */ + typedef enum _xbar_input_signal { kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ @@ -1367,35 +1401,6 @@ typedef enum _xbar_output_signal #define ANADIG_LDO_BBSM_BASE_PTRS { ANADIG_LDO_BBSM } #endif -/* ANADIG_MISC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x54480000u) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE_NS (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC_NS ((ANADIG_MISC_Type *)ANADIG_MISC_BASE_NS) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS_NS { ANADIG_MISC_BASE_NS } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS_NS { ANADIG_MISC_NS } -#else - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } -#endif - /* ANADIG_OSC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ANADIG_OSC base address */ @@ -2621,25 +2626,25 @@ typedef enum _xbar_output_signal #define FlexSPI2_ATDF_BASE_NS (0x4DE10000u) #else /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x28000000u, 0x2000000u}, {0x4000000u, 0x22000000u} } + #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x38000000u, 0x12000000u}, {0x14000000u, 0x32000000u} } /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x2FFFFFFFu, 0x3FFFFFFu}, {0x7FFFFFFu, 0x23FFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x3FFFFFFFu, 0x13FFFFFFu}, {0x17FFFFFFu, 0x33FFFFFFu} } /* FlexSPI1 AMBA address. */ - #define FlexSPI1_AMBA_BASE (0x28000000u) + #define FlexSPI1_AMBA_BASE (0x38000000u) /* FlexSPI1 ASFM address. */ - #define FlexSPI1_ASFM_BASE (0x28000000u) + #define FlexSPI1_ASFM_BASE (0x38000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI1_ARDF_BASE (0x47420000u) + #define FlexSPI1_ARDF_BASE (0x57420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI1_ATDF_BASE (0x47430000u) + #define FlexSPI1_ATDF_BASE (0x57430000u) /* FlexSPI2 AMBA address. */ - #define FlexSPI2_AMBA_BASE (0x4000000u) + #define FlexSPI2_AMBA_BASE (0x14000000u) /* FlexSPI2 ASFM address. */ - #define FlexSPI2_ASFM_BASE (0x4000000u) + #define FlexSPI2_ASFM_BASE (0x14000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI2_ARDF_BASE (0x4DE00000u) + #define FlexSPI2_ARDF_BASE (0x5DE00000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI2_ATDF_BASE (0x4DE10000u) + #define FlexSPI2_ATDF_BASE (0x5DE10000u) #endif @@ -5298,6 +5303,9 @@ typedef enum _xbar_output_signal /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { TSTMR1_TSTMRA, TSTMR2_TSTMRA } #endif +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + /* USBHSDCD - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181_features.h index fd0223c76..54163ef02 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/MIMXRT1181_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-03-09 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -295,6 +295,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* SCB module features */ @@ -321,8 +323,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -335,6 +335,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -484,8 +486,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -514,6 +514,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -530,7 +532,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -547,6 +549,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPT module features */ @@ -667,8 +695,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -711,6 +737,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* SYSPM module features */ @@ -969,6 +999,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/system_MIMXRT1181.c b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/system_MIMXRT1181.c index b00712d34..e7a756689 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/system_MIMXRT1181.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/system_MIMXRT1181.c @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -41,7 +41,7 @@ /*! * @file MIMXRT1181 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1181 (implementation file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/system_MIMXRT1181.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/system_MIMXRT1181.h index f1e1300bf..95196ee6c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/system_MIMXRT1181.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1181/system_MIMXRT1181.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -41,7 +41,7 @@ /*! * @file MIMXRT1181 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1181 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182.h index 4d1bcbf72..e79f25382 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1182 @@ -52,7 +52,6 @@ #include "PERI_ADC.h" #include "PERI_ANADIG.h" #include "PERI_ANADIG_LDO_BBSM.h" -#include "PERI_ANADIG_MISC.h" #include "PERI_ANADIG_OSC.h" #include "PERI_ANADIG_PLL.h" #include "PERI_ANADIG_PMU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182_COMMON.h index 24613768a..d3e17f296 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1182 @@ -395,6 +395,40 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup asrc_clock_source_mapping + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief The ASRC clock source + */ +typedef enum _asrc_clock_source +{ + kASRC_ClockSourceNotAvalible = -1, /**< not avalible */ + kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */ + kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */ + kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */ + kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */ + kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */ + kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */ + kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */ + kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */ + kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */ + kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */ + kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */ + kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */ + kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */ + kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */ + kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */ +} asrc_clock_source_t; + +/* @} */ + typedef enum _xbar_input_signal { kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ @@ -1367,35 +1401,6 @@ typedef enum _xbar_output_signal #define ANADIG_LDO_BBSM_BASE_PTRS { ANADIG_LDO_BBSM } #endif -/* ANADIG_MISC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x54480000u) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE_NS (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC_NS ((ANADIG_MISC_Type *)ANADIG_MISC_BASE_NS) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS_NS { ANADIG_MISC_BASE_NS } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS_NS { ANADIG_MISC_NS } -#else - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } -#endif - /* ANADIG_OSC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ANADIG_OSC base address */ @@ -2650,25 +2655,25 @@ typedef enum _xbar_output_signal #define FlexSPI2_ATDF_BASE_NS (0x4DE10000u) #else /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x28000000u, 0x2000000u}, {0x4000000u, 0x22000000u} } + #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x38000000u, 0x12000000u}, {0x14000000u, 0x32000000u} } /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x2FFFFFFFu, 0x3FFFFFFu}, {0x7FFFFFFu, 0x23FFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x3FFFFFFFu, 0x13FFFFFFu}, {0x17FFFFFFu, 0x33FFFFFFu} } /* FlexSPI1 AMBA address. */ - #define FlexSPI1_AMBA_BASE (0x28000000u) + #define FlexSPI1_AMBA_BASE (0x38000000u) /* FlexSPI1 ASFM address. */ - #define FlexSPI1_ASFM_BASE (0x28000000u) + #define FlexSPI1_ASFM_BASE (0x38000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI1_ARDF_BASE (0x47420000u) + #define FlexSPI1_ARDF_BASE (0x57420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI1_ATDF_BASE (0x47430000u) + #define FlexSPI1_ATDF_BASE (0x57430000u) /* FlexSPI2 AMBA address. */ - #define FlexSPI2_AMBA_BASE (0x4000000u) + #define FlexSPI2_AMBA_BASE (0x14000000u) /* FlexSPI2 ASFM address. */ - #define FlexSPI2_ASFM_BASE (0x4000000u) + #define FlexSPI2_ASFM_BASE (0x14000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI2_ARDF_BASE (0x4DE00000u) + #define FlexSPI2_ARDF_BASE (0x5DE00000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI2_ATDF_BASE (0x4DE10000u) + #define FlexSPI2_ATDF_BASE (0x5DE10000u) #endif @@ -5327,6 +5332,9 @@ typedef enum _xbar_output_signal /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { TSTMR1_TSTMRA, TSTMR2_TSTMRA } #endif +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + /* USBHSDCD - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182_features.h index e0b05c0ee..166e1d216 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/MIMXRT1182_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-03-09 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -295,6 +295,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* SCB module features */ @@ -321,8 +323,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -335,6 +335,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -484,8 +486,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -514,6 +514,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -530,7 +532,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -547,6 +549,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPT module features */ @@ -667,8 +695,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -711,6 +737,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* SYSPM module features */ @@ -969,6 +999,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/system_MIMXRT1182.c b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/system_MIMXRT1182.c index 067266353..f005bd69b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/system_MIMXRT1182.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/system_MIMXRT1182.c @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -41,7 +41,7 @@ /*! * @file MIMXRT1182 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1182 (implementation file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/system_MIMXRT1182.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/system_MIMXRT1182.h index 7d12b4d91..c16a6eb90 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/system_MIMXRT1182.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1182/system_MIMXRT1182.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -41,7 +41,7 @@ /*! * @file MIMXRT1182 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1182 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33.h index 3254443b7..12433e80c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1186_cm33 @@ -50,7 +50,6 @@ #include "PERI_ADC.h" #include "PERI_ANADIG.h" #include "PERI_ANADIG_LDO_BBSM.h" -#include "PERI_ANADIG_MISC.h" #include "PERI_ANADIG_OSC.h" #include "PERI_ANADIG_PLL.h" #include "PERI_ANADIG_PMU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33_COMMON.h index 03ceda2f7..de939d3b3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1186_cm33 @@ -393,6 +393,40 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup asrc_clock_source_mapping + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief The ASRC clock source + */ +typedef enum _asrc_clock_source +{ + kASRC_ClockSourceNotAvalible = -1, /**< not avalible */ + kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */ + kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */ + kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */ + kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */ + kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */ + kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */ + kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */ + kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */ + kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */ + kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */ + kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */ + kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */ + kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */ + kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */ + kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */ +} asrc_clock_source_t; + +/* @} */ + typedef enum _xbar_input_signal { kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ @@ -1365,35 +1399,6 @@ typedef enum _xbar_output_signal #define ANADIG_LDO_BBSM_BASE_PTRS { ANADIG_LDO_BBSM } #endif -/* ANADIG_MISC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x54480000u) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE_NS (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC_NS ((ANADIG_MISC_Type *)ANADIG_MISC_BASE_NS) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS_NS { ANADIG_MISC_BASE_NS } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS_NS { ANADIG_MISC_NS } -#else - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } -#endif - /* ANADIG_OSC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ANADIG_OSC base address */ @@ -2648,25 +2653,25 @@ typedef enum _xbar_output_signal #define FlexSPI2_ATDF_BASE_NS (0x4DE10000u) #else /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x28000000u, 0x2000000u}, {0x4000000u, 0x22000000u} } + #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x38000000u, 0x12000000u}, {0x14000000u, 0x32000000u} } /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x2FFFFFFFu, 0x3FFFFFFu}, {0x7FFFFFFu, 0x23FFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x3FFFFFFFu, 0x13FFFFFFu}, {0x17FFFFFFu, 0x33FFFFFFu} } /* FlexSPI1 AMBA address. */ - #define FlexSPI1_AMBA_BASE (0x28000000u) + #define FlexSPI1_AMBA_BASE (0x38000000u) /* FlexSPI1 ASFM address. */ - #define FlexSPI1_ASFM_BASE (0x28000000u) + #define FlexSPI1_ASFM_BASE (0x38000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI1_ARDF_BASE (0x47420000u) + #define FlexSPI1_ARDF_BASE (0x57420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI1_ATDF_BASE (0x47430000u) + #define FlexSPI1_ATDF_BASE (0x57430000u) /* FlexSPI2 AMBA address. */ - #define FlexSPI2_AMBA_BASE (0x4000000u) + #define FlexSPI2_AMBA_BASE (0x14000000u) /* FlexSPI2 ASFM address. */ - #define FlexSPI2_ASFM_BASE (0x4000000u) + #define FlexSPI2_ASFM_BASE (0x14000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI2_ARDF_BASE (0x4DE00000u) + #define FlexSPI2_ARDF_BASE (0x5DE00000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI2_ATDF_BASE (0x4DE10000u) + #define FlexSPI2_ATDF_BASE (0x5DE10000u) #endif @@ -5524,6 +5529,9 @@ typedef enum _xbar_output_signal /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { TSTMR1_TSTMRA, TSTMR2_TSTMRA } #endif +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + /* USB - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33_features.h index ede01ad7b..7b981973f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-03-09 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -303,6 +303,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* SCB module features */ @@ -329,8 +331,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -343,6 +343,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -492,8 +494,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -522,6 +522,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -538,7 +540,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -555,6 +557,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPT module features */ @@ -675,8 +703,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -719,6 +745,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* SYSPM module features */ @@ -983,6 +1013,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7.h index 04c8f8183..c97de22bd 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1186_cm7 @@ -50,7 +50,6 @@ #include "PERI_ADC.h" #include "PERI_ANADIG.h" #include "PERI_ANADIG_LDO_BBSM.h" -#include "PERI_ANADIG_MISC.h" #include "PERI_ANADIG_OSC.h" #include "PERI_ANADIG_PLL.h" #include "PERI_ANADIG_PMU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7_COMMON.h index 8db45dd5f..93e687a3d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1186_cm7 @@ -393,6 +393,40 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup asrc_clock_source_mapping + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief The ASRC clock source + */ +typedef enum _asrc_clock_source +{ + kASRC_ClockSourceNotAvalible = -1, /**< not avalible */ + kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */ + kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */ + kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */ + kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */ + kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */ + kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */ + kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */ + kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */ + kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */ + kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */ + kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */ + kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */ + kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */ + kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */ + kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */ +} asrc_clock_source_t; + +/* @} */ + typedef enum _xbar_input_signal { kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ @@ -1300,16 +1334,6 @@ typedef enum _xbar_output_signal /** Array initializer of ANADIG_LDO_BBSM peripheral base pointers */ #define ANADIG_LDO_BBSM_BASE_PTRS { ANADIG_LDO_BBSM } -/* ANADIG_MISC - Peripheral instance base addresses */ -/** Peripheral ANADIG_MISC base address */ -#define ANADIG_MISC_BASE (0x44480000u) -/** Peripheral ANADIG_MISC base pointer */ -#define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) -/** Array initializer of ANADIG_MISC peripheral base addresses */ -#define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } -/** Array initializer of ANADIG_MISC peripheral base pointers */ -#define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } - /* ANADIG_OSC - Peripheral instance base addresses */ /** Peripheral ANADIG_OSC base address */ #define ANADIG_OSC_BASE (0x44480000u) @@ -2786,6 +2810,9 @@ typedef enum _xbar_output_signal #define TSTMR_BASE_ADDRS { TSTMR1_TSTMRA_BASE, TSTMR2_TSTMRA_BASE } /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { TSTMR1_TSTMRA, TSTMR2_TSTMRA } +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + /* USB - Peripheral instance base addresses */ /** Peripheral USB_OTG1 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7_features.h index 32a58ac4f..b6a253ee4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/MIMXRT1186_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-03-09 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -301,6 +301,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* SCB module features */ @@ -327,8 +329,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -341,6 +341,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -490,8 +492,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -520,6 +520,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -536,7 +538,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -553,6 +555,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPT module features */ @@ -673,8 +701,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -717,6 +743,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* SYSPM module features */ @@ -981,6 +1011,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm33.c b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm33.c index 4629d6ae9..e7631a39e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm33.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm33.c @@ -10,7 +10,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -39,7 +39,7 @@ /*! * @file MIMXRT1186_cm33 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1186_cm33 (implementation file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm33.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm33.h index facd7203e..c59141760 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm33.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm33.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -39,7 +39,7 @@ /*! * @file MIMXRT1186_cm33 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1186_cm33 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm7.c b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm7.c index 13f27aa05..336718a3e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm7.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm7.c @@ -10,7 +10,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -39,7 +39,7 @@ /*! * @file MIMXRT1186_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1186_cm7 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm7.h index 05a96554d..e69bf3139 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1186/system_MIMXRT1186_cm7.h @@ -10,7 +10,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -39,7 +39,7 @@ /*! * @file MIMXRT1186_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1186_cm7 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33.h index 6c9bc32c1..6a990a045 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33.h @@ -14,7 +14,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1187_cm33 @@ -54,7 +54,6 @@ #include "PERI_ADC.h" #include "PERI_ANADIG.h" #include "PERI_ANADIG_LDO_BBSM.h" -#include "PERI_ANADIG_MISC.h" #include "PERI_ANADIG_OSC.h" #include "PERI_ANADIG_PLL.h" #include "PERI_ANADIG_PMU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33_COMMON.h index 2f700491c..64d75be4f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33_COMMON.h @@ -14,7 +14,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1187_cm33 @@ -397,6 +397,40 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup asrc_clock_source_mapping + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief The ASRC clock source + */ +typedef enum _asrc_clock_source +{ + kASRC_ClockSourceNotAvalible = -1, /**< not avalible */ + kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */ + kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */ + kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */ + kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */ + kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */ + kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */ + kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */ + kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */ + kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */ + kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */ + kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */ + kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */ + kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */ + kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */ + kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */ +} asrc_clock_source_t; + +/* @} */ + typedef enum _xbar_input_signal { kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ @@ -1369,35 +1403,6 @@ typedef enum _xbar_output_signal #define ANADIG_LDO_BBSM_BASE_PTRS { ANADIG_LDO_BBSM } #endif -/* ANADIG_MISC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x54480000u) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE_NS (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC_NS ((ANADIG_MISC_Type *)ANADIG_MISC_BASE_NS) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS_NS { ANADIG_MISC_BASE_NS } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS_NS { ANADIG_MISC_NS } -#else - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } -#endif - /* ANADIG_OSC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ANADIG_OSC base address */ @@ -2671,25 +2676,25 @@ typedef enum _xbar_output_signal #define FlexSPI2_ATDF_BASE_NS (0x4DE10000u) #else /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x28000000u, 0x2000000u}, {0x4000000u, 0x22000000u} } + #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x38000000u, 0x12000000u}, {0x14000000u, 0x32000000u} } /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x2FFFFFFFu, 0x3FFFFFFu}, {0x7FFFFFFu, 0x23FFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x3FFFFFFFu, 0x13FFFFFFu}, {0x17FFFFFFu, 0x33FFFFFFu} } /* FlexSPI1 AMBA address. */ - #define FlexSPI1_AMBA_BASE (0x28000000u) + #define FlexSPI1_AMBA_BASE (0x38000000u) /* FlexSPI1 ASFM address. */ - #define FlexSPI1_ASFM_BASE (0x28000000u) + #define FlexSPI1_ASFM_BASE (0x38000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI1_ARDF_BASE (0x47420000u) + #define FlexSPI1_ARDF_BASE (0x57420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI1_ATDF_BASE (0x47430000u) + #define FlexSPI1_ATDF_BASE (0x57430000u) /* FlexSPI2 AMBA address. */ - #define FlexSPI2_AMBA_BASE (0x4000000u) + #define FlexSPI2_AMBA_BASE (0x14000000u) /* FlexSPI2 ASFM address. */ - #define FlexSPI2_ASFM_BASE (0x4000000u) + #define FlexSPI2_ASFM_BASE (0x14000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI2_ARDF_BASE (0x4DE00000u) + #define FlexSPI2_ARDF_BASE (0x5DE00000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI2_ATDF_BASE (0x4DE10000u) + #define FlexSPI2_ATDF_BASE (0x5DE10000u) #endif @@ -5655,6 +5660,9 @@ typedef enum _xbar_output_signal /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { TSTMR1_TSTMRA, TSTMR2_TSTMRA } #endif +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + /* USB - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33_features.h index 68e626515..ace3b6296 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-03-09 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -303,6 +303,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* SCB module features */ @@ -329,8 +331,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -343,6 +343,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -492,8 +494,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -522,6 +522,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -538,7 +540,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -555,6 +557,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPT module features */ @@ -675,8 +703,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -719,6 +745,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* SYSPM module features */ @@ -985,6 +1015,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7.h index bdb0b3af2..2ae060c61 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7.h @@ -14,7 +14,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1187_cm7 @@ -54,7 +54,6 @@ #include "PERI_ADC.h" #include "PERI_ANADIG.h" #include "PERI_ANADIG_LDO_BBSM.h" -#include "PERI_ANADIG_MISC.h" #include "PERI_ANADIG_OSC.h" #include "PERI_ANADIG_PLL.h" #include "PERI_ANADIG_PMU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7_COMMON.h index 7cbfa5a2e..f3f9fd3b4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7_COMMON.h @@ -14,7 +14,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1187_cm7 @@ -397,6 +397,40 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup asrc_clock_source_mapping + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief The ASRC clock source + */ +typedef enum _asrc_clock_source +{ + kASRC_ClockSourceNotAvalible = -1, /**< not avalible */ + kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */ + kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */ + kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */ + kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */ + kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */ + kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */ + kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */ + kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */ + kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */ + kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */ + kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */ + kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */ + kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */ + kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */ + kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */ +} asrc_clock_source_t; + +/* @} */ + typedef enum _xbar_input_signal { kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ @@ -1304,16 +1338,6 @@ typedef enum _xbar_output_signal /** Array initializer of ANADIG_LDO_BBSM peripheral base pointers */ #define ANADIG_LDO_BBSM_BASE_PTRS { ANADIG_LDO_BBSM } -/* ANADIG_MISC - Peripheral instance base addresses */ -/** Peripheral ANADIG_MISC base address */ -#define ANADIG_MISC_BASE (0x44480000u) -/** Peripheral ANADIG_MISC base pointer */ -#define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) -/** Array initializer of ANADIG_MISC peripheral base addresses */ -#define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } -/** Array initializer of ANADIG_MISC peripheral base pointers */ -#define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } - /* ANADIG_OSC - Peripheral instance base addresses */ /** Peripheral ANADIG_OSC base address */ #define ANADIG_OSC_BASE (0x44480000u) @@ -2832,6 +2856,9 @@ typedef enum _xbar_output_signal #define TSTMR_BASE_ADDRS { TSTMR1_TSTMRA_BASE, TSTMR2_TSTMRA_BASE } /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { TSTMR1_TSTMRA, TSTMR2_TSTMRA } +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + /* USB - Peripheral instance base addresses */ /** Peripheral USB_OTG1 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7_features.h index da89d32eb..b5bc548bd 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/MIMXRT1187_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-03-09 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -301,6 +301,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* SCB module features */ @@ -327,8 +329,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -341,6 +341,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -490,8 +492,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -520,6 +520,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -536,7 +538,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -553,6 +555,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPT module features */ @@ -673,8 +701,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -717,6 +743,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* SYSPM module features */ @@ -983,6 +1013,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm33.c b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm33.c index 1cf6aab9d..3756ec511 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm33.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm33.c @@ -14,7 +14,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -43,7 +43,7 @@ /*! * @file MIMXRT1187_cm33 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1187_cm33 (implementation file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm33.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm33.h index a60b5533b..c6de31494 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm33.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm33.h @@ -14,7 +14,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -43,7 +43,7 @@ /*! * @file MIMXRT1187_cm33 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1187_cm33 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm7.c b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm7.c index 3ee062cda..ab8d550bd 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm7.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm7.c @@ -14,7 +14,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -43,7 +43,7 @@ /*! * @file MIMXRT1187_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1187_cm7 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm7.h index f9d16794d..72b3db975 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1187/system_MIMXRT1187_cm7.h @@ -14,7 +14,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -43,7 +43,7 @@ /*! * @file MIMXRT1187_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1187_cm7 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33.h index a11ba8fc7..47524e72b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1189_cm33 @@ -52,7 +52,6 @@ #include "PERI_ADC.h" #include "PERI_ANADIG.h" #include "PERI_ANADIG_LDO_BBSM.h" -#include "PERI_ANADIG_MISC.h" #include "PERI_ANADIG_OSC.h" #include "PERI_ANADIG_PLL.h" #include "PERI_ANADIG_PMU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33_COMMON.h index a9e15ade9..6f1479036 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1189_cm33 @@ -395,6 +395,40 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup asrc_clock_source_mapping + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief The ASRC clock source + */ +typedef enum _asrc_clock_source +{ + kASRC_ClockSourceNotAvalible = -1, /**< not avalible */ + kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */ + kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */ + kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */ + kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */ + kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */ + kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */ + kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */ + kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */ + kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */ + kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */ + kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */ + kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */ + kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */ + kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */ + kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */ +} asrc_clock_source_t; + +/* @} */ + typedef enum _xbar_input_signal { kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ @@ -1367,35 +1401,6 @@ typedef enum _xbar_output_signal #define ANADIG_LDO_BBSM_BASE_PTRS { ANADIG_LDO_BBSM } #endif -/* ANADIG_MISC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x54480000u) - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE_NS (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC_NS ((ANADIG_MISC_Type *)ANADIG_MISC_BASE_NS) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS_NS { ANADIG_MISC_BASE_NS } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS_NS { ANADIG_MISC_NS } -#else - /** Peripheral ANADIG_MISC base address */ - #define ANADIG_MISC_BASE (0x44480000u) - /** Peripheral ANADIG_MISC base pointer */ - #define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) - /** Array initializer of ANADIG_MISC peripheral base addresses */ - #define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } - /** Array initializer of ANADIG_MISC peripheral base pointers */ - #define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } -#endif - /* ANADIG_OSC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ANADIG_OSC base address */ @@ -2698,25 +2703,25 @@ typedef enum _xbar_output_signal #define FlexSPI2_ATDF_BASE_NS (0x4DE10000u) #else /* FlexSPI AMBA base address array. */ - #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x28000000u, 0x2000000u}, {0x4000000u, 0x22000000u} } + #define FlexSPI_AMBA_BASE_ARRAY { {0u, 0u}, {0x38000000u, 0x12000000u}, {0x14000000u, 0x32000000u} } /* FlexSPI AMBA end address array. */ - #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x2FFFFFFFu, 0x3FFFFFFu}, {0x7FFFFFFu, 0x23FFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY { {0u, 0u}, {0x3FFFFFFFu, 0x13FFFFFFu}, {0x17FFFFFFu, 0x33FFFFFFu} } /* FlexSPI1 AMBA address. */ - #define FlexSPI1_AMBA_BASE (0x28000000u) + #define FlexSPI1_AMBA_BASE (0x38000000u) /* FlexSPI1 ASFM address. */ - #define FlexSPI1_ASFM_BASE (0x28000000u) + #define FlexSPI1_ASFM_BASE (0x38000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI1_ARDF_BASE (0x47420000u) + #define FlexSPI1_ARDF_BASE (0x57420000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI1_ATDF_BASE (0x47430000u) + #define FlexSPI1_ATDF_BASE (0x57430000u) /* FlexSPI2 AMBA address. */ - #define FlexSPI2_AMBA_BASE (0x4000000u) + #define FlexSPI2_AMBA_BASE (0x14000000u) /* FlexSPI2 ASFM address. */ - #define FlexSPI2_ASFM_BASE (0x4000000u) + #define FlexSPI2_ASFM_BASE (0x14000000u) /* Base Address of AHB address space mapped to IP RX FIFO. */ - #define FlexSPI2_ARDF_BASE (0x4DE00000u) + #define FlexSPI2_ARDF_BASE (0x5DE00000u) /* Base Address of AHB address space mapped to IP TX FIFO. */ - #define FlexSPI2_ATDF_BASE (0x4DE10000u) + #define FlexSPI2_ATDF_BASE (0x5DE10000u) #endif @@ -5682,6 +5687,9 @@ typedef enum _xbar_output_signal /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { TSTMR1_TSTMRA, TSTMR2_TSTMRA } #endif +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + /* USB - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33_features.h index 8188de04f..9d5986dda 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-03-09 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -303,6 +303,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* SCB module features */ @@ -329,8 +331,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -343,6 +343,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -492,8 +494,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -522,6 +522,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -538,7 +540,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -555,6 +557,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPT module features */ @@ -675,8 +703,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -719,6 +745,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* SYSPM module features */ @@ -985,6 +1015,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7.h index 7177424c3..9fd9c594c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1189_cm7 @@ -52,7 +52,6 @@ #include "PERI_ADC.h" #include "PERI_ANADIG.h" #include "PERI_ANADIG_LDO_BBSM.h" -#include "PERI_ANADIG_MISC.h" #include "PERI_ANADIG_OSC.h" #include "PERI_ANADIG_PLL.h" #include "PERI_ANADIG_PMU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7_COMMON.h index 62d69bd62..ea264540f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1189_cm7 @@ -395,6 +395,40 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup asrc_clock_source_mapping + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief The ASRC clock source + */ +typedef enum _asrc_clock_source +{ + kASRC_ClockSourceNotAvalible = -1, /**< not avalible */ + kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */ + kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */ + kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */ + kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */ + kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */ + kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */ + kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */ + kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */ + kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */ + kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */ + kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */ + kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */ + kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */ + kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */ + kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */ +} asrc_clock_source_t; + +/* @} */ + typedef enum _xbar_input_signal { kXBAR1_InputLogicLow = 0|0x10000U, /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */ @@ -1302,16 +1336,6 @@ typedef enum _xbar_output_signal /** Array initializer of ANADIG_LDO_BBSM peripheral base pointers */ #define ANADIG_LDO_BBSM_BASE_PTRS { ANADIG_LDO_BBSM } -/* ANADIG_MISC - Peripheral instance base addresses */ -/** Peripheral ANADIG_MISC base address */ -#define ANADIG_MISC_BASE (0x44480000u) -/** Peripheral ANADIG_MISC base pointer */ -#define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) -/** Array initializer of ANADIG_MISC peripheral base addresses */ -#define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } -/** Array initializer of ANADIG_MISC peripheral base pointers */ -#define ANADIG_MISC_BASE_PTRS { ANADIG_MISC } - /* ANADIG_OSC - Peripheral instance base addresses */ /** Peripheral ANADIG_OSC base address */ #define ANADIG_OSC_BASE (0x44480000u) @@ -2840,6 +2864,9 @@ typedef enum _xbar_output_signal #define TSTMR_BASE_ADDRS { TSTMR1_TSTMRA_BASE, TSTMR2_TSTMRA_BASE } /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { TSTMR1_TSTMRA, TSTMR2_TSTMRA } +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + /* USB - Peripheral instance base addresses */ /** Peripheral USB_OTG1 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7_features.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7_features.h index 48b4f1b84..b926b2175 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/MIMXRT1189_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 0.1, 2021-03-09 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -301,6 +301,8 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) /* SCB module features */ @@ -327,8 +329,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (0) /* @brief If support round-robin mode */ @@ -341,6 +341,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* DAC12 module features */ @@ -490,8 +492,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -520,6 +520,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ @@ -536,7 +538,7 @@ /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ @@ -553,6 +555,32 @@ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (4096) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (3) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPT module features */ @@ -673,8 +701,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -717,6 +743,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* SYSPM module features */ @@ -983,6 +1013,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/drivers/fsl_clock.h index 57e952767..84c2f7f3f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/drivers/fsl_clock.h @@ -40,7 +40,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief CLOCK driver version. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /* Definition for delay API in clock driver, users can redefine it to the real application. */ #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY @@ -1278,6 +1278,29 @@ typedef enum _clock_pll_post_div kCLOCK_PllPostDiv1 = 3U, /*!< Divide by 1. */ } clock_pll_post_div_t; +/*! + * @brief The enumerater of clock output1's clock source. + */ +typedef enum _clock_output1_selection +{ + kCLOCK_CKO1OutputMuxOscRc24M = 0U, /*!< CKO1 mux from OscRc24M. */ + kCLOCK_CKO1OutputMuxOscRc400M = 1U, /*!< CKO1 mux from OscRc400M. */ + kCLOCK_CKO1OutputMuxSysPll3Div2 = 2U, /*!< CKO1 mux from SysPll3Div2. */ + kCLOCK_CKO1OutputMuxSysPll1Div2 = 3U, /*!< CKO1 mux from SysPll1Div2. */ +} clock_output1_selection_t; + +/*! + * @brief The enumerater of clock output2's clock source. + * + */ +typedef enum _clock_output2_selection +{ + kCLOCK_CKO2OutputMuxOscRc24M = 0U, /*!< CKO2 mux from OscRc24M. */ + kCLOCK_CKO2OutputMuxOscRc400M = 1U, /*!< CKO2 mux from OscRc400M. */ + kCLOCK_CKO2OutputMuxSysPll1Div5 = 2U, /*!< CKO2 mux from SysPll1Div5. */ + kCLOCK_CKO2OutputMuxArmPllOut = 3U, /*!< CKO2 mux from ArmPllOut. */ +} clock_output2_selection_t; + /*! * @brief PLL configuration for ARM. * @@ -1786,25 +1809,6 @@ void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode); */ void CLOCK_OSC_EnableOscRc400M(void); -/*! - * @brief Gate/ungate 400MHz RC oscillator. - * - * @param enableGate Used to gate/ungate 400MHz RC oscillator. - * - \b true Gate the 400MHz RC oscillator. - * - \b false Ungate the 400MHz RC oscillator. - */ -static inline void CLOCK_OSC_GateOscRc400M(bool enableGate) -{ - if (enableGate) - { - ANADIG_OSC->OSC_400M_CTRL1 |= ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK; - } - else - { - ANADIG_OSC->OSC_400M_CTRL1 &= ~ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK; - } -} - /*! * @brief Trims OSC RC 400MHz. * @@ -2296,6 +2300,61 @@ static inline void CLOCK_LPCG_SetWhiteList(clock_lpcg_t name, uint8_t domainId) */ void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name, uint32_t domainMap, clock_level_t level); +/*! + * @name Clock Output Inferfaces + * @{ + */ + +/*! + * @brief Set the clock source and the divider of the clock output1. + * + * param selection The clock source to be output, please refer to clock_output1_selection_t. + * param divider The divider of the output clock signal. + */ +static inline void CLOCK_SetClockOutput1(clock_output1_selection_t selection, uint32_t divider) +{ + clock_root_config_t rootCfg = {0}; + + rootCfg.mux = selection; + rootCfg.div = divider; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); +} + +/*! + * @brief Set the clock source and the divider of the clock output2. + * + * param selection The clock source to be output, please refer to clock_output2_selection_t. + * param divider The divider of the output clock signal. + */ +static inline void CLOCK_SetClockOutput2(clock_output2_selection_t selection, uint32_t divider) +{ + clock_root_config_t rootCfg = {0}; + + rootCfg.mux = selection; + rootCfg.div = divider; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); +} + +/*! + * @brief Get the frequency of clock output1 clock signal. + * + * @return The frequency of clock output1 clock signal. + */ +static inline uint32_t CLOCK_GetClockOutCLKO1Freq(void) +{ + return CLOCK_GetRootClockFreq(kCLOCK_Root_Cko1); +} + +/*! + * @brief Get the frequency of clock output2 clock signal. + * + * @return The frequency of clock output2 clock signal. + */ +static inline uint32_t CLOCK_GetClockOutClkO2Freq(void) +{ + return CLOCK_GetRootClockFreq(kCLOCK_Root_Cko2); +} + /* @} */ #if defined(__cplusplus) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm33.c b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm33.c index c56896c7e..ec23b6333 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm33.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm33.c @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -41,7 +41,7 @@ /*! * @file MIMXRT1189_cm33 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1189_cm33 (implementation file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm33.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm33.h index cd846eddd..33ae0a676 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm33.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm33.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -41,7 +41,7 @@ /*! * @file MIMXRT1189_cm33 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1189_cm33 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm7.c b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm7.c index ae924f340..7b31172b5 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm7.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm7.c @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -41,7 +41,7 @@ /*! * @file MIMXRT1189_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1189_cm7 (implementation * file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm7.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm7.h index bc3ac8f5e..4b0f0e851 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm7.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189/system_MIMXRT1189_cm7.h @@ -12,7 +12,7 @@ ** ** Reference manual: IMXRT1180RM, Rev 5, 01/2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -41,7 +41,7 @@ /*! * @file MIMXRT1189_cm7 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-21 * @brief Device specific configuration file for MIMXRT1189_cm7 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ADC.h index cebd49c10..fb085ebea 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ADC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG.h index b6c4f5a84..fa2d4e2b0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_LDO_BBSM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_LDO_BBSM.h index 50f9b7c36..1d7f2075e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_LDO_BBSM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_LDO_BBSM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_LDO_BBSM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_MISC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_MISC.h index f0d79aa4e..d3a06ed90 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_MISC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_MISC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250529 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_MISC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_OSC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_OSC.h index b00a26414..9ac373788 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_OSC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_OSC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_OSC @@ -257,14 +257,6 @@ typedef struct { */ #define ANADIG_OSC_OSC_400M_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK) -#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK (0x2U) -#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT (1U) -/*! CLKGATE_400MEG - Clock gate control for 400MHz RCOSC - * 0b0..Not Gated - * 0b1..Gated - */ -#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK) - #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U) #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U) /*! RC_400M_CONTROL_MODE - 400MHz RCOSC Control mode diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_PLL.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_PLL.h index 93652c888..217d611e7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_PLL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_PLL.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_PLL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_PMU.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_PMU.h index 935226c08..c77c5d4a3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_PMU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_PMU.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_PMU diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_TEMPSENSOR.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_TEMPSENSOR.h index 38d39ed8a..cffbce024 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_TEMPSENSOR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ANADIG_TEMPSENSOR.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ANADIG_TEMPSENSOR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_AOI.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_AOI.h index abb44fbfa..42a8df88f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_AOI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_AOI.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AOI diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ASRC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ASRC.h index 50518e3cd..34a67c01a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ASRC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ASRC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ASRC @@ -90,59 +90,6 @@ #error "No valid CPU defined!" #endif -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -#if !defined(ASRC_CLOCK_SOURCE_T_) -#define ASRC_CLOCK_SOURCE_T_ -/*! - * @addtogroup asrc_clock_source_mapping - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief The ASRC clock source - */ -typedef enum _asrc_clock_source -{ - kASRC_ClockSourceNotAvalible = -1, /**< not avalible */ - kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */ - kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */ - kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */ - kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */ - kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */ - kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */ - kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */ - kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */ - kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */ - kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */ - kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */ - kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */ - kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */ - kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */ - kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */ -} asrc_clock_source_t; - -/* @} */ -#endif /* ASRC_CLOCK_SOURCE_T_ */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_AXBS.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_AXBS.h index e1b34a4c4..de9b0766f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_AXBS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_AXBS.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for AXBS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BBNSM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BBNSM.h index 4a8dc0d36..8951ee228 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BBNSM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BBNSM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BBNSM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_BBSMMIX.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_BBSMMIX.h index c8eb1ab35..e1c77b081 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_BBSMMIX.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_BBSMMIX.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_BBSMMIX diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_NS_AONMIX.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_NS_AONMIX.h index 6e9240ed1..5d4b0f5fa 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_NS_AONMIX.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_NS_AONMIX.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_NS_AONMIX diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_S_AONMIX.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_S_AONMIX.h index 8d9e03c0a..2ba342ab9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_S_AONMIX.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_S_AONMIX.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_S_AONMIX diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_WAKEUPMIX.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_WAKEUPMIX.h index 2842e5904..0c93f8c0f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_WAKEUPMIX.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_BLK_CTRL_WAKEUPMIX.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLK_CTRL_WAKEUPMIX diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CACHE_ECC_MCM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CACHE_ECC_MCM.h index eafed03d0..9df77051f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CACHE_ECC_MCM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CACHE_ECC_MCM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CACHE_ECC_MCM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CAN.h index 51abefb9b..931032cb0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CAN.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CCM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CCM.h index 1804cf68a..4ab7f336d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CCM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CCM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CMP.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CMP.h index f375f5000..8fd8a6d0e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CMP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_CMP.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DAC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DAC.h index 488b6e52e..9e7c6cb87 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DAC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DAC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DAC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DCDC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DCDC.h index b25c92c26..2f6779e69 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DCDC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DCDC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DCDC @@ -520,10 +520,9 @@ typedef struct { #define DCDC_CURRENT_TRG_LP_EN_1P0_MASK (0x80000000U) #define DCDC_CURRENT_TRG_LP_EN_1P0_SHIFT (31U) -/*! LP_EN_1P0 - This value comes from the smaller one between TRG_SW_0 and TRG_SW_1. This bit only - * controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG - * 0b0..DCDC 1P0 works in run mode. Its output voltage is controlled by VDD1P0CTRL_TRG. - * 0b1..DCDC 1P0 works in low power mode. Its output voltage is controlled by VDD1P0CTRL_LP_TRG and its output current is less than 50mA. +/*! LP_EN_1P0 - Low-Power Enable. This value comes from the smaller one between TRG_SW_0 and TRG_SW_1. + * 0b0..DCDC works in run mode. Its output voltage is controlled by VDD1P0CTRL_TRG. + * 0b1..DCDC works in low power mode. */ #define DCDC_CURRENT_TRG_LP_EN_1P0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CURRENT_TRG_LP_EN_1P0_SHIFT)) & DCDC_CURRENT_TRG_LP_EN_1P0_MASK) /*! @} */ @@ -612,7 +611,7 @@ typedef struct { #define DCDC_TRG_SW_0_LP_EN_1P0_MASK (0x80000000U) #define DCDC_TRG_SW_0_LP_EN_1P0_SHIFT (31U) -/*! LP_EN_1P0 - LP_EN_1P0 only controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG */ +/*! LP_EN_1P0 - Low-Power Enable */ #define DCDC_TRG_SW_0_LP_EN_1P0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_0_LP_EN_1P0_SHIFT)) & DCDC_TRG_SW_0_LP_EN_1P0_MASK) /*! @} */ @@ -633,7 +632,7 @@ typedef struct { #define DCDC_TRG_GPC_0_LP_EN_1P0_MASK (0x80000000U) #define DCDC_TRG_GPC_0_LP_EN_1P0_SHIFT (31U) -/*! LP_EN_1P0 - LP_EN_1P0 only controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG */ +/*! LP_EN_1P0 - Low-Power Enable */ #define DCDC_TRG_GPC_0_LP_EN_1P0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_0_LP_EN_1P0_SHIFT)) & DCDC_TRG_GPC_0_LP_EN_1P0_MASK) /*! @} */ @@ -712,7 +711,7 @@ typedef struct { #define DCDC_TRG_SW_1_LP_EN_1P0_MASK (0x80000000U) #define DCDC_TRG_SW_1_LP_EN_1P0_SHIFT (31U) -/*! LP_EN_1P0 - LP_EN_1P0 only controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG */ +/*! LP_EN_1P0 - Low-Power Enable */ #define DCDC_TRG_SW_1_LP_EN_1P0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_1_LP_EN_1P0_SHIFT)) & DCDC_TRG_SW_1_LP_EN_1P0_MASK) /*! @} */ @@ -733,7 +732,7 @@ typedef struct { #define DCDC_TRG_GPC_1_LP_EN_1P0_MASK (0x80000000U) #define DCDC_TRG_GPC_1_LP_EN_1P0_SHIFT (31U) -/*! LP_EN_1P0 - LP_EN_1P0 only controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG */ +/*! LP_EN_1P0 - Low-Power Enable */ #define DCDC_TRG_GPC_1_LP_EN_1P0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_1_LP_EN_1P0_SHIFT)) & DCDC_TRG_GPC_1_LP_EN_1P0_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DMA.h index f58755b5f..053756b88 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DMA.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DMA4.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DMA4.h index a07ad1a53..f86f87577 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DMA4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_DMA4.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA4 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ECAT.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ECAT.h index 73bd8db0e..1e2b71447 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ECAT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ECAT.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ECAT diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EIM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EIM.h index 21ae0fa28..ac7f4a01f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EIM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EIM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for EIM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_GLOBAL.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_GLOBAL.h index 721c651ed..612282e7e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_GLOBAL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_GLOBAL.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_GLOBAL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PCI_TYPE0.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PCI_TYPE0.h index fb47f45b6..ef990331a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PCI_TYPE0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PCI_TYPE0.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_PCI_TYPE0 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PF_EMDIO.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PF_EMDIO.h index 9f83f3cbe..e6ece7101 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PF_EMDIO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PF_EMDIO.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_PF_EMDIO diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PF_TMR.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PF_TMR.h index 1085b1b89..df9ff25fc 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PF_TMR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_PF_TMR.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_PF_TMR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_SI.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_SI.h index 79a3de7f7..76044614b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_SI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_SI.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_SI diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_VF_PCI_TYPE0.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_VF_PCI_TYPE0.h index 3be135298..2d721cad3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_VF_PCI_TYPE0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ENETC_VF_PCI_TYPE0.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ENETC_VF_PCI_TYPE0 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EQDC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EQDC.h index 963da618e..f993c6f5d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EQDC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EQDC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for EQDC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ERM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ERM.h index 586488739..a8bfd6ae9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ERM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_ERM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for ERM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EWM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EWM.h index 655c14101..895f26fee 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EWM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_EWM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for EWM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXIO.h index 13c255804..75bbb0471 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXIO.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXSPI.h index 4bd90e2cb..cf8c55009 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXSPI.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -129,11 +129,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 8u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 8u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 128u @@ -148,11 +148,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -163,7 +163,7 @@ typedef struct { uint8_t RESERVED_4[4]; __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_5[24]; __I uint32_t STS0; /**< Status 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status 1, offset: 0xE4 */ @@ -756,9 +756,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) - /*! @name FLSHCR0 - Flash Control 0 */ /*! @{ */ @@ -776,9 +773,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_ADDRSHIFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT)) & FLEXSPI_FLSHCR0_ADDRSHIFT_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control 1 */ /*! @{ */ @@ -819,9 +813,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control 2 */ /*! @{ */ @@ -870,9 +861,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control 4 */ /*! @{ */ @@ -1054,9 +1042,6 @@ typedef struct { #define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status 0 */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXSPI_SLV.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXSPI_SLV.h index 824a28b14..29eab3c3d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXSPI_SLV.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_FLEXSPI_SLV.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI_SLV diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_CPU_CTRL.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_CPU_CTRL.h index fe50ad144..026941eec 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_CPU_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_CPU_CTRL.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_CPU_CTRL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_GLOBAL.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_GLOBAL.h index fde7e136e..0f38eea5c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_GLOBAL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_GLOBAL.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_GLOBAL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_SYS_SLEEP_CTRL.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_SYS_SLEEP_CTRL.h index e2179072e..8d94e353c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_SYS_SLEEP_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPC_SYS_SLEEP_CTRL.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPC_SYS_SLEEP_CTRL @@ -302,6 +302,21 @@ typedef struct { /*! @name SS_PMIC_IN_CTRL - System Sleep PMIC in control */ /*! @{ */ +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_STEP_CNT_MASK (0xFFFFU) +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, useage depends on CNT_MODE */ +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_STEP_CNT_MASK) + +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_CNT_MODE_MASK) + #define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -314,6 +329,21 @@ typedef struct { /*! @name SS_PMIC_OUT_CTRL - System Sleep PMIC out control */ /*! @{ */ +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, useage depends on CNT_MODE */ +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_STEP_CNT_MASK) + +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_CNT_MODE_MASK) + #define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPT.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPT.h index 1acbc4db3..04a623640 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_GPT.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPT diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_I2S.h index bdb07bad5..ad2d66b1b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_I2S.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_I3C.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_I3C.h index 1af027cdc..a53f4694d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_I3C.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_I3C.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for I3C diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IEE.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IEE.h index 2acf90ff3..5fd50491b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IEE.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IEE.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IEE diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IEE_APC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IEE_APC.h index a5cd05dde..389941d68 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IEE_APC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IEE_APC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IEE_APC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IERC_IERB.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IERC_IERB.h index 335d78221..71b076c84 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IERC_IERB.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IERC_IERB.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IERC_IERB diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IERC_PCI.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IERC_PCI.h index 7e40e384e..47cb69890 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IERC_PCI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IERC_PCI.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IERC_PCI diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IOMUXC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IOMUXC.h index 4e6f6f1dd..5de7e6381 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IOMUXC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IOMUXC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IOMUXC_AON.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IOMUXC_AON.h index cf8b031d8..09faa5e8b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IOMUXC_AON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_IOMUXC_AON.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOMUXC_AON diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_KPP.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_KPP.h index 6fab4601e..f536c821e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_KPP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_KPP.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for KPP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPI2C.h index 0c66a1602..1479c46c7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPI2C.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPIT.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPIT.h index 993fb4d64..2514fdbca 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPIT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPIT.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPIT diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPSPI.h index 05d620c71..3a3fe12d0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPSPI.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPTMR.h index 3da6a03d7..db3fc727e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPTMR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPTMR.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPTMR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPUART.h index 3c47891ee..d7377c262 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_LPUART.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_M7_MCM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_M7_MCM.h index 19b32dbbe..bdcff2102 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_M7_MCM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_M7_MCM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for M7_MCM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MECC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MECC.h index 7f8142f36..2aefeb29a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MECC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MECC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MECC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MSGINTR.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MSGINTR.h index 0ef0594a2..1aeac38bd 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MSGINTR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MSGINTR.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MSGINTR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MU.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MU.h index e3841e992..5e16f7f54 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_MU.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_ENETC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_ENETC.h index 7cfe8f5a7..18e283824 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_ENETC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_ENETC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_ENETC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_ETH_LINK.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_ETH_LINK.h index b58870592..e91f13c60 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_ETH_LINK.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_ETH_LINK.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_ETH_LINK @@ -739,7 +739,10 @@ typedef struct { #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U) #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U) -/*! SW_ENTROPY_VALID - SW programmable entropy valid */ +/*! SW_ENTROPY_VALID - Software programmable entropy valid + * 0b0..Not valid + * 0b1..VALID + */ #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK) /*! @} */ @@ -1610,7 +1613,10 @@ typedef struct { #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U) #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U) -/*! SW_ENTROPY_VALID - SW programmable entropy valid */ +/*! SW_ENTROPY_VALID - Software programmable entropy valid + * 0b0..Not valid + * 0b1..VALID + */ #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_IERB.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_IERB.h index f000921a4..54cbd7d53 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_IERB.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_IERB.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_IERB diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PORT.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PORT.h index 74cb0f34a..bafa2649b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PORT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PORT.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_PORT @@ -556,7 +556,7 @@ typedef struct { #define NETC_PORT_PRXSDUOR_MACSEC_BCO_MASK (0x1F00U) #define NETC_PORT_PRXSDUOR_MACSEC_BCO_SHIFT (8U) -/*! MACSEC_BCO - MACSec byte count overhead */ +/*! MACSEC_BCO - MACsec byte count overhead */ #define NETC_PORT_PRXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXSDUOR_MACSEC_BCO_SHIFT)) & NETC_PORT_PRXSDUOR_MACSEC_BCO_MASK) /*! @} */ @@ -570,7 +570,7 @@ typedef struct { #define NETC_PORT_PTXSDUOR_MACSEC_BCO_MASK (0x1F00U) #define NETC_PORT_PTXSDUOR_MACSEC_BCO_SHIFT (8U) -/*! MACSEC_BCO - MACSec byte count overhead */ +/*! MACSEC_BCO - MACsec byte count overhead */ #define NETC_PORT_PTXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXSDUOR_MACSEC_BCO_SHIFT)) & NETC_PORT_PTXSDUOR_MACSEC_BCO_MASK) /*! @} */ @@ -937,14 +937,27 @@ typedef struct { #define NETC_PORT_PTCTMSDUR_MAXSDU_MASK (0xFFFFU) #define NETC_PORT_PTCTMSDUR_MAXSDU_SHIFT (0U) +/*! MAXSDU - Tx Maximum Service Data Unit Size */ #define NETC_PORT_PTCTMSDUR_MAXSDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCTMSDUR_MAXSDU_SHIFT)) & NETC_PORT_PTCTMSDUR_MAXSDU_MASK) #define NETC_PORT_PTCTMSDUR_SDU_TYPE_MASK (0x30000U) #define NETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT (16U) +/*! SDU_TYPE - SDU type + * 0b00..PPDU (Physical Layer PDU). Includes preamble, IPG, SFD along with MPDU. The overhead (number of bytes) + * to be added to the actual length of each frame, to reflect the PPDU (Physical Layer PDU) frame length, is + * specified in the register PTXSDUOR. + * 0b01..MPDU (MAC PDU). Includes MAC Header, MSDU and FCS. The frame length can be adjusted if a link has MACsec + * enabled (such as MACsec enabled in a PHY). The MACsec overhead is specified in register PTXSDUOR. + * 0b10..MSDU (MAC SDU); MPDU minus 12B MAC Header and 4B FCS. The frame length is adjusted by subtracting 16 bytes from it. + */ #define NETC_PORT_PTCTMSDUR_SDU_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT)) & NETC_PORT_PTCTMSDUR_SDU_TYPE_MASK) #define NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK (0x1000000U) #define NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT (24U) +/*! SF_MAXSDU_DIS + * 0b0..Enabled + * 0b1..Disabled + */ #define NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT)) & NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK) /*! @} */ @@ -1069,8 +1082,8 @@ typedef struct { #define NETC_PORT_PPCPDEIMR_DRME_MASK (0x100000U) #define NETC_PORT_PPCPDEIMR_DRME_SHIFT (20U) /*! DRME - * 0b0..Preserve the DR value in the outer VLAN. - * 0b1..Update DR value in the outer VLAN based on DEnDEI field. + * 0b0..Preserve the DEI value in the outer VLAN. + * 0b1..Update DEI value in the outer VLAN based on DRnDEI field. */ #define NETC_PORT_PPCPDEIMR_DRME(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_DRME_SHIFT)) & NETC_PORT_PPCPDEIMR_DRME_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PRIV.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PRIV.h index cb8153174..c84da223e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PRIV.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PRIV.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_PRIV diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PSEUDO_LINK.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PSEUDO_LINK.h index d0c31372b..e62d93161 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PSEUDO_LINK.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_PSEUDO_LINK.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_PSEUDO_LINK diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_SW.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_SW.h index c2a9a07a8..3a430370a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_SW.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_SW.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_SW @@ -403,19 +403,22 @@ typedef struct { #define NETC_SW_IMDCR0_MIRDEST_MASK (0x2U) #define NETC_SW_IMDCR0_MIRDEST_SHIFT (1U) -/*! MIRDEST - Indicates the mirror destination */ +/*! MIRDEST - Mirror destination */ #define NETC_SW_IMDCR0_MIRDEST(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR0_MIRDEST_SHIFT)) & NETC_SW_IMDCR0_MIRDEST_MASK) #define NETC_SW_IMDCR0_IPV_MASK (0x1CU) #define NETC_SW_IMDCR0_IPV_SHIFT (2U) +/*! IPV - Internal Priority Value (IPV) */ #define NETC_SW_IMDCR0_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR0_IPV_SHIFT)) & NETC_SW_IMDCR0_IPV_MASK) #define NETC_SW_IMDCR0_DR_MASK (0xC0U) #define NETC_SW_IMDCR0_DR_SHIFT (6U) +/*! DR - Drop Resilience (DR) */ #define NETC_SW_IMDCR0_DR(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR0_DR_SHIFT)) & NETC_SW_IMDCR0_DR_MASK) #define NETC_SW_IMDCR0_PORT_MASK (0x1F00U) #define NETC_SW_IMDCR0_PORT_SHIFT (8U) +/*! PORT - Port number. */ #define NETC_SW_IMDCR0_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR0_PORT_SHIFT)) & NETC_SW_IMDCR0_PORT_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_SW_ENETC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_SW_ENETC.h index a05a7f54c..8d20ca8e5 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_SW_ENETC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_NETC_SW_ENETC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for NETC_SW_ENETC @@ -175,9 +175,9 @@ typedef struct { __I uint32_t TCRPTSR; /**< Time capture receive port timestamp register, offset: 0x1114, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */ __IO uint32_t TCMSIVR; /**< Time capture MSI-X vector register, offset: 0x1118, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */ uint8_t RESERVED_11[228]; - __IO uint32_t CVLANR1; /**< Custom VLAN Ethertype register 1, offset: 0x1200 */ - __IO uint32_t CVLANR2; /**< Custom VLAN Ethertype register 2, offset: 0x1204 */ - __IO uint32_t PSRTAGETR; /**< Pre-Standard RTAG Ethertype register, offset: 0x1208, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */ + __IO uint32_t CVLANR1; /**< Custom VLAN EtherType register 1, offset: 0x1200 */ + __IO uint32_t CVLANR2; /**< Custom VLAN EtherType register 2, offset: 0x1204 */ + __IO uint32_t PSRTAGETR; /**< Pre-Standard RTAG EtherType register, offset: 0x1208, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */ uint8_t RESERVED_12[20]; __IO uint32_t DOSL2CR; /**< DoS L2 configuration register, offset: 0x1220 */ uint8_t RESERVED_13[220]; @@ -740,7 +740,7 @@ typedef struct { #define NETC_SW_ENETC_TCMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCMSIVR_VECTOR_SHIFT)) & NETC_SW_ENETC_TCMSIVR_VECTOR_MASK) /*! @} */ -/*! @name CVLANR1 - Custom VLAN Ethertype register 1 */ +/*! @name CVLANR1 - Custom VLAN EtherType register 1 */ /*! @{ */ #define NETC_SW_ENETC_CVLANR1_ETYPE_MASK (0xFFFFU) @@ -753,7 +753,7 @@ typedef struct { #define NETC_SW_ENETC_CVLANR1_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR1_V_SHIFT)) & NETC_SW_ENETC_CVLANR1_V_MASK) /*! @} */ -/*! @name CVLANR2 - Custom VLAN Ethertype register 2 */ +/*! @name CVLANR2 - Custom VLAN EtherType register 2 */ /*! @{ */ #define NETC_SW_ENETC_CVLANR2_ETYPE_MASK (0xFFFFU) @@ -766,7 +766,7 @@ typedef struct { #define NETC_SW_ENETC_CVLANR2_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR2_V_SHIFT)) & NETC_SW_ENETC_CVLANR2_V_MASK) /*! @} */ -/*! @name PSRTAGETR - Pre-Standard RTAG Ethertype register */ +/*! @name PSRTAGETR - Pre-Standard RTAG EtherType register */ /*! @{ */ #define NETC_SW_ENETC_PSRTAGETR_ETHERTYPE_MASK (0xFFFFU) @@ -1533,8 +1533,8 @@ typedef struct { #define NETC_SW_ENETC_ISIDKC0CR0_OVIDP_MASK (0x20U) #define NETC_SW_ENETC_ISIDKC0CR0_OVIDP_SHIFT (5U) /*! OVIDP - Outer VID Present - * 0b0..Not present - * 0b1..Present + * 0b0..Outer VLAN ID is not present in the key + * 0b1..Outer VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC0CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_OVIDP_MASK) @@ -1549,16 +1549,16 @@ typedef struct { #define NETC_SW_ENETC_ISIDKC0CR0_IVIDP_MASK (0x80U) #define NETC_SW_ENETC_ISIDKC0CR0_IVIDP_SHIFT (7U) /*! IVIDP - Inner VID Present. - * 0b0..Not present - * 0b1..Present + * 0b0..Inner VLAN ID is not present in the key + * 0b1..Inner VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC0CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_IVIDP_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_IPCPP_MASK (0x100U) #define NETC_SW_ENETC_ISIDKC0CR0_IPCPP_SHIFT (8U) -/*! IPCPP - Inner PCP Present. - * 0b0..Not present - * 0b1..Present +/*! IPCPP - Inner PCP Present + * 0b0..Inner PCP is not present in the key + * 0b1..Inner PCP is present in the key */ #define NETC_SW_ENETC_ISIDKC0CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_IPCPP_MASK) @@ -1733,8 +1733,8 @@ typedef struct { #define NETC_SW_ENETC_ISIDKC1CR0_OVIDP_MASK (0x20U) #define NETC_SW_ENETC_ISIDKC1CR0_OVIDP_SHIFT (5U) /*! OVIDP - Outer VID Present - * 0b0..Not present - * 0b1..Present + * 0b0..Outer VLAN ID is not present in the key + * 0b1..Outer VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC1CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_OVIDP_MASK) @@ -1749,16 +1749,16 @@ typedef struct { #define NETC_SW_ENETC_ISIDKC1CR0_IVIDP_MASK (0x80U) #define NETC_SW_ENETC_ISIDKC1CR0_IVIDP_SHIFT (7U) /*! IVIDP - Inner VID Present. - * 0b0..Not present - * 0b1..Present + * 0b0..Inner VLAN ID is not present in the key + * 0b1..Inner VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC1CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_IVIDP_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_IPCPP_MASK (0x100U) #define NETC_SW_ENETC_ISIDKC1CR0_IPCPP_SHIFT (8U) -/*! IPCPP - Inner PCP Present. - * 0b0..Not present - * 0b1..Present +/*! IPCPP - Inner PCP Present + * 0b0..Inner PCP is not present in the key + * 0b1..Inner PCP is present in the key */ #define NETC_SW_ENETC_ISIDKC1CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_IPCPP_MASK) @@ -1933,8 +1933,8 @@ typedef struct { #define NETC_SW_ENETC_ISIDKC2CR0_OVIDP_MASK (0x20U) #define NETC_SW_ENETC_ISIDKC2CR0_OVIDP_SHIFT (5U) /*! OVIDP - Outer VID Present - * 0b0..Not present - * 0b1..Present + * 0b0..Outer VLAN ID is not present in the key + * 0b1..Outer VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC2CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_OVIDP_MASK) @@ -1949,16 +1949,16 @@ typedef struct { #define NETC_SW_ENETC_ISIDKC2CR0_IVIDP_MASK (0x80U) #define NETC_SW_ENETC_ISIDKC2CR0_IVIDP_SHIFT (7U) /*! IVIDP - Inner VID Present. - * 0b0..Not present - * 0b1..Present + * 0b0..Inner VLAN ID is not present in the key + * 0b1..Inner VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC2CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_IVIDP_MASK) #define NETC_SW_ENETC_ISIDKC2CR0_IPCPP_MASK (0x100U) #define NETC_SW_ENETC_ISIDKC2CR0_IPCPP_SHIFT (8U) -/*! IPCPP - Inner PCP Present. - * 0b0..Not present - * 0b1..Present +/*! IPCPP - Inner PCP Present + * 0b0..Inner PCP is not present in the key + * 0b1..Inner PCP is present in the key */ #define NETC_SW_ENETC_ISIDKC2CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_IPCPP_MASK) @@ -2133,8 +2133,8 @@ typedef struct { #define NETC_SW_ENETC_ISIDKC3CR0_OVIDP_MASK (0x20U) #define NETC_SW_ENETC_ISIDKC3CR0_OVIDP_SHIFT (5U) /*! OVIDP - Outer VID Present - * 0b0..Not present - * 0b1..Present + * 0b0..Outer VLAN ID is not present in the key + * 0b1..Outer VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC3CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_OVIDP_MASK) @@ -2149,16 +2149,16 @@ typedef struct { #define NETC_SW_ENETC_ISIDKC3CR0_IVIDP_MASK (0x80U) #define NETC_SW_ENETC_ISIDKC3CR0_IVIDP_SHIFT (7U) /*! IVIDP - Inner VID Present. - * 0b0..Not present - * 0b1..Present + * 0b0..Inner VLAN ID is not present in the key + * 0b1..Inner VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC3CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_IVIDP_MASK) #define NETC_SW_ENETC_ISIDKC3CR0_IPCPP_MASK (0x100U) #define NETC_SW_ENETC_ISIDKC3CR0_IPCPP_SHIFT (8U) -/*! IPCPP - Inner PCP Present. - * 0b0..Not present - * 0b1..Present +/*! IPCPP - Inner PCP Present + * 0b0..Inner PCP is not present in the key + * 0b1..Inner PCP is present in the key */ #define NETC_SW_ENETC_ISIDKC3CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_IPCPP_MASK) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OCOTP_FSB.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OCOTP_FSB.h index 1d5707bb1..6d49739e9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OCOTP_FSB.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OCOTP_FSB.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for OCOTP_FSB diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OSC_RC_400M.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OSC_RC_400M.h index f3a04aa83..8f04c1138 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OSC_RC_400M.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OSC_RC_400M.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSC_RC_400M diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OTFAD.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OTFAD.h index d623c05e8..2198b4985 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OTFAD.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_OTFAD.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for OTFAD diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PDM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PDM.h index c84be5411..a5b0a3525 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PDM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PDM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PDM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PHY_LDO.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PHY_LDO.h index 042b86faa..9e8902c64 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PHY_LDO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PHY_LDO.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PHY_LDO diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PLL.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PLL.h index 31d6c198e..2d3895a7a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PLL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PLL.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PLL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PWM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PWM.h index 68ebc4c29..9a0e8d324 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PWM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_PWM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for PWM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_RGPIO.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_RGPIO.h index 5b0842a23..38e7b1a7e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_RGPIO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_RGPIO.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for RGPIO diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_RTWDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_RTWDOG.h index 6636cb083..d025f577c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_RTWDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_RTWDOG.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTWDOG diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_S3MU.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_S3MU.h index 5ac34af47..eade81932 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_S3MU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_S3MU.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for S3MU diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SEMA42.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SEMA42.h index 53eb3e103..36697631d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SEMA42.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SEMA42.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMA42 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SEMC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SEMC.h index af0dcadce..18e8a4755 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SEMC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SEMC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SINC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SINC.h index fb5e4145c..2de84063c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SINC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SINC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SINC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SPDIF.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SPDIF.h index 51cc7b10c..5722b6e71 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SPDIF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SPDIF.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPDIF diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_GENERAL.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_GENERAL.h index c4084d0fd..a21e7a626 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_GENERAL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_GENERAL.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_GENERAL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_LN28FDSOI_SPLLRAM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_LN28FDSOI_SPLLRAM.h index bd5a40540..1e63ae9ee 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_LN28FDSOI_SPLLRAM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_LN28FDSOI_SPLLRAM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_MIF_LN28FDSOI_SPLLRAM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_S28SPREGH.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_S28SPREGH.h index 0e5eda61f..ebb901afb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_S28SPREGH.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_S28SPREGH.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_MIF_S28SPREGH diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_S28SPREGH_PSWA.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_S28SPREGH_PSWA.h index 1870f43ce..c6535cce9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_S28SPREGH_PSWA.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIF_S28SPREGH_PSWA.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_MIF_S28SPREGH_PSWA diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIX_SLICE.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIX_SLICE.h index 61d3cf447..f72b6e598 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIX_SLICE.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SRC_MIX_SLICE.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SRC_MIX_SLICE diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYSPM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYSPM.h index b86a1c6b4..2b2675535 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYSPM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYSPM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSPM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_COMPARE.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_COMPARE.h index f49e11332..cd103a9a4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_COMPARE.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_COMPARE.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYS_CTR_COMPARE diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_CONTROL.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_CONTROL.h index 64fdd7cb7..b881584fe 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_CONTROL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_CONTROL.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYS_CTR_CONTROL diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_READ.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_READ.h index a3e66e41c..49df7f561 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_READ.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_SYS_CTR_READ.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYS_CTR_READ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TCM_ECC_MCM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TCM_ECC_MCM.h index fefe78493..dede4319f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TCM_ECC_MCM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TCM_ECC_MCM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TCM_ECC_MCM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TMPSNS.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TMPSNS.h index 694a1202b..50f9841da 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TMPSNS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TMPSNS.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMPSNS diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TMR.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TMR.h index 16ff1c46e..8c6ceb6a3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TMR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TMR.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TMR diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TPM.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TPM.h index 37967e7da..68a3aa5df 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TPM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TPM.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TPM diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TRDC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TRDC.h index f87b9287c..6c97bc16c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TRDC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TRDC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TSTMR.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TSTMR.h index 0e4a135b3..6e8533f0f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TSTMR.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_TSTMR.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for TSTMR @@ -166,9 +166,6 @@ typedef struct { * @} */ /* end of group TSTMR_Register_Masks */ -/* Extra definition */ -#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) - /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USB.h index bbf2d434c..0116ddd3d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USB.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBHSDCD.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBHSDCD.h index b9b431a92..c888fb2bc 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBHSDCD.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBHSDCD.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBHSDCD diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBNC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBNC.h index 5eb82eb0a..e1d99a8f7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBNC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBNC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBNC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBPHY.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBPHY.h index 4f9aecbf1..e13502929 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBPHY.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USBPHY.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBPHY diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USDHC.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USDHC.h index 19a016e3a..563577471 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USDHC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_USDHC.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for USDHC diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_VMBANDGAP.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_VMBANDGAP.h index 1b1008baf..6932802c1 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_VMBANDGAP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_VMBANDGAP.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for VMBANDGAP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_VREF.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_VREF.h index 4e2b2ef8f..bafa11cf0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_VREF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_VREF.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for VREF diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XBAR_NUM_OUT221.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XBAR_NUM_OUT221.h index 255e547bd..3324c920f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XBAR_NUM_OUT221.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XBAR_NUM_OUT221.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBAR_NUM_OUT221 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XBAR_NUM_OUT32.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XBAR_NUM_OUT32.h index 998edb96e..2e24c50b4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XBAR_NUM_OUT32.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XBAR_NUM_OUT32.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for XBAR_NUM_OUT32 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XCACHE.h b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XCACHE.h index 1dfcaeeeb..d0f45fd9d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XCACHE.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT1180/periph/PERI_XCACHE.h @@ -34,7 +34,7 @@ ** MIMXRT1189XVM8C_cm7 ** ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCACHE diff --git a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT533S/MIMXRT533S_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT533S/MIMXRT533S_COMMON.h index 158be8c75..973378994 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT533S/MIMXRT533S_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT533S/MIMXRT533S_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: iMXRT500RM Rev.1, 07/2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT533S @@ -1044,29 +1044,27 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u}, {0x38000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu}, {0x3FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u}, {0x28000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu}, {0x2FFFFFFFu} } -/* FlexSPI0 AMBA address. */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) -/* FlexSPI1 AMBA address. */ -#define FlexSPI1_AMBA_BASE (0x38000000u) -#define FlexSPI1_AMBA_BASE_NS (0x28000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u}, {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u}, {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu}, {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu}, {0x2FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /* FlexSPI1 AMBA address. */ + #define FlexSPI1_AMBA_BASE (0x38000000u) + #define FlexSPI1_AMBA_BASE_NS (0x28000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u}, {0x28000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu}, {0x2FFFFFFFu} } -/* FlexSPI0 AMBA address. */ -#define FlexSPI0_AMBA_BASE (0x08000000u) -/* FlexSPI1 AMBA address. */ -#define FlexSPI1_AMBA_BASE (0x28000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u}, {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu}, {0x2FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x08000000u) + /* FlexSPI1 AMBA address. */ + #define FlexSPI1_AMBA_BASE (0x28000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT533S/MIMXRT533S_features.h b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT533S/MIMXRT533S_features.h index b4115f934..0259d3846 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT533S/MIMXRT533S_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT533S/MIMXRT533S_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2020-05-18 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -154,8 +154,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -168,6 +166,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -262,11 +262,6 @@ /* @brief Base address of the CASPER dedicated RAM. */ #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x40202000u) -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - /* CTIMER module features */ /* @brief CTIMER has no capture channel. */ @@ -454,8 +449,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -484,43 +477,69 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1) -/* @brief FlexSPI has no MCR0 ARDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) -/* @brief FlexSPI has no MCR0 ATDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) -/* @brief FlexSPI uses min DQS delay */ -#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1) -/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) /* @brief FLEXSPI has no IP parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) /* @brief FlexSPI has no FLSHCR4 WMENB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) -/* @brief Has Errata 051426 */ -#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (1) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) \ (((x) == FLEXSPI0) ? (1024) : \ (((x) == FLEXSPI1) ? (2048) : (-1))) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (2) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (1) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPIO module features */ @@ -553,14 +572,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -654,6 +673,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECGPIO module features */ @@ -752,6 +773,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) /* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MIMXRT533S_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT555S/MIMXRT555S_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT555S/MIMXRT555S_COMMON.h index fa049c0e5..4a3be972e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT555S/MIMXRT555S_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT555S/MIMXRT555S_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: iMXRT500RM Rev.1, 07/2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT555S @@ -1047,29 +1047,27 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u}, {0x38000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu}, {0x3FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u}, {0x28000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu}, {0x2FFFFFFFu} } -/* FlexSPI0 AMBA address. */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) -/* FlexSPI1 AMBA address. */ -#define FlexSPI1_AMBA_BASE (0x38000000u) -#define FlexSPI1_AMBA_BASE_NS (0x28000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u}, {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u}, {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu}, {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu}, {0x2FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /* FlexSPI1 AMBA address. */ + #define FlexSPI1_AMBA_BASE (0x38000000u) + #define FlexSPI1_AMBA_BASE_NS (0x28000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u}, {0x28000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu}, {0x2FFFFFFFu} } -/* FlexSPI0 AMBA address. */ -#define FlexSPI0_AMBA_BASE (0x08000000u) -/* FlexSPI1 AMBA address. */ -#define FlexSPI1_AMBA_BASE (0x28000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u}, {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu}, {0x2FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x08000000u) + /* FlexSPI1 AMBA address. */ + #define FlexSPI1_AMBA_BASE (0x28000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT555S/MIMXRT555S_features.h b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT555S/MIMXRT555S_features.h index 5e27c33a5..bd2dbfdcf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT555S/MIMXRT555S_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT555S/MIMXRT555S_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2020-05-18 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -158,8 +158,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -172,6 +170,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -266,11 +266,6 @@ /* @brief Base address of the CASPER dedicated RAM. */ #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x40202000u) -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - /* CTIMER module features */ /* @brief CTIMER has no capture channel. */ @@ -458,8 +453,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -488,43 +481,69 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1) -/* @brief FlexSPI has no MCR0 ARDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) -/* @brief FlexSPI has no MCR0 ATDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) -/* @brief FlexSPI uses min DQS delay */ -#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1) -/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) /* @brief FLEXSPI has no IP parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) /* @brief FlexSPI has no FLSHCR4 WMENB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) -/* @brief Has Errata 051426 */ -#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (1) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) \ (((x) == FLEXSPI0) ? (1024) : \ (((x) == FLEXSPI1) ? (2048) : (-1))) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (2) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (1) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPIO module features */ @@ -557,14 +576,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -676,6 +695,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECGPIO module features */ @@ -774,6 +795,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) /* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MIMXRT555S_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_cm33_COMMON.h index aae1ce054..0720198c5 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_cm33_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: iMXRT500RM Rev.1, 07/2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT595S_cm33 @@ -1048,29 +1048,27 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u}, {0x38000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu}, {0x3FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u}, {0x28000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu}, {0x2FFFFFFFu} } -/* FlexSPI0 AMBA address. */ -#define FlexSPI0_AMBA_BASE (0x18000000u) -#define FlexSPI0_AMBA_BASE_NS (0x08000000u) -/* FlexSPI1 AMBA address. */ -#define FlexSPI1_AMBA_BASE (0x38000000u) -#define FlexSPI1_AMBA_BASE_NS (0x28000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u}, {0x38000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u}, {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu}, {0x3FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu}, {0x2FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x18000000u) + #define FlexSPI0_AMBA_BASE_NS (0x08000000u) + /* FlexSPI1 AMBA address. */ + #define FlexSPI1_AMBA_BASE (0x38000000u) + #define FlexSPI1_AMBA_BASE_NS (0x28000000u) #else -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u}, {0x28000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu}, {0x2FFFFFFFu} } -/* FlexSPI0 AMBA address. */ -#define FlexSPI0_AMBA_BASE (0x08000000u) -/* FlexSPI1 AMBA address. */ -#define FlexSPI1_AMBA_BASE (0x28000000u) + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u}, {0x28000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu}, {0x2FFFFFFFu} } + /* FlexSPI0 AMBA address. */ + #define FlexSPI0_AMBA_BASE (0x08000000u) + /* FlexSPI1 AMBA address. */ + #define FlexSPI1_AMBA_BASE (0x28000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_cm33_features.h b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_cm33_features.h index 6dd493c94..94b94106e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2020-05-18 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -158,8 +158,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -172,6 +170,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -266,11 +266,6 @@ /* @brief Base address of the CASPER dedicated RAM. */ #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x40202000u) -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - /* CTIMER module features */ /* @brief CTIMER has no capture channel. */ @@ -458,8 +453,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -488,43 +481,69 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1) -/* @brief FlexSPI has no MCR0 ARDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) -/* @brief FlexSPI has no MCR0 ATDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) -/* @brief FlexSPI uses min DQS delay */ -#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1) -/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) /* @brief FLEXSPI has no IP parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) /* @brief FlexSPI has no FLSHCR4 WMENB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) -/* @brief Has Errata 051426 */ -#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (1) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) \ (((x) == FLEXSPI0) ? (1024) : \ (((x) == FLEXSPI1) ? (2048) : (-1))) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (2) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (1) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPIO module features */ @@ -557,14 +576,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -676,6 +695,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SECGPIO module features */ @@ -774,6 +795,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) /* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MIMXRT595S_cm33_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_dsp_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_dsp_COMMON.h index 547cd00c3..d50511878 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_dsp_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_dsp_COMMON.h @@ -6,7 +6,7 @@ ** Compiler: Xtensa Compiler ** Reference manual: iMXRT500RM Rev.1, 07/2022 ** Version: rev. 6.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** Peripheral Access Layer for MIMXRT595S_dsp diff --git a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_dsp_features.h b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_dsp_features.h index fca955317..5812741ef 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_dsp_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT500/MIMXRT595S/MIMXRT595S_dsp_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 4.0, 2020-05-18 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -152,8 +152,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -166,6 +164,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -260,11 +260,6 @@ /* @brief Base address of the CASPER dedicated RAM. */ #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x40202000u) -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - /* CTIMER module features */ /* @brief CTIMER has no capture channel. */ @@ -452,8 +447,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -482,43 +475,69 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* FLEXSPI module features */ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ -#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1) -/* @brief FlexSPI has no MCR0 ARDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) -/* @brief FlexSPI has no MCR0 ATDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI DMA needs multiple DES to transfer */ -#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) -/* @brief FlexSPI uses min DQS delay */ -#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1) -/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) /* @brief FLEXSPI has no IP parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) /* @brief FlexSPI has no FLSHCR4 WMENB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) /* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) -/* @brief Has Errata 051426 */ -#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (1) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) \ (((x) == FLEXSPI0) ? (1024) : \ (((x) == FLEXSPI1) ? (2048) : (-1))) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (2) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (1) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* GPIO module features */ @@ -551,14 +570,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -740,6 +759,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) /* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MIMXRT595S_dsp_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT633S/MIMXRT633S_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT633S/MIMXRT633S_COMMON.h index d4c9f913f..7eac75810 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT633S/MIMXRT633S_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT633S/MIMXRT633S_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: MIMXRT685 User manual Rev. 1.8 21 November 2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT633S @@ -822,24 +822,24 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } -/** FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } -/* FlexSPI AMBA address. */ -#define FlexSPI_AMBA_BASE (0x18000000u) -#define FlexSPI_AMBA_BASE_NS (0x08000000u) + /** FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } + /** FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } + /* FlexSPI AMBA address. */ + #define FlexSPI_AMBA_BASE (0x18000000u) + #define FlexSPI_AMBA_BASE_NS (0x08000000u) #else -/** FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } -/** FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } -/* FlexSPI AMBA address. */ -#define FlexSPI_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } + /** FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } + /* FlexSPI AMBA address. */ + #define FlexSPI_AMBA_BASE (0x08000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT633S/MIMXRT633S_features.h b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT633S/MIMXRT633S_features.h index a71f8d307..cddc01979 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT633S/MIMXRT633S_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT633S/MIMXRT633S_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-06-19 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -233,8 +233,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -247,14 +245,11 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - /* CTIMER module features */ /* @brief CTIMER has no capture channel. */ @@ -387,22 +382,60 @@ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI has no MCR0 ARDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) -/* @brief FlexSPI has no MCR0 ATDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0) /* @brief FLEXSPI has no IP parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPIO module features */ @@ -435,14 +468,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -534,6 +567,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -622,6 +657,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) /* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MIMXRT633S_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_cm33_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_cm33_COMMON.h index b86f95875..816fbb2e4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_cm33_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_cm33_COMMON.h @@ -12,7 +12,7 @@ ** ** Reference manual: MIMXRT685 User manual Rev. 1.8 21 November 2024 ** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT685S_cm33 @@ -823,24 +823,24 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/** FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } -/** FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } -/** FlexSPI AMBA base address array */ -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } -/** FlexSPI AMBA end address array */ -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } -/* FlexSPI AMBA address. */ -#define FlexSPI_AMBA_BASE (0x18000000u) -#define FlexSPI_AMBA_BASE_NS (0x08000000u) + /** FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u} } + /** FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu} } + /** FlexSPI AMBA base address array */ + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u} } + /** FlexSPI AMBA end address array */ + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu} } + /* FlexSPI AMBA address. */ + #define FlexSPI_AMBA_BASE (0x18000000u) + #define FlexSPI_AMBA_BASE_NS (0x08000000u) #else -/** FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } -/** FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } -/* FlexSPI AMBA address. */ -#define FlexSPI_AMBA_BASE (0x08000000u) + /** FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u} } + /** FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu} } + /* FlexSPI AMBA address. */ + #define FlexSPI_AMBA_BASE (0x08000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_cm33_features.h b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_cm33_features.h index f7a82f775..bfdfe234e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_cm33_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_cm33_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-06-19 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -233,8 +233,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -247,14 +245,11 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - /* CTIMER module features */ /* @brief CTIMER has no capture channel. */ @@ -387,22 +382,60 @@ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI has no MCR0 ARDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) -/* @brief FlexSPI has no MCR0 ATDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0) /* @brief FLEXSPI has no IP parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPIO module features */ @@ -435,14 +468,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -534,6 +567,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -622,6 +657,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) /* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MIMXRT685S_cm33_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_dsp_features.h b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_dsp_features.h index 7b73610bf..3c3d7fb51 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_dsp_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT600/MIMXRT685S/MIMXRT685S_dsp_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2018-06-19 -** Build: b250512 +** Build: b250812 ** ** Abstract: ** Chip specific module features. @@ -210,8 +210,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -224,14 +222,11 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (0) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (1) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - /* CTIMER module features */ /* @brief CTIMER has no capture channel. */ @@ -364,22 +359,60 @@ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) -/* @brief FlexSPI has no MCR0 ARDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) -/* @brief FlexSPI has no MCR0 ATDFEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) -/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0) /* @brief FLEXSPI has no IP parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) /* @brief FLEXSPI has no AHB parallel mode. */ #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) /* @brief FLEXSPI support address shift. */ #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) /* @brief FlexSPI AHB RX buffer size (byte) */ #define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI Array Length */ #define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) +/* @brief FlexSPI support sample clock source selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (0) +/* @brief FlexSPI support sample clock source or source_b selection */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (0) +/* @brief FlexSPI IPED REGION COUNT */ +#define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (0) +/* @brief FlexSPI Has ERRATA052733 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (0) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (0) /* GPIO module features */ @@ -407,14 +440,14 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (0) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ -#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_051617. */ #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) -/* @brief Has ERRATA_052123. */ -#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) /* @brief Has ERRATA_052086. */ #define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (1) /* @brief Has IBI bytes. */ #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) /* @brief Has SCL delay after START. */ @@ -556,6 +589,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) /* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _MIMXRT685S_dsp_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0.h index 03a921293..26058962c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGFOA_cm33_core0 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core0 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT735S_cm33_core0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core0 * * CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core0 @@ -82,6 +85,7 @@ #include "PERI_LPSPI.h" #include "PERI_LPUART.h" #include "PERI_LP_FLEXCOMM.h" +#include "PERI_MIPI_DSI_HOST.h" #include "PERI_MMU.h" #include "PERI_MRT.h" #include "PERI_MU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0_COMMON.h index 2ad859c57..19815cb98 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0_COMMON.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGFOA_cm33_core0 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core0 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT735S_cm33_core0_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core0 * * CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core0 @@ -48,7 +51,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -140,7 +143,7 @@ typedef enum IRQn { FLEXIO_IRQn = 55, /**< FLEXIO: Interrupt request */ Reserved72_IRQn = 56, /**< Reserved interrupt */ Reserved73_IRQn = 57, /**< Reserved interrupt */ - Reserved74_IRQn = 58, /**< Reserved interrupt */ + MIPI_IRQn = 58, /**< DSI: Interrupt request */ EDMA0_CH0_IRQn = 59, /**< EDMA: Channel 0 interrupt */ EDMA0_CH1_IRQn = 60, /**< EDMA: Channel 1 interrupt */ EDMA0_CH2_IRQn = 61, /**< EDMA: Channel 2 interrupt */ @@ -2732,6 +2735,37 @@ typedef enum _dma_request_source /** Interrupt vectors for the LP_FLEXCOMM peripheral type */ #define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn, LP_FLEXCOMM8_IRQn, LP_FLEXCOMM9_IRQn, LP_FLEXCOMM10_IRQn, LP_FLEXCOMM11_IRQn, LP_FLEXCOMM12_IRQn, LP_FLEXCOMM13_IRQn } +/* MIPI_DSI_HOST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MIPI_DSI_HOST base address */ + #define MIPI_DSI_HOST_BASE (0x50417000u) + /** Peripheral MIPI_DSI_HOST base address */ + #define MIPI_DSI_HOST_BASE_NS (0x40417000u) + /** Peripheral MIPI_DSI_HOST base pointer */ + #define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) + /** Peripheral MIPI_DSI_HOST base pointer */ + #define MIPI_DSI_HOST_NS ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE_NS) + /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ + #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE } + /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ + #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST } + /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ + #define MIPI_DSI_HOST_BASE_ADDRS_NS { MIPI_DSI_HOST_BASE_NS } + /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ + #define MIPI_DSI_HOST_BASE_PTRS_NS { MIPI_DSI_HOST_NS } +#else + /** Peripheral MIPI_DSI_HOST base address */ + #define MIPI_DSI_HOST_BASE (0x40417000u) + /** Peripheral MIPI_DSI_HOST base pointer */ + #define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) + /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ + #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE } + /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ + #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST } +#endif +/** Interrupt vectors for the MIPI_DSI_HOST peripheral type */ +#define MIPI_DSI_HOST_IRQS { MIPI_IRQn } + /* MMU - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral MMU0 base address */ @@ -3412,6 +3446,9 @@ typedef enum _dma_request_source /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC0 } #endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_ALARM_IRQS { RTC0_ALARM_IRQn } +#define RTC_WAKEUP_IRQS { RTC0_IRQn } /* SCT - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0_features.h index 68b73b924..8cdc9b9b8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -65,6 +67,8 @@ #define FSL_FEATURE_SOC_LPSPI_COUNT (16) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (14) +/* @brief MIPI_DSI_HOST availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1) /* @brief MPU availability on the SoC. */ #define FSL_FEATURE_SOC_MPU_COUNT (1) /* @brief MRT availability on the SoC. */ @@ -134,8 +138,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -148,6 +150,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -364,8 +368,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -394,6 +396,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -491,8 +495,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -535,6 +537,31 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MIPI_DSI_HOST module features */ + +/* @brief Does not have DPHY PLL(DPHY_CM) */ +#define FSL_FEATURE_MIPI_DSI_HOST_NO_DPHY_PLL (1) +/* @brief Support TX ULPS */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS (1) +/* @brief Has control register to enable or disable TX ULPS */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS_CTRL (0) +/* @brief Has pixel-link to DPI remap */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PXL2DPI (0) +/* @brief Has DBI Pixel Format register */ +#define FSL_FEATURE_MIPI_DSI_HOST_DBI_HAS_PIXEL_FORMAT (1) +/* @brief Has PHY ready status register */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PHY_RDY (1) +/* @brief Has HS control HS_MODE_ENABLE register */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_HS_CTRL (1) +/* @brief Has bitfield HOST_TURNAROUND[REQUEST_BTA] */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_BTA_CTRL (1) +/* @brief Has separate ULPS control */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_SEPARATE_ULPS_CTRL (1) /* MRT module features */ @@ -705,6 +732,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -716,6 +745,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -814,6 +845,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XCACHE module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1.h index 69aac4826..2151d1a86 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGFOA_cm33_core1 +** Processors: MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core1 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT735S_cm33_core1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core1 * * CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core1 @@ -73,6 +76,7 @@ #include "PERI_LPSPI.h" #include "PERI_LPUART.h" #include "PERI_LP_FLEXCOMM.h" +#include "PERI_MIPI_DSI_HOST.h" #include "PERI_MMU.h" #include "PERI_MRT.h" #include "PERI_MU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1_COMMON.h index 9d2792ff3..14a630495 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1_COMMON.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGFOA_cm33_core1 +** Processors: MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core1 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT735S_cm33_core1_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core1 * * CMSIS Peripheral Access Layer for MIMXRT735S_cm33_core1 @@ -48,7 +51,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -126,7 +129,7 @@ typedef enum IRQn { FLEXIO_IRQn = 41, /**< flexio: Interrupt request */ Reserved58_IRQn = 42, /**< Reserved interrupt */ Reserved59_IRQn = 43, /**< Reserved interrupt */ - Reserved60_IRQn = 44, /**< Reserved interrupt */ + MIPI_IRQn = 44, /**< DSI: Interrupt request */ EDMA2_CH0_IRQn = 45, /**< edma2: Channel 0 interrupt */ EDMA2_CH1_IRQn = 46, /**< edma2: Channel 1 interrupt */ EDMA2_CH2_IRQn = 47, /**< edma2: Channel 2 interrupt */ @@ -1517,6 +1520,37 @@ typedef enum _dma_request_source /** Interrupt vectors for the LP_FLEXCOMM peripheral type */ #define LP_FLEXCOMM_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LP_FLEXCOMM17_IRQn, LP_FLEXCOMM18_IRQn, LP_FLEXCOMM19_IRQn, LP_FLEXCOMM20_IRQn } +/* MIPI_DSI_HOST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MIPI_DSI_HOST base address */ + #define MIPI_DSI_HOST_BASE (0x50417000u) + /** Peripheral MIPI_DSI_HOST base address */ + #define MIPI_DSI_HOST_BASE_NS (0x40417000u) + /** Peripheral MIPI_DSI_HOST base pointer */ + #define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) + /** Peripheral MIPI_DSI_HOST base pointer */ + #define MIPI_DSI_HOST_NS ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE_NS) + /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ + #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE } + /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ + #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST } + /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ + #define MIPI_DSI_HOST_BASE_ADDRS_NS { MIPI_DSI_HOST_BASE_NS } + /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ + #define MIPI_DSI_HOST_BASE_PTRS_NS { MIPI_DSI_HOST_NS } +#else + /** Peripheral MIPI_DSI_HOST base address */ + #define MIPI_DSI_HOST_BASE (0x40417000u) + /** Peripheral MIPI_DSI_HOST base pointer */ + #define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) + /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ + #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE } + /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ + #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST } +#endif +/** Interrupt vectors for the MIPI_DSI_HOST peripheral type */ +#define MIPI_DSI_HOST_IRQS { MIPI_IRQn } + /* MMU - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral MMU2 base address */ @@ -1990,6 +2024,9 @@ typedef enum _dma_request_source /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC1 } #endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_ALARM_IRQS { RTC1_ALARM_IRQn } +#define RTC_WAKEUP_IRQS { RTC1_IRQn } /* SCT - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1_features.h index e40cb7b46..a0402b2ac 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -55,6 +57,8 @@ #define FSL_FEATURE_SOC_LPSPI_COUNT (6) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (4) +/* @brief MIPI_DSI_HOST availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1) /* @brief MPU availability on the SoC. */ #define FSL_FEATURE_SOC_MPU_COUNT (1) /* @brief MRT availability on the SoC. */ @@ -110,8 +114,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -124,6 +126,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -319,8 +323,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -349,6 +351,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -446,8 +450,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -490,6 +492,31 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MIPI_DSI_HOST module features */ + +/* @brief Does not have DPHY PLL(DPHY_CM) */ +#define FSL_FEATURE_MIPI_DSI_HOST_NO_DPHY_PLL (1) +/* @brief Support TX ULPS */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS (1) +/* @brief Has control register to enable or disable TX ULPS */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS_CTRL (0) +/* @brief Has pixel-link to DPI remap */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PXL2DPI (0) +/* @brief Has DBI Pixel Format register */ +#define FSL_FEATURE_MIPI_DSI_HOST_DBI_HAS_PIXEL_FORMAT (1) +/* @brief Has PHY ready status register */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PHY_RDY (1) +/* @brief Has HS control HS_MODE_ENABLE register */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_HS_CTRL (1) +/* @brief Has bitfield HOST_TURNAROUND[REQUEST_BTA] */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_BTA_CTRL (1) +/* @brief Has separate ULPS control */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_SEPARATE_ULPS_CTRL (1) /* MRT module features */ @@ -657,6 +684,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -668,6 +697,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -743,6 +774,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XSPI module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv.h index 20ea86f99..976060040 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv.h @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_ezhv -** MIMXRT735SGFOA_ezhv +** Processors: MIMXRT735SGAWBR_ezhv +** MIMXRT735SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT735S_ezhv @@ -25,14 +25,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT735S_ezhv.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT735S_ezhv * * Peripheral Access Layer for MIMXRT735S_ezhv @@ -77,6 +79,7 @@ #include "PERI_LPSPI.h" #include "PERI_LPUART.h" #include "PERI_LP_FLEXCOMM.h" +#include "PERI_MIPI_DSI_HOST.h" #include "PERI_MMU.h" #include "PERI_MRT.h" #include "PERI_MU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv_COMMON.h index e7aa2308a..0e1789413 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv_COMMON.h @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_ezhv -** MIMXRT735SGFOA_ezhv +** Processors: MIMXRT735SGAWBR_ezhv +** MIMXRT735SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT735S_ezhv @@ -25,14 +25,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT735S_ezhv_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT735S_ezhv * * Peripheral Access Layer for MIMXRT735S_ezhv @@ -43,7 +45,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -1010,6 +1012,16 @@ typedef enum IRQn { #define LP_FLEXCOMM_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +/* MIPI_DSI_HOST - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI_HOST base address */ +#define MIPI_DSI_HOST_BASE (0x40417000u) +/** Peripheral MIPI_DSI_HOST base pointer */ +#define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) +/** Array initializer of MIPI_DSI_HOST peripheral base addresses */ +#define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE } +/** Array initializer of MIPI_DSI_HOST peripheral base pointers */ +#define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST } + /* MMU - Peripheral instance base addresses */ /** Peripheral MMU0 base address */ #define MMU0_BASE (0x40030000u) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv_features.h index d6811c2b1..443b3e9cf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_ezhv_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -63,6 +65,8 @@ #define FSL_FEATURE_SOC_LPSPI_COUNT (20) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (18) +/* @brief MIPI_DSI_HOST availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1) /* @brief MRT availability on the SoC. */ #define FSL_FEATURE_SOC_MRT_COUNT (2) /* @brief MU availability on the SoC. */ @@ -132,8 +136,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -146,6 +148,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -366,8 +370,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -396,6 +398,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -493,8 +497,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -537,6 +539,31 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MIPI_DSI_HOST module features */ + +/* @brief Does not have DPHY PLL(DPHY_CM) */ +#define FSL_FEATURE_MIPI_DSI_HOST_NO_DPHY_PLL (1) +/* @brief Support TX ULPS */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS (1) +/* @brief Has control register to enable or disable TX ULPS */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS_CTRL (0) +/* @brief Has pixel-link to DPI remap */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PXL2DPI (0) +/* @brief Has DBI Pixel Format register */ +#define FSL_FEATURE_MIPI_DSI_HOST_DBI_HAS_PIXEL_FORMAT (1) +/* @brief Has PHY ready status register */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PHY_RDY (1) +/* @brief Has HS control HS_MODE_ENABLE register */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_HS_CTRL (1) +/* @brief Has bitfield HOST_TURNAROUND[REQUEST_BTA] */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_BTA_CTRL (1) +/* @brief Has separate ULPS control */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_SEPARATE_ULPS_CTRL (1) /* MRT module features */ @@ -711,6 +738,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -722,6 +751,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -813,6 +844,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XCACHE module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1.h index bcae364b1..48674ff80 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_hifi1 +** Processors: MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT735S_hifi1 @@ -26,14 +26,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT735S_hifi1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT735S_hifi1 * * Peripheral Access Layer for MIMXRT735S_hifi1 @@ -69,6 +71,7 @@ #include "PERI_LPSPI.h" #include "PERI_LPUART.h" #include "PERI_LP_FLEXCOMM.h" +#include "PERI_MIPI_DSI_HOST.h" #include "PERI_MMU.h" #include "PERI_MRT.h" #include "PERI_MU.h" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1_COMMON.h index a836732fe..b8cd93f4b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1_COMMON.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_hifi1 +** Processors: MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT735S_hifi1 @@ -26,14 +26,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT735S_hifi1_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT735S_hifi1 * * Peripheral Access Layer for MIMXRT735S_hifi1 @@ -44,7 +46,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -1478,6 +1480,35 @@ typedef enum _dma_request_source /** Interrupt vectors for the LP_FLEXCOMM peripheral type */ #define LP_FLEXCOMM_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LP_FLEXCOMM17_IRQn, LP_FLEXCOMM18_IRQn, LP_FLEXCOMM19_IRQn, LP_FLEXCOMM20_IRQn } +/* MIPI_DSI_HOST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MIPI_DSI_HOST base address */ + #define MIPI_DSI_HOST_BASE (0x50417000u) + /** Peripheral MIPI_DSI_HOST base address */ + #define MIPI_DSI_HOST_BASE_NS (0x40417000u) + /** Peripheral MIPI_DSI_HOST base pointer */ + #define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) + /** Peripheral MIPI_DSI_HOST base pointer */ + #define MIPI_DSI_HOST_NS ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE_NS) + /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ + #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE } + /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ + #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST } + /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ + #define MIPI_DSI_HOST_BASE_ADDRS_NS { MIPI_DSI_HOST_BASE_NS } + /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ + #define MIPI_DSI_HOST_BASE_PTRS_NS { MIPI_DSI_HOST_NS } +#else + /** Peripheral MIPI_DSI_HOST base address */ + #define MIPI_DSI_HOST_BASE (0x40417000u) + /** Peripheral MIPI_DSI_HOST base pointer */ + #define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) + /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ + #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE } + /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ + #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST } +#endif + /* MMU - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral MMU2 base address */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1_features.h index 78f8915f0..e9c705021 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/MIMXRT735S_hifi1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -55,6 +57,8 @@ #define FSL_FEATURE_SOC_LPSPI_COUNT (6) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (4) +/* @brief MIPI_DSI_HOST availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1) /* @brief MRT availability on the SoC. */ #define FSL_FEATURE_SOC_MRT_COUNT (1) /* @brief MU availability on the SoC. */ @@ -108,8 +112,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -122,6 +124,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -317,8 +321,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -347,6 +349,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -444,8 +448,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -488,6 +490,31 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) + +/* MIPI_DSI_HOST module features */ + +/* @brief Does not have DPHY PLL(DPHY_CM) */ +#define FSL_FEATURE_MIPI_DSI_HOST_NO_DPHY_PLL (1) +/* @brief Support TX ULPS */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS (1) +/* @brief Has control register to enable or disable TX ULPS */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS_CTRL (0) +/* @brief Has pixel-link to DPI remap */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PXL2DPI (0) +/* @brief Has DBI Pixel Format register */ +#define FSL_FEATURE_MIPI_DSI_HOST_DBI_HAS_PIXEL_FORMAT (1) +/* @brief Has PHY ready status register */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PHY_RDY (1) +/* @brief Has HS control HS_MODE_ENABLE register */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_HS_CTRL (1) +/* @brief Has bitfield HOST_TURNAROUND[REQUEST_BTA] */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_BTA_CTRL (1) +/* @brief Has separate ULPS control */ +#define FSL_FEATURE_MIPI_DSI_HOST_HAS_SEPARATE_ULPS_CTRL (1) /* MRT module features */ @@ -653,6 +680,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -664,6 +693,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -732,6 +763,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XSPI module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/fsl_device_registers.h index b3b362043..666cfaad3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/fsl_device_registers.h @@ -13,13 +13,13 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core0.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core0.c index 3749eb139..ef3b529e2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core0.c @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT735S_cm33_core0 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -146,7 +146,7 @@ WEAK void I3C1_IRQHandler(void); WEAK void FLEXIO_IRQHandler(void); WEAK void Reserved72_IRQHandler(void); WEAK void Reserved73_IRQHandler(void); -WEAK void Reserved74_IRQHandler(void); +WEAK void MIPI_IRQHandler(void); WEAK void EDMA0_CH0_IRQHandler(void); WEAK void EDMA0_CH1_IRQHandler(void); WEAK void EDMA0_CH2_IRQHandler(void); @@ -311,7 +311,7 @@ void I3C1_DriverIRQHandler(void) ALIAS(DefaultISR); void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved73_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved74_DriverIRQHandler(void) ALIAS(DefaultISR); +void MIPI_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA0_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA0_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA0_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -597,7 +597,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) FLEXIO_IRQHandler, // 71 : FLEXIO: Interrupt request Reserved72_IRQHandler, // 72 : Reserved interrupt Reserved73_IRQHandler, // 73 : Reserved interrupt - Reserved74_IRQHandler, // 74 : Reserved interrupt + MIPI_IRQHandler, // 74 : DSI: Interrupt request EDMA0_CH0_IRQHandler, // 75 : EDMA: Channel 0 interrupt EDMA0_CH1_IRQHandler, // 76 : EDMA: Channel 1 interrupt EDMA0_CH2_IRQHandler, // 77 : EDMA: Channel 2 interrupt @@ -1286,9 +1286,9 @@ WEAK void Reserved73_IRQHandler(void) Reserved73_DriverIRQHandler(); } -WEAK void Reserved74_IRQHandler(void) +WEAK void MIPI_IRQHandler(void) { - Reserved74_DriverIRQHandler(); + MIPI_DriverIRQHandler(); } WEAK void EDMA0_CH0_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core0.cpp b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core0.cpp index 3749eb139..ef3b529e2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core0.cpp +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core0.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT735S_cm33_core0 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -146,7 +146,7 @@ WEAK void I3C1_IRQHandler(void); WEAK void FLEXIO_IRQHandler(void); WEAK void Reserved72_IRQHandler(void); WEAK void Reserved73_IRQHandler(void); -WEAK void Reserved74_IRQHandler(void); +WEAK void MIPI_IRQHandler(void); WEAK void EDMA0_CH0_IRQHandler(void); WEAK void EDMA0_CH1_IRQHandler(void); WEAK void EDMA0_CH2_IRQHandler(void); @@ -311,7 +311,7 @@ void I3C1_DriverIRQHandler(void) ALIAS(DefaultISR); void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved72_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved73_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved74_DriverIRQHandler(void) ALIAS(DefaultISR); +void MIPI_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA0_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA0_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA0_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -597,7 +597,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) FLEXIO_IRQHandler, // 71 : FLEXIO: Interrupt request Reserved72_IRQHandler, // 72 : Reserved interrupt Reserved73_IRQHandler, // 73 : Reserved interrupt - Reserved74_IRQHandler, // 74 : Reserved interrupt + MIPI_IRQHandler, // 74 : DSI: Interrupt request EDMA0_CH0_IRQHandler, // 75 : EDMA: Channel 0 interrupt EDMA0_CH1_IRQHandler, // 76 : EDMA: Channel 1 interrupt EDMA0_CH2_IRQHandler, // 77 : EDMA: Channel 2 interrupt @@ -1286,9 +1286,9 @@ WEAK void Reserved73_IRQHandler(void) Reserved73_DriverIRQHandler(); } -WEAK void Reserved74_IRQHandler(void) +WEAK void MIPI_IRQHandler(void) { - Reserved74_DriverIRQHandler(); + MIPI_DriverIRQHandler(); } WEAK void EDMA0_CH0_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core1.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core1.c index 577bee8bb..6eb9e41d4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core1.c @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT735S_cm33_core1 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -132,7 +132,7 @@ WEAK void I3C3_IRQHandler(void); WEAK void FLEXIO_IRQHandler(void); WEAK void Reserved58_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); -WEAK void Reserved60_IRQHandler(void); +WEAK void MIPI_IRQHandler(void); WEAK void EDMA2_CH0_IRQHandler(void); WEAK void EDMA2_CH1_IRQHandler(void); WEAK void EDMA2_CH2_IRQHandler(void); @@ -231,7 +231,7 @@ void I3C3_DriverIRQHandler(void) ALIAS(DefaultISR); void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); +void MIPI_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA2_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA2_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA2_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -429,7 +429,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) FLEXIO_IRQHandler, // 57 : flexio: Interrupt request Reserved58_IRQHandler, // 58 : Reserved interrupt Reserved59_IRQHandler, // 59 : Reserved interrupt - Reserved60_IRQHandler, // 60 : Reserved interrupt + MIPI_IRQHandler, // 60 : DSI: Interrupt request EDMA2_CH0_IRQHandler, // 61 : edma2: Channel 0 interrupt EDMA2_CH1_IRQHandler, // 62 : edma2: Channel 1 interrupt EDMA2_CH2_IRQHandler, // 63 : edma2: Channel 2 interrupt @@ -983,9 +983,9 @@ WEAK void Reserved59_IRQHandler(void) Reserved59_DriverIRQHandler(); } -WEAK void Reserved60_IRQHandler(void) +WEAK void MIPI_IRQHandler(void) { - Reserved60_DriverIRQHandler(); + MIPI_DriverIRQHandler(); } WEAK void EDMA2_CH0_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core1.cpp b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core1.cpp index 577bee8bb..6eb9e41d4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core1.cpp +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/startup_MIMXRT735S_cm33_core1.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT735S_cm33_core1 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP @@ -132,7 +132,7 @@ WEAK void I3C3_IRQHandler(void); WEAK void FLEXIO_IRQHandler(void); WEAK void Reserved58_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); -WEAK void Reserved60_IRQHandler(void); +WEAK void MIPI_IRQHandler(void); WEAK void EDMA2_CH0_IRQHandler(void); WEAK void EDMA2_CH1_IRQHandler(void); WEAK void EDMA2_CH2_IRQHandler(void); @@ -231,7 +231,7 @@ void I3C3_DriverIRQHandler(void) ALIAS(DefaultISR); void FLEXIO_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved58_DriverIRQHandler(void) ALIAS(DefaultISR); void Reserved59_DriverIRQHandler(void) ALIAS(DefaultISR); -void Reserved60_DriverIRQHandler(void) ALIAS(DefaultISR); +void MIPI_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA2_CH0_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA2_CH1_DriverIRQHandler(void) ALIAS(DefaultISR); void EDMA2_CH2_DriverIRQHandler(void) ALIAS(DefaultISR); @@ -429,7 +429,7 @@ __attribute__((used, section(".isr_vector"))) void (*const __isr_vector[])(void) FLEXIO_IRQHandler, // 57 : flexio: Interrupt request Reserved58_IRQHandler, // 58 : Reserved interrupt Reserved59_IRQHandler, // 59 : Reserved interrupt - Reserved60_IRQHandler, // 60 : Reserved interrupt + MIPI_IRQHandler, // 60 : DSI: Interrupt request EDMA2_CH0_IRQHandler, // 61 : edma2: Channel 0 interrupt EDMA2_CH1_IRQHandler, // 62 : edma2: Channel 1 interrupt EDMA2_CH2_IRQHandler, // 63 : edma2: Channel 2 interrupt @@ -983,9 +983,9 @@ WEAK void Reserved59_IRQHandler(void) Reserved59_DriverIRQHandler(); } -WEAK void Reserved60_IRQHandler(void) +WEAK void MIPI_IRQHandler(void) { - Reserved60_DriverIRQHandler(); + MIPI_DriverIRQHandler(); } WEAK void EDMA2_CH0_IRQHandler(void) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core0.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core0.c index 06bd65239..77633bf7c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core0.c @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGFOA_cm33_core0 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT735S_cm33_core0 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT735S_cm33_core0 * (implementation file) * @@ -58,6 +61,28 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; +/* ---------------------------------------------------------------------------- + -- GlikeyWriteEnable + ---------------------------------------------------------------------------- */ +static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx) +{ + base->CTRL_0 |= GLIKEY_CTRL_0_SFT_RST_MASK; + base->CTRL_0 |= idx; + base->CTRL_0 = GLIKEY_CTRL_0_WR_EN_0(1U) | idx; + base->CTRL_1 = 0x00290000U; + base->CTRL_0 = GLIKEY_CTRL_0_WR_EN_0(2U) | idx; + base->CTRL_1 = 0x00280000U; + base->CTRL_0 = idx; /* Write enable*/ +} + +/* ---------------------------------------------------------------------------- + -- GlikeyClearConfig + ---------------------------------------------------------------------------- */ +static void GlikeyClearConfig(GLIKEY_Type *base) +{ + base->CTRL_0 |= GLIKEY_CTRL_0_SFT_RST_MASK; +} + /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ @@ -84,10 +109,40 @@ __attribute__((weak)) void SystemInit(void) { SYSCON3->TEMPDETECT_CTRL[0] &= ~SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK; } - + if ((SYSCON3->TEMPDETECT_CTRL[1] & SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK) != 0U) { - SYSCON3->TEMPDETECT_CTRL[1] &= ~SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK; + SYSCON3->TEMPDETECT_CTRL[1] &= ~SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK; + } + + if ((SYSCON0->ELS_AS_CFG0 & 0x06009500U) == 0x06009500U) /* Disable aGDET, dGDET, HVD, LVD reset. */ + { + PMC0->CTRL &= ~(PMC_CTRL_AGDET1RE_MASK | PMC_CTRL_AGDET2RE_MASK); + PMC0->INTRCTRL &= ~ (PMC_INTRCTRL_AGDET1IE_MASK | PMC_INTRCTRL_AGDET2IE_MASK); + + if (GDET0->GDET_ENABLE1 != 0U) /* Disable GDET0 */ + { + GlikeyWriteEnable(GLIKEY3, 0U); + SYSCON0->GDET_CTRL[0] = (SYSCON0->GDET_CTRL[0] & (~SYSCON0_GDET_CTRL_GDET_ISO_SW_MASK)) | SYSCON0_GDET_CTRL_GDET_ISO_SW(0x2U); + GDET0->GDET_ENABLE1 = 0U; + CLKCTL0->ONE_SRC_CLKSLICE_ENABLE &= ~CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET0_FCLK_EN_MASK; + GlikeyClearConfig(GLIKEY3); + } + + if (GDET3->GDET_ENABLE1 != 0U) /* Disable GDET3 */ + { + GlikeyWriteEnable(GLIKEY4, 0U); + SYSCON3->GDET_CTRL[0] = (SYSCON3->GDET_CTRL[0] & (~SYSCON3_GDET_CTRL_GDET_ISO_SW_MASK)) | SYSCON3_GDET_CTRL_GDET_ISO_SW(0x2U); + GDET3->GDET_ENABLE1 = 0U; + CLKCTL3->ONE_SRC_CLKSLICE_ENABLE_SENSE &= ~CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET3_FCLK_EN_MASK; + GlikeyClearConfig(GLIKEY4); + } + + /* Disable aGDET/LVD/HVD input for RAM_ZEROIZE and CHIP_RESET */ + ITRC->OUT_SEL[3][0] = (ITRC->OUT_SEL[3][0] & (~(ITRC_OUT_SEL_IN13_SELn_MASK | ITRC_OUT_SEL_IN14_SELn_MASK | ITRC_OUT_SEL_IN15_SELn_MASK))) | 0xA8000000U; + ITRC->OUT_SEL[4][0] = (ITRC->OUT_SEL[4][0] & (~(ITRC_OUT_SEL_IN13_SELn_MASK | ITRC_OUT_SEL_IN14_SELn_MASK | ITRC_OUT_SEL_IN15_SELn_MASK))) | 0xA8000000U; + ITRC->OUT_SEL_1[3][0] = (ITRC->OUT_SEL_1[3][0] & (~ITRC_OUT_SEL_1_IN16_SELn_MASK)) | 0x2U; + ITRC->OUT_SEL_1[4][0] = (ITRC->OUT_SEL_1[4][0] & (~ITRC_OUT_SEL_1_IN16_SELn_MASK)) | 0x2U; } SYSCON0->DSPSTALL = SYSCON0_DSPSTALL_DSPSTALL_MASK; diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core0.h index 108c9b761..1844d4ae7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core0.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGFOA_cm33_core0 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT735S_cm33_core0 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT735S_cm33_core0 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core1.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core1.c index f8312a36f..c472a55df 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core1.c @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGFOA_cm33_core1 +** Processors: MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT735S_cm33_core1 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT735S_cm33_core1 * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core1.h index 7f6f963c2..a089a9064 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_cm33_core1.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGFOA_cm33_core1 +** Processors: MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT735S_cm33_core1 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT735S_cm33_core1 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_ezhv.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_ezhv.c index f6b839293..6453b188f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_ezhv.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_ezhv.c @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_ezhv -** MIMXRT735SGFOA_ezhv +** Processors: MIMXRT735SGAWBR_ezhv +** MIMXRT735SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MIMXRT735S_ezhv * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT735S_ezhv * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_ezhv.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_ezhv.h index 2dc843b78..172029637 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_ezhv.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_ezhv.h @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_ezhv -** MIMXRT735SGFOA_ezhv +** Processors: MIMXRT735SGAWBR_ezhv +** MIMXRT735SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MIMXRT735S_ezhv * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT735S_ezhv (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_hifi1.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_hifi1.c index 9c8d9b915..e1101b3c7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_hifi1.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_hifi1.c @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_hifi1 +** Processors: MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -28,6 +28,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -35,7 +37,7 @@ /*! * @file MIMXRT735S * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT735S * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_hifi1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_hifi1.h index 578777fa8..adecf6a7c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_hifi1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT735S/system_MIMXRT735S_hifi1.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_hifi1 +** Processors: MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -28,6 +28,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -35,7 +37,7 @@ /*! * @file MIMXRT735S * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT735S (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0.h index 6bbe85dfc..da5e56802 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGFOA_cm33_core0 +** Processors: MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core0 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT758S_cm33_core0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core0 * * CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0_COMMON.h index f434cbd45..d0ef9879a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0_COMMON.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGFOA_cm33_core0 +** Processors: MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core0 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT758S_cm33_core0_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core0 * * CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core0 @@ -48,7 +51,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -3532,6 +3535,9 @@ typedef enum _dma_request_source /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC0 } #endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_ALARM_IRQS { RTC0_ALARM_IRQn } +#define RTC_WAKEUP_IRQS { RTC0_IRQn } /* SCT - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0_features.h index dca33c092..f4c39644b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -138,8 +140,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -152,6 +152,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -368,8 +370,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -398,6 +398,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -504,8 +506,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -548,6 +548,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_DSI_HOST module features */ @@ -739,6 +743,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -750,6 +756,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -848,6 +856,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XCACHE module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1.h index 68b20cecd..a8e708b2c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGFOA_cm33_core1 +** Processors: MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core1 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT758S_cm33_core1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core1 * * CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1_COMMON.h index bbb46582a..ffa03e6a8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1_COMMON.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGFOA_cm33_core1 +** Processors: MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core1 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT758S_cm33_core1_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core1 * * CMSIS Peripheral Access Layer for MIMXRT758S_cm33_core1 @@ -48,7 +51,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -2110,6 +2113,9 @@ typedef enum _dma_request_source /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC1 } #endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_ALARM_IRQS { RTC1_ALARM_IRQn } +#define RTC_WAKEUP_IRQS { RTC1_IRQn } /* SCT - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1_features.h index 8a8c4e0f1..709706ce5 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -114,8 +116,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -128,6 +128,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -323,8 +325,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -353,6 +353,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -459,8 +461,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -503,6 +503,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_DSI_HOST module features */ @@ -691,6 +695,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -702,6 +708,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -777,6 +785,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XSPI module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv.h index da554f2de..d1d3e2b3e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv.h @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_ezhv -** MIMXRT758SGFOA_ezhv +** Processors: MIMXRT758SGAWBR_ezhv +** MIMXRT758SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT758S_ezhv @@ -25,14 +25,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT758S_ezhv.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT758S_ezhv * * Peripheral Access Layer for MIMXRT758S_ezhv diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv_COMMON.h index d9447317c..f30ef0be6 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv_COMMON.h @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_ezhv -** MIMXRT758SGFOA_ezhv +** Processors: MIMXRT758SGAWBR_ezhv +** MIMXRT758SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT758S_ezhv @@ -25,14 +25,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT758S_ezhv_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT758S_ezhv * * Peripheral Access Layer for MIMXRT758S_ezhv @@ -43,7 +45,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv_features.h index 574b99efb..06ce44df3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_ezhv_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -136,8 +138,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -150,6 +150,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -370,8 +372,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -400,6 +400,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -506,8 +508,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -550,6 +550,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_DSI_HOST module features */ @@ -745,6 +749,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -756,6 +762,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -847,6 +855,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XCACHE module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1.h index ace0e1051..42ded3501 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_hifi1 +** Processors: MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT758S_hifi1 @@ -26,14 +26,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT758S_hifi1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT758S_hifi1 * * Peripheral Access Layer for MIMXRT758S_hifi1 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1_COMMON.h index 26e69bf68..02cd937ed 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1_COMMON.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_hifi1 +** Processors: MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT758S_hifi1 @@ -26,14 +26,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT758S_hifi1_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT758S_hifi1 * * Peripheral Access Layer for MIMXRT758S_hifi1 @@ -44,7 +46,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1_features.h index 5a9c806f1..8a8ec5c27 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/MIMXRT758S_hifi1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -112,8 +114,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -126,6 +126,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -321,8 +323,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -351,6 +351,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -457,8 +459,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -501,6 +501,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_DSI_HOST module features */ @@ -687,6 +691,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -698,6 +704,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -766,6 +774,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XSPI module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/fsl_device_registers.h index 674787359..5f32ad364 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/fsl_device_registers.h @@ -13,13 +13,13 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core0.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core0.c index 3cfc54435..be0ac5ed8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core0.c @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT758S_cm33_core0 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core0.cpp b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core0.cpp index 3cfc54435..be0ac5ed8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core0.cpp +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core0.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT758S_cm33_core0 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core1.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core1.c index 3d309b84f..7c7eaeb33 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core1.c @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT758S_cm33_core1 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core1.cpp b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core1.cpp index 3d309b84f..7c7eaeb33 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core1.cpp +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/startup_MIMXRT758S_cm33_core1.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT758S_cm33_core1 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core0.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core0.c index 811d8eced..22c2f869d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core0.c @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGFOA_cm33_core0 +** Processors: MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT758S_cm33_core0 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT758S_cm33_core0 * (implementation file) * @@ -58,6 +61,28 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; +/* ---------------------------------------------------------------------------- + -- GlikeyWriteEnable + ---------------------------------------------------------------------------- */ +static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx) +{ + base->CTRL_0 |= GLIKEY_CTRL_0_SFT_RST_MASK; + base->CTRL_0 |= idx; + base->CTRL_0 = GLIKEY_CTRL_0_WR_EN_0(1U) | idx; + base->CTRL_1 = 0x00290000U; + base->CTRL_0 = GLIKEY_CTRL_0_WR_EN_0(2U) | idx; + base->CTRL_1 = 0x00280000U; + base->CTRL_0 = idx; /* Write enable*/ +} + +/* ---------------------------------------------------------------------------- + -- GlikeyClearConfig + ---------------------------------------------------------------------------- */ +static void GlikeyClearConfig(GLIKEY_Type *base) +{ + base->CTRL_0 |= GLIKEY_CTRL_0_SFT_RST_MASK; +} + /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ @@ -84,10 +109,40 @@ __attribute__((weak)) void SystemInit(void) { SYSCON3->TEMPDETECT_CTRL[0] &= ~SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK; } - + if ((SYSCON3->TEMPDETECT_CTRL[1] & SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK) != 0U) { - SYSCON3->TEMPDETECT_CTRL[1] &= ~SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK; + SYSCON3->TEMPDETECT_CTRL[1] &= ~SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK; + } + + if ((SYSCON0->ELS_AS_CFG0 & 0x06009500U) == 0x06009500U) /* Disable aGDET, dGDET, HVD, LVD reset. */ + { + PMC0->CTRL &= ~(PMC_CTRL_AGDET1RE_MASK | PMC_CTRL_AGDET2RE_MASK); + PMC0->INTRCTRL &= ~ (PMC_INTRCTRL_AGDET1IE_MASK | PMC_INTRCTRL_AGDET2IE_MASK); + + if (GDET0->GDET_ENABLE1 != 0U) /* Disable GDET0 */ + { + GlikeyWriteEnable(GLIKEY3, 0U); + SYSCON0->GDET_CTRL[0] = (SYSCON0->GDET_CTRL[0] & (~SYSCON0_GDET_CTRL_GDET_ISO_SW_MASK)) | SYSCON0_GDET_CTRL_GDET_ISO_SW(0x2U); + GDET0->GDET_ENABLE1 = 0U; + CLKCTL0->ONE_SRC_CLKSLICE_ENABLE &= ~CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET0_FCLK_EN_MASK; + GlikeyClearConfig(GLIKEY3); + } + + if (GDET3->GDET_ENABLE1 != 0U) /* Disable GDET3 */ + { + GlikeyWriteEnable(GLIKEY4, 0U); + SYSCON3->GDET_CTRL[0] = (SYSCON3->GDET_CTRL[0] & (~SYSCON3_GDET_CTRL_GDET_ISO_SW_MASK)) | SYSCON3_GDET_CTRL_GDET_ISO_SW(0x2U); + GDET3->GDET_ENABLE1 = 0U; + CLKCTL3->ONE_SRC_CLKSLICE_ENABLE_SENSE &= ~CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET3_FCLK_EN_MASK; + GlikeyClearConfig(GLIKEY4); + } + + /* Disable aGDET/LVD/HVD input for RAM_ZEROIZE and CHIP_RESET */ + ITRC->OUT_SEL[3][0] = (ITRC->OUT_SEL[3][0] & (~(ITRC_OUT_SEL_IN13_SELn_MASK | ITRC_OUT_SEL_IN14_SELn_MASK | ITRC_OUT_SEL_IN15_SELn_MASK))) | 0xA8000000U; + ITRC->OUT_SEL[4][0] = (ITRC->OUT_SEL[4][0] & (~(ITRC_OUT_SEL_IN13_SELn_MASK | ITRC_OUT_SEL_IN14_SELn_MASK | ITRC_OUT_SEL_IN15_SELn_MASK))) | 0xA8000000U; + ITRC->OUT_SEL_1[3][0] = (ITRC->OUT_SEL_1[3][0] & (~ITRC_OUT_SEL_1_IN16_SELn_MASK)) | 0x2U; + ITRC->OUT_SEL_1[4][0] = (ITRC->OUT_SEL_1[4][0] & (~ITRC_OUT_SEL_1_IN16_SELn_MASK)) | 0x2U; } SYSCON0->DSPSTALL = SYSCON0_DSPSTALL_DSPSTALL_MASK; diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core0.h index adc35e59e..39aa80e74 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core0.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGFOA_cm33_core0 +** Processors: MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT758S_cm33_core0 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT758S_cm33_core0 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core1.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core1.c index 59432863e..f5f477d1e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core1.c @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGFOA_cm33_core1 +** Processors: MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT758S_cm33_core1 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT758S_cm33_core1 * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core1.h index ab4fbd3d6..7e74f761d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_cm33_core1.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGFOA_cm33_core1 +** Processors: MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT758S_cm33_core1 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT758S_cm33_core1 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_ezhv.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_ezhv.c index e3f3c0ad5..25b8af6ff 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_ezhv.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_ezhv.c @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_ezhv -** MIMXRT758SGFOA_ezhv +** Processors: MIMXRT758SGAWBR_ezhv +** MIMXRT758SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MIMXRT758S_ezhv * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT758S_ezhv * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_ezhv.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_ezhv.h index 92ff8b91f..f7915c4b2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_ezhv.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_ezhv.h @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_ezhv -** MIMXRT758SGFOA_ezhv +** Processors: MIMXRT758SGAWBR_ezhv +** MIMXRT758SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MIMXRT758S_ezhv * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT758S_ezhv (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_hifi1.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_hifi1.c index c7cb548e7..4e2446071 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_hifi1.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_hifi1.c @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_hifi1 +** Processors: MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -28,6 +28,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -35,7 +37,7 @@ /*! * @file MIMXRT758S * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT758S * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_hifi1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_hifi1.h index 645054527..ff302fa4c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_hifi1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT758S/system_MIMXRT758S_hifi1.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_hifi1 +** Processors: MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -28,6 +28,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -35,7 +37,7 @@ /*! * @file MIMXRT758S * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT758S (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0.h index da858b6ad..bf01035cb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGFOA_cm33_core0 +** Processors: MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core0 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_cm33_core0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core0 * * CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0_COMMON.h index 746c31ae7..349d1ddc4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0_COMMON.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGFOA_cm33_core0 +** Processors: MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core0 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_cm33_core0_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core0 * * CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core0 @@ -48,7 +51,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -3532,6 +3535,9 @@ typedef enum _dma_request_source /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC0 } #endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_ALARM_IRQS { RTC0_ALARM_IRQn } +#define RTC_WAKEUP_IRQS { RTC0_IRQn } /* SCT - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0_features.h index c0b97b567..a280dee33 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -138,8 +140,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -152,6 +152,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -368,8 +370,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -398,6 +398,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -504,8 +506,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -548,6 +548,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_DSI_HOST module features */ @@ -739,6 +743,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -750,6 +756,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -848,6 +856,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XCACHE module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1.h index c90b184f5..866f34de3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGFOA_cm33_core1 +** Processors: MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core1 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_cm33_core1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core1 * * CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1_COMMON.h index f61078639..9f43cf146 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1_COMMON.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGFOA_cm33_core1 +** Processors: MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core1 @@ -30,14 +31,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_cm33_core1_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core1 * * CMSIS Peripheral Access Layer for MIMXRT798S_cm33_core1 @@ -48,7 +51,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -2110,6 +2113,9 @@ typedef enum _dma_request_source /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC1 } #endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_ALARM_IRQS { RTC1_ALARM_IRQn } +#define RTC_WAKEUP_IRQS { RTC1_IRQn } /* SCT - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1_features.h index 297a1380a..6c93a3015 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -114,8 +116,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -128,6 +128,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -323,8 +325,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -353,6 +353,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -459,8 +461,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -503,6 +503,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_DSI_HOST module features */ @@ -691,6 +695,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -702,6 +708,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -777,6 +785,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XSPI module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv.h index 9102713d6..fb825f613 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv.h @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_ezhv -** MIMXRT798SGFOA_ezhv +** Processors: MIMXRT798SGAWBR_ezhv +** MIMXRT798SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT798S_ezhv @@ -25,14 +25,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_ezhv.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT798S_ezhv * * Peripheral Access Layer for MIMXRT798S_ezhv diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv_COMMON.h index c82ad0d58..11dbe8af0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv_COMMON.h @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_ezhv -** MIMXRT798SGFOA_ezhv +** Processors: MIMXRT798SGAWBR_ezhv +** MIMXRT798SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT798S_ezhv @@ -25,14 +25,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_ezhv_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT798S_ezhv * * Peripheral Access Layer for MIMXRT798S_ezhv @@ -43,7 +45,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv_features.h index fbef42c24..8eba9a80d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_ezhv_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -136,8 +138,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -150,6 +150,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -370,8 +372,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -400,6 +400,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -506,8 +508,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -550,6 +550,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_DSI_HOST module features */ @@ -745,6 +749,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -756,6 +762,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -847,6 +855,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XCACHE module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1.h index 0209bfbf9..c813cfa63 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGFOA_hifi1 +** Processors: MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT798S_hifi1 @@ -26,14 +26,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_hifi1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT798S_hifi1 * * Peripheral Access Layer for MIMXRT798S_hifi1 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1_COMMON.h index 98cb383ad..c02b5da73 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1_COMMON.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGFOA_hifi1 +** Processors: MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT798S_hifi1 @@ -26,14 +26,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_hifi1_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT798S_hifi1 * * Peripheral Access Layer for MIMXRT798S_hifi1 @@ -44,7 +46,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1_features.h index 9f611bbd0..3185decdf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -112,8 +114,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -126,6 +126,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -321,8 +323,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -351,6 +351,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -457,8 +459,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -501,6 +501,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_DSI_HOST module features */ @@ -687,6 +691,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -698,6 +704,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -766,6 +774,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XSPI module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4.h index 606102f2e..d07d8dbdc 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_hifi4 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT798S_hifi4 @@ -26,14 +26,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_hifi4.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT798S_hifi4 * * Peripheral Access Layer for MIMXRT798S_hifi4 diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4_COMMON.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4_COMMON.h index e257ad135..072826c69 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4_COMMON.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_hifi4 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Peripheral Access Layer for MIMXRT798S_hifi4 @@ -26,14 +26,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file MIMXRT798S_hifi4_COMMON.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief Peripheral Access Layer for MIMXRT798S_hifi4 * * Peripheral Access Layer for MIMXRT798S_hifi4 @@ -44,7 +46,7 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0300U +#define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4_features.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4_features.h index 4ad448593..f15b9150d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4_features.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/MIMXRT798S_hifi4_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 2.0, 2024-05-28 -** Build: b250513 +** Version: rev. 3.0, 2025-06-06 +** Build: b250813 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Initial version. ** - rev. 2.0 (2024-05-28) ** Rev2 DraftA. +** - rev. 3.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -136,8 +138,6 @@ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) -/* @brief Has C3 RDIVE Bit */ -#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief Has C0 HYSTCTR Bit */ #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) /* @brief If support round-robin mode */ @@ -150,6 +150,8 @@ #define FSL_FEATURE_ACMP_HAS_NO_FILTER_MODE (0) /* @brief Has No C0 SE Bit */ #define FSL_FEATURE_ACMP_HAS_NO_C0_SE_BIT (1) +/* @brief Has C3 RDIVE Bit */ +#define FSL_FEATURE_ACMP_HAS_C3_RDIVE_BIT (0) /* @brief If has acmp sample signal */ #define FSL_FEATURE_ACMP_HAS_NO_SAMPLE_SIGNAL (1) @@ -366,8 +368,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (1) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -396,6 +396,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* GPIO module features */ @@ -502,8 +504,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -546,6 +546,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* MIPI_DSI_HOST module features */ @@ -739,6 +743,8 @@ #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) /* @brief Has Bit Clock Swap option (register bit fields RCR2[BCS]) */ #define FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP (1) +/* @brief SAI5 and SAI6 share one irq number. */ +#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (0) /* SCT module features */ @@ -750,6 +756,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SEMA42 module features */ @@ -841,6 +849,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) /* @brief soc has reset. */ #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) /* XCACHE module features */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_clock.txt b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_clock.txt index 3a95f1a77..5eba3b827 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_clock.txt +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_clock.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.4.1) + mcux_component_version(2.5.0) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) mcux_add_include( INCLUDES . ) endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_ezhv.txt b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_ezhv.txt index d37932ea6..77d98bfdb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_ezhv.txt +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_ezhv.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.ezhv) - mcux_component_version(2.1.0) + mcux_component_version(2.1.2) mcux_add_source( SOURCES fsl_ezhv.c fsl_ezhv.h ) mcux_add_include( INCLUDES . ) endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_power.txt b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_power.txt index 938447a3c..6f1b8c1ab 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_power.txt +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_power.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.power) - mcux_component_version(2.4.1) + mcux_component_version(2.4.2) mcux_add_source( SOURCES fsl_power.c fsl_power.h ) mcux_add_include( INCLUDES . ) endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_pvts.txt b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_pvts.txt index 02fbdaa6a..89cdea5fb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_pvts.txt +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/CMakeLists_pvts.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.pvts) - mcux_component_version(2.0.0) + mcux_component_version(2.0.2) mcux_add_source( SOURCES fsl_pvts.c fsl_pvts.h ) mcux_add_include( INCLUDES . ) endif() \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_clock.c index 43294aba8..7beed6812 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_clock.c @@ -608,9 +608,9 @@ static uint32_t CLOCK_CalFroFreq(FRO_Type *base) { if ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u) { - freq = ((uint32_t)((uint64_t)(base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) * - ((uint64_t)refFreq / (uint64_t)((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1UL)) / - (uint64_t)((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT))); + freq = ((uint32_t)(((uint64_t)base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) * + ((uint64_t)refFreq / (((uint64_t)base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1ULL)) / + (((uint64_t)base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT))); } else { @@ -787,6 +787,126 @@ status_t CLOCK_EnableFroAutoTuning(FRO_Type *base, const clock_fro_config_t *con return ret; } +static uint32_t CLOCK_CalFroFreqFromTrimcnt(FRO_Type *base) +{ + uint32_t freq = 0U; + uint32_t refFreq = 0U; + + refFreq = (g_xtalFreq != 0U) ? g_xtalFreq : g_clkinFreq; + freq = ((uint32_t)((uint64_t)(base->TRIMCNT.RW & FRO_TRIMCNT_TRIMCNT_MASK) * + ((uint64_t)refFreq / (uint64_t)((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1UL)) / + (uint64_t)((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT))); + + return freq; +} + +/*! + * @brief Check if current frequency is in the set range of target frequency. + * @param curFreq current frequency + * @param targetFreq target frequency + * @param range The percentage value, The value/100 is the % deviation. + */ +static bool CLOCK_CheckFreqWithinRange(uint32_t curFreq, uint32_t targetFreq, uint32_t range) +{ + uint64_t temp = 0U; + if (curFreq >= targetFreq) + { + temp = ((uint64_t)curFreq - targetFreq) * 10000ULL / targetFreq; + } + else + { + temp = ((uint64_t)targetFreq - curFreq) * 10000ULL / targetFreq; + } + + return ((uint32_t)temp > range ? false : true); +} + +/* + * Calculate the approximate delay(count per reference clock) for FRO auto tuner lock. + */ +static uint32_t CLOCK_CalFroAutoTuneTimeout(FRO_Type *base) +{ + uint32_t count; + uint32_t refCnt = (base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT; + uint32_t trim1Delay = (base->CNFG2.RW & FRO_CNFG2_TRIM1_DELAY_MASK) >> FRO_CNFG2_TRIM1_DELAY_SHIFT; + uint32_t trim2Delay = (base->CNFG2.RW & FRO_CNFG2_TRIM2_DELAY_MASK) >> FRO_CNFG2_TRIM2_DELAY_SHIFT; + + /* Coarse tuning involves delay 4096 / 16 (COARSE=0) or 4096 / 128 (COARSEN=1). */ + count = (((base->CSR.RW & FRO_CSR_COARSEN_MASK) != 0U) ? 32U : 256U) * (refCnt + trim2Delay + 1U); + count += (refCnt + trim1Delay + 1U) * 22U; + + return count; +} + +uint32_t CLOCK_FroTuneOnce(FRO_Type *base, uint16_t trimVal) +{ + uint32_t targetFreq = 0U; + uint32_t refFreq; + uint32_t delayUs; + + refFreq = (g_xtalFreq != 0U) ? g_xtalFreq : g_clkinFreq; + + if (refFreq != 0U) + { + /* Disable auto-tuner to use FROTRIM to control FRO frequency. */ + base->CSR.CLR = FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; + + /* 1. Program the desired trim in FROTRIM */ + base->FROTRIM.RW = + (base->FROTRIM.RW & (~(FRO_FROTRIM_COARSE_TRIM_MASK | FRO_FROTRIM_FINE_TRIM_MASK))) | trimVal; + base->CSR.CLR = FRO_CSR_TUNEONCE_DONE_MASK; + /* 2. Make sure you wait enough time for the frequency to settle after applying the trim. */ + refFreq /= ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) >> FRO_CNFG1_REFDIV_SHIFT) + 1U; + delayUs = (base->CNFG2.RW & FRO_CNFG2_TRIM2_DELAY_MASK) >> FRO_CNFG2_TRIM2_DELAY_SHIFT; + delayUs = delayUs * 1000000UL / refFreq; + SDK_DelayAtLeastUs(delayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + /* 3. Enable TUNEONCE, TREN, but keep TRUPEN=0 -> this will allow the trims to be controlled by FROTRIM register + * instead of the auto-tuner. */ + base->CSR.SET = FRO_CSR_TUNEONCE_MASK; + base->CSR.SET = FRO_CSR_TREN_MASK; + /* 4. Wait until TUNEONCE_DONE=1. */ + while (!(base->CSR.RW & FRO_CSR_TUNEONCE_DONE_MASK)) + { + } + /* 5. Read TRIMCNT to get the frequency measurement for the FROTRIM in step 1 */ + targetFreq = CLOCK_CalFroFreqFromTrimcnt(base); + base->CSR.CLR = FRO_CSR_TUNEONCE_MASK; + base->CSR.CLR = FRO_CSR_TREN_MASK; + } + + return targetFreq; +} + +/*! Check the T+1, T, T-1 trim value and pick the closet one to targetFreq. */ +void CLOCK_FroFineTune(FRO_Type *base, uint32_t targetFreq, uint16_t trimVal) +{ + uint32_t prevFreq, curFreq, nextFreq, prevDelta, curDelta, nextDelta; + uint32_t fineTrim = 0U; + + prevFreq = CLOCK_FroTuneOnce(base, trimVal - 1U); + curFreq = CLOCK_FroTuneOnce(base, trimVal); + nextFreq = CLOCK_FroTuneOnce(base, trimVal + 1U); + + prevDelta = (targetFreq < prevFreq) ? (prevFreq - targetFreq) : (targetFreq - prevFreq); + curDelta = (targetFreq < curFreq) ? (curFreq - targetFreq) : (targetFreq - curFreq); + nextDelta = (targetFreq < nextFreq) ? (nextFreq - targetFreq) : (targetFreq - nextFreq); + + if (curDelta <= prevDelta && curDelta <= nextDelta) + { + fineTrim = trimVal; + } + else if (prevDelta < nextDelta) + { + fineTrim = trimVal - 1U; + } + else + { + fineTrim = trimVal + 1U; + } + + CLOCK_ConfigFroTrim(base, fineTrim); +} + void CLOCK_EnableFroClkFreq(FRO_Type *base, uint32_t targetFreq, uint32_t divOutEnable) { const clock_fro_config_t froAutotrimCfg = { @@ -798,8 +918,16 @@ void CLOCK_EnableFroClkFreq(FRO_Type *base, uint32_t targetFreq, uint32_t divOut .enableInt = 0U, .coarseTrimEn = true, }; - (void)CLOCK_EnableFroClkFreqCloseLoop(base, &froAutotrimCfg, divOutEnable); - (void)CLOCK_EnableFroAutoTuning(base, &froAutotrimCfg, false); + + if (kStatus_Success == CLOCK_EnableFroClkFreqCloseLoop(base, &froAutotrimCfg, divOutEnable)) + { + (void)CLOCK_EnableFroAutoTuning(base, &froAutotrimCfg, false); + } + else /* If the close loop not work, switch to open loop mode and search the nearest target frequency. */ + { + CLOCK_FroFineTune(base, targetFreq, (uint16_t)(base->AUTOTRIM.RW & FRO_AUTOTRIM_AUTOTRIM_MASK)); + CLOCK_EnableFroClkOutput(base, divOutEnable); + } } void CLOCK_ConfigFroTrim(FRO_Type *base, uint16_t trimVal) @@ -811,8 +939,10 @@ void CLOCK_ConfigFroTrim(FRO_Type *base, uint16_t trimVal) status_t CLOCK_EnableFroClkFreqCloseLoop(FRO_Type *base, const clock_fro_config_t *config, uint32_t divOutEnable) { - status_t ret = kStatus_Success; - uint32_t flags = 0U; + status_t ret = kStatus_Success; + uint32_t freq = 0U; + uint32_t timeout = 0U; + uint32_t refFreq = 0U; /*Power up FRO */ #if defined(FSL_CLOCK_DRIVER_COMPUTE) || defined(FSL_CLOCK_DRIVER_MEDIA) @@ -823,32 +953,61 @@ status_t CLOCK_EnableFroClkFreqCloseLoop(FRO_Type *base, const clock_fro_config_ /* Disable output before changeing frequency. */ CLOCK_EnableFroClkOutput(base, 0U); - ret = CLOCK_EnableFroAutoTuning(base, config, true); + /* Clear TUNE_ERR LOL_ERR flags. */ + base->CSR.CLR = FRO_CSR_TUNE_ERR_MASK | FRO_CSR_LOL_ERR_MASK; + ret = CLOCK_EnableFroAutoTuning(base, config, true); + + timeout = CLOCK_CalFroAutoTuneTimeout(base); + refFreq = (g_xtalFreq != 0U) ? g_xtalFreq : g_clkinFreq; + timeout = (SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY >> 2U) / refFreq * timeout; if (ret == kStatus_Success) { /* Polling wait tune finish. */ - do + while ((base->CSR.RW & FRO_CSR_TRIM_LOCK_MASK) == 0U) { - flags = CLOCK_GetFroFlags(base); - - } while ((flags & FRO_CSR_TRIM_LOCK_MASK) == 0U); - - if ((flags & (FRO_CSR_TUNE_ERR_MASK | FRO_CSR_LOL_ERR_MASK)) != 0U) - { - ret = kStatus_Fail; /* Error occures. */ + timeout--; + if (timeout == 0U) + { + ret = kStatus_Timeout; + break; + } } - else + if (ret == kStatus_Success) { - ret = kStatus_Success; - /* Configure the FROTRIM with autotrim value. */ - CLOCK_ConfigFroTrim(base, (uint16_t)(base->AUTOTRIM.RW & FRO_AUTOTRIM_AUTOTRIM_MASK)); + /* Check error. */ + if ((base->CSR.RW & (FRO_CSR_TUNE_ERR_MASK | FRO_CSR_LOL_ERR_MASK)) != 0U) + { + /* This is trim lock has happened and LOC comes back immediately. If measured freq matches the target + freq. clear the LOL error like nothing has happened. */ + base->CSR.CLR = FRO_CSR_TUNE_ERR_MASK | FRO_CSR_LOL_ERR_MASK; + + freq = CLOCK_CalFroFreqFromTrimcnt(base); + + if (CLOCK_CheckFreqWithinRange(freq, config->targetFreq, config->range)) + { + /* Configure the FROTRIM with autotrim value. */ + CLOCK_ConfigFroTrim(base, (uint16_t)(base->AUTOTRIM.RW & FRO_AUTOTRIM_AUTOTRIM_MASK)); + /* Enable output */ + CLOCK_EnableFroClkOutput(base, divOutEnable); + ret = kStatus_Success; + } + else + { + /* Error occurs, suggest to use tuneonce feature to tune to desired frrequnency. */ + ret = kStatus_Fail; + } + } + else /* This is a normal case, no timeout, no errors. */ + { + /* Configure the FROTRIM with autotrim value. */ + CLOCK_ConfigFroTrim(base, (uint16_t)(base->AUTOTRIM.RW & FRO_AUTOTRIM_AUTOTRIM_MASK)); + /* Enable output */ + CLOCK_EnableFroClkOutput(base, divOutEnable); + } } } - /* Enable output */ - CLOCK_EnableFroClkOutput(base, divOutEnable); - return ret; } @@ -1251,7 +1410,42 @@ uint32_t CLOCK_GetComputeAudioClkFreq(void) uint32_t CLOCK_GetSenseAudioClkFreq(void) { - return g_senseAudioClkFreq; + uint32_t freq = 0U; + uint32_t clkSel = 0U; + + if (SYSCON3->SILICONREV_ID == 0xA0000UL) + { + freq = g_senseAudioClkFreq; + } + else + { + clkSel = CLKCTL3->SENSEBASECLKSEL & CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL_MASK; + + /* Read again to avoid glitch. */ + if (clkSel == (CLKCTL3->SENSEBASECLKSEL & CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL_MASK)) + { + switch (clkSel) + { + case CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL(0U): + freq = CLOCK_GetMclkInClkFreq(); + break; + case CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL(1U): + freq = CLOCK_GetXtalInClkFreq(); + break; + case CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL(2U): + freq = CLOCK_GetFroClkFreq(2U) / 8U; + break; + case CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL(3U): + freq = CLOCK_GetAudioPfdFreq(kCLOCK_Pfd3); + break; + default: + freq = 0U; + break; + } + } + } + + return freq; } /* Get FCCLK Clk frequency */ @@ -1660,6 +1854,8 @@ void CLOCK_EnableMainPllPfdClkForDomain(clock_pfd_t pfd, uint32_t domainEnable) uint32_t pfdIndex = (uint32_t)pfd; uint32_t pfdValue; + assert(pfdIndex < 4U); + pfdValue = CLKCTL2->MAINPLL0PFDDOMAINEN & (~(0x7FUL << (8UL * pfdIndex))); CLKCTL2->MAINPLL0PFDDOMAINEN = pfdValue | ((domainEnable & (uint32_t)kCLOCK_AllDomainEnable) << (8UL * pfdIndex)); @@ -1670,6 +1866,8 @@ void CLOCK_EnableAudioPllPfdClkForDomain(clock_pfd_t pfd, uint32_t domainEnable) uint32_t pfdIndex = (uint32_t)pfd; uint32_t pfdValue; + assert(pfdIndex < 4U); + pfdValue = CLKCTL2->AUDIOPLL0PFDDOMAINEN & (~(0x7FUL << (8UL * pfdIndex))); CLKCTL2->AUDIOPLL0PFDDOMAINEN = pfdValue | ((domainEnable & (uint32_t)kCLOCK_AllDomainEnable) << (8UL * pfdIndex)); diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_clock.h index 3655e2d8f..ead02ba44 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_clock.h @@ -25,8 +25,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.4.1 */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*! @brief CLOCK driver version 2.5.0 */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) /*@}*/ #if defined(MIMXRT798S_hifi1_SERIES) || defined(MIMXRT798S_cm33_core1_SERIES) || \ @@ -113,9 +113,10 @@ extern volatile uint32_t g_mclkFreq; #if defined(FSL_CLOCK_DRIVER_COMPUTE) || defined(FSL_CLOCK_DRIVER_MEDIA) /*! @brief VDD1(Sense) audio_clk clock frequency. * - *NOTE, The compute domain can't read the Sense VDD1 audio_clk selection. The compute domain need call - *CLOCK_SetSenseAudioClkFreq() to tell the clock driver the frequncy of current VDD1 audio_clk, and then - *CLOCK_GetSenseAudioClkFreq() can return the correct value. + * NOTE, For A0 silicon, the compute domain can't read the Sense VDD1 audio_clk selection. The compute domain need call + * CLOCK_SetSenseAudioClkFreq() to tell the clock driver the frequncy of current VDD1 audio_clk, and then + * CLOCK_GetSenseAudioClkFreq() can return the correct value. For later silicon version(from B0), + * the CLOCK_SetSenseAudioClkFreq is not needed. * @code * CLOCK_SetSenseAudioClkFreq(24000000); * @endcode @@ -314,7 +315,20 @@ extern volatile uint32_t g_senseAudioClkFreq; kCLOCK_TrngRef \ } -#endif /* FSL_CLOCK_DRIVER_COMPUTE */ +#if defined(FSL_CLOCK_DRIVER_MEDIA) +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0, kCLOCK_InputMux1 \ + } +#else +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0 \ + } +#endif /* FSL_CLOCK_DRIVER_MEDIA */ + +#endif /* FSL_CLOCK_DRIVER_COMPUTE || FSL_CLOCK_DRIVER_MEDIA */ #if defined(FSL_CLOCK_DRIVER_SENSE) #ifndef __XTENSA__ @@ -334,6 +348,12 @@ extern volatile uint32_t g_senseAudioClkFreq; { \ kCLOCK_Dma2, kCLOCK_Dma3 \ } + +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux1 \ + } #endif /* FSL_CLOCK_DRIVER_SENSE */ /*! @brief Clock ip name array for CRC. */ @@ -344,27 +364,27 @@ extern volatile uint32_t g_senseAudioClkFreq; #if defined(FSL_CLOCK_DRIVER_COMPUTE) || defined(FSL_CLOCK_DRIVER_MEDIA) /*! @brief Clock ip name array for GDET. */ -#define GDET_CLOCKS \ - { \ +#define GDET_CLOCKS \ + { \ kCLOCK_Gdet0, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Gdet3 \ } /*! @brief Clock ip name array for GDET_REF. */ -#define GDET_REF_CLOCKS \ - { \ +#define GDET_REF_CLOCKS \ + { \ kCLOCK_Gdet0Ref, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Gdet3Ref \ } #endif #if defined(FSL_CLOCK_DRIVER_SENSE) /*! @brief Clock ip name array for GDET. */ -#define GDET_CLOCKS \ - { \ +#define GDET_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Gdet3 \ } /*! @brief Clock ip name array for GDET_REF. */ -#define GDET_REF_CLOCKS \ - { \ +#define GDET_REF_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Gdet3Ref \ } #endif @@ -2038,6 +2058,11 @@ uint32_t CLOCK_GetTpiuClkFreq(void); */ uint32_t CLOCK_GetTrngClkFreq(void); +/*! @brief Return Frequency of VDD2 ClockOut + * @return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void); + #else /* Sense domain specific APIs */ /*! @brief Return Frequency of VDD1 audio clk @@ -2091,7 +2116,7 @@ void CLOCK_EnableFroClkFreq(FRO_Type *base, uint32_t targetFreq, uint32_t divOut * @code * const clock_fro_config_t config = { * .targetFreq = 200000000U, - * .range = 50U, + * .range = 100U, * .trim1DelayUs = 15U, * .trim2DelayUs = 150U, * .refDiv = 0U, @@ -2100,15 +2125,37 @@ void CLOCK_EnableFroClkFreq(FRO_Type *base, uint32_t targetFreq, uint32_t divOut * }; * CLOCK_EnableFroClkFreqCloseLoop(FRO2, &config, kCLOCK_FroAllOutEn); * @endcode + * If the API returns kStatus_Timeout or kStatus_Fail, the CLOCK_FroTuneOnce and trim value from AUTOTRIM register can + * be used to get the desired frequency in open loop mode. * @param base : base address of FRO. * @param config : The configuration for FRO. * @param divOutEnable : Or'ed value of clock_fro_output_en_t to enable certain clock freq output. * @retval kStatus_Success successfully tuned to the target configuration. * @retval kStatus_InvalidArgument Invalid arguement. - * @retval kStatus_Fail failed to lock to the target frequency. + * @retval kStatus_Timeout Timeout to lock to the target frequency. The config->range may too strict(Suggested range >=100) + * or the auto tuner can't lock to the desired frequency. + * @retval kStatus_Fail The FRO locked with error. */ status_t CLOCK_EnableFroClkFreqCloseLoop(FRO_Type *base, const clock_fro_config_t *config, uint32_t divOutEnable); +/*! @brief FRO Tune once. Use FRO tuneonce feature to calculate the FRO output frequency with given trimVal. + * The FRO should be powered up and reference clock(SOSC) should be enabled. + * @param base : base address of FRO. + * @param trimVal : trim value. + * @return FRO frequency in Hz. + */ +uint32_t CLOCK_FroTuneOnce(FRO_Type *base, uint16_t trimVal); + +/*! @brief Fine tune FRO output frequency in open loop mode. + * The FRO should be powered up and reference clock(SOSC) should be enabled. The API uses the FRO tuneonce feature to + * try trim values from (trimVal-1, trimVal, trimVal+1) and select a best one. + * @param base : base address of FRO. + * @param targetFreq : Target frequency in Hz. + * @param trimVal : trim value. When CLOCK_EnableFroClkFreqCloseLoop failed to lock, the value in FRO AUTOTRIM register + * can be used to do fine tune. + */ +void CLOCK_FroFineTune(FRO_Type *base, uint32_t targetFreq, uint16_t trimVal); + /*! @brief Get FRO flags. * @param base : base address of FRO. * @param flags Or'ed value of #_clock_fro_flag. @@ -2264,8 +2311,8 @@ void CLOCK_EnableAudioPllVcoClkForDomain(uint32_t domainEnable); */ void CLOCK_InitMainPll(const clock_main_pll_config_t *config); -/*! brief Deinit the Main PLL. - * param none. +/*! @brief Deinit the Main PLL. + * @param none. */ static inline void CLOCK_DeinitMainPll(void) { @@ -2286,11 +2333,12 @@ static inline void CLOCK_DeinitMainPll(void) */ status_t CLOCK_InitMainPfd(clock_pfd_t pfd, uint8_t divider); -/*! brief Disable the Main PLL PFD. - * param pfd : Which PFD clock to disable. +/*! @brief Disable the Main PLL PFD. + * @param pfd : Which PFD clock to disable. */ static inline void CLOCK_DeinitMainPfd(clock_pfd_t pfd) { + assert(pfd <= kCLOCK_Pfd3); CLKCTL2->MAINPLL0PFD |= ((uint32_t)CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd)); } @@ -2299,8 +2347,8 @@ static inline void CLOCK_DeinitMainPfd(clock_pfd_t pfd) */ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); -/*! brief Deinit the Audio PLL. - * param none. +/*! @brief Deinit the Audio PLL. + * @param none. */ static inline void CLOCK_DeinitAudioPll(void) { @@ -2322,11 +2370,12 @@ static inline void CLOCK_DeinitAudioPll(void) * @note It is recommended that PFD settings are kept between 12-35. */ status_t CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider); -/*! brief Disable the audio PLL PFD. - * param pfd : Which PFD clock to disable. +/*! @brief Disable the audio PLL PFD. + * @param pfd : Which PFD clock to disable. */ -static inline void CLOCK_DeinitAudioPfd(uint32_t pfd) +static inline void CLOCK_DeinitAudioPfd(clock_pfd_t pfd) { + assert(pfd <= kCLOCK_Pfd3); CLKCTL2->AUDIOPLL0PFD |= ((uint32_t)CLKCTL2_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd)); } @@ -2509,11 +2558,6 @@ uint32_t CLOCK_GetMicfilClkFreq(void); */ uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); -/*! @brief Return Frequency of VDD2 ClockOut - * @return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void); - /*! @brief Return Frequency of VDD1 Clock Out * @return Frequency of ClockOut of sense domain */ @@ -2560,31 +2604,31 @@ uint32_t CLOCK_GetMipiDphyEscTxClkFreq(void); */ uint32_t CLOCK_GetUsdhcClkFreq(uint32_t id); -/*! brief Enable USB HS PHY PLL clock. +/*! @brief Enable USB HS PHY PLL clock. * * This function enables the internal 480MHz USB PHY PLL clock. * - * param src USB HS PHY PLL clock source. - * param freq The frequency specified by src. - * retval true The clock is set successfully. - * retval false The clock source is invalid to get proper USB HS clock. + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. */ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); -/*! brief Enable USB HS clock. +/*! @brief Enable USB HS clock. * * This function only enables the access to USB HS prepheral, upper layer * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY * clock to use USB HS. * - * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. - * param freq USB HS does not care about the clock source, so this parameter is ignored. - * retval true The clock is set successfully. - * retval false The clock source is invalid to get proper USB HS clock. + * @param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. */ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); -/*! brief Disable USB HS PHY PLL clock. +/*! @brief Disable USB HS PHY PLL clock. * * This function disables USB HS PHY PLL clock. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_ezhv.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_ezhv.c index edbb52e2b..b2f33c629 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_ezhv.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_ezhv.c @@ -60,7 +60,7 @@ void EZHV_InstallFirmware(ezhv_copy_image_t *ezhvCopyImage) srcAddr = ezhvCopyImage->srcAddr; size = ezhvCopyImage->size; - memcpy((void*)(uint32_t*)dstAddr, (const void*)(uint32_t*)srcAddr, size); + (void)memcpy((void*)(uint32_t*)dstAddr, (const void*)(uint32_t*)srcAddr, size); } void EZHV_Boot(uint32_t bootAddr) @@ -75,7 +75,7 @@ void EZHV_Boot(uint32_t bootAddr) void EZHV_SetPara(ezhv_param_t *para) { assert(para != NULL); - memcpy((void*)EZHV_SHARED_DATA_ADDR, para, sizeof(ezhv_param_t)); + (void)memcpy((void*)EZHV_SHARED_DATA_ADDR, (void const*)para, sizeof(ezhv_param_t)); } uint32_t *EZHV_GetParaAddr(void) @@ -120,7 +120,7 @@ static void EZHV_HandleIRQ(void) { for (uint32_t id = 0U; id < EZHV_INT_CHAN_NUM; id++) { - if ((0U != (intFlag & (1U << id))) && (NULL != s_ezhvCallback[id])) + if ((0U != (intFlag & (1UL << id))) && (NULL != s_ezhvCallback[id])) { s_ezhvCallback[id](s_ezhvCallbackParam[id]); } diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_ezhv.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_ezhv.h index 2f6f0f804..18886870f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_ezhv.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_ezhv.h @@ -32,7 +32,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief cache driver version. */ -#define FSL_EZHV_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +#define FSL_EZHV_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*@}*/ /*! @brief define callback function for EZH-V @@ -244,7 +244,7 @@ static inline void EZHV_ClearEzhv2ArmIntChan(ezhv2arm_int_chan_t chan) /*! * @brief Get EZH-V stop status flag */ -static inline bool EZHV_GetEzhvStopStatusFlag() +static inline bool EZHV_GetEzhvStopStatusFlag(void) { return (bool)((SLEEPCON0->SHA_MED_CSTAT0 & SLEEPCON0_SHA_MED_CSTAT0_EZHV_STOPPED_MASK) >> SLEEPCON0_SHA_MED_CSTAT0_EZHV_STOPPED_SHIFT); } @@ -252,7 +252,7 @@ static inline bool EZHV_GetEzhvStopStatusFlag() /*! * @brief Get EZH-V halt status flag */ -static inline bool EZHV_GetEzhvHaltStatusFlag() +static inline bool EZHV_GetEzhvHaltStatusFlag(void) { return (bool)((SLEEPCON0->SHA_MED_CSTAT0 & SLEEPCON0_SHA_MED_CSTAT0_EZHV_HALTED_MASK) >> SLEEPCON0_SHA_MED_CSTAT0_EZHV_HALTED_SHIFT); } @@ -260,7 +260,7 @@ static inline bool EZHV_GetEzhvHaltStatusFlag() /*! * @brief Get EZH-V wait status flag */ -static inline bool EZHV_GetEzhvWaitStatusFlag() +static inline bool EZHV_GetEzhvWaitStatusFlag(void) { return (bool)((SLEEPCON0->SHA_MED_CSTAT0 & SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAITING_MASK) >> SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAITING_SHIFT); } @@ -268,7 +268,7 @@ static inline bool EZHV_GetEzhvWaitStatusFlag() /*! * @brief Get EZH-V wakeup status flag */ -static inline bool EZHV_GetEzhvWakeupStatusFlag() +static inline bool EZHV_GetEzhvWakeupStatusFlag(void) { return (bool)((SLEEPCON0->SHA_MED_CSTAT0 & SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAKEUP_MASK) >> SLEEPCON0_SHA_MED_CSTAT0_EZHV_WAKEUP_SHIFT); } diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_inputmux_connections.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_inputmux_connections.h index 68ae8df80..17f2e2b65 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_inputmux_connections.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_inputmux_connections.h @@ -17,6 +17,24 @@ #define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" #endif +/*! @name Driver version */ +/*@{*/ +/*! @brief INPUTMUX_CONNECTION driver version 2.0.1. */ +#define FSL_INPUTMUX_CONNECTION_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* Driver compatibility definitions. */ +#ifndef INPUTMUX_BASE_PTRS +#if defined(INPUTMUX0) && defined(INPUTMUX1) +#define INPUTMUX_BASE_PTRS { INPUTMUX0, INPUTMUX1 } +#elif defined(INPUTMUX0) +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#elif defined(INPUTMUX1) +#define INPUTMUX_BASE_PTRS { INPUTMUX1 } +#else +#error "Unsupported core!" +#endif /* INPUTMUX0 && INPUTMUX1 */ +#endif /* INPUTMUX_BASE_PTRS */ /*! * @addtogroup inputmux_driver * @{ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_iopctl.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_iopctl.h index 7053b5515..524bd5a38 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_iopctl.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_iopctl.h @@ -94,11 +94,11 @@ __STATIC_INLINE void IOPCTL_PinMuxSet(uint8_t port, uint8_t pin, uint32_t modefu if (port >= 8U) /* IOPCTL_VDD1 */ { - pioBase = (uint32_t)IOPCTL1 + (uint32_t)((port - 8U) * 32U + pin) * 4UL; + pioBase = (uint32_t)IOPCTL1 + ((uint32_t)(port - 8U) * 32U + (uint32_t)pin) * 4UL; } else if (port >= 4U) /* IOPCTL_VDDN */ { - pioBase = (uint32_t)IOPCTL2 + (uint32_t)((port - 4U) * 32U + pin) * 4UL; + pioBase = (uint32_t)IOPCTL2 + ((uint32_t)(port - 4U) * 32U + (uint32_t)pin) * 4UL; } else /* IOPCTL_VDD2 */ { @@ -106,7 +106,7 @@ __STATIC_INLINE void IOPCTL_PinMuxSet(uint8_t port, uint8_t pin, uint32_t modefu defined(MIMXRT758S_cm33_core1_SERIES) || defined(MIMXRT735S_hifi1_SERIES) || defined(MIMXRT735S_cm33_core1_SERIES) assert(false); #else - pioBase = (uint32_t)IOPCTL0 + (uint32_t)(port * 32U + pin) * 4UL; + pioBase = (uint32_t)IOPCTL0 + ((uint32_t)port * 32U + (uint32_t)pin) * 4UL; #endif } diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_power.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_power.c index bbdb92071..3a277094f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_power.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_power.c @@ -1,5 +1,5 @@ /* - * Copyright 2023-2024 NXP + * Copyright 2023-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -103,9 +103,9 @@ (SLEEPCON1_SHA_MEDSEN_TSTAT0_FLEXIO_B_LPACCEPT_MASK | SLEEPCON1_SHA_MEDSEN_TSTAT0_MICFIL_STOP_MASK) #endif /* PMC PDSLEEPCFG0. Note, when V2COM_DSR other VDD2 and VDDN switches should be off. */ -#define PCFG0_DEEP_SLEEP \ - (PMC_PDSLEEPCFG0_V2DSP_PD_MASK | PMC_PDSLEEPCFG0_V2MIPI_PD_MASK | PMC_PDSLEEPCFG0_DCDC_LP_MASK | \ - PMC_PDSLEEPCFG0_V2NMED_DSR_MASK | PMC_PDSLEEPCFG0_VNCOM_DSR_MASK) +#define PCFG0_DEEP_SLEEP \ + (PMC_PDSLEEPCFG0_V2DSP_PD_MASK | PMC_PDSLEEPCFG0_V2MIPI_PD_MASK | PMC_PDSLEEPCFG0_V2NMED_DSR_MASK | \ + PMC_PDSLEEPCFG0_VNCOM_DSR_MASK) #define PCFG0_DSR \ (PMC_PDSLEEPCFG0_V2COMP_DSR_MASK | PMC_PDSLEEPCFG0_V2NMED_DSR_MASK | PMC_PDSLEEPCFG0_V2COM_DSR_MASK | \ PMC_PDSLEEPCFG0_VNCOM_DSR_MASK) @@ -121,8 +121,7 @@ #define PCFG4_DEEP_SLEEP (0xFFFFFFFFU) #define PCFG5_DEEP_SLEEP (0xFFFFFFFFU) -#define POWER_FREQ_LEVELS_NUM (5U) -#define POWER_DEFAULT_LVD_VOLT (200000U) /* Default LVD threshold 200mV. */ +#define POWER_FREQ_LEVELS_NUM (5U) #define POWER_INVALID_VOLT_LEVEL (0xFFFFFFFFU) /*! Invalid voltage level. */ #define POWER_MINI_ACTIVE_VOLT (700000U) /* Minimum VDD1/VDD2 volt for active mode. */ @@ -321,6 +320,8 @@ void POWER_DisableInterrupts(uint32_t interruptMask) void EnableDeepSleepIRQ(IRQn_Type interrupt) { + assert(interrupt < NUMBER_OF_INT_VECTORS - 16U); + uint32_t intNumber = (uint32_t)interrupt; #if defined(PMC0) @@ -354,6 +355,8 @@ void EnableDeepSleepIRQ(IRQn_Type interrupt) void DisableDeepSleepIRQ(IRQn_Type interrupt) { + assert(interrupt < NUMBER_OF_INT_VECTORS - 16U); + uint32_t intNumber = (uint32_t)interrupt; /* also disable interrupt at NVIC */ @@ -456,7 +459,8 @@ static uint32_t POWER_CalRegValueFromVolt(uint32_t volt, uint32_t base, uint32_t } else { - temp = volt - base - 1U; /* Rounding up.*/ + temp = volt - base - 1U; /* Rounding up.*/ + assert(temp < (UINT32_MAX - slope)); regValue = (uint32_t)((temp + slope) / slope); } @@ -497,7 +501,7 @@ uint32_t POWER_CalcVoltLevel(power_regulator_t regulator, uint32_t maxFreqHz, ui static void POWER_SetRegulatorRegister(power_regulator_t regulator, uint32_t ldoVolt, uint32_t lvdVolt, uint32_t index) { - assert(index < 4); + assert(index < 4U); uint32_t shift = index * 8UL; uint32_t ldoReg = POWER_CalRegValueFromVolt(ldoVolt, POWER_MINI_LDO_VOLT, POWER_LDO_VOLT_SLOPE); @@ -753,10 +757,20 @@ void POWER_SelectSleepSetpoint(power_regulator_t regulator, uint32_t setpoint) void POWER_SetRunRegulatorMode(power_regulator_t regulator, uint32_t mode) { + assert(mode <= 3U); + if (regulator == kRegulator_DCDC) { - PMC->PDRUNCFG0 &= ~PMC_PDRUNCFG0_DCDC_LP_MASK; - PMC->PDRUNCFG0 |= PMC_PDRUNCFG0_DCDC_LP(mode); + if (SYSCON3->SILICONREV_ID == 0xA0000UL) + { + PMC->PDRUNCFG0 &= ~PMC_PDRUNCFG0_DCDC_MODE_MASK; + PMC->PDRUNCFG0 |= PMC_PDRUNCFG0_DCDC_MODE(mode << 1U); /* A0 only has Bit12 for HP/LP. */ + } + else + { + PMC->PDRUNCFG0 &= ~PMC_PDRUNCFG0_DCDC_MODE_MASK; + PMC->PDRUNCFG0 |= PMC_PDRUNCFG0_DCDC_MODE(mode); + } } else if (regulator == kRegulator_Vdd2LDO) { @@ -772,10 +786,20 @@ void POWER_SetRunRegulatorMode(power_regulator_t regulator, uint32_t mode) void POWER_SetSleepRegulatorMode(power_regulator_t regulator, uint32_t mode) { + assert(mode <= 3U); + if (regulator == kRegulator_DCDC) { - PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_DCDC_LP_MASK; - PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_DCDC_LP(mode); + if (SYSCON3->SILICONREV_ID == 0xA0000UL) + { + PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_DCDC_MODE_MASK; + PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_DCDC_MODE(mode << 1U); /* A0 only has Bit12 for HP/LP. */ + } + else + { + PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_DCDC_MODE_MASK; + PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_DCDC_MODE(mode); + } } else if (regulator == kRegulator_Vdd2LDO) { @@ -822,8 +846,9 @@ void POWER_ConfigRBBVolt(const power_rbb_voltage_t *config) void POWER_SetVddnSupplySrc(power_vdd_src_t src) { +#if defined(FSL_FEATURE_SILICON_VERSION_A) && (FSL_FEATURE_SILICON_VERSION_A != 0U) assert(src == kVddSrc_PMIC); /* The VDDN can't be supplied by DCDC due to ERRATA052405. */ - +#endif s_vddnSrc = src; if (s_vddnSrc == kVddSrc_PMIC) /* If powered by external PMIC, power down DCDC. */ { @@ -1208,6 +1233,8 @@ AT_QUICKACCESS_SECTION_CODE(static void POWER_EnterLowPower_FullConfig(const uin pdsleepcfg0 &= ~(PMC_PDSLEEPCFG0_PMICMODE_MASK | PMC_PDSLEEPCFG0_FDSR_MASK); PMC->PDSLEEPCFG0 = pdsleepcfg0 | ((PCFG0_DEEP_SLEEP | PCFG0_DSR) & ~exclude_from_pd[1]) | PMC_PDSLEEPCFG0_DPD_MASK; + /* Clear DSR bits in PDRUNCFG0. */ + PMC->PDRUNCFG0 &= ~(PMC_PDRUNCFG0_V2NMED_DSR_MASK | PMC_PDRUNCFG0_VNCOM_DSR_MASK); break; case kPower_FullDeepPowerDown: @@ -1359,6 +1386,9 @@ AT_QUICKACCESS_SECTION_CODE(static void POWER_EnterLowPower_FullConfig(const uin /* Init XSPI in case XIP */ initXip(); + /* Clear LVD flags */ + PMC->FLAGS = PMC_FLAGS_LVDVDD1F_MASK | PMC_FLAGS_LVDVDD2F_MASK | PMC_FLAGS_LVDVDDNF_MASK | PMC_FLAGS_AGDET1F_MASK | + PMC_FLAGS_AGDET2F_MASK; /* Restore PMC LVD core reset and OTP switch setting */ PMC->CTRL = pmc_ctrl; @@ -1574,6 +1604,9 @@ AT_QUICKACCESS_SECTION_CODE(void static POWER_EnterLowPower_FullConfig(const uin POWER_DMA_HWWake_LPRestore(); } + /* Clear LVD flags */ + PMC->FLAGS = PMC_FLAGS_LVDVDD1F_MASK | PMC_FLAGS_LVDVDD2F_MASK | PMC_FLAGS_LVDVDDNF_MASK | PMC_FLAGS_AGDET1F_MASK | + PMC_FLAGS_AGDET2F_MASK; /* Restore PMC LVD core reset and OTP switch setting */ PMC->CTRL = pmc_ctrl; diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_power.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_power.h index c6d42619a..d19891de4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_power.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_power.h @@ -19,8 +19,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief power driver version 2.4.1. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*! @brief power driver version 2.4.2. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) /*@}*/ /* Define the default PMIC modes for power modes. */ @@ -37,6 +37,11 @@ #define POWER_DEFAULT_PMICMODE_FDPD 3U #endif +/* Define the default LVD threshold. */ +#ifndef POWER_DEFAULT_LVD_VOLT +#define POWER_DEFAULT_LVD_VOLT (100000U) /*> 8U) & 0xFFU) @@ -84,7 +89,6 @@ typedef enum pd_bits kPDRUNCFG_DSR_VDDN_COM = MAKE_PD_BITS(PMC_PDRCFG0, 8U), /*!< Power Switch and DSR Enable for the VDDN_COM domain. */ kPDRUNCFG_PD_VDD2_DSP = MAKE_PD_BITS(PMC_PDRCFG0, 9U), /*!< Power switch for the HiFi4 DSP. */ kPDRUNCFG_PD_VDD2_MIPI = MAKE_PD_BITS(PMC_PDRCFG0, 10U), /*!< Power Switch for the MIPI PHY. */ - kPDRUNCFG_LP_DCDC = MAKE_PD_BITS(PMC_PDRCFG0, 12U), /*!< DCDC Low-Power Mode. Deprecated, use POWER_SetRunRegulatorMode. */ kPDRUNCFG_PD_RBB_VDD1 = MAKE_PD_BITS(PMC_PDRCFG0, 22U), /*!< Power Down RBB in VDD1. */ kPDRUNCFG_PD_AFBB_VDD1 = MAKE_PD_BITS(PMC_PDRCFG0, 23U), /*!< Power Down AFBB in VDD1 Domain. */ kPDRUNCFG_PD_RBB_VDD2 = MAKE_PD_BITS(PMC_PDRCFG0, 24U), /*!< Power Down RBB in VDD2 Domain.*/ @@ -549,8 +553,9 @@ enum _power_ldo_mode */ enum _power_dcdc_mode { - kPower_DCDCMode_HP = 0U, /*!< LDO High Power mode. */ - kPower_DCDCMode_LP = 1U, /*!< LDO Low Power mode. */ + kPower_DCDCMode_HP = 0U, /*!< DCDC High Power mode. */ + kPower_DCDCMode_LP = 1U, /*!< DCDC Low Power mode. */ + kPower_DCDCMode_ULP = 3U, /*!< DCDC Ultra Low Power mode. A0 Silicon does not support this mode and will default to low power mode when configured. */ }; /*! @brief VDDN, VDD1 or VDD2 supply source. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_pvts.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_pvts.c index a92cd8398..3d6715928 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_pvts.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_pvts.c @@ -35,7 +35,7 @@ /******************************************************************************* * Prototypes ******************************************************************************/ -static uint32_t delay_to_control_word(uint8_t delay_value); +static uint32_t delay_to_control_word(pvts_delay_t delay_value); #if defined(PVTS0) const uint32_t cpu_freq[PVTS_PVT_COUNT][PVTS_NUM_OF_SP] = {{110000000U, 192000000U, 325000000U}, @@ -76,11 +76,11 @@ status_t PVTS_ReadDelayFromOTP(bool otp_initialized, uint32_t *delayValues) { uint32_t new_delay; - int32_t pvts_fuse_addr_index; + uint32_t pvts_fuse_addr_index; if (!otp_initialized) { - otp_init(); + otp_init(core_freq_hz); } pvts_fuse_addr_index = PVTS_GetFuseAddrIndex(core_freq_hz, (uint32_t)instance); @@ -96,7 +96,7 @@ status_t PVTS_ReadDelayFromOTP(bool otp_initialized, if (!otp_initialized) { - otp_deinit(); + (void)otp_deinit(); } if (!IS_DELAY_VALID(PVTS_GET_DELAY0_FROM_FUSE_VALUE(new_delay))) @@ -121,12 +121,16 @@ status_t PVTS_ReadDelayFromOTP(bool otp_initialized, */ static uint32_t delay_to_control_word(pvts_delay_t delay_value) { - uint32_t delay1, delay0; + uint8_t delay1, delay0; if (delay_value >= PVTS_DELAY_MAX) { return PVTS_DELAY_MAX_CTRL_WORD; } + if (delay_value < PVTS_DELAY_MIN) + { + return PVTS_DELAY_OFF; + } delay1 = delay_value >> 1U; delay0 = delay_value - delay1; diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_pvts.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_pvts.h index e929382c6..312b41c10 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_pvts.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_pvts.h @@ -21,8 +21,8 @@ ******************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief pvts driver version 2.0.0. */ -#define FSL_PVTS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief pvts driver version 2.0.2. */ +#define FSL_PVTS_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ #define PVTS_GET_DELAY0_FROM_FUSE_VALUE(fuse) ((pvts_delay_t)(fuse & 0x00FFU)) /*!< Calculate delay0 value from fuse word. */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_reset.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_reset.h index 4695dc8a0..f758267a3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_reset.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/fsl_reset.h @@ -515,11 +515,9 @@ static inline uint32_t RESET_GetDomainResetStatus(void) * can be used by ROM to reset the flash to default working mode. * @code * FLASH_run_context_t run_ctx = {.U = 0 }; - * // Set the current FLASH mode * run_ctx.B.current_mode = kFlashInstMode_OPI_DDR; - * // Select the FLASH reset sequences * run_ctx.B.restore_sequence = kRestoreSeqence_Send_6699_9966; - * RESET_SetFlashStateContext(run_ctx.U) // Update the context register + * RESET_SetFlashStateContext(run_ctx.U); * @endcode * * @param context Flash state context defined by @ref FLASH_run_context_t. diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/romapi/bootloader/fsl_romapi.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/romapi/bootloader/fsl_romapi.h index e8b02f77c..ccf48d287 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/romapi/bootloader/fsl_romapi.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/drivers/romapi/bootloader/fsl_romapi.h @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,8 +18,17 @@ /*! @name Driver version */ /*@{*/ -/*! @brief ROMAPI driver version 2.0.0. */ -#define FSL_ROMAPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief ROMAPI driver version 2.1.0. + * + * Current version: 2.1.0 + * + * Change log: + * - version 2.1.0 + * - Updated OTP API to support Silicon B0. + * - version 2.0.0 + * - Initial version. + */ +#define FSL_ROMAPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ #define ROM_API_TREE_ADDR (0x1303FC00U) @@ -46,8 +55,8 @@ | | | Prime boot mode | | | | | | | | | 4 - XSPI NOR | | | | | | | | | 5 - LPSPI NOR | | | | | | -| | | 6 - DFU | | | | | | | | | 7 - eMMC | | | | | | +| | | 9 - XSPI NAND | | | | | | */ /* clang-format on */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/fsl_device_registers.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/fsl_device_registers.h index 885372163..078bf2a5d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/fsl_device_registers.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/fsl_device_registers.h @@ -13,15 +13,15 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core0.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core0.c index 4a5868e3f..48a14b4e2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core0.c @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT798S_cm33_core0 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core0.cpp b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core0.cpp index 4a5868e3f..48a14b4e2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core0.cpp +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core0.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT798S_cm33_core0 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core1.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core1.c index 526d36b54..07ada95e4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core1.c @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT798S_cm33_core1 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core1.cpp b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core1.cpp index 526d36b54..07ada95e4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core1.cpp +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/startup_MIMXRT798S_cm33_core1.cpp @@ -1,7 +1,7 @@ //***************************************************************************** // MIMXRT798S_cm33_core1 startup code // -// Version : 200525 +// Version : 220725 //***************************************************************************** // // Copyright 2016-2025 NXP diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core0.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core0.c index 1f7c8a9f8..6b3c69497 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core0.c @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGFOA_cm33_core0 +** Processors: MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT798S_cm33_core0 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S_cm33_core0 * (implementation file) * @@ -58,6 +61,28 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; +/* ---------------------------------------------------------------------------- + -- GlikeyWriteEnable + ---------------------------------------------------------------------------- */ +static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx) +{ + base->CTRL_0 |= GLIKEY_CTRL_0_SFT_RST_MASK; + base->CTRL_0 |= idx; + base->CTRL_0 = GLIKEY_CTRL_0_WR_EN_0(1U) | idx; + base->CTRL_1 = 0x00290000U; + base->CTRL_0 = GLIKEY_CTRL_0_WR_EN_0(2U) | idx; + base->CTRL_1 = 0x00280000U; + base->CTRL_0 = idx; /* Write enable*/ +} + +/* ---------------------------------------------------------------------------- + -- GlikeyClearConfig + ---------------------------------------------------------------------------- */ +static void GlikeyClearConfig(GLIKEY_Type *base) +{ + base->CTRL_0 |= GLIKEY_CTRL_0_SFT_RST_MASK; +} + /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ @@ -84,10 +109,40 @@ __attribute__((weak)) void SystemInit(void) { SYSCON3->TEMPDETECT_CTRL[0] &= ~SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK; } - + if ((SYSCON3->TEMPDETECT_CTRL[1] & SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK) != 0U) { - SYSCON3->TEMPDETECT_CTRL[1] &= ~SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK; + SYSCON3->TEMPDETECT_CTRL[1] &= ~SYSCON3_TEMPDETECT_CTRL_ENABLE_MASK; + } + + if ((SYSCON0->ELS_AS_CFG0 & 0x06009500U) == 0x06009500U) /* Disable aGDET, dGDET, HVD, LVD reset. */ + { + PMC0->CTRL &= ~(PMC_CTRL_AGDET1RE_MASK | PMC_CTRL_AGDET2RE_MASK); + PMC0->INTRCTRL &= ~ (PMC_INTRCTRL_AGDET1IE_MASK | PMC_INTRCTRL_AGDET2IE_MASK); + + if (GDET0->GDET_ENABLE1 != 0U) /* Disable GDET0 */ + { + GlikeyWriteEnable(GLIKEY3, 0U); + SYSCON0->GDET_CTRL[0] = (SYSCON0->GDET_CTRL[0] & (~SYSCON0_GDET_CTRL_GDET_ISO_SW_MASK)) | SYSCON0_GDET_CTRL_GDET_ISO_SW(0x2U); + GDET0->GDET_ENABLE1 = 0U; + CLKCTL0->ONE_SRC_CLKSLICE_ENABLE &= ~CLKCTL0_ONE_SRC_CLKSLICE_ENABLE_DGDET0_FCLK_EN_MASK; + GlikeyClearConfig(GLIKEY3); + } + + if (GDET3->GDET_ENABLE1 != 0U) /* Disable GDET3 */ + { + GlikeyWriteEnable(GLIKEY4, 0U); + SYSCON3->GDET_CTRL[0] = (SYSCON3->GDET_CTRL[0] & (~SYSCON3_GDET_CTRL_GDET_ISO_SW_MASK)) | SYSCON3_GDET_CTRL_GDET_ISO_SW(0x2U); + GDET3->GDET_ENABLE1 = 0U; + CLKCTL3->ONE_SRC_CLKSLICE_ENABLE_SENSE &= ~CLKCTL3_ONE_SRC_CLKSLICE_ENABLE_SENSE_DGDET3_FCLK_EN_MASK; + GlikeyClearConfig(GLIKEY4); + } + + /* Disable aGDET/LVD/HVD input for RAM_ZEROIZE and CHIP_RESET */ + ITRC->OUT_SEL[3][0] = (ITRC->OUT_SEL[3][0] & (~(ITRC_OUT_SEL_IN13_SELn_MASK | ITRC_OUT_SEL_IN14_SELn_MASK | ITRC_OUT_SEL_IN15_SELn_MASK))) | 0xA8000000U; + ITRC->OUT_SEL[4][0] = (ITRC->OUT_SEL[4][0] & (~(ITRC_OUT_SEL_IN13_SELn_MASK | ITRC_OUT_SEL_IN14_SELn_MASK | ITRC_OUT_SEL_IN15_SELn_MASK))) | 0xA8000000U; + ITRC->OUT_SEL_1[3][0] = (ITRC->OUT_SEL_1[3][0] & (~ITRC_OUT_SEL_1_IN16_SELn_MASK)) | 0x2U; + ITRC->OUT_SEL_1[4][0] = (ITRC->OUT_SEL_1[4][0] & (~ITRC_OUT_SEL_1_IN16_SELn_MASK)) | 0x2U; } SYSCON0->DSPSTALL = SYSCON0_DSPSTALL_DSPSTALL_MASK; diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core0.h index 8970be448..654cda3cd 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core0.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGFOA_cm33_core0 +** Processors: MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGFOB_cm33_core0 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT798S_cm33_core0 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S_cm33_core0 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core1.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core1.c index add1a8ecb..07e84e925 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core1.c @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGFOA_cm33_core1 +** Processors: MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT798S_cm33_core1 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S_cm33_core1 * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core1.h index 5f92745c7..e3f72d2e2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_cm33_core1.h @@ -1,16 +1,17 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGFOA_cm33_core1 +** Processors: MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGFOB_cm33_core1 ** -** Compilers: GNU C Compiler +** Compilers: +** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -32,6 +33,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -39,7 +42,7 @@ /*! * @file MIMXRT798S_cm33_core1 * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S_cm33_core1 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_ezhv.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_ezhv.c index 97f7ba068..6206a03f3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_ezhv.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_ezhv.c @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_ezhv -** MIMXRT798SGFOA_ezhv +** Processors: MIMXRT798SGAWBR_ezhv +** MIMXRT798SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MIMXRT798S_ezhv * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S_ezhv * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_ezhv.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_ezhv.h index be858cebd..2cfbcf00f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_ezhv.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_ezhv.h @@ -1,11 +1,11 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_ezhv -** MIMXRT798SGFOA_ezhv +** Processors: MIMXRT798SGAWBR_ezhv +** MIMXRT798SGFOB_ezhv ** -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -27,6 +27,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -34,7 +36,7 @@ /*! * @file MIMXRT798S_ezhv * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S_ezhv (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi1.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi1.c index 1cd1c3ad4..642a4c550 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi1.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi1.c @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGFOA_hifi1 +** Processors: MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -28,6 +28,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -35,7 +37,7 @@ /*! * @file MIMXRT798S * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi1.h index 5c98fd40a..4289be31c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi1.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGFOA_hifi1 +** Processors: MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGFOB_hifi1 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -28,6 +28,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -35,7 +37,7 @@ /*! * @file MIMXRT798S * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi4.c b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi4.c index 8d3827a53..d0d0f30bd 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi4.c +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi4.c @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_hifi4 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -28,6 +28,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -35,7 +37,7 @@ /*! * @file MIMXRT798S * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S * (implementation file) * diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi4.h b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi4.h index 9394c3409..eda99a486 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/MIMXRT798S/system_MIMXRT798S_hifi4.h @@ -1,12 +1,12 @@ /* ** ################################################################### -** Processors: MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_hifi4 ** ** Compiler: Xtensa Compiler -** Reference manual: iMXRT700RM Rev.2 DraftA, 05/2024 -** Version: rev. 3.0, 2024-10-29 -** Build: b250520 +** Reference manual: iMXRT700RM Rev.3, 05/2025 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -28,6 +28,8 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ @@ -35,7 +37,7 @@ /*! * @file MIMXRT798S * @version 1.0 - * @date 2025-05-20 + * @date 2025-07-22 * @brief Device specific configuration file for MIMXRT798S (header file) * * Provides a system configuration function and a global variable that contains diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ADC.h index 7c3e30ceb..725ae061b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ADC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_ADC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for ADC * * CMSIS Peripheral Access Layer for ADC @@ -64,31 +66,31 @@ #if !defined(PERI_ADC_H_) #define PERI_ADC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC0.h index defe10296..418c82f26 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC0.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for AHBSC0 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_AHBSC0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for AHBSC0 * * CMSIS Peripheral Access Layer for AHBSC0 @@ -64,31 +66,31 @@ #if !defined(PERI_AHBSC0_H_) #define PERI_AHBSC0_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC3.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC3.h index 50486b0f1..0d6f79bd7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC3.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC3.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for AHBSC3 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_AHBSC3.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for AHBSC3 * * CMSIS Peripheral Access Layer for AHBSC3 @@ -64,31 +66,31 @@ #if !defined(PERI_AHBSC3_H_) #define PERI_AHBSC3_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC4.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC4.h index 27f053420..78710165b 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_AHBSC4.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for AHBSC4 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_AHBSC4.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for AHBSC4 * * CMSIS Peripheral Access Layer for AHBSC4 @@ -64,31 +66,31 @@ #if !defined(PERI_AHBSC4_H_) #define PERI_AHBSC4_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CACHE64_CTRL.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CACHE64_CTRL.h index 3a93e99b2..771d8e77e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CACHE64_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CACHE64_CTRL.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CACHE64_CTRL @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CACHE64_CTRL.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CACHE64_CTRL * * CMSIS Peripheral Access Layer for CACHE64_CTRL @@ -64,31 +66,31 @@ #if !defined(PERI_CACHE64_CTRL_H_) #define PERI_CACHE64_CTRL_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CACHE64_POLSEL.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CACHE64_POLSEL.h index b08393fad..e55c262a8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CACHE64_POLSEL.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CACHE64_POLSEL.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CACHE64_POLSEL @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CACHE64_POLSEL.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CACHE64_POLSEL * * CMSIS Peripheral Access Layer for CACHE64_POLSEL @@ -64,31 +66,31 @@ #if !defined(PERI_CACHE64_POLSEL_H_) #define PERI_CACHE64_POLSEL_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CDOG.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CDOG.h index c89957967..d1e412bae 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CDOG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CDOG.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CDOG @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CDOG.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CDOG * * CMSIS Peripheral Access Layer for CDOG @@ -64,31 +66,31 @@ #if !defined(PERI_CDOG_H_) #define PERI_CDOG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL0.h index 6586a5e5a..63261035e 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL0.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CLKCTL0 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CLKCTL0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CLKCTL0 * * CMSIS Peripheral Access Layer for CLKCTL0 @@ -64,31 +66,31 @@ #if !defined(PERI_CLKCTL0_H_) #define PERI_CLKCTL0_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -787,6 +789,14 @@ typedef struct { */ #define CLKCTL0_PSCCTL3_PINT0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_PINT0_SHIFT)) & CLKCTL0_PSCCTL3_PINT0_MASK) +#define CLKCTL0_PSCCTL3_PVTS0_MASK (0x40U) +#define CLKCTL0_PSCCTL3_PVTS0_SHIFT (6U) +/*! PVTS0 - PVTS0 Clock + * 0b0..Disable + * 0b1..Enable + */ +#define CLKCTL0_PSCCTL3_PVTS0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_PVTS0_SHIFT)) & CLKCTL0_PSCCTL3_PVTS0_MASK) + #define CLKCTL0_PSCCTL3_FREQME0_MASK (0x100U) #define CLKCTL0_PSCCTL3_FREQME0_SHIFT (8U) /*! FREQME0 - FREQME0 Clock @@ -1459,6 +1469,14 @@ typedef struct { */ #define CLKCTL0_PSCCTL3_SET_PINT0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_PINT0_SHIFT)) & CLKCTL0_PSCCTL3_SET_PINT0_MASK) +#define CLKCTL0_PSCCTL3_SET_PVTS0_MASK (0x40U) +#define CLKCTL0_PSCCTL3_SET_PVTS0_SHIFT (6U) +/*! PVTS0 - PVTS0 Clock + * 0b0..No effect + * 0b1..Enable + */ +#define CLKCTL0_PSCCTL3_SET_PVTS0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_SET_PVTS0_SHIFT)) & CLKCTL0_PSCCTL3_SET_PVTS0_MASK) + #define CLKCTL0_PSCCTL3_SET_FREQME0_MASK (0x100U) #define CLKCTL0_PSCCTL3_SET_FREQME0_SHIFT (8U) /*! FREQME0 - FREQME0 Clock @@ -2131,6 +2149,14 @@ typedef struct { */ #define CLKCTL0_PSCCTL3_CLR_PINT0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_PINT0_SHIFT)) & CLKCTL0_PSCCTL3_CLR_PINT0_MASK) +#define CLKCTL0_PSCCTL3_CLR_PVTS0_MASK (0x40U) +#define CLKCTL0_PSCCTL3_CLR_PVTS0_SHIFT (6U) +/*! PVTS0 - PVTS0 Clock + * 0b0..No effect + * 0b1..Disable + */ +#define CLKCTL0_PSCCTL3_CLR_PVTS0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL3_CLR_PVTS0_SHIFT)) & CLKCTL0_PSCCTL3_CLR_PVTS0_MASK) + #define CLKCTL0_PSCCTL3_CLR_FREQME0_MASK (0x100U) #define CLKCTL0_PSCCTL3_CLR_FREQME0_SHIFT (8U) /*! FREQME0 - FREQME0 Clock diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL1.h index 487425fcd..b5e534a10 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL1.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CLKCTL1 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CLKCTL1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CLKCTL1 * * CMSIS Peripheral Access Layer for CLKCTL1 @@ -64,31 +66,31 @@ #if !defined(PERI_CLKCTL1_H_) #define PERI_CLKCTL1_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -426,6 +428,14 @@ typedef struct { */ #define CLKCTL1_PSCCTL1_WWDT3(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_WWDT3_SHIFT)) & CLKCTL1_PSCCTL1_WWDT3_MASK) +#define CLKCTL1_PSCCTL1_PVTS1_MASK (0x10000000U) +#define CLKCTL1_PSCCTL1_PVTS1_SHIFT (28U) +/*! PVTS1 - PVTS1 Clock + * 0b0..Disable + * 0b1..Enable + */ +#define CLKCTL1_PSCCTL1_PVTS1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_PVTS1_SHIFT)) & CLKCTL1_PSCCTL1_PVTS1_MASK) + #define CLKCTL1_PSCCTL1_INPUTMUX1_MASK (0x40000000U) #define CLKCTL1_PSCCTL1_INPUTMUX1_SHIFT (30U) /*! INPUTMUX1 - INPUTMUX1 Clock @@ -666,6 +676,14 @@ typedef struct { */ #define CLKCTL1_PSCCTL1_SET_WWDT3(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_WWDT3_SHIFT)) & CLKCTL1_PSCCTL1_SET_WWDT3_MASK) +#define CLKCTL1_PSCCTL1_SET_PVTS1_MASK (0x10000000U) +#define CLKCTL1_PSCCTL1_SET_PVTS1_SHIFT (28U) +/*! PVTS1 - PVTS1 Clock + * 0b0..No effect + * 0b1..Enable + */ +#define CLKCTL1_PSCCTL1_SET_PVTS1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_PVTS1_SHIFT)) & CLKCTL1_PSCCTL1_SET_PVTS1_MASK) + #define CLKCTL1_PSCCTL1_SET_INPUTMUX1_MASK (0x40000000U) #define CLKCTL1_PSCCTL1_SET_INPUTMUX1_SHIFT (30U) /*! INPUTMUX1 - INPUTMUX1 Clock @@ -906,6 +924,14 @@ typedef struct { */ #define CLKCTL1_PSCCTL1_CLR_WWDT3(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_WWDT3_SHIFT)) & CLKCTL1_PSCCTL1_CLR_WWDT3_MASK) +#define CLKCTL1_PSCCTL1_CLR_PVTS1_MASK (0x10000000U) +#define CLKCTL1_PSCCTL1_CLR_PVTS1_SHIFT (28U) +/*! PVTS1 - PVTS1 Clock + * 0b0..No effect + * 0b1..Disable + */ +#define CLKCTL1_PSCCTL1_CLR_PVTS1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_PVTS1_SHIFT)) & CLKCTL1_PSCCTL1_CLR_PVTS1_MASK) + #define CLKCTL1_PSCCTL1_CLR_INPUTMUX1_MASK (0x40000000U) #define CLKCTL1_PSCCTL1_CLR_INPUTMUX1_SHIFT (30U) /*! INPUTMUX1 - INPUTMUX1 Clock diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL2.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL2.h index e19a1eca9..8fb450834 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL2.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL2.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CLKCTL2 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CLKCTL2.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CLKCTL2 * * CMSIS Peripheral Access Layer for CLKCTL2 @@ -64,31 +66,31 @@ #if !defined(PERI_CLKCTL2_H_) #define PERI_CLKCTL2_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL3.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL3.h index a11cc4e64..90252cf4a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL3.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL3.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CLKCTL3 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CLKCTL3.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CLKCTL3 * * CMSIS Peripheral Access Layer for CLKCTL3 @@ -64,31 +66,31 @@ #if !defined(PERI_CLKCTL3_H_) #define PERI_CLKCTL3_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -170,8 +172,7 @@ typedef struct { __IO uint32_t SARADCFCLKDIV; /**< ADC0 (SARADC) Functional Clock Divider, offset: 0x624 */ uint8_t RESERVED_14[296]; __IO uint32_t WAKE32KCLKSEL; /**< Wake 32 kHZ Clock Source Select, offset: 0x750 */ - __IO uint32_t WAKE32KCLKDIV; /**< Wake 32kHZ Clock Divider, offset: 0x754 */ - uint8_t RESERVED_15[40]; + uint8_t RESERVED_15[44]; __IO uint32_t MICFILFCLKSEL; /**< MICFIL Functional Clock Source Select, offset: 0x780 */ __IO uint32_t MICFILFCLKDIV; /**< MICFIL Functional Clock Divider, offset: 0x784 */ __IO uint32_t LPI2C15FCLKSEL; /**< LPI2C15 Functional Clock Source Select, offset: 0x788 */ @@ -662,6 +663,16 @@ typedef struct { * 0b11..1m_lposc */ #define CLKCTL3_SENSEBASECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSEBASECLKSEL_SEL_SHIFT)) & CLKCTL3_SENSEBASECLKSEL_SEL_MASK) + +#define CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL_MASK (0xCU) +#define CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL_SHIFT (2U) +/*! AUDIOCLKSEL - VDD1_SENSE Audio Clock Source Select + * 0b00..mclk_in + * 0b01..osc_clk + * 0b10..fro2_div8 + * 0b11..audio_pll_pfd3 + */ +#define CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL_SHIFT)) & CLKCTL3_SENSEBASECLKSEL_AUDIOCLKSEL_MASK) /*! @} */ /*! @name FRO2CLKSTATUS - FRO_TUNER2 Clock Status */ @@ -1017,47 +1028,6 @@ typedef struct { #define CLKCTL3_WAKE32KCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKSEL_SEL_SHIFT)) & CLKCTL3_WAKE32KCLKSEL_SEL_MASK) /*! @} */ -/*! @name WAKE32KCLKDIV - Wake 32kHZ Clock Divider */ -/*! @{ */ - -#define CLKCTL3_WAKE32KCLKDIV_DIV_MASK (0xFFU) -#define CLKCTL3_WAKE32KCLKDIV_DIV_SHIFT (0U) -/*! DIV - Clock Divider Value Select */ -#define CLKCTL3_WAKE32KCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_DIV_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_DIV_MASK) - -#define CLKCTL3_WAKE32KCLKDIV_BUSY_MASK (0x10000000U) -#define CLKCTL3_WAKE32KCLKDIV_BUSY_SHIFT (28U) -/*! BUSY - Busy Flag - * 0b0..The CLKOUT is outputted with the new divider value. - * 0b1..A change is being made to the divider value. - */ -#define CLKCTL3_WAKE32KCLKDIV_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_BUSY_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_BUSY_MASK) - -#define CLKCTL3_WAKE32KCLKDIV_RESET_MASK (0x20000000U) -#define CLKCTL3_WAKE32KCLKDIV_RESET_SHIFT (29U) -/*! RESET - Divider Counter Reset - * 0b0..No effect - * 0b1..Resets the divider counter. - */ -#define CLKCTL3_WAKE32KCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_RESET_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_RESET_MASK) - -#define CLKCTL3_WAKE32KCLKDIV_HALT_MASK (0x40000000U) -#define CLKCTL3_WAKE32KCLKDIV_HALT_SHIFT (30U) -/*! HALT - Divider Counter Halt - * 0b0..No effect - * 0b1..Halts (stops) the divider counter. - */ -#define CLKCTL3_WAKE32KCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_HALT_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_HALT_MASK) - -#define CLKCTL3_WAKE32KCLKDIV_REQFLAG_MASK (0x80000000U) -#define CLKCTL3_WAKE32KCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Request Flag - * 0b0..The change to the divider value has been finished. - * 0b1..A change is being made to the divider value. - */ -#define CLKCTL3_WAKE32KCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL3_WAKE32KCLKDIV_REQFLAG_SHIFT)) & CLKCTL3_WAKE32KCLKDIV_REQFLAG_MASK) -/*! @} */ - /*! @name MICFILFCLKSEL - MICFIL Functional Clock Source Select */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL4.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL4.h index e20e46915..74597947a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CLKCTL4.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CLKCTL4 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CLKCTL4.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CLKCTL4 * * CMSIS Peripheral Access Layer for CLKCTL4 @@ -64,31 +66,31 @@ #if !defined(PERI_CLKCTL4_H_) #define PERI_CLKCTL4_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CMP.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CMP.h index f31d206f9..27ce11e93 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CMP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CMP.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMP @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CMP.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CMP * * CMSIS Peripheral Access Layer for CMP @@ -64,31 +66,31 @@ #if !defined(PERI_CMP_H_) #define PERI_CMP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CRC.h index c2a57e445..3a18b4527 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CRC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CRC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CRC * * CMSIS Peripheral Access Layer for CRC @@ -64,31 +66,31 @@ #if !defined(PERI_CRC_H_) #define PERI_CRC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CTIMER.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CTIMER.h index 0ecc568d1..bfb0e45f2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CTIMER.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_CTIMER.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for CTIMER @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_CTIMER.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for CTIMER * * CMSIS Peripheral Access Layer for CTIMER @@ -64,31 +66,31 @@ #if !defined(PERI_CTIMER_H_) #define PERI_CTIMER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_DEBUG_MAILBOX.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_DEBUG_MAILBOX.h index 4771beeef..5740ef68f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_DEBUG_MAILBOX.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_DEBUG_MAILBOX.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for DEBUG_MAILBOX @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_DEBUG_MAILBOX.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for DEBUG_MAILBOX * * CMSIS Peripheral Access Layer for DEBUG_MAILBOX @@ -64,31 +66,31 @@ #if !defined(PERI_DEBUG_MAILBOX_H_) #define PERI_DEBUG_MAILBOX_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_DMA.h index 320b31a51..e69c065bb 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_DMA.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_DMA.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for DMA * * CMSIS Peripheral Access Layer for DMA @@ -64,31 +66,31 @@ #if !defined(PERI_DMA_H_) #define PERI_DMA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -233,9 +235,9 @@ typedef struct { #define DMA_MP_CSR_GMRC_MASK (0x80U) #define DMA_MP_CSR_GMRC_SHIFT (7U) -/*! GMRC - Global Master ID Replication Control - * 0b0..Master ID replication disabled for all channels - * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting +/*! GMRC - Global Initiator ID Replication Control + * 0b0..Initiator ID replication disabled for all channels + * 0b1..Initiator ID replication available and controlled by each channel's CHn_SBR[EMI] setting */ #define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) @@ -536,7 +538,7 @@ typedef struct { #define DMA_CH_SBR_MID_MASK (0x1FU) #define DMA_CH_SBR_MID_SHIFT (0U) -/*! MID - Master ID */ +/*! MID - Initiator ID */ #define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) #define DMA_CH_SBR_SEC_MASK (0x4000U) @@ -557,9 +559,9 @@ typedef struct { #define DMA_CH_SBR_EMI_MASK (0x10000U) #define DMA_CH_SBR_EMI_SHIFT (16U) -/*! EMI - Enable Master ID Replication - * 0b0..Master ID replication is disabled - * 0b1..Master ID replication is enabled +/*! EMI - Enable Initiator ID Replication + * 0b0..Initiator ID replication is disabled + * 0b1..Initiator ID replication is enabled */ #define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ELS.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ELS.h index e53372c0d..aa9ea4ec9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ELS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ELS.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for ELS @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_ELS.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for ELS * * CMSIS Peripheral Access Layer for ELS @@ -64,31 +66,31 @@ #if !defined(PERI_ELS_H_) #define PERI_ELS_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FLEXIO.h index 1095594b4..5ab5d6554 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FLEXIO.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_FLEXIO.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for FLEXIO * * CMSIS Peripheral Access Layer for FLEXIO @@ -64,31 +66,31 @@ #if !defined(PERI_FLEXIO_H_) #define PERI_FLEXIO_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FREQME.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FREQME.h index 0d1710d88..49bf21e25 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FREQME.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FREQME.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for FREQME @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_FREQME.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for FREQME * * CMSIS Peripheral Access Layer for FREQME @@ -64,31 +66,31 @@ #if !defined(PERI_FREQME_H_) #define PERI_FREQME_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FRO.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FRO.h index b7942fcaa..d5b737c7a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FRO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_FRO.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for FRO @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_FRO.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for FRO * * CMSIS Peripheral Access Layer for FRO @@ -64,31 +66,31 @@ #if !defined(PERI_FRO_H_) #define PERI_FRO_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GDET.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GDET.h index 1d842b7a2..979363732 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GDET.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GDET.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for GDET @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_GDET.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for GDET * * CMSIS Peripheral Access Layer for GDET @@ -64,31 +66,31 @@ #if !defined(PERI_GDET_H_) #define PERI_GDET_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GLIKEY.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GLIKEY.h index 77e102e72..df0781a70 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GLIKEY.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GLIKEY.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for GLIKEY @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_GLIKEY.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for GLIKEY * * CMSIS Peripheral Access Layer for GLIKEY @@ -64,31 +66,31 @@ #if !defined(PERI_GLIKEY_H_) #define PERI_GLIKEY_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GPIO.h index ff57cbdc8..e6432ce0a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_GPIO.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_GPIO.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for GPIO * * CMSIS Peripheral Access Layer for GPIO @@ -64,31 +66,31 @@ #if !defined(PERI_GPIO_H_) #define PERI_GPIO_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_I2S.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_I2S.h index 233e0ac9d..57bd264a2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_I2S.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_I2S.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for I2S @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_I2S.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for I2S * * CMSIS Peripheral Access Layer for I2S @@ -64,31 +66,31 @@ #if !defined(PERI_I2S_H_) #define PERI_I2S_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -392,7 +394,7 @@ typedef struct { /*! TFW - Transmit FIFO Watermark * 0b000..0 * 0b001..1 - * 0b010-0b110..(TFW) + * 0b010-0b110..(TFW value) * 0b111..7 */ #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_I3C.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_I3C.h index 2c41bb229..c9c09e38c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_I3C.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_I3C.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for I3C @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_I3C.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for I3C * * CMSIS Peripheral Access Layer for I3C @@ -64,31 +66,31 @@ #if !defined(PERI_I3C_H_) #define PERI_I3C_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_INPUTMUX0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_INPUTMUX0.h index 334d0a656..ca950ac14 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_INPUTMUX0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_INPUTMUX0.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for INPUTMUX0 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_INPUTMUX0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for INPUTMUX0 * * CMSIS Peripheral Access Layer for INPUTMUX0 @@ -64,31 +66,31 @@ #if !defined(PERI_INPUTMUX0_H_) #define PERI_INPUTMUX0_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_INPUTMUX1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_INPUTMUX1.h index 10d49af6c..735f95d19 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_INPUTMUX1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_INPUTMUX1.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for INPUTMUX1 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_INPUTMUX1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for INPUTMUX1 * * CMSIS Peripheral Access Layer for INPUTMUX1 @@ -64,31 +66,31 @@ #if !defined(PERI_INPUTMUX1_H_) #define PERI_INPUTMUX1_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL0.h index b1bba97ce..f1c5210f8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL0.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOPCTL0 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_IOPCTL0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for IOPCTL0 * * CMSIS Peripheral Access Layer for IOPCTL0 @@ -64,31 +66,31 @@ #if !defined(PERI_IOPCTL0_H_) #define PERI_IOPCTL0_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL1.h index e4137b37f..e0928ac1f 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL1.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOPCTL1 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_IOPCTL1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for IOPCTL1 * * CMSIS Peripheral Access Layer for IOPCTL1 @@ -64,31 +66,31 @@ #if !defined(PERI_IOPCTL1_H_) #define PERI_IOPCTL1_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL2.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL2.h index 18c9ddc62..94259667d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL2.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_IOPCTL2.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for IOPCTL2 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_IOPCTL2.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for IOPCTL2 * * CMSIS Peripheral Access Layer for IOPCTL2 @@ -64,31 +66,31 @@ #if !defined(PERI_IOPCTL2_H_) #define PERI_IOPCTL2_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ITRC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ITRC.h index 198e26a45..2bab5e9c3 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ITRC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ITRC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for ITRC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_ITRC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for ITRC * * CMSIS Peripheral Access Layer for ITRC @@ -64,31 +66,31 @@ #if !defined(PERI_ITRC_H_) #define PERI_ITRC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_JPEGDEC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_JPEGDEC.h index 4ed51045d..629f461b8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_JPEGDEC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_JPEGDEC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for JPEGDEC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_JPEGDEC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for JPEGDEC * * CMSIS Peripheral Access Layer for JPEGDEC @@ -64,31 +66,31 @@ #if !defined(PERI_JPEGDEC_H_) #define PERI_JPEGDEC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_JPGDECWRP.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_JPGDECWRP.h index 1f31ce742..5ca890234 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_JPGDECWRP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_JPGDECWRP.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for JPGDECWRP @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_JPGDECWRP.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for JPGDECWRP * * CMSIS Peripheral Access Layer for JPGDECWRP @@ -64,31 +66,31 @@ #if !defined(PERI_JPGDECWRP_H_) #define PERI_JPGDECWRP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LCDIF.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LCDIF.h index 0e232b868..cdd7ef063 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LCDIF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LCDIF.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for LCDIF @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_LCDIF.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for LCDIF * * CMSIS Peripheral Access Layer for LCDIF @@ -64,31 +66,31 @@ #if !defined(PERI_LCDIF_H_) #define PERI_LCDIF_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPI2C.h index e2bee3255..a513a1283 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPI2C.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_LPI2C.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for LPI2C * * CMSIS Peripheral Access Layer for LPI2C @@ -64,31 +66,31 @@ #if !defined(PERI_LPI2C_H_) #define PERI_LPI2C_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPSPI.h index 3314e2019..d1b6b4942 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPSPI.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_LPSPI.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for LPSPI * * CMSIS Peripheral Access Layer for LPSPI @@ -64,31 +66,31 @@ #if !defined(PERI_LPSPI_H_) #define PERI_LPSPI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPUART.h index ed4fae2f3..9ae45c278 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LPUART.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_LPUART.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for LPUART * * CMSIS Peripheral Access Layer for LPUART @@ -64,31 +66,31 @@ #if !defined(PERI_LPUART_H_) #define PERI_LPUART_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LP_FLEXCOMM.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LP_FLEXCOMM.h index 3483714b0..7a7e41cb9 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LP_FLEXCOMM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_LP_FLEXCOMM.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for LP_FLEXCOMM @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_LP_FLEXCOMM.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for LP_FLEXCOMM * * CMSIS Peripheral Access Layer for LP_FLEXCOMM @@ -64,31 +66,31 @@ #if !defined(PERI_LP_FLEXCOMM_H_) #define PERI_LP_FLEXCOMM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MIPI_DSI_HOST.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MIPI_DSI_HOST.h index ff8f18101..983e069ba 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MIPI_DSI_HOST.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MIPI_DSI_HOST.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIPI_DSI_HOST @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_MIPI_DSI_HOST.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MIPI_DSI_HOST * * CMSIS Peripheral Access Layer for MIPI_DSI_HOST @@ -64,31 +66,31 @@ #if !defined(PERI_MIPI_DSI_HOST_H_) #define PERI_MIPI_DSI_HOST_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MMU.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MMU.h index 1cab79a19..e5e852aaf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MMU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MMU.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MMU @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_MMU.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MMU * * CMSIS Peripheral Access Layer for MMU @@ -64,31 +66,31 @@ #if !defined(PERI_MMU_H_) #define PERI_MMU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MRT.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MRT.h index 21f581ad2..1619aab45 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MRT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MRT.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MRT @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_MRT.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MRT * * CMSIS Peripheral Access Layer for MRT @@ -64,31 +66,31 @@ #if !defined(PERI_MRT_H_) #define PERI_MRT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MU.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MU.h index af6067568..ea086e89c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_MU.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_MU.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for MU * * CMSIS Peripheral Access Layer for MU @@ -64,31 +66,31 @@ #if !defined(PERI_MU_H_) #define PERI_MU_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_NIC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_NIC.h index 27f331c29..3917f5c72 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_NIC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_NIC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for NIC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_NIC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for NIC * * CMSIS Peripheral Access Layer for NIC @@ -64,31 +66,31 @@ #if !defined(PERI_NIC_H_) #define PERI_NIC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OCOTP.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OCOTP.h index d16ae3a6c..70f15c335 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OCOTP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OCOTP.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for OCOTP @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_OCOTP.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for OCOTP * * CMSIS Peripheral Access Layer for OCOTP @@ -64,31 +66,31 @@ #if !defined(PERI_OCOTP_H_) #define PERI_OCOTP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSC32KNP.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSC32KNP.h index b2eefa416..85e6f5348 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSC32KNP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSC32KNP.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSC32KNP @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_OSC32KNP.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for OSC32KNP * * CMSIS Peripheral Access Layer for OSC32KNP @@ -64,31 +66,31 @@ #if !defined(PERI_OSC32KNP_H_) #define PERI_OSC32KNP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSCCA.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSCCA.h index fd3ecbdde..74c607a83 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSCCA.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSCCA.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSCCA @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_OSCCA.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for OSCCA * * CMSIS Peripheral Access Layer for OSCCA @@ -64,31 +66,31 @@ #if !defined(PERI_OSCCA_H_) #define PERI_OSCCA_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSTIMER.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSTIMER.h index 993a99332..b842384d4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSTIMER.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_OSTIMER.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for OSTIMER @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_OSTIMER.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for OSTIMER * * CMSIS Peripheral Access Layer for OSTIMER @@ -64,31 +66,31 @@ #if !defined(PERI_OSTIMER_H_) #define PERI_OSTIMER_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PDM.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PDM.h index 0e850b164..3a53d3368 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PDM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PDM.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for PDM @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_PDM.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for PDM * * CMSIS Peripheral Access Layer for PDM @@ -64,31 +66,31 @@ #if !defined(PERI_PDM_H_) #define PERI_PDM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PINT.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PINT.h index 9af6367ea..72912b71a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PINT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PINT.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for PINT @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_PINT.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for PINT * * CMSIS Peripheral Access Layer for PINT @@ -64,31 +66,31 @@ #if !defined(PERI_PINT_H_) #define PERI_PINT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PKC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PKC.h index b33be0ced..f64fd34be 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PKC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PKC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for PKC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_PKC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for PKC * * CMSIS Peripheral Access Layer for PKC @@ -64,31 +66,31 @@ #if !defined(PERI_PKC_H_) #define PERI_PKC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PMC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PMC.h index 5d8fab8c4..9262dee79 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PMC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PMC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for PMC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_PMC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for PMC * * CMSIS Peripheral Access Layer for PMC @@ -64,31 +66,31 @@ #if !defined(PERI_PMC_H_) #define PERI_PMC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -1443,13 +1445,15 @@ typedef struct { */ #define PMC_PDRUNCFG0_V2MIPI_PD(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_V2MIPI_PD_SHIFT)) & PMC_PDRUNCFG0_V2MIPI_PD_MASK) -#define PMC_PDRUNCFG0_DCDC_LP_MASK (0x1000U) -#define PMC_PDRUNCFG0_DCDC_LP_SHIFT (12U) -/*! DCDC_LP - DCDC Low-Power Mode - * 0b0..Enables DCDC in high-power mode - * 0b1..Enables DCDC in low-power mode +#define PMC_PDRUNCFG0_DCDC_MODE_MASK (0x1800U) +#define PMC_PDRUNCFG0_DCDC_MODE_SHIFT (11U) +/*! DCDC_MODE - DCDC Power Mode + * 0b00..Enables DCDC in high-power mode + * 0b01..Enables DCDC in low-power mode + * 0b10..Enables DCDC in ultra-low-power mode + * 0b11..Enables DCDC in ultra-low-power mode */ -#define PMC_PDRUNCFG0_DCDC_LP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_DCDC_LP_SHIFT)) & PMC_PDRUNCFG0_DCDC_LP_MASK) +#define PMC_PDRUNCFG0_DCDC_MODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_DCDC_MODE_SHIFT)) & PMC_PDRUNCFG0_DCDC_MODE_MASK) #define PMC_PDRUNCFG0_DCDC_VSEL_MASK (0x2000U) #define PMC_PDRUNCFG0_DCDC_VSEL_SHIFT (13U) @@ -2643,13 +2647,15 @@ typedef struct { */ #define PMC_PDSLEEPCFG0_V2MIPI_PD(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_V2MIPI_PD_SHIFT)) & PMC_PDSLEEPCFG0_V2MIPI_PD_MASK) -#define PMC_PDSLEEPCFG0_DCDC_LP_MASK (0x1000U) -#define PMC_PDSLEEPCFG0_DCDC_LP_SHIFT (12U) -/*! DCDC_LP - DCDC Low-Power Mode - * 0b0..Enables DCDC in high-power mode - * 0b1..Enables DCDC in low-power mode +#define PMC_PDSLEEPCFG0_DCDC_MODE_MASK (0x1800U) +#define PMC_PDSLEEPCFG0_DCDC_MODE_SHIFT (11U) +/*! DCDC_MODE - DCDC Power Mode + * 0b00..Enables DCDC in high-power mode + * 0b01..Enables DCDC in low-power mode + * 0b10..Enables DCDC in ultra-low-power mode + * 0b11..Enables DCDC in ultra-low-power mode */ -#define PMC_PDSLEEPCFG0_DCDC_LP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_DCDC_LP_SHIFT)) & PMC_PDSLEEPCFG0_DCDC_LP_MASK) +#define PMC_PDSLEEPCFG0_DCDC_MODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_DCDC_MODE_SHIFT)) & PMC_PDSLEEPCFG0_DCDC_MODE_MASK) #define PMC_PDSLEEPCFG0_DCDC_VSEL_MASK (0x2000U) #define PMC_PDSLEEPCFG0_DCDC_VSEL_SHIFT (13U) @@ -3851,13 +3857,15 @@ typedef struct { */ #define PMC_PDCFGSTATUS0_V2MIPI_PD(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2MIPI_PD_SHIFT)) & PMC_PDCFGSTATUS0_V2MIPI_PD_MASK) -#define PMC_PDCFGSTATUS0_DCDC_LP_MASK (0x1000U) -#define PMC_PDCFGSTATUS0_DCDC_LP_SHIFT (12U) -/*! DCDC_LP - DCDC Low-Power Mode - * 0b0..DCDC in high-power mode - * 0b1..DCDC in low-power mode +#define PMC_PDCFGSTATUS0_DCDC_MODE_MASK (0x1800U) +#define PMC_PDCFGSTATUS0_DCDC_MODE_SHIFT (11U) +/*! DCDC_MODE - DCDC Power Mode + * 0b00..DCDC in high-power mode + * 0b01..DCDC in low-power mode + * 0b10..DCDC in ultra-low-power mode + * 0b11..DCDC in ultra-low-power mode */ -#define PMC_PDCFGSTATUS0_DCDC_LP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_DCDC_LP_SHIFT)) & PMC_PDCFGSTATUS0_DCDC_LP_MASK) +#define PMC_PDCFGSTATUS0_DCDC_MODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_DCDC_MODE_SHIFT)) & PMC_PDCFGSTATUS0_DCDC_MODE_MASK) #define PMC_PDCFGSTATUS0_DCDC_VSEL_MASK (0x2000U) #define PMC_PDCFGSTATUS0_DCDC_VSEL_SHIFT (13U) diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PNGDEC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PNGDEC.h index 11e53cf16..2a6636bc2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PNGDEC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PNGDEC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for PNGDEC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_PNGDEC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for PNGDEC * * CMSIS Peripheral Access Layer for PNGDEC @@ -64,31 +66,31 @@ #if !defined(PERI_PNGDEC_H_) #define PERI_PNGDEC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PUF.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PUF.h index 07972d345..57c9045d2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PUF.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PUF.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for PUF @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_PUF.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for PUF * * CMSIS Peripheral Access Layer for PUF @@ -64,31 +66,31 @@ #if !defined(PERI_PUF_H_) #define PERI_PUF_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -157,8 +159,7 @@ typedef struct { __I uint32_t PSR; /**< PUF Score, offset: 0xDC */ __I uint32_t HW_RUC0; /**< Hardware Restrict User Context 0, offset: 0xE0 */ __I uint32_t HW_RUC1; /**< Hardware Restrict User Context 1, offset: 0xE4 */ - uint8_t RESERVED_6[12]; - __I uint32_t HW_INFO; /**< Hardware Information, offset: 0xF4 */ + uint8_t RESERVED_6[16]; __I uint32_t HW_ID; /**< Hardware Identifier, offset: 0xF8 */ __I uint32_t HW_VER; /**< Hardware Version, offset: 0xFC */ __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ @@ -713,26 +714,6 @@ typedef struct { #define PUF_HW_RUC1_APP_CTX(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK) /*! @} */ -/*! @name HW_INFO - Hardware Information */ -/*! @{ */ - -#define PUF_HW_INFO_CONFIG_WRAP_MASK (0x1000000U) -#define PUF_HW_INFO_CONFIG_WRAP_SHIFT (24U) -/*! CONFIG_WRAP - Wrap configuration - * 0b0..Indicates that Wrap is not included - * 0b1..Indicates that Wrap is included - */ -#define PUF_HW_INFO_CONFIG_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK) - -#define PUF_HW_INFO_CONFIG_TYPE_MASK (0xF0000000U) -#define PUF_HW_INFO_CONFIG_TYPE_SHIFT (28U) -/*! CONFIG_TYPE - PUF configuration - * 0b0001..Indicates that PUF configuration is Safe. - * 0b0010..Indicates that PUF configuration is Plus. - */ -#define PUF_HW_INFO_CONFIG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK) -/*! @} */ - /*! @name HW_ID - Hardware Identifier */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PVTS.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PVTS.h index 1b49e00f0..c968b1250 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PVTS.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_PVTS.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for PVTS @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_PVTS.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for PVTS * * CMSIS Peripheral Access Layer for PVTS @@ -64,31 +66,31 @@ #if !defined(PERI_PVTS_H_) #define PERI_PVTS_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ROMCP.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ROMCP.h index 39b7be39b..4ebf11c1d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ROMCP.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_ROMCP.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for ROMCP @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_ROMCP.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for ROMCP * * CMSIS Peripheral Access Layer for ROMCP @@ -64,31 +66,31 @@ #if !defined(PERI_ROMCP_H_) #define PERI_ROMCP_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL0.h index 951c06336..92f55cbf2 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL0.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for RSTCTL0 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_RSTCTL0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for RSTCTL0 * * CMSIS Peripheral Access Layer for RSTCTL0 @@ -64,31 +66,31 @@ #if !defined(PERI_RSTCTL0_H_) #define PERI_RSTCTL0_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL1.h index 24259847f..289c72fdf 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL1.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for RSTCTL1 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_RSTCTL1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for RSTCTL1 * * CMSIS Peripheral Access Layer for RSTCTL1 @@ -64,31 +66,31 @@ #if !defined(PERI_RSTCTL1_H_) #define PERI_RSTCTL1_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL2.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL2.h index 1182aa597..204a80039 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL2.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL2.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for RSTCTL2 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_RSTCTL2.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for RSTCTL2 * * CMSIS Peripheral Access Layer for RSTCTL2 @@ -64,31 +66,31 @@ #if !defined(PERI_RSTCTL2_H_) #define PERI_RSTCTL2_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL3.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL3.h index b2c2e1cb4..5547216d0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL3.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL3.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for RSTCTL3 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_RSTCTL3.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for RSTCTL3 * * CMSIS Peripheral Access Layer for RSTCTL3 @@ -64,31 +66,31 @@ #if !defined(PERI_RSTCTL3_H_) #define PERI_RSTCTL3_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL4.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL4.h index c90595773..bcbb87743 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RSTCTL4.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for RSTCTL4 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_RSTCTL4.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for RSTCTL4 * * CMSIS Peripheral Access Layer for RSTCTL4 @@ -64,31 +66,31 @@ #if !defined(PERI_RSTCTL4_H_) #define PERI_RSTCTL4_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RTC.h index 49d8b8df6..b91773621 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_RTC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_RTC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for RTC * * CMSIS Peripheral Access Layer for RTC @@ -64,31 +66,31 @@ #if !defined(PERI_RTC_H_) #define PERI_RTC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SCT.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SCT.h index c7eeec85f..301ff0bc8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SCT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SCT.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SCT @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SCT.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SCT * * CMSIS Peripheral Access Layer for SCT @@ -64,31 +66,31 @@ #if !defined(PERI_SCT_H_) #define PERI_SCT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SDADC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SDADC.h index 91839b862..16325b7e7 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SDADC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SDADC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SDADC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SDADC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SDADC * * CMSIS Peripheral Access Layer for SDADC @@ -64,31 +66,31 @@ #if !defined(PERI_SDADC_H_) #define PERI_SDADC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SEMA42.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SEMA42.h index 01e025e52..7ac1e2dcd 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SEMA42.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SEMA42.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMA42 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SEMA42.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SEMA42 * * CMSIS Peripheral Access Layer for SEMA42 @@ -64,31 +66,31 @@ #if !defined(PERI_SEMA42_H_) #define PERI_SEMA42_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SLEEPCON0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SLEEPCON0.h index 634f3d4f4..3d7c30714 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SLEEPCON0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SLEEPCON0.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SLEEPCON0 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SLEEPCON0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SLEEPCON0 * * CMSIS Peripheral Access Layer for SLEEPCON0 @@ -64,31 +66,31 @@ #if !defined(PERI_SLEEPCON0_H_) #define PERI_SLEEPCON0_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SLEEPCON1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SLEEPCON1.h index 0e3851852..83c2eeb81 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SLEEPCON1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SLEEPCON1.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SLEEPCON1 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SLEEPCON1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SLEEPCON1 * * CMSIS Peripheral Access Layer for SLEEPCON1 @@ -64,31 +66,31 @@ #if !defined(PERI_SLEEPCON1_H_) #define PERI_SLEEPCON1_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON0.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON0.h index d89f1cc8b..7298a588c 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON0.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON0.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON0 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SYSCON0.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SYSCON0 * * CMSIS Peripheral Access Layer for SYSCON0 @@ -64,31 +66,31 @@ #if !defined(PERI_SYSCON0_H_) #define PERI_SYSCON0_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -229,9 +231,11 @@ typedef struct { __I uint32_t ELS_OTP_LC_STATE_DP; /**< Lifecycle State, offset: 0xB04 */ __IO uint32_t ELS_TEMPORAL_STATE; /**< ELS Temporal State, offset: 0xB08 */ __IO uint32_t ELS_KDF_MASK; /**< Key Derivation Function Mask, offset: 0xB0C */ - uint8_t RESERVED_26[44]; + uint8_t RESERVED_26[40]; + __I uint32_t ELS_BOOT_STATE0; /**< ELS Boot State 0, offset: 0xB38 */ __I uint32_t ELS_BOOT_STATE1; /**< ELS Boot State 1, offset: 0xB3C */ - uint8_t RESERVED_27[40]; + __I uint32_t ELS_BOOT_STATE2; /**< ELS Boot State 2, offset: 0xB40 */ + uint8_t RESERVED_27[36]; __IO uint32_t ELS_ASSET_PROT; /**< ELS Asset Protection, offset: 0xB68 */ uint8_t RESERVED_28[84]; __I uint32_t ELS_AS_UUID[SYSCON0_ELS_AS_UUID_COUNT]; /**< ELS AS UUID, array offset: 0xBC0, array step: 0x4 */ @@ -3487,6 +3491,131 @@ typedef struct { #define SYSCON0_ELS_KDF_MASK_KDF_MASK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON0_ELS_KDF_MASK_KDF_MASK_MASK) /*! @} */ +/*! @name ELS_BOOT_STATE0 - ELS Boot State 0 */ +/*! @{ */ + +#define SYSCON0_ELS_BOOT_STATE0_BOOT_SRC_MASK (0x7U) +#define SYSCON0_ELS_BOOT_STATE0_BOOT_SRC_SHIFT (0U) +/*! BOOT_SRC - Boot Image Source + * 0b000..XSPI NOR instance 0 + * 0b001..XSPI NOR instance 1 + * 0b010..eMMC instance 0 + * 0b011..eMMC instance 1 + * 0b100..Recovery SPI flash image + * 0b101..Serial boot image (execute ISP command used) + * 0b110..XSPI NAND instance 0 + * 0b111..XSPI NAND instance 1 + */ +#define SYSCON0_ELS_BOOT_STATE0_BOOT_SRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_BOOT_SRC_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_BOOT_SRC_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_SB_JUMP_MASK (0x8U) +#define SYSCON0_ELS_BOOT_STATE0_SB_JUMP_SHIFT (3U) +/*! SB_JUMP - SB3 Containing SB_JUMP Command + * 0b0..Fail + * 0b1..Success + */ +#define SYSCON0_ELS_BOOT_STATE0_SB_JUMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_SB_JUMP_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_SB_JUMP_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_PSRAM_MASK (0x30U) +#define SYSCON0_ELS_BOOT_STATE0_PSRAM_SHIFT (4U) +/*! PSRAM - Image XIP or Copy-to-PSRAM + * 0b00..PSRAM is disabled + * 0b01..PSRAM is enabled + */ +#define SYSCON0_ELS_BOOT_STATE0_PSRAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_PSRAM_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_PSRAM_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_IMAGE_TYP_MASK (0xC0U) +#define SYSCON0_ELS_BOOT_STATE0_IMAGE_TYP_SHIFT (6U) +/*! IMAGE_TYP - Image Type + * 0b00..Signed image (ECDSA) + * 0b01..CRC image (CRC) + */ +#define SYSCON0_ELS_BOOT_STATE0_IMAGE_TYP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_IMAGE_TYP_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_IMAGE_TYP_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_SB3_IMAGE_MASK (0x100U) +#define SYSCON0_ELS_BOOT_STATE0_SB3_IMAGE_SHIFT (8U) +/*! SB3_IMAGE - SB3 Image Receive + * 0b0..Fail + * 0b1..Success + */ +#define SYSCON0_ELS_BOOT_STATE0_SB3_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_SB3_IMAGE_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_SB3_IMAGE_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_CDI_DEV_KEY_MASK (0x200U) +#define SYSCON0_ELS_BOOT_STATE0_CDI_DEV_KEY_SHIFT (9U) +/*! CDI_DEV_KEY - CDI Based Device Keys for CSR Harvesting + * 0b0..Fail + * 0b1..CDI device keys derived + */ +#define SYSCON0_ELS_BOOT_STATE0_CDI_DEV_KEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_CDI_DEV_KEY_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_CDI_DEV_KEY_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_CDI_COMP_MASK (0x400U) +#define SYSCON0_ELS_BOOT_STATE0_CDI_COMP_SHIFT (10U) +/*! CDI_COMP - CDI per DICE Specification + * 0b0..Fail + * 0b1..CDI compute done + */ +#define SYSCON0_ELS_BOOT_STATE0_CDI_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_CDI_COMP_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_CDI_COMP_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_TZ_PRESET_DATA_MASK (0x800U) +#define SYSCON0_ELS_BOOT_STATE0_TZ_PRESET_DATA_SHIFT (11U) +/*! TZ_PRESET_DATA - TrustZone Preset Data + * 0b0..Fail + * 0b1..TrustZone preset data loaded + */ +#define SYSCON0_ELS_BOOT_STATE0_TZ_PRESET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_TZ_PRESET_DATA_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_TZ_PRESET_DATA_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_DEBUG_AUTH_MASK (0x1000U) +#define SYSCON0_ELS_BOOT_STATE0_DEBUG_AUTH_SHIFT (12U) +/*! DEBUG_AUTH - Debug Authentication + * 0b0..Fail + * 0b1..Debug authentication done + */ +#define SYSCON0_ELS_BOOT_STATE0_DEBUG_AUTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_DEBUG_AUTH_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_DEBUG_AUTH_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_ITRC_ZEROIZE_MASK (0x2000U) +#define SYSCON0_ELS_BOOT_STATE0_ITRC_ZEROIZE_SHIFT (13U) +/*! ITRC_ZEROIZE - ITRC Zeroize Event + * 0b0..Fail + * 0b1..ITRC zeroize done + */ +#define SYSCON0_ELS_BOOT_STATE0_ITRC_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_ITRC_ZEROIZE_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_ITRC_ZEROIZE_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_XSPI0_IPED_EN_MASK (0x4000U) +#define SYSCON0_ELS_BOOT_STATE0_XSPI0_IPED_EN_SHIFT (14U) +/*! XSPI0_IPED_EN - XSPI0 IPED Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON0_ELS_BOOT_STATE0_XSPI0_IPED_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_XSPI0_IPED_EN_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_XSPI0_IPED_EN_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_XSPI1_IPED_EN_MASK (0x8000U) +#define SYSCON0_ELS_BOOT_STATE0_XSPI1_IPED_EN_SHIFT (15U) +/*! XSPI1_IPED_EN - XSPI1 IPED Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON0_ELS_BOOT_STATE0_XSPI1_IPED_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_XSPI1_IPED_EN_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_XSPI1_IPED_EN_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_BOOT_PIN_STATE_MASK (0x1C00000U) +#define SYSCON0_ELS_BOOT_STATE0_BOOT_PIN_STATE_SHIFT (22U) +/*! BOOT_PIN_STATE - Boot Pin State + * 0b000..kBootPinSrc_eMMC_uSDHC0 + * 0b001..kBootSrc_XSPI0 + * 0b010..kBootSrc_ISP_AUTO + * 0b011..kBootSrc_XSPI1 + * 0b100..Boot pin not working + */ +#define SYSCON0_ELS_BOOT_STATE0_BOOT_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_BOOT_PIN_STATE_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_BOOT_PIN_STATE_MASK) + +#define SYSCON0_ELS_BOOT_STATE0_DED_ERR_DET_MASK (0xE000000U) +#define SYSCON0_ELS_BOOT_STATE0_DED_ERR_DET_SHIFT (25U) +/*! DED_ERR_DET - DED Error Detect + * 0b010..Error detected + * 0b101..No error + */ +#define SYSCON0_ELS_BOOT_STATE0_DED_ERR_DET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE0_DED_ERR_DET_SHIFT)) & SYSCON0_ELS_BOOT_STATE0_DED_ERR_DET_MASK) +/*! @} */ + /*! @name ELS_BOOT_STATE1 - ELS Boot State 1 */ /*! @{ */ @@ -3502,7 +3631,7 @@ typedef struct { * 0b00000011..FIPS_AES_STEN * 0b00000100..FIPS_ECDSA_STEN * 0b00000101..FIPS_DRBG_STEN - * 0b00000110..FIPS_CMAC_STEN + * 0b00000110..FIPS_HMAC_STEN * 0b00000111..FIPS_CKDF_STEN * 0b00001000..FIPS_HKDF_STEN * 0b00001001.. @@ -3534,6 +3663,42 @@ typedef struct { #define SYSCON0_ELS_BOOT_STATE1_PMC0_FLAGS_17_16(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE1_PMC0_FLAGS_17_16_SHIFT)) & SYSCON0_ELS_BOOT_STATE1_PMC0_FLAGS_17_16_MASK) /*! @} */ +/*! @name ELS_BOOT_STATE2 - ELS Boot State 2 */ +/*! @{ */ + +#define SYSCON0_ELS_BOOT_STATE2_VDD_POR_MASK (0x1U) +#define SYSCON0_ELS_BOOT_STATE2_VDD_POR_SHIFT (0U) +/*! VDD_POR - VDD POR + * 0b0..No reset event + * 0b1..Reset event detected + */ +#define SYSCON0_ELS_BOOT_STATE2_VDD_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE2_VDD_POR_SHIFT)) & SYSCON0_ELS_BOOT_STATE2_VDD_POR_MASK) + +#define SYSCON0_ELS_BOOT_STATE2_RESETN_RST_MASK (0x2U) +#define SYSCON0_ELS_BOOT_STATE2_RESETN_RST_SHIFT (1U) +/*! RESETN_RST - RESETN Reset + * 0b0..No reset event + * 0b1..Reset event detected + */ +#define SYSCON0_ELS_BOOT_STATE2_RESETN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE2_RESETN_RST_SHIFT)) & SYSCON0_ELS_BOOT_STATE2_RESETN_RST_MASK) + +#define SYSCON0_ELS_BOOT_STATE2_ISP_AP_RST_MASK (0x4U) +#define SYSCON0_ELS_BOOT_STATE2_ISP_AP_RST_SHIFT (2U) +/*! ISP_AP_RST - ISP_AP Reset + * 0b0..No reset event + * 0b1..Reset event detected + */ +#define SYSCON0_ELS_BOOT_STATE2_ISP_AP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE2_ISP_AP_RST_SHIFT)) & SYSCON0_ELS_BOOT_STATE2_ISP_AP_RST_MASK) + +#define SYSCON0_ELS_BOOT_STATE2_ITRC_SW_RST_MASK (0x8U) +#define SYSCON0_ELS_BOOT_STATE2_ITRC_SW_RST_SHIFT (3U) +/*! ITRC_SW_RST - ITRC_SW Reset + * 0b0..No reset event + * 0b1..Reset event detected + */ +#define SYSCON0_ELS_BOOT_STATE2_ITRC_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON0_ELS_BOOT_STATE2_ITRC_SW_RST_SHIFT)) & SYSCON0_ELS_BOOT_STATE2_ITRC_SW_RST_MASK) +/*! @} */ + /*! @name ELS_ASSET_PROT - ELS Asset Protection */ /*! @{ */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON1.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON1.h index c5eb4b990..cfb6c2d11 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON1.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON1.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON1 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SYSCON1.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SYSCON1 * * CMSIS Peripheral Access Layer for SYSCON1 @@ -64,31 +66,31 @@ #if !defined(PERI_SYSCON1_H_) #define PERI_SYSCON1_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -505,8 +507,8 @@ typedef struct { #define SYSCON1_DSP_VECT_REMAP_STATVECSELECT_MASK (0x1000U) #define SYSCON1_DSP_VECT_REMAP_STATVECSELECT_SHIFT (12U) /*! STATVECSELECT - Static Vector Select - * 0b0..0058_0000h to another address in RAM0 - * 0b1..0060_0000h to another address in RAM1 + * 0b0..Selects the primary static vector address (0058_0000h) + * 0b1..No effect */ #define SYSCON1_DSP_VECT_REMAP_STATVECSELECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON1_DSP_VECT_REMAP_STATVECSELECT_SHIFT)) & SYSCON1_DSP_VECT_REMAP_STATVECSELECT_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON2.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON2.h index 1b90823cc..8314e13f4 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON2.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON2.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON2 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SYSCON2.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SYSCON2 * * CMSIS Peripheral Access Layer for SYSCON2 @@ -64,31 +66,31 @@ #if !defined(PERI_SYSCON2_H_) #define PERI_SYSCON2_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON3.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON3.h index 75e3a66ac..bc156d791 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON3.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON3.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON3 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SYSCON3.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SYSCON3 * * CMSIS Peripheral Access Layer for SYSCON3 @@ -64,31 +66,31 @@ #if !defined(PERI_SYSCON3_H_) #define PERI_SYSCON3_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -138,6 +140,7 @@ #define SYSCON3_GDET_CTRL_2_COUNT 1u #define SYSCON3_TEMPDETECT_CTRL_COUNT 2u #define SYSCON3_SWD_ACCESS_CPU_COUNT 2u +#define SYSCON3_DATA_REGS_COUNT 8u /** SYSCON3 - Register Layout Typedef */ typedef struct { @@ -162,7 +165,9 @@ typedef struct { uint8_t RESERVED_6[656]; __IO uint32_t TEMPDETECT_CTRL[SYSCON3_TEMPDETECT_CTRL_COUNT]; /**< TEMPDETECT0 Control..TEMPDETECT1 Control, array offset: 0x514, array step: 0x4 */ __I uint32_t TEMPDETECT_FLAGS; /**< TEMPDETECT Interrupts Output, offset: 0x51C */ - uint8_t RESERVED_7[736]; + uint8_t RESERVED_7[224]; + __IO uint32_t TEMPDETECT_INT_EN; /**< TEMPDETECT Interrupts Enable, offset: 0x600 */ + uint8_t RESERVED_8[508]; __IO uint32_t SWD_ACCESS_CPU[SYSCON3_SWD_ACCESS_CPU_COUNT]; /**< CPU0 Software Debug Access..CPU1 Software Debug Access, array offset: 0x800, array step: 0x4 */ __IO uint32_t SWD_ACCESS_APBAP; /**< APB-AP Software Debug Access, offset: 0x808 */ __IO uint32_t SWD_ACCESS_AHBAP; /**< AHB-AP Software Debug Access, offset: 0x80C */ @@ -170,11 +175,13 @@ typedef struct { __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0x814 */ __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control, offset: 0x818 */ __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication Beacon, offset: 0x81C */ - uint8_t RESERVED_8[832]; + uint8_t RESERVED_9[832]; __IO uint32_t GRAY_CODE_LSB; /**< Gray to Binary Converter - Gray Code [31:0], offset: 0xB60 */ __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter - Gray Code [63:32], offset: 0xB64 */ __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter - Binary Code [31:0], offset: 0xB68 */ __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter - Binary Code [63:32], offset: 0xB6C */ + uint8_t RESERVED_10[1136]; + uint32_t DATA_REG[SYSCON3_DATA_REGS_COUNT]; /**< Data Register 0..Data Register 7, array offset: 0xFE0, array step: 0x4 */ } SYSCON3_Type; /* ---------------------------------------------------------------------------- @@ -623,6 +630,26 @@ typedef struct { #define SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT1_SHIFT)) & SYSCON3_TEMPDETECT_FLAGS_TEMPDETECT1_MASK) /*! @} */ +/*! @name TEMPDETECT_INT_EN - TEMPDETECT Interrupts Enable */ +/*! @{ */ + +#define SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT0_INT_EN_MASK (0x40U) +#define SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT0_INT_EN_SHIFT (6U) +/*! TEMPDETECT0_INT_EN - TEMPDETECT0 Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT0_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT0_INT_EN_SHIFT)) & SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT0_INT_EN_MASK) + +#define SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT1_INT_EN_MASK (0x80U) +#define SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT1_INT_EN_SHIFT (7U) +/*! TEMPDETECT1_INT_EN - TEMPDETECT1 Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT1_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT1_INT_EN_SHIFT)) & SYSCON3_TEMPDETECT_INT_EN_TEMPDETECT1_INT_EN_MASK) +/*! @} */ + /*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access..CPU1 Software Debug Access */ /*! @{ */ @@ -980,6 +1007,9 @@ typedef struct { #define SYSCON3_BINARY_CODE_MSB_CODE_BIN_63_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON3_BINARY_CODE_MSB_CODE_BIN_63_32_SHIFT)) & SYSCON3_BINARY_CODE_MSB_CODE_BIN_63_32_MASK) /*! @} */ +/* The count of SYSCON3_DATA_REG */ +#define SYSCON3_DATA_REG_COUNT (8U) + /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON4.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON4.h index 3ff8daeee..578f15d7d 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON4.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSCON4.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSCON4 @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SYSCON4.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SYSCON4 * * CMSIS Peripheral Access Layer for SYSCON4 @@ -64,31 +66,31 @@ #if !defined(PERI_SYSCON4_H_) #define PERI_SYSCON4_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSPM.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSPM.h index bf2998516..002a156d0 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSPM.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_SYSPM.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSPM @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_SYSPM.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for SYSPM * * CMSIS Peripheral Access Layer for SYSPM @@ -64,31 +66,31 @@ #if !defined(PERI_SYSPM_H_) #define PERI_SYSPM_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_TRNG.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_TRNG.h index a01f1865e..c45d01355 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_TRNG.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_TRNG.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRNG @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_TRNG.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for TRNG * * CMSIS Peripheral Access Layer for TRNG @@ -64,31 +66,31 @@ #if !defined(PERI_TRNG_H_) #define PERI_TRNG_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USB.h index ab5c053f2..3cd9ddf82 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USB.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for USB @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_USB.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for USB * * CMSIS Peripheral Access Layer for USB @@ -64,31 +66,31 @@ #if !defined(PERI_USB_H_) #define PERI_USB_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBHSDCD.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBHSDCD.h index 543ccdee7..4a728dae6 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBHSDCD.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBHSDCD.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBHSDCD @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_USBHSDCD.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for USBHSDCD * * CMSIS Peripheral Access Layer for USBHSDCD @@ -64,31 +66,31 @@ #if !defined(PERI_USBHSDCD_H_) #define PERI_USBHSDCD_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBNC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBNC.h index dd9552b95..018fafcf8 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBNC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBNC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBNC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_USBNC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for USBNC * * CMSIS Peripheral Access Layer for USBNC @@ -64,31 +66,31 @@ #if !defined(PERI_USBNC_H_) #define PERI_USBNC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBPHY.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBPHY.h index f9c8f8aaa..983a74660 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBPHY.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USBPHY.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for USBPHY @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_USBPHY.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for USBPHY * * CMSIS Peripheral Access Layer for USBPHY @@ -64,31 +66,31 @@ #if !defined(PERI_USBPHY_H_) #define PERI_USBPHY_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USDHC.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USDHC.h index 011c398cb..1f759f964 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USDHC.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_USDHC.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for USDHC @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_USDHC.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for USDHC * * CMSIS Peripheral Access Layer for USDHC @@ -64,31 +66,31 @@ #if !defined(PERI_USDHC_H_) #define PERI_USDHC_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_UTICK.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_UTICK.h index f2bbe9341..e72f6e73a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_UTICK.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_UTICK.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for UTICK @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_UTICK.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for UTICK * * CMSIS Peripheral Access Layer for UTICK @@ -64,31 +66,31 @@ #if !defined(PERI_UTICK_H_) #define PERI_UTICK_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_WWDT.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_WWDT.h index cc25e17ee..1328c3d53 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_WWDT.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_WWDT.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for WWDT @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_WWDT.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for WWDT * * CMSIS Peripheral Access Layer for WWDT @@ -64,31 +66,31 @@ #if !defined(PERI_WWDT_H_) #define PERI_WWDT_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_XCACHE.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_XCACHE.h index ca3ca0d9a..3056879fc 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_XCACHE.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_XCACHE.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCACHE @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_XCACHE.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for XCACHE * * CMSIS Peripheral Access Layer for XCACHE @@ -64,31 +66,31 @@ #if !defined(PERI_XCACHE_H_) #define PERI_XCACHE_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" diff --git a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_XSPI.h b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_XSPI.h index 8e08a593d..8086a9b2a 100644 --- a/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_XSPI.h +++ b/mcux/mcux-sdk-ng/devices/RT/RT700/periph/PERI_XSPI.h @@ -1,34 +1,34 @@ /* ** ################################################################### -** Processors: MIMXRT735SGAWAR_cm33_core0 -** MIMXRT735SGAWAR_cm33_core1 -** MIMXRT735SGAWAR_ezhv -** MIMXRT735SGAWAR_hifi1 -** MIMXRT735SGFOA_cm33_core0 -** MIMXRT735SGFOA_cm33_core1 -** MIMXRT735SGFOA_ezhv -** MIMXRT735SGFOA_hifi1 -** MIMXRT758SGAWAR_cm33_core0 -** MIMXRT758SGAWAR_cm33_core1 -** MIMXRT758SGAWAR_ezhv -** MIMXRT758SGAWAR_hifi1 -** MIMXRT758SGFOA_cm33_core0 -** MIMXRT758SGFOA_cm33_core1 -** MIMXRT758SGFOA_ezhv -** MIMXRT758SGFOA_hifi1 -** MIMXRT798SGAWAR_cm33_core0 -** MIMXRT798SGAWAR_cm33_core1 -** MIMXRT798SGAWAR_ezhv -** MIMXRT798SGAWAR_hifi1 -** MIMXRT798SGAWAR_hifi4 -** MIMXRT798SGFOA_cm33_core0 -** MIMXRT798SGFOA_cm33_core1 -** MIMXRT798SGFOA_ezhv -** MIMXRT798SGFOA_hifi1 -** MIMXRT798SGFOA_hifi4 +** Processors: MIMXRT735SGAWBR_cm33_core0 +** MIMXRT735SGAWBR_cm33_core1 +** MIMXRT735SGAWBR_ezhv +** MIMXRT735SGAWBR_hifi1 +** MIMXRT735SGFOB_cm33_core0 +** MIMXRT735SGFOB_cm33_core1 +** MIMXRT735SGFOB_ezhv +** MIMXRT735SGFOB_hifi1 +** MIMXRT758SGAWBR_cm33_core0 +** MIMXRT758SGAWBR_cm33_core1 +** MIMXRT758SGAWBR_ezhv +** MIMXRT758SGAWBR_hifi1 +** MIMXRT758SGFOB_cm33_core0 +** MIMXRT758SGFOB_cm33_core1 +** MIMXRT758SGFOB_ezhv +** MIMXRT758SGFOB_hifi1 +** MIMXRT798SGAWBR_cm33_core0 +** MIMXRT798SGAWBR_cm33_core1 +** MIMXRT798SGAWBR_ezhv +** MIMXRT798SGAWBR_hifi1 +** MIMXRT798SGAWBR_hifi4 +** MIMXRT798SGFOB_cm33_core0 +** MIMXRT798SGFOB_cm33_core1 +** MIMXRT798SGFOB_ezhv +** MIMXRT798SGFOB_hifi1 +** MIMXRT798SGFOB_hifi4 ** -** Version: rev. 3.0, 2024-10-29 -** Build: b250526 +** Version: rev. 4.0, 2025-06-06 +** Build: b250722 ** ** Abstract: ** CMSIS Peripheral Access Layer for XSPI @@ -48,14 +48,16 @@ ** - rev. 3.0 (2024-10-29) ** Change the device header file from single flat file to multiple files based on peripherals, ** each peripheral with dedicated header file located in periphN folder. +** - rev. 4.0 (2025-06-06) +** B0 initial version ** ** ################################################################### */ /*! * @file PERI_XSPI.h - * @version 3.0 - * @date 2024-10-29 + * @version 4.0 + * @date 2025-06-06 * @brief CMSIS Peripheral Access Layer for XSPI * * CMSIS Peripheral Access Layer for XSPI @@ -64,31 +66,31 @@ #if !defined(PERI_XSPI_H_) #define PERI_XSPI_H_ /**< Symbol preventing repeated inclusion */ -#if (defined(CPU_MIMXRT735SGAWAR_cm33_core0) || defined(CPU_MIMXRT735SGFOA_cm33_core0)) +#if (defined(CPU_MIMXRT735SGAWBR_cm33_core0) || defined(CPU_MIMXRT735SGFOB_cm33_core0)) #include "MIMXRT735S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_cm33_core1) || defined(CPU_MIMXRT735SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT735SGAWBR_cm33_core1) || defined(CPU_MIMXRT735SGFOB_cm33_core1)) #include "MIMXRT735S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_ezhv) || defined(CPU_MIMXRT735SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT735SGAWBR_ezhv) || defined(CPU_MIMXRT735SGFOB_ezhv)) #include "MIMXRT735S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT735SGAWAR_hifi1) || defined(CPU_MIMXRT735SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT735SGAWBR_hifi1) || defined(CPU_MIMXRT735SGFOB_hifi1)) #include "MIMXRT735S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core0) || defined(CPU_MIMXRT758SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core0) || defined(CPU_MIMXRT758SGFOB_cm33_core0)) #include "MIMXRT758S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_cm33_core1) || defined(CPU_MIMXRT758SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT758SGAWBR_cm33_core1) || defined(CPU_MIMXRT758SGFOB_cm33_core1)) #include "MIMXRT758S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_ezhv) || defined(CPU_MIMXRT758SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT758SGAWBR_ezhv) || defined(CPU_MIMXRT758SGFOB_ezhv)) #include "MIMXRT758S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT758SGAWAR_hifi1) || defined(CPU_MIMXRT758SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT758SGAWBR_hifi1) || defined(CPU_MIMXRT758SGFOB_hifi1)) #include "MIMXRT758S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core0) || defined(CPU_MIMXRT798SGFOA_cm33_core0)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core0) || defined(CPU_MIMXRT798SGFOB_cm33_core0)) #include "MIMXRT798S_cm33_core0_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_cm33_core1) || defined(CPU_MIMXRT798SGFOA_cm33_core1)) +#elif (defined(CPU_MIMXRT798SGAWBR_cm33_core1) || defined(CPU_MIMXRT798SGFOB_cm33_core1)) #include "MIMXRT798S_cm33_core1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_ezhv) || defined(CPU_MIMXRT798SGFOA_ezhv)) +#elif (defined(CPU_MIMXRT798SGAWBR_ezhv) || defined(CPU_MIMXRT798SGFOB_ezhv)) #include "MIMXRT798S_ezhv_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi1) || defined(CPU_MIMXRT798SGFOA_hifi1)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi1) || defined(CPU_MIMXRT798SGFOB_hifi1)) #include "MIMXRT798S_hifi1_COMMON.h" -#elif (defined(CPU_MIMXRT798SGAWAR_hifi4) || defined(CPU_MIMXRT798SGFOA_hifi4)) +#elif (defined(CPU_MIMXRT798SGAWBR_hifi4) || defined(CPU_MIMXRT798SGFOB_hifi4)) #include "MIMXRT798S_hifi4_COMMON.h" #else #error "No valid CPU defined!" @@ -211,7 +213,7 @@ typedef struct { __IO uint32_t AHB_ERR_PAYLOAD_HI; /**< AHB Error Payload High, offset: 0x4E0 */ __IO uint32_t AHB_ERR_PAYLOAD_LO; /**< AHB Error Payload Low, offset: 0x4E4 */ __I uint32_t AHB_RD_ERR_ADDR; /**< AHB Read Error Address, offset: 0x4E8 */ - __I uint32_t AHB_RD_ERR_MID; /**< AHB Read Error Manager ID, offset: 0x4EC */ + __I uint32_t AHB_RD_ERR_MID; /**< AHB Read Error Initiator ID, offset: 0x4EC */ __I uint32_t SPNDST_ADDR; /**< Suspend Transaction Address, offset: 0x4F0 */ __IO uint32_t PPWF_TCNT; /**< Page Program Wait Time Counter, offset: 0x4F4 */ __IO uint32_t PPW_RDSR; /**< Page Program Wait Read Status, offset: 0x4F8 */ @@ -284,15 +286,15 @@ typedef struct { __I uint32_t FRAD7_WORD5; /**< Flash Region Word 5 - Compare Status Data, offset: 0x8F4 */ uint8_t RESERVED_23[4]; __IO uint32_t SFP_ARB_TIMEOUT; /**< SFP Arbitration Lock Timeout Counter, offset: 0x8FC */ - __IO uint32_t TG0MDAD; /**< Target Group Manager Domain Access Descriptor, offset: 0x900 */ + __IO uint32_t TG0MDAD; /**< Target Group Initiator Domain Access Descriptor, offset: 0x900 */ __I uint32_t TGSFAR; /**< Target Group SFAR Address, offset: 0x904 */ __IO uint32_t TGSFARS; /**< Target Group SFAR Status, offset: 0x908 */ __IO uint32_t TGIPCRS; /**< Target Group IP Configuration Status, offset: 0x90C */ - __IO uint32_t TG1MDAD; /**< Target Group Manager Domain Access Descriptor, offset: 0x910 */ + __IO uint32_t TG1MDAD; /**< Target Group Initiator Domain Access Descriptor, offset: 0x910 */ uint8_t RESERVED_24[12]; - __IO uint32_t MGC; /**< Manager Global Configuration, offset: 0x920 */ - __IO uint32_t MRC; /**< Manager Read Command, offset: 0x924 */ - __IO uint32_t MTO; /**< Manager Timeout, offset: 0x928 */ + __IO uint32_t MGC; /**< Initiator Global Configuration, offset: 0x920 */ + __IO uint32_t MRC; /**< Initiator Read Command, offset: 0x924 */ + __IO uint32_t MTO; /**< Initiator Timeout, offset: 0x928 */ __I uint32_t FLSEQREQ; /**< Flash Sequence Request, offset: 0x92C */ __I uint32_t FSMSTAT; /**< FSM Status, offset: 0x930 */ __IO uint32_t IPSERROR; /**< IPS Error, offset: 0x934 */ @@ -533,7 +535,7 @@ typedef struct { #define XSPI_BUFCR_MSTRID_MASK (0x1FU) #define XSPI_BUFCR_MSTRID_SHIFT (0U) -/*! MSTRID - Manager ID */ +/*! MSTRID - Initiator ID */ #define XSPI_BUFCR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_BUFCR_MSTRID_SHIFT)) & XSPI_BUFCR_MSTRID_MASK) #define XSPI_BUFCR_ADATSZ_MASK (0x3FF00U) @@ -581,7 +583,7 @@ typedef struct { #define XSPI_BUFCR_ALLMST_MASK (0x80000000U) #define XSPI_BUFCR_ALLMST_SHIFT (31U) -/*! ALLMST - All Manager Enable +/*! ALLMST - All Initiator Enable * 0b0..Disables * 0b1..Enables */ @@ -986,7 +988,7 @@ typedef struct { #define XSPI_DLLSR_DLLA_RANGE_ERR_MASK (0x2000U) #define XSPI_DLLSR_DLLA_RANGE_ERR_SHIFT (13U) -/*! DLLA_RANGE_ERR - DLL Manager Delay Chain Range Error - Flash Memory A +/*! DLLA_RANGE_ERR - DLL Initiator Delay Chain Range Error - Flash Memory A * 0b0..In range * 0b1..Out of range */ @@ -2211,12 +2213,12 @@ typedef struct { #define XSPI_AHB_RD_ERR_ADDR_READDR(x) (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_RD_ERR_ADDR_READDR_SHIFT)) & XSPI_AHB_RD_ERR_ADDR_READDR_MASK) /*! @} */ -/*! @name AHB_RD_ERR_MID - AHB Read Error Manager ID */ +/*! @name AHB_RD_ERR_MID - AHB Read Error Initiator ID */ /*! @{ */ #define XSPI_AHB_RD_ERR_MID_REMID_MASK (0x1FU) #define XSPI_AHB_RD_ERR_MID_REMID_SHIFT (0U) -/*! REMID - Read Error Manager ID */ +/*! REMID - Read Error Initiator ID */ #define XSPI_AHB_RD_ERR_MID_REMID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_AHB_RD_ERR_MID_REMID_SHIFT)) & XSPI_AHB_RD_ERR_MID_REMID_MASK) /*! @} */ @@ -2548,12 +2550,12 @@ typedef struct { #define XSPI_FRAD0_WORD2_MD0ACP_MASK (0x7U) #define XSPI_FRAD0_WORD2_MD0ACP_SHIFT (0U) -/*! MD0ACP - Manager Domain Access Control Policy */ +/*! MD0ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD0_WORD2_MD0ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD0_WORD2_MD0ACP_MASK) #define XSPI_FRAD0_WORD2_MD1ACP_MASK (0x38U) #define XSPI_FRAD0_WORD2_MD1ACP_SHIFT (3U) -/*! MD1ACP - Manager Domain Access Control Policy */ +/*! MD1ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD0_WORD2_MD1ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD0_WORD2_MD1ACP_MASK) #define XSPI_FRAD0_WORD2_EALO_MASK (0x3F000000U) @@ -2580,7 +2582,7 @@ typedef struct { /*! LOCK - Descriptor Lock * 0b00..Unlocks * 0b01..Locks until hard reset - * 0b10..Locks except for manager + * 0b10..Locks except for initiator * 0b11..Locks */ #define XSPI_FRAD0_WORD3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD3_LOCK_SHIFT)) & XSPI_FRAD0_WORD3_LOCK_MASK) @@ -2608,7 +2610,7 @@ typedef struct { #define XSPI_FRAD0_WORD5_CMP_MDID_MASK (0x3FU) #define XSPI_FRAD0_WORD5_CMP_MDID_SHIFT (0U) -/*! CMP_MDID - Captured Manager Value */ +/*! CMP_MDID - Captured Initiator Value */ #define XSPI_FRAD0_WORD5_CMP_MDID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD0_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD0_WORD5_CMP_MDID_MASK) #define XSPI_FRAD0_WORD5_CMP_SA_MASK (0x40U) @@ -2667,12 +2669,12 @@ typedef struct { #define XSPI_FRAD1_WORD2_MD0ACP_MASK (0x7U) #define XSPI_FRAD1_WORD2_MD0ACP_SHIFT (0U) -/*! MD0ACP - Manager Domain Access Control Policy */ +/*! MD0ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD1_WORD2_MD0ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD1_WORD2_MD0ACP_MASK) #define XSPI_FRAD1_WORD2_MD1ACP_MASK (0x38U) #define XSPI_FRAD1_WORD2_MD1ACP_SHIFT (3U) -/*! MD1ACP - Manager Domain Access Control Policy */ +/*! MD1ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD1_WORD2_MD1ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD1_WORD2_MD1ACP_MASK) #define XSPI_FRAD1_WORD2_EALO_MASK (0x3F000000U) @@ -2699,7 +2701,7 @@ typedef struct { /*! LOCK - Descriptor Lock * 0b00..Unlocks * 0b01..Locks until hard reset - * 0b10..Locks except for manager + * 0b10..Locks except for initiator * 0b11..Locks */ #define XSPI_FRAD1_WORD3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD3_LOCK_SHIFT)) & XSPI_FRAD1_WORD3_LOCK_MASK) @@ -2727,7 +2729,7 @@ typedef struct { #define XSPI_FRAD1_WORD5_CMP_MDID_MASK (0x3FU) #define XSPI_FRAD1_WORD5_CMP_MDID_SHIFT (0U) -/*! CMP_MDID - Captured Manager Value */ +/*! CMP_MDID - Captured Initiator Value */ #define XSPI_FRAD1_WORD5_CMP_MDID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD1_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD1_WORD5_CMP_MDID_MASK) #define XSPI_FRAD1_WORD5_CMP_SA_MASK (0x40U) @@ -2786,12 +2788,12 @@ typedef struct { #define XSPI_FRAD2_WORD2_MD0ACP_MASK (0x7U) #define XSPI_FRAD2_WORD2_MD0ACP_SHIFT (0U) -/*! MD0ACP - Manager Domain Access Control Policy */ +/*! MD0ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD2_WORD2_MD0ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD2_WORD2_MD0ACP_MASK) #define XSPI_FRAD2_WORD2_MD1ACP_MASK (0x38U) #define XSPI_FRAD2_WORD2_MD1ACP_SHIFT (3U) -/*! MD1ACP - Manager Domain Access Control Policy */ +/*! MD1ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD2_WORD2_MD1ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD2_WORD2_MD1ACP_MASK) #define XSPI_FRAD2_WORD2_EALO_MASK (0x3F000000U) @@ -2818,7 +2820,7 @@ typedef struct { /*! LOCK - Descriptor Lock * 0b00..Unlocks * 0b01..Locks until hard reset - * 0b10..Locks except for manager + * 0b10..Locks except for initiator * 0b11..Locks */ #define XSPI_FRAD2_WORD3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD3_LOCK_SHIFT)) & XSPI_FRAD2_WORD3_LOCK_MASK) @@ -2846,7 +2848,7 @@ typedef struct { #define XSPI_FRAD2_WORD5_CMP_MDID_MASK (0x3FU) #define XSPI_FRAD2_WORD5_CMP_MDID_SHIFT (0U) -/*! CMP_MDID - Captured Manager Value */ +/*! CMP_MDID - Captured Initiator Value */ #define XSPI_FRAD2_WORD5_CMP_MDID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD2_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD2_WORD5_CMP_MDID_MASK) #define XSPI_FRAD2_WORD5_CMP_SA_MASK (0x40U) @@ -2905,12 +2907,12 @@ typedef struct { #define XSPI_FRAD3_WORD2_MD0ACP_MASK (0x7U) #define XSPI_FRAD3_WORD2_MD0ACP_SHIFT (0U) -/*! MD0ACP - Manager Domain Access Control Policy */ +/*! MD0ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD3_WORD2_MD0ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD3_WORD2_MD0ACP_MASK) #define XSPI_FRAD3_WORD2_MD1ACP_MASK (0x38U) #define XSPI_FRAD3_WORD2_MD1ACP_SHIFT (3U) -/*! MD1ACP - Manager Domain Access Control Policy */ +/*! MD1ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD3_WORD2_MD1ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD3_WORD2_MD1ACP_MASK) #define XSPI_FRAD3_WORD2_EALO_MASK (0x3F000000U) @@ -2937,7 +2939,7 @@ typedef struct { /*! LOCK - Descriptor Lock * 0b00..Unlocks * 0b01..Locks until hard reset - * 0b10..Locks except for manager + * 0b10..Locks except for initiator * 0b11..Locks */ #define XSPI_FRAD3_WORD3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD3_LOCK_SHIFT)) & XSPI_FRAD3_WORD3_LOCK_MASK) @@ -2965,7 +2967,7 @@ typedef struct { #define XSPI_FRAD3_WORD5_CMP_MDID_MASK (0x3FU) #define XSPI_FRAD3_WORD5_CMP_MDID_SHIFT (0U) -/*! CMP_MDID - Captured Manager Value */ +/*! CMP_MDID - Captured Initiator Value */ #define XSPI_FRAD3_WORD5_CMP_MDID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD3_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD3_WORD5_CMP_MDID_MASK) #define XSPI_FRAD3_WORD5_CMP_SA_MASK (0x40U) @@ -3024,12 +3026,12 @@ typedef struct { #define XSPI_FRAD4_WORD2_MD0ACP_MASK (0x7U) #define XSPI_FRAD4_WORD2_MD0ACP_SHIFT (0U) -/*! MD0ACP - Manager Domain Access Control Policy */ +/*! MD0ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD4_WORD2_MD0ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD4_WORD2_MD0ACP_MASK) #define XSPI_FRAD4_WORD2_MD1ACP_MASK (0x38U) #define XSPI_FRAD4_WORD2_MD1ACP_SHIFT (3U) -/*! MD1ACP - Manager Domain Access Control Policy */ +/*! MD1ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD4_WORD2_MD1ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD4_WORD2_MD1ACP_MASK) #define XSPI_FRAD4_WORD2_EALO_MASK (0x3F000000U) @@ -3056,7 +3058,7 @@ typedef struct { /*! LOCK - Descriptor Lock * 0b00..Unlocks * 0b01..Locks until hard reset - * 0b10..Locks except for manager + * 0b10..Locks except for initiator * 0b11..Locks */ #define XSPI_FRAD4_WORD3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD3_LOCK_SHIFT)) & XSPI_FRAD4_WORD3_LOCK_MASK) @@ -3084,7 +3086,7 @@ typedef struct { #define XSPI_FRAD4_WORD5_CMP_MDID_MASK (0x3FU) #define XSPI_FRAD4_WORD5_CMP_MDID_SHIFT (0U) -/*! CMP_MDID - Captured Manager Value */ +/*! CMP_MDID - Captured Initiator Value */ #define XSPI_FRAD4_WORD5_CMP_MDID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD4_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD4_WORD5_CMP_MDID_MASK) #define XSPI_FRAD4_WORD5_CMP_SA_MASK (0x40U) @@ -3143,12 +3145,12 @@ typedef struct { #define XSPI_FRAD5_WORD2_MD0ACP_MASK (0x7U) #define XSPI_FRAD5_WORD2_MD0ACP_SHIFT (0U) -/*! MD0ACP - Manager Domain Access Control Policy */ +/*! MD0ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD5_WORD2_MD0ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD5_WORD2_MD0ACP_MASK) #define XSPI_FRAD5_WORD2_MD1ACP_MASK (0x38U) #define XSPI_FRAD5_WORD2_MD1ACP_SHIFT (3U) -/*! MD1ACP - Manager Domain Access Control Policy */ +/*! MD1ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD5_WORD2_MD1ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD5_WORD2_MD1ACP_MASK) #define XSPI_FRAD5_WORD2_EALO_MASK (0x3F000000U) @@ -3175,7 +3177,7 @@ typedef struct { /*! LOCK - Descriptor Lock * 0b00..Unlocks * 0b01..Locks until hard reset - * 0b10..Locks except for manager + * 0b10..Locks except for initiator * 0b11..Locks */ #define XSPI_FRAD5_WORD3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD3_LOCK_SHIFT)) & XSPI_FRAD5_WORD3_LOCK_MASK) @@ -3203,7 +3205,7 @@ typedef struct { #define XSPI_FRAD5_WORD5_CMP_MDID_MASK (0x3FU) #define XSPI_FRAD5_WORD5_CMP_MDID_SHIFT (0U) -/*! CMP_MDID - Captured Manager Value */ +/*! CMP_MDID - Captured Initiator Value */ #define XSPI_FRAD5_WORD5_CMP_MDID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD5_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD5_WORD5_CMP_MDID_MASK) #define XSPI_FRAD5_WORD5_CMP_SA_MASK (0x40U) @@ -3262,12 +3264,12 @@ typedef struct { #define XSPI_FRAD6_WORD2_MD0ACP_MASK (0x7U) #define XSPI_FRAD6_WORD2_MD0ACP_SHIFT (0U) -/*! MD0ACP - Manager Domain Access Control Policy */ +/*! MD0ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD6_WORD2_MD0ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD6_WORD2_MD0ACP_MASK) #define XSPI_FRAD6_WORD2_MD1ACP_MASK (0x38U) #define XSPI_FRAD6_WORD2_MD1ACP_SHIFT (3U) -/*! MD1ACP - Manager Domain Access Control Policy */ +/*! MD1ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD6_WORD2_MD1ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD6_WORD2_MD1ACP_MASK) #define XSPI_FRAD6_WORD2_EALO_MASK (0x3F000000U) @@ -3294,7 +3296,7 @@ typedef struct { /*! LOCK - Descriptor Lock * 0b00..Unlocks * 0b01..Locks until hard reset - * 0b10..Locks except for manager + * 0b10..Locks except for initiator * 0b11..Locks */ #define XSPI_FRAD6_WORD3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD3_LOCK_SHIFT)) & XSPI_FRAD6_WORD3_LOCK_MASK) @@ -3322,7 +3324,7 @@ typedef struct { #define XSPI_FRAD6_WORD5_CMP_MDID_MASK (0x3FU) #define XSPI_FRAD6_WORD5_CMP_MDID_SHIFT (0U) -/*! CMP_MDID - Captured Manager Value */ +/*! CMP_MDID - Captured Initiator Value */ #define XSPI_FRAD6_WORD5_CMP_MDID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD6_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD6_WORD5_CMP_MDID_MASK) #define XSPI_FRAD6_WORD5_CMP_SA_MASK (0x40U) @@ -3381,12 +3383,12 @@ typedef struct { #define XSPI_FRAD7_WORD2_MD0ACP_MASK (0x7U) #define XSPI_FRAD7_WORD2_MD0ACP_SHIFT (0U) -/*! MD0ACP - Manager Domain Access Control Policy */ +/*! MD0ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD7_WORD2_MD0ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD2_MD0ACP_SHIFT)) & XSPI_FRAD7_WORD2_MD0ACP_MASK) #define XSPI_FRAD7_WORD2_MD1ACP_MASK (0x38U) #define XSPI_FRAD7_WORD2_MD1ACP_SHIFT (3U) -/*! MD1ACP - Manager Domain Access Control Policy */ +/*! MD1ACP - Initiator Domain Access Control Policy */ #define XSPI_FRAD7_WORD2_MD1ACP(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD2_MD1ACP_SHIFT)) & XSPI_FRAD7_WORD2_MD1ACP_MASK) #define XSPI_FRAD7_WORD2_EALO_MASK (0x3F000000U) @@ -3413,7 +3415,7 @@ typedef struct { /*! LOCK - Descriptor Lock * 0b00..Unlocks * 0b01..Locks until hard reset - * 0b10..Locks except for manager + * 0b10..Locks except for initiator * 0b11..Locks */ #define XSPI_FRAD7_WORD3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD3_LOCK_SHIFT)) & XSPI_FRAD7_WORD3_LOCK_MASK) @@ -3441,7 +3443,7 @@ typedef struct { #define XSPI_FRAD7_WORD5_CMP_MDID_MASK (0x3FU) #define XSPI_FRAD7_WORD5_CMP_MDID_SHIFT (0U) -/*! CMP_MDID - Captured Manager Value */ +/*! CMP_MDID - Captured Initiator Value */ #define XSPI_FRAD7_WORD5_CMP_MDID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FRAD7_WORD5_CMP_MDID_SHIFT)) & XSPI_FRAD7_WORD5_CMP_MDID_MASK) #define XSPI_FRAD7_WORD5_CMP_SA_MASK (0x40U) @@ -3486,12 +3488,12 @@ typedef struct { #define XSPI_SFP_ARB_TIMEOUT_SFP_ARB_TOC(x) (((uint32_t)(((uint32_t)(x)) << XSPI_SFP_ARB_TIMEOUT_SFP_ARB_TOC_SHIFT)) & XSPI_SFP_ARB_TIMEOUT_SFP_ARB_TOC_MASK) /*! @} */ -/*! @name TG0MDAD - Target Group Manager Domain Access Descriptor */ +/*! @name TG0MDAD - Target Group Initiator Domain Access Descriptor */ /*! @{ */ #define XSPI_TG0MDAD_MIDMATCH_MASK (0x3FU) #define XSPI_TG0MDAD_MIDMATCH_SHIFT (0U) -/*! MIDMATCH - Manager ID Reference */ +/*! MIDMATCH - Initiator ID Reference */ #define XSPI_TG0MDAD_MIDMATCH(x) (((uint32_t)(((uint32_t)(x)) << XSPI_TG0MDAD_MIDMATCH_SHIFT)) & XSPI_TG0MDAD_MIDMATCH_MASK) #define XSPI_TG0MDAD_MASK_MASK (0xFC0U) @@ -3548,7 +3550,7 @@ typedef struct { #define XSPI_TGSFARS_TG_MID_MASK (0x3FU) #define XSPI_TGSFARS_TG_MID_SHIFT (0U) -/*! TG_MID - Transaction Manager ID */ +/*! TG_MID - Transaction Initiator ID */ #define XSPI_TGSFARS_TG_MID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_TG_MID_SHIFT)) & XSPI_TGSFARS_TG_MID_MASK) #define XSPI_TGSFARS_SA_MASK (0x400U) @@ -3650,12 +3652,12 @@ typedef struct { #define XSPI_TGIPCRS_VLD(x) (((uint32_t)(((uint32_t)(x)) << XSPI_TGIPCRS_VLD_SHIFT)) & XSPI_TGIPCRS_VLD_MASK) /*! @} */ -/*! @name TG1MDAD - Target Group Manager Domain Access Descriptor */ +/*! @name TG1MDAD - Target Group Initiator Domain Access Descriptor */ /*! @{ */ #define XSPI_TG1MDAD_MIDMATCH_MASK (0x3FU) #define XSPI_TG1MDAD_MIDMATCH_SHIFT (0U) -/*! MIDMATCH - Manager ID Reference */ +/*! MIDMATCH - Initiator ID Reference */ #define XSPI_TG1MDAD_MIDMATCH(x) (((uint32_t)(((uint32_t)(x)) << XSPI_TG1MDAD_MIDMATCH_SHIFT)) & XSPI_TG1MDAD_MIDMATCH_MASK) #define XSPI_TG1MDAD_MASK_MASK (0xFC0U) @@ -3698,7 +3700,7 @@ typedef struct { #define XSPI_TG1MDAD_VLD(x) (((uint32_t)(((uint32_t)(x)) << XSPI_TG1MDAD_VLD_SHIFT)) & XSPI_TG1MDAD_VLD_MASK) /*! @} */ -/*! @name MGC - Manager Global Configuration */ +/*! @name MGC - Initiator Global Configuration */ /*! @{ */ #define XSPI_MGC_GCLCKMID_MASK (0x3FU) @@ -3748,7 +3750,7 @@ typedef struct { #define XSPI_MGC_GVLD(x) (((uint32_t)(((uint32_t)(x)) << XSPI_MGC_GVLD_SHIFT)) & XSPI_MGC_GVLD_MASK) /*! @} */ -/*! @name MRC - Manager Read Command */ +/*! @name MRC - Initiator Read Command */ /*! @{ */ #define XSPI_MRC_READ_CMD0_MASK (0x3FU) @@ -3788,7 +3790,7 @@ typedef struct { #define XSPI_MRC_VLDCMD03(x) (((uint32_t)(((uint32_t)(x)) << XSPI_MRC_VLDCMD03_SHIFT)) & XSPI_MRC_VLDCMD03_MASK) /*! @} */ -/*! @name MTO - Manager Timeout */ +/*! @name MTO - Initiator Timeout */ /*! @{ */ #define XSPI_MTO_SFP_ACC_TO_MASK (0xFFFFFFFFU) @@ -3802,7 +3804,7 @@ typedef struct { #define XSPI_FLSEQREQ_REQ_MID_MASK (0x3FU) #define XSPI_FLSEQREQ_REQ_MID_SHIFT (0U) -/*! REQ_MID - Flash Sequence Request Manager ID */ +/*! REQ_MID - Flash Sequence Request Initiator ID */ #define XSPI_FLSEQREQ_REQ_MID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FLSEQREQ_REQ_MID_SHIFT)) & XSPI_FLSEQREQ_REQ_MID_MASK) #define XSPI_FLSEQREQ_REQ_TG_MASK (0x40U) @@ -3887,7 +3889,7 @@ typedef struct { #define XSPI_FSMSTAT_MID_MASK (0x3F00U) #define XSPI_FSMSTAT_MID_SHIFT (8U) -/*! MID - Manager ID */ +/*! MID - Initiator ID */ #define XSPI_FSMSTAT_MID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_FSMSTAT_MID_SHIFT)) & XSPI_FSMSTAT_MID_MASK) #define XSPI_FSMSTAT_CMD_MASK (0x10000U) @@ -3920,7 +3922,7 @@ typedef struct { #define XSPI_IPSERROR_MID_MASK (0x3FU) #define XSPI_IPSERROR_MID_SHIFT (0U) -/*! MID - IPS Manager ID */ +/*! MID - IPS Initiator ID */ #define XSPI_IPSERROR_MID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_IPSERROR_MID_SHIFT)) & XSPI_IPSERROR_MID_MASK) #define XSPI_IPSERROR_TG0LCK_MASK (0x100U) @@ -3957,7 +3959,7 @@ typedef struct { #define XSPI_IPSERROR_TG0MID_MASK (0x1000U) #define XSPI_IPSERROR_TG0MID_SHIFT (12U) -/*! TG0MID - TGn Manager-ID Status +/*! TG0MID - TGn Initiator-ID Status * 0b0..Passed * 0b1..Failed */ @@ -3965,7 +3967,7 @@ typedef struct { #define XSPI_IPSERROR_TG1MID_MASK (0x2000U) #define XSPI_IPSERROR_TG1MID_SHIFT (13U) -/*! TG1MID - TGn Manager-ID Status +/*! TG1MID - TGn Initiator-ID Status * 0b0..Passed * 0b1..Failed */ @@ -4580,7 +4582,7 @@ typedef struct { #define XSPI_TGSFARS_SUB_TG_MID_MASK (0x3FU) #define XSPI_TGSFARS_SUB_TG_MID_SHIFT (0U) -/*! TG_MID - Transaction Manager ID */ +/*! TG_MID - Transaction Initiator ID */ #define XSPI_TGSFARS_SUB_TG_MID(x) (((uint32_t)(((uint32_t)(x)) << XSPI_TGSFARS_SUB_TG_MID_SHIFT)) & XSPI_TGSFARS_SUB_TG_MID_MASK) #define XSPI_TGSFARS_SUB_SA_MASK (0x400U) From 0fc0555da5b37efdfca61c451ccb2e19e7fa307c Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:36:26 +0800 Subject: [PATCH 09/21] hal_nxp: mcux-sdk-ng: Update device/Wireless to sdk 25.09.00 Signed-off-by: Zhaoxiang Jin --- .../KW/KW45B41Z52/KW45B41Z52_COMMON.h | 39 +- .../KW/KW45B41Z52/KW45B41Z52_features.h | 95 +- .../KW/KW45B41Z53/KW45B41Z53_COMMON.h | 39 +- .../KW/KW45B41Z53/KW45B41Z53_features.h | 121 +- .../KW/KW45B41Z82/KW45B41Z82_COMMON.h | 39 +- .../KW/KW45B41Z82/KW45B41Z82_features.h | 95 +- .../KW/KW45B41Z83/KW45B41Z83_COMMON.h | 39 +- .../KW/KW45B41Z83/KW45B41Z83_features.h | 121 +- .../KW45B41Z83/drivers/CMakeLists_clock.txt | 2 +- .../KW45B41Z83/drivers/CMakeLists_romapi.txt | 4 +- .../KW/KW45B41Z83/drivers/fsl_clock.c | 2 +- .../KW/KW45B41Z83/drivers/fsl_clock.h | 17 +- .../KW45B41Z83/drivers/romapi/fsl_flash_api.h | 4 +- .../KW/KW45B41Z83/drivers/romapi/fsl_romapi.c | 8 +- .../KW/KW45Z41052/KW45Z41052_COMMON.h | 39 +- .../KW/KW45Z41052/KW45Z41052_features.h | 95 +- .../KW/KW45Z41053/KW45Z41053_COMMON.h | 39 +- .../KW/KW45Z41053/KW45Z41053_features.h | 121 +- .../KW/KW45Z41082/KW45Z41082_COMMON.h | 39 +- .../KW/KW45Z41082/KW45Z41082_features.h | 95 +- .../KW/KW45Z41083/KW45Z41083_COMMON.h | 39 +- .../KW/KW45Z41083/KW45Z41083_features.h | 121 +- .../KW45Z41083/drivers/CMakeLists_clock.txt | 2 +- .../KW45Z41083/drivers/CMakeLists_romapi.txt | 4 +- .../KW/KW45Z41083/drivers/fsl_clock.h | 17 +- .../KW45Z41083/drivers/romapi/fsl_flash_api.h | 4 +- .../KW/KW45Z41083/drivers/romapi/fsl_romapi.c | 8 +- .../KW/KW47B42Z83/KW47B42Z83_cm33_core0.h | 4 +- .../KW47B42Z83/KW47B42Z83_cm33_core0_COMMON.h | 92 +- .../KW47B42Z83_cm33_core0_features.h | 69 +- .../KW/KW47B42Z83/KW47B42Z83_cm33_core1.h | 4 +- .../KW47B42Z83/KW47B42Z83_cm33_core1_COMMON.h | 92 +- .../KW47B42Z83_cm33_core1_features.h | 69 +- .../KW47B42Z83/system_KW47B42Z83_cm33_core0.c | 4 +- .../KW47B42Z83/system_KW47B42Z83_cm33_core0.h | 4 +- .../KW47B42Z83/system_KW47B42Z83_cm33_core1.c | 4 +- .../KW47B42Z83/system_KW47B42Z83_cm33_core1.h | 4 +- .../KW/KW47B42Z96/KW47B42Z96_cm33_core0.h | 4 +- .../KW47B42Z96/KW47B42Z96_cm33_core0_COMMON.h | 92 +- .../KW47B42Z96_cm33_core0_features.h | 65 +- .../KW/KW47B42Z96/KW47B42Z96_cm33_core1.h | 4 +- .../KW47B42Z96/KW47B42Z96_cm33_core1_COMMON.h | 92 +- .../KW47B42Z96_cm33_core1_features.h | 65 +- .../KW47B42Z96/system_KW47B42Z96_cm33_core0.c | 4 +- .../KW47B42Z96/system_KW47B42Z96_cm33_core0.h | 4 +- .../KW47B42Z96/system_KW47B42Z96_cm33_core1.c | 4 +- .../KW47B42Z96/system_KW47B42Z96_cm33_core1.h | 4 +- .../KW/KW47B42Z97/KW47B42Z97_cm33_core0.h | 4 +- .../KW47B42Z97/KW47B42Z97_cm33_core0_COMMON.h | 92 +- .../KW47B42Z97_cm33_core0_features.h | 69 +- .../KW/KW47B42Z97/KW47B42Z97_cm33_core1.h | 4 +- .../KW47B42Z97/KW47B42Z97_cm33_core1_COMMON.h | 92 +- .../KW47B42Z97_cm33_core1_features.h | 69 +- .../KW47B42Z97/system_KW47B42Z97_cm33_core0.c | 4 +- .../KW47B42Z97/system_KW47B42Z97_cm33_core0.h | 4 +- .../KW47B42Z97/system_KW47B42Z97_cm33_core1.c | 4 +- .../KW47B42Z97/system_KW47B42Z97_cm33_core1.h | 4 +- .../KW/KW47B42ZB2/KW47B42ZB2_cm33_core0.h | 4 +- .../KW47B42ZB2/KW47B42ZB2_cm33_core0_COMMON.h | 92 +- .../KW47B42ZB2_cm33_core0_features.h | 63 +- .../KW/KW47B42ZB2/KW47B42ZB2_cm33_core1.h | 4 +- .../KW47B42ZB2/KW47B42ZB2_cm33_core1_COMMON.h | 92 +- .../KW47B42ZB2_cm33_core1_features.h | 63 +- .../KW47B42ZB2/system_KW47B42ZB2_cm33_core0.c | 4 +- .../KW47B42ZB2/system_KW47B42ZB2_cm33_core0.h | 4 +- .../KW47B42ZB2/system_KW47B42ZB2_cm33_core1.c | 4 +- .../KW47B42ZB2/system_KW47B42ZB2_cm33_core1.h | 4 +- .../KW/KW47B42ZB3/KW47B42ZB3_cm33_core0.h | 4 +- .../KW47B42ZB3/KW47B42ZB3_cm33_core0_COMMON.h | 92 +- .../KW47B42ZB3_cm33_core0_features.h | 67 +- .../KW/KW47B42ZB3/KW47B42ZB3_cm33_core1.h | 4 +- .../KW47B42ZB3/KW47B42ZB3_cm33_core1_COMMON.h | 92 +- .../KW47B42ZB3_cm33_core1_features.h | 67 +- .../KW47B42ZB3/system_KW47B42ZB3_cm33_core0.c | 4 +- .../KW47B42ZB3/system_KW47B42ZB3_cm33_core0.h | 4 +- .../KW47B42ZB3/system_KW47B42ZB3_cm33_core1.c | 4 +- .../KW47B42ZB3/system_KW47B42ZB3_cm33_core1.h | 4 +- .../KW/KW47B42ZB6/KW47B42ZB6_cm33_core0.h | 4 +- .../KW47B42ZB6/KW47B42ZB6_cm33_core0_COMMON.h | 92 +- .../KW47B42ZB6_cm33_core0_features.h | 63 +- .../KW/KW47B42ZB6/KW47B42ZB6_cm33_core1.h | 4 +- .../KW47B42ZB6/KW47B42ZB6_cm33_core1_COMMON.h | 92 +- .../KW47B42ZB6_cm33_core1_features.h | 63 +- .../KW47B42ZB6/system_KW47B42ZB6_cm33_core0.c | 4 +- .../KW47B42ZB6/system_KW47B42ZB6_cm33_core0.h | 4 +- .../KW47B42ZB6/system_KW47B42ZB6_cm33_core1.c | 4 +- .../KW47B42ZB6/system_KW47B42ZB6_cm33_core1.h | 4 +- .../KW/KW47B42ZB7/KW47B42ZB7_cm33_core0.h | 4 +- .../KW47B42ZB7/KW47B42ZB7_cm33_core0_COMMON.h | 92 +- .../KW47B42ZB7_cm33_core0_features.h | 67 +- .../KW/KW47B42ZB7/KW47B42ZB7_cm33_core1.h | 4 +- .../KW47B42ZB7/KW47B42ZB7_cm33_core1_COMMON.h | 92 +- .../KW47B42ZB7_cm33_core1_features.h | 67 +- .../KW47B42ZB7/drivers/CMakeLists_clock.txt | 2 +- .../KW47B42ZB7/drivers/CMakeLists_romapi.txt | 4 +- .../KW/KW47B42ZB7/drivers/fsl_clock.c | 2 +- .../KW/KW47B42ZB7/drivers/fsl_clock.h | 17 +- .../KW47B42ZB7/drivers/romapi/fsl_flash_api.h | 17 +- .../KW/KW47B42ZB7/drivers/romapi/fsl_romapi.c | 24 +- .../KW47B42ZB7/system_KW47B42ZB7_cm33_core0.c | 4 +- .../KW47B42ZB7/system_KW47B42ZB7_cm33_core0.h | 4 +- .../KW47B42ZB7/system_KW47B42ZB7_cm33_core1.c | 4 +- .../KW47B42ZB7/system_KW47B42ZB7_cm33_core1.h | 4 +- .../Wireless/KW/KW47Z42082/KW47Z42082.h | 4 +- .../KW/KW47Z42082/KW47Z42082_COMMON.h | 92 +- .../KW/KW47Z42082/KW47Z42082_features.h | 61 +- .../KW/KW47Z42082/system_KW47Z42082.c | 4 +- .../KW/KW47Z42082/system_KW47Z42082.h | 4 +- .../Wireless/KW/KW47Z42092/KW47Z42092.h | 4 +- .../KW/KW47Z42092/KW47Z42092_COMMON.h | 92 +- .../KW/KW47Z42092/KW47Z42092_features.h | 61 +- .../KW/KW47Z42092/system_KW47Z42092.c | 4 +- .../KW/KW47Z42092/system_KW47Z42092.h | 4 +- .../Wireless/KW/KW47Z420B2/KW47Z420B2.h | 4 +- .../KW/KW47Z420B2/KW47Z420B2_COMMON.h | 92 +- .../KW/KW47Z420B2/KW47Z420B2_features.h | 59 +- .../KW/KW47Z420B2/system_KW47Z420B2.c | 4 +- .../KW/KW47Z420B2/system_KW47Z420B2.h | 4 +- .../Wireless/KW/KW47Z420B3/KW47Z420B3.h | 4 +- .../KW/KW47Z420B3/KW47Z420B3_COMMON.h | 92 +- .../KW/KW47Z420B3/KW47Z420B3_features.h | 63 +- .../KW47Z420B3/drivers/CMakeLists_clock.txt | 2 +- .../KW47Z420B3/drivers/CMakeLists_romapi.txt | 4 +- .../KW/KW47Z420B3/drivers/fsl_clock.h | 13 + .../KW47Z420B3/drivers/romapi/fsl_flash_api.h | 17 +- .../KW/KW47Z420B3/drivers/romapi/fsl_romapi.c | 24 +- .../KW/KW47Z420B3/system_KW47Z420B3.c | 4 +- .../KW/KW47Z420B3/system_KW47Z420B3.h | 4 +- .../devices/Wireless/KW/periph6/PERI_ADC.h | 10 +- .../devices/Wireless/KW/periph6/PERI_ATX.h | 2 +- .../devices/Wireless/KW/periph6/PERI_AXBS.h | 1310 ++++++++--------- .../Wireless/KW/periph6/PERI_BLE2_REG.h | 2 +- .../devices/Wireless/KW/periph6/PERI_BRIC.h | 2 +- .../devices/Wireless/KW/periph6/PERI_BTRTU1.h | 2 +- .../Wireless/KW/periph6/PERI_BTU2_REG.h | 2 +- .../devices/Wireless/KW/periph6/PERI_CAN.h | 4 +- .../devices/Wireless/KW/periph6/PERI_CCM32K.h | 70 +- .../devices/Wireless/KW/periph6/PERI_CIU2.h | 2 +- .../devices/Wireless/KW/periph6/PERI_CMC.h | 2 +- .../devices/Wireless/KW/periph6/PERI_CRC.h | 2 +- .../devices/Wireless/KW/periph6/PERI_DBGMB.h | 2 +- .../devices/Wireless/KW/periph6/PERI_DMA.h | 17 +- .../devices/Wireless/KW/periph6/PERI_DSB.h | 10 +- .../devices/Wireless/KW/periph6/PERI_ELEMU.h | 2 +- .../devices/Wireless/KW/periph6/PERI_EWM.h | 2 +- .../devices/Wireless/KW/periph6/PERI_FLEXIO.h | 2 +- .../devices/Wireless/KW/periph6/PERI_FMU.h | 2 +- .../Wireless/KW/periph6/PERI_FRO192M.h | 2 +- .../Wireless/KW/periph6/PERI_GEN4PHY.h | 2 +- .../devices/Wireless/KW/periph6/PERI_GENFSK.h | 2 +- .../devices/Wireless/KW/periph6/PERI_GPIO.h | 2 +- .../devices/Wireless/KW/periph6/PERI_I3C.h | 4 +- .../devices/Wireless/KW/periph6/PERI_LPCMP.h | 2 +- .../devices/Wireless/KW/periph6/PERI_LPI2C.h | 10 +- .../devices/Wireless/KW/periph6/PERI_LPIT.h | 2 +- .../devices/Wireless/KW/periph6/PERI_LPSPI.h | 2 +- .../devices/Wireless/KW/periph6/PERI_LPTMR.h | 2 +- .../devices/Wireless/KW/periph6/PERI_LPUART.h | 2 +- .../devices/Wireless/KW/periph6/PERI_LTC.h | 2 +- .../devices/Wireless/KW/periph6/PERI_MCM.h | 4 +- .../devices/Wireless/KW/periph6/PERI_MRCC.h | 2 +- .../devices/Wireless/KW/periph6/PERI_MSCM.h | 43 +- .../Wireless/KW/periph6/PERI_MSF1_B_TEST.h | 2 +- .../devices/Wireless/KW/periph6/PERI_MU.h | 2 +- .../devices/Wireless/KW/periph6/PERI_NPX.h | 2 +- .../devices/Wireless/KW/periph6/PERI_PORT.h | 2 +- .../Wireless/KW/periph6/PERI_RADIO_CTRL.h | 2 +- .../devices/Wireless/KW/periph6/PERI_RBME.h | 2 +- .../Wireless/KW/periph6/PERI_REGFILE.h | 2 +- .../devices/Wireless/KW/periph6/PERI_RFMC.h | 48 +- .../Wireless/KW/periph6/PERI_RF_CMC1.h | 2 +- .../Wireless/KW/periph6/PERI_RF_FMCCFG.h | 2 +- .../devices/Wireless/KW/periph6/PERI_RTC.h | 11 +- .../Wireless/KW/periph6/PERI_RX_PACKET_RAM.h | 2 +- .../devices/Wireless/KW/periph6/PERI_SCG.h | 2 +- .../devices/Wireless/KW/periph6/PERI_SEMA42.h | 2 +- .../devices/Wireless/KW/periph6/PERI_SFA.h | 2 +- .../devices/Wireless/KW/periph6/PERI_SMSCM.h | 10 +- .../devices/Wireless/KW/periph6/PERI_SPC.h | 37 +- .../devices/Wireless/KW/periph6/PERI_SYSPM.h | 2 +- .../devices/Wireless/KW/periph6/PERI_TPM.h | 2 +- .../devices/Wireless/KW/periph6/PERI_TRDC.h | 116 +- .../devices/Wireless/KW/periph6/PERI_TRGMUX.h | 2 +- .../devices/Wireless/KW/periph6/PERI_TSTMR.h | 2 +- .../Wireless/KW/periph6/PERI_TX_PACKET_RAM.h | 2 +- .../devices/Wireless/KW/periph6/PERI_UART.h | 2 +- .../Wireless/KW/periph6/PERI_UART_PFU.h | 2 +- .../devices/Wireless/KW/periph6/PERI_VBAT.h | 2 +- .../devices/Wireless/KW/periph6/PERI_VREF.h | 4 +- .../devices/Wireless/KW/periph6/PERI_WDOG.h | 2 +- .../devices/Wireless/KW/periph6/PERI_WOR.h | 2 +- .../devices/Wireless/KW/periph6/PERI_WUU.h | 2 +- .../Wireless/KW/periph6/PERI_XCVR_ANALOG.h | 6 +- .../Wireless/KW/periph6/PERI_XCVR_MISC.h | 2 +- .../Wireless/KW/periph6/PERI_XCVR_PLL_DIG.h | 7 +- .../Wireless/KW/periph6/PERI_XCVR_RX_DIG.h | 136 +- .../Wireless/KW/periph6/PERI_XCVR_TSM.h | 2 +- .../Wireless/KW/periph6/PERI_XCVR_TX_DIG.h | 2 +- .../devices/Wireless/RW/RW610/RW610_COMMON.h | 60 +- .../Wireless/RW/RW610/RW610_features.h | 73 +- .../Wireless/RW/RW610/drivers/fsl_power.c | 4 +- .../devices/Wireless/RW/RW612/RW612_COMMON.h | 60 +- .../Wireless/RW/RW612/RW612_features.h | 73 +- .../Wireless/RW/RW612/drivers/fsl_power.c | 4 +- .../devices/Wireless/RW/periph/PERI_FLEXSPI.h | 37 +- 205 files changed, 5019 insertions(+), 1667 deletions(-) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z52/KW45B41Z52_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z52/KW45B41Z52_COMMON.h index 36353b0bc..f7591e075 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z52/KW45B41Z52_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z52/KW45B41Z52_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: Rev. 6, 05/22/2022 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW45B41Z52 @@ -2186,6 +2186,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z52/KW45B41Z52_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z52/KW45B41Z52_features.h index 6748532e5..a11a2fc4d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z52/KW45B41Z52_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z52/KW45B41Z52_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-05-12 -** Build: b250327 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -108,8 +108,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -126,10 +124,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -142,6 +136,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -164,6 +164,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) /* @brief Has internal temperature sensor. */ #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) /* @brief Temperature sensor parameter A (slope). */ @@ -197,6 +201,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -236,8 +245,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -266,6 +273,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -315,8 +324,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -327,10 +358,10 @@ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has dedicated interrupt for master and slave. */ -#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -343,15 +374,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -403,8 +434,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -437,6 +466,8 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ @@ -445,6 +476,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -538,14 +573,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -568,6 +615,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z53/KW45B41Z53_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z53/KW45B41Z53_COMMON.h index 7d8012fe5..1b0d63709 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z53/KW45B41Z53_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z53/KW45B41Z53_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: Rev. 6, 05/22/2022 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW45B41Z53 @@ -2222,6 +2222,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z53/KW45B41Z53_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z53/KW45B41Z53_features.h index 21cb79d5a..76af8d15e 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z53/KW45B41Z53_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z53/KW45B41Z53_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-05-12 -** Build: b250327 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -110,8 +110,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -128,10 +126,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -144,6 +138,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -166,6 +166,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) /* @brief Has internal temperature sensor. */ #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) /* @brief Temperature sensor parameter A (slope). */ @@ -219,12 +223,38 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -248,6 +278,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -287,8 +322,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -317,6 +350,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -366,8 +401,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -378,10 +435,10 @@ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has dedicated interrupt for master and slave. */ -#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -394,15 +451,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -454,8 +511,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -488,6 +543,8 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ @@ -496,6 +553,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -589,14 +650,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -619,6 +692,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z82/KW45B41Z82_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z82/KW45B41Z82_COMMON.h index 285424bc5..ac60f84bb 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z82/KW45B41Z82_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z82/KW45B41Z82_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: Rev. 6, 05/22/2022 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW45B41Z82 @@ -2186,6 +2186,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z82/KW45B41Z82_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z82/KW45B41Z82_features.h index 4acbe4131..c250be2af 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z82/KW45B41Z82_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z82/KW45B41Z82_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-05-12 -** Build: b250327 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -108,8 +108,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -126,10 +124,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -142,6 +136,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -164,6 +164,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) /* @brief Has internal temperature sensor. */ #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) /* @brief Temperature sensor parameter A (slope). */ @@ -197,6 +201,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -236,8 +245,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -266,6 +273,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -315,8 +324,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -327,10 +358,10 @@ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has dedicated interrupt for master and slave. */ -#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -343,15 +374,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -403,8 +434,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -437,6 +466,8 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ @@ -445,6 +476,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -538,14 +573,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -568,6 +615,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/KW45B41Z83_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/KW45B41Z83_COMMON.h index 39b0b70ee..e975edcbc 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/KW45B41Z83_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/KW45B41Z83_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: Rev. 6, 05/22/2022 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW45B41Z83 @@ -2222,6 +2222,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/KW45B41Z83_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/KW45B41Z83_features.h index db4a9e412..ccc16035d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/KW45B41Z83_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/KW45B41Z83_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-05-12 -** Build: b250327 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -110,8 +110,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -128,10 +126,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -144,6 +138,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -166,6 +166,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) /* @brief Has internal temperature sensor. */ #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) /* @brief Temperature sensor parameter A (slope). */ @@ -219,12 +223,38 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -248,6 +278,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -287,8 +322,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -317,6 +350,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -366,8 +401,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -378,10 +435,10 @@ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has dedicated interrupt for master and slave. */ -#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -394,15 +451,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -454,8 +511,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -488,6 +543,8 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ @@ -496,6 +553,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -589,14 +650,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -619,6 +692,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/CMakeLists_clock.txt b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/CMakeLists_clock.txt index a75567792..f4896e3f1 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/CMakeLists_clock.txt +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/CMakeLists_clock.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.2.2) + mcux_component_version(2.2.4) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) mcux_add_include( INCLUDES . ) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/CMakeLists_romapi.txt b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/CMakeLists_romapi.txt index 59474a041..6d754d155 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/CMakeLists_romapi.txt +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/CMakeLists_romapi.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.romapi_soc) - mcux_component_version(1.2.1) + mcux_component_version(1.2.2) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/fsl_clock.c index eb54f9adc..37291fa2b 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/fsl_clock.c @@ -738,7 +738,7 @@ status_t CLOCK_InitRfFro192M(const fro192m_rf_clk_config_t *config) */ uint32_t CLOCK_GetRfFro192MFreq(void) { - static const uint32_t fro192mFreq[] = {16000000U, 24000000U, 32000000U, 48000000U, 64000000U}; + static const uint32_t fro192mFreq[] = {16000000U, 24000000U, 32000000U, 48000000U, 64000000U, 0U, 0U, 0U}; /* * $Branch Coverage Justification$ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/fsl_clock.h index e18fc7877..fff7a6f93 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/fsl_clock.h @@ -39,8 +39,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.2.2. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*! @brief CLOCK driver version 2.2.4. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) /*@}*/ /* Definition for delay API in clock driver, users can redefine it to the real application. */ @@ -350,6 +350,13 @@ typedef enum _scg_sys_clk /*! * @brief SCG system clock source. + * + * ERR052742: FRO6M clock(kSCG_SysClkSrcSirc) is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. */ typedef enum _scg_sys_clk_src { @@ -682,6 +689,12 @@ static inline void CLOCK_DisableTPM2(void) * Set the clock source for specific IP, not all modules need to set the * clock source, should only use this function for the modules need source * setting. + * ERR052742: FRO6M clock is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. * * @param name Which peripheral to check, see \ref clock_ip_name_t. * @param src Clock source to set. diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/romapi/fsl_flash_api.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/romapi/fsl_flash_api.h index f8c0bdce9..d0e8d3e3f 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/romapi/fsl_flash_api.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/romapi/fsl_flash_api.h @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ * @{ */ /*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 1)) /*!< Version 1.2.1. */ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 2)) /*!< Version 1.2.2. */ /*@}*/ /*! @brief Constructs the four character code for the Flash driver API key. */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/romapi/fsl_romapi.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/romapi/fsl_romapi.c index a14307648..b804c6aac 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/romapi/fsl_romapi.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45B41Z83/drivers/romapi/fsl_romapi.c @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -16,7 +16,7 @@ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "driver.romapi" +#define FSL_COMPONENT_ID "driver.romapi_soc" #endif /* @@ -417,12 +417,12 @@ static status_t flash_check_param( status = kStatus_FLASH_Success; } #if defined(RF_FMU) - else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU))) + else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU)) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } #else - else if ((config == NULL) || (base == NULL) || (base != FMU0)) + else if ((config == NULL) || (base == NULL) || (base != FMU0) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41052/KW45Z41052_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41052/KW45Z41052_COMMON.h index 98910b418..f88841c43 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41052/KW45Z41052_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41052/KW45Z41052_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: Rev. 6, 05/22/2022 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW45Z41052 @@ -1611,6 +1611,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41052/KW45Z41052_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41052/KW45Z41052_features.h index 877f50071..b3aebc9f7 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41052/KW45Z41052_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41052/KW45Z41052_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-05-12 -** Build: b250327 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -106,8 +106,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -124,10 +122,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -140,6 +134,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -162,6 +162,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) /* @brief Has internal temperature sensor. */ #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) /* @brief Temperature sensor parameter A (slope). */ @@ -195,6 +199,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -234,8 +243,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -264,6 +271,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -313,8 +322,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -325,10 +356,10 @@ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has dedicated interrupt for master and slave. */ -#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -341,15 +372,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -401,8 +432,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -435,6 +464,8 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ @@ -443,6 +474,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -515,14 +550,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -545,6 +592,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41053/KW45Z41053_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41053/KW45Z41053_COMMON.h index 330ce89d6..c9ebdb413 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41053/KW45Z41053_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41053/KW45Z41053_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: Rev. 6, 05/22/2022 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW45Z41053 @@ -1647,6 +1647,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41053/KW45Z41053_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41053/KW45Z41053_features.h index 41c971e5d..c6d42fd6c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41053/KW45Z41053_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41053/KW45Z41053_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-05-12 -** Build: b250327 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -108,8 +108,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -126,10 +124,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -142,6 +136,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -164,6 +164,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) /* @brief Has internal temperature sensor. */ #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) /* @brief Temperature sensor parameter A (slope). */ @@ -217,12 +221,38 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -246,6 +276,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -285,8 +320,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -315,6 +348,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -364,8 +399,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -376,10 +433,10 @@ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has dedicated interrupt for master and slave. */ -#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -392,15 +449,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -452,8 +509,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -486,6 +541,8 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ @@ -494,6 +551,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -566,14 +627,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -596,6 +669,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41082/KW45Z41082_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41082/KW45Z41082_COMMON.h index aacf59918..e2120cac9 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41082/KW45Z41082_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41082/KW45Z41082_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: Rev. 6, 05/22/2022 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW45Z41082 @@ -1611,6 +1611,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41082/KW45Z41082_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41082/KW45Z41082_features.h index 05b00ff33..df950159e 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41082/KW45Z41082_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41082/KW45Z41082_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-05-12 -** Build: b250327 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -106,8 +106,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -124,10 +122,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -140,6 +134,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -162,6 +162,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) /* @brief Has internal temperature sensor. */ #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) /* @brief Temperature sensor parameter A (slope). */ @@ -195,6 +199,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -234,8 +243,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -264,6 +271,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -313,8 +322,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -325,10 +356,10 @@ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has dedicated interrupt for master and slave. */ -#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -341,15 +372,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -401,8 +432,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -435,6 +464,8 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ @@ -443,6 +474,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -515,14 +550,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -545,6 +592,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/KW45Z41083_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/KW45Z41083_COMMON.h index 6b3a6b2a3..39ca8540b 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/KW45Z41083_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/KW45Z41083_COMMON.h @@ -10,7 +10,7 @@ ** ** Reference manual: Rev. 6, 05/22/2022 ** Version: rev. 2.0, 2024-10-29 -** Build: b250520 +** Build: b250721 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW45Z41083 @@ -1647,6 +1647,43 @@ typedef enum IRQn { /*! @brief define LTC0 from LTC. */ #define LTC0 LTC +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04001FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04002000U) +#define PLATFORM_CTCM1_END_ADDR (0x04003FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x20019FFFU) +#define PLATFORM_STCM5_START_ADDR (0x2001A000U) +#define PLATFORM_STCM5_END_ADDR (0x2001BFFFU) + +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM5_IDX /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/KW45Z41083_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/KW45Z41083_features.h index 354687fb0..abf246f03 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/KW45Z41083_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/KW45Z41083_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2020-05-12 -** Build: b250327 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -108,8 +108,6 @@ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ @@ -126,10 +124,6 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) -/* @brief OFSTRIM availability on the SoC. */ -#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) -/* @brief Has Trigger status register. */ -#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ @@ -142,6 +136,12 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Enable hardware trigger command selection */ +#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has B side channels. */ #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ @@ -164,6 +164,10 @@ #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0) /* @brief Has internal temperature sensor. */ #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) /* @brief Temperature sensor parameter A (slope). */ @@ -217,12 +221,38 @@ #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) /* @brief Has Enhanced Rx FIFO. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_ENHANCED_RX_FIFOn(x) (1) /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) /* @brief The number of enhanced Rx FIFO filter element registers. */ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Does not support self wake feature(bitfield MCR[SLFWAK]) */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (0) +/* @brief Has external time tick source (bitfield CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTERNAL_TIME_TICK (0) +/* @brief Instance has external time tick source (register bit field CTRL2[TIMER_SRC]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTERNAL_TIME_TICKn(x) (0) +/* @brief Has Time Stamp Capture Point(bitfield CTRL2[TSTAMPCAP]). */ +#define FSL_FEATURE_FLEXCAN_HAS_HIGH_RESOLUTION_TIMESTAMP (0) +/* @brief Instance has Pretended Networking option (register bit field MCR[PNET_EN]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_PN_MODEn(x) (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (8000000) +/* @brief Support payload endianness selection (bitfield CTRL2[PES]). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENDIANNESS_SELECTION (0) +/* @brief Enter Freeze mode before entering Disable and Stop mode. */ +#define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) +/* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -246,6 +276,11 @@ /* @brief Does not have SRAMCTL register */ #define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -285,8 +320,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -315,6 +348,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -364,8 +399,30 @@ /* I3C module features */ +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (0) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -376,10 +433,10 @@ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has dedicated interrupt for master and slave. */ -#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) +/* @brief Has dedicated interrupt for master and slave. */ +#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0) /* LPIT module features */ @@ -392,15 +449,15 @@ /* LPSPI module features */ -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +/* @brief Capacity (number of entries) of the transmit/receive FIFO. */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) -/* @brief Has no PCSCFG bit in CFGR1 register */ +/* @brief Has no PCSCFG bit in CFGR1 register. */ #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) -/* @brief Has no WIDTH bits in TCR register */ +/* @brief Has no WIDTH bits in TCR register. */ #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -452,8 +509,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -486,6 +541,8 @@ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0) /* @brief Has register MODEM Control. */ #define FSL_FEATURE_LPUART_HAS_MCR (0) /* @brief Has register Half Duplex Control. */ @@ -494,6 +551,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -566,14 +627,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -596,6 +669,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/CMakeLists_clock.txt b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/CMakeLists_clock.txt index fa088f528..97c0ae505 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/CMakeLists_clock.txt +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/CMakeLists_clock.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.1.1) + mcux_component_version(2.1.2) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) mcux_add_include( INCLUDES . ) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/CMakeLists_romapi.txt b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/CMakeLists_romapi.txt index 59474a041..6d754d155 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/CMakeLists_romapi.txt +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/CMakeLists_romapi.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.romapi_soc) - mcux_component_version(1.2.1) + mcux_component_version(1.2.2) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/fsl_clock.h index 42e9ac716..c4f1bd29c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/fsl_clock.h @@ -39,8 +39,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.1.1. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*! @brief CLOCK driver version 2.1.2. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*@}*/ /* Definition for delay API in clock driver, users can redefine it to the real application. */ @@ -339,6 +339,13 @@ typedef enum _scg_sys_clk /*! * @brief SCG system clock source. + * + * ERR052742: FRO6M clock(kSCG_SysClkSrcSirc) is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. */ typedef enum _scg_sys_clk_src { @@ -623,6 +630,12 @@ static inline void CLOCK_DisableClock(clock_ip_name_t name) * Set the clock source for specific IP, not all modules need to set the * clock source, should only use this function for the modules need source * setting. + * ERR052742: FRO6M clock is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. * * @param name Which peripheral to check, see \ref clock_ip_name_t. * @param src Clock source to set. diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/romapi/fsl_flash_api.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/romapi/fsl_flash_api.h index f8c0bdce9..d0e8d3e3f 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/romapi/fsl_flash_api.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/romapi/fsl_flash_api.h @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ * @{ */ /*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 1)) /*!< Version 1.2.1. */ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 2)) /*!< Version 1.2.2. */ /*@}*/ /*! @brief Constructs the four character code for the Flash driver API key. */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/romapi/fsl_romapi.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/romapi/fsl_romapi.c index a14307648..b804c6aac 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/romapi/fsl_romapi.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW45Z41083/drivers/romapi/fsl_romapi.c @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -16,7 +16,7 @@ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "driver.romapi" +#define FSL_COMPONENT_ID "driver.romapi_soc" #endif /* @@ -417,12 +417,12 @@ static status_t flash_check_param( status = kStatus_FLASH_Success; } #if defined(RF_FMU) - else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU))) + else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU)) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } #else - else if ((config == NULL) || (base == NULL) || (base != FMU0)) + else if ((config == NULL) || (base == NULL) || (base != FMU0) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0.h index edd89f3ae..ebc11d862 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z83_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0_COMMON.h index 05c4632c4..0321b68e6 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z83_cm33_core0 @@ -2327,22 +2327,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2352,6 +2358,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0_features.h index 8592cb53f..1a350e6f8 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -251,6 +251,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -278,6 +282,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -317,8 +326,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -347,6 +354,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -361,7 +370,7 @@ /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1u) /* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x200000u) +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000u) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE_512KB (0x80000u) /* @brief Flash sector size. */ @@ -406,8 +415,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -494,8 +515,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -538,6 +557,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -623,18 +646,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -657,6 +694,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1.h index abea605ba..c79d05cd2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z83_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1_COMMON.h index 27fa5eceb..9451498c9 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z83_cm33_core1 @@ -946,22 +946,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -971,6 +977,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1_features.h index 97c5e3c7b..f04b4beab 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/KW47B42Z83_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -263,6 +263,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -290,6 +294,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -329,8 +338,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -359,6 +366,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -373,7 +382,7 @@ /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1u) /* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x200000u) +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000u) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE_512KB (0x80000u) /* @brief Flash sector size. */ @@ -418,8 +427,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -506,8 +527,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -550,6 +569,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -630,18 +653,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -664,6 +701,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core0.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core0.c index 4d94da81e..9a1d636d5 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core0.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core0.h index 60c278483..15a2c0431 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core1.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core1.c index 0b33b2fa7..f8447b91c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core1.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core1.h index e776e5a60..a0e9439a6 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z83/system_KW47B42Z83_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0.h index fd637efce..e29b93370 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z96_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0_COMMON.h index 1894b109e..52af7450b 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z96_cm33_core0 @@ -2308,22 +2308,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2333,6 +2339,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0_features.h index 6bf7ecad3..afc70627c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -207,6 +207,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -246,8 +251,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -276,6 +279,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -290,7 +295,7 @@ /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1u) /* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x200000u) +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000u) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE_512KB (0x80000u) /* @brief Flash sector size. */ @@ -335,8 +340,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -423,8 +440,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -467,6 +482,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -599,18 +618,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -633,6 +666,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1.h index 1bebeb0e2..8f0cdc6b7 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z96_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1_COMMON.h index 2ea0b826f..252b86d73 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z96_cm33_core1 @@ -942,22 +942,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -967,6 +973,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1_features.h index 85d79dcd0..05838482c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/KW47B42Z96_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -219,6 +219,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -258,8 +263,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -288,6 +291,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -302,7 +307,7 @@ /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1u) /* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x200000u) +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000u) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE_512KB (0x80000u) /* @brief Flash sector size. */ @@ -347,8 +352,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -435,8 +452,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -479,6 +494,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -606,18 +625,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -640,6 +673,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core0.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core0.c index 51ee23848..fa7600816 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core0.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core0.h index f5c2e3933..1fcf85ef6 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core1.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core1.c index 272cdff39..3bca1cf63 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core1.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core1.h index 13563cba2..17719cdd3 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z96/system_KW47B42Z96_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0.h index e22521e03..fc8ac0b3e 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z97_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0_COMMON.h index 6bb3f0aa3..db6385847 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z97_cm33_core0 @@ -2356,22 +2356,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2381,6 +2387,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0_features.h index a19b13dcf..b5cb387a8 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -253,6 +253,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -280,6 +284,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -319,8 +328,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -349,6 +356,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -363,7 +372,7 @@ /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1u) /* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x200000u) +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000u) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE_512KB (0x80000u) /* @brief Flash sector size. */ @@ -408,8 +417,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -496,8 +517,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -540,6 +559,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -672,18 +695,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -706,6 +743,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1.h index 143328b86..7358431b7 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z97_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1_COMMON.h index b3027790d..369520dd4 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42Z97_cm33_core1 @@ -956,22 +956,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -981,6 +987,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1_features.h index 2f319fdf6..eea763549 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/KW47B42Z97_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -265,6 +265,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -292,6 +296,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -331,8 +340,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -361,6 +368,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -375,7 +384,7 @@ /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1u) /* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x200000u) +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000u) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE_512KB (0x80000u) /* @brief Flash sector size. */ @@ -420,8 +429,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -508,8 +529,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -552,6 +571,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -679,18 +702,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -713,6 +750,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core0.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core0.c index 45de4538b..db112924b 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core0.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core0.h index ed47ad4a3..974274d0e 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core1.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core1.c index 48e7ae51f..df71a6da6 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core1.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core1.h index 2c0b373ca..52f028ecf 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42Z97/system_KW47B42Z97_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0.h index c055eace3..f7e1387ef 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB2_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0_COMMON.h index 03a589732..5397167a9 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB2_cm33_core0 @@ -2279,22 +2279,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2304,6 +2310,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0_features.h index d71e38a30..1aa9721a8 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -205,6 +205,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -244,8 +249,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -274,6 +277,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -333,8 +338,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -421,8 +438,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -465,6 +480,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -550,18 +569,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -584,6 +617,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1.h index f248ca596..f223492b0 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB2_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1_COMMON.h index 0497a41a5..bdbea4182 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB2_cm33_core1 @@ -932,22 +932,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -957,6 +963,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1_features.h index 5b63ccfce..c405bf2cf 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/KW47B42ZB2_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -217,6 +217,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -256,8 +261,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -286,6 +289,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -345,8 +350,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -433,8 +450,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -477,6 +492,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -557,18 +576,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -591,6 +624,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core0.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core0.c index 1c6992e86..241bcb4f6 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core0.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core0.h index f77acdb71..c71e597bc 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core1.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core1.c index 15a02d3d7..a5f393ec3 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core1.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core1.h index 02dc284e5..26429761d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB2/system_KW47B42ZB2_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0.h index 7ed1150ba..ff48f9b86 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB3_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0_COMMON.h index f6ab52ceb..ab8c57760 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB3_cm33_core0 @@ -2327,22 +2327,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2352,6 +2358,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0_features.h index 6929dc0b3..0781193e9 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -251,6 +251,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -278,6 +282,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -317,8 +326,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -347,6 +354,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -406,8 +415,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -494,8 +515,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -538,6 +557,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -623,18 +646,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -657,6 +694,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1.h index a4281ab97..227368704 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB3_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1_COMMON.h index 61e891132..1c02a8d37 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB3_cm33_core1 @@ -946,22 +946,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -971,6 +977,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1_features.h index 6025fc230..6588e56bc 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/KW47B42ZB3_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -263,6 +263,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -290,6 +294,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -329,8 +338,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -359,6 +366,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -418,8 +427,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -506,8 +527,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -550,6 +569,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -630,18 +653,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -664,6 +701,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core0.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core0.c index 0c560dd78..0a965ddcb 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core0.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core0.h index a85a8ed1d..ef3313923 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core1.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core1.c index 4ee84395e..71323494c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core1.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core1.h index 7d589e645..562ca8284 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB3/system_KW47B42ZB3_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0.h index e23c3a444..502929683 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB6_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0_COMMON.h index 58ffc2ff6..e787dbe99 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB6_cm33_core0 @@ -2308,22 +2308,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2333,6 +2339,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0_features.h index d27119bc1..46fe258f1 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -207,6 +207,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -246,8 +251,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -276,6 +279,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -335,8 +340,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -423,8 +440,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -467,6 +482,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -599,18 +618,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -633,6 +666,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1.h index 227e8cae9..2423e20c5 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB6_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1_COMMON.h index d5ce91a69..756052c38 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB6_cm33_core1 @@ -942,22 +942,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -967,6 +973,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1_features.h index fdd844dec..313e1542f 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/KW47B42ZB6_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -219,6 +219,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -258,8 +263,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -288,6 +291,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -347,8 +352,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -435,8 +452,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -479,6 +494,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -606,18 +625,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -640,6 +673,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core0.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core0.c index a259792a2..ba93d38af 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core0.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core0.h index ae4a781ef..60fb906d2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core1.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core1.c index 61dec2a62..441766256 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core1.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core1.h index 3bffe50f0..c0d4ec691 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB6/system_KW47B42ZB6_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0.h index 86d011085..322d161f0 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB7_cm33_core0 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0_COMMON.h index 2e94495cc..54c2ef2bb 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB7_cm33_core0 @@ -2356,22 +2356,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -2381,6 +2387,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0_features.h index a7678ed4f..5c59ce89f 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core0_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -253,6 +253,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -280,6 +284,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -319,8 +328,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -349,6 +356,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -408,8 +417,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -496,8 +517,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -540,6 +559,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -672,18 +695,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (1) : \ + (((x) == RF_SFA) ? (0) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -706,6 +743,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1.h index 35db298e3..fd46df0c7 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB7_cm33_core1 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1_COMMON.h index 166fa979f..6a1625c79 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47B42ZB7_cm33_core1 @@ -956,22 +956,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -981,6 +987,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1_features.h index 314581eaa..5dd017fa0 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/KW47B42ZB7_cm33_core1_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250902 ** ** Abstract: ** Chip specific module features. @@ -265,6 +265,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -292,6 +296,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -331,8 +340,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -361,6 +368,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -420,8 +429,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -508,8 +529,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -552,6 +571,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -679,18 +702,32 @@ /* @brief SFA instance support trigger. */ #define FSL_FEATURE_SFA_INSTANCE_HAS_TRIGGERn(x) (1) /* @brief SFA instance support interrupt. */ -#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) (1) +#define FSL_FEATURE_SFA_INSTANCE_HAS_INTERRUPTn(x) \ + (((x) == SFA0) ? (0) : \ + (((x) == RF_SFA) ? (1) : (-1))) /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -713,6 +750,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/CMakeLists_clock.txt b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/CMakeLists_clock.txt index 153a43109..67fac9bef 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/CMakeLists_clock.txt +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/CMakeLists_clock.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.2.3) + mcux_component_version(2.2.5) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) mcux_add_include( INCLUDES . ) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/CMakeLists_romapi.txt b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/CMakeLists_romapi.txt index 59474a041..fd1981e26 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/CMakeLists_romapi.txt +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/CMakeLists_romapi.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.romapi_soc) - mcux_component_version(1.2.1) + mcux_component_version(1.2.3) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/fsl_clock.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/fsl_clock.c index 60c72b765..4853fd196 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/fsl_clock.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/fsl_clock.c @@ -739,7 +739,7 @@ status_t CLOCK_InitRfFro192M(const fro192m_rf_clk_config_t *config) */ uint32_t CLOCK_GetRfFro192MFreq(void) { - static const uint32_t fro192mFreq[] = {16000000U, 24000000U, 32000000U, 48000000U, 64000000U}; + static const uint32_t fro192mFreq[] = {16000000U, 24000000U, 32000000U, 48000000U, 64000000U, 0U, 0U, 0U}; /* * $Branch Coverage Justification$ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/fsl_clock.h index 0f7b6e500..38d4e4832 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/fsl_clock.h @@ -39,8 +39,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.2.3. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) +/*! @brief CLOCK driver version 2.2.5. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) /*@}*/ /* Definition for delay API in clock driver, users can redefine it to the real application. */ @@ -369,6 +369,13 @@ typedef enum _scg_sys_clk /*! * @brief SCG system clock source. + * + * ERR052742: FRO6M clock(kSCG_SysClkSrcSirc) is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. */ typedef enum _scg_sys_clk_src { @@ -701,6 +708,12 @@ static inline void CLOCK_DisableTPM2(void) * Set the clock source for specific IP, not all modules need to set the * clock source, should only use this function for the modules need source * setting. + * ERR052742: FRO6M clock is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. * * @param name Which peripheral to check, see \ref clock_ip_name_t. * @param src Clock source to set. diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/romapi/fsl_flash_api.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/romapi/fsl_flash_api.h index f8c0bdce9..46d234824 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/romapi/fsl_flash_api.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/romapi/fsl_flash_api.h @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ * @{ */ /*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 1)) /*!< Version 1.2.1. */ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 3)) /*!< Version 1.2.3. */ /*@}*/ /*! @brief Constructs the four character code for the Flash driver API key. */ @@ -113,21 +113,11 @@ typedef enum _flash_property_tag kFLASH_PropertyPflash0BlockSize = 0x02U, /*!< Pflash block size property.*/ kFLASH_PropertyPflash0BlockCount = 0x03U, /*!< Pflash block count property.*/ kFLASH_PropertyPflash0BlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflash0FacSupport = 0x05U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflash0AccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflash0AccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ - kFLASH_PropertyPflash1SectorSize = 0x10U, /*!< Pflash sector size property.*/ kFLASH_PropertyPflash1TotalSize = 0x11U, /*!< Pflash total size property.*/ kFLASH_PropertyPflash1BlockSize = 0x12U, /*!< Pflash block size property.*/ kFLASH_PropertyPflash1BlockCount = 0x13U, /*!< Pflash block count property.*/ kFLASH_PropertyPflash1BlockBaseAddr = 0x14U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflash1FacSupport = 0x15U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflash1AccessSegmentSize = 0x16U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflash1AccessSegmentCount = 0x17U, /*!< Pflash access segment count property.*/ - - kFLASH_PropertyFlexRamBlockBaseAddr = 0x20U, /*!< FlexRam block base address property.*/ - kFLASH_PropertyFlexRamTotalSize = 0x21U, /*!< FlexRam total size property.*/ } flash_property_tag_t; /*! @@ -190,7 +180,8 @@ typedef struct FlashDriverInterface status_t (*flash_program_page)( flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t *src, uint32_t lengthInBytes); status_t (*flash_verify_erase_all)(FMU_Type *base); - status_t *reserved; + status_t (*flash_verify_erase_block)( + flash_config_t *config, FMU_Type *base, uint32_t blockaddr); status_t (*flash_verify_erase_phrase)(flash_config_t *config, FMU_Type *base, uint32_t start, diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/romapi/fsl_romapi.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/romapi/fsl_romapi.c index eafc68eb3..73549439c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/romapi/fsl_romapi.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/drivers/romapi/fsl_romapi.c @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -16,7 +16,7 @@ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "driver.romapi" +#define FSL_COMPONENT_ID "driver.romapi_soc" #endif /* @@ -330,6 +330,21 @@ status_t FLASH_VerifyEraseSector(flash_config_t *config, FMU_Type *base, uint32_ return status; } +/*! + * @brief Checking if a flash block is in the erased state. + */ +status_t FLASH_VerifyEraseBlock(flash_config_t *config, FMU_Type *base, uint32_t blockaddr) +{ + assert(BOOTLOADER_API_TREE_POINTER); + assert(config); + assert(base); + + status_t status; + status = BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_erase_block(config, base, blockaddr); + + return status; +} + /*! * @brief Read into MISR * @@ -362,6 +377,7 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro status_t status; status = BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_property(config, whichProperty, value); + status = kStatus_FLASH_Success; return status; } @@ -417,12 +433,12 @@ static status_t flash_check_param( status = kStatus_FLASH_Success; } #if defined(RF_FMU) - else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU))) + else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU)) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } #else - else if ((config == NULL) || (base == NULL) || (base != FMU0)) + else if ((config == NULL) || (base == NULL) || (base != FMU0) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core0.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core0.c index 4bdc23188..b6027ec23 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core0.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core0.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core0.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core0.h index 73a9ccf05..17358a94a 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core0.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core0.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core1.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core1.c index 55888f00c..2f1fd854d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core1.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core1.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core1.h index 68fe0ed04..688c1a666 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47B42ZB7/system_KW47B42ZB7_cm33_core1.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082.h index dbe5742bc..ef0e81adb 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47Z42082 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082_COMMON.h index 31f4cc69a..5b2442447 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47Z42082 @@ -1704,22 +1704,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -1729,6 +1735,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082_features.h index 3484359b2..2d6740aba 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/KW47Z42082_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -203,6 +203,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -242,8 +247,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -272,6 +275,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -286,7 +291,7 @@ /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1u) /* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x200000u) +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000u) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE_512KB (0x80000u) /* @brief Flash sector size. */ @@ -331,8 +336,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -419,8 +436,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -463,6 +478,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -537,14 +556,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -567,6 +598,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/system_KW47Z42082.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/system_KW47Z42082.c index 6b298bcc3..7266b15d2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/system_KW47Z42082.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/system_KW47Z42082.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/system_KW47Z42082.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/system_KW47Z42082.h index 89b99660c..0c8e7e2b7 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/system_KW47Z42082.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42082/system_KW47Z42082.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092.h index 6768946b0..d8ead7055 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47Z42092 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092_COMMON.h index 178e10cdd..cadfceeaa 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47Z42092 @@ -1704,22 +1704,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -1729,6 +1735,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092_features.h index 7b3d53107..aaecd3863 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/KW47Z42092_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -203,6 +203,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -242,8 +247,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -272,6 +275,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -286,7 +291,7 @@ /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1u) /* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x200000u) +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000u) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE_512KB (0x80000u) /* @brief Flash sector size. */ @@ -331,8 +336,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -419,8 +436,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -463,6 +478,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -537,14 +556,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -567,6 +598,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/system_KW47Z42092.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/system_KW47Z42092.c index 98fa8c8d1..2951a2990 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/system_KW47Z42092.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/system_KW47Z42092.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/system_KW47Z42092.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/system_KW47Z42092.h index 9097a2479..35dba48e2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/system_KW47Z42092.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z42092/system_KW47Z42092.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2.h index 52f9b06f4..8e036b594 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47Z420B2 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2_COMMON.h index 44cbe14df..519a93d6d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47Z420B2 @@ -1704,22 +1704,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -1729,6 +1735,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2_features.h index f9c59e295..1e4be6ef1 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/KW47Z420B2_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -203,6 +203,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -242,8 +247,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -272,6 +275,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -331,8 +336,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -419,8 +436,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -463,6 +478,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -537,14 +556,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -567,6 +598,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/system_KW47Z420B2.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/system_KW47Z420B2.c index eff7f73f7..ed6c2a8b2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/system_KW47Z420B2.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/system_KW47Z420B2.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/system_KW47Z420B2.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/system_KW47Z420B2.h index 5f7dbe6ec..4194bfea2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/system_KW47Z420B2.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B2/system_KW47Z420B2.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3.h index babcb872e..3eb79e487 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47Z420B3 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3_COMMON.h index b329e0bf3..b94f1ce88 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3_COMMON.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for KW47Z420B3 @@ -1752,22 +1752,28 @@ typedef enum IRQn { * Macros below define the chip revision. */ #define DEVICE_REVISION_A0 (0x10U) -#define DEVICE_REVISION_A1 (0x11U) -#define DEVICE_REVISION_A2 (0x12U) +#define DEVICE_REVISION_A1 (0x10U) +#define DEVICE_REVISION_A2 (0x10U) +#define DEVICE_REVISION_A2_1 (0x13U) #define DEVICE_REVISION_OTHERS (0xFFU) -#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) -#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2() (DEVICE_REVISION_A2 == Chip_GetVersion()) +#define IS_CHIP_REVISION_A2_1() (DEVICE_REVISION_A2_1 == Chip_GetVersion()) /*! * @brief Get the chip value. * -* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0x12: A2 version chip, 0xFF: invalid version. +* @return chip version, 0x10: A0, A1 or A2 version chip, 0x13: A2.1 version chip, 0xFF: invalid version. */ static inline uint8_t Chip_GetVersion(void) { - return DEVICE_REVISION_A0; + uint8_t deviceRevision; + + deviceRevision = (uint8_t)(*((uint8_t *)0x14817FCC)) & 0xFFu; + + return deviceRevision; } /* @@ -1777,6 +1783,74 @@ static inline uint8_t Chip_GetVersion(void) #define CE_STCM6_BASE (0x20028000u) #define CE_STCM7_BASE (0x20030000u) +#define PLATFORM_CTCM0_IDX 0U +#define PLATFORM_CTCM1_IDX 1U +#define PLATFORM_STCM0_IDX 2U +#define PLATFORM_STCM1_IDX 3U +#define PLATFORM_STCM2_IDX 4U +#define PLATFORM_STCM3_IDX 5U +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_IDX 6U +#define PLATFORM_STCM5_IDX 7U +#define PLATFORM_STCM6_IDX 8U +#define PLATFORM_STCM7_IDX 9U +#endif +#define PLATFORM_STCM8_IDX 10U + +#define PLATFORM_CTCM0_START_ADDR (0x04000000U) +#define PLATFORM_CTCM0_END_ADDR (0x04003FFFU) +#define PLATFORM_CTCM1_START_ADDR (0x04004000U) +#define PLATFORM_CTCM1_END_ADDR (0x04007FFFU) +#define PLATFORM_STCM0_START_ADDR (0x20000000U) +#define PLATFORM_STCM0_END_ADDR (0x20003FFFU) +#define PLATFORM_STCM1_START_ADDR (0x20004000U) +#define PLATFORM_STCM1_END_ADDR (0x20007FFFU) +#define PLATFORM_STCM2_START_ADDR (0x20008000U) +#define PLATFORM_STCM2_END_ADDR (0x2000FFFFU) +#define PLATFORM_STCM3_START_ADDR (0x20010000U) +#define PLATFORM_STCM3_END_ADDR (0x20017FFFU) +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +/* 136KB phantom does not support STCM4, STCM5, STCM6 and STCM7 */ +#define PLATFORM_STCM4_START_ADDR (0x20018000U) +#define PLATFORM_STCM4_END_ADDR (0x2001FFFFU) +#define PLATFORM_STCM5_START_ADDR (0x20020000U) +#define PLATFORM_STCM5_END_ADDR (0x20027FFFU) +#define PLATFORM_STCM6_START_ADDR (0x20028000U) +#define PLATFORM_STCM6_END_ADDR (0x2002FFFFU) +#define PLATFORM_STCM7_START_ADDR (0x20030000U) +#define PLATFORM_STCM7_END_ADDR (0x20037FFFU) +#endif +#define PLATFORM_STCM8_START_ADDR (0x20038000U) +#define PLATFORM_STCM8_END_ADDR (0x20039FFFU) + +#if !(defined(KW47B42Z83_cm33_core0_H_) || defined(KW47Z42082_H_)) +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, PLATFORM_STCM4_START_ADDR, PLATFORM_STCM5_START_ADDR, \ + PLATFORM_STCM6_START_ADDR, PLATFORM_STCM7_START_ADDR, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, PLATFORM_STCM4_END_ADDR, PLATFORM_STCM5_END_ADDR, \ + PLATFORM_STCM6_END_ADDR, PLATFORM_STCM7_END_ADDR, PLATFORM_STCM8_END_ADDR + +#else +#define PLATFORM_BANK_START_ADDR \ + PLATFORM_CTCM0_START_ADDR, PLATFORM_CTCM1_START_ADDR, PLATFORM_STCM0_START_ADDR, PLATFORM_STCM1_START_ADDR, \ + PLATFORM_STCM2_START_ADDR, PLATFORM_STCM3_START_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_START_ADDR + +#define PLATFORM_BANK_END_ADDR \ + PLATFORM_CTCM0_END_ADDR, PLATFORM_CTCM1_END_ADDR, PLATFORM_STCM0_END_ADDR, PLATFORM_STCM1_END_ADDR, \ + PLATFORM_STCM2_END_ADDR, PLATFORM_STCM3_END_ADDR, 0xFFFFFFFF, 0xFFFFFFFF, \ + 0xFFFFFFFF, 0xFFFFFFFF, PLATFORM_STCM8_END_ADDR +#endif + +#define PLATFORM_BANK_IS_ECC TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE + +#define PLATFORM_VBAT_LDORAM_IDX PLATFORM_STCM8_IDX + #elif defined(KW47B42Z83_cm33_core1_H_) || defined(KW47B42Z96_cm33_core1_H_) || defined(KW47B42Z97_cm33_core1_H_) || defined(KW47B42ZB2_cm33_core1_H_) || defined(KW47B42ZB3_cm33_core1_H_) || defined(KW47B42ZB6_cm33_core1_H_) || defined(KW47B42ZB7_cm33_core1_H_) #define RADIO_IS_GEN_4P7 (1) #define NXP_RADIO_GEN (470) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3_features.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3_features.h index c60b0bee9..e77210aba 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/KW47Z420B3_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2024-10-13 -** Build: b250521 +** Build: b250819 ** ** Abstract: ** Chip specific module features. @@ -249,6 +249,10 @@ #define FSL_FEATURE_FLEXCAN_ENTER_FREEZE_MODE (0) /* @brief Is affected by errata with ID 8341 (FlexCAN: Entering Freeze Mode or Low Power Mode from Normal Mode can cause the FlexCAN module to stop operating). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341 (0) +/* @brief Is affected by errata with ID 050443 (FlexCAN: : Receive Message Buffers may have its CODE Field corrupted if the Receive FIFO function is used in Classical CAN mode). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_050443 (0) +/* @brief Support memory error interrupt (bitfield MECR[CEI_MSK]). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_INTERRUPT (0) /* CCM32K module features */ @@ -276,6 +280,11 @@ /* @brief Has system clock generation reset (register bit SCG[SRIE]) */ #define FSL_FEATURE_CMC_HAS_SRIE_SCG_BIT (0) +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ @@ -315,8 +324,6 @@ /* FLEXIO module features */ -/* @brief Has DOZEN bit(CTRL[DOZEN]) */ -#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* @brief FLEXIO support reset from RSTCTL */ #define FSL_FEATURE_FLEXIO_HAS_RESET (0) /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ @@ -345,6 +352,8 @@ #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* @brief Has pin input output related registers */ #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has DOZEN bit(CTRL[DOZEN]) */ +#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1) /* MSF1 module features */ @@ -404,8 +413,20 @@ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) /* @brief Register SCONFIG has HDROK bitfield. */ #define FSL_FEATURE_I3C_HAS_HDROK (1) -/* @brief SOC doesn't support slave IBI/MR/HJ. */ +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (0) +/* @brief SOC does not support slave IBI/MR/HJ */ #define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_052086. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052086 (0) +/* @brief Has ERRATA_052123. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_052123 (0) +/* @brief Has IBI bytes. */ +#define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) /* LPCMP module features */ @@ -492,8 +513,6 @@ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ @@ -536,6 +555,10 @@ #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) /* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */ #define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief UART support receive rts configuration (has bit MODIR[RTSWATER]). */ +#define FSL_FEATURE_LPUART_HAS_MODIR_RTSWATER (1) /* LTC module features */ @@ -610,14 +633,26 @@ /* RTC module features */ -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (1) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ @@ -640,6 +675,14 @@ #define FSL_FEATURE_RTC_HAS_TTSR (1) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (1) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) +/* @brief Has no supervisor access bit (CR[SUP]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_SUP (1) +/* @brief Is affected by errata with ID 010716 (RTC: Timer Alarm Flag can assert erroneously). */ +#define FSL_FEATURE_RTC_HAS_ERRATA_010716 (0) +/* @brief Has clock output bit (CR[CLKO]). */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT (1) /* SEMA42 module features */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/CMakeLists_clock.txt b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/CMakeLists_clock.txt index fa088f528..97c0ae505 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/CMakeLists_clock.txt +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/CMakeLists_clock.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.clock) - mcux_component_version(2.1.1) + mcux_component_version(2.1.2) mcux_add_source( SOURCES fsl_clock.c fsl_clock.h ) mcux_add_include( INCLUDES . ) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/CMakeLists_romapi.txt b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/CMakeLists_romapi.txt index 59474a041..fd1981e26 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/CMakeLists_romapi.txt +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/CMakeLists_romapi.txt @@ -1,9 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_driver.romapi_soc) - mcux_component_version(1.2.1) + mcux_component_version(1.2.3) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/fsl_clock.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/fsl_clock.h index e4049f6e8..228b1fa56 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/fsl_clock.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/fsl_clock.h @@ -354,6 +354,13 @@ typedef enum _scg_sys_clk /*! * @brief SCG system clock source. + * + * ERR052742: FRO6M clock(kSCG_SysClkSrcSirc) is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. */ typedef enum _scg_sys_clk_src { @@ -638,6 +645,12 @@ static inline void CLOCK_DisableClock(clock_ip_name_t name) * Set the clock source for specific IP, not all modules need to set the * clock source, should only use this function for the modules need source * setting. + * ERR052742: FRO6M clock is not stable. + * The FRO6M clock is not stable on some parts. FRO6M outputs lower frequency + * signal instead of 6MHz when device is reset or wakes up from low power. + * It can impact peripherals using it as a clock source. Please use clock source + * other than the FRO6M. For example, use FRO192M instead of FRO6M as clock + * source for peripherals. * * @param name Which peripheral to check, see \ref clock_ip_name_t. * @param src Clock source to set. diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/romapi/fsl_flash_api.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/romapi/fsl_flash_api.h index f8c0bdce9..46d234824 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/romapi/fsl_flash_api.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/romapi/fsl_flash_api.h @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ * @{ */ /*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 1)) /*!< Version 1.2.1. */ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 2, 3)) /*!< Version 1.2.3. */ /*@}*/ /*! @brief Constructs the four character code for the Flash driver API key. */ @@ -113,21 +113,11 @@ typedef enum _flash_property_tag kFLASH_PropertyPflash0BlockSize = 0x02U, /*!< Pflash block size property.*/ kFLASH_PropertyPflash0BlockCount = 0x03U, /*!< Pflash block count property.*/ kFLASH_PropertyPflash0BlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflash0FacSupport = 0x05U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflash0AccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflash0AccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ - kFLASH_PropertyPflash1SectorSize = 0x10U, /*!< Pflash sector size property.*/ kFLASH_PropertyPflash1TotalSize = 0x11U, /*!< Pflash total size property.*/ kFLASH_PropertyPflash1BlockSize = 0x12U, /*!< Pflash block size property.*/ kFLASH_PropertyPflash1BlockCount = 0x13U, /*!< Pflash block count property.*/ kFLASH_PropertyPflash1BlockBaseAddr = 0x14U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflash1FacSupport = 0x15U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflash1AccessSegmentSize = 0x16U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflash1AccessSegmentCount = 0x17U, /*!< Pflash access segment count property.*/ - - kFLASH_PropertyFlexRamBlockBaseAddr = 0x20U, /*!< FlexRam block base address property.*/ - kFLASH_PropertyFlexRamTotalSize = 0x21U, /*!< FlexRam total size property.*/ } flash_property_tag_t; /*! @@ -190,7 +180,8 @@ typedef struct FlashDriverInterface status_t (*flash_program_page)( flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t *src, uint32_t lengthInBytes); status_t (*flash_verify_erase_all)(FMU_Type *base); - status_t *reserved; + status_t (*flash_verify_erase_block)( + flash_config_t *config, FMU_Type *base, uint32_t blockaddr); status_t (*flash_verify_erase_phrase)(flash_config_t *config, FMU_Type *base, uint32_t start, diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/romapi/fsl_romapi.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/romapi/fsl_romapi.c index eafc68eb3..73549439c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/romapi/fsl_romapi.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/drivers/romapi/fsl_romapi.c @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -16,7 +16,7 @@ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "driver.romapi" +#define FSL_COMPONENT_ID "driver.romapi_soc" #endif /* @@ -330,6 +330,21 @@ status_t FLASH_VerifyEraseSector(flash_config_t *config, FMU_Type *base, uint32_ return status; } +/*! + * @brief Checking if a flash block is in the erased state. + */ +status_t FLASH_VerifyEraseBlock(flash_config_t *config, FMU_Type *base, uint32_t blockaddr) +{ + assert(BOOTLOADER_API_TREE_POINTER); + assert(config); + assert(base); + + status_t status; + status = BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_erase_block(config, base, blockaddr); + + return status; +} + /*! * @brief Read into MISR * @@ -362,6 +377,7 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro status_t status; status = BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_property(config, whichProperty, value); + status = kStatus_FLASH_Success; return status; } @@ -417,12 +433,12 @@ static status_t flash_check_param( status = kStatus_FLASH_Success; } #if defined(RF_FMU) - else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU))) + else if ((config == NULL) || (base == NULL) || ((base != FMU0) && (base != RF_FMU)) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } #else - else if ((config == NULL) || (base == NULL) || (base != FMU0)) + else if ((config == NULL) || (base == NULL) || (base != FMU0) || (0u == alignmentBaseline)) { status = kStatus_FLASH_InvalidArgument; } diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/system_KW47Z420B3.c b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/system_KW47Z420B3.c index 540f819ec..7846299db 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/system_KW47Z420B3.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/system_KW47Z420B3.c @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/system_KW47Z420B3.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/system_KW47Z420B3.h index 74aad4a0c..de4095323 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/system_KW47Z420B3.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/KW47Z420B3/system_KW47Z420B3.h @@ -6,9 +6,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: Rev. 1, 2024-10-13 +** Reference manual: Rev. 2, 2025-05-01 ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** Provides a system configuration function and a global variable that diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ADC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ADC.h index 95c29a75d..d5512164d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ADC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ADC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for ADC @@ -755,6 +755,14 @@ typedef struct { */ #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + * 0b0..Disable + * 0b1..Enable + */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + #define ADC_TCTRL_TDLY_MASK (0xF0000U) #define ADC_TCTRL_TDLY_SHIFT (16U) /*! TDLY - Trigger Delay Select */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ATX.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ATX.h index e8581e7c1..b3a849c04 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ATX.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ATX.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for ATX diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_AXBS.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_AXBS.h index 8edf99eaa..d2d92a1fa 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_AXBS.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_AXBS.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for AXBS @@ -134,51 +134,51 @@ /** AXBS - Register Layout Typedef */ typedef struct { - __IO uint32_t PRS0; /**< Priority Slave Registers, offset: 0x0 */ + __IO uint32_t PRS0; /**< Priority Target Registers, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t CRS0; /**< Control Register, offset: 0x10 */ uint8_t RESERVED_1[236]; - __IO uint32_t PRS1; /**< Priority Slave Registers, offset: 0x100 */ + __IO uint32_t PRS1; /**< Priority Target Registers, offset: 0x100 */ uint8_t RESERVED_2[12]; __IO uint32_t CRS1; /**< Control Register, offset: 0x110 */ uint8_t RESERVED_3[236]; - __IO uint32_t PRS2; /**< Priority Slave Registers, offset: 0x200 */ + __IO uint32_t PRS2; /**< Priority Target Registers, offset: 0x200 */ uint8_t RESERVED_4[12]; __IO uint32_t CRS2; /**< Control Register, offset: 0x210 */ uint8_t RESERVED_5[236]; - __IO uint32_t PRS3; /**< Priority Slave Registers, offset: 0x300 */ + __IO uint32_t PRS3; /**< Priority Target Registers, offset: 0x300 */ uint8_t RESERVED_6[12]; __IO uint32_t CRS3; /**< Control Register, offset: 0x310 */ uint8_t RESERVED_7[236]; - __IO uint32_t PRS4; /**< Priority Slave Registers, offset: 0x400 */ + __IO uint32_t PRS4; /**< Priority Target Registers, offset: 0x400 */ uint8_t RESERVED_8[12]; __IO uint32_t CRS4; /**< Control Register, offset: 0x410 */ uint8_t RESERVED_9[236]; - __IO uint32_t PRS5; /**< Priority Slave Registers, offset: 0x500 */ + __IO uint32_t PRS5; /**< Priority Target Registers, offset: 0x500 */ uint8_t RESERVED_10[12]; __IO uint32_t CRS5; /**< Control Register, offset: 0x510 */ uint8_t RESERVED_11[236]; - __IO uint32_t PRS6; /**< Priority Slave Registers, offset: 0x600 */ + __IO uint32_t PRS6; /**< Priority Target Registers, offset: 0x600 */ uint8_t RESERVED_12[12]; __IO uint32_t CRS6; /**< Control Register, offset: 0x610 */ uint8_t RESERVED_13[236]; - __IO uint32_t PRS7; /**< Priority Slave Registers, offset: 0x700 */ + __IO uint32_t PRS7; /**< Priority Target Registers, offset: 0x700 */ uint8_t RESERVED_14[12]; __IO uint32_t CRS7; /**< Control Register, offset: 0x710 */ uint8_t RESERVED_15[236]; - __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ + __IO uint32_t MGPCR0; /**< Initiator General Purpose Control Register, offset: 0x800 */ uint8_t RESERVED_16[252]; - __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ + __IO uint32_t MGPCR1; /**< Initiator General Purpose Control Register, offset: 0x900 */ uint8_t RESERVED_17[252]; - __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ + __IO uint32_t MGPCR2; /**< Initiator General Purpose Control Register, offset: 0xA00 */ uint8_t RESERVED_18[252]; - __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ + __IO uint32_t MGPCR3; /**< Initiator General Purpose Control Register, offset: 0xB00 */ uint8_t RESERVED_19[252]; - __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ + __IO uint32_t MGPCR4; /**< Initiator General Purpose Control Register, offset: 0xC00 */ uint8_t RESERVED_20[252]; - __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ + __IO uint32_t MGPCR5; /**< Initiator General Purpose Control Register, offset: 0xD00 */ uint8_t RESERVED_21[252]; - __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */ + __IO uint32_t MGPCR6; /**< Initiator General Purpose Control Register, offset: 0xE00 */ } AXBS_Type; /* ---------------------------------------------------------------------------- @@ -190,104 +190,104 @@ typedef struct { * @{ */ -/*! @name PRS0 - Priority Slave Registers */ +/*! @name PRS0 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS0_M0_MASK (0x7U) #define AXBS_PRS0_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS0_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M0_SHIFT)) & AXBS_PRS0_M0_MASK) #define AXBS_PRS0_M1_MASK (0x70U) #define AXBS_PRS0_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS0_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M1_SHIFT)) & AXBS_PRS0_M1_MASK) #define AXBS_PRS0_M2_MASK (0x700U) #define AXBS_PRS0_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS0_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M2_SHIFT)) & AXBS_PRS0_M2_MASK) #define AXBS_PRS0_M3_MASK (0x7000U) #define AXBS_PRS0_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS0_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M3_SHIFT)) & AXBS_PRS0_M3_MASK) #define AXBS_PRS0_M4_MASK (0x70000U) #define AXBS_PRS0_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS0_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M4_SHIFT)) & AXBS_PRS0_M4_MASK) #define AXBS_PRS0_M5_MASK (0x700000U) #define AXBS_PRS0_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS0_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M5_SHIFT)) & AXBS_PRS0_M5_MASK) #define AXBS_PRS0_M6_MASK (0x7000000U) #define AXBS_PRS0_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS0_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M6_SHIFT)) & AXBS_PRS0_M6_MASK) /*! @} */ @@ -298,23 +298,23 @@ typedef struct { #define AXBS_CRS0_PARK_MASK (0x7U) #define AXBS_CRS0_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS0_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PARK_SHIFT)) & AXBS_CRS0_PARK_MASK) #define AXBS_CRS0_PCTL_MASK (0x30U) #define AXBS_CRS0_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS0_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PCTL_SHIFT)) & AXBS_CRS0_PCTL_MASK) @@ -332,119 +332,119 @@ typedef struct { #define AXBS_CRS0_HLP_MASK (0x40000000U) #define AXBS_CRS0_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS0_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HLP_SHIFT)) & AXBS_CRS0_HLP_MASK) #define AXBS_CRS0_RO_MASK (0x80000000U) #define AXBS_CRS0_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS0_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_RO_SHIFT)) & AXBS_CRS0_RO_MASK) /*! @} */ -/*! @name PRS1 - Priority Slave Registers */ +/*! @name PRS1 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS1_M0_MASK (0x7U) #define AXBS_PRS1_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS1_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M0_SHIFT)) & AXBS_PRS1_M0_MASK) #define AXBS_PRS1_M1_MASK (0x70U) #define AXBS_PRS1_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS1_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M1_SHIFT)) & AXBS_PRS1_M1_MASK) #define AXBS_PRS1_M2_MASK (0x700U) #define AXBS_PRS1_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS1_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M2_SHIFT)) & AXBS_PRS1_M2_MASK) #define AXBS_PRS1_M3_MASK (0x7000U) #define AXBS_PRS1_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS1_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M3_SHIFT)) & AXBS_PRS1_M3_MASK) #define AXBS_PRS1_M4_MASK (0x70000U) #define AXBS_PRS1_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS1_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M4_SHIFT)) & AXBS_PRS1_M4_MASK) #define AXBS_PRS1_M5_MASK (0x700000U) #define AXBS_PRS1_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS1_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M5_SHIFT)) & AXBS_PRS1_M5_MASK) #define AXBS_PRS1_M6_MASK (0x7000000U) #define AXBS_PRS1_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS1_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M6_SHIFT)) & AXBS_PRS1_M6_MASK) /*! @} */ @@ -455,23 +455,23 @@ typedef struct { #define AXBS_CRS1_PARK_MASK (0x7U) #define AXBS_CRS1_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS1_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PARK_SHIFT)) & AXBS_CRS1_PARK_MASK) #define AXBS_CRS1_PCTL_MASK (0x30U) #define AXBS_CRS1_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS1_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PCTL_SHIFT)) & AXBS_CRS1_PCTL_MASK) @@ -489,119 +489,119 @@ typedef struct { #define AXBS_CRS1_HLP_MASK (0x40000000U) #define AXBS_CRS1_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS1_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HLP_SHIFT)) & AXBS_CRS1_HLP_MASK) #define AXBS_CRS1_RO_MASK (0x80000000U) #define AXBS_CRS1_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS1_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_RO_SHIFT)) & AXBS_CRS1_RO_MASK) /*! @} */ -/*! @name PRS2 - Priority Slave Registers */ +/*! @name PRS2 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS2_M0_MASK (0x7U) #define AXBS_PRS2_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS2_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M0_SHIFT)) & AXBS_PRS2_M0_MASK) #define AXBS_PRS2_M1_MASK (0x70U) #define AXBS_PRS2_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS2_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M1_SHIFT)) & AXBS_PRS2_M1_MASK) #define AXBS_PRS2_M2_MASK (0x700U) #define AXBS_PRS2_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS2_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M2_SHIFT)) & AXBS_PRS2_M2_MASK) #define AXBS_PRS2_M3_MASK (0x7000U) #define AXBS_PRS2_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS2_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M3_SHIFT)) & AXBS_PRS2_M3_MASK) #define AXBS_PRS2_M4_MASK (0x70000U) #define AXBS_PRS2_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS2_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M4_SHIFT)) & AXBS_PRS2_M4_MASK) #define AXBS_PRS2_M5_MASK (0x700000U) #define AXBS_PRS2_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS2_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M5_SHIFT)) & AXBS_PRS2_M5_MASK) #define AXBS_PRS2_M6_MASK (0x7000000U) #define AXBS_PRS2_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS2_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M6_SHIFT)) & AXBS_PRS2_M6_MASK) /*! @} */ @@ -612,23 +612,23 @@ typedef struct { #define AXBS_CRS2_PARK_MASK (0x7U) #define AXBS_CRS2_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS2_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PARK_SHIFT)) & AXBS_CRS2_PARK_MASK) #define AXBS_CRS2_PCTL_MASK (0x30U) #define AXBS_CRS2_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS2_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PCTL_SHIFT)) & AXBS_CRS2_PCTL_MASK) @@ -646,119 +646,119 @@ typedef struct { #define AXBS_CRS2_HLP_MASK (0x40000000U) #define AXBS_CRS2_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS2_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HLP_SHIFT)) & AXBS_CRS2_HLP_MASK) #define AXBS_CRS2_RO_MASK (0x80000000U) #define AXBS_CRS2_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS2_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_RO_SHIFT)) & AXBS_CRS2_RO_MASK) /*! @} */ -/*! @name PRS3 - Priority Slave Registers */ +/*! @name PRS3 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS3_M0_MASK (0x7U) #define AXBS_PRS3_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS3_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M0_SHIFT)) & AXBS_PRS3_M0_MASK) #define AXBS_PRS3_M1_MASK (0x70U) #define AXBS_PRS3_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS3_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M1_SHIFT)) & AXBS_PRS3_M1_MASK) #define AXBS_PRS3_M2_MASK (0x700U) #define AXBS_PRS3_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS3_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M2_SHIFT)) & AXBS_PRS3_M2_MASK) #define AXBS_PRS3_M3_MASK (0x7000U) #define AXBS_PRS3_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS3_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M3_SHIFT)) & AXBS_PRS3_M3_MASK) #define AXBS_PRS3_M4_MASK (0x70000U) #define AXBS_PRS3_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS3_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M4_SHIFT)) & AXBS_PRS3_M4_MASK) #define AXBS_PRS3_M5_MASK (0x700000U) #define AXBS_PRS3_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS3_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M5_SHIFT)) & AXBS_PRS3_M5_MASK) #define AXBS_PRS3_M6_MASK (0x7000000U) #define AXBS_PRS3_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS3_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M6_SHIFT)) & AXBS_PRS3_M6_MASK) /*! @} */ @@ -769,23 +769,23 @@ typedef struct { #define AXBS_CRS3_PARK_MASK (0x7U) #define AXBS_CRS3_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS3_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PARK_SHIFT)) & AXBS_CRS3_PARK_MASK) #define AXBS_CRS3_PCTL_MASK (0x30U) #define AXBS_CRS3_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS3_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PCTL_SHIFT)) & AXBS_CRS3_PCTL_MASK) @@ -803,119 +803,119 @@ typedef struct { #define AXBS_CRS3_HLP_MASK (0x40000000U) #define AXBS_CRS3_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS3_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HLP_SHIFT)) & AXBS_CRS3_HLP_MASK) #define AXBS_CRS3_RO_MASK (0x80000000U) #define AXBS_CRS3_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS3_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_RO_SHIFT)) & AXBS_CRS3_RO_MASK) /*! @} */ -/*! @name PRS4 - Priority Slave Registers */ +/*! @name PRS4 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS4_M0_MASK (0x7U) #define AXBS_PRS4_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS4_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M0_SHIFT)) & AXBS_PRS4_M0_MASK) #define AXBS_PRS4_M1_MASK (0x70U) #define AXBS_PRS4_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS4_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M1_SHIFT)) & AXBS_PRS4_M1_MASK) #define AXBS_PRS4_M2_MASK (0x700U) #define AXBS_PRS4_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS4_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M2_SHIFT)) & AXBS_PRS4_M2_MASK) #define AXBS_PRS4_M3_MASK (0x7000U) #define AXBS_PRS4_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS4_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M3_SHIFT)) & AXBS_PRS4_M3_MASK) #define AXBS_PRS4_M4_MASK (0x70000U) #define AXBS_PRS4_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS4_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M4_SHIFT)) & AXBS_PRS4_M4_MASK) #define AXBS_PRS4_M5_MASK (0x700000U) #define AXBS_PRS4_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS4_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M5_SHIFT)) & AXBS_PRS4_M5_MASK) #define AXBS_PRS4_M6_MASK (0x7000000U) #define AXBS_PRS4_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS4_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M6_SHIFT)) & AXBS_PRS4_M6_MASK) /*! @} */ @@ -926,23 +926,23 @@ typedef struct { #define AXBS_CRS4_PARK_MASK (0x7U) #define AXBS_CRS4_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS4_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PARK_SHIFT)) & AXBS_CRS4_PARK_MASK) #define AXBS_CRS4_PCTL_MASK (0x30U) #define AXBS_CRS4_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS4_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PCTL_SHIFT)) & AXBS_CRS4_PCTL_MASK) @@ -960,119 +960,119 @@ typedef struct { #define AXBS_CRS4_HLP_MASK (0x40000000U) #define AXBS_CRS4_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS4_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HLP_SHIFT)) & AXBS_CRS4_HLP_MASK) #define AXBS_CRS4_RO_MASK (0x80000000U) #define AXBS_CRS4_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS4_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_RO_SHIFT)) & AXBS_CRS4_RO_MASK) /*! @} */ -/*! @name PRS5 - Priority Slave Registers */ +/*! @name PRS5 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS5_M0_MASK (0x7U) #define AXBS_PRS5_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS5_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M0_SHIFT)) & AXBS_PRS5_M0_MASK) #define AXBS_PRS5_M1_MASK (0x70U) #define AXBS_PRS5_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS5_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M1_SHIFT)) & AXBS_PRS5_M1_MASK) #define AXBS_PRS5_M2_MASK (0x700U) #define AXBS_PRS5_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS5_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M2_SHIFT)) & AXBS_PRS5_M2_MASK) #define AXBS_PRS5_M3_MASK (0x7000U) #define AXBS_PRS5_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS5_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M3_SHIFT)) & AXBS_PRS5_M3_MASK) #define AXBS_PRS5_M4_MASK (0x70000U) #define AXBS_PRS5_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS5_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M4_SHIFT)) & AXBS_PRS5_M4_MASK) #define AXBS_PRS5_M5_MASK (0x700000U) #define AXBS_PRS5_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS5_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M5_SHIFT)) & AXBS_PRS5_M5_MASK) #define AXBS_PRS5_M6_MASK (0x7000000U) #define AXBS_PRS5_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS5_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M6_SHIFT)) & AXBS_PRS5_M6_MASK) /*! @} */ @@ -1083,23 +1083,23 @@ typedef struct { #define AXBS_CRS5_PARK_MASK (0x7U) #define AXBS_CRS5_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS5_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PARK_SHIFT)) & AXBS_CRS5_PARK_MASK) #define AXBS_CRS5_PCTL_MASK (0x30U) #define AXBS_CRS5_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS5_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PCTL_SHIFT)) & AXBS_CRS5_PCTL_MASK) @@ -1117,119 +1117,119 @@ typedef struct { #define AXBS_CRS5_HLP_MASK (0x40000000U) #define AXBS_CRS5_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS5_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HLP_SHIFT)) & AXBS_CRS5_HLP_MASK) #define AXBS_CRS5_RO_MASK (0x80000000U) #define AXBS_CRS5_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS5_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_RO_SHIFT)) & AXBS_CRS5_RO_MASK) /*! @} */ -/*! @name PRS6 - Priority Slave Registers */ +/*! @name PRS6 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS6_M0_MASK (0x7U) #define AXBS_PRS6_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS6_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M0_SHIFT)) & AXBS_PRS6_M0_MASK) #define AXBS_PRS6_M1_MASK (0x70U) #define AXBS_PRS6_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS6_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M1_SHIFT)) & AXBS_PRS6_M1_MASK) #define AXBS_PRS6_M2_MASK (0x700U) #define AXBS_PRS6_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS6_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M2_SHIFT)) & AXBS_PRS6_M2_MASK) #define AXBS_PRS6_M3_MASK (0x7000U) #define AXBS_PRS6_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS6_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M3_SHIFT)) & AXBS_PRS6_M3_MASK) #define AXBS_PRS6_M4_MASK (0x70000U) #define AXBS_PRS6_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS6_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M4_SHIFT)) & AXBS_PRS6_M4_MASK) #define AXBS_PRS6_M5_MASK (0x700000U) #define AXBS_PRS6_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS6_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M5_SHIFT)) & AXBS_PRS6_M5_MASK) #define AXBS_PRS6_M6_MASK (0x7000000U) #define AXBS_PRS6_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS6_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M6_SHIFT)) & AXBS_PRS6_M6_MASK) /*! @} */ @@ -1240,23 +1240,23 @@ typedef struct { #define AXBS_CRS6_PARK_MASK (0x7U) #define AXBS_CRS6_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS6_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PARK_SHIFT)) & AXBS_CRS6_PARK_MASK) #define AXBS_CRS6_PCTL_MASK (0x30U) #define AXBS_CRS6_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS6_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PCTL_SHIFT)) & AXBS_CRS6_PCTL_MASK) @@ -1274,119 +1274,119 @@ typedef struct { #define AXBS_CRS6_HLP_MASK (0x40000000U) #define AXBS_CRS6_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS6_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HLP_SHIFT)) & AXBS_CRS6_HLP_MASK) #define AXBS_CRS6_RO_MASK (0x80000000U) #define AXBS_CRS6_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS6_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_RO_SHIFT)) & AXBS_CRS6_RO_MASK) /*! @} */ -/*! @name PRS7 - Priority Slave Registers */ +/*! @name PRS7 - Priority Target Registers */ /*! @{ */ #define AXBS_PRS7_M0_MASK (0x7U) #define AXBS_PRS7_M0_SHIFT (0U) -/*! M0 - Master 0 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or the lowest priority when accessing the slave port. +/*! M0 - Initiator 0 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or the lowest priority when accessing the target port. */ #define AXBS_PRS7_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M0_SHIFT)) & AXBS_PRS7_M0_MASK) #define AXBS_PRS7_M1_MASK (0x70U) #define AXBS_PRS7_M1_SHIFT (4U) -/*! M1 - Master 1 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M1 - Initiator 1 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS7_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M1_SHIFT)) & AXBS_PRS7_M1_MASK) #define AXBS_PRS7_M2_MASK (0x700U) #define AXBS_PRS7_M2_SHIFT (8U) -/*! M2 - Master 2 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M2 - Initiator 2 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS7_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M2_SHIFT)) & AXBS_PRS7_M2_MASK) #define AXBS_PRS7_M3_MASK (0x7000U) #define AXBS_PRS7_M3_SHIFT (12U) -/*! M3 - Master 3 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M3 - Initiator 3 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS7_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M3_SHIFT)) & AXBS_PRS7_M3_MASK) #define AXBS_PRS7_M4_MASK (0x70000U) #define AXBS_PRS7_M4_SHIFT (16U) -/*! M4 - Master 4 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M4 - Initiator 4 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS7_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M4_SHIFT)) & AXBS_PRS7_M4_MASK) #define AXBS_PRS7_M5_MASK (0x700000U) #define AXBS_PRS7_M5_SHIFT (20U) -/*! M5 - Master 5 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8 or lowest priority when accessing the slave port. +/*! M5 - Initiator 5 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8 or lowest priority when accessing the target port. */ #define AXBS_PRS7_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M5_SHIFT)) & AXBS_PRS7_M5_MASK) #define AXBS_PRS7_M6_MASK (0x7000000U) #define AXBS_PRS7_M6_SHIFT (24U) -/*! M6 - Master 6 Priority - * 0b000..This master has level 1 or highest priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8the or lowest priority when accessing the slave port. +/*! M6 - Initiator 6 Priority + * 0b000..This initiator has level 1 or highest priority when accessing the target port. + * 0b001..This initiator has level 2 priority when accessing the target port. + * 0b010..This initiator has level 3 priority when accessing the target port. + * 0b011..This initiator has level 4 priority when accessing the target port. + * 0b100..This initiator has level 5 priority when accessing the target port. + * 0b101..This initiator has level 6 priority when accessing the target port. + * 0b110..This initiator has level 7 priority when accessing the target port. + * 0b111..This initiator has level 8the or lowest priority when accessing the target port. */ #define AXBS_PRS7_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M6_SHIFT)) & AXBS_PRS7_M6_MASK) /*! @} */ @@ -1397,23 +1397,23 @@ typedef struct { #define AXBS_CRS7_PARK_MASK (0x7U) #define AXBS_CRS7_PARK_SHIFT (0U) /*! PARK - Park - * 0b000..Park on master port M0. - * 0b001..Park on master port M1. - * 0b010..Park on master port M2. - * 0b011..Park on master port M3. - * 0b100..Park on master port M4. - * 0b101..Park on master port M5. - * 0b110..Park on master port M6. - * 0b111..Park on master port M7. + * 0b000..Park on initiator port M0. + * 0b001..Park on initiator port M1. + * 0b010..Park on initiator port M2. + * 0b011..Park on initiator port M3. + * 0b100..Park on initiator port M4. + * 0b101..Park on initiator port M5. + * 0b110..Park on initiator port M6. + * 0b111..Park on initiator port M7. */ #define AXBS_CRS7_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PARK_SHIFT)) & AXBS_CRS7_PARK_MASK) #define AXBS_CRS7_PCTL_MASK (0x30U) #define AXBS_CRS7_PCTL_SHIFT (4U) /*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field. - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state. + * 0b00..When no initiator makes a request, the arbiter parks the target port on the initiator port defined by the PARK field. + * 0b01..When no initiator makes a request, the arbiter parks the target port on the last initiator to be in control of the target port. + * 0b10..When no initiator makes a request, the target port is not parked on a initiator and the arbiter drives all outputs to a constant safe state. * 0b11..Reserved */ #define AXBS_CRS7_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PCTL_SHIFT)) & AXBS_CRS7_PCTL_MASK) @@ -1431,22 +1431,22 @@ typedef struct { #define AXBS_CRS7_HLP_MASK (0x40000000U) #define AXBS_CRS7_HLP_SHIFT (30U) /*! HLP - Halt Low Priority - * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. - * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. + * 0b0..The low-power mode request has the highest priority for arbitration on this target port. + * 0b1..The low-power mode request has the lowest initial priority for arbitration on this target port. */ #define AXBS_CRS7_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HLP_SHIFT)) & AXBS_CRS7_HLP_MASK) #define AXBS_CRS7_RO_MASK (0x80000000U) #define AXBS_CRS7_RO_SHIFT (31U) /*! RO - Read Only - * 0b0..The slave port's registers are writeable. - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not affect the + * 0b0..The target port's registers are writeable. + * 0b1..The target port's registers are read-only and cannot be written. Attempted writes do not affect the * registers and result in a bus error response. */ #define AXBS_CRS7_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_RO_SHIFT)) & AXBS_CRS7_RO_MASK) /*! @} */ -/*! @name MGPCR0 - Master General Purpose Control Register */ +/*! @name MGPCR0 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR0_AULB_MASK (0x7U) @@ -1464,7 +1464,7 @@ typedef struct { #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) /*! @} */ -/*! @name MGPCR1 - Master General Purpose Control Register */ +/*! @name MGPCR1 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR1_AULB_MASK (0x7U) @@ -1482,7 +1482,7 @@ typedef struct { #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) /*! @} */ -/*! @name MGPCR2 - Master General Purpose Control Register */ +/*! @name MGPCR2 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR2_AULB_MASK (0x7U) @@ -1500,7 +1500,7 @@ typedef struct { #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) /*! @} */ -/*! @name MGPCR3 - Master General Purpose Control Register */ +/*! @name MGPCR3 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR3_AULB_MASK (0x7U) @@ -1518,7 +1518,7 @@ typedef struct { #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) /*! @} */ -/*! @name MGPCR4 - Master General Purpose Control Register */ +/*! @name MGPCR4 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR4_AULB_MASK (0x7U) @@ -1536,7 +1536,7 @@ typedef struct { #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) /*! @} */ -/*! @name MGPCR5 - Master General Purpose Control Register */ +/*! @name MGPCR5 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR5_AULB_MASK (0x7U) @@ -1554,7 +1554,7 @@ typedef struct { #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) /*! @} */ -/*! @name MGPCR6 - Master General Purpose Control Register */ +/*! @name MGPCR6 - Initiator General Purpose Control Register */ /*! @{ */ #define AXBS_MGPCR6_AULB_MASK (0x7U) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BLE2_REG.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BLE2_REG.h index cecffee46..09bd7791d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BLE2_REG.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BLE2_REG.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for BLE2_REG diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BRIC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BRIC.h index 134b138a4..3598584ec 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BRIC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BRIC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for BRIC diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BTRTU1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BTRTU1.h index 22a7a2034..0bce27a00 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BTRTU1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BTRTU1.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for BTRTU1 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BTU2_REG.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BTU2_REG.h index 7d7aa65ad..2fb0807da 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BTU2_REG.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_BTU2_REG.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for BTU2_REG diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CAN.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CAN.h index 7717a8d49..a12314e43 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CAN.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CAN.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CAN @@ -352,7 +352,7 @@ typedef struct { #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) -/*! SLFWAK - Self Wake-up +/*! SLFWAK - Self-Wake-Up Feature * 0b0..Disable * 0b1..Enable */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CCM32K.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CCM32K.h index fe97e7570..0addcbad2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CCM32K.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CCM32K.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CCM32K @@ -142,6 +142,8 @@ typedef struct { __IO uint32_t CLKMON_CTRL; /**< Clock Monitor Control Register, offset: 0x14 */ __IO uint32_t CLKMON_TST; /**< Clock Monitor Test Register, offset: 0x18 */ __IO uint32_t CGC32K; /**< 32 kHz Clock Gate Control Register, offset: 0x1C */ + uint8_t RESERVED_1[4]; + __IO uint32_t OSC32K_MON_TRIM; /**< 32 kHz OSC Internal Monitor Trim Register, offset: 0x24 */ } CCM32K_Type; /* ---------------------------------------------------------------------------- @@ -219,6 +221,14 @@ typedef struct { */ #define CCM32K_OSC32K_CTRL_OSC_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_OSC_BYP_EN_SHIFT)) & CCM32K_OSC32K_CTRL_OSC_BYP_EN_MASK) +#define CCM32K_OSC32K_CTRL_OSC_CLKMON_EN_MASK (0x4U) +#define CCM32K_OSC32K_CTRL_OSC_CLKMON_EN_SHIFT (2U) +/*! OSC_CLKMON_EN - Crystal Oscillator Internal Clock Monitor Enable + * 0b0..Oscillator internal clock monitor is disabled + * 0b1..Oscillator internal clock monitor is enabled + */ +#define CCM32K_OSC32K_CTRL_OSC_CLKMON_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_OSC_CLKMON_EN_SHIFT)) & CCM32K_OSC32K_CTRL_OSC_CLKMON_EN_MASK) + #define CCM32K_OSC32K_CTRL_CAP_TRIM_MASK (0x60U) #define CCM32K_OSC32K_CTRL_CAP_TRIM_SHIFT (5U) /*! CAP_TRIM - SOX Capacitor Trim */ @@ -281,6 +291,14 @@ typedef struct { /*! CMP_TRIM - SOX Comparator trim */ #define CCM32K_OSC32K_CTRL_CMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_CMP_TRIM_SHIFT)) & CCM32K_OSC32K_CTRL_CMP_TRIM_MASK) +#define CCM32K_OSC32K_CTRL_OSC_HP_EN_MASK (0x80000U) +#define CCM32K_OSC32K_CTRL_OSC_HP_EN_SHIFT (19U) +/*! OSC_HP_EN - Crystal Oscillator High Power Enable + * 0b0..Oscillator internal clock monitor is disabled + * 0b1..Oscillator internal clock monitor is enabled + */ +#define CCM32K_OSC32K_CTRL_OSC_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_OSC_HP_EN_SHIFT)) & CCM32K_OSC32K_CTRL_OSC_HP_EN_MASK) + #define CCM32K_OSC32K_CTRL_COARSE_AMP_GAIN_MASK (0x300000U) #define CCM32K_OSC32K_CTRL_COARSE_AMP_GAIN_SHIFT (20U) /*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external crystal ESR values. @@ -352,6 +370,14 @@ typedef struct { * 0b1..Clock error is detected */ #define CCM32K_STATUS_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_STATUS_CLOCK_DET_SHIFT)) & CCM32K_STATUS_CLOCK_DET_MASK) + +#define CCM32K_STATUS_AUTO_SWITCH_MASK (0x100U) +#define CCM32K_STATUS_AUTO_SWITCH_SHIFT (8U) +/*! AUTO_SWITCH - Clock Source Auto switch + * 0b0..Clock source do not switch + * 0b1..Clock source switch back to FRO + */ +#define CCM32K_STATUS_AUTO_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_STATUS_AUTO_SWITCH_SHIFT)) & CCM32K_STATUS_AUTO_SWITCH_MASK) /*! @} */ /*! @name CLKMON_CTRL - Clock Monitor Control Register */ @@ -385,6 +411,14 @@ typedef struct { */ #define CCM32K_CLKMON_CTRL_DIVIDE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_CLKMON_CTRL_DIVIDE_TRIM_SHIFT)) & CCM32K_CLKMON_CTRL_DIVIDE_TRIM_MASK) +#define CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN_MASK (0x100U) +#define CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN_SHIFT (8U) +/*! AUTO_SWITCH_EN - Automatic Switch Enable Bit + * 0b0..Automatic switch is disable + * 0b1..Automatic switch is enable + */ +#define CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN_SHIFT)) & CCM32K_CLKMON_CTRL_AUTO_SWITCH_EN_MASK) + #define CCM32K_CLKMON_CTRL_LOCK_EN_MASK (0x80000000U) #define CCM32K_CLKMON_CTRL_LOCK_EN_SHIFT (31U) /*! LOCK_EN - Write Access Lock bit @@ -439,6 +473,40 @@ typedef struct { #define CCM32K_CGC32K_LOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_CGC32K_LOCK_EN_SHIFT)) & CCM32K_CGC32K_LOCK_EN_MASK) /*! @} */ +/*! @name OSC32K_MON_TRIM - 32 kHz OSC Internal Monitor Trim Register */ +/*! @{ */ + +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH_MASK (0x1FU) +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH_SHIFT (0U) +/*! CAP_TRIM_HIGH - OSC32K Internal Monitor Capacitance Trim for Clock High Level + * 0b11111..Default trim value + */ +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH_SHIFT)) & CCM32K_OSC32K_MON_TRIM_CAP_TRIM_HIGH_MASK) + +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW_MASK (0x1F00U) +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW_SHIFT (8U) +/*! CAP_TRIM_LOW - OSC32K Internal Monitor Capacitance Trim for Clock Low Level + * 0b11111..Default trim value + */ +#define CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW_SHIFT)) & CCM32K_OSC32K_MON_TRIM_CAP_TRIM_LOW_MASK) + +#define CCM32K_OSC32K_MON_TRIM_IFR_DIS_MASK (0x20000000U) +#define CCM32K_OSC32K_MON_TRIM_IFR_DIS_SHIFT (29U) +/*! IFR_DIS - IFR Loading Disable Control + * 0b0..IFR loading is enabled + * 0b1..IFR loading is disabled + */ +#define CCM32K_OSC32K_MON_TRIM_IFR_DIS(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_MON_TRIM_IFR_DIS_SHIFT)) & CCM32K_OSC32K_MON_TRIM_IFR_DIS_MASK) + +#define CCM32K_OSC32K_MON_TRIM_LOCK_EN_MASK (0x80000000U) +#define CCM32K_OSC32K_MON_TRIM_LOCK_EN_SHIFT (31U) +/*! LOCK_EN - Write Access Lock + * 0b0..Register write access is unlocked + * 0b1..Register write access is locked + */ +#define CCM32K_OSC32K_MON_TRIM_LOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_MON_TRIM_LOCK_EN_SHIFT)) & CCM32K_OSC32K_MON_TRIM_LOCK_EN_MASK) +/*! @} */ + /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CIU2.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CIU2.h index ee2e60159..ae08c1e1f 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CIU2.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CIU2.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CIU2 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CMC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CMC.h index 593f65f70..5d3b7347e 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CMC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CMC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CMC diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CRC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CRC.h index 4d03ea145..1c802844d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CRC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_CRC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for CRC diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DBGMB.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DBGMB.h index 9501c89df..413e7df07 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DBGMB.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DBGMB.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for DBGMB diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DMA.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DMA.h index 1ef434e7c..c9c982b57 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DMA.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DMA.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for DMA @@ -328,9 +328,9 @@ typedef struct { #define DMA_MP_CSR_GMRC_MASK (0x80U) #define DMA_MP_CSR_GMRC_SHIFT (7U) -/*! GMRC - Global Master ID Replication Control - * 0b0..Master ID replication disabled for all channels - * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting +/*! GMRC - Global Initiator ID Replication Control + * 0b0..Initiator ID replication disabled for all channels + * 0b1..Initiator ID replication available and controlled by each channel's CHn_SBR[EMI] setting */ #define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) @@ -631,7 +631,7 @@ typedef struct { #define DMA_CH_SBR_MID_MASK (0x3FU) #define DMA_CH_SBR_MID_SHIFT (0U) -/*! MID - Master ID */ +/*! MID - Initiator ID */ #define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) #define DMA_CH_SBR_SEC_MASK (0x4000U) @@ -652,9 +652,9 @@ typedef struct { #define DMA_CH_SBR_EMI_MASK (0x10000U) #define DMA_CH_SBR_EMI_SHIFT (16U) -/*! EMI - Enable Master ID Replication - * 0b0..Master ID replication is disabled - * 0b1..Master ID replication is enabled +/*! EMI - Enable Initiator ID Replication + * 0b0..Initiator ID replication is disabled + * 0b1..Initiator ID replication is enabled */ #define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) @@ -762,7 +762,6 @@ typedef struct { #define DMA_TCD_ATTR_SMOD_SHIFT (11U) /*! SMOD - Source Address Modulo * 0b00000..Source address modulo feature disabled - * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] */ #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DSB.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DSB.h index 747ef43de..313aceea0 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DSB.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_DSB.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for DSB @@ -193,6 +193,14 @@ typedef struct { * 0b1..Error interrupt requests enabled */ #define DSB_CSR_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DSB_CSR_ERR_EN_SHIFT)) & DSB_CSR_ERR_EN_MASK) + +#define DSB_CSR_CBT_EN_MASK (0x20U) +#define DSB_CSR_CBT_EN_SHIFT (5U) +/*! CBT_EN - Continuous Burst Transfer Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define DSB_CSR_CBT_EN(x) (((uint32_t)(((uint32_t)(x)) << DSB_CSR_CBT_EN_SHIFT)) & DSB_CSR_CBT_EN_MASK) /*! @} */ /*! @name INT - Interrupt Request Status */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ELEMU.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ELEMU.h index 4a72f9be2..e5e3507f7 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ELEMU.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_ELEMU.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for ELEMU diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_EWM.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_EWM.h index ddb552375..d231f4ae3 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_EWM.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_EWM.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for EWM diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FLEXIO.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FLEXIO.h index 4b6dfa0e1..d504d3140 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FLEXIO.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FLEXIO.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXIO diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FMU.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FMU.h index 22e6f9bfb..a2ff8e7b3 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FMU.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FMU.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for FMU diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FRO192M.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FRO192M.h index d2b3df8b5..8f586a954 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FRO192M.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_FRO192M.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for FRO192M diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GEN4PHY.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GEN4PHY.h index f94feb082..163cf3608 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GEN4PHY.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GEN4PHY.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for GEN4PHY diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GENFSK.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GENFSK.h index 066c720d0..83cfa5b80 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GENFSK.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GENFSK.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for GENFSK diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GPIO.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GPIO.h index 92fa82d49..e1ba36bdd 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GPIO.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_GPIO.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for GPIO diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_I3C.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_I3C.h index 748975df5..ecdf7b759 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_I3C.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_I3C.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for I3C @@ -237,7 +237,7 @@ typedef struct { #define I3C_MCONFIG_DISTO_SHIFT (3U) /*! DISTO - Disable Timeout * 0b0..Enabled - * 0b1..Disabled, if configured + * 0b1..Disabled */ #define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPCMP.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPCMP.h index aaf97c2b4..3a3dcb2b8 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPCMP.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPCMP.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPCMP diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPI2C.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPI2C.h index 0147e68d7..84fa4c472 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPI2C.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPI2C.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPI2C @@ -1228,16 +1228,16 @@ typedef struct { #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) /*! TXCFG - Transmit Flag Configuration - * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty - * 0b1..MSR[TDF] is set whenever STDR is empty + * 0b0..SSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..SSR[TDF] is set whenever STDR is empty */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration - * 0b0..Return received data, clear MSR[RDF] - * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set + * 0b0..Return received data, clear SSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear SSR[RDF] when SSR[AFV] is not set */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPIT.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPIT.h index 95a72a1e4..51d720a72 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPIT.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPIT.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPIT diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPSPI.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPSPI.h index bde50fe3c..8c07efb60 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPSPI.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPSPI.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPSPI diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPTMR.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPTMR.h index a807e86fa..87e9effb2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPTMR.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPTMR.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPTMR diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPUART.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPUART.h index b33294a0a..0c718136f 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPUART.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LPUART.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPUART diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LTC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LTC.h index 672399ef3..80935e9f7 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LTC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_LTC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for LTC diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MCM.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MCM.h index 6168c9714..01cf9f564 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MCM.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MCM.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCM @@ -366,7 +366,7 @@ typedef struct { #define MCM_FATR_BEMN_MASK (0xF00U) #define MCM_FATR_BEMN_SHIFT (8U) -/*! BEMN - Bus Error Master Number */ +/*! BEMN - Bus Error Initiator Number */ #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) #define MCM_FATR_BEOVR_MASK (0x80000000U) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MRCC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MRCC.h index cc46ce22b..4111ef486 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MRCC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MRCC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MRCC diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MSCM.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MSCM.h index a027337f9..10dae4ac6 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MSCM.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MSCM.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MSCM @@ -1119,19 +1119,21 @@ typedef struct { #define MSCM_SID_PINID_MASK (0x70U) #define MSCM_SID_PINID_SHIFT (4U) /*! PINID - Pin Identification - * 0b010..40HVQFN + * 0b010..Reserved * 0b011..48HVQFN - * 0b100..56HVQFN + * 0b100..Reserved + * 0b101..Reserved + * 0b110..Reserved */ #define MSCM_SID_PINID(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_PINID_SHIFT)) & MSCM_SID_PINID_MASK) -#define MSCM_SID_CMP_MASK (0x80U) -#define MSCM_SID_CMP_SHIFT (7U) -/*! CMP - CMP Presence - * 0b0..No CMP - * 0b1..CMP present +#define MSCM_SID_LCE_MASK (0x80U) +#define MSCM_SID_LCE_SHIFT (7U) +/*! LCE - LCE Presence + * 0b0..No LCE + * 0b1..LCE present */ -#define MSCM_SID_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_CMP_SHIFT)) & MSCM_SID_CMP_MASK) +#define MSCM_SID_LCE(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_LCE_SHIFT)) & MSCM_SID_LCE_MASK) #define MSCM_SID_FLXIO_MASK (0x100U) #define MSCM_SID_FLXIO_SHIFT (8U) @@ -1176,16 +1178,19 @@ typedef struct { #define MSCM_SID_RAMSZ_MASK (0xE000U) #define MSCM_SID_RAMSZ_SHIFT (13U) /*! RAMSZ - RAM Size - * 0b000..96 KB - * 0b111..128 KB + * 0b101..136 KB + 171 KB + * 0b110..Reserved + * 0b111..264 KB + 171 KB */ #define MSCM_SID_RAMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_RAMSZ_SHIFT)) & MSCM_SID_RAMSZ_MASK) #define MSCM_SID_FLSZ_MASK (0xF0000U) #define MSCM_SID_FLSZ_SHIFT (16U) /*! FLSZ - Flash Size - * 0b1101..1 MB - * 0b1111..512 KB + * 0b1011..Reserved + * 0b1101..1 MB + 512 KB + * 0b1110..Reserved + * 0b1111..2 MB + 512 KB */ #define MSCM_SID_FLSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_FLSZ_SHIFT)) & MSCM_SID_FLSZ_MASK) @@ -1193,9 +1198,11 @@ typedef struct { #define MSCM_SID_BLEF_SHIFT (20U) /*! BLEF - Bluetooth LE Feature * 0b0000..No Bluetooth LE present - * 0b0001..Bluetooth LE 5.1 - * 0b0010..Bluetooth LE 5.2 - * 0b0011..Bluetooth LE 5.3 + * 0b0001..Reserved + * 0b0010..Reserved + * 0b0011..Reserved + * 0b0100..Reserved + * 0b1000..Reserved * 0b1111..Bluetooth LE Upgrade */ #define MSCM_SID_BLEF(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_BLEF_SHIFT)) & MSCM_SID_BLEF_MASK) @@ -1203,9 +1210,9 @@ typedef struct { #define MSCM_SID_RADIOF_MASK (0xF000000U) #define MSCM_SID_RADIOF_SHIFT (24U) /*! RADIOF - Radio Feature - * 0b0000..802.15.4 + * 0b0000..Reserved * 0b0001..Bluetooth LE - * 0b0010..Bluetooth LE + 802.15.4 + * 0b0010..Reserved */ #define MSCM_SID_RADIOF(x) (((uint32_t)(((uint32_t)(x)) << MSCM_SID_RADIOF_SHIFT)) & MSCM_SID_RADIOF_MASK) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MSF1_B_TEST.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MSF1_B_TEST.h index 2fb0fbb07..12e6a654f 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MSF1_B_TEST.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MSF1_B_TEST.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MSF1_B_test diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MU.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MU.h index 78727db9c..4be35e345 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MU.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_MU.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for MU diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_NPX.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_NPX.h index c5f6bcaaa..6cea2dd21 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_NPX.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_NPX.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for NPX diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_PORT.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_PORT.h index c50d24325..c223564b2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_PORT.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_PORT.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for PORT diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RADIO_CTRL.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RADIO_CTRL.h index e08b506ae..296dabbe1 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RADIO_CTRL.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RADIO_CTRL.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RADIO_CTRL diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RBME.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RBME.h index 371b89a32..871eddefa 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RBME.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RBME.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RBME diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_REGFILE.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_REGFILE.h index b705a5fc3..0f09fabbd 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_REGFILE.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_REGFILE.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for REGFILE diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RFMC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RFMC.h index e6cf774d0..9ae150895 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RFMC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RFMC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RFMC @@ -154,6 +154,7 @@ typedef struct { __IO uint32_t RF2P4GHZ_HOST2RADIO; /**< RF 2.4GHz Buffer from Host to Radio, offset: 0x48 */ __I uint32_t RF2P4GHZ_RADIO2HOST; /**< RF 2.4GHz Buffer from Radio to Host, offset: 0x4C */ __IO uint32_t RF2P4GHZ_CFG; /**< 2.4GHz Radio Configuration Register, offset: 0x50 */ + __I uint32_t RF2P4GHZ_WKUP_SRC; /**< 2.4GHz Radio WakeUp Source Register, offset: 0x54 */ } RFMC_Type; /* ---------------------------------------------------------------------------- @@ -401,8 +402,8 @@ typedef struct { #define RFMC_XO_TEST_CDAC_MASK (0x3F0U) #define RFMC_XO_TEST_CDAC_SHIFT (4U) /*! CDAC - XO On-chip Load Capacitor Trim - * 0b000000..6pF - * 0b111111..11pF + * 0b000000..C_FIX + * 0b111111..C_FIX + 14.36pF */ #define RFMC_XO_TEST_CDAC(x) (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_CDAC_SHIFT)) & RFMC_XO_TEST_CDAC_MASK) @@ -456,7 +457,12 @@ typedef struct { #define RFMC_XO_TEST_XO_CDAC_TRIM_MASK (0x600000U) #define RFMC_XO_TEST_XO_CDAC_TRIM_SHIFT (21U) -/*! XO_CDAC_TRIM - reg_xo_cdac_trim[1:0] */ +/*! XO_CDAC_TRIM - XO fixed cap bank C_FIX trimming + * 0b00..5.19pF + * 0b01..3.81pF + * 0b10..2.44pF + * 0b11..1.98pF + */ #define RFMC_XO_TEST_XO_CDAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_XO_CDAC_TRIM_SHIFT)) & RFMC_XO_TEST_XO_CDAC_TRIM_MASK) /*! @} */ @@ -977,6 +983,40 @@ typedef struct { #define RFMC_RF2P4GHZ_CFG_FORCE_DBG_PWRUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CFG_FORCE_DBG_PWRUP_ACK_SHIFT)) & RFMC_RF2P4GHZ_CFG_FORCE_DBG_PWRUP_ACK_MASK) /*! @} */ +/*! @name RF2P4GHZ_WKUP_SRC - 2.4GHz Radio WakeUp Source Register */ +/*! @{ */ + +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS_MASK (0x1U) +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS_SHIFT (0U) +/*! RFMC_RADIO_DEBUG_REQ_STATUS - Radio debug request status */ +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_RFMC_RADIO_DEBUG_REQ_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS_MASK (0x6U) +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS_SHIFT (1U) +/*! RFMC_EXT_WAKEUP_STATUS - Radio wakeup by external source status */ +#define RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_RFMC_EXT_WAKEUP_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS_MASK (0x8U) +#define RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS_SHIFT (3U) +/*! BLE_WKUP_STATUS - RFMC BLE Wakeup status (Host Controlled) */ +#define RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_BLE_WKUP_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS_MASK (0x10U) +#define RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS_SHIFT (4U) +/*! MAN_WKUP_STATUS - RFMC MAN Wakeup status (Host Controlled) */ +#define RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_MAN_WKUP_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS_MASK (0x20U) +#define RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS_SHIFT (5U) +/*! WOR_WKUP_STATUS - RFMC WOR Wakeup status (Host Controlled) */ +#define RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_WOR_WKUP_STATUS_MASK) + +#define RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS_MASK (0x40U) +#define RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS_SHIFT (6U) +/*! RF_CMC_BLE_WKUP_STATUS - RF_CMC BLE Wakeup status */ +#define RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS_SHIFT)) & RFMC_RF2P4GHZ_WKUP_SRC_RF_CMC_BLE_WKUP_STATUS_MASK) +/*! @} */ + /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RF_CMC1.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RF_CMC1.h index 2a9caff99..1e91d79e0 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RF_CMC1.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RF_CMC1.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RF_CMC1 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RF_FMCCFG.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RF_FMCCFG.h index 2d76eb5a9..396cfb98a 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RF_FMCCFG.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RF_FMCCFG.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RF_FMCCFG diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RTC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RTC.h index 22b4b1790..32f49f558 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RTC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RTC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RTC @@ -231,7 +231,7 @@ typedef struct { #define RTC_CR_SWR_SHIFT (0U) /*! SWR - Software Reset * 0b0..No effect. - * 0b1..Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. + * 0b1..Resets all RTC registers except for this bit . This bit is cleared by POR and by software explicitly clearing it. */ #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) @@ -271,7 +271,7 @@ typedef struct { #define RTC_CR_CPE_SHIFT (24U) /*! CPE - Clock Pin Enable * 0b000..Disables - * 0b001..Enables on RTC_TAMPER[1] + * 0b001..Enables RTC_CLKOUT function on RTC_TAMPER[1]. * 0b010..Enables RTC_CLKOUT function on RTC_TAMPER[2]. * 0b011..Enables RTC_CLKOUT function on RTC_TAMPER[3]. * 0b100..Enables RTC_CLKOUT function on RTC_TAMPER[4]. @@ -419,7 +419,10 @@ typedef struct { #define RTC_LR_PCL_MASK (0xFF0000U) #define RTC_LR_PCL_SHIFT (16U) -/*! PCL - Pin Configuration Lock */ +/*! PCL - Pin Configuration Lock + * 0b00000000..Pin Configuration Register is locked and writes are ignored. + * 0b00000001..Pin Configuration Register is not locked and writes complete as normal. + */ #define RTC_LR_PCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_PCL_SHIFT)) & RTC_LR_PCL_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RX_PACKET_RAM.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RX_PACKET_RAM.h index de6c5666f..9b2969079 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RX_PACKET_RAM.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_RX_PACKET_RAM.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for RX_PACKET_RAM diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SCG.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SCG.h index 237f06efb..7d262be81 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SCG.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SCG.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SCG diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SEMA42.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SEMA42.h index de095cec4..fca1ae669 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SEMA42.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SEMA42.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SEMA42 diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SFA.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SFA.h index 6184b90d7..94d6c280c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SFA.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SFA.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SFA diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SMSCM.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SMSCM.h index e1cb6404d..5f58efe3d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SMSCM.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SMSCM.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SMSCM @@ -805,14 +805,6 @@ typedef struct { * 0b1..AXBS0 in round robin arbitration mode at reset. */ #define SMSCM_CPCR_AXBS0_RREN(x) (((uint32_t)(((uint32_t)(x)) << SMSCM_CPCR_AXBS0_RREN_SHIFT)) & SMSCM_CPCR_AXBS0_RREN_MASK) - -#define SMSCM_CPCR_AXBS1_RREN_MASK (0x2U) -#define SMSCM_CPCR_AXBS1_RREN_SHIFT (1U) -/*! AXBS1_RREN - AXBS1 Round Robin Enable - * 0b0..AXBS1 in fixed priority arbitration mode at reset. - * 0b1..AXBS1 in round robin arbitration mode at reset. - */ -#define SMSCM_CPCR_AXBS1_RREN(x) (((uint32_t)(((uint32_t)(x)) << SMSCM_CPCR_AXBS1_RREN_SHIFT)) & SMSCM_CPCR_AXBS1_RREN_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SPC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SPC.h index 949c86059..095c2a3b0 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SPC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SPC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SPC @@ -475,8 +475,7 @@ typedef struct { #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU) #define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U) /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level - * 0b00.. - * 0b00..Regulate to under voltage (0.95 V) + * 0b00..Regulate to boost voltage (0.95 V) * 0b01..Regulate to mid voltage (1.0 V) * 0b10..Regulate to normal voltage (1.1 V) * 0b11..Regulate to safe-mode voltage (1.15 V) @@ -510,10 +509,10 @@ typedef struct { #define SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level - * 0b00..Low undervoltage (1.25 V) - * 0b01..Midvoltage (1.35 V) - * 0b10..Normal voltage (1.5 V) - * 0b11..Safe-mode voltage (1.8 V) + * 0b00..Low undervoltage voltage (0.95 V) + * 0b01..Mid voltage (1 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.8 V) */ #define SPC_ACTIVE_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) @@ -634,10 +633,10 @@ typedef struct { #define SPC_LP_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level - * 0b00..Low under voltage (1.25 V) - * 0b01..Mid voltage (1.35 V) - * 0b10.. - * 0b11..Safe-mode voltage (1.8 V) + * 0b00..Low undervoltage (0.95 V) + * 0b01..Mid voltage (1 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.8 V) */ #define SPC_LP_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_LP_CFG_DCDC_VDD_LVL_MASK) @@ -780,10 +779,10 @@ typedef struct { #define SPC_HP_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_HP_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level - * 0b00..Low undervoltage (1.25 V) - * 0b01..Midvoltage (1.35 V) - * 0b10..Normal voltage (1.5 V) - * 0b11..Safe-mode voltage (1.8 V) + * 0b00..Low undervoltage (0.95 V) + * 0b01..Mid voltage (1 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.8 V) */ #define SPC_HP_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_HP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_HP_CFG_DCDC_VDD_LVL_MASK) @@ -1023,6 +1022,14 @@ typedef struct { */ #define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) +#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - System Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) + #define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) #define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) /*! LOCK - System Voltage Detect Reset Enable Lock diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SYSPM.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SYSPM.h index 28828f49b..abfd8ae9c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SYSPM.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_SYSPM.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for SYSPM diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TPM.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TPM.h index 63a7257ce..4218fcf56 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TPM.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TPM.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TPM diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TRDC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TRDC.h index fff3b3447..95693372f 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TRDC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TRDC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRDC @@ -304,10 +304,10 @@ typedef struct { __IO uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */ } MRC_DERR[TRDC_MRC_DERR_COUNT]; uint8_t RESERVED_8[880]; - __IO uint32_t MDA_W0_0_DFMT0; /**< DAC Master Domain Assignment Register, offset: 0x800 */ + __IO uint32_t MDA_W0_0_DFMT0; /**< DAC Initiator Domain Assignment Register, offset: 0x800 */ uint8_t RESERVED_9[28]; struct { /* offset: 0x820, array step: 0x20 */ - __IO uint32_t MDA_W0_x_DFMT1; /**< DAC Master Domain Assignment Register, array offset: 0x820, array step: 0x20 */ + __IO uint32_t MDA_W0_x_DFMT1; /**< DAC Initiator Domain Assignment Register, array offset: 0x820, array step: 0x20 */ uint8_t RESERVED_0[28]; } MDA_W0_DFMT1[TRDC_MDA_W0_DFMT1_COUNT]; uint8_t RESERVED_10[1888]; @@ -449,7 +449,7 @@ typedef struct { #define TRDC_TRDC_HWCFG0_NMSTR_MASK (0xFF00U) #define TRDC_TRDC_HWCFG0_NMSTR_SHIFT (8U) -/*! NMSTR - Number of bus masters */ +/*! NMSTR - Number of bus initiators */ #define TRDC_TRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_TRDC_HWCFG0_NMSTR_MASK) #define TRDC_TRDC_HWCFG0_NMBC_MASK (0x70000U) @@ -482,14 +482,14 @@ typedef struct { #define TRDC_DACFG_NMDAR_MASK (0xFU) #define TRDC_DACFG_NMDAR_SHIFT (0U) -/*! NMDAR - Number of master domain assignment registers for bus master m */ +/*! NMDAR - Number of initiator domain assignment registers for bus initiator m */ #define TRDC_DACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NMDAR_SHIFT)) & TRDC_DACFG_NMDAR_MASK) #define TRDC_DACFG_NCM_MASK (0x80U) #define TRDC_DACFG_NCM_SHIFT (7U) -/*! NCM - Non-CPU Master - * 0b0..Bus master is a processor. - * 0b1..Bus master is a non-processor. +/*! NCM - Non-CPU Initiator + * 0b0..Bus initiator is a processor. + * 0b1..Bus initiator is a non-processor. */ #define TRDC_DACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NCM_SHIFT)) & TRDC_DACFG_NCM_MASK) /*! @} */ @@ -499,42 +499,42 @@ typedef struct { #define TRDC_CFG_SLV0_NMBLK_MASK (0x3FFU) #define TRDC_CFG_SLV0_NMBLK_SHIFT (0U) -/*! SLV0_NMBLK - Number of blocks in slave 0. */ +/*! SLV0_NMBLK - Number of blocks in target 0. */ #define TRDC_CFG_SLV0_NMBLK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV0_NMBLK_SHIFT)) & TRDC_CFG_SLV0_NMBLK_MASK) #define TRDC_CFG_SLV2_NMBLK_MASK (0x3FFU) #define TRDC_CFG_SLV2_NMBLK_SHIFT (0U) -/*! SLV2_NMBLK - Number of blocks in slave 2. */ +/*! SLV2_NMBLK - Number of blocks in target 2. */ #define TRDC_CFG_SLV2_NMBLK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV2_NMBLK_SHIFT)) & TRDC_CFG_SLV2_NMBLK_MASK) #define TRDC_CFG_SLV0_BLKSZL2_MASK (0x7C00U) #define TRDC_CFG_SLV0_BLKSZL2_SHIFT (10U) -/*! SLV0_BLKSZL2 - Block size log2 in slave 0. */ +/*! SLV0_BLKSZL2 - Block size log2 in target 0. */ #define TRDC_CFG_SLV0_BLKSZL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV0_BLKSZL2_SHIFT)) & TRDC_CFG_SLV0_BLKSZL2_MASK) #define TRDC_CFG_SLV2_BLKSZL2_MASK (0x7C00U) #define TRDC_CFG_SLV2_BLKSZL2_SHIFT (10U) -/*! SLV2_BLKSZL2 - Block size log2 in slave 2. */ +/*! SLV2_BLKSZL2 - Block size log2 in target 2. */ #define TRDC_CFG_SLV2_BLKSZL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV2_BLKSZL2_SHIFT)) & TRDC_CFG_SLV2_BLKSZL2_MASK) #define TRDC_CFG_SLV1_NMBLK_MASK (0x3FF0000U) #define TRDC_CFG_SLV1_NMBLK_SHIFT (16U) -/*! SLV1_NMBLK - Number of blocks in slave 1. */ +/*! SLV1_NMBLK - Number of blocks in target 1. */ #define TRDC_CFG_SLV1_NMBLK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV1_NMBLK_SHIFT)) & TRDC_CFG_SLV1_NMBLK_MASK) #define TRDC_CFG_SLV3_NMBLK_MASK (0x3FF0000U) #define TRDC_CFG_SLV3_NMBLK_SHIFT (16U) -/*! SLV3_NMBLK - Number of blocks in slave 3. */ +/*! SLV3_NMBLK - Number of blocks in target 3. */ #define TRDC_CFG_SLV3_NMBLK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV3_NMBLK_SHIFT)) & TRDC_CFG_SLV3_NMBLK_MASK) #define TRDC_CFG_SLV1_BLKSZL2_MASK (0x7C000000U) #define TRDC_CFG_SLV1_BLKSZL2_SHIFT (26U) -/*! SLV1_BLKSZL2 - Block size log2 in slave 1. */ +/*! SLV1_BLKSZL2 - Block size log2 in target 1. */ #define TRDC_CFG_SLV1_BLKSZL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV1_BLKSZL2_SHIFT)) & TRDC_CFG_SLV1_BLKSZL2_MASK) #define TRDC_CFG_SLV3_BLKSZL2_MASK (0x7C000000U) #define TRDC_CFG_SLV3_BLKSZL2_SHIFT (26U) -/*! SLV3_BLKSZL2 - Block size log2 in slave 3. */ +/*! SLV3_BLKSZL2 - Block size log2 in target 3. */ #define TRDC_CFG_SLV3_BLKSZL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV3_BLKSZL2_SHIFT)) & TRDC_CFG_SLV3_BLKSZL2_MASK) /*! @} */ @@ -760,6 +760,26 @@ typedef struct { /*! EDID - Error domain identifier */ #define TRDC_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK) +#define TRDC_W1_SLV_DID_ERR_MASK (0x10U) +#define TRDC_W1_SLV_DID_ERR_SHIFT (4U) +/*! SLV_DID_ERR - DID check error */ +#define TRDC_W1_SLV_DID_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_DID_ERR_SHIFT)) & TRDC_W1_SLV_DID_ERR_MASK) + +#define TRDC_W1_SLV_PA_ERR_MASK (0x20U) +#define TRDC_W1_SLV_PA_ERR_SHIFT (5U) +/*! SLV_PA_ERR - Privilege attribute check error */ +#define TRDC_W1_SLV_PA_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_PA_ERR_SHIFT)) & TRDC_W1_SLV_PA_ERR_MASK) + +#define TRDC_W1_SLV_SA_ERR_MASK (0x40U) +#define TRDC_W1_SLV_SA_ERR_SHIFT (6U) +/*! SLV_SA_ERR - Secure attribute check error */ +#define TRDC_W1_SLV_SA_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_SA_ERR_SHIFT)) & TRDC_W1_SLV_SA_ERR_MASK) + +#define TRDC_W1_SLV_ABORT_MASK (0x80U) +#define TRDC_W1_SLV_ABORT_SHIFT (7U) +/*! SLV_ABORT - Bus protect error */ +#define TRDC_W1_SLV_ABORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_ABORT_SHIFT)) & TRDC_W1_SLV_ABORT_MASK) + #define TRDC_W1_EATR_MASK (0x700U) #define TRDC_W1_EATR_SHIFT (8U) /*! EATR - Error attributes @@ -839,6 +859,26 @@ typedef struct { /*! EDID - Error domain identifier */ #define TRDC_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK) +#define TRDC_W1_SLV_DID_ERR_MASK (0x10U) +#define TRDC_W1_SLV_DID_ERR_SHIFT (4U) +/*! SLV_DID_ERR - DID check error */ +#define TRDC_W1_SLV_DID_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_DID_ERR_SHIFT)) & TRDC_W1_SLV_DID_ERR_MASK) + +#define TRDC_W1_SLV_PA_ERR_MASK (0x20U) +#define TRDC_W1_SLV_PA_ERR_SHIFT (5U) +/*! SLV_PA_ERR - Privilege attribute check error */ +#define TRDC_W1_SLV_PA_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_PA_ERR_SHIFT)) & TRDC_W1_SLV_PA_ERR_MASK) + +#define TRDC_W1_SLV_SA_ERR_MASK (0x40U) +#define TRDC_W1_SLV_SA_ERR_SHIFT (6U) +/*! SLV_SA_ERR - Secure attribute check error */ +#define TRDC_W1_SLV_SA_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_SA_ERR_SHIFT)) & TRDC_W1_SLV_SA_ERR_MASK) + +#define TRDC_W1_SLV_ABORT_MASK (0x80U) +#define TRDC_W1_SLV_ABORT_SHIFT (7U) +/*! SLV_ABORT - Bus protect error */ +#define TRDC_W1_SLV_ABORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_W1_SLV_ABORT_SHIFT)) & TRDC_W1_SLV_ABORT_MASK) + #define TRDC_W1_EATR_MASK (0x700U) #define TRDC_W1_EATR_SHIFT (8U) /*! EATR - Error attributes @@ -893,7 +933,7 @@ typedef struct { /* The count of TRDC_W3 */ #define TRDC_MRC_DERR_W3_COUNT (1U) -/*! @name MDA_W0_0_DFMT0 - DAC Master Domain Assignment Register */ +/*! @name MDA_W0_0_DFMT0 - DAC Initiator Domain Assignment Register */ /*! @{ */ #define TRDC_MDA_W0_0_DFMT0_DID_MASK (0xFU) @@ -914,21 +954,13 @@ typedef struct { #define TRDC_MDA_W0_0_DFMT0_SA_MASK (0xC000U) #define TRDC_MDA_W0_0_DFMT0_SA_SHIFT (14U) /*! SA - Secure attribute - * 0b00..Force the bus attribute for this master to secure. - * 0b01..Force the bus attribute for this master to nonsecure. - * 0b10..Use the bus master's secure/nonsecure attribute directly. - * 0b11..Use the bus master's secure/nonsecure attribute directly. + * 0b00..Force the bus attribute for this initiator to secure. + * 0b01..Force the bus attribute for this initiator to nonsecure. + * 0b10..Use the bus initiator's secure/nonsecure attribute directly. + * 0b11..Use the bus initiator's secure/nonsecure attribute directly. */ #define TRDC_MDA_W0_0_DFMT0_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_SA_SHIFT)) & TRDC_MDA_W0_0_DFMT0_SA_MASK) -#define TRDC_MDA_W0_0_DFMT0_KPA_MASK (0x10000000U) -#define TRDC_MDA_W0_0_DFMT0_KPA_SHIFT (28U) -/*! KPA - Known Physical Address - * 0b0..The address is non-physical and requires SMMU translation. - * 0b1..The address is physical and bypasses any downstream SMMU. - */ -#define TRDC_MDA_W0_0_DFMT0_KPA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_KPA_SHIFT)) & TRDC_MDA_W0_0_DFMT0_KPA_MASK) - #define TRDC_MDA_W0_0_DFMT0_DFMT_MASK (0x20000000U) #define TRDC_MDA_W0_0_DFMT0_DFMT_SHIFT (29U) /*! DFMT - Domain format @@ -954,7 +986,7 @@ typedef struct { #define TRDC_MDA_W0_0_DFMT0_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_VLD_SHIFT)) & TRDC_MDA_W0_0_DFMT0_VLD_MASK) /*! @} */ -/*! @name MDA_W0_x_DFMT1 - DAC Master Domain Assignment Register */ +/*! @name MDA_W0_x_DFMT1 - DAC Initiator Domain Assignment Register */ /*! @{ */ #define TRDC_MDA_W0_x_DFMT1_DID_MASK (0xFU) @@ -965,20 +997,20 @@ typedef struct { #define TRDC_MDA_W0_x_DFMT1_PA_MASK (0x30U) #define TRDC_MDA_W0_x_DFMT1_PA_SHIFT (4U) /*! PA - Privileged attribute - * 0b00..Force the bus attribute for this master to user. - * 0b01..Force the bus attribute for this master to privileged. - * 0b10..Use the bus master's privileged/user attribute directly. - * 0b11..Use the bus master's privileged/user attribute directly. + * 0b00..Force the bus attribute for this initiator to user. + * 0b01..Force the bus attribute for this initiator to privileged. + * 0b10..Use the bus initiator's privileged/user attribute directly. + * 0b11..Use the bus initiator's privileged/user attribute directly. */ #define TRDC_MDA_W0_x_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_PA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_PA_MASK) #define TRDC_MDA_W0_x_DFMT1_SA_MASK (0xC0U) #define TRDC_MDA_W0_x_DFMT1_SA_SHIFT (6U) /*! SA - Secure attribute - * 0b00..Force the bus attribute for this master to secure. - * 0b01..Force the bus attribute for this master to nonsecure. - * 0b10..Use the bus master's secure/nonsecure attribute directly. - * 0b11..Use the bus master's secure/nonsecure attribute directly. + * 0b00..Force the bus attribute for this initiator to secure. + * 0b01..Force the bus attribute for this initiator to nonsecure. + * 0b10..Use the bus initiator's secure/nonsecure attribute directly. + * 0b11..Use the bus initiator's secure/nonsecure attribute directly. */ #define TRDC_MDA_W0_x_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_SA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_SA_MASK) @@ -990,14 +1022,6 @@ typedef struct { */ #define TRDC_MDA_W0_x_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_DIDB_SHIFT)) & TRDC_MDA_W0_x_DFMT1_DIDB_MASK) -#define TRDC_MDA_W0_x_DFMT1_KPA_MASK (0x10000000U) -#define TRDC_MDA_W0_x_DFMT1_KPA_SHIFT (28U) -/*! KPA - Known Physical Address - * 0b0..The address is non-physical and requires SMMU translation. - * 0b1..The address is physical and bypasses any downstream SMMU. - */ -#define TRDC_MDA_W0_x_DFMT1_KPA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_KPA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_KPA_MASK) - #define TRDC_MDA_W0_x_DFMT1_DFMT_MASK (0x20000000U) #define TRDC_MDA_W0_x_DFMT1_DFMT_SHIFT (29U) /*! DFMT - Domain format diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TRGMUX.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TRGMUX.h index 504769ba7..4b83fd5ca 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TRGMUX.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TRGMUX.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TRGMUX diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TSTMR.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TSTMR.h index f8f675db7..417624635 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TSTMR.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TSTMR.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TSTMR diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TX_PACKET_RAM.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TX_PACKET_RAM.h index 97a7cbf39..cf3ce4dce 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TX_PACKET_RAM.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_TX_PACKET_RAM.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for TX_PACKET_RAM diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_UART.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_UART.h index 8bd890e6a..e1c967645 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_UART.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_UART.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for UART diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_UART_PFU.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_UART_PFU.h index 1060641ab..9e8a71e1c 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_UART_PFU.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_UART_PFU.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for UART_PFU diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_VBAT.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_VBAT.h index fc93b243a..95840a1ab 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_VBAT.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_VBAT.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for VBAT diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_VREF.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_VREF.h index 70ac0aafd..bda498002 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_VREF.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_VREF.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for VREF @@ -266,7 +266,7 @@ typedef struct { #define VREF_UTRIM_TRIM2V1_MASK (0xFU) #define VREF_UTRIM_TRIM2V1_SHIFT (0U) -/*! TRIM2V1 - VREF 2.1 V Trim */ +/*! TRIM2V1 - VREF 2.048 V Trim */ #define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) #define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WDOG.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WDOG.h index de147768d..bf8d2d8d5 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WDOG.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WDOG.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for WDOG diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WOR.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WOR.h index a3bbd5b31..d61e66fc7 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WOR.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WOR.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for WOR diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WUU.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WUU.h index 6ca44ff17..50c119ebc 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WUU.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_WUU.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for WUU diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_ANALOG.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_ANALOG.h index b6e4397ef..f63e5f876 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_ANALOG.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_ANALOG.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_ANALOG @@ -505,8 +505,8 @@ typedef struct { /*! PLL_PD_TRIM_FCAL_BIAS - reg_pd_trim_fcal_bias_dig[1:0] * 0b00..0.276V (recommended setting for legacy operation) * 0b01..0.164V - * 0b10..0.320V - * 0b11..0.391V (recommended setting for PIC use) + * 0b10..0.320V (recommended setting for PIC use) + * 0b11..0.391V */ #define XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS_SHIFT)) & XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS_MASK) diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_MISC.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_MISC.h index 6d1d0fdda..57493d5d8 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_MISC.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_MISC.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_MISC diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_PLL_DIG.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_PLL_DIG.h index bec8fbc94..a4fda5aa7 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_PLL_DIG.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_PLL_DIG.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_PLL_DIG @@ -1196,6 +1196,11 @@ typedef struct { #define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_SHIFT (24U) /*! HPM_INTEGER_DELAY_DRS - DRS HPM_SDM_DELAY */ #define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_MASK) + +#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS_MASK (0xF0000000U) +#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS_SHIFT (28U) +/*! HPM_COUNT_ADJUST_DRS - HPM_COUNT_ADJUST_DRS */ +#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_COUNT_ADJUST_DRS_MASK) /*! @} */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_RX_DIG.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_RX_DIG.h index 7d07f0c70..aa5cde779 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_RX_DIG.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_RX_DIG.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_RX_DIG @@ -234,6 +234,10 @@ typedef struct { __IO uint32_t CTRL2; /**< RXDIG Control 2, offset: 0x184 */ __IO uint32_t NADM_CTRL; /**< Controls for the NADM module, offset: 0x188 */ __I uint32_t NADM_RES; /**< NADM latest packet results., offset: 0x18C */ + __IO uint32_t FCFO_CTRL; /**< Fine CFO module controls., offset: 0x190 */ + __IO uint32_t FCFO_TN; /**< Tone parameters., offset: 0x194 */ + __IO uint32_t FCFO_TN_PH; /**< F2 carrier iq phases, offset: 0x198 */ + __I uint32_t FCFO_RES; /**< Fine CFO results., offset: 0x19C */ } XCVR_RX_DIG_Type; /* ---------------------------------------------------------------------------- @@ -3260,10 +3264,12 @@ typedef struct { #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_MASK (0xFFFFU) #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_SHIFT (0U) +/*! rx_tone_ana_out_q - Accumulator Q path result. */ #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_MASK) #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_MASK (0xFFFF0000U) #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_SHIFT (16U) +/*! rx_tone_ana_out_i - Accumulator I path result */ #define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_MASK) /*! @} */ @@ -3335,7 +3341,7 @@ typedef struct { #define XCVR_RX_DIG_TQI_CTRL_TQI_EN_MASK (0x10000U) #define XCVR_RX_DIG_TQI_CTRL_TQI_EN_SHIFT (16U) -/*! TQI_EN +/*! TQI_EN - Enables TQI operation. * 0b0..TQI operation is disabled. * 0b1..TQI operation is enabled. */ @@ -3413,6 +3419,16 @@ typedef struct { #define XCVR_RX_DIG_NADM_CTRL_NADM_FIR_LATENCY_SHIFT (17U) /*! NADM_FIR_LATENCY - FM correlator path, delay between reference start and correlator start. */ #define XCVR_RX_DIG_NADM_CTRL_NADM_FIR_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NADM_CTRL_NADM_FIR_LATENCY_SHIFT)) & XCVR_RX_DIG_NADM_CTRL_NADM_FIR_LATENCY_MASK) + +#define XCVR_RX_DIG_NADM_CTRL_NADM_SIZE_MASK (0x1C00000U) +#define XCVR_RX_DIG_NADM_CTRL_NADM_SIZE_SHIFT (22U) +/*! NADM_SIZE - NADM size aligned on RTT_TYPE standard value */ +#define XCVR_RX_DIG_NADM_CTRL_NADM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NADM_CTRL_NADM_SIZE_SHIFT)) & XCVR_RX_DIG_NADM_CTRL_NADM_SIZE_MASK) + +#define XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE_MASK (0xE000000U) +#define XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE_SHIFT (25U) +/*! NADM_IDX_CAPTURE - Index used to get optimum fm_diff in DMA_DBG */ +#define XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE_SHIFT)) & XCVR_RX_DIG_NADM_CTRL_NADM_IDX_CAPTURE_MASK) /*! @} */ /*! @name NADM_RES - NADM latest packet results. */ @@ -3429,6 +3445,122 @@ typedef struct { #define XCVR_RX_DIG_NADM_RES_NADM_INST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NADM_RES_NADM_INST_SHIFT)) & XCVR_RX_DIG_NADM_RES_NADM_INST_MASK) /*! @} */ +/*! @name FCFO_CTRL - Fine CFO module controls. */ +/*! @{ */ + +#define XCVR_RX_DIG_FCFO_CTRL_A_MUL_MASK (0xFFU) +#define XCVR_RX_DIG_FCFO_CTRL_A_MUL_SHIFT (0U) +/*! A_MUL - Alpha linear multiplication coeficient */ +#define XCVR_RX_DIG_FCFO_CTRL_A_MUL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_A_MUL_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_A_MUL_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_A_DIV_MASK (0xF000U) +#define XCVR_RX_DIG_FCFO_CTRL_A_DIV_SHIFT (12U) +/*! A_DIV - Alpha linear division coeficient */ +#define XCVR_RX_DIG_FCFO_CTRL_A_DIV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_A_DIV_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_A_DIV_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA_MASK (0x10000U) +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA_SHIFT (16U) +/*! FCFO_ENA - Enables FCFO module. + * 0b0..Fcfo algorithm disabled. + * 0b1..Fcfo algorithm enabled. + */ +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_FCFO_ENA_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_OUT_IQ_MASK (0x40000U) +#define XCVR_RX_DIG_FCFO_CTRL_OUT_IQ_SHIFT (18U) +/*! OUT_IQ - FCFO output format. + * 0b0..Fcfo output are g function values (previous/current). + * 0b1..Fcfo output are IQ values. + */ +#define XCVR_RX_DIG_FCFO_CTRL_OUT_IQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_OUT_IQ_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_OUT_IQ_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC_MASK (0x300000U) +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC_SHIFT (20U) +/*! TRIG_SRC - Selects FCFO trigger source. + * 0b00..Selects TPM as trigger source + * 0b01..Selects TFM as trigger source + * 0b10..Selects software as trigger source. + */ +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_TRIG_SRC_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY_MASK (0x3000000U) +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY_SHIFT (24U) +/*! TRIG_DLY - Delay between trigger and fcfo start. + * 0b00..Selects 2us trigger delay. + * 0b01..Selects 5us trigger delay. + * 0b10..Selects 10us trigger delay. + * 0b11..Selects 15us trigger delay. + */ +#define XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_TRIG_DLY_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_A_OVF_MASK (0x10000000U) +#define XCVR_RX_DIG_FCFO_CTRL_A_OVF_SHIFT (28U) +/*! A_OVF - Alpha multiplier overflow. */ +#define XCVR_RX_DIG_FCFO_CTRL_A_OVF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_A_OVF_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_A_OVF_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR_MASK (0x20000000U) +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR_SHIFT (29U) +/*! FCFO_ERR - FCFO value error. */ +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_FCFO_ERR_MASK) + +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE_MASK (0x40000000U) +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE_SHIFT (30U) +/*! FCFO_DONE - FCFO done. */ +#define XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE_SHIFT)) & XCVR_RX_DIG_FCFO_CTRL_FCFO_DONE_MASK) +/*! @} */ + +/*! @name FCFO_TN - Tone parameters. */ +/*! @{ */ + +#define XCVR_RX_DIG_FCFO_TN_TN_F1_INC_MASK (0x7FU) +#define XCVR_RX_DIG_FCFO_TN_TN_F1_INC_SHIFT (0U) +/*! TN_F1_INC - Tone F1 increment. */ +#define XCVR_RX_DIG_FCFO_TN_TN_F1_INC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_TN_F1_INC_SHIFT)) & XCVR_RX_DIG_FCFO_TN_TN_F1_INC_MASK) + +#define XCVR_RX_DIG_FCFO_TN_TN_F1_DIV_MASK (0x700U) +#define XCVR_RX_DIG_FCFO_TN_TN_F1_DIV_SHIFT (8U) +/*! TN_F1_DIV - Tone F1 clock divisor. */ +#define XCVR_RX_DIG_FCFO_TN_TN_F1_DIV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_TN_F1_DIV_SHIFT)) & XCVR_RX_DIG_FCFO_TN_TN_F1_DIV_MASK) + +#define XCVR_RX_DIG_FCFO_TN_TN_F2_INC_MASK (0x7F0000U) +#define XCVR_RX_DIG_FCFO_TN_TN_F2_INC_SHIFT (16U) +/*! TN_F2_INC - Tone F2 increment. */ +#define XCVR_RX_DIG_FCFO_TN_TN_F2_INC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_TN_F2_INC_SHIFT)) & XCVR_RX_DIG_FCFO_TN_TN_F2_INC_MASK) + +#define XCVR_RX_DIG_FCFO_TN_TN_F2_DIV_MASK (0x7000000U) +#define XCVR_RX_DIG_FCFO_TN_TN_F2_DIV_SHIFT (24U) +/*! TN_F2_DIV - Tone F2 clock divisor. */ +#define XCVR_RX_DIG_FCFO_TN_TN_F2_DIV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_TN_F2_DIV_SHIFT)) & XCVR_RX_DIG_FCFO_TN_TN_F2_DIV_MASK) +/*! @} */ + +/*! @name FCFO_TN_PH - F2 carrier iq phases */ +/*! @{ */ + +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I_MASK (0x1FFU) +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I_SHIFT (0U) +/*! F2_PH_I - F2 carrier I start phase */ +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I_SHIFT)) & XCVR_RX_DIG_FCFO_TN_PH_F2_PH_I_MASK) + +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q_MASK (0x1FF0000U) +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q_SHIFT (16U) +/*! F2_PH_Q - F2 carrier Q start phase */ +#define XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q_SHIFT)) & XCVR_RX_DIG_FCFO_TN_PH_F2_PH_Q_MASK) +/*! @} */ + +/*! @name FCFO_RES - Fine CFO results. */ +/*! @{ */ + +#define XCVR_RX_DIG_FCFO_RES_G_CUR_MASK (0xFFFFU) +#define XCVR_RX_DIG_FCFO_RES_G_CUR_SHIFT (0U) +/*! G_CUR - g function, current value. */ +#define XCVR_RX_DIG_FCFO_RES_G_CUR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_RES_G_CUR_SHIFT)) & XCVR_RX_DIG_FCFO_RES_G_CUR_MASK) + +#define XCVR_RX_DIG_FCFO_RES_G_PRV_MASK (0xFFFF0000U) +#define XCVR_RX_DIG_FCFO_RES_G_PRV_SHIFT (16U) +/*! G_PRV - g function, previous value. */ +#define XCVR_RX_DIG_FCFO_RES_G_PRV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_FCFO_RES_G_PRV_SHIFT)) & XCVR_RX_DIG_FCFO_RES_G_PRV_MASK) +/*! @} */ + /*! * @} diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_TSM.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_TSM.h index f415ee9fb..cd1f25858 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_TSM.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_TSM.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_TSM diff --git a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_TX_DIG.h b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_TX_DIG.h index eafc07e6d..ddc8fa43d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_TX_DIG.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/KW/periph6/PERI_XCVR_TX_DIG.h @@ -20,7 +20,7 @@ ** KW47Z420B3AFTA ** ** Version: rev. 2.0, 2024-10-29 -** Build: b250522 +** Build: b250730 ** ** Abstract: ** CMSIS Peripheral Access Layer for XCVR_TX_DIG diff --git a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/RW610_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/RW610_COMMON.h index 7053a8cfd..adfb8170d 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/RW610_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/RW610_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: RW61X User manual Rev. 0.95, June 2022 ** Version: rev. 3.0, 2025-04-07 -** Build: b250519 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for RW610 @@ -1222,35 +1222,35 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x38000000u, 0x58000000u} } -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x28000000u, 0x48000000u} } -/* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x3FFFFFFFu, 0x5FFFFFFFu} } -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x2FFFFFFFu, 0x4FFFFFFFu} } -/** FlexSPI AMBA Cache0 address. */ -#define FlexSPI_AMBA_PC_CACHE_BASE (0x18000000u) -/** FlexSPI AMBA Cache1 address. */ -#define FlexSPI_AMBA_PS_CACHE_BASE (0x38000000u) -/** FlexSPI AMBA Non-Cache address. */ -#define FlexSPI_AMBA_PS_NCACHE_BASE (0x58000000u) -/** FlexSPI AMBA Cache0 address */ -#define FlexSPI_AMBA_PC_CACHE_BASE_NS (0x08000000u) -/** FlexSPI AMBA Cache1 address */ -#define FlexSPI_AMBA_PS_CACHE_BASE_NS (0x28000000u) -/** FlexSPI AMBA Non-Cache address */ -#define FlexSPI_AMBA_PS_NCACHE_BASE_NS (0x48000000u) -#else -/* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x28000000u, 0x48000000u} } -/* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x2FFFFFFFu, 0x4FFFFFFFu} } -/** FlexSPI AMBA Cache0 address. */ -#define FlexSPI_AMBA_PC_CACHE_BASE (0x08000000u) -/** FlexSPI AMBA Cache1 address. */ -#define FlexSPI_AMBA_PS_CACHE_BASE (0x28000000u) -/** FlexSPI AMBA Non-cache address. */ -#define FlexSPI_AMBA_PS_NCACHE_BASE (0x48000000u) + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x38000000u, 0x58000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x28000000u, 0x48000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x3FFFFFFFu, 0x5FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x2FFFFFFFu, 0x4FFFFFFFu} } + /** FlexSPI AMBA Cache0 address. */ + #define FlexSPI_AMBA_PC_CACHE_BASE (0x18000000u) + /** FlexSPI AMBA Cache1 address. */ + #define FlexSPI_AMBA_PS_CACHE_BASE (0x38000000u) + /** FlexSPI AMBA Non-Cache address. */ + #define FlexSPI_AMBA_PS_NCACHE_BASE (0x58000000u) + /** FlexSPI AMBA Cache0 address */ + #define FlexSPI_AMBA_PC_CACHE_BASE_NS (0x08000000u) + /** FlexSPI AMBA Cache1 address */ + #define FlexSPI_AMBA_PS_CACHE_BASE_NS (0x28000000u) + /** FlexSPI AMBA Non-Cache address */ + #define FlexSPI_AMBA_PS_NCACHE_BASE_NS (0x48000000u) +#else + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x28000000u, 0x48000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x2FFFFFFFu, 0x4FFFFFFFu} } + /** FlexSPI AMBA Cache0 address. */ + #define FlexSPI_AMBA_PC_CACHE_BASE (0x08000000u) + /** FlexSPI AMBA Cache1 address. */ + #define FlexSPI_AMBA_PS_CACHE_BASE (0x28000000u) + /** FlexSPI AMBA Non-cache address. */ + #define FlexSPI_AMBA_PS_NCACHE_BASE (0x48000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/RW610_features.h b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/RW610_features.h index a4184ef6f..fe0a681a2 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/RW610_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/RW610_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-03-16 -** Build: b250512 +** Build: b250815 ** ** Abstract: ** Chip specific module features. @@ -172,11 +172,6 @@ /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (1) -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - /* CTIMER module features */ /* @brief CTIMER has no capture channel. */ @@ -237,7 +232,7 @@ /* @brief Has Additional 1588 Timer Channel Interrupt. */ #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) /* @brief Support Interrupt Coalesce for each instance */ -#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0) +#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1) /* @brief Queue Size for each instance. */ #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1) /* @brief Has AVB Support for each instance. */ @@ -250,11 +245,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ +#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (1) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -313,28 +310,60 @@ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) -/* @brief FlexSPI has no IP parallel mode */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) -/* @brief FlexSPI has no AHB parallel mode */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) -/* @brief FlexSPI support address shift */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) /* @brief FlexSPI support sample clock source selection */ #define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) /* @brief FlexSPI support sample clock source or source_b selection */ #define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) -/* @brief FlexSPI AHB RX buffer size (byte) */ -#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI IPED REGION COUNT */ #define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (15) -/* @brief FlexSPI Array Length */ -#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* ADC module features */ @@ -411,6 +440,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SPI module features */ @@ -466,6 +497,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) /* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _RW610_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/drivers/fsl_power.c b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/drivers/fsl_power.c index 6ff483e0b..947166f79 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/drivers/fsl_power.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW610/drivers/fsl_power.c @@ -711,7 +711,7 @@ void POWER_ConfigCauInSleep(bool pdCau) } else { - CAU->PD_CTRL_ONE_REG &= ~CAU_PD_CTRL_ONE_REG_SLPBIAS_PD_MASK; + CAU->PD_CTRL_ONE_REG &= (uint8_t)((~CAU_PD_CTRL_ONE_REG_SLPBIAS_PD_MASK) & 0xFFU); CAU->SLP_CTRL_ONE_REG = 0x9EU; CAU->SLP_CTRL_TWO_REG = 0x6AU; } @@ -1264,7 +1264,7 @@ void POWER_InitVoltage(uint32_t dro, uint32_t pack) SystemCoreClockUpdate(); /* LPBG trim */ - BUCK11->BUCK_CTRL_EIGHTEEN_REG &= ~BUCK11_BUCK_CTRL_EIGHTEEN_REG_LPBG_TRIM_MASK; + BUCK11->BUCK_CTRL_EIGHTEEN_REG &= (uint8_t)((~BUCK11_BUCK_CTRL_EIGHTEEN_REG_LPBG_TRIM_MASK) & 0xFFU); if (dro == 0U) { /* Boot voltage 1.11V */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/RW612_COMMON.h b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/RW612_COMMON.h index 2321f4f35..ce69ef8c5 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/RW612_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/RW612_COMMON.h @@ -11,7 +11,7 @@ ** ** Reference manual: RW61X User manual Rev. 0.95, June 2022 ** Version: rev. 3.0, 2025-04-07 -** Build: b250519 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for RW612 @@ -1222,35 +1222,35 @@ typedef enum IRQn { /** FlexSPI AMBA memory base alias count */ #define FLEXSPI_AMBA_BASE_ALIAS_COUNT (3) #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) -/* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x38000000u, 0x58000000u} } -#define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x28000000u, 0x48000000u} } -/* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x3FFFFFFFu, 0x5FFFFFFFu} } -#define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x2FFFFFFFu, 0x4FFFFFFFu} } -/** FlexSPI AMBA Cache0 address. */ -#define FlexSPI_AMBA_PC_CACHE_BASE (0x18000000u) -/** FlexSPI AMBA Cache1 address. */ -#define FlexSPI_AMBA_PS_CACHE_BASE (0x38000000u) -/** FlexSPI AMBA Non-Cache address. */ -#define FlexSPI_AMBA_PS_NCACHE_BASE (0x58000000u) -/** FlexSPI AMBA Cache0 address */ -#define FlexSPI_AMBA_PC_CACHE_BASE_NS (0x08000000u) -/** FlexSPI AMBA Cache1 address */ -#define FlexSPI_AMBA_PS_CACHE_BASE_NS (0x28000000u) -/** FlexSPI AMBA Non-Cache address */ -#define FlexSPI_AMBA_PS_NCACHE_BASE_NS (0x48000000u) -#else -/* FlexSPI AMBA base address array. */ -#define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x28000000u, 0x48000000u} } -/* FlexSPI AMBA end address array. */ -#define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x2FFFFFFFu, 0x4FFFFFFFu} } -/** FlexSPI AMBA Cache0 address. */ -#define FlexSPI_AMBA_PC_CACHE_BASE (0x08000000u) -/** FlexSPI AMBA Cache1 address. */ -#define FlexSPI_AMBA_PS_CACHE_BASE (0x28000000u) -/** FlexSPI AMBA Non-cache address. */ -#define FlexSPI_AMBA_PS_NCACHE_BASE (0x48000000u) + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x18000000u, 0x38000000u, 0x58000000u} } + #define FlexSPI_AMBA_BASE_ARRAY_NS { {0x08000000u, 0x28000000u, 0x48000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x1FFFFFFFu, 0x3FFFFFFFu, 0x5FFFFFFFu} } + #define FlexSPI_AMBA_END_ARRAY_NS { {0x0FFFFFFFu, 0x2FFFFFFFu, 0x4FFFFFFFu} } + /** FlexSPI AMBA Cache0 address. */ + #define FlexSPI_AMBA_PC_CACHE_BASE (0x18000000u) + /** FlexSPI AMBA Cache1 address. */ + #define FlexSPI_AMBA_PS_CACHE_BASE (0x38000000u) + /** FlexSPI AMBA Non-Cache address. */ + #define FlexSPI_AMBA_PS_NCACHE_BASE (0x58000000u) + /** FlexSPI AMBA Cache0 address */ + #define FlexSPI_AMBA_PC_CACHE_BASE_NS (0x08000000u) + /** FlexSPI AMBA Cache1 address */ + #define FlexSPI_AMBA_PS_CACHE_BASE_NS (0x28000000u) + /** FlexSPI AMBA Non-Cache address */ + #define FlexSPI_AMBA_PS_NCACHE_BASE_NS (0x48000000u) +#else + /* FlexSPI AMBA base address array. */ + #define FlexSPI_AMBA_BASE_ARRAY { {0x08000000u, 0x28000000u, 0x48000000u} } + /* FlexSPI AMBA end address array. */ + #define FlexSPI_AMBA_END_ARRAY { {0x0FFFFFFFu, 0x2FFFFFFFu, 0x4FFFFFFFu} } + /** FlexSPI AMBA Cache0 address. */ + #define FlexSPI_AMBA_PC_CACHE_BASE (0x08000000u) + /** FlexSPI AMBA Cache1 address. */ + #define FlexSPI_AMBA_PS_CACHE_BASE (0x28000000u) + /** FlexSPI AMBA Non-cache address. */ + #define FlexSPI_AMBA_PS_NCACHE_BASE (0x48000000u) #endif diff --git a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/RW612_features.h b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/RW612_features.h index 725e23bd6..c1dced6d5 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/RW612_features.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/RW612_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-03-16 -** Build: b250512 +** Build: b250815 ** ** Abstract: ** Chip specific module features. @@ -172,11 +172,6 @@ /* @brief CDOG Load default configurations during init function */ #define FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF (1) -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - /* CTIMER module features */ /* @brief CTIMER has no capture channel. */ @@ -237,7 +232,7 @@ /* @brief Has Additional 1588 Timer Channel Interrupt. */ #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) /* @brief Support Interrupt Coalesce for each instance */ -#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0) +#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1) /* @brief Queue Size for each instance. */ #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1) /* @brief Has AVB Support for each instance. */ @@ -250,11 +245,13 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) -/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +/* @brief Has transfer clock delay (register bit field ECR[TXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) -/* @brief ENET Has Extra Clock Gate.(RW610). */ +/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ +#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) +/* @brief ENET Has Extra Clock Gate (RW610). */ #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (1) /* @brief ENET support reset. */ #define FSL_FEATURE_ENET_HAS_RSTCTL (1) @@ -313,28 +310,60 @@ /* @brief FlexSPI AHB buffer count */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) /* @brief FlexSPI has no MCR0 ARDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) /* @brief FlexSPI has no MCR0 ATDFEN bit */ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) -/* @brief FlexSPI has no IP parallel mode */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) -/* @brief FlexSPI has no AHB parallel mode */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) -/* @brief FlexSPI support address shift */ -#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (1) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (0) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (0) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (0) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (0) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) +/* @brief FlexSPI has no STS2 BSLVLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK (0) +/* @brief FlexSPI has no STS2 BREFLOCK bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK (0) +/* @brief FlexSPI supports Port A only, do not support Port B. */ +#define FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB (0) +/* @brief FlexSPI LUTKEY is read only. */ +#define FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO (0) +/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */ +#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief FlexSPI DMA needs multiple DES to transfer */ +#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (0) +/* @brief FlexSPI uses min DQS delay */ +#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (0) /* @brief FlexSPI support sample clock source selection */ #define FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB (1) /* @brief FlexSPI support sample clock source or source_b selection */ #define FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF (1) -/* @brief FlexSPI AHB RX buffer size (byte) */ -#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* @brief FlexSPI IPED REGION COUNT */ #define FSL_FEATURE_FLEXSPI_IPED_REGION_COUNT (15) -/* @brief FlexSPI Array Length */ -#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) /* @brief FlexSPI Has ERRATA052733 */ #define FSL_FEATURE_FLEXSPI_HAS_ERRATA_052733 (1) +/* @brief FlexSPI Has ERRATA051426 */ +#define FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426 (0) +/* @brief FlexSPI has AHBCR RESUMEDISABLE bit */ +#define FSL_FEATURE_FLEXSPI_HAS_RESUMEDISABLE_BIT_CONFIG_SUPPORT (1) /* ADC module features */ @@ -411,6 +440,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) /* @brief Number of outputs */ #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) +/* @brief Writing a zero asserts the SCT reset. */ +#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (0) /* SPI module features */ @@ -466,6 +497,10 @@ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0) /* @brief WWDT does not support power down configure. */ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) +/* @brief Has LPOSC as clock source. */ +#define FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE (0) +/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */ +#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (0) #endif /* _RW612_FEATURES_H_ */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/drivers/fsl_power.c b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/drivers/fsl_power.c index 6ff483e0b..947166f79 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/drivers/fsl_power.c +++ b/mcux/mcux-sdk-ng/devices/Wireless/RW/RW612/drivers/fsl_power.c @@ -711,7 +711,7 @@ void POWER_ConfigCauInSleep(bool pdCau) } else { - CAU->PD_CTRL_ONE_REG &= ~CAU_PD_CTRL_ONE_REG_SLPBIAS_PD_MASK; + CAU->PD_CTRL_ONE_REG &= (uint8_t)((~CAU_PD_CTRL_ONE_REG_SLPBIAS_PD_MASK) & 0xFFU); CAU->SLP_CTRL_ONE_REG = 0x9EU; CAU->SLP_CTRL_TWO_REG = 0x6AU; } @@ -1264,7 +1264,7 @@ void POWER_InitVoltage(uint32_t dro, uint32_t pack) SystemCoreClockUpdate(); /* LPBG trim */ - BUCK11->BUCK_CTRL_EIGHTEEN_REG &= ~BUCK11_BUCK_CTRL_EIGHTEEN_REG_LPBG_TRIM_MASK; + BUCK11->BUCK_CTRL_EIGHTEEN_REG &= (uint8_t)((~BUCK11_BUCK_CTRL_EIGHTEEN_REG_LPBG_TRIM_MASK) & 0xFFU); if (dro == 0U) { /* Boot voltage 1.11V */ diff --git a/mcux/mcux-sdk-ng/devices/Wireless/RW/periph/PERI_FLEXSPI.h b/mcux/mcux-sdk-ng/devices/Wireless/RW/periph/PERI_FLEXSPI.h index b8ae7b4a3..4a4d7cd07 100644 --- a/mcux/mcux-sdk-ng/devices/Wireless/RW/periph/PERI_FLEXSPI.h +++ b/mcux/mcux-sdk-ng/devices/Wireless/RW/periph/PERI_FLEXSPI.h @@ -8,7 +8,7 @@ ** RW612UKA2I ** ** Version: rev. 3.0, 2025-04-07 -** Build: b250519 +** Build: b250619 ** ** Abstract: ** CMSIS Peripheral Access Layer for FLEXSPI @@ -91,11 +91,11 @@ */ /** FLEXSPI - Size of Registers Arrays */ -#define FLEXSPI_AHBRXBUFXCR0_COUNT 8u -#define FLEXSPI_FLSHXCR0_COUNT 4u -#define FLEXSPI_FLSHXCR1_COUNT 4u -#define FLEXSPI_FLSHXCR2_COUNT 4u -#define FLEXSPI_DLLXCR_COUNT 2u +#define FLEXSPI_AHBRXBUFCR0_COUNT 8u +#define FLEXSPI_FLSHCR0_COUNT 4u +#define FLEXSPI_FLSHCR1_COUNT 4u +#define FLEXSPI_FLSHCR2_COUNT 4u +#define FLEXSPI_DLLCR_COUNT 2u #define FLEXSPI_RFDR_COUNT 32u #define FLEXSPI_TFDR_COUNT 32u #define FLEXSPI_LUT_COUNT 64u @@ -111,11 +111,11 @@ typedef struct { __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFXCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ + __IO uint32_t AHBRXBUFCR0[FLEXSPI_AHBRXBUFCR0_COUNT]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; - __IO uint32_t FLSHCR0[FLEXSPI_FLSHXCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[FLEXSPI_FLSHXCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[FLEXSPI_FLSHXCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR0[FLEXSPI_FLSHCR0_COUNT]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[FLEXSPI_FLSHCR1_COUNT]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[FLEXSPI_FLSHCR2_COUNT]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; @@ -127,7 +127,7 @@ typedef struct { __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */ __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[FLEXSPI_DLLXCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DLLCR[FLEXSPI_DLLCR_COUNT]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ @@ -740,9 +740,6 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) - /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ @@ -770,9 +767,6 @@ typedef struct { #define FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ @@ -814,9 +808,6 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ @@ -872,9 +863,6 @@ typedef struct { #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ @@ -1069,9 +1057,6 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - /*! @name STS0 - Status Register 0 */ /*! @{ */ From d58d1348d3f64b0dc3f270d4a46db54e3789e2bb Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 14:59:00 +0800 Subject: [PATCH 10/21] hal_nxp: mcux-sdk-ng: Update components to SDK 25.09.00 Signed-off-by: Zhaoxiang Jin --- .../components/conn_fwloader/CMakeLists.txt | 3 +- .../conn_fwloader/fsl_loader_utils.c | 2 +- .../components/conn_fwloader/readme.txt | 10 +- .../flash/mflash/frdmrw612/mflash_drv.c | 19 ++ .../flash/mflash/mcxe3x/CMakeLists.txt | 24 +++ .../flash/mflash/mcxe3x/mflash_drv.c | 138 +++++++++++++ .../flash/mflash/mcxe3x/mflash_drv.h | 26 +++ .../flash/mflash/mcxw71/CMakeLists.txt | 24 +++ .../flash/mflash/mcxw71/mflash_drv.c | 134 ++++++++++++ .../flash/mflash/mcxw71/mflash_drv.h | 26 +++ .../flash/mflash/mimxrt1021/mflash_drv.c | 10 +- .../flash/mflash/mimxrt1062/mflash_drv.c | 7 + .../flash/mflash/mimxrt1160/mflash_drv.c | 10 +- .../flash/nor/flexspi/fsl_flexspi_nor_flash.c | 27 ++- .../components/flash/nor/fsl_nor_flash.h | 10 +- .../flash/nor/spifi/fsl_spifi_nor_flash.c | 191 ++++++++++++++++-- .../flash/nor/spifi/fsl_spifi_nor_flash.h | 32 ++- .../flash/nor/xspi/fsl_xspi_nor_flash.c | 27 ++- .../components/misc_utilities/CMakeLists.txt | 6 +- .../components/misc_utilities/fsl_incbin.S | 26 ++- .../components/osa/fsl_os_abstraction.h | 4 +- .../components/osa/fsl_os_abstraction_bm.c | 43 ++-- .../osa/fsl_os_abstraction_free_rtos.c | 80 +++++--- .../osa/fsl_os_abstraction_threadx.c | 52 +++-- .../phy/device/phyyt8521/fsl_phyyt8521.c | 34 +++- .../components/rpmsg/fsl_adapter_rpmsg.c | 4 + .../components/wifi_bt_module/CMakeLists.txt | 28 ++- .../incl/wifi_bt_module_config.h | 11 + 28 files changed, 877 insertions(+), 131 deletions(-) create mode 100644 mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/CMakeLists.txt create mode 100644 mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/mflash_drv.c create mode 100644 mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/mflash_drv.h create mode 100644 mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/CMakeLists.txt create mode 100644 mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/mflash_drv.c create mode 100644 mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/mflash_drv.h diff --git a/mcux/mcux-sdk-ng/components/conn_fwloader/CMakeLists.txt b/mcux/mcux-sdk-ng/components/conn_fwloader/CMakeLists.txt index 0e107d777..9e5c07463 100644 --- a/mcux/mcux-sdk-ng/components/conn_fwloader/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/components/conn_fwloader/CMakeLists.txt @@ -22,8 +22,7 @@ endif() if (CONFIG_MCUX_COMPONENT_driver.conn_fwloader.fw_bin) mcux_add_source( - SOURCES script/fw_bin2c_conv.py - fw_bin/rw61x_sb_wifi_a2.bin + SOURCES fw_bin/rw61x_sb_wifi_a2.bin fw_bin/rw61x_sb_ble_a2.bin fw_bin/rw61x_sb_ble_15d4_combo_a2.bin fw_bin/script/wlan_gen_fw_incs.py diff --git a/mcux/mcux-sdk-ng/components/conn_fwloader/fsl_loader_utils.c b/mcux/mcux-sdk-ng/components/conn_fwloader/fsl_loader_utils.c index 6d29e006f..904ba88fa 100644 --- a/mcux/mcux-sdk-ng/components/conn_fwloader/fsl_loader_utils.c +++ b/mcux/mcux-sdk-ng/components/conn_fwloader/fsl_loader_utils.c @@ -129,7 +129,7 @@ static void sb3_DelayUs(uint32_t us) //static uint32_t _ActiveApplicationRemapOffset(void) //{ -// return (MFLASH_FLEXSPI->HADDROFFSET); +// return (MFLASH_FLEXSPI->HADDROFFSET); //} //////////////////////////////////////////////////////////////////////////// //! @brief power on device implementation diff --git a/mcux/mcux-sdk-ng/components/conn_fwloader/readme.txt b/mcux/mcux-sdk-ng/components/conn_fwloader/readme.txt index 0ca02c86d..93ee0285c 100644 --- a/mcux/mcux-sdk-ng/components/conn_fwloader/readme.txt +++ b/mcux/mcux-sdk-ng/components/conn_fwloader/readme.txt @@ -1,4 +1,4 @@ -1.Examples that support monolithic image download do not need the steps 2-6 to load fw: +1.Examples that support monolithic image download do not need the steps 2-5 to load fw: Wi-Fi examples: wifi_cli, wifi_wpa_supplicant, wifi_cert, wifi_cli_fw_dump, wifi_test_mode ncp examples: ncp_device coex examples: coex_cli, coex_supplicant_cli @@ -25,13 +25,7 @@ The CMD to write CPU2_15.4 image to flash in J-link window: loadbin C:\xxx\rw61x_sb_ble_15d4_combo_xx.bin,0x085e0000 -5. How to generate the C files to be compiled in the monolithic binary: - In a shell go to directory /components/conn_fwloader. Enter the following command: - 'python script/fw_bin2c_conv.py -t sb fw_bin' - or 'python script/fw_bin2c_conv.py -t raw fw_bin': - This results in generating the C files under fw_bin/A1 and fw_bin/A2 subdirectories. - -6. Remap mechanism support +5. Remap mechanism support Whenever the remap feature is active, the flash should not be accessed in direct mode. As a consequence, no structure cast should be done on flash direct addresses. Likewise memcpy operations should be avoided. Instead all flash accesses must be done via staging buffers in RAM, that diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/frdmrw612/mflash_drv.c b/mcux/mcux-sdk-ng/components/flash/mflash/frdmrw612/mflash_drv.c index 1a64bc979..c7bded207 100644 --- a/mcux/mcux-sdk-ng/components/flash/mflash/frdmrw612/mflash_drv.c +++ b/mcux/mcux-sdk-ng/components/flash/mflash/frdmrw612/mflash_drv.c @@ -353,6 +353,25 @@ static int32_t mflash_drv_init_internal(void) #endif config.ahbConfig.enableAHBBufferable = true; config.ahbConfig.enableAHBCachable = true; + +#ifdef ENCRYPTED_XIP_IPED + /* MCUX-73057: Make sure that there is only one buffer per master as multiple + * buffers for a single AHB master make a conflict between IPED and PKC + */ + for (uint8_t i = 0; i < ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1U); i++) + { + config.ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */ + config.ahbConfig.buffer[i].masterIndex = 0xFU; /* Invalid master index which is not used, so will never hit. */ + config.ahbConfig.buffer[i].bufferSize = 0x0U; /* Default buffer size 0 for buffer0 to buffer(FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1U)*/ + config.ahbConfig.buffer[i].priority = 0; + } + /* AHBRXBUF7CR0 */ + config.ahbConfig.buffer[7].enablePrefetch = true; + config.ahbConfig.buffer[7].masterIndex = 0x0U; + config.ahbConfig.buffer[7].bufferSize = 0x0U; + config.ahbConfig.buffer[7].priority = 0; +#endif + FLEXSPI_Init(MFLASH_FLEXSPI, &config); /* Configure flash settings according to serial flash feature. */ diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/CMakeLists.txt b/mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/CMakeLists.txt new file mode 100644 index 000000000..cae21743a --- /dev/null +++ b/mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/CMakeLists.txt @@ -0,0 +1,24 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: BSD-3-Clause + +if (CONFIG_MCUX_COMPONENT_component.mflash_onchip) + mcux_add_include( + BASE_PATH ${SdkRootDirPath}/components/flash/mflash + INCLUDES + . + ./mcxe3x + ) + mcux_add_source( + BASE_PATH ${SdkRootDirPath}/components/flash/mflash + SOURCES + mflash_common.h + mflash_file.c + mflash_file.h + ./mcxe3x/mflash_drv.c + ./mcxe3x/mflash_drv.h + ) +# default mflash_file address 0x100000 + mcux_add_macro( + "-DMFLASH_FILE_BASEADDR=1048576" + ) +endif() diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/mflash_drv.c b/mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/mflash_drv.c new file mode 100644 index 000000000..ecc930497 --- /dev/null +++ b/mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/mflash_drv.c @@ -0,0 +1,138 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include "mflash_drv.h" +#include "fsl_flash.h" +#include "fsl_cache.h" + +static flash_config_t flash_ctx; + + +/* API - initialize 'mflash' */ +int32_t mflash_drv_init(void) +{ + status_t result; + + memset(&flash_ctx, 0, sizeof(flash_ctx)); + + result = FLASH_Init(&flash_ctx); + if (result != kStatus_Success) + { + return result; + } + + return kStatus_Success; +} + +/* API - Erase single sector */ +int32_t mflash_drv_sector_erase(uint32_t sector_addr) +{ + status_t ret; + uint32_t primask; + + if ((sector_addr % MFLASH_SECTOR_SIZE) != 0UL) + { + return kStatus_InvalidArgument; + } + + primask = __get_PRIMASK(); + __disable_irq(); + + ret = FLASH_Erase(&flash_ctx, sector_addr, MFLASH_SECTOR_SIZE, kFLASH_ApiEraseKey); + + //L1CACHE_InvalidateDCacheByRange(sector_addr, MFLASH_SECTOR_SIZE); + + if (primask == 0UL) + { + __enable_irq(); + } + + __ISB(); + + return ret; +} + +/* API - Page program */ + +int32_t mflash_drv_page_program(uint32_t page_addr, uint32_t *data) +{ + status_t ret; + uint32_t primask; + + if ((page_addr % (uint32_t)MFLASH_PAGE_SIZE) != 0UL) + { + return kStatus_InvalidArgument; + } + + primask = __get_PRIMASK(); + __disable_irq(); + + ret = FLASH_Program(&flash_ctx, page_addr, data, MFLASH_PAGE_SIZE); + + //L1CACHE_InvalidateDCacheByRange(page_addr, MFLASH_PAGE_SIZE); + + if (primask == 0UL) + { + __enable_irq(); + } + + __ISB(); + + return ret; +} + + +/* API - Phrase program */ +int32_t mflash_drv_phrase_program(uint32_t phrase_addr, uint32_t *data) +{ + status_t ret; + uint32_t primask; + + if ((phrase_addr % (uint32_t)MFLASH_PHRASE_SIZE) != 0UL) + { + return kStatus_InvalidArgument; + } + + primask = __get_PRIMASK(); + __disable_irq(); + + ret = FLASH_Program(&flash_ctx, phrase_addr, data, MFLASH_PHRASE_SIZE); + + //L1CACHE_InvalidateDCacheByRange(phrase_addr, MFLASH_PHRASE_SIZE); + + if (primask == 0UL) + { + __enable_irq(); + } + + __ISB(); + + return ret; +} + +/* API - Read data */ +int32_t mflash_drv_read(uint32_t addr, uint32_t *buffer, uint32_t len) +{ + (void)memcpy(buffer, (void *)addr, len); + return kStatus_Success; +} + +/* API - Get pointer to FLASH region */ +void *mflash_drv_phys2log(uint32_t addr, uint32_t len) +{ + /* FLASH is directly mapped in the address space */ + return (void *)(addr); +} + +/* API - Get pointer to FLASH region */ +uint32_t mflash_drv_log2phys(void *ptr, uint32_t len) +{ + /* FLASH is directly mapped in the address space */ + return ((uint32_t)ptr); +} diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/mflash_drv.h b/mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/mflash_drv.h new file mode 100644 index 000000000..9f5883cc4 --- /dev/null +++ b/mcux/mcux-sdk-ng/components/flash/mflash/mcxe3x/mflash_drv.h @@ -0,0 +1,26 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MFLASH_DRV_H__ +#define __MFLASH_DRV_H__ + +#include "mflash_common.h" + +/* Flash constants */ + +#define MFLASH_SECTOR_SIZE (8192) + +#define MFLASH_SUPER_SECTOR_SIZE (65536) + +#define MFLASH_PAGE_SIZE (128) + +#define MFLASH_PHRASE_SIZE (8) + +#define MFLASH_BASE_ADDRESS (0) + +int32_t mflash_drv_phrase_program(uint32_t phrase_addr, uint32_t *data); + +#endif diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/CMakeLists.txt b/mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/CMakeLists.txt new file mode 100644 index 000000000..75df58bd2 --- /dev/null +++ b/mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/CMakeLists.txt @@ -0,0 +1,24 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: BSD-3-Clause + +if (CONFIG_MCUX_COMPONENT_component.mflash_onchip) + mcux_add_include( + BASE_PATH ${SdkRootDirPath}/components/flash/mflash + INCLUDES + . + ./mcxw71 + ) + mcux_add_source( + BASE_PATH ${SdkRootDirPath}/components/flash/mflash + SOURCES + mflash_common.h + mflash_file.c + mflash_file.h + ./mcxw71/mflash_drv.c + ./mcxw71/mflash_drv.h + ) + + mcux_add_macro( + "-DMFLASH_FILE_BASEADDR=0x00700000" + ) +endif() diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/mflash_drv.c b/mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/mflash_drv.c new file mode 100644 index 000000000..d25a9c892 --- /dev/null +++ b/mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/mflash_drv.c @@ -0,0 +1,134 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include "mflash_drv.h" +#include "fsl_flash.h" +#include "fsl_mcm.h" +#include "pin_mux.h" + +static flash_config_t s_flashDriver = {0}; + +static uint32_t pflashBlock0Base = 0; +static uint32_t pflashBlock0Size = 0; +static uint32_t pflashSectorSize = 0; +static uint32_t pflashBlockCount = 0; +static uint32_t pflashTotalSize = 0; + +/* API - initialize 'mflash' */ +int32_t mflash_drv_init(void) +{ + status_t result; + + (void)memset(&s_flashDriver, 0, sizeof(flash_config_t)); + + result = FLASH_Init(&s_flashDriver); + if (result != kStatus_Success) + { + return result; + } + +#if defined(SMSCM_CACHE_CLEAR_MASK) && SMSCM_CACHE_CLEAR_MASK + /* disable flash cache/Prefetch */ + FLASH_CACHE_Disable(); +#endif /* SMSCM_CACHE_CLEAR_MASK */ + + result = FLASH_GetProperty(&s_flashDriver, kFLASH_PropertyPflash0BlockBaseAddr, &pflashBlock0Base); + if (result != kStatus_Success) + { + return result; + } + + result = FLASH_GetProperty(&s_flashDriver, kFLASH_PropertyPflash0BlockSize, &pflashBlock0Size); + if (result != kStatus_Success) + { + return result; + } + + result = FLASH_GetProperty(&s_flashDriver, kFLASH_PropertyPflash0SectorSize, &pflashSectorSize); + if (result != kStatus_Success) + { + return result; + } + + result = FLASH_GetProperty(&s_flashDriver, kFLASH_PropertyPflash0BlockCount, &pflashBlockCount); + if (result != kStatus_Success) + { + return result; + } + + result = FLASH_GetProperty(&s_flashDriver, kFLASH_PropertyPflash0TotalSize, &pflashTotalSize); + + return result; +} + +/* API - Erase single sector */ +int32_t mflash_drv_sector_erase(uint32_t sector_addr) +{ + uint32_t primask = 0; + int32_t ret = kStatus_Fail; + + primask = DisableGlobalIRQ(); + + flash_cache_speculation_control(true, FLASH); + + ret = FLASH_Erase(&s_flashDriver, FLASH, sector_addr, MFLASH_SECTOR_SIZE, (uint32_t)kFLASH_ApiEraseKey); + + /* Clear code bus cache */ + MCM_ClearCodeBusCache(MCM); + + flash_cache_speculation_control(false, FLASH); + + EnableGlobalIRQ(primask); + + return ret; +} + +/* API - Page program */ +int32_t mflash_drv_page_program(uint32_t page_addr, uint32_t *data) +{ + uint32_t primask = 0; + int32_t ret = kStatus_Fail; + + primask = DisableGlobalIRQ(); + + flash_cache_speculation_control(true, FLASH); + + ret = FLASH_ProgramPage(&s_flashDriver, FLASH, page_addr, (uint8_t *)data, MFLASH_PAGE_SIZE); + + /* Clear code bus cache */ + MCM_ClearCodeBusCache(MCM); + + flash_cache_speculation_control(false, FLASH); + + EnableGlobalIRQ(primask); + + return ret; +} + +/* API - Read data */ +int32_t mflash_drv_read(uint32_t addr, uint32_t *buffer, uint32_t len) +{ + (void)memcpy((void *)buffer, (void *)(uint32_t *)addr, len); + + return kStatus_Success; +} + +/* API - Get pointer to FLASH region */ +void *mflash_drv_phys2log(uint32_t addr, uint32_t len) +{ + /* FLASH is directly mapped in the address space */ + return (void *)(addr); +} + +/* API - Get pointer to FLASH region */ +uint32_t mflash_drv_log2phys(void *ptr, uint32_t len) +{ + /* FLASH is directly mapped in the address space */ + return ((uint32_t)ptr); +} \ No newline at end of file diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/mflash_drv.h b/mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/mflash_drv.h new file mode 100644 index 000000000..cb7205384 --- /dev/null +++ b/mcux/mcux-sdk-ng/components/flash/mflash/mcxw71/mflash_drv.h @@ -0,0 +1,26 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MFLASH_DRV_H__ +#define __MFLASH_DRV_H__ + +#include "mflash_common.h" + +/* Flash constants */ + +/* + * The value is not sector size as reported by FLASH_GetProperty() in mflash_drv_init(). + * this platform can erase/program the flash memory by smaller block (actually page size). + */ +#ifndef MFLASH_SECTOR_SIZE +#define MFLASH_SECTOR_SIZE (8192U) +#endif + +#ifndef MFLASH_PAGE_SIZE +#define MFLASH_PAGE_SIZE (128U) +#endif + +#endif diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1021/mflash_drv.c b/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1021/mflash_drv.c index 2df09d9f8..489d113e5 100644 --- a/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1021/mflash_drv.c +++ b/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1021/mflash_drv.c @@ -30,7 +30,11 @@ #define FLASH_BUSY_STATUS_POL 1 #define FLASH_BUSY_STATUS_OFFSET 0 -#define FLASH_SIZE 0x8000 +// on-board QSPI Flash 64Mb/8MB IS25LP064 +// flash memory size [KB] JEDEC unit definition, +// 1 KB = 1024 bytes, 1 MB = 1024 KB, +// 8 MB = 0x800000 B = 8388608 B => 8388608/1024 = 8192 KB = 0x2000 KB +#define FLASH_SIZE 0x2000 #ifndef XIP_EXTERNAL_FLASH flexspi_device_config_t deviceconfig = { @@ -62,7 +66,7 @@ const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { /* Fast read mode - SDR */ [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - /* In XIP, the speed of external flash is set to 133MHz, and the external flash require to match 8 corresponding dummy cycles. + /* In XIP, the speed of external flash is set to 133MHz, and the external flash require to match 8 corresponding dummy cycles. * However, other non XIP boot targets are not suitable for XIP boot flow, uses flash default configuration */ #if defined(XIP_BOOT_HEADER_ENABLE) && XIP_BOOT_HEADER_ENABLE [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ( @@ -81,7 +85,7 @@ const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { #else [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), -#endif +#endif /* Read extend parameters */ [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] = diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1062/mflash_drv.c b/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1062/mflash_drv.c index 8b933a684..154bcb7aa 100644 --- a/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1062/mflash_drv.c +++ b/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1062/mflash_drv.c @@ -68,8 +68,15 @@ const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { /* Fast read quad mode - SDR */ [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18), + /* In XIP, the speed of external flash is set to 120MHz, and the external flash require to match 8 corresponding dummy cycles. + * However, other non XIP boot targets are not suitable for XIP boot flow, uses flash default configuration */ +#if defined(XIP_BOOT_HEADER_ENABLE) && XIP_BOOT_HEADER_ENABLE + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), +#else [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), +#endif /* Read extend parameters */ [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] = diff --git a/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1160/mflash_drv.c b/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1160/mflash_drv.c index 89aa786ed..c1489fa81 100644 --- a/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1160/mflash_drv.c +++ b/mcux/mcux-sdk-ng/components/flash/mflash/mimxrt1160/mflash_drv.c @@ -30,7 +30,11 @@ #define FLASH_BUSY_STATUS_POL 1 #define FLASH_BUSY_STATUS_OFFSET 0 -#define FLASH_SIZE 0x10000 +// on-board QSPI Flash 128Mb/16MB IS25WP128 +// flash memory size [KB] JEDEC unit definition, +// 1 KB = 1024 bytes, 1 MB = 1024 KB, +// 16 MB = 0x1000000 B = 16777216 B => 16777216/1024 = 16384 KB = 4000 KB +#define FLASH_SIZE 0x4000 #ifndef XIP_EXTERNAL_FLASH flexspi_device_config_t deviceconfig = { @@ -62,14 +66,14 @@ const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { /* Fast read mode - SDR */ [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - /* In XIP, the speed of external flash is set to 133MHz, and the external flash require to match 8 corresponding dummy cycles. + /* In XIP, the speed of external flash is set to 133MHz, and the external flash require to match 8 corresponding dummy cycles. * However, cm4 core cases or other non XIP boot targets are not suitable for XIP boot flow, uses flash default configuration */ #if defined(XIP_BOOT_HEADER_ENABLE) && XIP_BOOT_HEADER_ENABLE [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), #else [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), #endif /* Fast read quad mode - SDR */ diff --git a/mcux/mcux-sdk-ng/components/flash/nor/flexspi/fsl_flexspi_nor_flash.c b/mcux/mcux-sdk-ng/components/flash/nor/flexspi/fsl_flexspi_nor_flash.c index bbab488df..dd4df3302 100644 --- a/mcux/mcux-sdk-ng/components/flash/nor/flexspi/fsl_flexspi_nor_flash.c +++ b/mcux/mcux-sdk-ng/components/flash/nor/flexspi/fsl_flexspi_nor_flash.c @@ -1,5 +1,5 @@ /* - * Copyright 2019-2023, 2024 NXP + * Copyright 2019-2023, 2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -3653,7 +3653,18 @@ status_t Nor_Flash_Erase(nor_handle_t *handle, uint32_t address, uint32_t size_B uint32_t startAddress = address; status_t status = kStatus_Success; - for (uint32_t i = 0x00U; i <= (size_Byte / handle->bytesInSectorSize); i++) + if ((address % (handle->bytesInSectorSize)) != 0UL) + { + /* Invalid address. */ + return kStatus_InvalidArgument; + } + if ((size_Byte % (handle->bytesInSectorSize)) != 0UL) + { + /* Invalid size_byte. */ + return kStatus_InvalidArgument; + } + + for (uint32_t i = 0x00U; i < (size_Byte / handle->bytesInSectorSize); i++) { status = Nor_Flash_Erase_Sector(handle, startAddress); startAddress += handle->bytesInSectorSize; @@ -3714,7 +3725,17 @@ status_t Nor_Flash_Program(nor_handle_t *handle, uint32_t address, uint8_t *buff uint32_t startAddress = address; status_t status = kStatus_Success; - for (uint32_t i = 0x00U; i <= (length / handle->bytesInPageSize); i++) + if ((address % (handle->bytesInPageSize)) != 0UL) + { + return kStatus_InvalidArgument; + } + + if ((length % (handle->bytesInPageSize)) != 0UL) + { + return kStatus_InvalidArgument; + } + + for (uint32_t i = 0x00U; i < (length / handle->bytesInPageSize); i++) { status = Nor_Flash_Page_Program(handle, startAddress, buffer); /* Avoid buffer overflow. */ diff --git a/mcux/mcux-sdk-ng/components/flash/nor/fsl_nor_flash.h b/mcux/mcux-sdk-ng/components/flash/nor/fsl_nor_flash.h index 485378967..a78d768f6 100644 --- a/mcux/mcux-sdk-ng/components/flash/nor/fsl_nor_flash.h +++ b/mcux/mcux-sdk-ng/components/flash/nor/fsl_nor_flash.h @@ -1,5 +1,5 @@ /* - * Copyright 2019-2022 NXP + * Copyright 2019-2022, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -103,7 +103,9 @@ status_t Nor_Flash_Page_Program(nor_handle_t *handle, uint32_t address, uint8_t * @param address The address to be programed. * @param buffer The buffer to be programed to the page. * @param length The data length to be programed to the page. - * @retval execution status + * + * @retval kStatus_Success Program specific region successfully. + * @retval kStatus_InvalidArgument address or length not sector size aligned. */ status_t Nor_Flash_Program(nor_handle_t *handle, uint32_t address, uint8_t *buffer, uint32_t length); @@ -131,7 +133,9 @@ status_t Nor_Flash_Erase_Block(nor_handle_t *handle, uint32_t address); * @param handle The NOR Flash handler. * @param address The start address to be erased. * @param size_Byte Erase flash size. - * @retval execution status + * + * @retval kStatus_Success Erase specific region successfully. + * @retval kStatus_InvalidArgument Address or size_Byte not sector size aligned. */ status_t Nor_Flash_Erase(nor_handle_t *handle, uint32_t address, uint32_t size_Byte); diff --git a/mcux/mcux-sdk-ng/components/flash/nor/spifi/fsl_spifi_nor_flash.c b/mcux/mcux-sdk-ng/components/flash/nor/spifi/fsl_spifi_nor_flash.c index a9a37e253..1ca4addb6 100644 --- a/mcux/mcux-sdk-ng/components/flash/nor/spifi/fsl_spifi_nor_flash.c +++ b/mcux/mcux-sdk-ng/components/flash/nor/spifi/fsl_spifi_nor_flash.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,12 @@ #define SPIFI_256K_SECTOR_SIZE_OFFSET (18U) #define NOR_SFDP_SIGNATURE 0x50444653 /* ASCII: SFDP */ +enum +{ + kSerialFlash_Unlocked = 0x0, + kSerialFlash_Locked +}; + enum { kSerialFlash_ReadSFDP = 0x5A, @@ -256,6 +262,20 @@ spifi_mem_nor_handle_t spifi_handle; /******************************************************************************* * Code ******************************************************************************/ +static bool spifi_nor_lock(spifi_mem_nor_handle_t *memSpifiHandler) +{ + return (SDK_ATOMIC_LOCAL_TEST_AND_SET(&memSpifiHandler->lock, kSerialFlash_Locked) == kSerialFlash_Unlocked); +} + +static void spifi_nor_unlock(spifi_mem_nor_handle_t *memSpifiHandler) +{ + memSpifiHandler->lock = kSerialFlash_Unlocked; +} + +static bool spifi_nor_is_locked(spifi_mem_nor_handle_t *memSpifiHandler) +{ + return (memSpifiHandler->lock == kSerialFlash_Locked); +} static uint8_t spifi_nor_read_status(SPIFI_Type *base, uint8_t readCmd) { @@ -784,10 +804,16 @@ static status_t spifi_nor_erase_sector(nor_handle_t *handle, uint32_t address) address &= ~(handle->bytesInSectorSize - 1); spifi_command_type_t cmdType = memSpifiHandler->commandType; + if (!spifi_nor_lock(memSpifiHandler)) + { + return kStatus_Busy; + } + /* Enable write operation. */ status = spifi_nor_write_enable(base, memSpifiHandler, kSPIFI_CommandAllSerial); if (kStatus_Success != status) { + spifi_nor_unlock(memSpifiHandler); return status; } /* Set address. */ @@ -806,9 +832,16 @@ static status_t spifi_nor_erase_sector(nor_handle_t *handle, uint32_t address) /* Check if finished. */ status = spifi_check_norflash_finish(base, memSpifiHandler); + spifi_nor_unlock(memSpifiHandler); + return status; } +status_t Nor_Flash_Initialization(nor_config_t *config, nor_handle_t *handle) +{ + return Nor_Flash_Init(config, handle); +} + status_t Nor_Flash_Init(nor_config_t *config, nor_handle_t *handle) { assert(config); @@ -873,6 +906,37 @@ status_t Nor_Flash_Init(nor_config_t *config, nor_handle_t *handle) return status; } +status_t Nor_Flash_Erase(nor_handle_t *handle, uint32_t address, uint32_t size_Byte) +{ + assert(handle != NULL); + assert(size_Byte > 0x00U); + uint32_t startAddress = address; + status_t status = kStatus_Success; + + if ((address % (handle->bytesInSectorSize)) != 0UL) + { + /* Invalid address. */ + return kStatus_InvalidArgument; + } + if ((size_Byte % (handle->bytesInSectorSize)) != 0UL) + { + /* Invalid size_byte. */ + return kStatus_InvalidArgument; + } + + for (uint32_t i = 0x00U; i < (size_Byte / handle->bytesInSectorSize); i++) + { + status = Nor_Flash_Erase_Sector(handle, startAddress); + if (kStatus_Success != status) + { + break; + } + startAddress += handle->bytesInSectorSize; + } + + return status; +} + status_t Nor_Flash_Page_Program(nor_handle_t *handle, uint32_t address, uint8_t *buffer) { if (!buffer) @@ -887,10 +951,16 @@ status_t Nor_Flash_Page_Program(nor_handle_t *handle, uint32_t address, uint8_t uint32_t pageSize = handle->bytesInPageSize; SPIFI_Type *base = (SPIFI_Type *)handle->driverBaseAddr; + if (!spifi_nor_lock(memSpifiHandler)) + { + return kStatus_Busy; + } + /* Enable write operation. */ status = spifi_nor_write_enable(base, memSpifiHandler, kSPIFI_CommandAllSerial); if (kStatus_Success != status) { + spifi_nor_unlock(memSpifiHandler); return status; } @@ -915,19 +985,50 @@ status_t Nor_Flash_Page_Program(nor_handle_t *handle, uint32_t address, uint8_t status = spifi_check_norflash_finish(base, memSpifiHandler); + spifi_nor_unlock(memSpifiHandler); return status; } -status_t Nor_Flash_Erase_Sector(nor_handle_t *handle, uint32_t address, uint32_t size_Byte) +status_t Nor_Flash_Program(nor_handle_t *handle, uint32_t address, uint8_t *buffer, uint32_t length) { - uint32_t endAddress = address + size_Byte; - status_t status; + assert(handle != NULL); + assert(buffer != NULL); + uint32_t startAddress = address; + status_t status = kStatus_Success; + + if ((address % (handle->bytesInPageSize)) != 0UL) + { + return kStatus_InvalidArgument; + } - if (endAddress > FSL_FEATURE_SPIFI_START_ADDR + handle->bytesInMemorySize) + if ((length % (handle->bytesInPageSize)) != 0UL) { return kStatus_InvalidArgument; } + for (uint32_t i = 0x00U; i < (length / handle->bytesInPageSize); i++) + { + status = Nor_Flash_Page_Program(handle, startAddress, buffer); + if (kStatus_Success != status) + { + break; + } + + /* Avoid buffer overflow. */ + if (length >= handle->bytesInPageSize) + { + buffer += handle->bytesInPageSize; + startAddress += handle->bytesInPageSize; + } + } + + return status; +} + +status_t Nor_Flash_Erase_Sector(nor_handle_t *handle, uint32_t address) +{ + status_t status; + address &= ~(handle->bytesInSectorSize - 1); status = spifi_nor_erase_sector(handle, address); @@ -935,27 +1036,13 @@ status_t Nor_Flash_Erase_Sector(nor_handle_t *handle, uint32_t address, uint32_t return status; } -status_t Nor_Flash_Erase_Block(nor_handle_t *handle, uint32_t address, uint32_t size_Byte) +status_t Nor_Flash_Erase_Block(nor_handle_t *handle, uint32_t address) { - uint32_t endAddress = address + size_Byte; status_t status; - if (endAddress > FSL_FEATURE_SPIFI_START_ADDR + handle->bytesInMemorySize) - { - return kStatus_InvalidArgument; - } - address &= ~(handle->bytesInSectorSize - 1); - while (address < endAddress) - { - status = spifi_nor_erase_sector(handle, address); - if (kStatus_Success != status) - { - return status; - } - address += handle->bytesInSectorSize; - } + status = spifi_nor_erase_sector(handle, address); return status; } @@ -974,10 +1061,16 @@ status_t Nor_Flash_Erase_Chip(nor_handle_t *handle) SPIFI_Type *base = (SPIFI_Type *)handle->driverBaseAddr; uint8_t opcode = memSpifiHandler->commandSet.eraseChipCommand; + if (!spifi_nor_lock(memSpifiHandler)) + { + return kStatus_Busy; + } + /* Enable write operation. */ status = spifi_nor_write_enable(base, memSpifiHandler, kSPIFI_CommandAllSerial); if (kStatus_Success != status) { + spifi_nor_unlock(memSpifiHandler); return status; } /* Set address. */ @@ -996,6 +1089,8 @@ status_t Nor_Flash_Erase_Chip(nor_handle_t *handle) /* Check if finished. */ status = spifi_check_norflash_finish(base, memSpifiHandler); + spifi_nor_unlock(memSpifiHandler); + return status; } @@ -1019,11 +1114,65 @@ status_t Nor_Flash_Read(nor_handle_t *handle, uint32_t address, uint8_t *buffer, cmd.format = memSpifiHandler->readmemCommandFormt; cmd.type = memSpifiHandler->commandType; cmd.opcode = memSpifiHandler->commandSet.readMemoryCommand; + + if (!spifi_nor_lock(memSpifiHandler)) + { + return kStatus_Busy; + } + SPIFI_SetMemoryCommand(base, &cmd); memcpy(buffer, (void *)address, length); /* Reset to command mode. */ SPIFI_ResetCommand(base); + spifi_nor_unlock(memSpifiHandler); + return status; } + +/*! + * @brief Get the busy status of the NOR Flash. + * + * @param handle The NOR Flash handler. + * @retval Always return kStatus_Success + */ +status_t Nor_Flash_Is_Busy(nor_handle_t *handle, bool *isBusy) +{ + assert(handle); + + spifi_mem_nor_handle_t *memSpifiHandler = (spifi_mem_nor_handle_t *)(handle->deviceSpecific); + + *isBusy = spifi_nor_is_locked(memSpifiHandler); + + return kStatus_Success; +} + +status_t Nor_Flash_Enter_Lowpower(nor_handle_t *handle) +{ + spifi_mem_nor_handle_t *memSpifiHandler = (spifi_mem_nor_handle_t *)(handle->deviceSpecific); + SPIFI_Type *base = (SPIFI_Type *)handle->driverBaseAddr; + + /* Wait and make sure no flash opearation. */ + while (!spifi_nor_lock(memSpifiHandler)) + { + } + + SPIFI_Deinit(base); + + return kStatus_Success; +} + +status_t Nor_Flash_Exit_Lowpower(nor_handle_t *handle) +{ + spifi_config_t memConfig; + spifi_mem_nor_handle_t *memSpifiHandler = (spifi_mem_nor_handle_t *)(handle->deviceSpecific); + SPIFI_Type *base = (SPIFI_Type *)handle->driverBaseAddr; + + SPIFI_GetDefaultConfig(&memConfig); + SPIFI_Init(base, &memConfig); + + spifi_nor_unlock(memSpifiHandler); + + return kStatus_Success; +} diff --git a/mcux/mcux-sdk-ng/components/flash/nor/spifi/fsl_spifi_nor_flash.h b/mcux/mcux-sdk-ng/components/flash/nor/spifi/fsl_spifi_nor_flash.h index 1f14c1f6f..5c824dab8 100644 --- a/mcux/mcux-sdk-ng/components/flash/nor/spifi/fsl_spifi_nor_flash.h +++ b/mcux/mcux-sdk-ng/components/flash/nor/spifi/fsl_spifi_nor_flash.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #include "fsl_common.h" #include "fsl_spifi.h" +#include "fsl_nor_flash.h" /*! * @addtogroup spifi_nor_flash @@ -119,9 +120,38 @@ typedef struct _spifi_mem_nor_handle spifi_command_type_t commandType; /*!< Opcode and address type */ spifi_command_format_t readmemCommandFormt; /*!< Command formt for read memory opration */ uint8_t intermediateLen; /*!< Intermediate bytes precede the data */ + uint8_t lock; /*!< Lock to protect flash operation */ serial_nor_command_set_t commandSet; /*!< Serial NOR basic command set */ } spifi_mem_nor_handle_t; /*! @}*/ +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Prepare the NOR flash for low power entry + * + * @param handle The NOR Flash handler. + * @retval status_t execution status + */ +status_t Nor_Flash_Enter_Lowpower(nor_handle_t *handle); + +/*! + * @brief Prepare the NOR flash for low power exit + * + * @param handle The NOR Flash handler. + * @retval status_t execution status + */ +status_t Nor_Flash_Exit_Lowpower(nor_handle_t *handle); + +#ifdef __cplusplus +} +#endif + #endif /* __FSL_SPIFI_NOR_FLASH_H__ */ diff --git a/mcux/mcux-sdk-ng/components/flash/nor/xspi/fsl_xspi_nor_flash.c b/mcux/mcux-sdk-ng/components/flash/nor/xspi/fsl_xspi_nor_flash.c index 0a079e789..fcece78f1 100644 --- a/mcux/mcux-sdk-ng/components/flash/nor/xspi/fsl_xspi_nor_flash.c +++ b/mcux/mcux-sdk-ng/components/flash/nor/xspi/fsl_xspi_nor_flash.c @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -1482,7 +1482,17 @@ status_t Nor_Flash_Program(nor_handle_t *handle, uint32_t address, uint8_t *buff uint32_t startAddress = address; status_t status = kStatus_Success; - for (uint32_t i = 0x00U; i <= (length / handle->bytesInPageSize); i++) + if ((address % (handle->bytesInPageSize)) != 0UL) + { + return kStatus_InvalidArgument; + } + + if ((length % (handle->bytesInPageSize)) != 0UL) + { + return kStatus_InvalidArgument; + } + + for (uint32_t i = 0x00U; i < (length / handle->bytesInPageSize); i++) { status = Nor_Flash_Page_Program(handle, startAddress, buffer); /* Avoid buffer overflow. */ @@ -1594,7 +1604,18 @@ status_t Nor_Flash_Erase(nor_handle_t *handle, uint32_t address, uint32_t size_B uint32_t startAddress = address; status_t status = kStatus_Success; - for (uint32_t i = 0x00U; i <= (size_Byte / handle->bytesInSectorSize); i++) + if ((address % (handle->bytesInSectorSize)) != 0UL) + { + /* Invalid address. */ + return kStatus_InvalidArgument; + } + if ((size_Byte % (handle->bytesInSectorSize)) != 0UL) + { + /* Invalid size_byte. */ + return kStatus_InvalidArgument; + } + + for (uint32_t i = 0x00U; i < (size_Byte / handle->bytesInSectorSize); i++) { status = Nor_Flash_Erase_Sector(handle, startAddress); startAddress += handle->bytesInSectorSize; diff --git a/mcux/mcux-sdk-ng/components/misc_utilities/CMakeLists.txt b/mcux/mcux-sdk-ng/components/misc_utilities/CMakeLists.txt index b1300121f..7e98a8376 100644 --- a/mcux/mcux-sdk-ng/components/misc_utilities/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/components/misc_utilities/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # SPDX-License-Identifier: BSD-3-Clause if (CONFIG_MCUX_COMPONENT_utilities.misc_utilities) @@ -19,8 +19,8 @@ if (CONFIG_MCUX_COMPONENT_utilities.misc_utilities) mcux_add_source( SOURCES fsl_memcpy.S TOOLCHAINS armgcc mcux mdk - CORES cm3 cm4 cm4f cm7 cm7f cm23 cm33 cm33f - ) + CORES cm3 cm4 cm4f cm7 cm7f cm33 cm33f + ) endif() diff --git a/mcux/mcux-sdk-ng/components/misc_utilities/fsl_incbin.S b/mcux/mcux-sdk-ng/components/misc_utilities/fsl_incbin.S index 99114bcb6..b3c446dc6 100644 --- a/mcux/mcux-sdk-ng/components/misc_utilities/fsl_incbin.S +++ b/mcux/mcux-sdk-ng/components/misc_utilities/fsl_incbin.S @@ -1,5 +1,5 @@ ;/* -; * Copyright 2020 NXP +; * Copyright 2020,2025 NXP ; * ; * All rights reserved. ; * @@ -14,6 +14,14 @@ core1_image_start INCBIN core1_image.bin core1_image_end +#if CONFIG_UTILITY_INCBIN_NS == 1 + AREA core1_ns_code, DATA, READONLY, PREINIT_ARRAY, ALIGN=3 + EXPORT core1_ns_image_start + EXPORT core1_ns_image_end +core1_ns_image_start + INCBIN core1_ns_image.bin +core1_ns_image_end +#endif /* CONFIG_UTILITY_INCBIN_NS == 1 */ END #elif defined(__GNUC__) || defined(__ARMCC_VERSION) @@ -32,6 +40,22 @@ core1_image_end: .align 4 core1_image_size: .int core1_image_end - core1_image_start +#if CONFIG_UTILITY_INCBIN_NS == 1 + .section .core1_ns_code, "ax" @progbits @preinit_array + .global core1_ns_image_start + .type core1_ns_image_start, %object + .align 4 +core1_ns_image_start: + .incbin "core1_ns_image.bin" + .global core1_ns_image_end + .type core1_ns_image_end, %object +core1_ns_image_end: + .global core1_ns_image_size + .type core1_ns_image_size, %object + .align 4 +core1_ns_image_size: + .int core1_ns_image_end - core1_ns_image_start +#endif /* CONFIG_UTILITY_INCBIN_NS == 1 */ .end #endif diff --git a/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction.h b/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction.h index 586d0a25d..2353f8c89 100644 --- a/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction.h +++ b/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction.h @@ -203,10 +203,10 @@ extern const uint8_t gUseRtos_c; #define OSA_EVENT_HANDLE_SIZE (16U) #endif /* FSL_OSA_TASK_ENABLE */ #if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) -#define OSA_SEM_HANDLE_SIZE (16U) +#define OSA_SEM_HANDLE_SIZE (20U) #define OSA_MUTEX_HANDLE_SIZE (12U) #else -#define OSA_SEM_HANDLE_SIZE (8U) +#define OSA_SEM_HANDLE_SIZE (12U) #define OSA_MUTEX_HANDLE_SIZE (4U) #endif #if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) diff --git a/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_bm.c b/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_bm.c index 7af95cbaa..6600ee49e 100644 --- a/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_bm.c +++ b/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_bm.c @@ -1,6 +1,6 @@ /*! * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019,2022 NXP + * Copyright 2016-2019,2022,2025 NXP * * * This is the source file for the OS Abstraction layer for MQXLite. @@ -146,7 +146,7 @@ typedef struct _osa_state list_label_t taskList; task_handler_t curTaskHandler; #endif - volatile uint32_t interruptDisableCount; + volatile uint32_t disableIRQGlobalNesting; volatile uint32_t interruptRegPrimask; volatile uint32_t tickCounter; #if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) @@ -227,6 +227,11 @@ void *OSA_MemoryAllocateAlign(uint32_t memLength, uint32_t alignbytes) osa_mem_align_cb_t *p_cb = NULL; uint32_t alignedsize; + if ((alignbytes < 1U) || (alignbytes > UINT16_MAX)) + { + return NULL; + } + /* Check overflow. */ alignedsize = (uint32_t)(unsigned int)OSA_MEM_SIZE_ALIGN(memLength, alignbytes); if (alignedsize < memLength) @@ -234,7 +239,7 @@ void *OSA_MemoryAllocateAlign(uint32_t memLength, uint32_t alignbytes) return NULL; } - if (alignedsize > 0xFFFFFFFFU - alignbytes - sizeof(osa_mem_align_cb_t)) + if (alignedsize > UINT32_MAX - alignbytes - sizeof(osa_mem_align_cb_t)) { return NULL; } @@ -301,11 +306,11 @@ void OSA_ExitCritical(uint32_t sr) *END**************************************************************************/ void OSA_EnableIRQGlobal(void) { - if (s_osaState.interruptDisableCount > 0U) + if (s_osaState.disableIRQGlobalNesting > 0U) { - s_osaState.interruptDisableCount--; + s_osaState.disableIRQGlobalNesting--; - if (0U == s_osaState.interruptDisableCount) + if (0U == s_osaState.disableIRQGlobalNesting) { EnableGlobalIRQ(s_osaState.interruptRegPrimask); } @@ -323,13 +328,13 @@ void OSA_EnableIRQGlobal(void) void OSA_DisableIRQGlobal(void) { /* call API to disable the global interrupt*/ - if (0U == s_osaState.interruptDisableCount) + if (0U == s_osaState.disableIRQGlobalNesting) { s_osaState.interruptRegPrimask = DisableGlobalIRQ(); } /* update counter*/ - s_osaState.interruptDisableCount++; + s_osaState.disableIRQGlobalNesting++; } /*FUNCTION********************************************************************** @@ -479,6 +484,8 @@ osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t * uint32_t regPrimask; assert(sizeof(task_control_block_t) == OSA_TASK_HANDLE_SIZE); assert(taskHandle); + assert(thread_def->tpriority <= OSA_TASK_PRIORITY_MIN); + assert(OSA_TASK_PRIORITY_MIN > OSA_TASK_PRIORITY_MAX); ptaskStruct->p_func = thread_def->pthread; ptaskStruct->haveToRun = 1U; @@ -604,12 +611,15 @@ void OSA_TimeDelay(uint32_t millisec) #if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) uint32_t currTime, timeStart; - timeStart = OSA_TimeGetMsec(); - - do + if (millisec > 0U) { - currTime = OSA_TimeGetMsec(); /* Get current time stamp */ - } while (millisec >= OSA_TimeDiff(timeStart, currTime)); + timeStart = OSA_TimeGetMsec(); + + do + { + currTime = OSA_TimeGetMsec(); /* Get current time stamp */ + } while (millisec >= OSA_TimeDiff(timeStart, currTime)); + } #endif } /*FUNCTION********************************************************************** @@ -655,6 +665,7 @@ osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_ semaphore_t *pSemStruct = (semaphore_t *)semaphoreHandle; assert(sizeof(semaphore_t) <= OSA_SEM_HANDLE_SIZE); assert(semaphoreHandle); + assert(initValue <= UINT8_MAX); pSemStruct->semCount = (uint8_t)initValue; pSemStruct->isWaiting = 0U; @@ -1477,9 +1488,9 @@ int main(void) void OSA_Init(void) { LIST_Init((&s_osaState.taskList), 0); - s_osaState.curTaskHandler = NULL; - s_osaState.interruptDisableCount = 0U; - s_osaState.tickCounter = 0U; + s_osaState.curTaskHandler = NULL; + s_osaState.disableIRQGlobalNesting = 0U; + s_osaState.tickCounter = 0U; } #endif diff --git a/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_free_rtos.c b/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_free_rtos.c index 4a29e74e4..ec8112da4 100644 --- a/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_free_rtos.c +++ b/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_free_rtos.c @@ -1,6 +1,6 @@ /*! ********************************************************************************* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2019 NXP + * Copyright 2016-2017, 2019, 2025 NXP * * * This is the source file for the OS Abstraction layer for freertos. @@ -34,8 +34,6 @@ #define __WEAK_FUNC __attribute__((weak)) #endif -#define millisecToTicks(millisec) (((millisec) * (uint32_t)(configTICK_RATE_HZ) + 999U) / 1000U) - #ifdef DEBUG_ASSERT #define OS_ASSERT(condition) \ if (!(condition)) \ @@ -46,8 +44,7 @@ #endif /*! @brief Converts milliseconds to ticks*/ -#define MSEC_TO_TICK(msec) \ - (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL) +#define MSEC_TO_TICKS(msec) (((msec) * (uint32_t)(configTICK_RATE_HZ) + 999U) / 1000U) #define TICKS_TO_MSEC(tick) ((uint32_t)((uint64_t)(tick)*1000uL / (uint64_t)configTICK_RATE_HZ)) #define OSA_MEM_MAGIC_NUMBER (12345U) @@ -80,9 +77,10 @@ typedef struct _osa_state OSA_TASK_HANDLE_DEFINE(mainTaskHandle); #endif #endif - uint32_t basePriority; - int32_t basePriorityNesting; - uint32_t interruptDisableCount; + uint32_t interruptReg; + int32_t interruptDisableNesting; + uint32_t interruptRegPrimask; + uint32_t disableIRQGlobalNesting; } osa_state_t; /*! @brief Definition structure contains allocated memory information.*/ @@ -117,10 +115,8 @@ static osa_state_t s_osaState = {0}; #if (defined(FSL_OSA_ALLOCATED_HEAP) && (FSL_OSA_ALLOCATED_HEAP > 0U)) #if defined(configAPPLICATION_ALLOCATED_HEAP) && (configAPPLICATION_ALLOCATED_HEAP) #if defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE) -extern uint8_t ucHeap[configTOTAL_HEAP_SIZE]; AT_NONCACHEABLE_SECTION_ALIGN(uint8_t ucHeap[configTOTAL_HEAP_SIZE], 4); #else -extern uint8_t ucHeap[configTOTAL_HEAP_SIZE]; SDK_ALIGN(uint8_t ucHeap[configTOTAL_HEAP_SIZE], 4); #endif /* DATA_SECTION_IS_CACHEABLE */ #endif /* configAPPLICATION_ALLOCATED_HEAP */ @@ -178,6 +174,11 @@ void *OSA_MemoryAllocateAlign(uint32_t memLength, uint32_t alignbytes) osa_mem_align_cb_t *p_cb = NULL; uint32_t alignedsize; + if ((alignbytes < 1U) || (alignbytes > UINT16_MAX)) + { + return NULL; + } + /* Check overflow. */ alignedsize = (uint32_t)(unsigned int)OSA_MEM_SIZE_ALIGN(memLength, alignbytes); if (alignedsize < memLength) @@ -185,7 +186,7 @@ void *OSA_MemoryAllocateAlign(uint32_t memLength, uint32_t alignbytes) return NULL; } - if (alignedsize > 0xFFFFFFFFU - alignbytes - sizeof(osa_mem_align_cb_t)) + if (alignedsize > UINT32_MAX - alignbytes - sizeof(osa_mem_align_cb_t)) { return NULL; } @@ -342,6 +343,8 @@ osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle) osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority) { assert(NULL != taskHandle); + assert(taskPriority <= OSA_TASK_PRIORITY_MIN); + assert(OSA_TASK_PRIORITY_MIN > OSA_TASK_PRIORITY_MAX); osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; vTaskPrioritySet((task_handler_t)ptask->taskHandle, PRIORITY_OSA_TO_RTOS(((uint32_t)taskPriority))); return KOSA_StatusSuccess; @@ -368,6 +371,9 @@ osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t * assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE); #endif assert(NULL != taskHandle); + assert(NULL != thread_def); + assert(thread_def->tpriority <= OSA_TASK_PRIORITY_MIN); + assert(OSA_TASK_PRIORITY_MIN > OSA_TASK_PRIORITY_MAX); #if defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0) TaskHandle_t pxCreatedTask; #endif @@ -382,7 +388,7 @@ osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t * xHandle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread, /* pointer to the task */ (const char *)thread_def->tname, /* task name for kernel awareness debugging */ - (uint32_t)((uint16_t)thread_def->stacksize / sizeof(portSTACK_TYPE)), /* task stack size */ + (uint32_t)(thread_def->stacksize / sizeof(portSTACK_TYPE)), /* task stack size */ (task_param_t)task_param, /* optional task startup argument */ PRIORITY_OSA_TO_RTOS((thread_def->tpriority)), /* initial priority */ (StackType_t *)thread_def->tstack, /*Array to use as the task's stack*/ @@ -399,7 +405,7 @@ osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t * if (xTaskCreate( (TaskFunction_t)thread_def->pthread, /* pointer to the task */ (char const *)thread_def->tname, /* task name for kernel awareness debugging */ - (configSTACK_DEPTH_TYPE)((uint16_t)thread_def->stacksize / sizeof(portSTACK_TYPE)), /* task stack size */ + (configSTACK_DEPTH_TYPE)(thread_def->stacksize / sizeof(portSTACK_TYPE)), /* task stack size */ (task_param_t)task_param, /* optional task startup argument */ PRIORITY_OSA_TO_RTOS((thread_def->tpriority)), /* initial priority */ &pxCreatedTask /* optional task handle to create */ @@ -458,7 +464,8 @@ osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle) *END**************************************************************************/ void OSA_TimeDelay(uint32_t millisec) { - vTaskDelay(millisecToTicks(millisec)); + assert(millisec <= (UINT32_MAX - 999U) / (uint32_t)(configTICK_RATE_HZ)); + vTaskDelay(MSEC_TO_TICKS(millisec)); } /*FUNCTION********************************************************************** * @@ -613,7 +620,8 @@ osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t } else { - timeoutTicks = MSEC_TO_TICK(millisec); + assert(millisec <= (UINT32_MAX - 999U) / (uint32_t)(configTICK_RATE_HZ)); + timeoutTicks = MSEC_TO_TICKS(millisec); } if (((BaseType_t)0) == (BaseType_t)xSemaphoreTake(sem, timeoutTicks)) @@ -729,7 +737,8 @@ osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec) } else { - timeoutTicks = MSEC_TO_TICK(millisec); + assert(millisec <= (UINT32_MAX - 999U) / (uint32_t)(configTICK_RATE_HZ)); + timeoutTicks = MSEC_TO_TICKS(millisec); } if (((BaseType_t)0) == (BaseType_t)xSemaphoreTakeRecursive(mutex, timeoutTicks)) @@ -980,7 +989,8 @@ osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, } else { - timeoutTicks = millisecToTicks(millisec); + assert(millisec <= (UINT32_MAX - 999U) / (uint32_t)(configTICK_RATE_HZ)); + timeoutTicks = MSEC_TO_TICKS(millisec); } clearMode = (pEventStruct->autoClear != 0U) ? pdTRUE : pdFALSE; @@ -1127,7 +1137,8 @@ osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage } else { - timeoutTicks = MSEC_TO_TICK(millisec); + assert(millisec <= (UINT32_MAX - 999U) / (uint32_t)(configTICK_RATE_HZ)); + timeoutTicks = MSEC_TO_TICKS(millisec); } if (pdPASS != xQueueReceive(handler, pMessage, timeoutTicks)) { @@ -1181,14 +1192,14 @@ void OSA_InterruptEnable(void) { if (0U != __get_IPSR()) { - if (1 == s_osaState.basePriorityNesting) + if (1 == s_osaState.interruptDisableNesting) { - portCLEAR_INTERRUPT_MASK_FROM_ISR(s_osaState.basePriority); + portCLEAR_INTERRUPT_MASK_FROM_ISR(s_osaState.interruptReg); } - if (s_osaState.basePriorityNesting > 0) + if (s_osaState.interruptDisableNesting > 0) { - s_osaState.basePriorityNesting--; + s_osaState.interruptDisableNesting--; } } else @@ -1207,11 +1218,11 @@ void OSA_InterruptDisable(void) { if (0U != __get_IPSR()) { - if (0 == s_osaState.basePriorityNesting) + if (0 == s_osaState.interruptDisableNesting) { - s_osaState.basePriority = portSET_INTERRUPT_MASK_FROM_ISR(); + s_osaState.interruptReg = portSET_INTERRUPT_MASK_FROM_ISR(); } - s_osaState.basePriorityNesting++; + s_osaState.interruptDisableNesting++; } else { @@ -1227,13 +1238,13 @@ void OSA_InterruptDisable(void) *END**************************************************************************/ void OSA_EnableIRQGlobal(void) { - if (s_osaState.interruptDisableCount > 0U) + if (s_osaState.disableIRQGlobalNesting > 0U) { - s_osaState.interruptDisableCount--; + s_osaState.disableIRQGlobalNesting--; - if (0U == s_osaState.interruptDisableCount) + if (0U == s_osaState.disableIRQGlobalNesting) { - __enable_irq(); + EnableGlobalIRQ(s_osaState.interruptRegPrimask); } /* call core API to enable the global interrupt*/ } @@ -1248,10 +1259,13 @@ void OSA_EnableIRQGlobal(void) void OSA_DisableIRQGlobal(void) { /* call core API to disable the global interrupt*/ - __disable_irq(); + if (0 == s_osaState.disableIRQGlobalNesting) + { + s_osaState.interruptRegPrimask = DisableGlobalIRQ(); + } /* update counter*/ - s_osaState.interruptDisableCount++; + s_osaState.disableIRQGlobalNesting++; } /*FUNCTION********************************************************************** @@ -1332,8 +1346,8 @@ int main(void) void OSA_Init(void) { LIST_Init((&s_osaState.taskList), 0); - s_osaState.basePriorityNesting = 0; - s_osaState.interruptDisableCount = 0; + s_osaState.interruptDisableNesting = 0; + s_osaState.disableIRQGlobalNesting = 0; } #endif diff --git a/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_threadx.c b/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_threadx.c index 20c2f02bd..44997591e 100644 --- a/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_threadx.c +++ b/mcux/mcux-sdk-ng/components/osa/fsl_os_abstraction_threadx.c @@ -79,10 +79,9 @@ typedef struct _osa_state #if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) list_label_t taskList; #endif - uint32_t basePriority; - int32_t basePriorityNesting; + int32_t interruptDisableNesting; uint32_t interruptRegPrimask; - uint32_t interruptDisableCount; + uint32_t disableIRQGlobalNesting; } osa_state_t; /*! @brief Definition structure contains allocated memory information.*/ @@ -148,6 +147,11 @@ void *OSA_MemoryAllocateAlign(uint32_t memLength, uint32_t alignbytes) osa_mem_align_cb_t *p_cb = NULL; uint32_t alignedsize; + if ((alignbytes < 1U) || (alignbytes > UINT16_MAX)) + { + return NULL; + } + /* Check overflow. */ alignedsize = (uint32_t)(unsigned int)OSA_MEM_SIZE_ALIGN(memLength, alignbytes); if (alignedsize < memLength) @@ -155,7 +159,7 @@ void *OSA_MemoryAllocateAlign(uint32_t memLength, uint32_t alignbytes) return NULL; } - if (alignedsize > 0xFFFFFFFFU - alignbytes - sizeof(osa_mem_align_cb_t)) + if (alignedsize > UINT32_MAX - alignbytes - sizeof(osa_mem_align_cb_t)) { return NULL; } @@ -237,8 +241,8 @@ void OSA_ExitCritical(uint32_t sr) void OSA_Init(void) { LIST_Init((&s_osaState.taskList), 0); - s_osaState.basePriorityNesting = 0; - s_osaState.interruptDisableCount = 0; + s_osaState.interruptDisableNesting = 0; + s_osaState.disableIRQGlobalNesting = 0; } #endif @@ -349,6 +353,8 @@ osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle) osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority) { assert(taskHandle); + assert(taskPriority <= OSA_TASK_PRIORITY_MIN); + assert(OSA_TASK_PRIORITY_MIN > OSA_TASK_PRIORITY_MAX); osa_thread_task_t *ptask = (osa_thread_task_t *)taskHandle; UINT status = 0; UINT priority; @@ -502,8 +508,7 @@ osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_ *END**************************************************************************/ osa_status_t OSA_SemaphoreCreateBinary(osa_semaphore_handle_t semaphoreHandle) { - /* TODO */ - return KOSA_StatusError; + return OSA_SemaphoreCreate(semaphoreHandle, 1U); } /*FUNCTION********************************************************************** @@ -915,10 +920,15 @@ osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize) { assert(NULL != msgqHandle); + assert(msgSize <= UINT32_MAX - sizeof(uint32_t) + 1); + + /* ThreadX expects sizes in word, but OSA API passes byte size, so we have to convert it */ + uint32_t sizeWord = (msgSize + sizeof(uint32_t) - 1) / sizeof(uint32_t); + assert(msgNo <= UINT32_MAX / sizeWord); - /* Create the message queue where the number and size is specified by msgNo and msgSize */ - if (TX_SUCCESS == tx_queue_create((TX_QUEUE *)msgqHandle, (CHAR *)"queue 0", msgSize, - (uint8_t *)msgqHandle + OSA_MSGQ_HANDLE_SIZE, msgNo * msgSize)) + /* Create the message queue where the number and size is specified by msgNo and sizeWord */ + if (TX_SUCCESS == tx_queue_create((TX_QUEUE *)msgqHandle, (CHAR *)"queue 0", sizeWord, + (uint8_t *)msgqHandle + OSA_MSGQ_HANDLE_SIZE, msgNo * sizeWord)) { return KOSA_StatusSuccess; } @@ -1035,11 +1045,11 @@ osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle) *END**************************************************************************/ void OSA_InterruptEnable(void) { - if (s_osaState.basePriorityNesting > 0U) + if (s_osaState.interruptDisableNesting > 0) { - s_osaState.basePriorityNesting--; + s_osaState.interruptDisableNesting--; - if (0U == s_osaState.basePriorityNesting) + if (0 == s_osaState.interruptDisableNesting) { TX_RESTORE } @@ -1054,13 +1064,13 @@ void OSA_InterruptEnable(void) *END**************************************************************************/ void OSA_InterruptDisable(void) { - if (0U == s_osaState.basePriorityNesting) + if (0 == s_osaState.interruptDisableNesting) { TX_DISABLE } /* update counter*/ - s_osaState.basePriorityNesting++; + s_osaState.interruptDisableNesting++; } /*FUNCTION********************************************************************** @@ -1071,11 +1081,11 @@ void OSA_InterruptDisable(void) *END**************************************************************************/ void OSA_EnableIRQGlobal(void) { - if (s_osaState.interruptDisableCount > 0U) + if (s_osaState.disableIRQGlobalNesting > 0U) { - s_osaState.interruptDisableCount--; + s_osaState.disableIRQGlobalNesting--; - if (0U == s_osaState.interruptDisableCount) + if (0U == s_osaState.disableIRQGlobalNesting) { EnableGlobalIRQ(s_osaState.interruptRegPrimask); } @@ -1092,13 +1102,13 @@ void OSA_EnableIRQGlobal(void) void OSA_DisableIRQGlobal(void) { /* call core API to disable the global interrupt*/ - if (0 == s_osaState.interruptDisableCount) + if (0 == s_osaState.disableIRQGlobalNesting) { s_osaState.interruptRegPrimask = DisableGlobalIRQ(); } /* update counter*/ - s_osaState.interruptDisableCount++; + s_osaState.disableIRQGlobalNesting++; } /*FUNCTION********************************************************************** diff --git a/mcux/mcux-sdk-ng/components/phy/device/phyyt8521/fsl_phyyt8521.c b/mcux/mcux-sdk-ng/components/phy/device/phyyt8521/fsl_phyyt8521.c index 49ce9e575..0c04a2ea3 100644 --- a/mcux/mcux-sdk-ng/components/phy/device/phyyt8521/fsl_phyyt8521.c +++ b/mcux/mcux-sdk-ng/components/phy/device/phyyt8521/fsl_phyyt8521.c @@ -17,13 +17,25 @@ #define PHY_INER_REG 0x12U /*!< Interrupt Enable Register */ #define PHY_INSR_REG 0x13U /*!< Interrupt Status Register */ -/*! @brief Defines the YT8521 PHY ID number. */ -#define PHY_CONTROL_ID1 (0x001CU) /*!< The PHY ID1 . */ +/*! @brief Defines the PHY YT8521 device ID information. */ +#define PHY_OUI1 0x0U /*!< The PHY organizationally unique identifier. */ +#define PHY_MODEL_NUM1 0x11U /*!< The PHY manufacturer's type number. */ +#define PHY_DEVICE_REVISION_NUM1 0xAU /*!< The PHY manufacturer's revision number. */ +#define PHY_DEVICE_ID1 ((PHY_OUI1 << 10U) | (PHY_MODEL_NUM1 << 4U) | (PHY_DEVICE_REVISION_NUM1)) + +/*! @brief Defines the PHY YT8531 device ID information. */ +#define PHY_OUI 0x3AU /*!< The PHY organizationally unique identifier. */ +#define PHY_MODEL_NUM 0x11U /*!< The PHY manufacturer's type number. */ +#define PHY_DEVICE_REVISION_NUM 0xAU /*!< The PHY manufacturer's revision number. */ +#define PHY_DEVICE_ID ((PHY_OUI << 10U) | (PHY_MODEL_NUM << 4U) | (PHY_DEVICE_REVISION_NUM)) /*! @brief Defines the mask flag in interrupt enable register. */ -#define PHY_INER_LINKSTATUS_SUCCESS_MASK ((uint16_t)0x0400U) /*!< bit 10, The PHY link status success interrupt mask. */ -#define PHY_INER_LINKSTATUS_FAILURE_MASK ((uint16_t)0x0800U) /*!< bit 11, The PHY link status failure interrupt mask. */ - +#define PHY_INER_LINKSTATUS_SUCCESS_MASK \ + ((uint16_t)0x0400U) /*!< bit 10, The PHY link status success interrupt mask. \ + */ +#define PHY_INER_LINKSTATUS_FAILURE_MASK \ + ((uint16_t)0x0800U) /*!< bit 11, The PHY link status failure interrupt mask. \ + */ /*! @brief Defines the mask flag in specific status register. */ #define PHY_SSTATUS_LINKSTATUS_MASK ((uint16_t)0x0400U) /*!< The PHY link status mask. */ #define PHY_SSTATUS_LINKSPEED_MASK ((uint16_t)0xC000U) /*!< bit 15:14 The PHY link speed mask. */ @@ -66,6 +78,7 @@ status_t PHY_YT8521_Init(phy_handle_t *handle, const phy_config_t *config) { uint32_t counter = PHY_READID_TIMEOUT_COUNT; uint16_t regValue = 0U; + uint32_t devId = 0U; status_t result; /* Assign PHY address and operation resource. */ @@ -80,8 +93,17 @@ status_t PHY_YT8521_Init(phy_handle_t *handle, const phy_config_t *config) { return result; } + devId = regValue << 16U; + + result = PHY_YT8521_READ(handle, PHY_ID2_REG, ®Value); + if (result != kStatus_Success) + { + return result; + } + devId += regValue; + counter--; - } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); + } while ((regValue != PHY_DEVICE_ID) && (regValue != PHY_DEVICE_ID1) && (counter != 0U)); if (counter == 0U) { diff --git a/mcux/mcux-sdk-ng/components/rpmsg/fsl_adapter_rpmsg.c b/mcux/mcux-sdk-ng/components/rpmsg/fsl_adapter_rpmsg.c index 72a69edde..1c5911578 100644 --- a/mcux/mcux-sdk-ng/components/rpmsg/fsl_adapter_rpmsg.c +++ b/mcux/mcux-sdk-ng/components/rpmsg/fsl_adapter_rpmsg.c @@ -52,7 +52,9 @@ typedef struct _hal_rpmsg_peer_ept_state #ifndef RPMSG_GLOBAL_VARIABLE_ALLOC #if (defined(HAL_RPMSG_SELECT_ROLE) && (HAL_RPMSG_SELECT_ROLE == 0U)) +#ifndef SH_MEM_TOTAL_SIZE #define SH_MEM_TOTAL_SIZE (6144U) +#endif /* SH_MEM_TOTAL_SIZE */ #if defined(__ICCARM__) /* IAR Workbench */ #pragma location = "rpmsg_sh_mem_section" static char rpmsg_lite_base[SH_MEM_TOTAL_SIZE]; @@ -70,7 +72,9 @@ extern uint32_t rpmsg_sh_mem_end[]; #else #if (defined(HAL_RPMSG_SELECT_ROLE) && (HAL_RPMSG_SELECT_ROLE == 0U)) +#ifndef SH_MEM_TOTAL_SIZE #define SH_MEM_TOTAL_SIZE (6144U) +#endif /* SH_MEM_TOTAL_SIZE */ extern char *rpmsg_lite_base; #endif /* HAL_RPMSG_SELECT_ROLE */ diff --git a/mcux/mcux-sdk-ng/components/wifi_bt_module/CMakeLists.txt b/mcux/mcux-sdk-ng/components/wifi_bt_module/CMakeLists.txt index d06643bd4..74dc11438 100644 --- a/mcux/mcux-sdk-ng/components/wifi_bt_module/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/components/wifi_bt_module/CMakeLists.txt @@ -37,7 +37,27 @@ endif() if (CONFIG_MCUX_COMPONENT_component.wifi_bt_module.bt_only_fw) mcux_add_macro( "-DCONFIG_BT_ONLY_DNLD\ - -DCONFIG_BT_IND_DNLD" + -DCONFIG_BT_IND_DNLD=1" + ) +endif() + +if (CONFIG_MCUX_COMPONENT_component.wifi_bt_module.wifi_fw) + mcux_add_macro( + "-DCONFIG_WIFI_IND_DNLD=1\ + -DCONFIG_WIFI_IND_RESET=1" + ) +endif() + +if (CONFIG_MCUX_COMPONENT_component.wifi_bt_module.nb_fw) + mcux_add_macro( + "-DCONFIG_BT_IND_DNLD=1" + ) +endif() + +if (CONFIG_MCUX_COMPONENT_component.wifi_bt_module.wifi_nb_combo_fw) + mcux_add_macro( + "-DCONFIG_WIFI_IND_DNLD=0\ + -DCONFIG_WIFI_IND_RESET=0" ) endif() @@ -184,6 +204,12 @@ if (CONFIG_MCUX_COMPONENT_component.wifi_bt_module.board_murata_2ll_m2) ) endif() +if (CONFIG_MCUX_COMPONENT_component.wifi_bt_module.board_murata_2ll_usd) + mcux_add_macro( + "-DWIFI_IW610_BOARD_MURATA_2LL_USD" + ) +endif() + if (CONFIG_MCUX_COMPONENT_component.wifi_bt_module.K32W061_transceiver) mcux_add_macro( "-DK32W061_TRANSCEIVER" diff --git a/mcux/mcux-sdk-ng/components/wifi_bt_module/incl/wifi_bt_module_config.h b/mcux/mcux-sdk-ng/components/wifi_bt_module/incl/wifi_bt_module_config.h index b59457dc0..72e957df8 100644 --- a/mcux/mcux-sdk-ng/components/wifi_bt_module/incl/wifi_bt_module_config.h +++ b/mcux/mcux-sdk-ng/components/wifi_bt_module/incl/wifi_bt_module_config.h @@ -343,6 +343,17 @@ .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ } +/* 2LL NightHawk module with uSD adapter */ +#elif defined(WIFI_IW610_BOARD_MURATA_2LL_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_NH.h" +#define IW610 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ + } #else #error "Please define macro related to wifi board" #endif From 51b940a7d31c0dd990bcb3b9ae3d2eb6c3cec63b Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 15:01:20 +0800 Subject: [PATCH 11/21] hal_nxp: mcux-sdk-ng: update usb to sdk 25.09.00-pvw2 Signed-off-by: Zhaoxiang Jin --- .../middleware/usb/host/class/usb_host_msd.c | 5 +- .../middleware/usb/host/usb_host_devices.c | 3 +- .../middleware/usb/host/usb_host_ehci.c | 7 +- .../usb/pd/ptn5110/usb_pd_ptn5110_msg.c | 5 +- .../middleware/usb/utility/usb_eth_adapter.h | 7 +- .../usb/utility/usb_eth_enet_adapter.c | 97 ++++++++++++++----- .../usb/utility/usb_eth_mcx_enet_adapter.c | 94 +++++++++++++----- 7 files changed, 164 insertions(+), 54 deletions(-) diff --git a/mcux/mcux-sdk-ng/middleware/usb/host/class/usb_host_msd.c b/mcux/mcux-sdk-ng/middleware/usb/host/class/usb_host_msd.c index 867cdc69d..61bc367ff 100644 --- a/mcux/mcux-sdk-ng/middleware/usb/host/class/usb_host_msd.c +++ b/mcux/mcux-sdk-ng/middleware/usb/host/class/usb_host_msd.c @@ -917,7 +917,10 @@ usb_status_t USB_HostMsdInit(usb_device_handle deviceHandle, usb_host_class_hand msdInstance->msdCommand.cbwBlock = (usb_host_cbw_t *)OSA_MemoryAllocate(sizeof(usb_host_cbw_t)); msdInstance->msdCommand.cswBlock = (usb_host_csw_t *)OSA_MemoryAllocate(sizeof(usb_host_csw_t)); #endif - + if (NULL == msdInstance->msdCommand.cbwBlock) + { + return kStatus_USB_AllocFail; + } /* initialize msd instance */ msdInstance->deviceHandle = deviceHandle; msdInstance->interfaceHandle = NULL; diff --git a/mcux/mcux-sdk-ng/middleware/usb/host/usb_host_devices.c b/mcux/mcux-sdk-ng/middleware/usb/host/usb_host_devices.c index b74ac3122..fa0fdcc6b 100644 --- a/mcux/mcux-sdk-ng/middleware/usb/host/usb_host_devices.c +++ b/mcux/mcux-sdk-ng/middleware/usb/host/usb_host_devices.c @@ -597,13 +597,12 @@ static usb_status_t USB_HostNotifyDevice(usb_host_handle hostHandle, { if (hostInstance->deviceCallback != NULL) { - (void)hostInstance->deviceCallback(NULL, NULL, eventCode); return kStatus_USB_InvalidHandle; } else { return status1; - } + } } #if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) diff --git a/mcux/mcux-sdk-ng/middleware/usb/host/usb_host_ehci.c b/mcux/mcux-sdk-ng/middleware/usb/host/usb_host_ehci.c index d1231d58f..f67a390b9 100644 --- a/mcux/mcux-sdk-ng/middleware/usb/host/usb_host_ehci.c +++ b/mcux/mcux-sdk-ng/middleware/usb/host/usb_host_ehci.c @@ -1,4 +1,4 @@ -/* + /* * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016,2019 - 2020 NXP * All rights reserved. @@ -3932,7 +3932,10 @@ static void USB_HostEhciTransferCallback(usb_host_transfer_t *transfer, usb_stat DCACHE_InvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferSofar); } #endif - transfer->callbackFn(transfer->callbackParam, transfer, status); + if ((transfer->callbackFn != NULL) && (transfer->callbackParam != NULL)) + { + transfer->callbackFn(transfer->callbackParam, transfer, status); + } } void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance) diff --git a/mcux/mcux-sdk-ng/middleware/usb/pd/ptn5110/usb_pd_ptn5110_msg.c b/mcux/mcux-sdk-ng/middleware/usb/pd/ptn5110/usb_pd_ptn5110_msg.c index 9e4d82f8e..2c3f4107a 100644 --- a/mcux/mcux-sdk-ng/middleware/usb/pd/ptn5110/usb_pd_ptn5110_msg.c +++ b/mcux/mcux-sdk-ng/middleware/usb/pd/ptn5110/usb_pd_ptn5110_msg.c @@ -409,7 +409,10 @@ static void PDPTN5110_MsgHalRcvdExtMsgUnChunked(pd_instance_t *pdInstance, uint8 /* Returned data format is {readable_byte_count, frame type, data0, data1 ... dataN} */ /* Need to store data0 at dst[0], so read buffer from */ (void)Reg_BusReadBlock(pdInstance, receive_byte_count, (uint32_t)rx_buf_count + 1U, dst); - total_bytes_received += (uint16_t)rx_buf_count - 1U; + if (rx_buf_count >= 1U) + { + total_bytes_received += (uint16_t)rx_buf_count - 1U; + } if ((Reg_CacheRead(pdInstance, INTERRUPT, alert) & TCPC_ALERT_BEGINNING_SOP_MESSAGE_STATUS_MASK) != 0U) { diff --git a/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_adapter.h b/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_adapter.h index 59fb8848c..e5b4882f7 100644 --- a/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_adapter.h +++ b/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_adapter.h @@ -17,6 +17,9 @@ /* 54-27-8D is assigned by IEEE, and 45-54-48 is ANSCII code of string 'ETH'. */ #define ETH_ADAPTER_MAC_ADDRESS {0x54, 0x27, 0x8d, 0x45, 0x54, 0x48} +#define ETH_ADAPTER_PHY_STABILITY_DELAY_US (500000U) +#define ETH_ADAPTER_PHY_AUTONEGOTIATION_COUNT (10U) + #define ETH_ADAPTER_PHY_FRAME_TX_BUFFER_LENGTH (10U) #define ETH_ADAPTER_PHY_RRAME_RX_BUFFER_LENGTH (10U) @@ -31,7 +34,7 @@ #endif #define ETH_ADAPTER_ENTER_CRITICAL() \ - OSA_SR_ALLOC(); \ + OSA_SR_ALLOC(); \ OSA_ENTER_CRITICAL() #define ETH_ADAPTER_EXIT_CRITICAL() OSA_EXIT_CRITICAL() @@ -292,6 +295,8 @@ static inline eth_adapter_err_t ETH_ADAPTER_FrameQueueClear(eth_adapter_frame_qu eth_adapter_err_t ETH_ADAPTER_Init(void); +eth_adapter_err_t ETH_ADAPTER_Reset(void); + eth_adapter_err_t ETH_ADAPTER_GetMacAddress(uint8_t *address); eth_adapter_err_t ETH_ADAPTER_GetLinkStatus(bool *status); diff --git a/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_enet_adapter.c b/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_enet_adapter.c index 9a6b30644..8a66afd05 100644 --- a/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_enet_adapter.c +++ b/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_enet_adapter.c @@ -72,10 +72,34 @@ eth_adapter_handle_t ethAdapterHandle; /******************************************************************************* * Code ******************************************************************************/ -static eth_adapter_err_t ETH_ADAPTER_HW_Init(void) +static eth_adapter_err_t ETH_ADAPTER_PHY_Init(void) +{ + phy_config_t phyConfig = { + .phyAddr = BOARD_PhyAddress, + .autoNeg = true, + .ops = BOARD_PhyOps, + .resource = BOARD_PhySource, + }; + + /* Initialize PHY and wait auto-negotiation over. */ + while (PHY_Init(&phyHandle, &phyConfig) != kStatus_Success) + { + (void)usb_echo("PHY_Init failed.\r\n"); + + return ETH_ADAPTER_ERROR; + } + + /* Wait a moment for PHY status to be stable. */ + SDK_DelayAtLeastUs(ETH_ADAPTER_PHY_STABILITY_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + return ETH_ADAPTER_OK; +} + +static eth_adapter_err_t ETH_ADAPTER_MAC_Init(void) { enet_config_t config; - phy_config_t phyConfig = {0}; + bool link = false; + bool autonego = false; /* Prepare the buffer configuration. */ enet_buffer_config_t buffConfig[] = {{ @@ -101,39 +125,37 @@ static eth_adapter_err_t ETH_ADAPTER_HW_Init(void) */ ENET_GetDefaultConfig(&config); + for (uint32_t cnt = 0; cnt < ETH_ADAPTER_PHY_AUTONEGOTIATION_COUNT && !autonego; cnt++) + { + (void)PHY_GetLinkStatus(&phyHandle, &link); + if (link) + { + (void)PHY_GetAutoNegotiationStatus(&phyHandle, &autonego); + } + } + + if (autonego) + { + /* Get the actual PHY link speed and set in MAC. */ + if (PHY_GetLinkSpeedDuplex(&phyHandle, (phy_speed_t *)(&config.miiSpeed), (phy_duplex_t *)(&config.miiDuplex)) != kStatus_Success) + { + (void)usb_echo("PHY_GetLinkSpeedDuplex failed.\r\n"); + + return ETH_ADAPTER_ERROR; + } + } + /* The miiMode should be set according to the different PHY interfaces. */ #ifdef EXAMPLE_PHY_INTERFACE_RGMII config.miiMode = kENET_RgmiiMode; - config.miiSpeed = kENET_MiiSpeed1000M; #else config.miiMode = kENET_RmiiMode; - config.miiSpeed = kENET_MiiSpeed100M; #endif - config.miiDuplex = kENET_MiiFullDuplex; /* Mount callback to ENET for getting interrupt event. */ config.interrupt = ENET_TX_INTERRUPT | ENET_RX_INTERRUPT | ENET_ERR_INTERRUPT; config.callback = ETH_Callback; - phyConfig.phyAddr = BOARD_PhyAddress; - phyConfig.autoNeg = true; - phyConfig.ops = BOARD_PhyOps; - phyConfig.resource = BOARD_PhySource; - - /* Initialize PHY and wait auto-negotiation over. */ - while (PHY_Init(&phyHandle, &phyConfig) != kStatus_Success) - { - (void)usb_echo("PHY_Init failed.\r\n"); - - return ETH_ADAPTER_ERROR; - } - - /* set PHY link speed/duplex. */ - PHY_SetLinkSpeedDuplex(&phyHandle, (phy_speed_t)config.miiSpeed, (phy_duplex_t)config.miiDuplex); - - /* Wait a moment for PHY status to be stable. */ - SDK_DelayAtLeastUs(100000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - #ifdef USB_STACK_FREERTOS ENET_Type *const enetBases[] = ENET_BASE_PTRS; const IRQn_Type enetTxIrqId[] = ENET_Transmit_IRQS; @@ -186,7 +208,32 @@ eth_adapter_err_t ETH_ADAPTER_Init(void) ethAdapterHandle.multicastFramePass = true; ethAdapterHandle.boardcastFramePass = true; - return ETH_ADAPTER_HW_Init(); + if (ETH_ADAPTER_PHY_Init() != ETH_ADAPTER_OK) + { + return ETH_ADAPTER_ERROR; + } + + if (ETH_ADAPTER_MAC_Init() != ETH_ADAPTER_OK) + { + return ETH_ADAPTER_ERROR; + } + + return ETH_ADAPTER_OK; +} + +eth_adapter_err_t ETH_ADAPTER_Reset(void) +{ + if (ETH_ADAPTER_FrameQueueClear(ðAdapterHandle.txFrameQueue) != ETH_ADAPTER_OK) + { + return ETH_ADAPTER_ERROR; + } + + if (ETH_ADAPTER_FrameQueueClear(ðAdapterHandle.rxFrameQueue) != ETH_ADAPTER_OK) + { + return ETH_ADAPTER_ERROR; + } + + return ETH_ADAPTER_MAC_Init(); } eth_adapter_err_t ETH_ADAPTER_GetMacAddress(uint8_t *address) diff --git a/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_mcx_enet_adapter.c b/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_mcx_enet_adapter.c index 0cc29b69a..a22f62fcf 100644 --- a/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_mcx_enet_adapter.c +++ b/mcux/mcux-sdk-ng/middleware/usb/utility/usb_eth_mcx_enet_adapter.c @@ -68,10 +68,34 @@ eth_adapter_handle_t ethAdapterHandle; /******************************************************************************* * Code ******************************************************************************/ -static eth_adapter_err_t ETH_ADAPTER_HW_Init(void) +static eth_adapter_err_t ETH_ADAPTER_PHY_Init(void) +{ + phy_config_t phyConfig = { + .phyAddr = BOARD_PhyAddress, + .autoNeg = true, + .ops = BOARD_PhyOps, + .resource = BOARD_PhySource, + }; + + /* Initialize PHY and wait auto-negotiation over. */ + while (PHY_Init(&phyHandle, &phyConfig) != kStatus_Success) + { + (void)usb_echo("PHY_Init failed.\r\n"); + + return ETH_ADAPTER_ERROR; + } + + /* Wait a moment for PHY status to be stable. */ + SDK_DelayAtLeastUs(ETH_ADAPTER_PHY_STABILITY_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + return ETH_ADAPTER_OK; +} + +static eth_adapter_err_t ETH_ADAPTER_MAC_Init(void) { enet_config_t config; - phy_config_t phyConfig = {0}; + bool link = false; + bool autonego = false; uint32_t rxbuffer[ENET_RXBD_NUM]; for (uint8_t index = 0U; index < ENET_RXBD_NUM; index++) @@ -101,38 +125,39 @@ static eth_adapter_err_t ETH_ADAPTER_HW_Init(void) */ ENET_GetDefaultConfig(&config); + for (uint32_t cnt = 0; cnt < ETH_ADAPTER_PHY_AUTONEGOTIATION_COUNT && !autonego; cnt++) + { + (void)PHY_GetLinkStatus(&phyHandle, &link); + if (link) + { + (void)PHY_GetAutoNegotiationStatus(&phyHandle, &autonego); + } + } + + if (autonego) + { + /* Get the actual PHY link speed and set in MAC. */ + if (PHY_GetLinkSpeedDuplex(&phyHandle, (phy_speed_t *)(&config.miiSpeed), (phy_duplex_t *)(&config.miiDuplex)) != kStatus_Success) + { + (void)usb_echo("PHY_GetLinkSpeedDuplex failed.\r\n"); + + return ETH_ADAPTER_ERROR; + } + } + /* The miiMode should be set according to the different PHY interfaces. */ #ifdef EXAMPLE_PHY_INTERFACE_RGMII config.miiMode = kENET_RgmiiMode; - config.miiSpeed = kENET_MiiSpeed1000M; #else config.miiMode = kENET_RmiiMode; - config.miiSpeed = kENET_MiiSpeed100M; #endif - config.miiDuplex = kENET_MiiFullDuplex; /* Mount callback to ENET for getting interrupt event. */ config.interrupt = kENET_DmaTx | kENET_DmaRx | kENET_DmaBusErr; - phyConfig.phyAddr = BOARD_PhyAddress; - phyConfig.autoNeg = true; - phyConfig.ops = BOARD_PhyOps; - phyConfig.resource = BOARD_PhySource; - - /* Initialize PHY and wait auto-negotiation over. */ - while (PHY_Init(&phyHandle, &phyConfig) != kStatus_Success) - { - (void)usb_echo("PHY_Init failed.\r\n"); - - return ETH_ADAPTER_ERROR; - } - /* set PHY link speed/duplex. */ PHY_SetLinkSpeedDuplex(&phyHandle, (phy_speed_t)config.miiSpeed, (phy_duplex_t)config.miiDuplex); - /* Wait a moment for PHY status to be stable. */ - SDK_DelayAtLeastUs(100000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - #ifdef USB_STACK_FREERTOS ENET_Type *const enetBases[] = ENET_BASE_PTRS; const IRQn_Type enetIrqId[] = ENET_IRQS; @@ -188,7 +213,32 @@ eth_adapter_err_t ETH_ADAPTER_Init(void) ethAdapterHandle.multicastFramePass = true; ethAdapterHandle.boardcastFramePass = true; - return ETH_ADAPTER_HW_Init(); + if (ETH_ADAPTER_PHY_Init() != ETH_ADAPTER_OK) + { + return ETH_ADAPTER_ERROR; + } + + if (ETH_ADAPTER_MAC_Init() != ETH_ADAPTER_OK) + { + return ETH_ADAPTER_ERROR; + } + + return ETH_ADAPTER_OK; +} + +eth_adapter_err_t ETH_ADAPTER_Reset(void) +{ + if (ETH_ADAPTER_FrameQueueClear(ðAdapterHandle.txFrameQueue) != ETH_ADAPTER_OK) + { + return ETH_ADAPTER_ERROR; + } + + if (ETH_ADAPTER_FrameQueueClear(ðAdapterHandle.rxFrameQueue) != ETH_ADAPTER_OK) + { + return ETH_ADAPTER_ERROR; + } + + return ETH_ADAPTER_MAC_Init(); } eth_adapter_err_t ETH_ADAPTER_GetMacAddress(uint8_t *address) From 242640b89cd45e8c944014607f9ed2927da2332b Mon Sep 17 00:00:00 2001 From: Simon Egger Date: Mon, 8 Sep 2025 18:00:39 +0200 Subject: [PATCH 12/21] hal_nxp: Expose Timestamp of 1588_EVENT_IN ENET provides 1588_EVENT_IN signals to latch the current timer value in TCCRn when a rising edge is detected. This commit exposes the latched timer value via ENET_Ptp1588GetCapture. Signed-off-by: Simon Egger --- mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h b/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h index fc3506d64..aba579685 100644 --- a/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h +++ b/mcux/mcux-sdk-ng/drivers/enet/fsl_enet.h @@ -1953,6 +1953,17 @@ void ENET_Ptp1588GetTimerNoIrqDisable(ENET_Type *base, enet_handle_t *handle, en */ void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); +/*! + * @brief Gets the last captured ENET time from the PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + */ +static inline uint32_t ENET_Ptp1588GetChannelCaptureValue(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + return base->CHANNEL[channel].TCCR; +} + /*! * @brief Sets the ENET PTP 1588 timer to the assigned time. * From bc25a673e265297ed7f3c0c664bb7d609939e020 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 27 Aug 2025 17:37:19 +0800 Subject: [PATCH 13/21] mcux-sdk-ng: drivers: netc: get right size of TX timestamp response frame Got right size of TX timestamp response frame. Signed-off-by: Yangbo Lu --- mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c index 74b029c5b..8dcf294c1 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c @@ -1146,6 +1146,7 @@ status_t EP_GetRxFrameSizeCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, u else { /* Get Transmit Timestamp Reference Response messages */ + *length = rxDesc->writeback.bufLen; result = kStatus_NETC_RxTsrResp; } } From 4054430ed51c1796c33187db1f87970f36cfc278 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 27 Aug 2025 17:35:12 +0800 Subject: [PATCH 14/21] mcux-sdk-ng: drivers: netc: support rrt member in netc_tb_ipf_cfge_t Supported rrt member in netc_tb_ipf_cfge_t. This is to enable Report Receive Timestamp in switch tag. Signed-off-by: Yangbo Lu --- mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h index 0166df6fe..8e9b3ed72 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h @@ -1376,7 +1376,12 @@ typedef struct _netc_tb_ipf_cfge netc_host_reason_t hr : 4; /*!< Host Reason metadata when frame is redirected/copied to the switch management port */ uint32_t timecape : 1; /*!< Timestam capture enable */ +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG + uint32_t rrt : 1; /*!< Report Receive Timestamp */ + uint32_t : 8; +#else uint32_t : 9; +#endif uint32_t fltaTgt; /*!< Target for selected switch forwarding action or filter action*/ } netc_tb_ipf_cfge_t; From 6eb3a503b4fbc792686ffe8848885267b686b9ab Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Fri, 11 Jul 2025 17:36:41 +0800 Subject: [PATCH 15/21] devices: imx943: ca55: add definition of cpu frequency Defined SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY which is used for delay function in hal driver. Signed-off-by: Jiafei Pan --- .../devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_COMMON.h | 1 + 1 file changed, 1 insertion(+) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_COMMON.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_COMMON.h index 988401fe0..a9804f968 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_COMMON.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_COMMON.h @@ -4116,6 +4116,7 @@ typedef enum } \ } #include "fsl_elec_spec.h" +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (1700000000UL) /* XSPI - Peripheral instance base addresses */ From 16cf63e7e35a08eef90dc44f9bca91d5a7133656 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Fri, 11 Jul 2025 16:59:09 +0800 Subject: [PATCH 16/21] devices: imx943: ca55: fix memory feature Cortex-A Core should set FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET to be 0. Signed-off-by: Jiafei Pan --- .../devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_features.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_features.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_features.h index 72ef67d26..217477baa 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_features.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/MIMX94398/MIMX94398_ca55_features.h @@ -605,7 +605,7 @@ /* MEMORY module features */ /* @brief Memory map has offset between subsystems. */ -#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1) +#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (0) /* MU module features */ From cb220b360ece4958d0d3f913bcfd3e05a4383a0b Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 5 Sep 2025 09:02:15 -0400 Subject: [PATCH 17/21] hal_nxp: undefine PAGESIZE macro before naming fields Several fields in various HAL structures are named `PAGESIZE` which conflicts with the POSIX standard. Since POSIX has been around for a few decades, is standardized, etc, and since the HAL definitions seem to have operated correctly without POSIX conformance, undefine the standard `PAGESIZE` macro in order to prevent compile errors. Fixes #95285 Signed-off-by: Chris Friedt --- mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_USB.h | 1 + mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DWC_USB3.h | 1 + mcux/mcux-sdk-ng/devices/i.MX/i.MX95/periph/PERI_USB3_CORE.h | 1 + 3 files changed, 3 insertions(+) diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_USB.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_USB.h index 5499a4bfb..2639ca0f0 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_USB.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX8MP/periph/PERI_USB.h @@ -168,6 +168,7 @@ typedef struct { __I uint32_t HCCPARAMS2; /**< Host Controller Capability Parameters 2, offset: 0x1C */ __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x20 */ __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x24 */ +#undef PAGESIZE __I uint32_t PAGESIZE; /**< Page Size Register, offset: 0x28 */ uint8_t RESERVED_0[8]; __IO uint32_t DNCTRL; /**< Device Notification Register, offset: 0x34 */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DWC_USB3.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DWC_USB3.h index f920cb283..f3182809a 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DWC_USB3.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX943/periph/PERI_DWC_USB3.h @@ -247,6 +247,7 @@ typedef struct { __I uint32_t HCCPARAMS2; /**< Host Controller Capability Parameters 2, offset: 0x1C */ __IO uint32_t USBCMD; /**< USB Command, offset: 0x20 */ __IO uint32_t USBSTS; /**< USB Status, offset: 0x24 */ +#undef PAGESIZE __I uint32_t PAGESIZE; /**< Page Size, offset: 0x28 */ uint8_t RESERVED_0[8]; __IO uint32_t DNCTRL; /**< Device Notification, offset: 0x34 */ diff --git a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/periph/PERI_USB3_CORE.h b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/periph/PERI_USB3_CORE.h index febd0f4a0..51033e962 100644 --- a/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/periph/PERI_USB3_CORE.h +++ b/mcux/mcux-sdk-ng/devices/i.MX/i.MX95/periph/PERI_USB3_CORE.h @@ -421,6 +421,7 @@ typedef struct { __I uint32_t HCCPARAMS2; /**< Host Controller Capability Parameters 2, offset: 0x1C */ __IO uint32_t USBCMD; /**< USB Command, offset: 0x20 */ __IO uint32_t USBSTS; /**< USB Status, offset: 0x24 */ +#undef PAGESIZE __I uint32_t PAGESIZE; /**< Page Size, offset: 0x28 */ uint8_t RESERVED_0[8]; __IO uint32_t DNCTRL; /**< Device Notification, offset: 0x34 */ From 8beec0a5b1914422b200edf9c11c5933373b2cfe Mon Sep 17 00:00:00 2001 From: Neil Chen Date: Thu, 9 Oct 2025 10:32:36 +0800 Subject: [PATCH 18/21] dts: add pinctrl dtsi for MCXA344 Generate MCXA344 pinctrl dtsi. Signed-off-by: Neil Chen --- dts/nxp/mcx/MCXA344VFM-pinctrl.h | 242 +++++++++++++ dts/nxp/mcx/MCXA344VLF-pinctrl.h | 333 +++++++++++++++++ dts/nxp/mcx/MCXA344VLH-pinctrl.h | 441 +++++++++++++++++++++++ dts/nxp/mcx/MCXA344VLL-pinctrl.h | 596 +++++++++++++++++++++++++++++++ 4 files changed, 1612 insertions(+) create mode 100644 dts/nxp/mcx/MCXA344VFM-pinctrl.h create mode 100644 dts/nxp/mcx/MCXA344VLF-pinctrl.h create mode 100644 dts/nxp/mcx/MCXA344VLH-pinctrl.h create mode 100644 dts/nxp/mcx/MCXA344VLL-pinctrl.h diff --git a/dts/nxp/mcx/MCXA344VFM-pinctrl.h b/dts/nxp/mcx/MCXA344VFM-pinctrl.h new file mode 100644 index 000000000..1c9db15cb --- /dev/null +++ b/dts/nxp/mcx/MCXA344VFM-pinctrl.h @@ -0,0 +1,242 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA344VFM/signal_configuration.xml + * + * + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA344VFM_ +#define _ZEPHYR_DTS_BINDING_MCXA344VFM_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define CMP2_IN3_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define SMARTDMA_PIO4_P1_8 A15X_MUX('1',8,7) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define SMARTDMA_PIO5_P1_9 A15X_MUX('1',9,7) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP2_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP1_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define SMARTDMA_PIO26_P2_2 A15X_MUX('2',2,7) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A3_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define SMARTDMA_PIO27_P2_3 A15X_MUX('2',3,7) /* PT2_3 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define SMARTDMA_PIO31_P2_7 A15X_MUX('2',7,7) /* PT2_7 */ +#define OPAMP0_INP_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define SMARTDMA_PIO16_P2_12 A15X_MUX('2',12,7) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define SMARTDMA_PIO17_P2_13 A15X_MUX('2',13,7) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define WUU0_IN21_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define CMP0_INP4_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define SMARTDMA_PIO18_P2_15 A15X_MUX('2',15,7) /* PT2_15 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define SMARTDMA_PIO20_P2_17 A15X_MUX('2',17,7) /* PT2_17 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define SMARTDMA_PIO0_P3_0 A15X_MUX('3',0,10) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define SMARTDMA_PIO1_P3_1 A15X_MUX('3',1,10) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define SMARTDMA_PIO8_P3_8 A15X_MUX('3',8,10) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define SMARTDMA_PIO9_P3_9 A15X_MUX('3',9,10) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define SMARTDMA_PIO10_P3_10 A15X_MUX('3',10,10) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define SMARTDMA_PIO11_P3_11 A15X_MUX('3',11,10) /* PT3_11 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C1_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define PWM1_A3_P3_27 A15X_MUX('3',27,7) /* PT3_27 */ +#define SMARTDMA_PIO27_P3_27 A15X_MUX('3',27,10) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C1_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define PWM1_B3_P3_28 A15X_MUX('3',28,7) /* PT3_28 */ +#define SMARTDMA_PIO28_P3_28 A15X_MUX('3',28,10) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C1_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define SMARTDMA_PIO29_P3_29 A15X_MUX('3',29,10) /* PT3_29 */ +#endif diff --git a/dts/nxp/mcx/MCXA344VLF-pinctrl.h b/dts/nxp/mcx/MCXA344VLF-pinctrl.h new file mode 100644 index 000000000..441b63e8a --- /dev/null +++ b/dts/nxp/mcx/MCXA344VLF-pinctrl.h @@ -0,0 +1,333 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA344VLF/signal_configuration.xml + * + * + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA344VLF_ +#define _ZEPHYR_DTS_BINDING_MCXA344VLF_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define SMARTDMA_PIO2_P0_6 A15X_MUX('0',6,7) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define SMARTDMA_PIO6_P0_16 A15X_MUX('0',16,7) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define SMARTDMA_PIO7_P0_17 A15X_MUX('0',17,7) /* PT0_17 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define CMP2_IN3_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define SMARTDMA_PIO4_P1_8 A15X_MUX('1',8,7) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define SMARTDMA_PIO5_P1_9 A15X_MUX('1',9,7) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define OPAMP2_INP_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define SMARTDMA_PIO24_P2_0 A15X_MUX('2',0,7) /* PT2_0 */ +#define OPAMP2_INN_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC1_A0_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define SMARTDMA_PIO25_P2_1 A15X_MUX('2',1,7) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP2_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP1_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define SMARTDMA_PIO26_P2_2 A15X_MUX('2',2,7) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A3_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define SMARTDMA_PIO27_P2_3 A15X_MUX('2',3,7) /* PT2_3 */ +#define CMP2_INP4_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define OPAMP2_OUT_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define SMARTDMA_PIO30_P2_6 A15X_MUX('2',6,7) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define SMARTDMA_PIO31_P2_7 A15X_MUX('2',7,7) /* PT2_7 */ +#define OPAMP0_INP_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define SMARTDMA_PIO16_P2_12 A15X_MUX('2',12,7) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define SMARTDMA_PIO17_P2_13 A15X_MUX('2',13,7) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define WUU0_IN21_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define CMP0_INP4_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define SMARTDMA_PIO18_P2_15 A15X_MUX('2',15,7) /* PT2_15 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define OPAMP1_INP_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define SMARTDMA_PIO19_P2_16 A15X_MUX('2',16,7) /* PT2_16 */ +#define OPAMP1_INN_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define SMARTDMA_PIO20_P2_17 A15X_MUX('2',17,7) /* PT2_17 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define OPAMP1_OUT_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define CMP1_INP4_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define SMARTDMA_PIO21_P2_19 A15X_MUX('2',19,7) /* PT2_19 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define SMARTDMA_PIO0_P3_0 A15X_MUX('3',0,10) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define SMARTDMA_PIO1_P3_1 A15X_MUX('3',1,10) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define SMARTDMA_PIO8_P3_8 A15X_MUX('3',8,10) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define SMARTDMA_PIO9_P3_9 A15X_MUX('3',9,10) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define SMARTDMA_PIO10_P3_10 A15X_MUX('3',10,10) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define SMARTDMA_PIO11_P3_11 A15X_MUX('3',11,10) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define SMARTDMA_PIO12_P3_12 A15X_MUX('3',12,10) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define SMARTDMA_PIO13_P3_13 A15X_MUX('3',13,10) /* PT3_13 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C1_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define PWM1_A3_P3_27 A15X_MUX('3',27,7) /* PT3_27 */ +#define SMARTDMA_PIO27_P3_27 A15X_MUX('3',27,10) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C1_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define PWM1_B3_P3_28 A15X_MUX('3',28,7) /* PT3_28 */ +#define SMARTDMA_PIO28_P3_28 A15X_MUX('3',28,10) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C1_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define SMARTDMA_PIO29_P3_29 A15X_MUX('3',29,10) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C1_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define PWM1_A0_P3_30 A15X_MUX('3',30,7) /* PT3_30 */ +#define SMARTDMA_PIO30_P3_30 A15X_MUX('3',30,10) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C1_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define PWM1_B0_P3_31 A15X_MUX('3',31,7) /* PT3_31 */ +#define SMARTDMA_PIO31_P3_31 A15X_MUX('3',31,10) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA344VLH-pinctrl.h b/dts/nxp/mcx/MCXA344VLH-pinctrl.h new file mode 100644 index 000000000..8ea94c63d --- /dev/null +++ b/dts/nxp/mcx/MCXA344VLH-pinctrl.h @@ -0,0 +1,441 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA344VLH/signal_configuration.xml + * + * + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA344VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA344VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define SMARTDMA_PIO2_P0_6 A15X_MUX('0',6,7) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define SMARTDMA_PIO6_P0_16 A15X_MUX('0',16,7) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define SMARTDMA_PIO7_P0_17 A15X_MUX('0',17,7) /* PT0_17 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define CMP2_IN3_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define SMARTDMA_PIO0_P1_4 A15X_MUX('1',4,7) /* PT1_4 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define SMARTDMA_PIO1_P1_5 A15X_MUX('1',5,7) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define SMARTDMA_PIO2_P1_6 A15X_MUX('1',6,7) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define SMARTDMA_PIO3_P1_7 A15X_MUX('1',7,7) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define SMARTDMA_PIO4_P1_8 A15X_MUX('1',8,7) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define SMARTDMA_PIO5_P1_9 A15X_MUX('1',9,7) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define SMARTDMA_PIO6_P1_10 A15X_MUX('1',10,7) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define SMARTDMA_PIO7_P1_11 A15X_MUX('1',11,7) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define SMARTDMA_PIO8_P1_12 A15X_MUX('1',12,7) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define SMARTDMA_PIO9_P1_13 A15X_MUX('1',13,7) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define OPAMP2_INP_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define SMARTDMA_PIO24_P2_0 A15X_MUX('2',0,7) /* PT2_0 */ +#define OPAMP2_INN_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC1_A0_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define SMARTDMA_PIO25_P2_1 A15X_MUX('2',1,7) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP2_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP1_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define SMARTDMA_PIO26_P2_2 A15X_MUX('2',2,7) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A3_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define SMARTDMA_PIO27_P2_3 A15X_MUX('2',3,7) /* PT2_3 */ +#define CMP2_IN0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC0_A1_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define SMARTDMA_PIO28_P2_4 A15X_MUX('2',4,7) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define SMARTDMA_PIO29_P2_5 A15X_MUX('2',5,7) /* PT2_5 */ +#define CMP2_INP4_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define OPAMP2_OUT_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define SMARTDMA_PIO30_P2_6 A15X_MUX('2',6,7) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define SMARTDMA_PIO31_P2_7 A15X_MUX('2',7,7) /* PT2_7 */ +#define OPAMP0_INP_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define SMARTDMA_PIO16_P2_12 A15X_MUX('2',12,7) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define SMARTDMA_PIO17_P2_13 A15X_MUX('2',13,7) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define WUU0_IN21_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define CMP0_INP4_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define SMARTDMA_PIO18_P2_15 A15X_MUX('2',15,7) /* PT2_15 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define OPAMP1_INP_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define SMARTDMA_PIO19_P2_16 A15X_MUX('2',16,7) /* PT2_16 */ +#define OPAMP1_INN_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define SMARTDMA_PIO20_P2_17 A15X_MUX('2',17,7) /* PT2_17 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define OPAMP1_OUT_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define CMP1_INP4_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define SMARTDMA_PIO21_P2_19 A15X_MUX('2',19,7) /* PT2_19 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define SMARTDMA_PIO0_P3_0 A15X_MUX('3',0,10) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define SMARTDMA_PIO1_P3_1 A15X_MUX('3',1,10) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define PWM0_A3_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define SMARTDMA_PIO6_P3_6 A15X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define PWM0_B3_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define SMARTDMA_PIO7_P3_7 A15X_MUX('3',7,10) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define SMARTDMA_PIO8_P3_8 A15X_MUX('3',8,10) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define SMARTDMA_PIO9_P3_9 A15X_MUX('3',9,10) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define SMARTDMA_PIO10_P3_10 A15X_MUX('3',10,10) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define SMARTDMA_PIO11_P3_11 A15X_MUX('3',11,10) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define SMARTDMA_PIO12_P3_12 A15X_MUX('3',12,10) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define SMARTDMA_PIO13_P3_13 A15X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define SMARTDMA_PIO14_P3_14 A15X_MUX('3',14,10) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define PWM0_X3_P3_15 A15X_MUX('3',15,5) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define SMARTDMA_PIO15_P3_15 A15X_MUX('3',15,10) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C1_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define PWM1_A3_P3_27 A15X_MUX('3',27,7) /* PT3_27 */ +#define SMARTDMA_PIO27_P3_27 A15X_MUX('3',27,10) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C1_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define PWM1_B3_P3_28 A15X_MUX('3',28,7) /* PT3_28 */ +#define SMARTDMA_PIO28_P3_28 A15X_MUX('3',28,10) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C1_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define SMARTDMA_PIO29_P3_29 A15X_MUX('3',29,10) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C1_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define PWM1_A0_P3_30 A15X_MUX('3',30,7) /* PT3_30 */ +#define SMARTDMA_PIO30_P3_30 A15X_MUX('3',30,10) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C1_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define PWM1_B0_P3_31 A15X_MUX('3',31,7) /* PT3_31 */ +#define SMARTDMA_PIO31_P3_31 A15X_MUX('3',31,10) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA344VLL-pinctrl.h b/dts/nxp/mcx/MCXA344VLL-pinctrl.h new file mode 100644 index 000000000..10f531193 --- /dev/null +++ b/dts/nxp/mcx/MCXA344VLL-pinctrl.h @@ -0,0 +1,596 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA344VLL/signal_configuration.xml + * + * + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA344VLL_ +#define _ZEPHYR_DTS_BINDING_MCXA344VLL_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define SMARTDMA_PIO2_P0_6 A15X_MUX('0',6,7) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_14 A15X_MUX('0',14,0) /* PT0_14 */ +#define CT_INP2_P0_14 A15X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_P0_14 A15X_MUX('0',14,5) /* PT0_14 */ +#define SMARTDMA_PIO4_P0_14 A15X_MUX('0',14,7) /* PT0_14 */ +#define P0_15 A15X_MUX('0',15,0) /* PT0_15 */ +#define CT_INP3_P0_15 A15X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_P0_15 A15X_MUX('0',15,5) /* PT0_15 */ +#define SMARTDMA_PIO5_P0_15 A15X_MUX('0',15,7) /* PT0_15 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define SMARTDMA_PIO6_P0_16 A15X_MUX('0',16,7) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define SMARTDMA_PIO7_P0_17 A15X_MUX('0',17,7) /* PT0_17 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define SMARTDMA_PIO8_P0_18 A15X_MUX('0',18,7) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define SMARTDMA_PIO9_P0_19 A15X_MUX('0',19,7) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define SMARTDMA_PIO10_P0_20 A15X_MUX('0',20,7) /* PT0_20 */ +#define CMP2_OUT_P0_20 A15X_MUX('0',20,8) /* PT0_20 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define SMARTDMA_PIO11_P0_21 A15X_MUX('0',21,7) /* PT0_21 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define SMARTDMA_PIO12_P0_22 A15X_MUX('0',22,7) /* PT0_22 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define CMP2_IN2_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define SMARTDMA_PIO13_P0_23 A15X_MUX('0',23,7) /* PT0_23 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define CMP2_IN3_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define SMARTDMA_PIO0_P1_4 A15X_MUX('1',4,7) /* PT1_4 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define SMARTDMA_PIO1_P1_5 A15X_MUX('1',5,7) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define SMARTDMA_PIO2_P1_6 A15X_MUX('1',6,7) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define SMARTDMA_PIO3_P1_7 A15X_MUX('1',7,7) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define SMARTDMA_PIO4_P1_8 A15X_MUX('1',8,7) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define SMARTDMA_PIO5_P1_9 A15X_MUX('1',9,7) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define SMARTDMA_PIO6_P1_10 A15X_MUX('1',10,7) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define SMARTDMA_PIO7_P1_11 A15X_MUX('1',11,7) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define SMARTDMA_PIO8_P1_12 A15X_MUX('1',12,7) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define SMARTDMA_PIO9_P1_13 A15X_MUX('1',13,7) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define SMARTDMA_PIO10_P1_14 A15X_MUX('1',14,7) /* PT1_14 */ +#define WUU0_IN13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define SMARTDMA_PIO11_P1_15 A15X_MUX('1',15,7) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define OPAMP2_INP_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define SMARTDMA_PIO24_P2_0 A15X_MUX('2',0,7) /* PT2_0 */ +#define OPAMP2_INN_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC1_A0_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define SMARTDMA_PIO25_P2_1 A15X_MUX('2',1,7) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP2_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP1_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define SMARTDMA_PIO26_P2_2 A15X_MUX('2',2,7) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A3_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define SMARTDMA_PIO27_P2_3 A15X_MUX('2',3,7) /* PT2_3 */ +#define CMP2_IN0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC0_A1_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define SMARTDMA_PIO28_P2_4 A15X_MUX('2',4,7) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define SMARTDMA_PIO29_P2_5 A15X_MUX('2',5,7) /* PT2_5 */ +#define CMP2_INP4_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define OPAMP2_OUT_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define SMARTDMA_PIO30_P2_6 A15X_MUX('2',6,7) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define SMARTDMA_PIO31_P2_7 A15X_MUX('2',7,7) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define SMARTDMA_PIO14_P2_10 A15X_MUX('2',10,7) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define SMARTDMA_PIO15_P2_11 A15X_MUX('2',11,7) /* PT2_11 */ +#define OPAMP0_INP_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define SMARTDMA_PIO16_P2_12 A15X_MUX('2',12,7) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define SMARTDMA_PIO17_P2_13 A15X_MUX('2',13,7) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define WUU0_IN21_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define CMP0_INP4_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define SMARTDMA_PIO18_P2_15 A15X_MUX('2',15,7) /* PT2_15 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define OPAMP1_INP_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define SMARTDMA_PIO19_P2_16 A15X_MUX('2',16,7) /* PT2_16 */ +#define OPAMP1_INN_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define SMARTDMA_PIO20_P2_17 A15X_MUX('2',17,7) /* PT2_17 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define OPAMP1_OUT_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define CMP1_INP4_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define SMARTDMA_PIO21_P2_19 A15X_MUX('2',19,7) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define SMARTDMA_PIO22_P2_20 A15X_MUX('2',20,7) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define SMARTDMA_PIO23_P2_21 A15X_MUX('2',21,7) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define P2_24 A15X_MUX('2',24,0) /* PT2_24 */ +#define TRIG_OUT6_P2_24 A15X_MUX('2',24,1) /* PT2_24 */ +#define CT_INP8_P2_24 A15X_MUX('2',24,4) /* PT2_24 */ +#define P2_25 A15X_MUX('2',25,0) /* PT2_25 */ +#define TRIG_OUT7_P2_25 A15X_MUX('2',25,1) /* PT2_25 */ +#define CT_INP9_P2_25 A15X_MUX('2',25,4) /* PT2_25 */ +#define P2_26 A15X_MUX('2',26,0) /* PT2_26 */ +#define TRIG_IN5_P2_26 A15X_MUX('2',26,1) /* PT2_26 */ +#define CT_INP10_P2_26 A15X_MUX('2',26,4) /* PT2_26 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define SMARTDMA_PIO0_P3_0 A15X_MUX('3',0,10) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define SMARTDMA_PIO1_P3_1 A15X_MUX('3',1,10) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define PWM0_A3_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define SMARTDMA_PIO6_P3_6 A15X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define PWM0_B3_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define SMARTDMA_PIO7_P3_7 A15X_MUX('3',7,10) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define SMARTDMA_PIO8_P3_8 A15X_MUX('3',8,10) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define SMARTDMA_PIO9_P3_9 A15X_MUX('3',9,10) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define SMARTDMA_PIO10_P3_10 A15X_MUX('3',10,10) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define SMARTDMA_PIO11_P3_11 A15X_MUX('3',11,10) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define SMARTDMA_PIO12_P3_12 A15X_MUX('3',12,10) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define SMARTDMA_PIO13_P3_13 A15X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define SMARTDMA_PIO14_P3_14 A15X_MUX('3',14,10) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define PWM0_X3_P3_15 A15X_MUX('3',15,5) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define SMARTDMA_PIO15_P3_15 A15X_MUX('3',15,10) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define PWM1_A0_P3_16 A15X_MUX('3',16,7) /* PT3_16 */ +#define SMARTDMA_PIO16_P3_16 A15X_MUX('3',16,10) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define PWM1_B0_P3_17 A15X_MUX('3',17,7) /* PT3_17 */ +#define SMARTDMA_PIO17_P3_17 A15X_MUX('3',17,10) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define PWM1_X0_P3_18 A15X_MUX('3',18,7) /* PT3_18 */ +#define SMARTDMA_PIO18_P3_18 A15X_MUX('3',18,10) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define PWM1_X1_P3_19 A15X_MUX('3',19,7) /* PT3_19 */ +#define SMARTDMA_PIO19_P3_19 A15X_MUX('3',19,10) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define PWM1_A3_P3_20 A15X_MUX('3',20,7) /* PT3_20 */ +#define SMARTDMA_PIO20_P3_20 A15X_MUX('3',20,10) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define PWM0_X3_P3_21 A15X_MUX('3',21,5) /* PT3_21 */ +#define PWM1_B3_P3_21 A15X_MUX('3',21,7) /* PT3_21 */ +#define SMARTDMA_PIO21_P3_21 A15X_MUX('3',21,10) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define PWM1_X2_P3_22 A15X_MUX('3',22,7) /* PT3_22 */ +#define SMARTDMA_PIO22_P3_22 A15X_MUX('3',22,10) /* PT3_22 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C1_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define PWM1_A3_P3_27 A15X_MUX('3',27,7) /* PT3_27 */ +#define SMARTDMA_PIO27_P3_27 A15X_MUX('3',27,10) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C1_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define PWM1_B3_P3_28 A15X_MUX('3',28,7) /* PT3_28 */ +#define SMARTDMA_PIO28_P3_28 A15X_MUX('3',28,10) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C1_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define SMARTDMA_PIO29_P3_29 A15X_MUX('3',29,10) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C1_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define PWM1_A0_P3_30 A15X_MUX('3',30,7) /* PT3_30 */ +#define SMARTDMA_PIO30_P3_30 A15X_MUX('3',30,10) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C1_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define PWM1_B0_P3_31 A15X_MUX('3',31,7) /* PT3_31 */ +#define SMARTDMA_PIO31_P3_31 A15X_MUX('3',31,10) /* PT3_31 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define SMARTDMA_PIO22_P4_2 A15X_MUX('4',2,7) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define SMARTDMA_PIO23_P4_3 A15X_MUX('4',3,7) /* PT4_3 */ +#define WUU0_IN17_P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define SMARTDMA_PIO24_P4_4 A15X_MUX('4',4,7) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define SMARTDMA_PIO25_P4_5 A15X_MUX('4',5,7) /* PT4_5 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define SMARTDMA_PIO26_P4_6 A15X_MUX('4',6,7) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define SMARTDMA_PIO27_P4_7 A15X_MUX('4',7,7) /* PT4_7 */ +#endif From a0894a89ab24afea2645ce08f490e145bbab20a9 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 9 Oct 2025 11:29:10 +0800 Subject: [PATCH 19/21] mcux-sdk-ng: drivers: Fix flash_k4 driver bug The call to the function "flash_cache_invalidate();" should be conditional. This patch has been submitted to the MCUX SDK. Signed-off-by: Zhaoxiang Jin --- mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.c b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.c index 6de74b98d..5f9cd1efe 100644 --- a/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.c +++ b/mcux/mcux-sdk-ng/drivers/flash_k4/fsl_k4_flash.c @@ -216,11 +216,13 @@ status_t FLASH_Erase(flash_config_t *config, FMU_Type *base, uint32_t start, uin start += FLASH_FEATURE_SECTOR_SIZE; } } +#if defined(SMSCM) || defined (SYSCON_FMC0_CTRL_DFC_MASK) /* * Data cache may contain stale values following a flash programming or erasing operation. * Data cache invalidation is only on KW43. */ flash_cache_invalidate(); +#endif } else { @@ -251,11 +253,13 @@ status_t FLASH_EraseAll(FMU_Type *base, uint32_t key) if (kStatus_FLASH_Success == status) { status = FLASH_CMD_EraseAll(base); +#if defined(SMSCM) || defined (SYSCON_FMC0_CTRL_DFC_MASK) /* * Data cache may contain stale values following a flash programming or erasing operation. * Data cache invalidation is only on KW43. */ flash_cache_invalidate(); +#endif } else { @@ -337,11 +341,13 @@ status_t FLASH_Program(flash_config_t *config, FMU_Type *base, uint32_t start, u status = FLASH_CMD_ProgramPhrase(base, start, extraData); } +#if defined(SMSCM) || defined (SYSCON_FMC0_CTRL_DFC_MASK) /* * Data cache may contain stale values following a flash programming or erasing operation. * Data cache invalidation is only on KW43. */ flash_cache_invalidate(); +#endif } else { @@ -427,11 +433,13 @@ status_t FLASH_ProgramPage(flash_config_t *config, FMU_Type *base, uint32_t star status = FLASH_CMD_ProgramPage(base, start, extraData); } +#if defined(SMSCM) || defined (SYSCON_FMC0_CTRL_DFC_MASK) /* * Data cache may contain stale values following a flash programming or erasing operation. * Data cache invalidation is only on KW43. */ flash_cache_invalidate(); +#endif } else { From 20f34e95974117f767653c20de0eb17286ccfb5d Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Sat, 11 Oct 2025 09:58:21 +0800 Subject: [PATCH 20/21] hal: sdk-ng: Update edma4 driver to sdk latest Update edma4 driver to sdk latest. After this patch, https://github.com/zephyrproject-rtos/hal_nxp/pull/609 can be closed. Signed-off-by: Zhaoxiang Jin --- mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt | 2 +- mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c | 32 ++++++++++--------- mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h | 7 ++-- 3 files changed, 23 insertions(+), 18 deletions(-) diff --git a/mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt index 5db123f0e..3b951185b 100644 --- a/mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/edma4/CMakeLists.txt @@ -3,7 +3,7 @@ # SPDX-License-Identifier: BSD-3-Clause if(CONFIG_MCUX_COMPONENT_driver.edma4) - mcux_component_version(2.10.6) + mcux_component_version(2.10.7) mcux_add_source( SOURCES diff --git a/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c b/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c index 6e32fac22..9e4247446 100644 --- a/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c +++ b/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.c @@ -1463,8 +1463,11 @@ void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t ma * parameters. * param base eDMA peripheral base address. * param channel eDMA channel number. + * + * @retval #kStatus_Success + * @retval #kStatus_InvalidArgument */ -void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel) +status_t EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel) { assert(handle != NULL); assert(FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base) != -1); @@ -1480,6 +1483,10 @@ void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel) /* Get the DMA instance number */ edmaInstance = EDMA_GetInstance(base); + if (edmaInstance >= ARRAY_SIZE(s_edmaBases)) + { + return kStatus_InvalidArgument; + } s_EDMAHandle[edmaInstance][channel] = handle; handle->tcdBase = EDMA_TCD_BASE(base, channel); @@ -1507,6 +1514,8 @@ void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel) /* Enable NVIC interrupt */ (void)EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); + + return kStatus_Success; } /*! @@ -1536,7 +1545,7 @@ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t * During first submit, the header should be assigned to 1, since 0 is current one and 1 is next TCD to be loaded, * but software cannot know which submission is the first one, so assign 1 to header here. */ - handle->header = 1; + handle->header = 0; handle->tcdUsed = 0; handle->tcdSize = (int8_t)tcdSize; handle->tcdPool = tcdPool; @@ -2507,7 +2516,7 @@ void EDMA_AbortTransfer(edma_handle_t *handle) /* Handle the tcd */ if (handle->tcdPool != NULL) { - handle->header = 1; + handle->header = 0; handle->tail = 0; handle->tcdUsed = 0; } @@ -2585,17 +2594,9 @@ void EDMA_HandleIRQ(edma_handle_t *handle) sga -= CONVERT_TO_DMA_ADDRESS((uint32_t)handle->tcdPool); /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */ sga_index = sga / sizeof(edma_tcd_t); - /* Adjust header positions. */ - if (transfer_done) - { - /* New header shall point to the next TCD to be loaded (current one is already finished) */ - new_header = (uint8_t)sga_index; - } - else - { - /* New header shall point to this descriptor currently loaded (not finished yet) */ - new_header = sga_index != 0U ? (uint8_t)sga_index - 1U : (uint8_t)handle->tcdSize - 1U; - } + /* Adjust header positions, new_header should be the index of the current transfer TCD blocks. */ + new_header = sga_index != 0U ? (uint8_t)sga_index - 1U : (uint8_t)handle->tcdSize - 1U; + /* Calculate the number of finished TCDs */ if (new_header == (uint8_t)handle->header) { @@ -2606,8 +2607,9 @@ void EDMA_HandleIRQ(edma_handle_t *handle) * new_header(1) = handle->header(1) * tcdUsed(1) != tcdSize(>1) * As the application submit only once, so scatter gather must not enabled, then tcds_done should be 1 + * check transfer_done to handle the half interrupt or internal error occurs. */ - if ((tmpTcdUsed == tmpTcdSize) || (!esg)) + if (((tmpTcdUsed == tmpTcdSize) || (!esg)) && transfer_done) { tcds_done = handle->tcdUsed; } diff --git a/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h b/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h index c53710e5b..4f65f93b7 100644 --- a/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h +++ b/mcux/mcux-sdk-ng/drivers/edma4/fsl_edma.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*! @{ */ /*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 10, 6)) /*!< Version 2.10.6. */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 10, 7)) /*!< Version 2.10.7. */ /*! @} */ /*! @brief eDMA driver name */ @@ -1578,8 +1578,11 @@ void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t ma * parameters. * @param base eDMA peripheral base address. * @param channel eDMA channel number. + * + * @retval #kStatus_Success + * @retval #kStatus_InvalidArgument */ -void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel); +status_t EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel); /*! * @brief Installs the TCDs memory pool into the eDMA handle. From f5f731eb66309c02ec0fe51ae38c1b105c1f6b66 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Thu, 25 Sep 2025 16:09:44 +0800 Subject: [PATCH 21/21] hal_nxp: mcux: Update README Update README to: 1. Reflect the latest hal_nxp code source. 2. Add patch list which are not included in the MCUX SDK 25.09.00 release but required by Zephyr/hal_nxp. Signed-off-by: Zhaoxiang Jin --- mcux/README | 65 +++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 48 insertions(+), 17 deletions(-) diff --git a/mcux/README b/mcux/README index 14629bf83..8cf73d840 100644 --- a/mcux/README +++ b/mcux/README @@ -3,18 +3,13 @@ MCUXpresso SDK Origin: NXP MCUXpresso SDK - https://github.com/nxp-mcuxpresso/mcux-sdk - SHA: cc77cb1006ad2226fe45f0431e85add0fcd891d8 + https://github.com/nxp-mcuxpresso/mcuxsdk-manifests + SHA: 9039bbdc5b053d3155f1023caf65fb8305567041 NXP Kinetis Connectivity Software https://www.nxp.com/webapp/Download?colCode=KW40Z-CONNECTIVITY-SOFTWARE&appType=license&Parent_nodeId=1432854896956716810497&Parent_pageType=product https://www.nxp.com/webapp/Download?colCode=MKW2XD-MRC20A-CONNECTIVITY-SW&appType=license&Parent_nodeId=1425322332576706617013&Parent_pageType=productI - NXP MCUXpresso SDK USB - https://github.com/nxp-mcuxpresso/mcux-sdk-middleware-usb - SHA: e0f1fc8488508db2f92ae454f4378513d96e83e2 - SDK 2.16.000 merge - NXP MCUXpresso SDK Connectivity Framework https://github.com/nxp-mcuxpresso/mcux-sdk-middleware-connectivity-framework BRANCH: release/25.06.00 @@ -41,55 +36,55 @@ Origin: NXP MCUXpresso SDK Core https://github.com/nxp-mcuxpresso/mcuxsdk-core - SHA: 84547d55114471cd361e32559db1c4ecb3a32815 + SHA: e570f283a05a8cc291ac1165b405168250b9717a Source folder: cmake/extension Destination folder: mcux-sdk-ng/cmake/extension NXP MCUXpresso SDK Component https://github.com/nxp-mcuxpresso/mcux-component - SHA: 0a95c0536c168a97e1caac0bc41898c3cf9f75a8 + SHA: bcf7fef88d50f038ee6e500601ad0a2e18f83473 Source folder: Root folder of the NXP MCUXpresso SDK Component Repository Destination folder: mcux-sdk-ng/components NXP MCUXpresso SDK USB - https://github.com/nxp-mcuxpresso/mcuxsdk-middleware-usb - SHA: ff4c277499155029637526e0bf7ad7fa4c875e48 + https://github.com/nxp-mcuxpresso/mcuxsdk-middleware-usb/tree/release/25.09.00 + SHA: fae72b7af511b5097c8b8e2c16337215c0bab058 Source folder: Root folder of the NXP MCUXpresso SDK USB Repository Destination folder: mcux-sdk-ng/middleware/usb NXP MCUXpresso SDK Device i.MX https://github.com/nxp-mcuxpresso/mcux-devices-imx - SHA: bd9dec893950a163c5f9f4c53e5bc7a202b83819 + SHA: a999a1c98ec7fd058bd24416a7e4ff330235b09d Source folder: Root folder of the NXP MCUXpresso SDK Device i.MX Repository Destination folder: mcux-sdk-ng/devices/i.MX NXP MCUXpresso SDK Device RT https://github.com/nxp-mcuxpresso/mcux-devices-rt - SHA: 69599d3038bf20fdffb5b89dc3fcb34a2322f43a + SHA: 6b306e8feca475462e7fd4cd682440513f570bc4 Source folder: Root folder of the NXP MCUXpresso SDK Device RT Repository Destination folder: mcux-sdk-ng/devices/RT NXP MCUXpresso SDK Device Kinetis https://github.com/nxp-mcuxpresso/mcux-devices-kinetis - SHA: d3b2cbe46095f59a27d7f0d8b251bcfa7a8f5d6f + SHA: 978c1f97060c884d548c68ac06836750426033e8 Source folder: Root folder of the NXP MCUXpresso SDK Device Kinetis Repository Destination folder: mcux-sdk-ng/devices/Kinetis NXP MCUXpresso SDK Device LPC https://github.com/nxp-mcuxpresso/mcux-devices-lpc - SHA: 4671b7f19480417fefb23eb8c6e71a2bc9f2d9f1 + SHA: fe228b87e081a1938f6211b4c60926a333ed93fb Source folder: Root folder of the NXP MCUXpresso SDK Device LPC Repository Destination folder: mcux-sdk-ng/devices/LPC NXP MCUXpresso SDK Device MCX https://github.com/nxp-mcuxpresso/mcux-devices-mcx - SHA: 3ff51c8cf729c59918e96f4ce33b37c3e93ffc74 + SHA: 6bbddd36a6efe653c4633b064705dd9f30e32ac8 Source folder: Root folder of the NXP MCUXpresso SDK Device MCX Repository Destination folder: mcux-sdk-ng/devices/MCX NXP MCUXpresso SDK Device Wireless https://github.com/nxp-mcuxpresso/mcux-devices-wireless - SHA: 0dbc39ab4a247d7edc1b2b9aecdf3f0ea33369af + SHA: 5eb6a44dfbc2b36f5a3a058a3e06985e99829b76 Source folder: Root folder of the NXP MCUXpresso SDK Device Wireless Repository Destination folder: mcux-sdk-ng/devices/Wireless @@ -208,3 +203,39 @@ Patch List: - Update usb_host_ehci.c and usb_host_ip3516hs.c to not depend on usb_host_device_instance_t struct. - mcux-sdk: devices: fix MKV56F24.h wrong macro - The MKV56F24 device doesn't contain CAN2 peripheral. Remove it from the device header. + + - hal_nxp: undefine PAGESIZE macro before naming fields. + - Commit: https://github.com/zephyrproject-rtos/hal_nxp/pull/598/commits/c8b649a8af4d7235e67f67d5a6682df2c54c5c93 + - This patch is in hal_nxp but is not in mcux-sdk-ng 25.09.00. + + - devices: imx943: ca55: fix memory feature + - Commit: https://github.com/zephyrproject-rtos/hal_nxp/pull/578/commits/0145d78f5a68ac2ea1df5de165fb429ebf51c1da + - This patch is in hal_nxp but is not in mcux-sdk-ng 25.09.00. + + - devices: imx943: ca55: add definition of cpu frequency + - Commit: https://github.com/zephyrproject-rtos/hal_nxp/pull/578/commits/cf3d4d6721c1741c2d86d5dc564c1fe175e87969 + - This patch is in hal_nxp but is not in mcux-sdk-ng 25.09.00. + + - mcux-sdk-ng: drivers: netc: support rrt member in netc_tb_ipf_cfge_t + - Commit: https://github.com/zephyrproject-rtos/hal_nxp/pull/594/commits/49ccd7d3aafe178162de1f716888ebd3e5493239 + - This patch is in hal_nxp but is not in mcux-sdk-ng 25.09.00. + + - mcux-sdk-ng: drivers: netc: get right size of TX timestamp response frame + - Commit: https://github.com/zephyrproject-rtos/hal_nxp/pull/594/commits/3565235cb5968c9a70a0419b3330ab8d323159af + - This patch is in hal_nxp but is not in mcux-sdk-ng 25.09.00. + + - hal_nxp: Expose Timestamp of 1588_EVENT_IN + - Commit: https://github.com/zephyrproject-rtos/hal_nxp/pull/588/commits/fa0da84a8cb1b4f324a93624f7b7ca8fcb71994c + - This patch is in hal_nxp but is not in mcux-sdk-ng 25.09.00. + + - drivers: fsl_power.c: fix building warning + - Commit: https://github.com/zephyrproject-rtos/hal_nxp/pull/605/commits/584ebaab198efe281a4de3451f81132b0e373bad + - This patch is in hal_nxp but is not in mcux-sdk-ng 25.09.00. + This patch was merged after PR https://github.com/zephyrproject-rtos/hal_nxp/pull/612/commits was created, so it + did not enter PR#612 via cherry-pick but rather via rebasing onto the master branch. + + - Allow disable quickaccess section + - Commit: https://github.com/zephyrproject-rtos/hal_nxp/pull/605/commits/6b184471ec9eb0c32c07a2cc713baef170585f3e + - This patch is in hal_nxp but is not in mcux-sdk-ng 25.09.00. + This patch was merged after PR https://github.com/zephyrproject-rtos/hal_nxp/pull/612/commits was created, so it + did not enter PR#612 via cherry-pick but rather via rebasing onto the master branch.